if_sk.c revision 1.21.2.5
1 /* $NetBSD: if_sk.c,v 1.21.2.5 2006/09/14 12:31:33 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 #include "rnd.h" 126 127 #include <sys/param.h> 128 #include <sys/systm.h> 129 #include <sys/sockio.h> 130 #include <sys/mbuf.h> 131 #include <sys/malloc.h> 132 #include <sys/kernel.h> 133 #include <sys/socket.h> 134 #include <sys/device.h> 135 #include <sys/queue.h> 136 #include <sys/callout.h> 137 #include <sys/sysctl.h> 138 #include <sys/endian.h> 139 140 #include <net/if.h> 141 #include <net/if_dl.h> 142 #include <net/if_types.h> 143 144 #include <net/if_media.h> 145 146 #if NBPFILTER > 0 147 #include <net/bpf.h> 148 #endif 149 #if NRND > 0 150 #include <sys/rnd.h> 151 #endif 152 153 #include <dev/mii/mii.h> 154 #include <dev/mii/miivar.h> 155 #include <dev/mii/brgphyreg.h> 156 157 #include <dev/pci/pcireg.h> 158 #include <dev/pci/pcivar.h> 159 #include <dev/pci/pcidevs.h> 160 161 /* #define SK_USEIOSPACE */ 162 163 #include <dev/pci/if_skreg.h> 164 #include <dev/pci/if_skvar.h> 165 166 int skc_probe(struct device *, struct cfdata *, void *); 167 void skc_attach(struct device *, struct device *self, void *aux); 168 int sk_probe(struct device *, struct cfdata *, void *); 169 void sk_attach(struct device *, struct device *self, void *aux); 170 int skcprint(void *, const char *); 171 int sk_intr(void *); 172 void sk_intr_bcom(struct sk_if_softc *); 173 void sk_intr_xmac(struct sk_if_softc *); 174 void sk_intr_yukon(struct sk_if_softc *); 175 void sk_rxeof(struct sk_if_softc *); 176 void sk_txeof(struct sk_if_softc *); 177 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 178 void sk_start(struct ifnet *); 179 int sk_ioctl(struct ifnet *, u_long, caddr_t); 180 int sk_init(struct ifnet *); 181 void sk_init_xmac(struct sk_if_softc *); 182 void sk_init_yukon(struct sk_if_softc *); 183 void sk_stop(struct ifnet *, int); 184 void sk_watchdog(struct ifnet *); 185 void sk_shutdown(void *); 186 int sk_ifmedia_upd(struct ifnet *); 187 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 188 void sk_reset(struct sk_softc *); 189 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 190 int sk_alloc_jumbo_mem(struct sk_if_softc *); 191 void sk_free_jumbo_mem(struct sk_if_softc *); 192 void *sk_jalloc(struct sk_if_softc *); 193 void sk_jfree(struct mbuf *, caddr_t, size_t, void *); 194 int sk_init_rx_ring(struct sk_if_softc *); 195 int sk_init_tx_ring(struct sk_if_softc *); 196 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 197 void sk_vpd_read_res(struct sk_softc *, 198 struct vpd_res *, int); 199 void sk_vpd_read(struct sk_softc *); 200 201 void sk_update_int_mod(struct sk_softc *); 202 203 int sk_xmac_miibus_readreg(struct device *, int, int); 204 void sk_xmac_miibus_writereg(struct device *, int, int, int); 205 void sk_xmac_miibus_statchg(struct device *); 206 207 int sk_marv_miibus_readreg(struct device *, int, int); 208 void sk_marv_miibus_writereg(struct device *, int, int, int); 209 void sk_marv_miibus_statchg(struct device *); 210 211 u_int32_t sk_xmac_hash(caddr_t); 212 u_int32_t sk_yukon_hash(caddr_t); 213 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 214 void sk_setmulti(struct sk_if_softc *); 215 void sk_tick(void *); 216 217 /* #define SK_DEBUG 2 */ 218 #ifdef SK_DEBUG 219 #define DPRINTF(x) if (skdebug) printf x 220 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 221 int skdebug = SK_DEBUG; 222 223 void sk_dump_txdesc(struct sk_tx_desc *, int); 224 void sk_dump_mbuf(struct mbuf *); 225 void sk_dump_bytes(const char *, int); 226 #else 227 #define DPRINTF(x) 228 #define DPRINTFN(n,x) 229 #endif 230 231 static int sk_sysctl_handler(SYSCTLFN_PROTO); 232 static int sk_root_num; 233 234 /* supported device vendors */ 235 static const struct sk_product { 236 pci_vendor_id_t sk_vendor; 237 pci_product_id_t sk_product; 238 } sk_products[] = { 239 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 240 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 241 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T, }, 242 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 243 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 244 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 245 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 246 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 247 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 248 { 0, 0, } 249 }; 250 251 #define SK_LINKSYS_EG1032_SUBID 0x00151737 252 253 static inline u_int32_t 254 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 255 { 256 #ifdef SK_USEIOSPACE 257 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 258 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 259 #else 260 return CSR_READ_4(sc, reg); 261 #endif 262 } 263 264 static inline u_int16_t 265 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 266 { 267 #ifdef SK_USEIOSPACE 268 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 269 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 270 #else 271 return CSR_READ_2(sc, reg); 272 #endif 273 } 274 275 static inline u_int8_t 276 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 277 { 278 #ifdef SK_USEIOSPACE 279 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 280 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 281 #else 282 return CSR_READ_1(sc, reg); 283 #endif 284 } 285 286 static inline void 287 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 288 { 289 #ifdef SK_USEIOSPACE 290 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 291 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 292 #else 293 CSR_WRITE_4(sc, reg, x); 294 #endif 295 } 296 297 static inline void 298 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 299 { 300 #ifdef SK_USEIOSPACE 301 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 302 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 303 #else 304 CSR_WRITE_2(sc, reg, x); 305 #endif 306 } 307 308 static inline void 309 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 310 { 311 #ifdef SK_USEIOSPACE 312 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 313 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 314 #else 315 CSR_WRITE_1(sc, reg, x); 316 #endif 317 } 318 319 /* 320 * The VPD EEPROM contains Vital Product Data, as suggested in 321 * the PCI 2.1 specification. The VPD data is separared into areas 322 * denoted by resource IDs. The SysKonnect VPD contains an ID string 323 * resource (the name of the adapter), a read-only area resource 324 * containing various key/data fields and a read/write area which 325 * can be used to store asset management information or log messages. 326 * We read the ID string and read-only into buffers attached to 327 * the controller softc structure for later use. At the moment, 328 * we only use the ID string during sk_attach(). 329 */ 330 u_int8_t 331 sk_vpd_readbyte(struct sk_softc *sc, int addr) 332 { 333 int i; 334 335 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 336 for (i = 0; i < SK_TIMEOUT; i++) { 337 DELAY(1); 338 if (sk_win_read_2(sc, 339 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 340 break; 341 } 342 343 if (i == SK_TIMEOUT) 344 return 0; 345 346 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 347 } 348 349 void 350 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 351 { 352 int i; 353 u_int8_t *ptr; 354 355 ptr = (u_int8_t *)res; 356 for (i = 0; i < sizeof(struct vpd_res); i++) 357 ptr[i] = sk_vpd_readbyte(sc, i + addr); 358 } 359 360 void 361 sk_vpd_read(struct sk_softc *sc) 362 { 363 int pos = 0, i; 364 struct vpd_res res; 365 366 if (sc->sk_vpd_prodname != NULL) 367 free(sc->sk_vpd_prodname, M_DEVBUF); 368 if (sc->sk_vpd_readonly != NULL) 369 free(sc->sk_vpd_readonly, M_DEVBUF); 370 sc->sk_vpd_prodname = NULL; 371 sc->sk_vpd_readonly = NULL; 372 373 sk_vpd_read_res(sc, &res, pos); 374 375 if (res.vr_id != VPD_RES_ID) { 376 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 377 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 378 return; 379 } 380 381 pos += sizeof(res); 382 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 383 if (sc->sk_vpd_prodname == NULL) 384 panic("sk_vpd_read"); 385 for (i = 0; i < res.vr_len; i++) 386 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 387 sc->sk_vpd_prodname[i] = '\0'; 388 pos += i; 389 390 sk_vpd_read_res(sc, &res, pos); 391 392 if (res.vr_id != VPD_RES_READ) { 393 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 394 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 395 return; 396 } 397 398 pos += sizeof(res); 399 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 400 if (sc->sk_vpd_readonly == NULL) 401 panic("sk_vpd_read"); 402 for (i = 0; i < res.vr_len ; i++) 403 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 404 } 405 406 int 407 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 408 { 409 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 410 int i; 411 412 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 413 414 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 415 return 0; 416 417 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 418 SK_XM_READ_2(sc_if, XM_PHY_DATA); 419 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 420 for (i = 0; i < SK_TIMEOUT; i++) { 421 DELAY(1); 422 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 423 XM_MMUCMD_PHYDATARDY) 424 break; 425 } 426 427 if (i == SK_TIMEOUT) { 428 aprint_error("%s: phy failed to come ready\n", 429 sc_if->sk_dev.dv_xname); 430 return 0; 431 } 432 } 433 DELAY(1); 434 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 435 } 436 437 void 438 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 439 { 440 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 441 int i; 442 443 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 444 445 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 446 for (i = 0; i < SK_TIMEOUT; i++) { 447 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 448 break; 449 } 450 451 if (i == SK_TIMEOUT) { 452 aprint_error("%s: phy failed to come ready\n", 453 sc_if->sk_dev.dv_xname); 454 return; 455 } 456 457 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 458 for (i = 0; i < SK_TIMEOUT; i++) { 459 DELAY(1); 460 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 461 break; 462 } 463 464 if (i == SK_TIMEOUT) 465 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 466 } 467 468 void 469 sk_xmac_miibus_statchg(struct device *dev) 470 { 471 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 472 struct mii_data *mii = &sc_if->sk_mii; 473 474 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 475 476 /* 477 * If this is a GMII PHY, manually set the XMAC's 478 * duplex mode accordingly. 479 */ 480 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 481 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 482 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 483 else 484 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 485 } 486 } 487 488 int 489 sk_marv_miibus_readreg(struct device *dev, int phy, int reg) 490 { 491 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 492 u_int16_t val; 493 int i; 494 495 if (phy != 0 || 496 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 497 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 498 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 499 phy, reg)); 500 return 0; 501 } 502 503 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 504 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 505 506 for (i = 0; i < SK_TIMEOUT; i++) { 507 DELAY(1); 508 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 509 if (val & YU_SMICR_READ_VALID) 510 break; 511 } 512 513 if (i == SK_TIMEOUT) { 514 aprint_error("%s: phy failed to come ready\n", 515 sc_if->sk_dev.dv_xname); 516 return 0; 517 } 518 519 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 520 SK_TIMEOUT)); 521 522 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 523 524 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 525 phy, reg, val)); 526 527 return val; 528 } 529 530 void 531 sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 532 { 533 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 534 int i; 535 536 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 537 phy, reg, val)); 538 539 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 540 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 541 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 542 543 for (i = 0; i < SK_TIMEOUT; i++) { 544 DELAY(1); 545 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 546 break; 547 } 548 } 549 550 void 551 sk_marv_miibus_statchg(struct device *dev) 552 { 553 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 554 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 555 } 556 557 #define SK_HASH_BITS 6 558 559 u_int32_t 560 sk_xmac_hash(caddr_t addr) 561 { 562 u_int32_t crc; 563 564 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 565 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 566 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 567 return crc; 568 } 569 570 u_int32_t 571 sk_yukon_hash(caddr_t addr) 572 { 573 u_int32_t crc; 574 575 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 576 crc &= ((1 << SK_HASH_BITS) - 1); 577 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 578 return crc; 579 } 580 581 void 582 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 583 { 584 int base = XM_RXFILT_ENTRY(slot); 585 586 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 587 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 588 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 589 } 590 591 void 592 sk_setmulti(struct sk_if_softc *sc_if) 593 { 594 struct sk_softc *sc = sc_if->sk_softc; 595 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 596 u_int32_t hashes[2] = { 0, 0 }; 597 int h = 0, i; 598 struct ethercom *ec = &sc_if->sk_ethercom; 599 struct ether_multi *enm; 600 struct ether_multistep step; 601 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 602 603 /* First, zot all the existing filters. */ 604 switch (sc->sk_type) { 605 case SK_GENESIS: 606 for (i = 1; i < XM_RXFILT_MAX; i++) 607 sk_setfilt(sc_if, (caddr_t)&dummy, i); 608 609 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 610 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 611 break; 612 case SK_YUKON: 613 case SK_YUKON_LITE: 614 case SK_YUKON_LP: 615 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 616 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 617 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 618 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 619 break; 620 } 621 622 /* Now program new ones. */ 623 allmulti: 624 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 625 hashes[0] = 0xFFFFFFFF; 626 hashes[1] = 0xFFFFFFFF; 627 } else { 628 i = 1; 629 /* First find the tail of the list. */ 630 ETHER_FIRST_MULTI(step, ec, enm); 631 while (enm != NULL) { 632 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 633 ETHER_ADDR_LEN)) { 634 ifp->if_flags |= IFF_ALLMULTI; 635 goto allmulti; 636 } 637 DPRINTFN(2,("multicast address %s\n", 638 ether_sprintf(enm->enm_addrlo))); 639 /* 640 * Program the first XM_RXFILT_MAX multicast groups 641 * into the perfect filter. For all others, 642 * use the hash table. 643 */ 644 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 645 sk_setfilt(sc_if, enm->enm_addrlo, i); 646 i++; 647 } 648 else { 649 switch (sc->sk_type) { 650 case SK_GENESIS: 651 h = sk_xmac_hash(enm->enm_addrlo); 652 break; 653 case SK_YUKON: 654 case SK_YUKON_LITE: 655 case SK_YUKON_LP: 656 h = sk_yukon_hash(enm->enm_addrlo); 657 break; 658 } 659 if (h < 32) 660 hashes[0] |= (1 << h); 661 else 662 hashes[1] |= (1 << (h - 32)); 663 } 664 665 ETHER_NEXT_MULTI(step, enm); 666 } 667 } 668 669 switch (sc->sk_type) { 670 case SK_GENESIS: 671 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 672 XM_MODE_RX_USE_PERFECT); 673 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 674 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 675 break; 676 case SK_YUKON: 677 case SK_YUKON_LITE: 678 case SK_YUKON_LP: 679 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 680 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 681 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 682 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 683 break; 684 } 685 } 686 687 int 688 sk_init_rx_ring(struct sk_if_softc *sc_if) 689 { 690 struct sk_chain_data *cd = &sc_if->sk_cdata; 691 struct sk_ring_data *rd = sc_if->sk_rdata; 692 int i; 693 694 bzero((char *)rd->sk_rx_ring, 695 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 696 697 for (i = 0; i < SK_RX_RING_CNT; i++) { 698 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 699 if (i == (SK_RX_RING_CNT - 1)) { 700 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 701 rd->sk_rx_ring[i].sk_next = 702 htole32(SK_RX_RING_ADDR(sc_if, 0)); 703 } else { 704 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 705 rd->sk_rx_ring[i].sk_next = 706 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 707 } 708 } 709 710 for (i = 0; i < SK_RX_RING_CNT; i++) { 711 if (sk_newbuf(sc_if, i, NULL, 712 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 713 aprint_error("%s: failed alloc of %dth mbuf\n", 714 sc_if->sk_dev.dv_xname, i); 715 return ENOBUFS; 716 } 717 } 718 sc_if->sk_cdata.sk_rx_prod = 0; 719 sc_if->sk_cdata.sk_rx_cons = 0; 720 721 return 0; 722 } 723 724 int 725 sk_init_tx_ring(struct sk_if_softc *sc_if) 726 { 727 struct sk_chain_data *cd = &sc_if->sk_cdata; 728 struct sk_ring_data *rd = sc_if->sk_rdata; 729 int i; 730 731 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 732 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 733 734 for (i = 0; i < SK_TX_RING_CNT; i++) { 735 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 736 if (i == (SK_TX_RING_CNT - 1)) { 737 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 738 rd->sk_tx_ring[i].sk_next = 739 htole32(SK_TX_RING_ADDR(sc_if, 0)); 740 } else { 741 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 742 rd->sk_tx_ring[i].sk_next = 743 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 744 } 745 } 746 747 sc_if->sk_cdata.sk_tx_prod = 0; 748 sc_if->sk_cdata.sk_tx_cons = 0; 749 sc_if->sk_cdata.sk_tx_cnt = 0; 750 751 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 752 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 753 754 return 0; 755 } 756 757 int 758 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 759 bus_dmamap_t dmamap) 760 { 761 struct mbuf *m_new = NULL; 762 struct sk_chain *c; 763 struct sk_rx_desc *r; 764 765 if (m == NULL) { 766 caddr_t buf = NULL; 767 768 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 769 if (m_new == NULL) { 770 aprint_error("%s: no memory for rx list -- " 771 "packet dropped!\n", sc_if->sk_dev.dv_xname); 772 return ENOBUFS; 773 } 774 775 /* Allocate the jumbo buffer */ 776 buf = sk_jalloc(sc_if); 777 if (buf == NULL) { 778 m_freem(m_new); 779 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 780 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 781 return ENOBUFS; 782 } 783 784 /* Attach the buffer to the mbuf */ 785 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 786 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 787 788 } else { 789 /* 790 * We're re-using a previously allocated mbuf; 791 * be sure to re-init pointers and lengths to 792 * default values. 793 */ 794 m_new = m; 795 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 796 m_new->m_data = m_new->m_ext.ext_buf; 797 } 798 m_adj(m_new, ETHER_ALIGN); 799 800 c = &sc_if->sk_cdata.sk_rx_chain[i]; 801 r = c->sk_desc; 802 c->sk_mbuf = m_new; 803 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 804 (((vaddr_t)m_new->m_data 805 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 806 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 807 808 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 809 810 return 0; 811 } 812 813 /* 814 * Memory management for jumbo frames. 815 */ 816 817 int 818 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 819 { 820 struct sk_softc *sc = sc_if->sk_softc; 821 caddr_t ptr, kva; 822 bus_dma_segment_t seg; 823 int i, rseg, state, error; 824 struct sk_jpool_entry *entry; 825 826 state = error = 0; 827 828 /* Grab a big chunk o' storage. */ 829 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 830 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 831 aprint_error("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 832 return ENOBUFS; 833 } 834 835 state = 1; 836 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, &kva, 837 BUS_DMA_NOWAIT)) { 838 aprint_error("%s: can't map dma buffers (%d bytes)\n", 839 sc->sk_dev.dv_xname, SK_JMEM); 840 error = ENOBUFS; 841 goto out; 842 } 843 844 state = 2; 845 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 846 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 847 aprint_error("%s: can't create dma map\n", sc->sk_dev.dv_xname); 848 error = ENOBUFS; 849 goto out; 850 } 851 852 state = 3; 853 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 854 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 855 aprint_error("%s: can't load dma map\n", sc->sk_dev.dv_xname); 856 error = ENOBUFS; 857 goto out; 858 } 859 860 state = 4; 861 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 862 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 863 864 LIST_INIT(&sc_if->sk_jfree_listhead); 865 LIST_INIT(&sc_if->sk_jinuse_listhead); 866 867 /* 868 * Now divide it up into 9K pieces and save the addresses 869 * in an array. 870 */ 871 ptr = sc_if->sk_cdata.sk_jumbo_buf; 872 for (i = 0; i < SK_JSLOTS; i++) { 873 sc_if->sk_cdata.sk_jslots[i] = ptr; 874 ptr += SK_JLEN; 875 entry = malloc(sizeof(struct sk_jpool_entry), 876 M_DEVBUF, M_NOWAIT); 877 if (entry == NULL) { 878 aprint_error("%s: no memory for jumbo buffer queue!\n", 879 sc->sk_dev.dv_xname); 880 error = ENOBUFS; 881 goto out; 882 } 883 entry->slot = i; 884 if (i) 885 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 886 entry, jpool_entries); 887 else 888 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 889 entry, jpool_entries); 890 } 891 out: 892 if (error != 0) { 893 switch (state) { 894 case 4: 895 bus_dmamap_unload(sc->sc_dmatag, 896 sc_if->sk_cdata.sk_rx_jumbo_map); 897 case 3: 898 bus_dmamap_destroy(sc->sc_dmatag, 899 sc_if->sk_cdata.sk_rx_jumbo_map); 900 case 2: 901 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 902 case 1: 903 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 904 break; 905 default: 906 break; 907 } 908 } 909 910 return error; 911 } 912 913 /* 914 * Allocate a jumbo buffer. 915 */ 916 void * 917 sk_jalloc(struct sk_if_softc *sc_if) 918 { 919 struct sk_jpool_entry *entry; 920 921 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 922 923 if (entry == NULL) 924 return NULL; 925 926 LIST_REMOVE(entry, jpool_entries); 927 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 928 return sc_if->sk_cdata.sk_jslots[entry->slot]; 929 } 930 931 /* 932 * Release a jumbo buffer. 933 */ 934 void 935 sk_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 936 { 937 struct sk_jpool_entry *entry; 938 struct sk_if_softc *sc; 939 int i, s; 940 941 /* Extract the softc struct pointer. */ 942 sc = (struct sk_if_softc *)arg; 943 944 if (sc == NULL) 945 panic("sk_jfree: can't find softc pointer!"); 946 947 /* calculate the slot this buffer belongs to */ 948 949 i = ((vaddr_t)buf 950 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 951 952 if ((i < 0) || (i >= SK_JSLOTS)) 953 panic("sk_jfree: asked to free buffer that we don't manage!"); 954 955 s = splvm(); 956 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 957 if (entry == NULL) 958 panic("sk_jfree: buffer not in use!"); 959 entry->slot = i; 960 LIST_REMOVE(entry, jpool_entries); 961 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 962 963 if (__predict_true(m != NULL)) 964 pool_cache_put(&mbpool_cache, m); 965 splx(s); 966 } 967 968 /* 969 * Set media options. 970 */ 971 int 972 sk_ifmedia_upd(struct ifnet *ifp) 973 { 974 struct sk_if_softc *sc_if = ifp->if_softc; 975 976 (void) sk_init(ifp); 977 mii_mediachg(&sc_if->sk_mii); 978 return 0; 979 } 980 981 /* 982 * Report current media status. 983 */ 984 void 985 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 986 { 987 struct sk_if_softc *sc_if = ifp->if_softc; 988 989 mii_pollstat(&sc_if->sk_mii); 990 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 991 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 992 } 993 994 int 995 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 996 { 997 struct sk_if_softc *sc_if = ifp->if_softc; 998 struct sk_softc *sc = sc_if->sk_softc; 999 struct ifreq *ifr = (struct ifreq *) data; 1000 struct mii_data *mii; 1001 int s, error = 0; 1002 1003 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1004 1005 s = splnet(); 1006 1007 switch (command) { 1008 1009 case SIOCSIFFLAGS: 1010 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1011 if (ifp->if_flags & IFF_UP) { 1012 if (ifp->if_flags & IFF_RUNNING && 1013 ifp->if_flags & IFF_PROMISC && 1014 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1015 switch (sc->sk_type) { 1016 case SK_GENESIS: 1017 SK_XM_SETBIT_4(sc_if, XM_MODE, 1018 XM_MODE_RX_PROMISC); 1019 break; 1020 case SK_YUKON: 1021 case SK_YUKON_LITE: 1022 case SK_YUKON_LP: 1023 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1024 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1025 break; 1026 } 1027 sk_setmulti(sc_if); 1028 } else if (ifp->if_flags & IFF_RUNNING && 1029 !(ifp->if_flags & IFF_PROMISC) && 1030 sc_if->sk_if_flags & IFF_PROMISC) { 1031 switch (sc->sk_type) { 1032 case SK_GENESIS: 1033 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1034 XM_MODE_RX_PROMISC); 1035 break; 1036 case SK_YUKON: 1037 case SK_YUKON_LITE: 1038 case SK_YUKON_LP: 1039 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1040 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1041 break; 1042 } 1043 1044 sk_setmulti(sc_if); 1045 } else 1046 (void) sk_init(ifp); 1047 } else { 1048 if (ifp->if_flags & IFF_RUNNING) 1049 sk_stop(ifp,0); 1050 } 1051 sc_if->sk_if_flags = ifp->if_flags; 1052 error = 0; 1053 break; 1054 1055 case SIOCGIFMEDIA: 1056 case SIOCSIFMEDIA: 1057 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 1058 mii = &sc_if->sk_mii; 1059 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1060 break; 1061 default: 1062 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1063 error = ether_ioctl(ifp, command, data); 1064 1065 if ( error == ENETRESET) { 1066 if (ifp->if_flags & IFF_RUNNING) { 1067 sk_setmulti(sc_if); 1068 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1069 } 1070 error = 0; 1071 } else if ( error ) { 1072 splx(s); 1073 return error; 1074 } 1075 break; 1076 } 1077 1078 splx(s); 1079 return error; 1080 } 1081 1082 void 1083 sk_update_int_mod(struct sk_softc *sc) 1084 { 1085 u_int32_t sk_imtimer_ticks; 1086 1087 /* 1088 * Configure interrupt moderation. The moderation timer 1089 * defers interrupts specified in the interrupt moderation 1090 * timer mask based on the timeout specified in the interrupt 1091 * moderation timer init register. Each bit in the timer 1092 * register represents one tick, so to specify a timeout in 1093 * microseconds, we have to multiply by the correct number of 1094 * ticks-per-microsecond. 1095 */ 1096 switch (sc->sk_type) { 1097 case SK_GENESIS: 1098 sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1099 break; 1100 case SK_YUKON_EC: 1101 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1102 break; 1103 default: 1104 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1105 } 1106 aprint_verbose("%s: interrupt moderation is %d us\n", 1107 sc->sk_dev.dv_xname, sc->sk_int_mod); 1108 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1109 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1110 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1111 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1112 sc->sk_int_mod_pending = 0; 1113 } 1114 1115 /* 1116 * Lookup: Check the PCI vendor and device, and return a pointer to 1117 * The structure if the IDs match against our list. 1118 */ 1119 1120 static const struct sk_product * 1121 sk_lookup(const struct pci_attach_args *pa) 1122 { 1123 const struct sk_product *psk; 1124 1125 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1126 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1127 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1128 return psk; 1129 } 1130 return NULL; 1131 } 1132 1133 /* 1134 * Probe for a SysKonnect GEnesis chip. 1135 */ 1136 1137 int 1138 skc_probe(struct device *parent, struct cfdata *match, void *aux) 1139 { 1140 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1141 const struct sk_product *psk; 1142 pcireg_t subid; 1143 1144 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1145 1146 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1147 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1148 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1149 subid == SK_LINKSYS_EG1032_SUBID) 1150 return 1; 1151 1152 if ((psk = sk_lookup(pa))) { 1153 return 1; 1154 } 1155 return 0; 1156 } 1157 1158 /* 1159 * Force the GEnesis into reset, then bring it out of reset. 1160 */ 1161 void sk_reset(struct sk_softc *sc) 1162 { 1163 DPRINTFN(2, ("sk_reset\n")); 1164 1165 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1166 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1167 if (SK_YUKON_FAMILY(sc->sk_type)) 1168 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1169 1170 DELAY(1000); 1171 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1172 DELAY(2); 1173 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1174 if (SK_YUKON_FAMILY(sc->sk_type)) 1175 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1176 1177 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1178 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1179 CSR_READ_2(sc, SK_LINK_CTRL))); 1180 1181 if (sc->sk_type == SK_GENESIS) { 1182 /* Configure packet arbiter */ 1183 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1184 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1185 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1186 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1187 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1188 } 1189 1190 /* Enable RAM interface */ 1191 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1192 1193 sk_update_int_mod(sc); 1194 } 1195 1196 int 1197 sk_probe(struct device *parent, struct cfdata *match, void *aux) 1198 { 1199 struct skc_attach_args *sa = aux; 1200 1201 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1202 return 0; 1203 1204 return 1; 1205 } 1206 1207 /* 1208 * Each XMAC chip is attached as a separate logical IP interface. 1209 * Single port cards will have only one logical interface of course. 1210 */ 1211 void 1212 sk_attach(struct device *parent, struct device *self, void *aux) 1213 { 1214 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1215 struct sk_softc *sc = (struct sk_softc *)parent; 1216 struct skc_attach_args *sa = aux; 1217 struct sk_txmap_entry *entry; 1218 struct ifnet *ifp; 1219 bus_dma_segment_t seg; 1220 bus_dmamap_t dmamap; 1221 caddr_t kva; 1222 int i, rseg; 1223 1224 sc_if->sk_port = sa->skc_port; 1225 sc_if->sk_softc = sc; 1226 sc->sk_if[sa->skc_port] = sc_if; 1227 1228 if (sa->skc_port == SK_PORT_A) 1229 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1230 if (sa->skc_port == SK_PORT_B) 1231 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1232 1233 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1234 1235 /* 1236 * Get station address for this interface. Note that 1237 * dual port cards actually come with three station 1238 * addresses: one for each port, plus an extra. The 1239 * extra one is used by the SysKonnect driver software 1240 * as a 'virtual' station address for when both ports 1241 * are operating in failover mode. Currently we don't 1242 * use this extra address. 1243 */ 1244 for (i = 0; i < ETHER_ADDR_LEN; i++) 1245 sc_if->sk_enaddr[i] = 1246 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1247 1248 1249 aprint_normal(": Ethernet address %s\n", 1250 ether_sprintf(sc_if->sk_enaddr)); 1251 1252 /* 1253 * Set up RAM buffer addresses. The NIC will have a certain 1254 * amount of SRAM on it, somewhere between 512K and 2MB. We 1255 * need to divide this up a) between the transmitter and 1256 * receiver and b) between the two XMACs, if this is a 1257 * dual port NIC. Our algorithm is to divide up the memory 1258 * evenly so that everyone gets a fair share. 1259 */ 1260 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1261 u_int32_t chunk, val; 1262 1263 chunk = sc->sk_ramsize / 2; 1264 val = sc->sk_rboff / sizeof(u_int64_t); 1265 sc_if->sk_rx_ramstart = val; 1266 val += (chunk / sizeof(u_int64_t)); 1267 sc_if->sk_rx_ramend = val - 1; 1268 sc_if->sk_tx_ramstart = val; 1269 val += (chunk / sizeof(u_int64_t)); 1270 sc_if->sk_tx_ramend = val - 1; 1271 } else { 1272 u_int32_t chunk, val; 1273 1274 chunk = sc->sk_ramsize / 4; 1275 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1276 sizeof(u_int64_t); 1277 sc_if->sk_rx_ramstart = val; 1278 val += (chunk / sizeof(u_int64_t)); 1279 sc_if->sk_rx_ramend = val - 1; 1280 sc_if->sk_tx_ramstart = val; 1281 val += (chunk / sizeof(u_int64_t)); 1282 sc_if->sk_tx_ramend = val - 1; 1283 } 1284 1285 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1286 " tx_ramstart=%#x tx_ramend=%#x\n", 1287 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1288 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1289 1290 /* Read and save PHY type and set PHY address */ 1291 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1292 switch (sc_if->sk_phytype) { 1293 case SK_PHYTYPE_XMAC: 1294 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1295 break; 1296 case SK_PHYTYPE_BCOM: 1297 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1298 break; 1299 case SK_PHYTYPE_MARV_COPPER: 1300 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1301 break; 1302 default: 1303 aprint_error("%s: unsupported PHY type: %d\n", 1304 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1305 return; 1306 } 1307 1308 /* Allocate the descriptor queues. */ 1309 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1310 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1311 aprint_error("%s: can't alloc rx buffers\n", 1312 sc->sk_dev.dv_xname); 1313 goto fail; 1314 } 1315 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1316 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1317 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1318 sc_if->sk_dev.dv_xname, 1319 (u_long) sizeof(struct sk_ring_data)); 1320 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1321 goto fail; 1322 } 1323 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1324 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1325 &sc_if->sk_ring_map)) { 1326 aprint_error("%s: can't create dma map\n", 1327 sc_if->sk_dev.dv_xname); 1328 bus_dmamem_unmap(sc->sc_dmatag, kva, 1329 sizeof(struct sk_ring_data)); 1330 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1331 goto fail; 1332 } 1333 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1334 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1335 aprint_error("%s: can't load dma map\n", 1336 sc_if->sk_dev.dv_xname); 1337 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1338 bus_dmamem_unmap(sc->sc_dmatag, kva, 1339 sizeof(struct sk_ring_data)); 1340 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1341 goto fail; 1342 } 1343 1344 for (i = 0; i < SK_RX_RING_CNT; i++) 1345 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1346 1347 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1348 for (i = 0; i < SK_TX_RING_CNT; i++) { 1349 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1350 1351 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1352 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1353 aprint_error("%s: Can't create TX dmamap\n", 1354 sc_if->sk_dev.dv_xname); 1355 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1356 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1357 bus_dmamem_unmap(sc->sc_dmatag, kva, 1358 sizeof(struct sk_ring_data)); 1359 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1360 goto fail; 1361 } 1362 1363 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1364 if (!entry) { 1365 aprint_error("%s: Can't alloc txmap entry\n", 1366 sc_if->sk_dev.dv_xname); 1367 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1368 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1369 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1370 bus_dmamem_unmap(sc->sc_dmatag, kva, 1371 sizeof(struct sk_ring_data)); 1372 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1373 goto fail; 1374 } 1375 entry->dmamap = dmamap; 1376 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1377 } 1378 1379 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1380 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1381 1382 ifp = &sc_if->sk_ethercom.ec_if; 1383 /* Try to allocate memory for jumbo buffers. */ 1384 if (sk_alloc_jumbo_mem(sc_if)) { 1385 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1386 goto fail; 1387 } 1388 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1389 | ETHERCAP_JUMBO_MTU; 1390 1391 ifp->if_softc = sc_if; 1392 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1393 ifp->if_ioctl = sk_ioctl; 1394 ifp->if_start = sk_start; 1395 ifp->if_stop = sk_stop; 1396 ifp->if_init = sk_init; 1397 ifp->if_watchdog = sk_watchdog; 1398 ifp->if_capabilities = 0; 1399 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1400 IFQ_SET_READY(&ifp->if_snd); 1401 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1402 1403 /* 1404 * Do miibus setup. 1405 */ 1406 switch (sc->sk_type) { 1407 case SK_GENESIS: 1408 sk_init_xmac(sc_if); 1409 break; 1410 case SK_YUKON: 1411 case SK_YUKON_LITE: 1412 case SK_YUKON_LP: 1413 sk_init_yukon(sc_if); 1414 break; 1415 default: 1416 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1417 sc->sk_type); 1418 } 1419 1420 DPRINTFN(2, ("sk_attach: 1\n")); 1421 1422 sc_if->sk_mii.mii_ifp = ifp; 1423 switch (sc->sk_type) { 1424 case SK_GENESIS: 1425 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1426 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1427 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1428 break; 1429 case SK_YUKON: 1430 case SK_YUKON_LITE: 1431 case SK_YUKON_LP: 1432 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1433 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1434 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1435 break; 1436 } 1437 1438 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1439 sk_ifmedia_upd, sk_ifmedia_sts); 1440 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1441 MII_OFFSET_ANY, 0); 1442 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1443 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1444 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1445 0, NULL); 1446 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1447 } else 1448 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1449 1450 callout_init(&sc_if->sk_tick_ch); 1451 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1452 1453 DPRINTFN(2, ("sk_attach: 1\n")); 1454 1455 /* 1456 * Call MI attach routines. 1457 */ 1458 if_attach(ifp); 1459 1460 ether_ifattach(ifp, sc_if->sk_enaddr); 1461 1462 #if NRND > 0 1463 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1464 RND_TYPE_NET, 0); 1465 #endif 1466 1467 DPRINTFN(2, ("sk_attach: end\n")); 1468 1469 return; 1470 1471 fail: 1472 sc->sk_if[sa->skc_port] = NULL; 1473 } 1474 1475 int 1476 skcprint(void *aux, const char *pnp) 1477 { 1478 struct skc_attach_args *sa = aux; 1479 1480 if (pnp) 1481 aprint_normal("sk port %c at %s", 1482 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1483 else 1484 aprint_normal(" port %c", 1485 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1486 return UNCONF; 1487 } 1488 1489 /* 1490 * Attach the interface. Allocate softc structures, do ifmedia 1491 * setup and ethernet/BPF attach. 1492 */ 1493 void 1494 skc_attach(struct device *parent, struct device *self, void *aux) 1495 { 1496 struct sk_softc *sc = (struct sk_softc *)self; 1497 struct pci_attach_args *pa = aux; 1498 struct skc_attach_args skca; 1499 pci_chipset_tag_t pc = pa->pa_pc; 1500 #ifndef SK_USEIOSPACE 1501 pcireg_t memtype; 1502 #endif 1503 pci_intr_handle_t ih; 1504 const char *intrstr = NULL; 1505 bus_addr_t iobase; 1506 bus_size_t iosize; 1507 int rc, sk_nodenum; 1508 u_int32_t command; 1509 const char *revstr; 1510 const struct sysctlnode *node; 1511 1512 DPRINTFN(2, ("begin skc_attach\n")); 1513 1514 /* 1515 * Handle power management nonsense. 1516 */ 1517 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1518 1519 if (command == 0x01) { 1520 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1521 if (command & SK_PSTATE_MASK) { 1522 u_int32_t xiobase, membase, irq; 1523 1524 /* Save important PCI config data. */ 1525 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1526 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1527 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1528 1529 /* Reset the power state. */ 1530 aprint_normal("%s chip is in D%d power mode " 1531 "-- setting to D0\n", sc->sk_dev.dv_xname, 1532 command & SK_PSTATE_MASK); 1533 command &= 0xFFFFFFFC; 1534 pci_conf_write(pc, pa->pa_tag, 1535 SK_PCI_PWRMGMTCTRL, command); 1536 1537 /* Restore PCI config data. */ 1538 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1539 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1540 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1541 } 1542 } 1543 1544 /* 1545 * Map control/status registers. 1546 */ 1547 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1548 command |= PCI_COMMAND_IO_ENABLE | 1549 PCI_COMMAND_MEM_ENABLE | 1550 PCI_COMMAND_MASTER_ENABLE; 1551 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1552 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1553 1554 #ifdef SK_USEIOSPACE 1555 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1556 aprint_error(": failed to enable I/O ports!\n"); 1557 return; 1558 } 1559 /* 1560 * Map control/status registers. 1561 */ 1562 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1563 &sc->sk_btag, &sc->sk_bhandle, 1564 &iobase, &iosize)) { 1565 aprint_error(": can't find i/o space\n"); 1566 return; 1567 } 1568 #else 1569 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1570 aprint_error(": failed to enable memory mapping!\n"); 1571 return; 1572 } 1573 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1574 switch (memtype) { 1575 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1576 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1577 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1578 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1579 &iobase, &iosize) == 0) 1580 break; 1581 default: 1582 aprint_error("%s: can't find mem space\n", 1583 sc->sk_dev.dv_xname); 1584 return; 1585 } 1586 1587 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1588 #endif 1589 sc->sc_dmatag = pa->pa_dmat; 1590 1591 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1592 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1593 1594 /* bail out here if chip is not recognized */ 1595 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1596 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1597 goto fail; 1598 } 1599 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1600 1601 /* Allocate interrupt */ 1602 if (pci_intr_map(pa, &ih)) { 1603 aprint_error(": couldn't map interrupt\n"); 1604 goto fail; 1605 } 1606 1607 intrstr = pci_intr_string(pc, ih); 1608 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1609 if (sc->sk_intrhand == NULL) { 1610 aprint_error(": couldn't establish interrupt"); 1611 if (intrstr != NULL) 1612 aprint_normal(" at %s", intrstr); 1613 goto fail; 1614 } 1615 aprint_normal(": %s\n", intrstr); 1616 1617 /* Reset the adapter. */ 1618 sk_reset(sc); 1619 1620 /* Read and save vital product data from EEPROM. */ 1621 sk_vpd_read(sc); 1622 1623 if (sc->sk_type == SK_GENESIS) { 1624 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1625 /* Read and save RAM size and RAMbuffer offset */ 1626 switch (val) { 1627 case SK_RAMSIZE_512K_64: 1628 sc->sk_ramsize = 0x80000; 1629 sc->sk_rboff = SK_RBOFF_0; 1630 break; 1631 case SK_RAMSIZE_1024K_64: 1632 sc->sk_ramsize = 0x100000; 1633 sc->sk_rboff = SK_RBOFF_80000; 1634 break; 1635 case SK_RAMSIZE_1024K_128: 1636 sc->sk_ramsize = 0x100000; 1637 sc->sk_rboff = SK_RBOFF_0; 1638 break; 1639 case SK_RAMSIZE_2048K_128: 1640 sc->sk_ramsize = 0x200000; 1641 sc->sk_rboff = SK_RBOFF_0; 1642 break; 1643 default: 1644 aprint_error("%s: unknown ram size: %d\n", 1645 sc->sk_dev.dv_xname, val); 1646 goto fail_1; 1647 break; 1648 } 1649 1650 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1651 sc->sk_ramsize, sc->sk_ramsize / 1024, 1652 sc->sk_rboff)); 1653 } else { 1654 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1655 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1656 sc->sk_rboff = SK_RBOFF_0; 1657 1658 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1659 sc->sk_ramsize / 1024, sc->sk_ramsize, 1660 sc->sk_rboff)); 1661 } 1662 1663 /* Read and save physical media type */ 1664 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1665 case SK_PMD_1000BASESX: 1666 sc->sk_pmd = IFM_1000_SX; 1667 break; 1668 case SK_PMD_1000BASELX: 1669 sc->sk_pmd = IFM_1000_LX; 1670 break; 1671 case SK_PMD_1000BASECX: 1672 sc->sk_pmd = IFM_1000_CX; 1673 break; 1674 case SK_PMD_1000BASETX: 1675 case SK_PMD_1000BASETX_ALT: 1676 sc->sk_pmd = IFM_1000_T; 1677 break; 1678 default: 1679 aprint_error("%s: unknown media type: 0x%x\n", 1680 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1681 goto fail_1; 1682 } 1683 1684 /* determine whether to name it with vpd or just make it up */ 1685 /* Marvell Yukon VPD's can freqently be bogus */ 1686 1687 switch (pa->pa_id) { 1688 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1689 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1690 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1691 case PCI_PRODUCT_3COM_3C940: 1692 case PCI_PRODUCT_DLINK_DGE530T: 1693 case PCI_PRODUCT_DLINK_DGE560T: 1694 case PCI_PRODUCT_DLINK_DGE560T_2: 1695 case PCI_PRODUCT_LINKSYS_EG1032: 1696 case PCI_PRODUCT_LINKSYS_EG1064: 1697 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1698 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1699 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1700 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1701 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1702 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1703 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1704 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1705 sc->sk_name = sc->sk_vpd_prodname; 1706 break; 1707 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1708 /* whoops yukon vpd prodname bears no resemblance to reality */ 1709 switch (sc->sk_type) { 1710 case SK_GENESIS: 1711 sc->sk_name = sc->sk_vpd_prodname; 1712 break; 1713 case SK_YUKON: 1714 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1715 break; 1716 case SK_YUKON_LITE: 1717 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1718 break; 1719 case SK_YUKON_LP: 1720 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1721 break; 1722 default: 1723 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1724 } 1725 1726 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1727 1728 if ( sc->sk_type == SK_YUKON ) { 1729 uint32_t flashaddr; 1730 uint8_t testbyte; 1731 1732 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1733 1734 /* test Flash-Address Register */ 1735 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1736 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1737 1738 if (testbyte != 0) { 1739 /* this is yukon lite Rev. A0 */ 1740 sc->sk_type = SK_YUKON_LITE; 1741 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1742 /* restore Flash-Address Register */ 1743 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1744 } 1745 } 1746 break; 1747 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1748 sc->sk_name = sc->sk_vpd_prodname; 1749 break; 1750 default: 1751 sc->sk_name = "Unknown Marvell"; 1752 } 1753 1754 1755 if ( sc->sk_type == SK_YUKON_LITE ) { 1756 switch (sc->sk_rev) { 1757 case SK_YUKON_LITE_REV_A0: 1758 revstr = "A0"; 1759 break; 1760 case SK_YUKON_LITE_REV_A1: 1761 revstr = "A1"; 1762 break; 1763 case SK_YUKON_LITE_REV_A3: 1764 revstr = "A3"; 1765 break; 1766 default: 1767 revstr = ""; 1768 } 1769 } else { 1770 revstr = ""; 1771 } 1772 1773 /* Announce the product name. */ 1774 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1775 sc->sk_name, revstr, sc->sk_rev); 1776 1777 skca.skc_port = SK_PORT_A; 1778 (void)config_found(&sc->sk_dev, &skca, skcprint); 1779 1780 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1781 skca.skc_port = SK_PORT_B; 1782 (void)config_found(&sc->sk_dev, &skca, skcprint); 1783 } 1784 1785 /* Turn on the 'driver is loaded' LED. */ 1786 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1787 1788 /* skc sysctl setup */ 1789 1790 sc->sk_int_mod = SK_IM_DEFAULT; 1791 sc->sk_int_mod_pending = 0; 1792 1793 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1794 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1795 SYSCTL_DESCR("skc per-controller controls"), 1796 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1797 CTL_EOL)) != 0) { 1798 aprint_normal("%s: couldn't create sysctl node\n", 1799 sc->sk_dev.dv_xname); 1800 goto fail_1; 1801 } 1802 1803 sk_nodenum = node->sysctl_num; 1804 1805 /* interrupt moderation time in usecs */ 1806 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1807 CTLFLAG_READWRITE, 1808 CTLTYPE_INT, "int_mod", 1809 SYSCTL_DESCR("sk interrupt moderation timer"), 1810 sk_sysctl_handler, 0, sc, 1811 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1812 CTL_EOL)) != 0) { 1813 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1814 sc->sk_dev.dv_xname); 1815 goto fail_1; 1816 } 1817 1818 return; 1819 1820 fail_1: 1821 pci_intr_disestablish(pc, sc->sk_intrhand); 1822 fail: 1823 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1824 } 1825 1826 int 1827 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1828 { 1829 struct sk_softc *sc = sc_if->sk_softc; 1830 struct sk_tx_desc *f = NULL; 1831 u_int32_t frag, cur, cnt = 0, sk_ctl; 1832 int i; 1833 struct sk_txmap_entry *entry; 1834 bus_dmamap_t txmap; 1835 1836 DPRINTFN(3, ("sk_encap\n")); 1837 1838 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1839 if (entry == NULL) { 1840 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1841 return ENOBUFS; 1842 } 1843 txmap = entry->dmamap; 1844 1845 cur = frag = *txidx; 1846 1847 #ifdef SK_DEBUG 1848 if (skdebug >= 3) 1849 sk_dump_mbuf(m_head); 1850 #endif 1851 1852 /* 1853 * Start packing the mbufs in this chain into 1854 * the fragment pointers. Stop when we run out 1855 * of fragments or hit the end of the mbuf chain. 1856 */ 1857 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1858 BUS_DMA_NOWAIT)) { 1859 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1860 return ENOBUFS; 1861 } 1862 1863 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1864 1865 /* Sync the DMA map. */ 1866 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1867 BUS_DMASYNC_PREWRITE); 1868 1869 for (i = 0; i < txmap->dm_nsegs; i++) { 1870 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1871 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1872 return ENOBUFS; 1873 } 1874 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1875 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1876 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1877 if (cnt == 0) 1878 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1879 else 1880 sk_ctl |= SK_TXCTL_OWN; 1881 f->sk_ctl = htole32(sk_ctl); 1882 cur = frag; 1883 SK_INC(frag, SK_TX_RING_CNT); 1884 cnt++; 1885 } 1886 1887 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1888 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1889 1890 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1891 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1892 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1893 1894 /* Sync descriptors before handing to chip */ 1895 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1896 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1897 1898 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1899 htole32(SK_TXCTL_OWN); 1900 1901 /* Sync first descriptor to hand it off */ 1902 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1903 1904 sc_if->sk_cdata.sk_tx_cnt += cnt; 1905 1906 #ifdef SK_DEBUG 1907 if (skdebug >= 3) { 1908 struct sk_tx_desc *desc; 1909 u_int32_t idx; 1910 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1911 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1912 sk_dump_txdesc(desc, idx); 1913 } 1914 } 1915 #endif 1916 1917 *txidx = frag; 1918 1919 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1920 1921 return 0; 1922 } 1923 1924 void 1925 sk_start(struct ifnet *ifp) 1926 { 1927 struct sk_if_softc *sc_if = ifp->if_softc; 1928 struct sk_softc *sc = sc_if->sk_softc; 1929 struct mbuf *m_head = NULL; 1930 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1931 int pkts = 0; 1932 1933 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1934 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1935 1936 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1937 IFQ_POLL(&ifp->if_snd, m_head); 1938 if (m_head == NULL) 1939 break; 1940 1941 /* 1942 * Pack the data into the transmit ring. If we 1943 * don't have room, set the OACTIVE flag and wait 1944 * for the NIC to drain the ring. 1945 */ 1946 if (sk_encap(sc_if, m_head, &idx)) { 1947 ifp->if_flags |= IFF_OACTIVE; 1948 break; 1949 } 1950 1951 /* now we are committed to transmit the packet */ 1952 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1953 pkts++; 1954 1955 /* 1956 * If there's a BPF listener, bounce a copy of this frame 1957 * to him. 1958 */ 1959 #if NBPFILTER > 0 1960 if (ifp->if_bpf) 1961 bpf_mtap(ifp->if_bpf, m_head); 1962 #endif 1963 } 1964 if (pkts == 0) 1965 return; 1966 1967 /* Transmit */ 1968 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1969 sc_if->sk_cdata.sk_tx_prod = idx; 1970 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1971 1972 /* Set a timeout in case the chip goes out to lunch. */ 1973 ifp->if_timer = 5; 1974 } 1975 } 1976 1977 1978 void 1979 sk_watchdog(struct ifnet *ifp) 1980 { 1981 struct sk_if_softc *sc_if = ifp->if_softc; 1982 1983 /* 1984 * Reclaim first as there is a possibility of losing Tx completion 1985 * interrupts. 1986 */ 1987 sk_txeof(sc_if); 1988 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1989 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1990 1991 ifp->if_oerrors++; 1992 1993 sk_init(ifp); 1994 } 1995 } 1996 1997 void 1998 sk_shutdown(void * v) 1999 { 2000 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2001 struct sk_softc *sc = sc_if->sk_softc; 2002 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2003 2004 DPRINTFN(2, ("sk_shutdown\n")); 2005 sk_stop(ifp,1); 2006 2007 /* Turn off the 'driver is loaded' LED. */ 2008 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2009 2010 /* 2011 * Reset the GEnesis controller. Doing this should also 2012 * assert the resets on the attached XMAC(s). 2013 */ 2014 sk_reset(sc); 2015 } 2016 2017 void 2018 sk_rxeof(struct sk_if_softc *sc_if) 2019 { 2020 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2021 struct mbuf *m; 2022 struct sk_chain *cur_rx; 2023 struct sk_rx_desc *cur_desc; 2024 int i, cur, total_len = 0; 2025 u_int32_t rxstat, sk_ctl; 2026 bus_dmamap_t dmamap; 2027 2028 i = sc_if->sk_cdata.sk_rx_prod; 2029 2030 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2031 2032 for (;;) { 2033 cur = i; 2034 2035 /* Sync the descriptor */ 2036 SK_CDRXSYNC(sc_if, cur, 2037 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2038 2039 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2040 if (sk_ctl & SK_RXCTL_OWN) { 2041 /* Invalidate the descriptor -- it's not ready yet */ 2042 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2043 sc_if->sk_cdata.sk_rx_prod = i; 2044 break; 2045 } 2046 2047 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2048 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2049 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2050 2051 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2052 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2053 2054 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2055 m = cur_rx->sk_mbuf; 2056 cur_rx->sk_mbuf = NULL; 2057 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2058 2059 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2060 2061 SK_INC(i, SK_RX_RING_CNT); 2062 2063 if (rxstat & XM_RXSTAT_ERRFRAME) { 2064 ifp->if_ierrors++; 2065 sk_newbuf(sc_if, cur, m, dmamap); 2066 continue; 2067 } 2068 2069 /* 2070 * Try to allocate a new jumbo buffer. If that 2071 * fails, copy the packet to mbufs and put the 2072 * jumbo buffer back in the ring so it can be 2073 * re-used. If allocating mbufs fails, then we 2074 * have to drop the packet. 2075 */ 2076 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2077 struct mbuf *m0; 2078 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2079 total_len + ETHER_ALIGN, 0, ifp, NULL); 2080 sk_newbuf(sc_if, cur, m, dmamap); 2081 if (m0 == NULL) { 2082 aprint_error("%s: no receive buffers " 2083 "available -- packet dropped!\n", 2084 sc_if->sk_dev.dv_xname); 2085 ifp->if_ierrors++; 2086 continue; 2087 } 2088 m_adj(m0, ETHER_ALIGN); 2089 m = m0; 2090 } else { 2091 m->m_pkthdr.rcvif = ifp; 2092 m->m_pkthdr.len = m->m_len = total_len; 2093 } 2094 2095 ifp->if_ipackets++; 2096 2097 #if NBPFILTER > 0 2098 if (ifp->if_bpf) 2099 bpf_mtap(ifp->if_bpf, m); 2100 #endif 2101 /* pass it on. */ 2102 (*ifp->if_input)(ifp, m); 2103 } 2104 } 2105 2106 void 2107 sk_txeof(struct sk_if_softc *sc_if) 2108 { 2109 struct sk_softc *sc = sc_if->sk_softc; 2110 struct sk_tx_desc *cur_tx; 2111 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2112 u_int32_t idx, sk_ctl; 2113 struct sk_txmap_entry *entry; 2114 2115 DPRINTFN(3, ("sk_txeof\n")); 2116 2117 /* 2118 * Go through our tx ring and free mbufs for those 2119 * frames that have been sent. 2120 */ 2121 idx = sc_if->sk_cdata.sk_tx_cons; 2122 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2123 SK_CDTXSYNC(sc_if, idx, 1, 2124 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2125 2126 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2127 sk_ctl = le32toh(cur_tx->sk_ctl); 2128 #ifdef SK_DEBUG 2129 if (skdebug >= 3) 2130 sk_dump_txdesc(cur_tx, idx); 2131 #endif 2132 if (sk_ctl & SK_TXCTL_OWN) { 2133 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2134 break; 2135 } 2136 if (sk_ctl & SK_TXCTL_LASTFRAG) 2137 ifp->if_opackets++; 2138 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2139 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2140 2141 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2142 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2143 2144 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2145 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2146 2147 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2148 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2149 link); 2150 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2151 } 2152 sc_if->sk_cdata.sk_tx_cnt--; 2153 SK_INC(idx, SK_TX_RING_CNT); 2154 } 2155 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2156 ifp->if_timer = 0; 2157 else /* nudge chip to keep tx ring moving */ 2158 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2159 2160 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2161 ifp->if_flags &= ~IFF_OACTIVE; 2162 2163 sc_if->sk_cdata.sk_tx_cons = idx; 2164 } 2165 2166 void 2167 sk_tick(void *xsc_if) 2168 { 2169 struct sk_if_softc *sc_if = xsc_if; 2170 struct mii_data *mii = &sc_if->sk_mii; 2171 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2172 int i; 2173 2174 DPRINTFN(3, ("sk_tick\n")); 2175 2176 if (!(ifp->if_flags & IFF_UP)) 2177 return; 2178 2179 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2180 sk_intr_bcom(sc_if); 2181 return; 2182 } 2183 2184 /* 2185 * According to SysKonnect, the correct way to verify that 2186 * the link has come back up is to poll bit 0 of the GPIO 2187 * register three times. This pin has the signal from the 2188 * link sync pin connected to it; if we read the same link 2189 * state 3 times in a row, we know the link is up. 2190 */ 2191 for (i = 0; i < 3; i++) { 2192 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2193 break; 2194 } 2195 2196 if (i != 3) { 2197 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2198 return; 2199 } 2200 2201 /* Turn the GP0 interrupt back on. */ 2202 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2203 SK_XM_READ_2(sc_if, XM_ISR); 2204 mii_tick(mii); 2205 mii_pollstat(mii); 2206 callout_stop(&sc_if->sk_tick_ch); 2207 } 2208 2209 void 2210 sk_intr_bcom(struct sk_if_softc *sc_if) 2211 { 2212 struct mii_data *mii = &sc_if->sk_mii; 2213 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2214 int status; 2215 2216 2217 DPRINTFN(3, ("sk_intr_bcom\n")); 2218 2219 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2220 2221 /* 2222 * Read the PHY interrupt register to make sure 2223 * we clear any pending interrupts. 2224 */ 2225 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2226 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2227 2228 if (!(ifp->if_flags & IFF_RUNNING)) { 2229 sk_init_xmac(sc_if); 2230 return; 2231 } 2232 2233 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2234 int lstat; 2235 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2236 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2237 2238 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2239 mii_mediachg(mii); 2240 /* Turn off the link LED. */ 2241 SK_IF_WRITE_1(sc_if, 0, 2242 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2243 sc_if->sk_link = 0; 2244 } else if (status & BRGPHY_ISR_LNK_CHG) { 2245 sk_xmac_miibus_writereg((struct device *)sc_if, 2246 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2247 mii_tick(mii); 2248 sc_if->sk_link = 1; 2249 /* Turn on the link LED. */ 2250 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2251 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2252 SK_LINKLED_BLINK_OFF); 2253 mii_pollstat(mii); 2254 } else { 2255 mii_tick(mii); 2256 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2257 } 2258 } 2259 2260 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2261 } 2262 2263 void 2264 sk_intr_xmac(struct sk_if_softc *sc_if) 2265 { 2266 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2267 2268 DPRINTFN(3, ("sk_intr_xmac\n")); 2269 2270 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2271 if (status & XM_ISR_GP0_SET) { 2272 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2273 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2274 } 2275 2276 if (status & XM_ISR_AUTONEG_DONE) { 2277 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2278 } 2279 } 2280 2281 if (status & XM_IMR_TX_UNDERRUN) 2282 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2283 2284 if (status & XM_IMR_RX_OVERRUN) 2285 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2286 } 2287 2288 void 2289 sk_intr_yukon(struct sk_if_softc *sc_if) 2290 { 2291 int status; 2292 2293 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2294 2295 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2296 } 2297 2298 int 2299 sk_intr(void *xsc) 2300 { 2301 struct sk_softc *sc = xsc; 2302 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2303 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2304 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2305 u_int32_t status; 2306 int claimed = 0; 2307 2308 if (sc_if0 != NULL) 2309 ifp0 = &sc_if0->sk_ethercom.ec_if; 2310 if (sc_if1 != NULL) 2311 ifp1 = &sc_if1->sk_ethercom.ec_if; 2312 2313 for (;;) { 2314 status = CSR_READ_4(sc, SK_ISSR); 2315 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2316 2317 if (!(status & sc->sk_intrmask)) 2318 break; 2319 2320 claimed = 1; 2321 2322 /* Handle receive interrupts first. */ 2323 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2324 sk_rxeof(sc_if0); 2325 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2326 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2327 } 2328 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2329 sk_rxeof(sc_if1); 2330 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2331 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2332 } 2333 2334 /* Then transmit interrupts. */ 2335 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2336 sk_txeof(sc_if0); 2337 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2338 SK_TXBMU_CLR_IRQ_EOF); 2339 } 2340 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2341 sk_txeof(sc_if1); 2342 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2343 SK_TXBMU_CLR_IRQ_EOF); 2344 } 2345 2346 /* Then MAC interrupts. */ 2347 if (sc_if0 && (status & SK_ISR_MAC1) && 2348 (ifp0->if_flags & IFF_RUNNING)) { 2349 if (sc->sk_type == SK_GENESIS) 2350 sk_intr_xmac(sc_if0); 2351 else 2352 sk_intr_yukon(sc_if0); 2353 } 2354 2355 if (sc_if1 && (status & SK_ISR_MAC2) && 2356 (ifp1->if_flags & IFF_RUNNING)) { 2357 if (sc->sk_type == SK_GENESIS) 2358 sk_intr_xmac(sc_if1); 2359 else 2360 sk_intr_yukon(sc_if1); 2361 2362 } 2363 2364 if (status & SK_ISR_EXTERNAL_REG) { 2365 if (sc_if0 != NULL && 2366 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2367 sk_intr_bcom(sc_if0); 2368 2369 if (sc_if1 != NULL && 2370 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2371 sk_intr_bcom(sc_if1); 2372 } 2373 } 2374 2375 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2376 2377 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2378 sk_start(ifp0); 2379 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2380 sk_start(ifp1); 2381 2382 #if NRND > 0 2383 if (RND_ENABLED(&sc->rnd_source)) 2384 rnd_add_uint32(&sc->rnd_source, status); 2385 #endif 2386 2387 if (sc->sk_int_mod_pending) 2388 sk_update_int_mod(sc); 2389 2390 return claimed; 2391 } 2392 2393 void 2394 sk_init_xmac(struct sk_if_softc *sc_if) 2395 { 2396 struct sk_softc *sc = sc_if->sk_softc; 2397 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2398 static const struct sk_bcom_hack bhack[] = { 2399 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2400 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2401 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2402 { 0, 0 } }; 2403 2404 DPRINTFN(1, ("sk_init_xmac\n")); 2405 2406 /* Unreset the XMAC. */ 2407 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2408 DELAY(1000); 2409 2410 /* Reset the XMAC's internal state. */ 2411 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2412 2413 /* Save the XMAC II revision */ 2414 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2415 2416 /* 2417 * Perform additional initialization for external PHYs, 2418 * namely for the 1000baseTX cards that use the XMAC's 2419 * GMII mode. 2420 */ 2421 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2422 int i = 0; 2423 u_int32_t val; 2424 2425 /* Take PHY out of reset. */ 2426 val = sk_win_read_4(sc, SK_GPIO); 2427 if (sc_if->sk_port == SK_PORT_A) 2428 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2429 else 2430 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2431 sk_win_write_4(sc, SK_GPIO, val); 2432 2433 /* Enable GMII mode on the XMAC. */ 2434 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2435 2436 sk_xmac_miibus_writereg((struct device *)sc_if, 2437 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2438 DELAY(10000); 2439 sk_xmac_miibus_writereg((struct device *)sc_if, 2440 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2441 2442 /* 2443 * Early versions of the BCM5400 apparently have 2444 * a bug that requires them to have their reserved 2445 * registers initialized to some magic values. I don't 2446 * know what the numbers do, I'm just the messenger. 2447 */ 2448 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2449 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2450 while (bhack[i].reg) { 2451 sk_xmac_miibus_writereg((struct device *)sc_if, 2452 SK_PHYADDR_BCOM, bhack[i].reg, 2453 bhack[i].val); 2454 i++; 2455 } 2456 } 2457 } 2458 2459 /* Set station address */ 2460 SK_XM_WRITE_2(sc_if, XM_PAR0, 2461 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2462 SK_XM_WRITE_2(sc_if, XM_PAR1, 2463 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2464 SK_XM_WRITE_2(sc_if, XM_PAR2, 2465 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2466 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2467 2468 if (ifp->if_flags & IFF_PROMISC) 2469 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2470 else 2471 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2472 2473 if (ifp->if_flags & IFF_BROADCAST) 2474 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2475 else 2476 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2477 2478 /* We don't need the FCS appended to the packet. */ 2479 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2480 2481 /* We want short frames padded to 60 bytes. */ 2482 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2483 2484 /* 2485 * Enable the reception of all error frames. This is is 2486 * a necessary evil due to the design of the XMAC. The 2487 * XMAC's receive FIFO is only 8K in size, however jumbo 2488 * frames can be up to 9000 bytes in length. When bad 2489 * frame filtering is enabled, the XMAC's RX FIFO operates 2490 * in 'store and forward' mode. For this to work, the 2491 * entire frame has to fit into the FIFO, but that means 2492 * that jumbo frames larger than 8192 bytes will be 2493 * truncated. Disabling all bad frame filtering causes 2494 * the RX FIFO to operate in streaming mode, in which 2495 * case the XMAC will start transfering frames out of the 2496 * RX FIFO as soon as the FIFO threshold is reached. 2497 */ 2498 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2499 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2500 XM_MODE_RX_INRANGELEN); 2501 2502 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2503 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2504 else 2505 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2506 2507 /* 2508 * Bump up the transmit threshold. This helps hold off transmit 2509 * underruns when we're blasting traffic from both ports at once. 2510 */ 2511 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2512 2513 /* Set multicast filter */ 2514 sk_setmulti(sc_if); 2515 2516 /* Clear and enable interrupts */ 2517 SK_XM_READ_2(sc_if, XM_ISR); 2518 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2519 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2520 else 2521 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2522 2523 /* Configure MAC arbiter */ 2524 switch (sc_if->sk_xmac_rev) { 2525 case XM_XMAC_REV_B2: 2526 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2527 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2528 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2529 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2530 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2531 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2532 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2533 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2534 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2535 break; 2536 case XM_XMAC_REV_C1: 2537 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2538 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2539 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2540 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2541 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2542 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2543 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2544 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2545 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2546 break; 2547 default: 2548 break; 2549 } 2550 sk_win_write_2(sc, SK_MACARB_CTL, 2551 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2552 2553 sc_if->sk_link = 1; 2554 } 2555 2556 void sk_init_yukon(struct sk_if_softc *sc_if) 2557 { 2558 u_int32_t /*mac, */phy; 2559 u_int16_t reg; 2560 struct sk_softc *sc; 2561 int i; 2562 2563 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2564 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2565 2566 sc = sc_if->sk_softc; 2567 if (sc->sk_type == SK_YUKON_LITE && 2568 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2569 /* Take PHY out of reset. */ 2570 sk_win_write_4(sc, SK_GPIO, 2571 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2572 } 2573 2574 2575 /* GMAC and GPHY Reset */ 2576 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2577 2578 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2579 2580 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2581 DELAY(1000); 2582 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2583 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2584 DELAY(1000); 2585 2586 2587 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2588 2589 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2590 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2591 2592 switch (sc_if->sk_softc->sk_pmd) { 2593 case IFM_1000_SX: 2594 case IFM_1000_LX: 2595 phy |= SK_GPHY_FIBER; 2596 break; 2597 2598 case IFM_1000_CX: 2599 case IFM_1000_T: 2600 phy |= SK_GPHY_COPPER; 2601 break; 2602 } 2603 2604 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2605 2606 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2607 DELAY(1000); 2608 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2609 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2610 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2611 2612 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2613 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2614 2615 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2616 2617 /* unused read of the interrupt source register */ 2618 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2619 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2620 2621 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2622 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2623 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2624 2625 /* MIB Counter Clear Mode set */ 2626 reg |= YU_PAR_MIB_CLR; 2627 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2628 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2629 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2630 2631 /* MIB Counter Clear Mode clear */ 2632 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2633 reg &= ~YU_PAR_MIB_CLR; 2634 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2635 2636 /* receive control reg */ 2637 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2638 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2639 YU_RCR_CRCR); 2640 2641 /* transmit parameter register */ 2642 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2643 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2644 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2645 2646 /* serial mode register */ 2647 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2648 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2649 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2650 YU_SMR_IPG_DATA(0x1e)); 2651 2652 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2653 /* Setup Yukon's address */ 2654 for (i = 0; i < 3; i++) { 2655 /* Write Source Address 1 (unicast filter) */ 2656 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2657 sc_if->sk_enaddr[i * 2] | 2658 sc_if->sk_enaddr[i * 2 + 1] << 8); 2659 } 2660 2661 for (i = 0; i < 3; i++) { 2662 reg = sk_win_read_2(sc_if->sk_softc, 2663 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2664 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2665 } 2666 2667 /* Set multicast filter */ 2668 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2669 sk_setmulti(sc_if); 2670 2671 /* enable interrupt mask for counter overflows */ 2672 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2673 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2674 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2675 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2676 2677 /* Configure RX MAC FIFO */ 2678 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2679 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2680 2681 /* Configure TX MAC FIFO */ 2682 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2683 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2684 2685 DPRINTFN(6, ("sk_init_yukon: end\n")); 2686 } 2687 2688 /* 2689 * Note that to properly initialize any part of the GEnesis chip, 2690 * you first have to take it out of reset mode. 2691 */ 2692 int 2693 sk_init(struct ifnet *ifp) 2694 { 2695 struct sk_if_softc *sc_if = ifp->if_softc; 2696 struct sk_softc *sc = sc_if->sk_softc; 2697 struct mii_data *mii = &sc_if->sk_mii; 2698 int s; 2699 u_int32_t imr, sk_imtimer_ticks; 2700 2701 DPRINTFN(1, ("sk_init\n")); 2702 2703 s = splnet(); 2704 2705 if (ifp->if_flags & IFF_RUNNING) { 2706 splx(s); 2707 return 0; 2708 } 2709 2710 /* Cancel pending I/O and free all RX/TX buffers. */ 2711 sk_stop(ifp,0); 2712 2713 if (sc->sk_type == SK_GENESIS) { 2714 /* Configure LINK_SYNC LED */ 2715 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2716 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2717 SK_LINKLED_LINKSYNC_ON); 2718 2719 /* Configure RX LED */ 2720 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2721 SK_RXLEDCTL_COUNTER_START); 2722 2723 /* Configure TX LED */ 2724 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2725 SK_TXLEDCTL_COUNTER_START); 2726 } 2727 2728 /* Configure I2C registers */ 2729 2730 /* Configure XMAC(s) */ 2731 switch (sc->sk_type) { 2732 case SK_GENESIS: 2733 sk_init_xmac(sc_if); 2734 break; 2735 case SK_YUKON: 2736 case SK_YUKON_LITE: 2737 case SK_YUKON_LP: 2738 sk_init_yukon(sc_if); 2739 break; 2740 } 2741 mii_mediachg(mii); 2742 2743 if (sc->sk_type == SK_GENESIS) { 2744 /* Configure MAC FIFOs */ 2745 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2746 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2747 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2748 2749 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2750 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2751 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2752 } 2753 2754 /* Configure transmit arbiter(s) */ 2755 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2756 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2757 2758 /* Configure RAMbuffers */ 2759 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2760 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2761 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2762 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2763 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2764 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2765 2766 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2767 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2768 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2769 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2770 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2771 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2772 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2773 2774 /* Configure BMUs */ 2775 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2776 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2777 SK_RX_RING_ADDR(sc_if, 0)); 2778 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2779 2780 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2781 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2782 SK_TX_RING_ADDR(sc_if, 0)); 2783 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2784 2785 /* Init descriptors */ 2786 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2787 aprint_error("%s: initialization failed: no " 2788 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2789 sk_stop(ifp,0); 2790 splx(s); 2791 return ENOBUFS; 2792 } 2793 2794 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2795 aprint_error("%s: initialization failed: no " 2796 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2797 sk_stop(ifp,0); 2798 splx(s); 2799 return ENOBUFS; 2800 } 2801 2802 /* Set interrupt moderation if changed via sysctl. */ 2803 switch (sc->sk_type) { 2804 case SK_GENESIS: 2805 sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2806 break; 2807 case SK_YUKON_EC: 2808 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2809 break; 2810 default: 2811 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2812 } 2813 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2814 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2815 sk_win_write_4(sc, SK_IMTIMERINIT, 2816 SK_IM_USECS(sc->sk_int_mod)); 2817 aprint_verbose("%s: interrupt moderation is %d us\n", 2818 sc->sk_dev.dv_xname, sc->sk_int_mod); 2819 } 2820 2821 /* Configure interrupt handling */ 2822 CSR_READ_4(sc, SK_ISSR); 2823 if (sc_if->sk_port == SK_PORT_A) 2824 sc->sk_intrmask |= SK_INTRS1; 2825 else 2826 sc->sk_intrmask |= SK_INTRS2; 2827 2828 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2829 2830 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2831 2832 /* Start BMUs. */ 2833 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2834 2835 if (sc->sk_type == SK_GENESIS) { 2836 /* Enable XMACs TX and RX state machines */ 2837 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2838 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2839 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2840 } 2841 2842 if (SK_YUKON_FAMILY(sc->sk_type)) { 2843 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2844 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2845 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2846 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2847 } 2848 2849 2850 ifp->if_flags |= IFF_RUNNING; 2851 ifp->if_flags &= ~IFF_OACTIVE; 2852 2853 splx(s); 2854 return 0; 2855 } 2856 2857 void 2858 sk_stop(struct ifnet *ifp, int disable) 2859 { 2860 struct sk_if_softc *sc_if = ifp->if_softc; 2861 struct sk_softc *sc = sc_if->sk_softc; 2862 int i; 2863 2864 DPRINTFN(1, ("sk_stop\n")); 2865 2866 callout_stop(&sc_if->sk_tick_ch); 2867 2868 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2869 u_int32_t val; 2870 2871 /* Put PHY back into reset. */ 2872 val = sk_win_read_4(sc, SK_GPIO); 2873 if (sc_if->sk_port == SK_PORT_A) { 2874 val |= SK_GPIO_DIR0; 2875 val &= ~SK_GPIO_DAT0; 2876 } else { 2877 val |= SK_GPIO_DIR2; 2878 val &= ~SK_GPIO_DAT2; 2879 } 2880 sk_win_write_4(sc, SK_GPIO, val); 2881 } 2882 2883 /* Turn off various components of this interface. */ 2884 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2885 switch (sc->sk_type) { 2886 case SK_GENESIS: 2887 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2888 SK_TXMACCTL_XMAC_RESET); 2889 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2890 break; 2891 case SK_YUKON: 2892 case SK_YUKON_LITE: 2893 case SK_YUKON_LP: 2894 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2895 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2896 break; 2897 } 2898 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2899 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2900 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2901 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2902 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2903 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2904 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2905 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2906 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2907 2908 /* Disable interrupts */ 2909 if (sc_if->sk_port == SK_PORT_A) 2910 sc->sk_intrmask &= ~SK_INTRS1; 2911 else 2912 sc->sk_intrmask &= ~SK_INTRS2; 2913 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2914 2915 SK_XM_READ_2(sc_if, XM_ISR); 2916 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2917 2918 /* Free RX and TX mbufs still in the queues. */ 2919 for (i = 0; i < SK_RX_RING_CNT; i++) { 2920 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2921 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2922 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2923 } 2924 } 2925 2926 for (i = 0; i < SK_TX_RING_CNT; i++) { 2927 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2928 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2929 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2930 } 2931 } 2932 2933 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2934 } 2935 2936 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2937 2938 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2939 2940 #ifdef SK_DEBUG 2941 void 2942 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2943 { 2944 #define DESC_PRINT(X) \ 2945 if (X) \ 2946 printf("txdesc[%d]." #X "=%#x\n", \ 2947 idx, X); 2948 2949 DESC_PRINT(le32toh(desc->sk_ctl)); 2950 DESC_PRINT(le32toh(desc->sk_next)); 2951 DESC_PRINT(le32toh(desc->sk_data_lo)); 2952 DESC_PRINT(le32toh(desc->sk_data_hi)); 2953 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2954 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2955 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2956 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2957 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2958 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2959 #undef PRINT 2960 } 2961 2962 void 2963 sk_dump_bytes(const char *data, int len) 2964 { 2965 int c, i, j; 2966 2967 for (i = 0; i < len; i += 16) { 2968 printf("%08x ", i); 2969 c = len - i; 2970 if (c > 16) c = 16; 2971 2972 for (j = 0; j < c; j++) { 2973 printf("%02x ", data[i + j] & 0xff); 2974 if ((j & 0xf) == 7 && j > 0) 2975 printf(" "); 2976 } 2977 2978 for (; j < 16; j++) 2979 printf(" "); 2980 printf(" "); 2981 2982 for (j = 0; j < c; j++) { 2983 int ch = data[i + j] & 0xff; 2984 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2985 } 2986 2987 printf("\n"); 2988 2989 if (c < 16) 2990 break; 2991 } 2992 } 2993 2994 void 2995 sk_dump_mbuf(struct mbuf *m) 2996 { 2997 int count = m->m_pkthdr.len; 2998 2999 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3000 3001 while (count > 0 && m) { 3002 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3003 m, m->m_data, m->m_len); 3004 sk_dump_bytes(mtod(m, char *), m->m_len); 3005 3006 count -= m->m_len; 3007 m = m->m_next; 3008 } 3009 } 3010 #endif 3011 3012 static int 3013 sk_sysctl_handler(SYSCTLFN_ARGS) 3014 { 3015 int error, t; 3016 struct sysctlnode node; 3017 struct sk_softc *sc; 3018 3019 node = *rnode; 3020 sc = node.sysctl_data; 3021 t = sc->sk_int_mod; 3022 node.sysctl_data = &t; 3023 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3024 if (error || newp == NULL) 3025 return error; 3026 3027 if (t < SK_IM_MIN || t > SK_IM_MAX) 3028 return EINVAL; 3029 3030 /* update the softc with sysctl-changed value, and mark 3031 for hardware update */ 3032 sc->sk_int_mod = t; 3033 sc->sk_int_mod_pending = 1; 3034 return 0; 3035 } 3036 3037 /* 3038 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3039 * set up in skc_attach() 3040 */ 3041 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3042 { 3043 int rc; 3044 const struct sysctlnode *node; 3045 3046 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3047 0, CTLTYPE_NODE, "hw", NULL, 3048 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3049 goto err; 3050 } 3051 3052 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3053 0, CTLTYPE_NODE, "sk", 3054 SYSCTL_DESCR("sk interface controls"), 3055 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3056 goto err; 3057 } 3058 3059 sk_root_num = node->sysctl_num; 3060 return; 3061 3062 err: 3063 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3064 } 3065
Indexes created Mon Oct 13 15:10:03 GMT 2025