if_sk.c revision 1.22
1 /* $NetBSD: if_sk.c,v 1.22 2006/03/28 18:29:42 riz Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 #include "rnd.h" 126 127 #include <sys/param.h> 128 #include <sys/systm.h> 129 #include <sys/sockio.h> 130 #include <sys/mbuf.h> 131 #include <sys/malloc.h> 132 #include <sys/kernel.h> 133 #include <sys/socket.h> 134 #include <sys/device.h> 135 #include <sys/queue.h> 136 #include <sys/callout.h> 137 #include <sys/sysctl.h> 138 139 #include <net/if.h> 140 #include <net/if_dl.h> 141 #include <net/if_types.h> 142 143 #ifdef INET 144 #include <netinet/in.h> 145 #include <netinet/in_systm.h> 146 #include <netinet/in_var.h> 147 #include <netinet/ip.h> 148 #include <netinet/if_ether.h> 149 #endif 150 151 #include <net/if_media.h> 152 153 #if NBPFILTER > 0 154 #include <net/bpf.h> 155 #endif 156 #if NRND > 0 157 #include <sys/rnd.h> 158 #endif 159 160 #include <dev/mii/mii.h> 161 #include <dev/mii/miivar.h> 162 #include <dev/mii/brgphyreg.h> 163 164 #include <dev/pci/pcireg.h> 165 #include <dev/pci/pcivar.h> 166 #include <dev/pci/pcidevs.h> 167 168 #define SK_VERBOSE 169 /* #define SK_USEIOSPACE */ 170 171 #include <dev/pci/if_skreg.h> 172 #include <dev/pci/if_skvar.h> 173 174 int skc_probe(struct device *, struct cfdata *, void *); 175 void skc_attach(struct device *, struct device *self, void *aux); 176 int sk_probe(struct device *, struct cfdata *, void *); 177 void sk_attach(struct device *, struct device *self, void *aux); 178 int skcprint(void *, const char *); 179 int sk_intr(void *); 180 void sk_intr_bcom(struct sk_if_softc *); 181 void sk_intr_xmac(struct sk_if_softc *); 182 void sk_intr_yukon(struct sk_if_softc *); 183 void sk_rxeof(struct sk_if_softc *); 184 void sk_txeof(struct sk_if_softc *); 185 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 186 void sk_start(struct ifnet *); 187 int sk_ioctl(struct ifnet *, u_long, caddr_t); 188 int sk_init(struct ifnet *); 189 void sk_init_xmac(struct sk_if_softc *); 190 void sk_init_yukon(struct sk_if_softc *); 191 void sk_stop(struct ifnet *, int); 192 void sk_watchdog(struct ifnet *); 193 void sk_shutdown(void *); 194 int sk_ifmedia_upd(struct ifnet *); 195 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 196 void sk_reset(struct sk_softc *); 197 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 198 int sk_alloc_jumbo_mem(struct sk_if_softc *); 199 void sk_free_jumbo_mem(struct sk_if_softc *); 200 void *sk_jalloc(struct sk_if_softc *); 201 void sk_jfree(struct mbuf *, caddr_t, size_t, void *); 202 int sk_init_rx_ring(struct sk_if_softc *); 203 int sk_init_tx_ring(struct sk_if_softc *); 204 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 205 void sk_vpd_read_res(struct sk_softc *, 206 struct vpd_res *, int); 207 void sk_vpd_read(struct sk_softc *); 208 209 void sk_update_int_mod(struct sk_softc *); 210 211 int sk_xmac_miibus_readreg(struct device *, int, int); 212 void sk_xmac_miibus_writereg(struct device *, int, int, int); 213 void sk_xmac_miibus_statchg(struct device *); 214 215 int sk_marv_miibus_readreg(struct device *, int, int); 216 void sk_marv_miibus_writereg(struct device *, int, int, int); 217 void sk_marv_miibus_statchg(struct device *); 218 219 u_int32_t sk_xmac_hash(caddr_t); 220 u_int32_t sk_yukon_hash(caddr_t); 221 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 222 void sk_setmulti(struct sk_if_softc *); 223 void sk_tick(void *); 224 225 /* #define SK_DEBUG 2 */ 226 #ifdef SK_DEBUG 227 #define DPRINTF(x) if (skdebug) printf x 228 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 229 int skdebug = SK_DEBUG; 230 231 void sk_dump_txdesc(struct sk_tx_desc *, int); 232 void sk_dump_mbuf(struct mbuf *); 233 void sk_dump_bytes(const char *, int); 234 #else 235 #define DPRINTF(x) 236 #define DPRINTFN(n,x) 237 #endif 238 239 #define SK_SETBIT(sc, reg, x) \ 240 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 241 242 #define SK_CLRBIT(sc, reg, x) \ 243 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 244 245 #define SK_WIN_SETBIT_4(sc, reg, x) \ 246 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 247 248 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 249 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 250 251 #define SK_WIN_SETBIT_2(sc, reg, x) \ 252 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 253 254 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 255 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 256 257 static int sk_sysctl_handler(SYSCTLFN_PROTO); 258 static int sk_root_num; 259 260 /* supported device vendors */ 261 static const struct sk_product { 262 pci_vendor_id_t sk_vendor; 263 pci_product_id_t sk_product; 264 } sk_products[] = { 265 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 266 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 267 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 268 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 269 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 270 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_SKNET, }, 271 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_BELKIN, }, 272 { 0, 0, } 273 }; 274 275 #define SK_LINKSYS_EG1032_SUBID 0x00151737 276 277 static inline u_int32_t 278 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 279 { 280 #ifdef SK_USEIOSPACE 281 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 282 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 283 #else 284 return CSR_READ_4(sc, reg); 285 #endif 286 } 287 288 static inline u_int16_t 289 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 290 { 291 #ifdef SK_USEIOSPACE 292 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 293 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 294 #else 295 return CSR_READ_2(sc, reg); 296 #endif 297 } 298 299 static inline u_int8_t 300 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 301 { 302 #ifdef SK_USEIOSPACE 303 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 304 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 305 #else 306 return CSR_READ_1(sc, reg); 307 #endif 308 } 309 310 static inline void 311 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 312 { 313 #ifdef SK_USEIOSPACE 314 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 315 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 316 #else 317 CSR_WRITE_4(sc, reg, x); 318 #endif 319 } 320 321 static inline void 322 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 323 { 324 #ifdef SK_USEIOSPACE 325 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 326 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 327 #else 328 CSR_WRITE_2(sc, reg, x); 329 #endif 330 } 331 332 static inline void 333 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 334 { 335 #ifdef SK_USEIOSPACE 336 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 337 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 338 #else 339 CSR_WRITE_1(sc, reg, x); 340 #endif 341 } 342 343 /* 344 * The VPD EEPROM contains Vital Product Data, as suggested in 345 * the PCI 2.1 specification. The VPD data is separared into areas 346 * denoted by resource IDs. The SysKonnect VPD contains an ID string 347 * resource (the name of the adapter), a read-only area resource 348 * containing various key/data fields and a read/write area which 349 * can be used to store asset management information or log messages. 350 * We read the ID string and read-only into buffers attached to 351 * the controller softc structure for later use. At the moment, 352 * we only use the ID string during sk_attach(). 353 */ 354 u_int8_t 355 sk_vpd_readbyte(struct sk_softc *sc, int addr) 356 { 357 int i; 358 359 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 360 for (i = 0; i < SK_TIMEOUT; i++) { 361 DELAY(1); 362 if (sk_win_read_2(sc, 363 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 364 break; 365 } 366 367 if (i == SK_TIMEOUT) 368 return(0); 369 370 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 371 } 372 373 void 374 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 375 { 376 int i; 377 u_int8_t *ptr; 378 379 ptr = (u_int8_t *)res; 380 for (i = 0; i < sizeof(struct vpd_res); i++) 381 ptr[i] = sk_vpd_readbyte(sc, i + addr); 382 } 383 384 void 385 sk_vpd_read(struct sk_softc *sc) 386 { 387 int pos = 0, i; 388 struct vpd_res res; 389 390 if (sc->sk_vpd_prodname != NULL) 391 free(sc->sk_vpd_prodname, M_DEVBUF); 392 if (sc->sk_vpd_readonly != NULL) 393 free(sc->sk_vpd_readonly, M_DEVBUF); 394 sc->sk_vpd_prodname = NULL; 395 sc->sk_vpd_readonly = NULL; 396 397 sk_vpd_read_res(sc, &res, pos); 398 399 if (res.vr_id != VPD_RES_ID) { 400 printf("%s: bad VPD resource id: expected %x got %x\n", 401 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 402 return; 403 } 404 405 pos += sizeof(res); 406 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 407 if (sc->sk_vpd_prodname == NULL) 408 panic("sk_vpd_read"); 409 for (i = 0; i < res.vr_len; i++) 410 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 411 sc->sk_vpd_prodname[i] = '\0'; 412 pos += i; 413 414 sk_vpd_read_res(sc, &res, pos); 415 416 if (res.vr_id != VPD_RES_READ) { 417 printf("%s: bad VPD resource id: expected %x got %x\n", 418 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 419 return; 420 } 421 422 pos += sizeof(res); 423 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 424 if (sc->sk_vpd_readonly == NULL) 425 panic("sk_vpd_read"); 426 for (i = 0; i < res.vr_len ; i++) 427 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 428 } 429 430 int 431 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 432 { 433 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 434 int i; 435 436 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 437 438 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 439 return(0); 440 441 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 442 SK_XM_READ_2(sc_if, XM_PHY_DATA); 443 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 444 for (i = 0; i < SK_TIMEOUT; i++) { 445 DELAY(1); 446 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 447 XM_MMUCMD_PHYDATARDY) 448 break; 449 } 450 451 if (i == SK_TIMEOUT) { 452 printf("%s: phy failed to come ready\n", 453 sc_if->sk_dev.dv_xname); 454 return(0); 455 } 456 } 457 DELAY(1); 458 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 459 } 460 461 void 462 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 463 { 464 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 465 int i; 466 467 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 468 469 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 470 for (i = 0; i < SK_TIMEOUT; i++) { 471 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 472 break; 473 } 474 475 if (i == SK_TIMEOUT) { 476 printf("%s: phy failed to come ready\n", 477 sc_if->sk_dev.dv_xname); 478 return; 479 } 480 481 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 482 for (i = 0; i < SK_TIMEOUT; i++) { 483 DELAY(1); 484 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 485 break; 486 } 487 488 if (i == SK_TIMEOUT) 489 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 490 } 491 492 void 493 sk_xmac_miibus_statchg(struct device *dev) 494 { 495 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 496 struct mii_data *mii = &sc_if->sk_mii; 497 498 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 499 500 /* 501 * If this is a GMII PHY, manually set the XMAC's 502 * duplex mode accordingly. 503 */ 504 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 505 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 506 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 507 } else { 508 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 509 } 510 } 511 } 512 513 int 514 sk_marv_miibus_readreg(dev, phy, reg) 515 struct device *dev; 516 int phy, reg; 517 { 518 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 519 u_int16_t val; 520 int i; 521 522 if (phy != 0 || 523 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 524 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 525 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 526 phy, reg)); 527 return(0); 528 } 529 530 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 531 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 532 533 for (i = 0; i < SK_TIMEOUT; i++) { 534 DELAY(1); 535 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 536 if (val & YU_SMICR_READ_VALID) 537 break; 538 } 539 540 if (i == SK_TIMEOUT) { 541 printf("%s: phy failed to come ready\n", 542 sc_if->sk_dev.dv_xname); 543 return 0; 544 } 545 546 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 547 SK_TIMEOUT)); 548 549 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 550 551 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 552 phy, reg, val)); 553 554 return val; 555 } 556 557 void 558 sk_marv_miibus_writereg(dev, phy, reg, val) 559 struct device *dev; 560 int phy, reg, val; 561 { 562 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 563 int i; 564 565 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 566 phy, reg, val)); 567 568 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 569 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 570 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 571 572 for (i = 0; i < SK_TIMEOUT; i++) { 573 DELAY(1); 574 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 575 break; 576 } 577 } 578 579 void 580 sk_marv_miibus_statchg(dev) 581 struct device *dev; 582 { 583 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 584 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 585 } 586 587 #define SK_HASH_BITS 6 588 589 u_int32_t 590 sk_xmac_hash(caddr_t addr) 591 { 592 u_int32_t crc; 593 594 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 595 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 596 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 597 return (crc); 598 } 599 600 u_int32_t 601 sk_yukon_hash(caddr_t addr) 602 { 603 u_int32_t crc; 604 605 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 606 crc &= ((1 << SK_HASH_BITS) - 1); 607 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 608 return (crc); 609 } 610 611 void 612 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 613 { 614 int base = XM_RXFILT_ENTRY(slot); 615 616 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 617 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 618 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 619 } 620 621 void 622 sk_setmulti(struct sk_if_softc *sc_if) 623 { 624 struct sk_softc *sc = sc_if->sk_softc; 625 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 626 u_int32_t hashes[2] = { 0, 0 }; 627 int h = 0, i; 628 struct ethercom *ec = &sc_if->sk_ethercom; 629 struct ether_multi *enm; 630 struct ether_multistep step; 631 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 632 633 /* First, zot all the existing filters. */ 634 switch(sc->sk_type) { 635 case SK_GENESIS: 636 for (i = 1; i < XM_RXFILT_MAX; i++) 637 sk_setfilt(sc_if, (caddr_t)&dummy, i); 638 639 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 640 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 641 break; 642 case SK_YUKON: 643 case SK_YUKON_LITE: 644 case SK_YUKON_LP: 645 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 646 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 647 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 648 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 649 break; 650 } 651 652 /* Now program new ones. */ 653 allmulti: 654 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 655 hashes[0] = 0xFFFFFFFF; 656 hashes[1] = 0xFFFFFFFF; 657 } else { 658 i = 1; 659 /* First find the tail of the list. */ 660 ETHER_FIRST_MULTI(step, ec, enm); 661 while (enm != NULL) { 662 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 663 ETHER_ADDR_LEN)) { 664 ifp->if_flags |= IFF_ALLMULTI; 665 goto allmulti; 666 } 667 DPRINTFN(2,("multicast address %s\n", 668 ether_sprintf(enm->enm_addrlo))); 669 /* 670 * Program the first XM_RXFILT_MAX multicast groups 671 * into the perfect filter. For all others, 672 * use the hash table. 673 */ 674 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 675 sk_setfilt(sc_if, enm->enm_addrlo, i); 676 i++; 677 } 678 else { 679 switch (sc->sk_type) { 680 case SK_GENESIS: 681 h = sk_xmac_hash(enm->enm_addrlo); 682 break; 683 case SK_YUKON: 684 case SK_YUKON_LITE: 685 case SK_YUKON_LP: 686 h = sk_yukon_hash(enm->enm_addrlo); 687 break; 688 } 689 if (h < 32) 690 hashes[0] |= (1 << h); 691 else 692 hashes[1] |= (1 << (h - 32)); 693 } 694 695 ETHER_NEXT_MULTI(step, enm); 696 } 697 } 698 699 switch(sc->sk_type) { 700 case SK_GENESIS: 701 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 702 XM_MODE_RX_USE_PERFECT); 703 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 704 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 705 break; 706 case SK_YUKON: 707 case SK_YUKON_LITE: 708 case SK_YUKON_LP: 709 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 710 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 711 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 712 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 713 break; 714 } 715 } 716 717 int 718 sk_init_rx_ring(struct sk_if_softc *sc_if) 719 { 720 struct sk_chain_data *cd = &sc_if->sk_cdata; 721 struct sk_ring_data *rd = sc_if->sk_rdata; 722 int i; 723 724 bzero((char *)rd->sk_rx_ring, 725 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 726 727 for (i = 0; i < SK_RX_RING_CNT; i++) { 728 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 729 if (i == (SK_RX_RING_CNT - 1)) { 730 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 731 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 732 } else { 733 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 734 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 735 } 736 } 737 738 for (i = 0; i < SK_RX_RING_CNT; i++) { 739 if (sk_newbuf(sc_if, i, NULL, 740 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 741 printf("%s: failed alloc of %dth mbuf\n", 742 sc_if->sk_dev.dv_xname, i); 743 return(ENOBUFS); 744 } 745 } 746 sc_if->sk_cdata.sk_rx_prod = 0; 747 sc_if->sk_cdata.sk_rx_cons = 0; 748 749 return(0); 750 } 751 752 int 753 sk_init_tx_ring(struct sk_if_softc *sc_if) 754 { 755 struct sk_chain_data *cd = &sc_if->sk_cdata; 756 struct sk_ring_data *rd = sc_if->sk_rdata; 757 int i; 758 759 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 760 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 761 762 for (i = 0; i < SK_TX_RING_CNT; i++) { 763 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 764 if (i == (SK_TX_RING_CNT - 1)) { 765 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 766 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 767 } else { 768 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 769 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 770 } 771 } 772 773 sc_if->sk_cdata.sk_tx_prod = 0; 774 sc_if->sk_cdata.sk_tx_cons = 0; 775 sc_if->sk_cdata.sk_tx_cnt = 0; 776 777 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 778 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 779 780 return (0); 781 } 782 783 int 784 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 785 bus_dmamap_t dmamap) 786 { 787 struct mbuf *m_new = NULL; 788 struct sk_chain *c; 789 struct sk_rx_desc *r; 790 791 if (m == NULL) { 792 caddr_t buf = NULL; 793 794 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 795 if (m_new == NULL) { 796 printf("%s: no memory for rx list -- " 797 "packet dropped!\n", sc_if->sk_dev.dv_xname); 798 return(ENOBUFS); 799 } 800 801 /* Allocate the jumbo buffer */ 802 buf = sk_jalloc(sc_if); 803 if (buf == NULL) { 804 m_freem(m_new); 805 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 806 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 807 return(ENOBUFS); 808 } 809 810 /* Attach the buffer to the mbuf */ 811 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 812 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 813 814 } else { 815 /* 816 * We're re-using a previously allocated mbuf; 817 * be sure to re-init pointers and lengths to 818 * default values. 819 */ 820 m_new = m; 821 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 822 m_new->m_data = m_new->m_ext.ext_buf; 823 } 824 m_adj(m_new, ETHER_ALIGN); 825 826 c = &sc_if->sk_cdata.sk_rx_chain[i]; 827 r = c->sk_desc; 828 c->sk_mbuf = m_new; 829 r->sk_data_lo = dmamap->dm_segs[0].ds_addr + 830 (((vaddr_t)m_new->m_data 831 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf)); 832 r->sk_ctl = SK_JLEN | SK_RXSTAT; 833 834 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 835 836 return(0); 837 } 838 839 /* 840 * Memory management for jumbo frames. 841 */ 842 843 int 844 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 845 { 846 struct sk_softc *sc = sc_if->sk_softc; 847 caddr_t ptr, kva; 848 bus_dma_segment_t seg; 849 int i, rseg, state, error; 850 struct sk_jpool_entry *entry; 851 852 state = error = 0; 853 854 /* Grab a big chunk o' storage. */ 855 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 856 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 857 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 858 return (ENOBUFS); 859 } 860 861 state = 1; 862 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, &kva, 863 BUS_DMA_NOWAIT)) { 864 printf("%s: can't map dma buffers (%d bytes)\n", 865 sc->sk_dev.dv_xname, SK_JMEM); 866 error = ENOBUFS; 867 goto out; 868 } 869 870 state = 2; 871 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 872 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 873 printf("%s: can't create dma map\n", sc->sk_dev.dv_xname); 874 error = ENOBUFS; 875 goto out; 876 } 877 878 state = 3; 879 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 880 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 881 printf("%s: can't load dma map\n", sc->sk_dev.dv_xname); 882 error = ENOBUFS; 883 goto out; 884 } 885 886 state = 4; 887 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 888 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 889 890 LIST_INIT(&sc_if->sk_jfree_listhead); 891 LIST_INIT(&sc_if->sk_jinuse_listhead); 892 893 /* 894 * Now divide it up into 9K pieces and save the addresses 895 * in an array. 896 */ 897 ptr = sc_if->sk_cdata.sk_jumbo_buf; 898 for (i = 0; i < SK_JSLOTS; i++) { 899 sc_if->sk_cdata.sk_jslots[i] = ptr; 900 ptr += SK_JLEN; 901 entry = malloc(sizeof(struct sk_jpool_entry), 902 M_DEVBUF, M_NOWAIT); 903 if (entry == NULL) { 904 printf("%s: no memory for jumbo buffer queue!\n", 905 sc->sk_dev.dv_xname); 906 error = ENOBUFS; 907 goto out; 908 } 909 entry->slot = i; 910 if (i) 911 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 912 entry, jpool_entries); 913 else 914 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 915 entry, jpool_entries); 916 } 917 out: 918 if (error != 0) { 919 switch (state) { 920 case 4: 921 bus_dmamap_unload(sc->sc_dmatag, 922 sc_if->sk_cdata.sk_rx_jumbo_map); 923 case 3: 924 bus_dmamap_destroy(sc->sc_dmatag, 925 sc_if->sk_cdata.sk_rx_jumbo_map); 926 case 2: 927 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 928 case 1: 929 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 930 break; 931 default: 932 break; 933 } 934 } 935 936 return (error); 937 } 938 939 /* 940 * Allocate a jumbo buffer. 941 */ 942 void * 943 sk_jalloc(struct sk_if_softc *sc_if) 944 { 945 struct sk_jpool_entry *entry; 946 947 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 948 949 if (entry == NULL) 950 return (NULL); 951 952 LIST_REMOVE(entry, jpool_entries); 953 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 954 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 955 } 956 957 /* 958 * Release a jumbo buffer. 959 */ 960 void 961 sk_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 962 { 963 struct sk_jpool_entry *entry; 964 struct sk_if_softc *sc; 965 int i, s; 966 967 /* Extract the softc struct pointer. */ 968 sc = (struct sk_if_softc *)arg; 969 970 if (sc == NULL) 971 panic("sk_jfree: can't find softc pointer!"); 972 973 /* calculate the slot this buffer belongs to */ 974 975 i = ((vaddr_t)buf 976 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 977 978 if ((i < 0) || (i >= SK_JSLOTS)) 979 panic("sk_jfree: asked to free buffer that we don't manage!"); 980 981 s = splvm(); 982 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 983 if (entry == NULL) 984 panic("sk_jfree: buffer not in use!"); 985 entry->slot = i; 986 LIST_REMOVE(entry, jpool_entries); 987 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 988 989 if (__predict_true(m != NULL)) 990 pool_cache_put(&mbpool_cache, m); 991 splx(s); 992 } 993 994 /* 995 * Set media options. 996 */ 997 int 998 sk_ifmedia_upd(struct ifnet *ifp) 999 { 1000 struct sk_if_softc *sc_if = ifp->if_softc; 1001 1002 (void) sk_init(ifp); 1003 mii_mediachg(&sc_if->sk_mii); 1004 return(0); 1005 } 1006 1007 /* 1008 * Report current media status. 1009 */ 1010 void 1011 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1012 { 1013 struct sk_if_softc *sc_if = ifp->if_softc; 1014 1015 mii_pollstat(&sc_if->sk_mii); 1016 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 1017 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 1018 } 1019 1020 int 1021 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1022 { 1023 struct sk_if_softc *sc_if = ifp->if_softc; 1024 struct sk_softc *sc = sc_if->sk_softc; 1025 struct ifreq *ifr = (struct ifreq *) data; 1026 /* struct ifaddr *ifa = (struct ifaddr *) data; */ 1027 struct mii_data *mii; 1028 int s, error = 0; 1029 1030 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1031 1032 s = splnet(); 1033 1034 switch(command) { 1035 1036 case SIOCSIFFLAGS: 1037 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1038 if (ifp->if_flags & IFF_UP) { 1039 if (ifp->if_flags & IFF_RUNNING && 1040 ifp->if_flags & IFF_PROMISC && 1041 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1042 switch(sc->sk_type) { 1043 case SK_GENESIS: 1044 SK_XM_SETBIT_4(sc_if, XM_MODE, 1045 XM_MODE_RX_PROMISC); 1046 break; 1047 case SK_YUKON: 1048 case SK_YUKON_LITE: 1049 case SK_YUKON_LP: 1050 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1051 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1052 break; 1053 } 1054 sk_setmulti(sc_if); 1055 } else if (ifp->if_flags & IFF_RUNNING && 1056 !(ifp->if_flags & IFF_PROMISC) && 1057 sc_if->sk_if_flags & IFF_PROMISC) { 1058 switch(sc->sk_type) { 1059 case SK_GENESIS: 1060 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1061 XM_MODE_RX_PROMISC); 1062 break; 1063 case SK_YUKON: 1064 case SK_YUKON_LITE: 1065 case SK_YUKON_LP: 1066 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1067 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1068 break; 1069 } 1070 1071 sk_setmulti(sc_if); 1072 } else 1073 (void) sk_init(ifp); 1074 } else { 1075 if (ifp->if_flags & IFF_RUNNING) 1076 sk_stop(ifp,0); 1077 } 1078 sc_if->sk_if_flags = ifp->if_flags; 1079 error = 0; 1080 break; 1081 1082 case SIOCGIFMEDIA: 1083 case SIOCSIFMEDIA: 1084 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 1085 mii = &sc_if->sk_mii; 1086 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1087 break; 1088 default: 1089 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1090 error = ether_ioctl(ifp, command, data); 1091 1092 if ( error == ENETRESET) { 1093 if (ifp->if_flags & IFF_RUNNING) { 1094 sk_setmulti(sc_if); 1095 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1096 } 1097 error = 0; 1098 } else if ( error ) { 1099 splx(s); 1100 return error; 1101 } 1102 break; 1103 } 1104 1105 splx(s); 1106 return(error); 1107 } 1108 1109 void 1110 sk_update_int_mod(struct sk_softc *sc) 1111 { 1112 u_int32_t sk_imtimer_ticks; 1113 1114 /* 1115 * Configure interrupt moderation. The moderation timer 1116 * defers interrupts specified in the interrupt moderation 1117 * timer mask based on the timeout specified in the interrupt 1118 * moderation timer init register. Each bit in the timer 1119 * register represents one tick, so to specify a timeout in 1120 * microseconds, we have to multiply by the correct number of 1121 * ticks-per-microsecond. 1122 */ 1123 switch (sc->sk_type) { 1124 case SK_GENESIS: 1125 sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1126 break; 1127 case SK_YUKON_EC: 1128 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1129 break; 1130 default: 1131 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1132 } 1133 aprint_verbose("%s: interrupt moderation is %d us\n", 1134 sc->sk_dev.dv_xname, sc->sk_int_mod); 1135 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1136 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1137 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1138 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1139 sc->sk_int_mod_pending = 0; 1140 } 1141 1142 /* 1143 * Lookup: Check the PCI vendor and device, and return a pointer to 1144 * The structure if the IDs match against our list. 1145 */ 1146 1147 static const struct sk_product * 1148 sk_lookup(const struct pci_attach_args *pa) 1149 { 1150 const struct sk_product *psk; 1151 1152 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1153 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1154 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1155 return (psk); 1156 } 1157 return (NULL); 1158 } 1159 1160 /* 1161 * Probe for a SysKonnect GEnesis chip. 1162 */ 1163 1164 int 1165 skc_probe(struct device *parent, struct cfdata *match, void *aux) 1166 { 1167 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1168 const struct sk_product *psk; 1169 pcireg_t subid; 1170 1171 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1172 1173 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1174 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1175 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1176 subid == SK_LINKSYS_EG1032_SUBID) 1177 return(1); 1178 1179 if ((psk = sk_lookup(pa))) { 1180 return(1); 1181 } 1182 return(0); 1183 } 1184 1185 /* 1186 * Force the GEnesis into reset, then bring it out of reset. 1187 */ 1188 void sk_reset(struct sk_softc *sc) 1189 { 1190 DPRINTFN(2, ("sk_reset\n")); 1191 1192 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1193 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1194 if (SK_YUKON_FAMILY(sc->sk_type)) 1195 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1196 1197 DELAY(1000); 1198 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1199 DELAY(2); 1200 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1201 if (SK_YUKON_FAMILY(sc->sk_type)) 1202 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1203 1204 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1205 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1206 CSR_READ_2(sc, SK_LINK_CTRL))); 1207 1208 if (sc->sk_type == SK_GENESIS) { 1209 /* Configure packet arbiter */ 1210 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1211 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1212 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1213 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1214 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1215 } 1216 1217 /* Enable RAM interface */ 1218 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1219 1220 sk_update_int_mod(sc); 1221 } 1222 1223 int 1224 sk_probe(struct device *parent, struct cfdata *match, void *aux) 1225 { 1226 struct skc_attach_args *sa = aux; 1227 1228 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1229 return(0); 1230 1231 return (1); 1232 } 1233 1234 /* 1235 * Each XMAC chip is attached as a separate logical IP interface. 1236 * Single port cards will have only one logical interface of course. 1237 */ 1238 void 1239 sk_attach(struct device *parent, struct device *self, void *aux) 1240 { 1241 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1242 struct sk_softc *sc = (struct sk_softc *)parent; 1243 struct skc_attach_args *sa = aux; 1244 struct sk_txmap_entry *entry; 1245 struct ifnet *ifp; 1246 bus_dma_segment_t seg; 1247 bus_dmamap_t dmamap; 1248 caddr_t kva; 1249 int i, rseg; 1250 1251 sc_if->sk_port = sa->skc_port; 1252 sc_if->sk_softc = sc; 1253 sc->sk_if[sa->skc_port] = sc_if; 1254 1255 if (sa->skc_port == SK_PORT_A) 1256 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1257 if (sa->skc_port == SK_PORT_B) 1258 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1259 1260 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1261 1262 /* 1263 * Get station address for this interface. Note that 1264 * dual port cards actually come with three station 1265 * addresses: one for each port, plus an extra. The 1266 * extra one is used by the SysKonnect driver software 1267 * as a 'virtual' station address for when both ports 1268 * are operating in failover mode. Currently we don't 1269 * use this extra address. 1270 */ 1271 for (i = 0; i < ETHER_ADDR_LEN; i++) 1272 sc_if->sk_enaddr[i] = 1273 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1274 1275 1276 aprint_normal(": Ethernet address %s\n", 1277 ether_sprintf(sc_if->sk_enaddr)); 1278 1279 /* 1280 * Set up RAM buffer addresses. The NIC will have a certain 1281 * amount of SRAM on it, somewhere between 512K and 2MB. We 1282 * need to divide this up a) between the transmitter and 1283 * receiver and b) between the two XMACs, if this is a 1284 * dual port NIC. Our algorithm is to divide up the memory 1285 * evenly so that everyone gets a fair share. 1286 */ 1287 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1288 u_int32_t chunk, val; 1289 1290 chunk = sc->sk_ramsize / 2; 1291 val = sc->sk_rboff / sizeof(u_int64_t); 1292 sc_if->sk_rx_ramstart = val; 1293 val += (chunk / sizeof(u_int64_t)); 1294 sc_if->sk_rx_ramend = val - 1; 1295 sc_if->sk_tx_ramstart = val; 1296 val += (chunk / sizeof(u_int64_t)); 1297 sc_if->sk_tx_ramend = val - 1; 1298 } else { 1299 u_int32_t chunk, val; 1300 1301 chunk = sc->sk_ramsize / 4; 1302 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1303 sizeof(u_int64_t); 1304 sc_if->sk_rx_ramstart = val; 1305 val += (chunk / sizeof(u_int64_t)); 1306 sc_if->sk_rx_ramend = val - 1; 1307 sc_if->sk_tx_ramstart = val; 1308 val += (chunk / sizeof(u_int64_t)); 1309 sc_if->sk_tx_ramend = val - 1; 1310 } 1311 1312 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1313 " tx_ramstart=%#x tx_ramend=%#x\n", 1314 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1315 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1316 1317 /* Read and save PHY type and set PHY address */ 1318 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1319 switch (sc_if->sk_phytype) { 1320 case SK_PHYTYPE_XMAC: 1321 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1322 break; 1323 case SK_PHYTYPE_BCOM: 1324 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1325 break; 1326 case SK_PHYTYPE_MARV_COPPER: 1327 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1328 break; 1329 default: 1330 aprint_error("%s: unsupported PHY type: %d\n", 1331 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1332 return; 1333 } 1334 1335 /* Allocate the descriptor queues. */ 1336 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1337 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1338 aprint_error("%s: can't alloc rx buffers\n", 1339 sc->sk_dev.dv_xname); 1340 goto fail; 1341 } 1342 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1343 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1344 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1345 sc_if->sk_dev.dv_xname, 1346 (u_long) sizeof(struct sk_ring_data)); 1347 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1348 goto fail; 1349 } 1350 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1351 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1352 &sc_if->sk_ring_map)) { 1353 aprint_error("%s: can't create dma map\n", 1354 sc_if->sk_dev.dv_xname); 1355 bus_dmamem_unmap(sc->sc_dmatag, kva, 1356 sizeof(struct sk_ring_data)); 1357 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1358 goto fail; 1359 } 1360 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1361 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1362 aprint_error("%s: can't load dma map\n", 1363 sc_if->sk_dev.dv_xname); 1364 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1365 bus_dmamem_unmap(sc->sc_dmatag, kva, 1366 sizeof(struct sk_ring_data)); 1367 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1368 goto fail; 1369 } 1370 1371 for (i = 0; i < SK_RX_RING_CNT; i++) 1372 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1373 1374 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1375 for (i = 0; i < SK_TX_RING_CNT; i++) { 1376 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1377 1378 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1379 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1380 aprint_error("%s: Can't create TX dmamap\n", 1381 sc_if->sk_dev.dv_xname); 1382 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1383 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1384 bus_dmamem_unmap(sc->sc_dmatag, kva, 1385 sizeof(struct sk_ring_data)); 1386 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1387 goto fail; 1388 } 1389 1390 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1391 if (!entry) { 1392 aprint_error("%s: Can't alloc txmap entry\n", 1393 sc_if->sk_dev.dv_xname); 1394 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1395 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1396 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1397 bus_dmamem_unmap(sc->sc_dmatag, kva, 1398 sizeof(struct sk_ring_data)); 1399 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1400 goto fail; 1401 } 1402 entry->dmamap = dmamap; 1403 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1404 } 1405 1406 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1407 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1408 1409 ifp = &sc_if->sk_ethercom.ec_if; 1410 /* Try to allocate memory for jumbo buffers. */ 1411 if (sk_alloc_jumbo_mem(sc_if)) { 1412 printf("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1413 goto fail; 1414 } 1415 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1416 | ETHERCAP_JUMBO_MTU; 1417 1418 ifp->if_softc = sc_if; 1419 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1420 ifp->if_ioctl = sk_ioctl; 1421 ifp->if_start = sk_start; 1422 ifp->if_stop = sk_stop; 1423 ifp->if_init = sk_init; 1424 ifp->if_watchdog = sk_watchdog; 1425 ifp->if_capabilities = 0; 1426 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1427 IFQ_SET_READY(&ifp->if_snd); 1428 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1429 1430 /* 1431 * Do miibus setup. 1432 */ 1433 switch (sc->sk_type) { 1434 case SK_GENESIS: 1435 sk_init_xmac(sc_if); 1436 break; 1437 case SK_YUKON: 1438 case SK_YUKON_LITE: 1439 case SK_YUKON_LP: 1440 sk_init_yukon(sc_if); 1441 break; 1442 default: 1443 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1444 sc->sk_type); 1445 } 1446 1447 DPRINTFN(2, ("sk_attach: 1\n")); 1448 1449 sc_if->sk_mii.mii_ifp = ifp; 1450 switch (sc->sk_type) { 1451 case SK_GENESIS: 1452 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1453 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1454 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1455 break; 1456 case SK_YUKON: 1457 case SK_YUKON_LITE: 1458 case SK_YUKON_LP: 1459 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1460 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1461 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1462 break; 1463 } 1464 1465 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1466 sk_ifmedia_upd, sk_ifmedia_sts); 1467 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1468 MII_OFFSET_ANY, 0); 1469 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1470 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1471 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1472 0, NULL); 1473 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1474 } 1475 else 1476 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1477 1478 callout_init(&sc_if->sk_tick_ch); 1479 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1480 1481 DPRINTFN(2, ("sk_attach: 1\n")); 1482 1483 /* 1484 * Call MI attach routines. 1485 */ 1486 if_attach(ifp); 1487 1488 ether_ifattach(ifp, sc_if->sk_enaddr); 1489 1490 #if NRND > 0 1491 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1492 RND_TYPE_NET, 0); 1493 #endif 1494 1495 DPRINTFN(2, ("sk_attach: end\n")); 1496 1497 return; 1498 1499 fail: 1500 sc->sk_if[sa->skc_port] = NULL; 1501 } 1502 1503 int 1504 skcprint(void *aux, const char *pnp) 1505 { 1506 struct skc_attach_args *sa = aux; 1507 1508 if (pnp) 1509 aprint_normal("sk port %c at %s", 1510 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1511 else 1512 aprint_normal(" port %c", 1513 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1514 return (UNCONF); 1515 } 1516 1517 /* 1518 * Attach the interface. Allocate softc structures, do ifmedia 1519 * setup and ethernet/BPF attach. 1520 */ 1521 void 1522 skc_attach(struct device *parent, struct device *self, void *aux) 1523 { 1524 struct sk_softc *sc = (struct sk_softc *)self; 1525 struct pci_attach_args *pa = aux; 1526 struct skc_attach_args skca; 1527 pci_chipset_tag_t pc = pa->pa_pc; 1528 pcireg_t memtype; 1529 pci_intr_handle_t ih; 1530 const char *intrstr = NULL; 1531 bus_addr_t iobase; 1532 bus_size_t iosize; 1533 int s, rc, sk_nodenum; 1534 u_int32_t command; 1535 const char *revstr; 1536 const struct sysctlnode *node; 1537 1538 DPRINTFN(2, ("begin skc_attach\n")); 1539 1540 s = splnet(); 1541 1542 /* 1543 * Handle power management nonsense. 1544 */ 1545 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1546 1547 if (command == 0x01) { 1548 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1549 if (command & SK_PSTATE_MASK) { 1550 u_int32_t xiobase, membase, irq; 1551 1552 /* Save important PCI config data. */ 1553 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1554 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1555 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1556 1557 /* Reset the power state. */ 1558 aprint_normal("%s chip is in D%d power mode " 1559 "-- setting to D0\n", sc->sk_dev.dv_xname, 1560 command & SK_PSTATE_MASK); 1561 command &= 0xFFFFFFFC; 1562 pci_conf_write(pc, pa->pa_tag, 1563 SK_PCI_PWRMGMTCTRL, command); 1564 1565 /* Restore PCI config data. */ 1566 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1567 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1568 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1569 } 1570 } 1571 1572 /* 1573 * Map control/status registers. 1574 */ 1575 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1576 command |= PCI_COMMAND_IO_ENABLE | 1577 PCI_COMMAND_MEM_ENABLE | 1578 PCI_COMMAND_MASTER_ENABLE; 1579 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1580 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1581 1582 #ifdef SK_USEIOSPACE 1583 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1584 aprint_error(": failed to enable I/O ports!\n"); 1585 goto fail; 1586 } 1587 /* 1588 * Map control/status registers. 1589 */ 1590 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1591 &iobase, &iosize)) { 1592 aprint_error(": can't find i/o space\n"); 1593 goto fail; 1594 } 1595 #else 1596 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1597 aprint_error(": failed to enable memory mapping!\n"); 1598 goto fail; 1599 } 1600 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1601 switch (memtype) { 1602 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1603 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1604 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1605 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1606 &iobase, &iosize) == 0) 1607 break; 1608 default: 1609 aprint_error("%s: can't find mem space\n", 1610 sc->sk_dev.dv_xname); 1611 return; 1612 } 1613 1614 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1615 #endif 1616 sc->sc_dmatag = pa->pa_dmat; 1617 1618 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1619 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1620 1621 /* bail out here if chip is not recognized */ 1622 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1623 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1624 goto fail; 1625 } 1626 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1627 1628 /* Allocate interrupt */ 1629 if (pci_intr_map(pa, &ih)) { 1630 aprint_error(": couldn't map interrupt\n"); 1631 goto fail; 1632 } 1633 1634 intrstr = pci_intr_string(pc, ih); 1635 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1636 if (sc->sk_intrhand == NULL) { 1637 aprint_error(": couldn't establish interrupt"); 1638 if (intrstr != NULL) 1639 aprint_normal(" at %s", intrstr); 1640 goto fail; 1641 } 1642 aprint_normal(": %s\n", intrstr); 1643 1644 /* Reset the adapter. */ 1645 sk_reset(sc); 1646 1647 /* Read and save vital product data from EEPROM. */ 1648 sk_vpd_read(sc); 1649 1650 if (sc->sk_type == SK_GENESIS) { 1651 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1652 /* Read and save RAM size and RAMbuffer offset */ 1653 switch(val) { 1654 case SK_RAMSIZE_512K_64: 1655 sc->sk_ramsize = 0x80000; 1656 sc->sk_rboff = SK_RBOFF_0; 1657 break; 1658 case SK_RAMSIZE_1024K_64: 1659 sc->sk_ramsize = 0x100000; 1660 sc->sk_rboff = SK_RBOFF_80000; 1661 break; 1662 case SK_RAMSIZE_1024K_128: 1663 sc->sk_ramsize = 0x100000; 1664 sc->sk_rboff = SK_RBOFF_0; 1665 break; 1666 case SK_RAMSIZE_2048K_128: 1667 sc->sk_ramsize = 0x200000; 1668 sc->sk_rboff = SK_RBOFF_0; 1669 break; 1670 default: 1671 aprint_error("%s: unknown ram size: %d\n", 1672 sc->sk_dev.dv_xname, val); 1673 goto fail; 1674 break; 1675 } 1676 1677 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1678 sc->sk_ramsize, sc->sk_ramsize / 1024, 1679 sc->sk_rboff)); 1680 } else { 1681 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1682 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1683 sc->sk_rboff = SK_RBOFF_0; 1684 1685 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1686 sc->sk_ramsize / 1024, sc->sk_ramsize, 1687 sc->sk_rboff)); 1688 } 1689 1690 /* Read and save physical media type */ 1691 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1692 case SK_PMD_1000BASESX: 1693 sc->sk_pmd = IFM_1000_SX; 1694 break; 1695 case SK_PMD_1000BASELX: 1696 sc->sk_pmd = IFM_1000_LX; 1697 break; 1698 case SK_PMD_1000BASECX: 1699 sc->sk_pmd = IFM_1000_CX; 1700 break; 1701 case SK_PMD_1000BASETX: 1702 sc->sk_pmd = IFM_1000_T; 1703 break; 1704 default: 1705 aprint_error("%s: unknown media type: 0x%x\n", 1706 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1707 goto fail; 1708 } 1709 1710 /* determine whether to name it with vpd or just make it up */ 1711 /* Marvell Yukon VPD's can freqently be bogus */ 1712 1713 switch (pa->pa_id) { 1714 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1715 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1716 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1717 case PCI_PRODUCT_3COM_3C940: 1718 case PCI_PRODUCT_DLINK_DGE530T: 1719 case PCI_PRODUCT_LINKSYS_EG1032: 1720 case PCI_PRODUCT_LINKSYS_EG1064: 1721 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1722 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1723 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1724 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1725 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1726 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1727 sc->sk_name = sc->sk_vpd_prodname; 1728 break; 1729 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_SKNET): 1730 /* whoops yukon vpd prodname bears no resemblance to reality */ 1731 switch (sc->sk_type) { 1732 case SK_GENESIS: 1733 sc->sk_name = sc->sk_vpd_prodname; 1734 break; 1735 case SK_YUKON: 1736 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1737 break; 1738 case SK_YUKON_LITE: 1739 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1740 break; 1741 case SK_YUKON_LP: 1742 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1743 break; 1744 default: 1745 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1746 } 1747 1748 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1749 1750 if ( sc->sk_type == SK_YUKON ) { 1751 uint32_t flashaddr; 1752 uint8_t testbyte; 1753 1754 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1755 1756 /* test Flash-Address Register */ 1757 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1758 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1759 1760 if (testbyte != 0) { 1761 /* this is yukon lite Rev. A0 */ 1762 sc->sk_type = SK_YUKON_LITE; 1763 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1764 /* restore Flash-Address Register */ 1765 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1766 } 1767 } 1768 break; 1769 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_BELKIN): 1770 sc->sk_name = sc->sk_vpd_prodname; 1771 break; 1772 default: 1773 sc->sk_name = "Unknown Marvell"; 1774 } 1775 1776 1777 if ( sc->sk_type == SK_YUKON_LITE ) { 1778 switch (sc->sk_rev) { 1779 case SK_YUKON_LITE_REV_A0: 1780 revstr = "A0"; 1781 break; 1782 case SK_YUKON_LITE_REV_A1: 1783 revstr = "A1"; 1784 break; 1785 case SK_YUKON_LITE_REV_A3: 1786 revstr = "A3"; 1787 break; 1788 default: 1789 revstr = ""; 1790 } 1791 } else { 1792 revstr = ""; 1793 } 1794 1795 /* Announce the product name. */ 1796 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1797 sc->sk_name, revstr, sc->sk_rev); 1798 1799 skca.skc_port = SK_PORT_A; 1800 (void)config_found(&sc->sk_dev, &skca, skcprint); 1801 1802 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1803 skca.skc_port = SK_PORT_B; 1804 (void)config_found(&sc->sk_dev, &skca, skcprint); 1805 } 1806 1807 /* Turn on the 'driver is loaded' LED. */ 1808 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1809 1810 /* skc sysctl setup */ 1811 1812 sc->sk_int_mod = SK_IM_DEFAULT; 1813 sc->sk_int_mod_pending = 0; 1814 1815 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1816 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1817 SYSCTL_DESCR("skc per-controller controls"), 1818 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1819 CTL_EOL)) != 0) { 1820 aprint_normal("%s: couldn't create sysctl node\n", 1821 sc->sk_dev.dv_xname); 1822 goto fail; 1823 } 1824 1825 sk_nodenum = node->sysctl_num; 1826 1827 /* interrupt moderation time in usecs */ 1828 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1829 CTLFLAG_READWRITE, 1830 CTLTYPE_INT, "int_mod", 1831 SYSCTL_DESCR("sk interrupt moderation timer"), 1832 sk_sysctl_handler, 0, sc, 1833 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1834 CTL_EOL)) != 0) { 1835 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1836 sc->sk_dev.dv_xname); 1837 goto fail; 1838 } 1839 1840 fail: 1841 splx(s); 1842 } 1843 1844 int 1845 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1846 { 1847 struct sk_softc *sc = sc_if->sk_softc; 1848 struct sk_tx_desc *f = NULL; 1849 u_int32_t frag, cur, cnt = 0; 1850 int i; 1851 struct sk_txmap_entry *entry; 1852 bus_dmamap_t txmap; 1853 1854 DPRINTFN(3, ("sk_encap\n")); 1855 1856 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1857 if (entry == NULL) { 1858 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1859 return ENOBUFS; 1860 } 1861 txmap = entry->dmamap; 1862 1863 cur = frag = *txidx; 1864 1865 #ifdef SK_DEBUG 1866 if (skdebug >= 3) 1867 sk_dump_mbuf(m_head); 1868 #endif 1869 1870 /* 1871 * Start packing the mbufs in this chain into 1872 * the fragment pointers. Stop when we run out 1873 * of fragments or hit the end of the mbuf chain. 1874 */ 1875 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1876 BUS_DMA_NOWAIT)) { 1877 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1878 return(ENOBUFS); 1879 } 1880 1881 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1882 1883 /* Sync the DMA map. */ 1884 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1885 BUS_DMASYNC_PREWRITE); 1886 1887 for (i = 0; i < txmap->dm_nsegs; i++) { 1888 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1889 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1890 return(ENOBUFS); 1891 } 1892 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1893 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1894 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1895 if (cnt == 0) 1896 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1897 else 1898 f->sk_ctl |= SK_TXCTL_OWN; 1899 1900 cur = frag; 1901 SK_INC(frag, SK_TX_RING_CNT); 1902 cnt++; 1903 } 1904 1905 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1906 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1907 1908 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1909 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1910 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1911 1912 /* Sync descriptors before handing to chip */ 1913 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1914 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1915 1916 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1917 1918 /* Sync first descriptor to hand it off */ 1919 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1920 1921 sc_if->sk_cdata.sk_tx_cnt += cnt; 1922 1923 #ifdef SK_DEBUG 1924 if (skdebug >= 3) { 1925 struct sk_tx_desc *desc; 1926 u_int32_t idx; 1927 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1928 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1929 sk_dump_txdesc(desc, idx); 1930 } 1931 } 1932 #endif 1933 1934 *txidx = frag; 1935 1936 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1937 1938 return(0); 1939 } 1940 1941 void 1942 sk_start(struct ifnet *ifp) 1943 { 1944 struct sk_if_softc *sc_if = ifp->if_softc; 1945 struct sk_softc *sc = sc_if->sk_softc; 1946 struct mbuf *m_head = NULL; 1947 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1948 int pkts = 0; 1949 1950 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1951 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1952 1953 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1954 1955 IFQ_POLL(&ifp->if_snd, m_head); 1956 if (m_head == NULL) 1957 break; 1958 1959 /* 1960 * Pack the data into the transmit ring. If we 1961 * don't have room, set the OACTIVE flag and wait 1962 * for the NIC to drain the ring. 1963 */ 1964 if (sk_encap(sc_if, m_head, &idx)) { 1965 ifp->if_flags |= IFF_OACTIVE; 1966 break; 1967 } 1968 1969 /* now we are committed to transmit the packet */ 1970 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1971 pkts++; 1972 1973 /* 1974 * If there's a BPF listener, bounce a copy of this frame 1975 * to him. 1976 */ 1977 #if NBPFILTER > 0 1978 if (ifp->if_bpf) 1979 bpf_mtap(ifp->if_bpf, m_head); 1980 #endif 1981 } 1982 if (pkts == 0) 1983 return; 1984 1985 /* Transmit */ 1986 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1987 sc_if->sk_cdata.sk_tx_prod = idx; 1988 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1989 1990 /* Set a timeout in case the chip goes out to lunch. */ 1991 ifp->if_timer = 5; 1992 } 1993 } 1994 1995 1996 void 1997 sk_watchdog(struct ifnet *ifp) 1998 { 1999 struct sk_if_softc *sc_if = ifp->if_softc; 2000 2001 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 2002 (void) sk_init(ifp); 2003 } 2004 2005 void 2006 sk_shutdown(void * v) 2007 { 2008 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2009 struct sk_softc *sc = sc_if->sk_softc; 2010 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2011 2012 DPRINTFN(2, ("sk_shutdown\n")); 2013 sk_stop(ifp,1); 2014 2015 /* Turn off the 'driver is loaded' LED. */ 2016 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2017 2018 /* 2019 * Reset the GEnesis controller. Doing this should also 2020 * assert the resets on the attached XMAC(s). 2021 */ 2022 sk_reset(sc); 2023 } 2024 2025 void 2026 sk_rxeof(struct sk_if_softc *sc_if) 2027 { 2028 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2029 struct mbuf *m; 2030 struct sk_chain *cur_rx; 2031 struct sk_rx_desc *cur_desc; 2032 int i, cur, total_len = 0; 2033 u_int32_t rxstat; 2034 bus_dmamap_t dmamap; 2035 2036 i = sc_if->sk_cdata.sk_rx_prod; 2037 2038 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2039 2040 for (;;) { 2041 cur = i; 2042 2043 /* Sync the descriptor */ 2044 SK_CDRXSYNC(sc_if, cur, 2045 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2046 2047 if (sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl & SK_RXCTL_OWN) { 2048 /* Invalidate the descriptor -- it's not ready yet */ 2049 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2050 sc_if->sk_cdata.sk_rx_prod = i; 2051 break; 2052 } 2053 2054 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2055 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2056 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2057 2058 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2059 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2060 2061 rxstat = cur_desc->sk_xmac_rxstat; 2062 m = cur_rx->sk_mbuf; 2063 cur_rx->sk_mbuf = NULL; 2064 total_len = SK_RXBYTES(cur_desc->sk_ctl); 2065 2066 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2067 2068 SK_INC(i, SK_RX_RING_CNT); 2069 2070 if (rxstat & XM_RXSTAT_ERRFRAME) { 2071 ifp->if_ierrors++; 2072 sk_newbuf(sc_if, cur, m, dmamap); 2073 continue; 2074 } 2075 2076 /* 2077 * Try to allocate a new jumbo buffer. If that 2078 * fails, copy the packet to mbufs and put the 2079 * jumbo buffer back in the ring so it can be 2080 * re-used. If allocating mbufs fails, then we 2081 * have to drop the packet. 2082 */ 2083 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2084 struct mbuf *m0; 2085 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2086 total_len + ETHER_ALIGN, 0, ifp, NULL); 2087 sk_newbuf(sc_if, cur, m, dmamap); 2088 if (m0 == NULL) { 2089 printf("%s: no receive buffers " 2090 "available -- packet dropped!\n", 2091 sc_if->sk_dev.dv_xname); 2092 ifp->if_ierrors++; 2093 continue; 2094 } 2095 m_adj(m0, ETHER_ALIGN); 2096 m = m0; 2097 } else { 2098 m->m_pkthdr.rcvif = ifp; 2099 m->m_pkthdr.len = m->m_len = total_len; 2100 } 2101 2102 ifp->if_ipackets++; 2103 2104 #if NBPFILTER > 0 2105 if (ifp->if_bpf) 2106 bpf_mtap(ifp->if_bpf, m); 2107 #endif 2108 /* pass it on. */ 2109 (*ifp->if_input)(ifp, m); 2110 } 2111 } 2112 2113 void 2114 sk_txeof(struct sk_if_softc *sc_if) 2115 { 2116 struct sk_softc *sc = sc_if->sk_softc; 2117 struct sk_tx_desc *cur_tx; 2118 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2119 u_int32_t idx; 2120 struct sk_txmap_entry *entry; 2121 2122 DPRINTFN(3, ("sk_txeof\n")); 2123 2124 /* 2125 * Go through our tx ring and free mbufs for those 2126 * frames that have been sent. 2127 */ 2128 idx = sc_if->sk_cdata.sk_tx_cons; 2129 while(idx != sc_if->sk_cdata.sk_tx_prod) { 2130 SK_CDTXSYNC(sc_if, idx, 1, 2131 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2132 2133 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2134 #ifdef SK_DEBUG 2135 if (skdebug >= 3) 2136 sk_dump_txdesc(cur_tx, idx); 2137 #endif 2138 if (cur_tx->sk_ctl & SK_TXCTL_OWN) { 2139 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2140 break; 2141 } 2142 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 2143 ifp->if_opackets++; 2144 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2145 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2146 2147 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2148 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2149 2150 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2151 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2152 2153 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2154 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2155 link); 2156 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2157 } 2158 sc_if->sk_cdata.sk_tx_cnt--; 2159 SK_INC(idx, SK_TX_RING_CNT); 2160 } 2161 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2162 ifp->if_timer = 0; 2163 else /* nudge chip to keep tx ring moving */ 2164 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2165 2166 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2167 ifp->if_flags &= ~IFF_OACTIVE; 2168 2169 sc_if->sk_cdata.sk_tx_cons = idx; 2170 } 2171 2172 void 2173 sk_tick(void *xsc_if) 2174 { 2175 struct sk_if_softc *sc_if = xsc_if; 2176 struct mii_data *mii = &sc_if->sk_mii; 2177 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2178 int i; 2179 2180 DPRINTFN(3, ("sk_tick\n")); 2181 2182 if (!(ifp->if_flags & IFF_UP)) 2183 return; 2184 2185 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2186 sk_intr_bcom(sc_if); 2187 return; 2188 } 2189 2190 /* 2191 * According to SysKonnect, the correct way to verify that 2192 * the link has come back up is to poll bit 0 of the GPIO 2193 * register three times. This pin has the signal from the 2194 * link sync pin connected to it; if we read the same link 2195 * state 3 times in a row, we know the link is up. 2196 */ 2197 for (i = 0; i < 3; i++) { 2198 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2199 break; 2200 } 2201 2202 if (i != 3) { 2203 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2204 return; 2205 } 2206 2207 /* Turn the GP0 interrupt back on. */ 2208 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2209 SK_XM_READ_2(sc_if, XM_ISR); 2210 mii_tick(mii); 2211 mii_pollstat(mii); 2212 callout_stop(&sc_if->sk_tick_ch); 2213 } 2214 2215 void 2216 sk_intr_bcom(struct sk_if_softc *sc_if) 2217 { 2218 struct mii_data *mii = &sc_if->sk_mii; 2219 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2220 int status; 2221 2222 2223 DPRINTFN(3, ("sk_intr_bcom\n")); 2224 2225 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2226 2227 /* 2228 * Read the PHY interrupt register to make sure 2229 * we clear any pending interrupts. 2230 */ 2231 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2232 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2233 2234 if (!(ifp->if_flags & IFF_RUNNING)) { 2235 sk_init_xmac(sc_if); 2236 return; 2237 } 2238 2239 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2240 int lstat; 2241 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2242 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2243 2244 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2245 mii_mediachg(mii); 2246 /* Turn off the link LED. */ 2247 SK_IF_WRITE_1(sc_if, 0, 2248 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2249 sc_if->sk_link = 0; 2250 } else if (status & BRGPHY_ISR_LNK_CHG) { 2251 sk_xmac_miibus_writereg((struct device *)sc_if, 2252 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2253 mii_tick(mii); 2254 sc_if->sk_link = 1; 2255 /* Turn on the link LED. */ 2256 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2257 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2258 SK_LINKLED_BLINK_OFF); 2259 mii_pollstat(mii); 2260 } else { 2261 mii_tick(mii); 2262 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2263 } 2264 } 2265 2266 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2267 } 2268 2269 void 2270 sk_intr_xmac(struct sk_if_softc *sc_if) 2271 { 2272 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2273 2274 DPRINTFN(3, ("sk_intr_xmac\n")); 2275 2276 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2277 if (status & XM_ISR_GP0_SET) { 2278 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2279 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2280 } 2281 2282 if (status & XM_ISR_AUTONEG_DONE) { 2283 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2284 } 2285 } 2286 2287 if (status & XM_IMR_TX_UNDERRUN) 2288 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2289 2290 if (status & XM_IMR_RX_OVERRUN) 2291 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2292 } 2293 2294 void 2295 sk_intr_yukon(sc_if) 2296 struct sk_if_softc *sc_if; 2297 { 2298 int status; 2299 2300 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2301 2302 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2303 } 2304 2305 int 2306 sk_intr(void *xsc) 2307 { 2308 struct sk_softc *sc = xsc; 2309 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2310 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2311 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2312 u_int32_t status; 2313 int claimed = 0; 2314 2315 if (sc_if0 != NULL) 2316 ifp0 = &sc_if0->sk_ethercom.ec_if; 2317 if (sc_if1 != NULL) 2318 ifp1 = &sc_if1->sk_ethercom.ec_if; 2319 2320 for (;;) { 2321 status = CSR_READ_4(sc, SK_ISSR); 2322 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2323 2324 if (!(status & sc->sk_intrmask)) 2325 break; 2326 2327 claimed = 1; 2328 2329 /* Handle receive interrupts first. */ 2330 if (status & SK_ISR_RX1_EOF) { 2331 sk_rxeof(sc_if0); 2332 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2333 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2334 } 2335 if (status & SK_ISR_RX2_EOF) { 2336 sk_rxeof(sc_if1); 2337 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2338 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2339 } 2340 2341 /* Then transmit interrupts. */ 2342 if (status & SK_ISR_TX1_S_EOF) { 2343 sk_txeof(sc_if0); 2344 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2345 SK_TXBMU_CLR_IRQ_EOF); 2346 } 2347 if (status & SK_ISR_TX2_S_EOF) { 2348 sk_txeof(sc_if1); 2349 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2350 SK_TXBMU_CLR_IRQ_EOF); 2351 } 2352 2353 /* Then MAC interrupts. */ 2354 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 2355 if (sc->sk_type == SK_GENESIS) 2356 sk_intr_xmac(sc_if0); 2357 else 2358 sk_intr_yukon(sc_if0); 2359 } 2360 2361 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 2362 if (sc->sk_type == SK_GENESIS) 2363 sk_intr_xmac(sc_if1); 2364 else 2365 sk_intr_yukon(sc_if1); 2366 2367 } 2368 2369 if (status & SK_ISR_EXTERNAL_REG) { 2370 if (ifp0 != NULL && 2371 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2372 sk_intr_bcom(sc_if0); 2373 2374 if (ifp1 != NULL && 2375 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2376 sk_intr_bcom(sc_if1); 2377 } 2378 } 2379 2380 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2381 2382 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2383 sk_start(ifp0); 2384 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2385 sk_start(ifp1); 2386 2387 #if NRND > 0 2388 if (RND_ENABLED(&sc->rnd_source)) 2389 rnd_add_uint32(&sc->rnd_source, status); 2390 #endif 2391 2392 if (sc->sk_int_mod_pending) 2393 sk_update_int_mod(sc); 2394 2395 return (claimed); 2396 } 2397 2398 void 2399 sk_init_xmac(struct sk_if_softc *sc_if) 2400 { 2401 struct sk_softc *sc = sc_if->sk_softc; 2402 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2403 static const struct sk_bcom_hack bhack[] = { 2404 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2405 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2406 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2407 { 0, 0 } }; 2408 2409 DPRINTFN(1, ("sk_init_xmac\n")); 2410 2411 /* Unreset the XMAC. */ 2412 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2413 DELAY(1000); 2414 2415 /* Reset the XMAC's internal state. */ 2416 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2417 2418 /* Save the XMAC II revision */ 2419 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2420 2421 /* 2422 * Perform additional initialization for external PHYs, 2423 * namely for the 1000baseTX cards that use the XMAC's 2424 * GMII mode. 2425 */ 2426 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2427 int i = 0; 2428 u_int32_t val; 2429 2430 /* Take PHY out of reset. */ 2431 val = sk_win_read_4(sc, SK_GPIO); 2432 if (sc_if->sk_port == SK_PORT_A) 2433 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2434 else 2435 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2436 sk_win_write_4(sc, SK_GPIO, val); 2437 2438 /* Enable GMII mode on the XMAC. */ 2439 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2440 2441 sk_xmac_miibus_writereg((struct device *)sc_if, 2442 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2443 DELAY(10000); 2444 sk_xmac_miibus_writereg((struct device *)sc_if, 2445 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2446 2447 /* 2448 * Early versions of the BCM5400 apparently have 2449 * a bug that requires them to have their reserved 2450 * registers initialized to some magic values. I don't 2451 * know what the numbers do, I'm just the messenger. 2452 */ 2453 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2454 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2455 while(bhack[i].reg) { 2456 sk_xmac_miibus_writereg((struct device *)sc_if, 2457 SK_PHYADDR_BCOM, bhack[i].reg, 2458 bhack[i].val); 2459 i++; 2460 } 2461 } 2462 } 2463 2464 /* Set station address */ 2465 SK_XM_WRITE_2(sc_if, XM_PAR0, 2466 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2467 SK_XM_WRITE_2(sc_if, XM_PAR1, 2468 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2469 SK_XM_WRITE_2(sc_if, XM_PAR2, 2470 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2471 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2472 2473 if (ifp->if_flags & IFF_PROMISC) { 2474 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2475 } else { 2476 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2477 } 2478 2479 if (ifp->if_flags & IFF_BROADCAST) { 2480 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2481 } else { 2482 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2483 } 2484 2485 /* We don't need the FCS appended to the packet. */ 2486 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2487 2488 /* We want short frames padded to 60 bytes. */ 2489 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2490 2491 /* 2492 * Enable the reception of all error frames. This is is 2493 * a necessary evil due to the design of the XMAC. The 2494 * XMAC's receive FIFO is only 8K in size, however jumbo 2495 * frames can be up to 9000 bytes in length. When bad 2496 * frame filtering is enabled, the XMAC's RX FIFO operates 2497 * in 'store and forward' mode. For this to work, the 2498 * entire frame has to fit into the FIFO, but that means 2499 * that jumbo frames larger than 8192 bytes will be 2500 * truncated. Disabling all bad frame filtering causes 2501 * the RX FIFO to operate in streaming mode, in which 2502 * case the XMAC will start transfering frames out of the 2503 * RX FIFO as soon as the FIFO threshold is reached. 2504 */ 2505 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2506 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2507 XM_MODE_RX_INRANGELEN); 2508 2509 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2510 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2511 else 2512 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2513 2514 /* 2515 * Bump up the transmit threshold. This helps hold off transmit 2516 * underruns when we're blasting traffic from both ports at once. 2517 */ 2518 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2519 2520 /* Set multicast filter */ 2521 sk_setmulti(sc_if); 2522 2523 /* Clear and enable interrupts */ 2524 SK_XM_READ_2(sc_if, XM_ISR); 2525 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2526 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2527 else 2528 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2529 2530 /* Configure MAC arbiter */ 2531 switch(sc_if->sk_xmac_rev) { 2532 case XM_XMAC_REV_B2: 2533 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2534 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2535 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2536 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2537 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2538 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2539 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2540 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2541 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2542 break; 2543 case XM_XMAC_REV_C1: 2544 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2545 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2546 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2547 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2548 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2549 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2550 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2551 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2552 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2553 break; 2554 default: 2555 break; 2556 } 2557 sk_win_write_2(sc, SK_MACARB_CTL, 2558 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2559 2560 sc_if->sk_link = 1; 2561 } 2562 2563 void sk_init_yukon(sc_if) 2564 struct sk_if_softc *sc_if; 2565 { 2566 u_int32_t /*mac, */phy; 2567 u_int16_t reg; 2568 struct sk_softc *sc; 2569 int i; 2570 2571 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2572 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2573 2574 sc = sc_if->sk_softc; 2575 if (sc->sk_type == SK_YUKON_LITE && 2576 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2577 /* Take PHY out of reset. */ 2578 sk_win_write_4(sc, SK_GPIO, 2579 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2580 } 2581 2582 2583 /* GMAC and GPHY Reset */ 2584 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2585 2586 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2587 2588 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2589 DELAY(1000); 2590 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2591 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2592 DELAY(1000); 2593 2594 2595 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2596 2597 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2598 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2599 2600 switch(sc_if->sk_softc->sk_pmd) { 2601 case IFM_1000_SX: 2602 case IFM_1000_LX: 2603 phy |= SK_GPHY_FIBER; 2604 break; 2605 2606 case IFM_1000_CX: 2607 case IFM_1000_T: 2608 phy |= SK_GPHY_COPPER; 2609 break; 2610 } 2611 2612 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2613 2614 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2615 DELAY(1000); 2616 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2617 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2618 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2619 2620 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2621 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2622 2623 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2624 2625 /* unused read of the interrupt source register */ 2626 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2627 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2628 2629 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2630 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2631 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2632 2633 /* MIB Counter Clear Mode set */ 2634 reg |= YU_PAR_MIB_CLR; 2635 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2636 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2637 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2638 2639 /* MIB Counter Clear Mode clear */ 2640 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2641 reg &= ~YU_PAR_MIB_CLR; 2642 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2643 2644 /* receive control reg */ 2645 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2646 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2647 YU_RCR_CRCR); 2648 2649 /* transmit parameter register */ 2650 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2651 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2652 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2653 2654 /* serial mode register */ 2655 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2656 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2657 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2658 YU_SMR_IPG_DATA(0x1e)); 2659 2660 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2661 /* Setup Yukon's address */ 2662 for (i = 0; i < 3; i++) { 2663 /* Write Source Address 1 (unicast filter) */ 2664 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2665 sc_if->sk_enaddr[i * 2] | 2666 sc_if->sk_enaddr[i * 2 + 1] << 8); 2667 } 2668 2669 for (i = 0; i < 3; i++) { 2670 reg = sk_win_read_2(sc_if->sk_softc, 2671 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2672 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2673 } 2674 2675 /* Set multicast filter */ 2676 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2677 sk_setmulti(sc_if); 2678 2679 /* enable interrupt mask for counter overflows */ 2680 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2681 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2682 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2683 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2684 2685 /* Configure RX MAC FIFO */ 2686 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2687 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2688 2689 /* Configure TX MAC FIFO */ 2690 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2691 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2692 2693 DPRINTFN(6, ("sk_init_yukon: end\n")); 2694 } 2695 2696 /* 2697 * Note that to properly initialize any part of the GEnesis chip, 2698 * you first have to take it out of reset mode. 2699 */ 2700 int 2701 sk_init(struct ifnet *ifp) 2702 { 2703 struct sk_if_softc *sc_if = ifp->if_softc; 2704 struct sk_softc *sc = sc_if->sk_softc; 2705 struct mii_data *mii = &sc_if->sk_mii; 2706 int s; 2707 u_int32_t imr, sk_imtimer_ticks; 2708 2709 DPRINTFN(1, ("sk_init\n")); 2710 2711 s = splnet(); 2712 2713 if (ifp->if_flags & IFF_RUNNING) { 2714 splx(s); 2715 return 0; 2716 } 2717 2718 /* Cancel pending I/O and free all RX/TX buffers. */ 2719 sk_stop(ifp,0); 2720 2721 if (sc->sk_type == SK_GENESIS) { 2722 /* Configure LINK_SYNC LED */ 2723 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2724 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2725 SK_LINKLED_LINKSYNC_ON); 2726 2727 /* Configure RX LED */ 2728 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2729 SK_RXLEDCTL_COUNTER_START); 2730 2731 /* Configure TX LED */ 2732 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2733 SK_TXLEDCTL_COUNTER_START); 2734 } 2735 2736 /* Configure I2C registers */ 2737 2738 /* Configure XMAC(s) */ 2739 switch (sc->sk_type) { 2740 case SK_GENESIS: 2741 sk_init_xmac(sc_if); 2742 break; 2743 case SK_YUKON: 2744 case SK_YUKON_LITE: 2745 case SK_YUKON_LP: 2746 sk_init_yukon(sc_if); 2747 break; 2748 } 2749 mii_mediachg(mii); 2750 2751 if (sc->sk_type == SK_GENESIS) { 2752 /* Configure MAC FIFOs */ 2753 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2754 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2755 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2756 2757 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2758 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2759 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2760 } 2761 2762 /* Configure transmit arbiter(s) */ 2763 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2764 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2765 2766 /* Configure RAMbuffers */ 2767 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2768 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2769 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2770 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2771 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2772 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2773 2774 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2775 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2776 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2777 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2778 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2779 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2780 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2781 2782 /* Configure BMUs */ 2783 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2784 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2785 SK_RX_RING_ADDR(sc_if, 0)); 2786 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2787 2788 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2789 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2790 SK_TX_RING_ADDR(sc_if, 0)); 2791 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2792 2793 /* Init descriptors */ 2794 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2795 printf("%s: initialization failed: no " 2796 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2797 sk_stop(ifp,0); 2798 splx(s); 2799 return(ENOBUFS); 2800 } 2801 2802 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2803 printf("%s: initialization failed: no " 2804 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2805 sk_stop(ifp,0); 2806 splx(s); 2807 return(ENOBUFS); 2808 } 2809 2810 /* Set interrupt moderation if changed via sysctl. */ 2811 switch (sc->sk_type) { 2812 case SK_GENESIS: 2813 sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2814 break; 2815 case SK_YUKON_EC: 2816 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2817 break; 2818 default: 2819 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2820 } 2821 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2822 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2823 sk_win_write_4(sc, SK_IMTIMERINIT, 2824 SK_IM_USECS(sc->sk_int_mod)); 2825 aprint_verbose("%s: interrupt moderation is %d us\n", 2826 sc->sk_dev.dv_xname, sc->sk_int_mod); 2827 } 2828 2829 /* Configure interrupt handling */ 2830 CSR_READ_4(sc, SK_ISSR); 2831 if (sc_if->sk_port == SK_PORT_A) 2832 sc->sk_intrmask |= SK_INTRS1; 2833 else 2834 sc->sk_intrmask |= SK_INTRS2; 2835 2836 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2837 2838 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2839 2840 /* Start BMUs. */ 2841 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2842 2843 if (sc->sk_type == SK_GENESIS) { 2844 /* Enable XMACs TX and RX state machines */ 2845 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2846 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2847 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2848 } 2849 2850 if (SK_YUKON_FAMILY(sc->sk_type)) { 2851 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2852 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2853 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2854 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2855 } 2856 2857 2858 ifp->if_flags |= IFF_RUNNING; 2859 ifp->if_flags &= ~IFF_OACTIVE; 2860 2861 splx(s); 2862 return(0); 2863 } 2864 2865 void 2866 sk_stop(struct ifnet *ifp, int disable) 2867 { 2868 struct sk_if_softc *sc_if = ifp->if_softc; 2869 struct sk_softc *sc = sc_if->sk_softc; 2870 //struct sk_txmap_entry *dma; 2871 int i; 2872 2873 DPRINTFN(1, ("sk_stop\n")); 2874 2875 callout_stop(&sc_if->sk_tick_ch); 2876 2877 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2878 u_int32_t val; 2879 2880 /* Put PHY back into reset. */ 2881 val = sk_win_read_4(sc, SK_GPIO); 2882 if (sc_if->sk_port == SK_PORT_A) { 2883 val |= SK_GPIO_DIR0; 2884 val &= ~SK_GPIO_DAT0; 2885 } else { 2886 val |= SK_GPIO_DIR2; 2887 val &= ~SK_GPIO_DAT2; 2888 } 2889 sk_win_write_4(sc, SK_GPIO, val); 2890 } 2891 2892 /* Turn off various components of this interface. */ 2893 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2894 switch (sc->sk_type) { 2895 case SK_GENESIS: 2896 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2897 SK_TXMACCTL_XMAC_RESET); 2898 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2899 break; 2900 case SK_YUKON: 2901 case SK_YUKON_LITE: 2902 case SK_YUKON_LP: 2903 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2904 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2905 break; 2906 } 2907 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2908 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2909 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2910 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2911 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2912 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2913 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2914 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2915 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2916 2917 /* Disable interrupts */ 2918 if (sc_if->sk_port == SK_PORT_A) 2919 sc->sk_intrmask &= ~SK_INTRS1; 2920 else 2921 sc->sk_intrmask &= ~SK_INTRS2; 2922 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2923 2924 SK_XM_READ_2(sc_if, XM_ISR); 2925 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2926 2927 /* Free RX and TX mbufs still in the queues. */ 2928 for (i = 0; i < SK_RX_RING_CNT; i++) { 2929 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2930 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2931 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2932 } 2933 } 2934 2935 for (i = 0; i < SK_TX_RING_CNT; i++) { 2936 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2937 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2938 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2939 } 2940 } 2941 2942 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2943 } 2944 2945 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2946 2947 /* 2948 struct cfdriver skc_cd = { 2949 0, "skc", DV_DULL 2950 }; 2951 */ 2952 2953 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2954 2955 /* 2956 struct cfdriver sk_cd = { 2957 0, "sk", DV_IFNET 2958 }; 2959 */ 2960 2961 #ifdef SK_DEBUG 2962 void 2963 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2964 { 2965 #define DESC_PRINT(X) \ 2966 if (desc->X) \ 2967 printf("txdesc[%d]." #X "=%#x\n", \ 2968 idx, desc->X); 2969 2970 DESC_PRINT(sk_ctl); 2971 DESC_PRINT(sk_next); 2972 DESC_PRINT(sk_data_lo); 2973 DESC_PRINT(sk_data_hi); 2974 DESC_PRINT(sk_xmac_txstat); 2975 DESC_PRINT(sk_rsvd0); 2976 DESC_PRINT(sk_csum_startval); 2977 DESC_PRINT(sk_csum_startpos); 2978 DESC_PRINT(sk_csum_writepos); 2979 DESC_PRINT(sk_rsvd1); 2980 #undef PRINT 2981 } 2982 2983 void 2984 sk_dump_bytes(const char *data, int len) 2985 { 2986 int c, i, j; 2987 2988 for (i = 0; i < len; i += 16) { 2989 printf("%08x ", i); 2990 c = len - i; 2991 if (c > 16) c = 16; 2992 2993 for (j = 0; j < c; j++) { 2994 printf("%02x ", data[i + j] & 0xff); 2995 if ((j & 0xf) == 7 && j > 0) 2996 printf(" "); 2997 } 2998 2999 for (; j < 16; j++) 3000 printf(" "); 3001 printf(" "); 3002 3003 for (j = 0; j < c; j++) { 3004 int ch = data[i + j] & 0xff; 3005 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3006 } 3007 3008 printf("\n"); 3009 3010 if (c < 16) 3011 break; 3012 } 3013 } 3014 3015 void 3016 sk_dump_mbuf(struct mbuf *m) 3017 { 3018 int count = m->m_pkthdr.len; 3019 3020 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3021 3022 while (count > 0 && m) { 3023 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3024 m, m->m_data, m->m_len); 3025 sk_dump_bytes(mtod(m, char *), m->m_len); 3026 3027 count -= m->m_len; 3028 m = m->m_next; 3029 } 3030 } 3031 #endif 3032 3033 static int 3034 sk_sysctl_handler(SYSCTLFN_ARGS) 3035 { 3036 int error, t; 3037 struct sysctlnode node; 3038 struct sk_softc *sc; 3039 3040 node = *rnode; 3041 sc = node.sysctl_data; 3042 t = sc->sk_int_mod; 3043 node.sysctl_data = &t; 3044 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3045 if (error || newp == NULL) 3046 return (error); 3047 3048 if (t < SK_IM_MIN || t > SK_IM_MAX) 3049 return (EINVAL); 3050 3051 /* update the softc with sysctl-changed value, and mark 3052 for hardware update */ 3053 sc->sk_int_mod = t; 3054 sc->sk_int_mod_pending = 1; 3055 return (0); 3056 } 3057 3058 /* 3059 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3060 * set up in skc_attach() 3061 */ 3062 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3063 { 3064 int rc; 3065 const struct sysctlnode *node; 3066 3067 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3068 0, CTLTYPE_NODE, "hw", NULL, 3069 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3070 goto err; 3071 } 3072 3073 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3074 0, CTLTYPE_NODE, "sk", 3075 SYSCTL_DESCR("sk interface controls"), 3076 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3077 goto err; 3078 } 3079 3080 sk_root_num = node->sysctl_num; 3081 return; 3082 3083 err: 3084 printf("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3085 } 3086
Indexes created Mon Sep 22 21:09:42 GMT 2025