if_sk.c revision 1.28
1 /* $NetBSD: if_sk.c,v 1.28 2006/08/20 18:04:53 riz Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 #include "rnd.h" 126 127 #include <sys/param.h> 128 #include <sys/systm.h> 129 #include <sys/sockio.h> 130 #include <sys/mbuf.h> 131 #include <sys/malloc.h> 132 #include <sys/kernel.h> 133 #include <sys/socket.h> 134 #include <sys/device.h> 135 #include <sys/queue.h> 136 #include <sys/callout.h> 137 #include <sys/sysctl.h> 138 139 #include <net/if.h> 140 #include <net/if_dl.h> 141 #include <net/if_types.h> 142 143 #ifdef INET 144 #include <netinet/in.h> 145 #include <netinet/in_systm.h> 146 #include <netinet/in_var.h> 147 #include <netinet/ip.h> 148 #include <netinet/if_ether.h> 149 #endif 150 151 #include <net/if_media.h> 152 153 #if NBPFILTER > 0 154 #include <net/bpf.h> 155 #endif 156 #if NRND > 0 157 #include <sys/rnd.h> 158 #endif 159 160 #include <dev/mii/mii.h> 161 #include <dev/mii/miivar.h> 162 #include <dev/mii/brgphyreg.h> 163 164 #include <dev/pci/pcireg.h> 165 #include <dev/pci/pcivar.h> 166 #include <dev/pci/pcidevs.h> 167 168 #define SK_VERBOSE 169 /* #define SK_USEIOSPACE */ 170 171 #include <dev/pci/if_skreg.h> 172 #include <dev/pci/if_skvar.h> 173 174 int skc_probe(struct device *, struct cfdata *, void *); 175 void skc_attach(struct device *, struct device *self, void *aux); 176 int sk_probe(struct device *, struct cfdata *, void *); 177 void sk_attach(struct device *, struct device *self, void *aux); 178 int skcprint(void *, const char *); 179 int sk_intr(void *); 180 void sk_intr_bcom(struct sk_if_softc *); 181 void sk_intr_xmac(struct sk_if_softc *); 182 void sk_intr_yukon(struct sk_if_softc *); 183 void sk_rxeof(struct sk_if_softc *); 184 void sk_txeof(struct sk_if_softc *); 185 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 186 void sk_start(struct ifnet *); 187 int sk_ioctl(struct ifnet *, u_long, caddr_t); 188 int sk_init(struct ifnet *); 189 void sk_init_xmac(struct sk_if_softc *); 190 void sk_init_yukon(struct sk_if_softc *); 191 void sk_stop(struct ifnet *, int); 192 void sk_watchdog(struct ifnet *); 193 void sk_shutdown(void *); 194 int sk_ifmedia_upd(struct ifnet *); 195 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 196 void sk_reset(struct sk_softc *); 197 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 198 int sk_alloc_jumbo_mem(struct sk_if_softc *); 199 void sk_free_jumbo_mem(struct sk_if_softc *); 200 void *sk_jalloc(struct sk_if_softc *); 201 void sk_jfree(struct mbuf *, caddr_t, size_t, void *); 202 int sk_init_rx_ring(struct sk_if_softc *); 203 int sk_init_tx_ring(struct sk_if_softc *); 204 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 205 void sk_vpd_read_res(struct sk_softc *, 206 struct vpd_res *, int); 207 void sk_vpd_read(struct sk_softc *); 208 209 void sk_update_int_mod(struct sk_softc *); 210 211 int sk_xmac_miibus_readreg(struct device *, int, int); 212 void sk_xmac_miibus_writereg(struct device *, int, int, int); 213 void sk_xmac_miibus_statchg(struct device *); 214 215 int sk_marv_miibus_readreg(struct device *, int, int); 216 void sk_marv_miibus_writereg(struct device *, int, int, int); 217 void sk_marv_miibus_statchg(struct device *); 218 219 u_int32_t sk_xmac_hash(caddr_t); 220 u_int32_t sk_yukon_hash(caddr_t); 221 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 222 void sk_setmulti(struct sk_if_softc *); 223 void sk_tick(void *); 224 225 /* #define SK_DEBUG 2 */ 226 #ifdef SK_DEBUG 227 #define DPRINTF(x) if (skdebug) printf x 228 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 229 int skdebug = SK_DEBUG; 230 231 void sk_dump_txdesc(struct sk_tx_desc *, int); 232 void sk_dump_mbuf(struct mbuf *); 233 void sk_dump_bytes(const char *, int); 234 #else 235 #define DPRINTF(x) 236 #define DPRINTFN(n,x) 237 #endif 238 239 #define SK_SETBIT(sc, reg, x) \ 240 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 241 242 #define SK_CLRBIT(sc, reg, x) \ 243 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 244 245 #define SK_WIN_SETBIT_4(sc, reg, x) \ 246 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 247 248 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 249 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 250 251 #define SK_WIN_SETBIT_2(sc, reg, x) \ 252 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 253 254 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 255 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 256 257 static int sk_sysctl_handler(SYSCTLFN_PROTO); 258 static int sk_root_num; 259 260 /* supported device vendors */ 261 static const struct sk_product { 262 pci_vendor_id_t sk_vendor; 263 pci_product_id_t sk_product; 264 } sk_products[] = { 265 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 266 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 267 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T, }, 268 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 269 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 270 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 271 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 272 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_SKNET, }, 273 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_BELKIN, }, 274 { 0, 0, } 275 }; 276 277 #define SK_LINKSYS_EG1032_SUBID 0x00151737 278 279 static inline u_int32_t 280 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 281 { 282 #ifdef SK_USEIOSPACE 283 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 284 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 285 #else 286 return CSR_READ_4(sc, reg); 287 #endif 288 } 289 290 static inline u_int16_t 291 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 292 { 293 #ifdef SK_USEIOSPACE 294 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 295 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 296 #else 297 return CSR_READ_2(sc, reg); 298 #endif 299 } 300 301 static inline u_int8_t 302 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 303 { 304 #ifdef SK_USEIOSPACE 305 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 306 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 307 #else 308 return CSR_READ_1(sc, reg); 309 #endif 310 } 311 312 static inline void 313 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 314 { 315 #ifdef SK_USEIOSPACE 316 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 317 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 318 #else 319 CSR_WRITE_4(sc, reg, x); 320 #endif 321 } 322 323 static inline void 324 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 325 { 326 #ifdef SK_USEIOSPACE 327 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 328 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 329 #else 330 CSR_WRITE_2(sc, reg, x); 331 #endif 332 } 333 334 static inline void 335 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 336 { 337 #ifdef SK_USEIOSPACE 338 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 339 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 340 #else 341 CSR_WRITE_1(sc, reg, x); 342 #endif 343 } 344 345 /* 346 * The VPD EEPROM contains Vital Product Data, as suggested in 347 * the PCI 2.1 specification. The VPD data is separared into areas 348 * denoted by resource IDs. The SysKonnect VPD contains an ID string 349 * resource (the name of the adapter), a read-only area resource 350 * containing various key/data fields and a read/write area which 351 * can be used to store asset management information or log messages. 352 * We read the ID string and read-only into buffers attached to 353 * the controller softc structure for later use. At the moment, 354 * we only use the ID string during sk_attach(). 355 */ 356 u_int8_t 357 sk_vpd_readbyte(struct sk_softc *sc, int addr) 358 { 359 int i; 360 361 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 362 for (i = 0; i < SK_TIMEOUT; i++) { 363 DELAY(1); 364 if (sk_win_read_2(sc, 365 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 366 break; 367 } 368 369 if (i == SK_TIMEOUT) 370 return(0); 371 372 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 373 } 374 375 void 376 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 377 { 378 int i; 379 u_int8_t *ptr; 380 381 ptr = (u_int8_t *)res; 382 for (i = 0; i < sizeof(struct vpd_res); i++) 383 ptr[i] = sk_vpd_readbyte(sc, i + addr); 384 } 385 386 void 387 sk_vpd_read(struct sk_softc *sc) 388 { 389 int pos = 0, i; 390 struct vpd_res res; 391 392 if (sc->sk_vpd_prodname != NULL) 393 free(sc->sk_vpd_prodname, M_DEVBUF); 394 if (sc->sk_vpd_readonly != NULL) 395 free(sc->sk_vpd_readonly, M_DEVBUF); 396 sc->sk_vpd_prodname = NULL; 397 sc->sk_vpd_readonly = NULL; 398 399 sk_vpd_read_res(sc, &res, pos); 400 401 if (res.vr_id != VPD_RES_ID) { 402 printf("%s: bad VPD resource id: expected %x got %x\n", 403 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 404 return; 405 } 406 407 pos += sizeof(res); 408 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 409 if (sc->sk_vpd_prodname == NULL) 410 panic("sk_vpd_read"); 411 for (i = 0; i < res.vr_len; i++) 412 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 413 sc->sk_vpd_prodname[i] = '\0'; 414 pos += i; 415 416 sk_vpd_read_res(sc, &res, pos); 417 418 if (res.vr_id != VPD_RES_READ) { 419 printf("%s: bad VPD resource id: expected %x got %x\n", 420 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 421 return; 422 } 423 424 pos += sizeof(res); 425 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 426 if (sc->sk_vpd_readonly == NULL) 427 panic("sk_vpd_read"); 428 for (i = 0; i < res.vr_len ; i++) 429 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 430 } 431 432 int 433 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 434 { 435 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 436 int i; 437 438 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 439 440 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 441 return(0); 442 443 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 444 SK_XM_READ_2(sc_if, XM_PHY_DATA); 445 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 446 for (i = 0; i < SK_TIMEOUT; i++) { 447 DELAY(1); 448 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 449 XM_MMUCMD_PHYDATARDY) 450 break; 451 } 452 453 if (i == SK_TIMEOUT) { 454 printf("%s: phy failed to come ready\n", 455 sc_if->sk_dev.dv_xname); 456 return(0); 457 } 458 } 459 DELAY(1); 460 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 461 } 462 463 void 464 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 465 { 466 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 467 int i; 468 469 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 470 471 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 472 for (i = 0; i < SK_TIMEOUT; i++) { 473 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 474 break; 475 } 476 477 if (i == SK_TIMEOUT) { 478 printf("%s: phy failed to come ready\n", 479 sc_if->sk_dev.dv_xname); 480 return; 481 } 482 483 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 484 for (i = 0; i < SK_TIMEOUT; i++) { 485 DELAY(1); 486 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 487 break; 488 } 489 490 if (i == SK_TIMEOUT) 491 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 492 } 493 494 void 495 sk_xmac_miibus_statchg(struct device *dev) 496 { 497 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 498 struct mii_data *mii = &sc_if->sk_mii; 499 500 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 501 502 /* 503 * If this is a GMII PHY, manually set the XMAC's 504 * duplex mode accordingly. 505 */ 506 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 507 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 508 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 509 } else { 510 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 511 } 512 } 513 } 514 515 int 516 sk_marv_miibus_readreg(dev, phy, reg) 517 struct device *dev; 518 int phy, reg; 519 { 520 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 521 u_int16_t val; 522 int i; 523 524 if (phy != 0 || 525 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 526 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 527 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 528 phy, reg)); 529 return(0); 530 } 531 532 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 533 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 534 535 for (i = 0; i < SK_TIMEOUT; i++) { 536 DELAY(1); 537 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 538 if (val & YU_SMICR_READ_VALID) 539 break; 540 } 541 542 if (i == SK_TIMEOUT) { 543 printf("%s: phy failed to come ready\n", 544 sc_if->sk_dev.dv_xname); 545 return 0; 546 } 547 548 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 549 SK_TIMEOUT)); 550 551 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 552 553 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 554 phy, reg, val)); 555 556 return val; 557 } 558 559 void 560 sk_marv_miibus_writereg(dev, phy, reg, val) 561 struct device *dev; 562 int phy, reg, val; 563 { 564 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 565 int i; 566 567 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 568 phy, reg, val)); 569 570 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 571 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 572 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 573 574 for (i = 0; i < SK_TIMEOUT; i++) { 575 DELAY(1); 576 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 577 break; 578 } 579 } 580 581 void 582 sk_marv_miibus_statchg(dev) 583 struct device *dev; 584 { 585 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 586 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 587 } 588 589 #define SK_HASH_BITS 6 590 591 u_int32_t 592 sk_xmac_hash(caddr_t addr) 593 { 594 u_int32_t crc; 595 596 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 597 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 598 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 599 return (crc); 600 } 601 602 u_int32_t 603 sk_yukon_hash(caddr_t addr) 604 { 605 u_int32_t crc; 606 607 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 608 crc &= ((1 << SK_HASH_BITS) - 1); 609 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 610 return (crc); 611 } 612 613 void 614 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 615 { 616 int base = XM_RXFILT_ENTRY(slot); 617 618 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 619 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 620 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 621 } 622 623 void 624 sk_setmulti(struct sk_if_softc *sc_if) 625 { 626 struct sk_softc *sc = sc_if->sk_softc; 627 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 628 u_int32_t hashes[2] = { 0, 0 }; 629 int h = 0, i; 630 struct ethercom *ec = &sc_if->sk_ethercom; 631 struct ether_multi *enm; 632 struct ether_multistep step; 633 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 634 635 /* First, zot all the existing filters. */ 636 switch(sc->sk_type) { 637 case SK_GENESIS: 638 for (i = 1; i < XM_RXFILT_MAX; i++) 639 sk_setfilt(sc_if, (caddr_t)&dummy, i); 640 641 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 642 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 643 break; 644 case SK_YUKON: 645 case SK_YUKON_LITE: 646 case SK_YUKON_LP: 647 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 648 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 649 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 650 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 651 break; 652 } 653 654 /* Now program new ones. */ 655 allmulti: 656 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 657 hashes[0] = 0xFFFFFFFF; 658 hashes[1] = 0xFFFFFFFF; 659 } else { 660 i = 1; 661 /* First find the tail of the list. */ 662 ETHER_FIRST_MULTI(step, ec, enm); 663 while (enm != NULL) { 664 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 665 ETHER_ADDR_LEN)) { 666 ifp->if_flags |= IFF_ALLMULTI; 667 goto allmulti; 668 } 669 DPRINTFN(2,("multicast address %s\n", 670 ether_sprintf(enm->enm_addrlo))); 671 /* 672 * Program the first XM_RXFILT_MAX multicast groups 673 * into the perfect filter. For all others, 674 * use the hash table. 675 */ 676 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 677 sk_setfilt(sc_if, enm->enm_addrlo, i); 678 i++; 679 } 680 else { 681 switch (sc->sk_type) { 682 case SK_GENESIS: 683 h = sk_xmac_hash(enm->enm_addrlo); 684 break; 685 case SK_YUKON: 686 case SK_YUKON_LITE: 687 case SK_YUKON_LP: 688 h = sk_yukon_hash(enm->enm_addrlo); 689 break; 690 } 691 if (h < 32) 692 hashes[0] |= (1 << h); 693 else 694 hashes[1] |= (1 << (h - 32)); 695 } 696 697 ETHER_NEXT_MULTI(step, enm); 698 } 699 } 700 701 switch(sc->sk_type) { 702 case SK_GENESIS: 703 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 704 XM_MODE_RX_USE_PERFECT); 705 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 706 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 707 break; 708 case SK_YUKON: 709 case SK_YUKON_LITE: 710 case SK_YUKON_LP: 711 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 712 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 713 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 714 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 715 break; 716 } 717 } 718 719 int 720 sk_init_rx_ring(struct sk_if_softc *sc_if) 721 { 722 struct sk_chain_data *cd = &sc_if->sk_cdata; 723 struct sk_ring_data *rd = sc_if->sk_rdata; 724 int i; 725 726 bzero((char *)rd->sk_rx_ring, 727 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 728 729 for (i = 0; i < SK_RX_RING_CNT; i++) { 730 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 731 if (i == (SK_RX_RING_CNT - 1)) { 732 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 733 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 734 } else { 735 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 736 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 737 } 738 } 739 740 for (i = 0; i < SK_RX_RING_CNT; i++) { 741 if (sk_newbuf(sc_if, i, NULL, 742 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 743 printf("%s: failed alloc of %dth mbuf\n", 744 sc_if->sk_dev.dv_xname, i); 745 return(ENOBUFS); 746 } 747 } 748 sc_if->sk_cdata.sk_rx_prod = 0; 749 sc_if->sk_cdata.sk_rx_cons = 0; 750 751 return(0); 752 } 753 754 int 755 sk_init_tx_ring(struct sk_if_softc *sc_if) 756 { 757 struct sk_chain_data *cd = &sc_if->sk_cdata; 758 struct sk_ring_data *rd = sc_if->sk_rdata; 759 int i; 760 761 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 762 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 763 764 for (i = 0; i < SK_TX_RING_CNT; i++) { 765 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 766 if (i == (SK_TX_RING_CNT - 1)) { 767 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 768 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 769 } else { 770 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 771 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 772 } 773 } 774 775 sc_if->sk_cdata.sk_tx_prod = 0; 776 sc_if->sk_cdata.sk_tx_cons = 0; 777 sc_if->sk_cdata.sk_tx_cnt = 0; 778 779 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 780 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 781 782 return (0); 783 } 784 785 int 786 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 787 bus_dmamap_t dmamap) 788 { 789 struct mbuf *m_new = NULL; 790 struct sk_chain *c; 791 struct sk_rx_desc *r; 792 793 if (m == NULL) { 794 caddr_t buf = NULL; 795 796 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 797 if (m_new == NULL) { 798 printf("%s: no memory for rx list -- " 799 "packet dropped!\n", sc_if->sk_dev.dv_xname); 800 return(ENOBUFS); 801 } 802 803 /* Allocate the jumbo buffer */ 804 buf = sk_jalloc(sc_if); 805 if (buf == NULL) { 806 m_freem(m_new); 807 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 808 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 809 return(ENOBUFS); 810 } 811 812 /* Attach the buffer to the mbuf */ 813 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 814 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 815 816 } else { 817 /* 818 * We're re-using a previously allocated mbuf; 819 * be sure to re-init pointers and lengths to 820 * default values. 821 */ 822 m_new = m; 823 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 824 m_new->m_data = m_new->m_ext.ext_buf; 825 } 826 m_adj(m_new, ETHER_ALIGN); 827 828 c = &sc_if->sk_cdata.sk_rx_chain[i]; 829 r = c->sk_desc; 830 c->sk_mbuf = m_new; 831 r->sk_data_lo = dmamap->dm_segs[0].ds_addr + 832 (((vaddr_t)m_new->m_data 833 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf)); 834 r->sk_ctl = SK_JLEN | SK_RXSTAT; 835 836 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 837 838 return(0); 839 } 840 841 /* 842 * Memory management for jumbo frames. 843 */ 844 845 int 846 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 847 { 848 struct sk_softc *sc = sc_if->sk_softc; 849 caddr_t ptr, kva; 850 bus_dma_segment_t seg; 851 int i, rseg, state, error; 852 struct sk_jpool_entry *entry; 853 854 state = error = 0; 855 856 /* Grab a big chunk o' storage. */ 857 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 858 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 859 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 860 return (ENOBUFS); 861 } 862 863 state = 1; 864 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, &kva, 865 BUS_DMA_NOWAIT)) { 866 printf("%s: can't map dma buffers (%d bytes)\n", 867 sc->sk_dev.dv_xname, SK_JMEM); 868 error = ENOBUFS; 869 goto out; 870 } 871 872 state = 2; 873 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 874 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 875 printf("%s: can't create dma map\n", sc->sk_dev.dv_xname); 876 error = ENOBUFS; 877 goto out; 878 } 879 880 state = 3; 881 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 882 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 883 printf("%s: can't load dma map\n", sc->sk_dev.dv_xname); 884 error = ENOBUFS; 885 goto out; 886 } 887 888 state = 4; 889 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 890 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 891 892 LIST_INIT(&sc_if->sk_jfree_listhead); 893 LIST_INIT(&sc_if->sk_jinuse_listhead); 894 895 /* 896 * Now divide it up into 9K pieces and save the addresses 897 * in an array. 898 */ 899 ptr = sc_if->sk_cdata.sk_jumbo_buf; 900 for (i = 0; i < SK_JSLOTS; i++) { 901 sc_if->sk_cdata.sk_jslots[i] = ptr; 902 ptr += SK_JLEN; 903 entry = malloc(sizeof(struct sk_jpool_entry), 904 M_DEVBUF, M_NOWAIT); 905 if (entry == NULL) { 906 printf("%s: no memory for jumbo buffer queue!\n", 907 sc->sk_dev.dv_xname); 908 error = ENOBUFS; 909 goto out; 910 } 911 entry->slot = i; 912 if (i) 913 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 914 entry, jpool_entries); 915 else 916 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 917 entry, jpool_entries); 918 } 919 out: 920 if (error != 0) { 921 switch (state) { 922 case 4: 923 bus_dmamap_unload(sc->sc_dmatag, 924 sc_if->sk_cdata.sk_rx_jumbo_map); 925 case 3: 926 bus_dmamap_destroy(sc->sc_dmatag, 927 sc_if->sk_cdata.sk_rx_jumbo_map); 928 case 2: 929 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 930 case 1: 931 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 932 break; 933 default: 934 break; 935 } 936 } 937 938 return (error); 939 } 940 941 /* 942 * Allocate a jumbo buffer. 943 */ 944 void * 945 sk_jalloc(struct sk_if_softc *sc_if) 946 { 947 struct sk_jpool_entry *entry; 948 949 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 950 951 if (entry == NULL) 952 return (NULL); 953 954 LIST_REMOVE(entry, jpool_entries); 955 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 956 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 957 } 958 959 /* 960 * Release a jumbo buffer. 961 */ 962 void 963 sk_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 964 { 965 struct sk_jpool_entry *entry; 966 struct sk_if_softc *sc; 967 int i, s; 968 969 /* Extract the softc struct pointer. */ 970 sc = (struct sk_if_softc *)arg; 971 972 if (sc == NULL) 973 panic("sk_jfree: can't find softc pointer!"); 974 975 /* calculate the slot this buffer belongs to */ 976 977 i = ((vaddr_t)buf 978 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 979 980 if ((i < 0) || (i >= SK_JSLOTS)) 981 panic("sk_jfree: asked to free buffer that we don't manage!"); 982 983 s = splvm(); 984 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 985 if (entry == NULL) 986 panic("sk_jfree: buffer not in use!"); 987 entry->slot = i; 988 LIST_REMOVE(entry, jpool_entries); 989 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 990 991 if (__predict_true(m != NULL)) 992 pool_cache_put(&mbpool_cache, m); 993 splx(s); 994 } 995 996 /* 997 * Set media options. 998 */ 999 int 1000 sk_ifmedia_upd(struct ifnet *ifp) 1001 { 1002 struct sk_if_softc *sc_if = ifp->if_softc; 1003 1004 (void) sk_init(ifp); 1005 mii_mediachg(&sc_if->sk_mii); 1006 return(0); 1007 } 1008 1009 /* 1010 * Report current media status. 1011 */ 1012 void 1013 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1014 { 1015 struct sk_if_softc *sc_if = ifp->if_softc; 1016 1017 mii_pollstat(&sc_if->sk_mii); 1018 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 1019 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 1020 } 1021 1022 int 1023 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1024 { 1025 struct sk_if_softc *sc_if = ifp->if_softc; 1026 struct sk_softc *sc = sc_if->sk_softc; 1027 struct ifreq *ifr = (struct ifreq *) data; 1028 /* struct ifaddr *ifa = (struct ifaddr *) data; */ 1029 struct mii_data *mii; 1030 int s, error = 0; 1031 1032 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1033 1034 s = splnet(); 1035 1036 switch(command) { 1037 1038 case SIOCSIFFLAGS: 1039 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1040 if (ifp->if_flags & IFF_UP) { 1041 if (ifp->if_flags & IFF_RUNNING && 1042 ifp->if_flags & IFF_PROMISC && 1043 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1044 switch(sc->sk_type) { 1045 case SK_GENESIS: 1046 SK_XM_SETBIT_4(sc_if, XM_MODE, 1047 XM_MODE_RX_PROMISC); 1048 break; 1049 case SK_YUKON: 1050 case SK_YUKON_LITE: 1051 case SK_YUKON_LP: 1052 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1053 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1054 break; 1055 } 1056 sk_setmulti(sc_if); 1057 } else if (ifp->if_flags & IFF_RUNNING && 1058 !(ifp->if_flags & IFF_PROMISC) && 1059 sc_if->sk_if_flags & IFF_PROMISC) { 1060 switch(sc->sk_type) { 1061 case SK_GENESIS: 1062 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1063 XM_MODE_RX_PROMISC); 1064 break; 1065 case SK_YUKON: 1066 case SK_YUKON_LITE: 1067 case SK_YUKON_LP: 1068 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1069 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1070 break; 1071 } 1072 1073 sk_setmulti(sc_if); 1074 } else 1075 (void) sk_init(ifp); 1076 } else { 1077 if (ifp->if_flags & IFF_RUNNING) 1078 sk_stop(ifp,0); 1079 } 1080 sc_if->sk_if_flags = ifp->if_flags; 1081 error = 0; 1082 break; 1083 1084 case SIOCGIFMEDIA: 1085 case SIOCSIFMEDIA: 1086 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 1087 mii = &sc_if->sk_mii; 1088 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1089 break; 1090 default: 1091 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1092 error = ether_ioctl(ifp, command, data); 1093 1094 if ( error == ENETRESET) { 1095 if (ifp->if_flags & IFF_RUNNING) { 1096 sk_setmulti(sc_if); 1097 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1098 } 1099 error = 0; 1100 } else if ( error ) { 1101 splx(s); 1102 return error; 1103 } 1104 break; 1105 } 1106 1107 splx(s); 1108 return(error); 1109 } 1110 1111 void 1112 sk_update_int_mod(struct sk_softc *sc) 1113 { 1114 u_int32_t sk_imtimer_ticks; 1115 1116 /* 1117 * Configure interrupt moderation. The moderation timer 1118 * defers interrupts specified in the interrupt moderation 1119 * timer mask based on the timeout specified in the interrupt 1120 * moderation timer init register. Each bit in the timer 1121 * register represents one tick, so to specify a timeout in 1122 * microseconds, we have to multiply by the correct number of 1123 * ticks-per-microsecond. 1124 */ 1125 switch (sc->sk_type) { 1126 case SK_GENESIS: 1127 sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1128 break; 1129 case SK_YUKON_EC: 1130 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1131 break; 1132 default: 1133 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1134 } 1135 aprint_verbose("%s: interrupt moderation is %d us\n", 1136 sc->sk_dev.dv_xname, sc->sk_int_mod); 1137 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1138 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1139 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1140 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1141 sc->sk_int_mod_pending = 0; 1142 } 1143 1144 /* 1145 * Lookup: Check the PCI vendor and device, and return a pointer to 1146 * The structure if the IDs match against our list. 1147 */ 1148 1149 static const struct sk_product * 1150 sk_lookup(const struct pci_attach_args *pa) 1151 { 1152 const struct sk_product *psk; 1153 1154 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1155 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1156 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1157 return (psk); 1158 } 1159 return (NULL); 1160 } 1161 1162 /* 1163 * Probe for a SysKonnect GEnesis chip. 1164 */ 1165 1166 int 1167 skc_probe(struct device *parent, struct cfdata *match, void *aux) 1168 { 1169 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1170 const struct sk_product *psk; 1171 pcireg_t subid; 1172 1173 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1174 1175 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1176 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1177 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1178 subid == SK_LINKSYS_EG1032_SUBID) 1179 return(1); 1180 1181 if ((psk = sk_lookup(pa))) { 1182 return(1); 1183 } 1184 return(0); 1185 } 1186 1187 /* 1188 * Force the GEnesis into reset, then bring it out of reset. 1189 */ 1190 void sk_reset(struct sk_softc *sc) 1191 { 1192 DPRINTFN(2, ("sk_reset\n")); 1193 1194 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1195 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1196 if (SK_YUKON_FAMILY(sc->sk_type)) 1197 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1198 1199 DELAY(1000); 1200 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1201 DELAY(2); 1202 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1203 if (SK_YUKON_FAMILY(sc->sk_type)) 1204 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1205 1206 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1207 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1208 CSR_READ_2(sc, SK_LINK_CTRL))); 1209 1210 if (sc->sk_type == SK_GENESIS) { 1211 /* Configure packet arbiter */ 1212 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1213 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1214 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1215 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1216 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1217 } 1218 1219 /* Enable RAM interface */ 1220 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1221 1222 sk_update_int_mod(sc); 1223 } 1224 1225 int 1226 sk_probe(struct device *parent, struct cfdata *match, void *aux) 1227 { 1228 struct skc_attach_args *sa = aux; 1229 1230 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1231 return(0); 1232 1233 return (1); 1234 } 1235 1236 /* 1237 * Each XMAC chip is attached as a separate logical IP interface. 1238 * Single port cards will have only one logical interface of course. 1239 */ 1240 void 1241 sk_attach(struct device *parent, struct device *self, void *aux) 1242 { 1243 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1244 struct sk_softc *sc = (struct sk_softc *)parent; 1245 struct skc_attach_args *sa = aux; 1246 struct sk_txmap_entry *entry; 1247 struct ifnet *ifp; 1248 bus_dma_segment_t seg; 1249 bus_dmamap_t dmamap; 1250 caddr_t kva; 1251 int i, rseg; 1252 1253 sc_if->sk_port = sa->skc_port; 1254 sc_if->sk_softc = sc; 1255 sc->sk_if[sa->skc_port] = sc_if; 1256 1257 if (sa->skc_port == SK_PORT_A) 1258 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1259 if (sa->skc_port == SK_PORT_B) 1260 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1261 1262 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1263 1264 /* 1265 * Get station address for this interface. Note that 1266 * dual port cards actually come with three station 1267 * addresses: one for each port, plus an extra. The 1268 * extra one is used by the SysKonnect driver software 1269 * as a 'virtual' station address for when both ports 1270 * are operating in failover mode. Currently we don't 1271 * use this extra address. 1272 */ 1273 for (i = 0; i < ETHER_ADDR_LEN; i++) 1274 sc_if->sk_enaddr[i] = 1275 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1276 1277 1278 aprint_normal(": Ethernet address %s\n", 1279 ether_sprintf(sc_if->sk_enaddr)); 1280 1281 /* 1282 * Set up RAM buffer addresses. The NIC will have a certain 1283 * amount of SRAM on it, somewhere between 512K and 2MB. We 1284 * need to divide this up a) between the transmitter and 1285 * receiver and b) between the two XMACs, if this is a 1286 * dual port NIC. Our algorithm is to divide up the memory 1287 * evenly so that everyone gets a fair share. 1288 */ 1289 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1290 u_int32_t chunk, val; 1291 1292 chunk = sc->sk_ramsize / 2; 1293 val = sc->sk_rboff / sizeof(u_int64_t); 1294 sc_if->sk_rx_ramstart = val; 1295 val += (chunk / sizeof(u_int64_t)); 1296 sc_if->sk_rx_ramend = val - 1; 1297 sc_if->sk_tx_ramstart = val; 1298 val += (chunk / sizeof(u_int64_t)); 1299 sc_if->sk_tx_ramend = val - 1; 1300 } else { 1301 u_int32_t chunk, val; 1302 1303 chunk = sc->sk_ramsize / 4; 1304 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1305 sizeof(u_int64_t); 1306 sc_if->sk_rx_ramstart = val; 1307 val += (chunk / sizeof(u_int64_t)); 1308 sc_if->sk_rx_ramend = val - 1; 1309 sc_if->sk_tx_ramstart = val; 1310 val += (chunk / sizeof(u_int64_t)); 1311 sc_if->sk_tx_ramend = val - 1; 1312 } 1313 1314 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1315 " tx_ramstart=%#x tx_ramend=%#x\n", 1316 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1317 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1318 1319 /* Read and save PHY type and set PHY address */ 1320 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1321 switch (sc_if->sk_phytype) { 1322 case SK_PHYTYPE_XMAC: 1323 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1324 break; 1325 case SK_PHYTYPE_BCOM: 1326 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1327 break; 1328 case SK_PHYTYPE_MARV_COPPER: 1329 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1330 break; 1331 default: 1332 aprint_error("%s: unsupported PHY type: %d\n", 1333 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1334 return; 1335 } 1336 1337 /* Allocate the descriptor queues. */ 1338 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1339 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1340 aprint_error("%s: can't alloc rx buffers\n", 1341 sc->sk_dev.dv_xname); 1342 goto fail; 1343 } 1344 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1345 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1346 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1347 sc_if->sk_dev.dv_xname, 1348 (u_long) sizeof(struct sk_ring_data)); 1349 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1350 goto fail; 1351 } 1352 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1353 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1354 &sc_if->sk_ring_map)) { 1355 aprint_error("%s: can't create dma map\n", 1356 sc_if->sk_dev.dv_xname); 1357 bus_dmamem_unmap(sc->sc_dmatag, kva, 1358 sizeof(struct sk_ring_data)); 1359 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1360 goto fail; 1361 } 1362 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1363 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1364 aprint_error("%s: can't load dma map\n", 1365 sc_if->sk_dev.dv_xname); 1366 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1367 bus_dmamem_unmap(sc->sc_dmatag, kva, 1368 sizeof(struct sk_ring_data)); 1369 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1370 goto fail; 1371 } 1372 1373 for (i = 0; i < SK_RX_RING_CNT; i++) 1374 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1375 1376 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1377 for (i = 0; i < SK_TX_RING_CNT; i++) { 1378 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1379 1380 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1381 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1382 aprint_error("%s: Can't create TX dmamap\n", 1383 sc_if->sk_dev.dv_xname); 1384 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1385 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1386 bus_dmamem_unmap(sc->sc_dmatag, kva, 1387 sizeof(struct sk_ring_data)); 1388 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1389 goto fail; 1390 } 1391 1392 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1393 if (!entry) { 1394 aprint_error("%s: Can't alloc txmap entry\n", 1395 sc_if->sk_dev.dv_xname); 1396 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1397 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1398 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1399 bus_dmamem_unmap(sc->sc_dmatag, kva, 1400 sizeof(struct sk_ring_data)); 1401 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1402 goto fail; 1403 } 1404 entry->dmamap = dmamap; 1405 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1406 } 1407 1408 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1409 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1410 1411 ifp = &sc_if->sk_ethercom.ec_if; 1412 /* Try to allocate memory for jumbo buffers. */ 1413 if (sk_alloc_jumbo_mem(sc_if)) { 1414 printf("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1415 goto fail; 1416 } 1417 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1418 | ETHERCAP_JUMBO_MTU; 1419 1420 ifp->if_softc = sc_if; 1421 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1422 ifp->if_ioctl = sk_ioctl; 1423 ifp->if_start = sk_start; 1424 ifp->if_stop = sk_stop; 1425 ifp->if_init = sk_init; 1426 ifp->if_watchdog = sk_watchdog; 1427 ifp->if_capabilities = 0; 1428 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1429 IFQ_SET_READY(&ifp->if_snd); 1430 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1431 1432 /* 1433 * Do miibus setup. 1434 */ 1435 switch (sc->sk_type) { 1436 case SK_GENESIS: 1437 sk_init_xmac(sc_if); 1438 break; 1439 case SK_YUKON: 1440 case SK_YUKON_LITE: 1441 case SK_YUKON_LP: 1442 sk_init_yukon(sc_if); 1443 break; 1444 default: 1445 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1446 sc->sk_type); 1447 } 1448 1449 DPRINTFN(2, ("sk_attach: 1\n")); 1450 1451 sc_if->sk_mii.mii_ifp = ifp; 1452 switch (sc->sk_type) { 1453 case SK_GENESIS: 1454 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1455 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1456 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1457 break; 1458 case SK_YUKON: 1459 case SK_YUKON_LITE: 1460 case SK_YUKON_LP: 1461 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1462 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1463 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1464 break; 1465 } 1466 1467 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1468 sk_ifmedia_upd, sk_ifmedia_sts); 1469 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1470 MII_OFFSET_ANY, 0); 1471 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1472 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1473 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1474 0, NULL); 1475 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1476 } 1477 else 1478 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1479 1480 callout_init(&sc_if->sk_tick_ch); 1481 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1482 1483 DPRINTFN(2, ("sk_attach: 1\n")); 1484 1485 /* 1486 * Call MI attach routines. 1487 */ 1488 if_attach(ifp); 1489 1490 ether_ifattach(ifp, sc_if->sk_enaddr); 1491 1492 #if NRND > 0 1493 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1494 RND_TYPE_NET, 0); 1495 #endif 1496 1497 DPRINTFN(2, ("sk_attach: end\n")); 1498 1499 return; 1500 1501 fail: 1502 sc->sk_if[sa->skc_port] = NULL; 1503 } 1504 1505 int 1506 skcprint(void *aux, const char *pnp) 1507 { 1508 struct skc_attach_args *sa = aux; 1509 1510 if (pnp) 1511 aprint_normal("sk port %c at %s", 1512 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1513 else 1514 aprint_normal(" port %c", 1515 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1516 return (UNCONF); 1517 } 1518 1519 /* 1520 * Attach the interface. Allocate softc structures, do ifmedia 1521 * setup and ethernet/BPF attach. 1522 */ 1523 void 1524 skc_attach(struct device *parent, struct device *self, void *aux) 1525 { 1526 struct sk_softc *sc = (struct sk_softc *)self; 1527 struct pci_attach_args *pa = aux; 1528 struct skc_attach_args skca; 1529 pci_chipset_tag_t pc = pa->pa_pc; 1530 #ifndef SK_USEIOSPACE 1531 pcireg_t memtype; 1532 #endif 1533 pci_intr_handle_t ih; 1534 const char *intrstr = NULL; 1535 bus_addr_t iobase; 1536 bus_size_t iosize; 1537 int rc, sk_nodenum; 1538 u_int32_t command; 1539 const char *revstr; 1540 const struct sysctlnode *node; 1541 1542 DPRINTFN(2, ("begin skc_attach\n")); 1543 1544 /* 1545 * Handle power management nonsense. 1546 */ 1547 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1548 1549 if (command == 0x01) { 1550 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1551 if (command & SK_PSTATE_MASK) { 1552 u_int32_t xiobase, membase, irq; 1553 1554 /* Save important PCI config data. */ 1555 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1556 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1557 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1558 1559 /* Reset the power state. */ 1560 aprint_normal("%s chip is in D%d power mode " 1561 "-- setting to D0\n", sc->sk_dev.dv_xname, 1562 command & SK_PSTATE_MASK); 1563 command &= 0xFFFFFFFC; 1564 pci_conf_write(pc, pa->pa_tag, 1565 SK_PCI_PWRMGMTCTRL, command); 1566 1567 /* Restore PCI config data. */ 1568 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1569 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1570 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1571 } 1572 } 1573 1574 /* 1575 * Map control/status registers. 1576 */ 1577 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1578 command |= PCI_COMMAND_IO_ENABLE | 1579 PCI_COMMAND_MEM_ENABLE | 1580 PCI_COMMAND_MASTER_ENABLE; 1581 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1582 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1583 1584 #ifdef SK_USEIOSPACE 1585 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1586 aprint_error(": failed to enable I/O ports!\n"); 1587 return; 1588 } 1589 /* 1590 * Map control/status registers. 1591 */ 1592 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1593 &sc->sk_btag, &sc->sk_bhandle, 1594 &iobase, &iosize)) { 1595 aprint_error(": can't find i/o space\n"); 1596 return; 1597 } 1598 #else 1599 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1600 aprint_error(": failed to enable memory mapping!\n"); 1601 return; 1602 } 1603 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1604 switch (memtype) { 1605 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1606 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1607 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1608 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1609 &iobase, &iosize) == 0) 1610 break; 1611 default: 1612 aprint_error("%s: can't find mem space\n", 1613 sc->sk_dev.dv_xname); 1614 return; 1615 } 1616 1617 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1618 #endif 1619 sc->sc_dmatag = pa->pa_dmat; 1620 1621 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1622 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1623 1624 /* bail out here if chip is not recognized */ 1625 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1626 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1627 goto fail; 1628 } 1629 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1630 1631 /* Allocate interrupt */ 1632 if (pci_intr_map(pa, &ih)) { 1633 aprint_error(": couldn't map interrupt\n"); 1634 goto fail; 1635 } 1636 1637 intrstr = pci_intr_string(pc, ih); 1638 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1639 if (sc->sk_intrhand == NULL) { 1640 aprint_error(": couldn't establish interrupt"); 1641 if (intrstr != NULL) 1642 aprint_normal(" at %s", intrstr); 1643 goto fail; 1644 } 1645 aprint_normal(": %s\n", intrstr); 1646 1647 /* Reset the adapter. */ 1648 sk_reset(sc); 1649 1650 /* Read and save vital product data from EEPROM. */ 1651 sk_vpd_read(sc); 1652 1653 if (sc->sk_type == SK_GENESIS) { 1654 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1655 /* Read and save RAM size and RAMbuffer offset */ 1656 switch(val) { 1657 case SK_RAMSIZE_512K_64: 1658 sc->sk_ramsize = 0x80000; 1659 sc->sk_rboff = SK_RBOFF_0; 1660 break; 1661 case SK_RAMSIZE_1024K_64: 1662 sc->sk_ramsize = 0x100000; 1663 sc->sk_rboff = SK_RBOFF_80000; 1664 break; 1665 case SK_RAMSIZE_1024K_128: 1666 sc->sk_ramsize = 0x100000; 1667 sc->sk_rboff = SK_RBOFF_0; 1668 break; 1669 case SK_RAMSIZE_2048K_128: 1670 sc->sk_ramsize = 0x200000; 1671 sc->sk_rboff = SK_RBOFF_0; 1672 break; 1673 default: 1674 aprint_error("%s: unknown ram size: %d\n", 1675 sc->sk_dev.dv_xname, val); 1676 goto fail_1; 1677 break; 1678 } 1679 1680 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1681 sc->sk_ramsize, sc->sk_ramsize / 1024, 1682 sc->sk_rboff)); 1683 } else { 1684 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1685 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1686 sc->sk_rboff = SK_RBOFF_0; 1687 1688 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1689 sc->sk_ramsize / 1024, sc->sk_ramsize, 1690 sc->sk_rboff)); 1691 } 1692 1693 /* Read and save physical media type */ 1694 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1695 case SK_PMD_1000BASESX: 1696 sc->sk_pmd = IFM_1000_SX; 1697 break; 1698 case SK_PMD_1000BASELX: 1699 sc->sk_pmd = IFM_1000_LX; 1700 break; 1701 case SK_PMD_1000BASECX: 1702 sc->sk_pmd = IFM_1000_CX; 1703 break; 1704 case SK_PMD_1000BASETX: 1705 case SK_PMD_1000BASETX_ALT: 1706 sc->sk_pmd = IFM_1000_T; 1707 break; 1708 default: 1709 aprint_error("%s: unknown media type: 0x%x\n", 1710 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1711 goto fail_1; 1712 } 1713 1714 /* determine whether to name it with vpd or just make it up */ 1715 /* Marvell Yukon VPD's can freqently be bogus */ 1716 1717 switch (pa->pa_id) { 1718 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1719 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1720 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1721 case PCI_PRODUCT_3COM_3C940: 1722 case PCI_PRODUCT_DLINK_DGE530T: 1723 case PCI_PRODUCT_DLINK_DGE560T: 1724 case PCI_PRODUCT_DLINK_DGE560T_2: 1725 case PCI_PRODUCT_LINKSYS_EG1032: 1726 case PCI_PRODUCT_LINKSYS_EG1064: 1727 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1728 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1729 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1730 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1731 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1732 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1733 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1734 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1735 sc->sk_name = sc->sk_vpd_prodname; 1736 break; 1737 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_SKNET): 1738 /* whoops yukon vpd prodname bears no resemblance to reality */ 1739 switch (sc->sk_type) { 1740 case SK_GENESIS: 1741 sc->sk_name = sc->sk_vpd_prodname; 1742 break; 1743 case SK_YUKON: 1744 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1745 break; 1746 case SK_YUKON_LITE: 1747 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1748 break; 1749 case SK_YUKON_LP: 1750 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1751 break; 1752 default: 1753 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1754 } 1755 1756 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1757 1758 if ( sc->sk_type == SK_YUKON ) { 1759 uint32_t flashaddr; 1760 uint8_t testbyte; 1761 1762 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1763 1764 /* test Flash-Address Register */ 1765 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1766 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1767 1768 if (testbyte != 0) { 1769 /* this is yukon lite Rev. A0 */ 1770 sc->sk_type = SK_YUKON_LITE; 1771 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1772 /* restore Flash-Address Register */ 1773 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1774 } 1775 } 1776 break; 1777 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_BELKIN): 1778 sc->sk_name = sc->sk_vpd_prodname; 1779 break; 1780 default: 1781 sc->sk_name = "Unknown Marvell"; 1782 } 1783 1784 1785 if ( sc->sk_type == SK_YUKON_LITE ) { 1786 switch (sc->sk_rev) { 1787 case SK_YUKON_LITE_REV_A0: 1788 revstr = "A0"; 1789 break; 1790 case SK_YUKON_LITE_REV_A1: 1791 revstr = "A1"; 1792 break; 1793 case SK_YUKON_LITE_REV_A3: 1794 revstr = "A3"; 1795 break; 1796 default: 1797 revstr = ""; 1798 } 1799 } else { 1800 revstr = ""; 1801 } 1802 1803 /* Announce the product name. */ 1804 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1805 sc->sk_name, revstr, sc->sk_rev); 1806 1807 skca.skc_port = SK_PORT_A; 1808 (void)config_found(&sc->sk_dev, &skca, skcprint); 1809 1810 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1811 skca.skc_port = SK_PORT_B; 1812 (void)config_found(&sc->sk_dev, &skca, skcprint); 1813 } 1814 1815 /* Turn on the 'driver is loaded' LED. */ 1816 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1817 1818 /* skc sysctl setup */ 1819 1820 sc->sk_int_mod = SK_IM_DEFAULT; 1821 sc->sk_int_mod_pending = 0; 1822 1823 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1824 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1825 SYSCTL_DESCR("skc per-controller controls"), 1826 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1827 CTL_EOL)) != 0) { 1828 aprint_normal("%s: couldn't create sysctl node\n", 1829 sc->sk_dev.dv_xname); 1830 goto fail_1; 1831 } 1832 1833 sk_nodenum = node->sysctl_num; 1834 1835 /* interrupt moderation time in usecs */ 1836 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1837 CTLFLAG_READWRITE, 1838 CTLTYPE_INT, "int_mod", 1839 SYSCTL_DESCR("sk interrupt moderation timer"), 1840 sk_sysctl_handler, 0, sc, 1841 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1842 CTL_EOL)) != 0) { 1843 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1844 sc->sk_dev.dv_xname); 1845 goto fail_1; 1846 } 1847 1848 return; 1849 1850 fail_1: 1851 pci_intr_disestablish(pc, sc->sk_intrhand); 1852 fail: 1853 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1854 } 1855 1856 int 1857 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1858 { 1859 struct sk_softc *sc = sc_if->sk_softc; 1860 struct sk_tx_desc *f = NULL; 1861 u_int32_t frag, cur, cnt = 0; 1862 int i; 1863 struct sk_txmap_entry *entry; 1864 bus_dmamap_t txmap; 1865 1866 DPRINTFN(3, ("sk_encap\n")); 1867 1868 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1869 if (entry == NULL) { 1870 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1871 return ENOBUFS; 1872 } 1873 txmap = entry->dmamap; 1874 1875 cur = frag = *txidx; 1876 1877 #ifdef SK_DEBUG 1878 if (skdebug >= 3) 1879 sk_dump_mbuf(m_head); 1880 #endif 1881 1882 /* 1883 * Start packing the mbufs in this chain into 1884 * the fragment pointers. Stop when we run out 1885 * of fragments or hit the end of the mbuf chain. 1886 */ 1887 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1888 BUS_DMA_NOWAIT)) { 1889 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1890 return(ENOBUFS); 1891 } 1892 1893 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1894 1895 /* Sync the DMA map. */ 1896 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1897 BUS_DMASYNC_PREWRITE); 1898 1899 for (i = 0; i < txmap->dm_nsegs; i++) { 1900 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1901 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1902 return(ENOBUFS); 1903 } 1904 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1905 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1906 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1907 if (cnt == 0) 1908 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1909 else 1910 f->sk_ctl |= SK_TXCTL_OWN; 1911 1912 cur = frag; 1913 SK_INC(frag, SK_TX_RING_CNT); 1914 cnt++; 1915 } 1916 1917 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1918 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1919 1920 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1921 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1922 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1923 1924 /* Sync descriptors before handing to chip */ 1925 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1926 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1927 1928 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1929 1930 /* Sync first descriptor to hand it off */ 1931 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1932 1933 sc_if->sk_cdata.sk_tx_cnt += cnt; 1934 1935 #ifdef SK_DEBUG 1936 if (skdebug >= 3) { 1937 struct sk_tx_desc *desc; 1938 u_int32_t idx; 1939 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1940 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1941 sk_dump_txdesc(desc, idx); 1942 } 1943 } 1944 #endif 1945 1946 *txidx = frag; 1947 1948 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1949 1950 return(0); 1951 } 1952 1953 void 1954 sk_start(struct ifnet *ifp) 1955 { 1956 struct sk_if_softc *sc_if = ifp->if_softc; 1957 struct sk_softc *sc = sc_if->sk_softc; 1958 struct mbuf *m_head = NULL; 1959 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1960 int pkts = 0; 1961 1962 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1963 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1964 1965 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1966 1967 IFQ_POLL(&ifp->if_snd, m_head); 1968 if (m_head == NULL) 1969 break; 1970 1971 /* 1972 * Pack the data into the transmit ring. If we 1973 * don't have room, set the OACTIVE flag and wait 1974 * for the NIC to drain the ring. 1975 */ 1976 if (sk_encap(sc_if, m_head, &idx)) { 1977 ifp->if_flags |= IFF_OACTIVE; 1978 break; 1979 } 1980 1981 /* now we are committed to transmit the packet */ 1982 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1983 pkts++; 1984 1985 /* 1986 * If there's a BPF listener, bounce a copy of this frame 1987 * to him. 1988 */ 1989 #if NBPFILTER > 0 1990 if (ifp->if_bpf) 1991 bpf_mtap(ifp->if_bpf, m_head); 1992 #endif 1993 } 1994 if (pkts == 0) 1995 return; 1996 1997 /* Transmit */ 1998 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1999 sc_if->sk_cdata.sk_tx_prod = idx; 2000 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2001 2002 /* Set a timeout in case the chip goes out to lunch. */ 2003 ifp->if_timer = 5; 2004 } 2005 } 2006 2007 2008 void 2009 sk_watchdog(struct ifnet *ifp) 2010 { 2011 struct sk_if_softc *sc_if = ifp->if_softc; 2012 2013 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 2014 (void) sk_init(ifp); 2015 } 2016 2017 void 2018 sk_shutdown(void * v) 2019 { 2020 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2021 struct sk_softc *sc = sc_if->sk_softc; 2022 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2023 2024 DPRINTFN(2, ("sk_shutdown\n")); 2025 sk_stop(ifp,1); 2026 2027 /* Turn off the 'driver is loaded' LED. */ 2028 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2029 2030 /* 2031 * Reset the GEnesis controller. Doing this should also 2032 * assert the resets on the attached XMAC(s). 2033 */ 2034 sk_reset(sc); 2035 } 2036 2037 void 2038 sk_rxeof(struct sk_if_softc *sc_if) 2039 { 2040 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2041 struct mbuf *m; 2042 struct sk_chain *cur_rx; 2043 struct sk_rx_desc *cur_desc; 2044 int i, cur, total_len = 0; 2045 u_int32_t rxstat; 2046 bus_dmamap_t dmamap; 2047 2048 i = sc_if->sk_cdata.sk_rx_prod; 2049 2050 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2051 2052 for (;;) { 2053 cur = i; 2054 2055 /* Sync the descriptor */ 2056 SK_CDRXSYNC(sc_if, cur, 2057 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2058 2059 if (sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl & SK_RXCTL_OWN) { 2060 /* Invalidate the descriptor -- it's not ready yet */ 2061 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2062 sc_if->sk_cdata.sk_rx_prod = i; 2063 break; 2064 } 2065 2066 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2067 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2068 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2069 2070 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2071 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2072 2073 rxstat = cur_desc->sk_xmac_rxstat; 2074 m = cur_rx->sk_mbuf; 2075 cur_rx->sk_mbuf = NULL; 2076 total_len = SK_RXBYTES(cur_desc->sk_ctl); 2077 2078 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2079 2080 SK_INC(i, SK_RX_RING_CNT); 2081 2082 if (rxstat & XM_RXSTAT_ERRFRAME) { 2083 ifp->if_ierrors++; 2084 sk_newbuf(sc_if, cur, m, dmamap); 2085 continue; 2086 } 2087 2088 /* 2089 * Try to allocate a new jumbo buffer. If that 2090 * fails, copy the packet to mbufs and put the 2091 * jumbo buffer back in the ring so it can be 2092 * re-used. If allocating mbufs fails, then we 2093 * have to drop the packet. 2094 */ 2095 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2096 struct mbuf *m0; 2097 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2098 total_len + ETHER_ALIGN, 0, ifp, NULL); 2099 sk_newbuf(sc_if, cur, m, dmamap); 2100 if (m0 == NULL) { 2101 printf("%s: no receive buffers " 2102 "available -- packet dropped!\n", 2103 sc_if->sk_dev.dv_xname); 2104 ifp->if_ierrors++; 2105 continue; 2106 } 2107 m_adj(m0, ETHER_ALIGN); 2108 m = m0; 2109 } else { 2110 m->m_pkthdr.rcvif = ifp; 2111 m->m_pkthdr.len = m->m_len = total_len; 2112 } 2113 2114 ifp->if_ipackets++; 2115 2116 #if NBPFILTER > 0 2117 if (ifp->if_bpf) 2118 bpf_mtap(ifp->if_bpf, m); 2119 #endif 2120 /* pass it on. */ 2121 (*ifp->if_input)(ifp, m); 2122 } 2123 } 2124 2125 void 2126 sk_txeof(struct sk_if_softc *sc_if) 2127 { 2128 struct sk_softc *sc = sc_if->sk_softc; 2129 struct sk_tx_desc *cur_tx; 2130 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2131 u_int32_t idx; 2132 struct sk_txmap_entry *entry; 2133 2134 DPRINTFN(3, ("sk_txeof\n")); 2135 2136 /* 2137 * Go through our tx ring and free mbufs for those 2138 * frames that have been sent. 2139 */ 2140 idx = sc_if->sk_cdata.sk_tx_cons; 2141 while(idx != sc_if->sk_cdata.sk_tx_prod) { 2142 SK_CDTXSYNC(sc_if, idx, 1, 2143 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2144 2145 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2146 #ifdef SK_DEBUG 2147 if (skdebug >= 3) 2148 sk_dump_txdesc(cur_tx, idx); 2149 #endif 2150 if (cur_tx->sk_ctl & SK_TXCTL_OWN) { 2151 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2152 break; 2153 } 2154 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 2155 ifp->if_opackets++; 2156 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2157 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2158 2159 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2160 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2161 2162 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2163 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2164 2165 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2166 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2167 link); 2168 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2169 } 2170 sc_if->sk_cdata.sk_tx_cnt--; 2171 SK_INC(idx, SK_TX_RING_CNT); 2172 } 2173 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2174 ifp->if_timer = 0; 2175 else /* nudge chip to keep tx ring moving */ 2176 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2177 2178 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2179 ifp->if_flags &= ~IFF_OACTIVE; 2180 2181 sc_if->sk_cdata.sk_tx_cons = idx; 2182 } 2183 2184 void 2185 sk_tick(void *xsc_if) 2186 { 2187 struct sk_if_softc *sc_if = xsc_if; 2188 struct mii_data *mii = &sc_if->sk_mii; 2189 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2190 int i; 2191 2192 DPRINTFN(3, ("sk_tick\n")); 2193 2194 if (!(ifp->if_flags & IFF_UP)) 2195 return; 2196 2197 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2198 sk_intr_bcom(sc_if); 2199 return; 2200 } 2201 2202 /* 2203 * According to SysKonnect, the correct way to verify that 2204 * the link has come back up is to poll bit 0 of the GPIO 2205 * register three times. This pin has the signal from the 2206 * link sync pin connected to it; if we read the same link 2207 * state 3 times in a row, we know the link is up. 2208 */ 2209 for (i = 0; i < 3; i++) { 2210 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2211 break; 2212 } 2213 2214 if (i != 3) { 2215 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2216 return; 2217 } 2218 2219 /* Turn the GP0 interrupt back on. */ 2220 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2221 SK_XM_READ_2(sc_if, XM_ISR); 2222 mii_tick(mii); 2223 mii_pollstat(mii); 2224 callout_stop(&sc_if->sk_tick_ch); 2225 } 2226 2227 void 2228 sk_intr_bcom(struct sk_if_softc *sc_if) 2229 { 2230 struct mii_data *mii = &sc_if->sk_mii; 2231 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2232 int status; 2233 2234 2235 DPRINTFN(3, ("sk_intr_bcom\n")); 2236 2237 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2238 2239 /* 2240 * Read the PHY interrupt register to make sure 2241 * we clear any pending interrupts. 2242 */ 2243 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2244 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2245 2246 if (!(ifp->if_flags & IFF_RUNNING)) { 2247 sk_init_xmac(sc_if); 2248 return; 2249 } 2250 2251 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2252 int lstat; 2253 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2254 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2255 2256 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2257 mii_mediachg(mii); 2258 /* Turn off the link LED. */ 2259 SK_IF_WRITE_1(sc_if, 0, 2260 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2261 sc_if->sk_link = 0; 2262 } else if (status & BRGPHY_ISR_LNK_CHG) { 2263 sk_xmac_miibus_writereg((struct device *)sc_if, 2264 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2265 mii_tick(mii); 2266 sc_if->sk_link = 1; 2267 /* Turn on the link LED. */ 2268 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2269 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2270 SK_LINKLED_BLINK_OFF); 2271 mii_pollstat(mii); 2272 } else { 2273 mii_tick(mii); 2274 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2275 } 2276 } 2277 2278 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2279 } 2280 2281 void 2282 sk_intr_xmac(struct sk_if_softc *sc_if) 2283 { 2284 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2285 2286 DPRINTFN(3, ("sk_intr_xmac\n")); 2287 2288 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2289 if (status & XM_ISR_GP0_SET) { 2290 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2291 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2292 } 2293 2294 if (status & XM_ISR_AUTONEG_DONE) { 2295 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2296 } 2297 } 2298 2299 if (status & XM_IMR_TX_UNDERRUN) 2300 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2301 2302 if (status & XM_IMR_RX_OVERRUN) 2303 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2304 } 2305 2306 void 2307 sk_intr_yukon(sc_if) 2308 struct sk_if_softc *sc_if; 2309 { 2310 int status; 2311 2312 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2313 2314 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2315 } 2316 2317 int 2318 sk_intr(void *xsc) 2319 { 2320 struct sk_softc *sc = xsc; 2321 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2322 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2323 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2324 u_int32_t status; 2325 int claimed = 0; 2326 2327 if (sc_if0 != NULL) 2328 ifp0 = &sc_if0->sk_ethercom.ec_if; 2329 if (sc_if1 != NULL) 2330 ifp1 = &sc_if1->sk_ethercom.ec_if; 2331 2332 for (;;) { 2333 status = CSR_READ_4(sc, SK_ISSR); 2334 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2335 2336 if (!(status & sc->sk_intrmask)) 2337 break; 2338 2339 claimed = 1; 2340 2341 /* Handle receive interrupts first. */ 2342 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2343 sk_rxeof(sc_if0); 2344 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2345 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2346 } 2347 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2348 sk_rxeof(sc_if1); 2349 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2350 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2351 } 2352 2353 /* Then transmit interrupts. */ 2354 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2355 sk_txeof(sc_if0); 2356 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2357 SK_TXBMU_CLR_IRQ_EOF); 2358 } 2359 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2360 sk_txeof(sc_if1); 2361 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2362 SK_TXBMU_CLR_IRQ_EOF); 2363 } 2364 2365 /* Then MAC interrupts. */ 2366 if (sc_if0 && (status & SK_ISR_MAC1) && 2367 (ifp0->if_flags & IFF_RUNNING)) { 2368 if (sc->sk_type == SK_GENESIS) 2369 sk_intr_xmac(sc_if0); 2370 else 2371 sk_intr_yukon(sc_if0); 2372 } 2373 2374 if (sc_if1 && (status & SK_ISR_MAC2) && 2375 (ifp1->if_flags & IFF_RUNNING)) { 2376 if (sc->sk_type == SK_GENESIS) 2377 sk_intr_xmac(sc_if1); 2378 else 2379 sk_intr_yukon(sc_if1); 2380 2381 } 2382 2383 if (status & SK_ISR_EXTERNAL_REG) { 2384 if (sc_if0 != NULL && 2385 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2386 sk_intr_bcom(sc_if0); 2387 2388 if (sc_if1 != NULL && 2389 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2390 sk_intr_bcom(sc_if1); 2391 } 2392 } 2393 2394 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2395 2396 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2397 sk_start(ifp0); 2398 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2399 sk_start(ifp1); 2400 2401 #if NRND > 0 2402 if (RND_ENABLED(&sc->rnd_source)) 2403 rnd_add_uint32(&sc->rnd_source, status); 2404 #endif 2405 2406 if (sc->sk_int_mod_pending) 2407 sk_update_int_mod(sc); 2408 2409 return (claimed); 2410 } 2411 2412 void 2413 sk_init_xmac(struct sk_if_softc *sc_if) 2414 { 2415 struct sk_softc *sc = sc_if->sk_softc; 2416 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2417 static const struct sk_bcom_hack bhack[] = { 2418 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2419 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2420 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2421 { 0, 0 } }; 2422 2423 DPRINTFN(1, ("sk_init_xmac\n")); 2424 2425 /* Unreset the XMAC. */ 2426 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2427 DELAY(1000); 2428 2429 /* Reset the XMAC's internal state. */ 2430 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2431 2432 /* Save the XMAC II revision */ 2433 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2434 2435 /* 2436 * Perform additional initialization for external PHYs, 2437 * namely for the 1000baseTX cards that use the XMAC's 2438 * GMII mode. 2439 */ 2440 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2441 int i = 0; 2442 u_int32_t val; 2443 2444 /* Take PHY out of reset. */ 2445 val = sk_win_read_4(sc, SK_GPIO); 2446 if (sc_if->sk_port == SK_PORT_A) 2447 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2448 else 2449 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2450 sk_win_write_4(sc, SK_GPIO, val); 2451 2452 /* Enable GMII mode on the XMAC. */ 2453 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2454 2455 sk_xmac_miibus_writereg((struct device *)sc_if, 2456 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2457 DELAY(10000); 2458 sk_xmac_miibus_writereg((struct device *)sc_if, 2459 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2460 2461 /* 2462 * Early versions of the BCM5400 apparently have 2463 * a bug that requires them to have their reserved 2464 * registers initialized to some magic values. I don't 2465 * know what the numbers do, I'm just the messenger. 2466 */ 2467 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2468 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2469 while(bhack[i].reg) { 2470 sk_xmac_miibus_writereg((struct device *)sc_if, 2471 SK_PHYADDR_BCOM, bhack[i].reg, 2472 bhack[i].val); 2473 i++; 2474 } 2475 } 2476 } 2477 2478 /* Set station address */ 2479 SK_XM_WRITE_2(sc_if, XM_PAR0, 2480 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2481 SK_XM_WRITE_2(sc_if, XM_PAR1, 2482 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2483 SK_XM_WRITE_2(sc_if, XM_PAR2, 2484 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2485 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2486 2487 if (ifp->if_flags & IFF_PROMISC) { 2488 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2489 } else { 2490 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2491 } 2492 2493 if (ifp->if_flags & IFF_BROADCAST) { 2494 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2495 } else { 2496 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2497 } 2498 2499 /* We don't need the FCS appended to the packet. */ 2500 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2501 2502 /* We want short frames padded to 60 bytes. */ 2503 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2504 2505 /* 2506 * Enable the reception of all error frames. This is is 2507 * a necessary evil due to the design of the XMAC. The 2508 * XMAC's receive FIFO is only 8K in size, however jumbo 2509 * frames can be up to 9000 bytes in length. When bad 2510 * frame filtering is enabled, the XMAC's RX FIFO operates 2511 * in 'store and forward' mode. For this to work, the 2512 * entire frame has to fit into the FIFO, but that means 2513 * that jumbo frames larger than 8192 bytes will be 2514 * truncated. Disabling all bad frame filtering causes 2515 * the RX FIFO to operate in streaming mode, in which 2516 * case the XMAC will start transfering frames out of the 2517 * RX FIFO as soon as the FIFO threshold is reached. 2518 */ 2519 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2520 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2521 XM_MODE_RX_INRANGELEN); 2522 2523 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2524 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2525 else 2526 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2527 2528 /* 2529 * Bump up the transmit threshold. This helps hold off transmit 2530 * underruns when we're blasting traffic from both ports at once. 2531 */ 2532 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2533 2534 /* Set multicast filter */ 2535 sk_setmulti(sc_if); 2536 2537 /* Clear and enable interrupts */ 2538 SK_XM_READ_2(sc_if, XM_ISR); 2539 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2540 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2541 else 2542 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2543 2544 /* Configure MAC arbiter */ 2545 switch(sc_if->sk_xmac_rev) { 2546 case XM_XMAC_REV_B2: 2547 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2548 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2549 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2550 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2551 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2552 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2553 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2554 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2555 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2556 break; 2557 case XM_XMAC_REV_C1: 2558 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2559 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2560 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2561 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2562 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2563 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2564 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2565 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2566 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2567 break; 2568 default: 2569 break; 2570 } 2571 sk_win_write_2(sc, SK_MACARB_CTL, 2572 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2573 2574 sc_if->sk_link = 1; 2575 } 2576 2577 void sk_init_yukon(sc_if) 2578 struct sk_if_softc *sc_if; 2579 { 2580 u_int32_t /*mac, */phy; 2581 u_int16_t reg; 2582 struct sk_softc *sc; 2583 int i; 2584 2585 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2586 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2587 2588 sc = sc_if->sk_softc; 2589 if (sc->sk_type == SK_YUKON_LITE && 2590 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2591 /* Take PHY out of reset. */ 2592 sk_win_write_4(sc, SK_GPIO, 2593 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2594 } 2595 2596 2597 /* GMAC and GPHY Reset */ 2598 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2599 2600 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2601 2602 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2603 DELAY(1000); 2604 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2605 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2606 DELAY(1000); 2607 2608 2609 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2610 2611 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2612 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2613 2614 switch(sc_if->sk_softc->sk_pmd) { 2615 case IFM_1000_SX: 2616 case IFM_1000_LX: 2617 phy |= SK_GPHY_FIBER; 2618 break; 2619 2620 case IFM_1000_CX: 2621 case IFM_1000_T: 2622 phy |= SK_GPHY_COPPER; 2623 break; 2624 } 2625 2626 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2627 2628 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2629 DELAY(1000); 2630 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2631 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2632 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2633 2634 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2635 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2636 2637 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2638 2639 /* unused read of the interrupt source register */ 2640 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2641 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2642 2643 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2644 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2645 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2646 2647 /* MIB Counter Clear Mode set */ 2648 reg |= YU_PAR_MIB_CLR; 2649 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2650 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2651 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2652 2653 /* MIB Counter Clear Mode clear */ 2654 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2655 reg &= ~YU_PAR_MIB_CLR; 2656 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2657 2658 /* receive control reg */ 2659 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2660 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2661 YU_RCR_CRCR); 2662 2663 /* transmit parameter register */ 2664 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2665 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2666 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2667 2668 /* serial mode register */ 2669 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2670 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2671 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2672 YU_SMR_IPG_DATA(0x1e)); 2673 2674 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2675 /* Setup Yukon's address */ 2676 for (i = 0; i < 3; i++) { 2677 /* Write Source Address 1 (unicast filter) */ 2678 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2679 sc_if->sk_enaddr[i * 2] | 2680 sc_if->sk_enaddr[i * 2 + 1] << 8); 2681 } 2682 2683 for (i = 0; i < 3; i++) { 2684 reg = sk_win_read_2(sc_if->sk_softc, 2685 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2686 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2687 } 2688 2689 /* Set multicast filter */ 2690 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2691 sk_setmulti(sc_if); 2692 2693 /* enable interrupt mask for counter overflows */ 2694 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2695 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2696 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2697 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2698 2699 /* Configure RX MAC FIFO */ 2700 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2701 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2702 2703 /* Configure TX MAC FIFO */ 2704 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2705 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2706 2707 DPRINTFN(6, ("sk_init_yukon: end\n")); 2708 } 2709 2710 /* 2711 * Note that to properly initialize any part of the GEnesis chip, 2712 * you first have to take it out of reset mode. 2713 */ 2714 int 2715 sk_init(struct ifnet *ifp) 2716 { 2717 struct sk_if_softc *sc_if = ifp->if_softc; 2718 struct sk_softc *sc = sc_if->sk_softc; 2719 struct mii_data *mii = &sc_if->sk_mii; 2720 int s; 2721 u_int32_t imr, sk_imtimer_ticks; 2722 2723 DPRINTFN(1, ("sk_init\n")); 2724 2725 s = splnet(); 2726 2727 if (ifp->if_flags & IFF_RUNNING) { 2728 splx(s); 2729 return 0; 2730 } 2731 2732 /* Cancel pending I/O and free all RX/TX buffers. */ 2733 sk_stop(ifp,0); 2734 2735 if (sc->sk_type == SK_GENESIS) { 2736 /* Configure LINK_SYNC LED */ 2737 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2738 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2739 SK_LINKLED_LINKSYNC_ON); 2740 2741 /* Configure RX LED */ 2742 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2743 SK_RXLEDCTL_COUNTER_START); 2744 2745 /* Configure TX LED */ 2746 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2747 SK_TXLEDCTL_COUNTER_START); 2748 } 2749 2750 /* Configure I2C registers */ 2751 2752 /* Configure XMAC(s) */ 2753 switch (sc->sk_type) { 2754 case SK_GENESIS: 2755 sk_init_xmac(sc_if); 2756 break; 2757 case SK_YUKON: 2758 case SK_YUKON_LITE: 2759 case SK_YUKON_LP: 2760 sk_init_yukon(sc_if); 2761 break; 2762 } 2763 mii_mediachg(mii); 2764 2765 if (sc->sk_type == SK_GENESIS) { 2766 /* Configure MAC FIFOs */ 2767 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2768 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2769 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2770 2771 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2772 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2773 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2774 } 2775 2776 /* Configure transmit arbiter(s) */ 2777 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2778 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2779 2780 /* Configure RAMbuffers */ 2781 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2782 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2783 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2784 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2785 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2786 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2787 2788 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2789 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2790 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2791 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2792 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2793 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2794 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2795 2796 /* Configure BMUs */ 2797 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2798 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2799 SK_RX_RING_ADDR(sc_if, 0)); 2800 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2801 2802 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2803 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2804 SK_TX_RING_ADDR(sc_if, 0)); 2805 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2806 2807 /* Init descriptors */ 2808 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2809 printf("%s: initialization failed: no " 2810 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2811 sk_stop(ifp,0); 2812 splx(s); 2813 return(ENOBUFS); 2814 } 2815 2816 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2817 printf("%s: initialization failed: no " 2818 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2819 sk_stop(ifp,0); 2820 splx(s); 2821 return(ENOBUFS); 2822 } 2823 2824 /* Set interrupt moderation if changed via sysctl. */ 2825 switch (sc->sk_type) { 2826 case SK_GENESIS: 2827 sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2828 break; 2829 case SK_YUKON_EC: 2830 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2831 break; 2832 default: 2833 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2834 } 2835 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2836 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2837 sk_win_write_4(sc, SK_IMTIMERINIT, 2838 SK_IM_USECS(sc->sk_int_mod)); 2839 aprint_verbose("%s: interrupt moderation is %d us\n", 2840 sc->sk_dev.dv_xname, sc->sk_int_mod); 2841 } 2842 2843 /* Configure interrupt handling */ 2844 CSR_READ_4(sc, SK_ISSR); 2845 if (sc_if->sk_port == SK_PORT_A) 2846 sc->sk_intrmask |= SK_INTRS1; 2847 else 2848 sc->sk_intrmask |= SK_INTRS2; 2849 2850 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2851 2852 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2853 2854 /* Start BMUs. */ 2855 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2856 2857 if (sc->sk_type == SK_GENESIS) { 2858 /* Enable XMACs TX and RX state machines */ 2859 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2860 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2861 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2862 } 2863 2864 if (SK_YUKON_FAMILY(sc->sk_type)) { 2865 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2866 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2867 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2868 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2869 } 2870 2871 2872 ifp->if_flags |= IFF_RUNNING; 2873 ifp->if_flags &= ~IFF_OACTIVE; 2874 2875 splx(s); 2876 return(0); 2877 } 2878 2879 void 2880 sk_stop(struct ifnet *ifp, int disable) 2881 { 2882 struct sk_if_softc *sc_if = ifp->if_softc; 2883 struct sk_softc *sc = sc_if->sk_softc; 2884 //struct sk_txmap_entry *dma; 2885 int i; 2886 2887 DPRINTFN(1, ("sk_stop\n")); 2888 2889 callout_stop(&sc_if->sk_tick_ch); 2890 2891 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2892 u_int32_t val; 2893 2894 /* Put PHY back into reset. */ 2895 val = sk_win_read_4(sc, SK_GPIO); 2896 if (sc_if->sk_port == SK_PORT_A) { 2897 val |= SK_GPIO_DIR0; 2898 val &= ~SK_GPIO_DAT0; 2899 } else { 2900 val |= SK_GPIO_DIR2; 2901 val &= ~SK_GPIO_DAT2; 2902 } 2903 sk_win_write_4(sc, SK_GPIO, val); 2904 } 2905 2906 /* Turn off various components of this interface. */ 2907 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2908 switch (sc->sk_type) { 2909 case SK_GENESIS: 2910 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2911 SK_TXMACCTL_XMAC_RESET); 2912 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2913 break; 2914 case SK_YUKON: 2915 case SK_YUKON_LITE: 2916 case SK_YUKON_LP: 2917 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2918 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2919 break; 2920 } 2921 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2922 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2923 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2924 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2925 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2926 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2927 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2928 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2929 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2930 2931 /* Disable interrupts */ 2932 if (sc_if->sk_port == SK_PORT_A) 2933 sc->sk_intrmask &= ~SK_INTRS1; 2934 else 2935 sc->sk_intrmask &= ~SK_INTRS2; 2936 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2937 2938 SK_XM_READ_2(sc_if, XM_ISR); 2939 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2940 2941 /* Free RX and TX mbufs still in the queues. */ 2942 for (i = 0; i < SK_RX_RING_CNT; i++) { 2943 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2944 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2945 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2946 } 2947 } 2948 2949 for (i = 0; i < SK_TX_RING_CNT; i++) { 2950 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2951 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2952 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2953 } 2954 } 2955 2956 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2957 } 2958 2959 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2960 2961 /* 2962 struct cfdriver skc_cd = { 2963 0, "skc", DV_DULL 2964 }; 2965 */ 2966 2967 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2968 2969 /* 2970 struct cfdriver sk_cd = { 2971 0, "sk", DV_IFNET 2972 }; 2973 */ 2974 2975 #ifdef SK_DEBUG 2976 void 2977 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2978 { 2979 #define DESC_PRINT(X) \ 2980 if (desc->X) \ 2981 printf("txdesc[%d]." #X "=%#x\n", \ 2982 idx, desc->X); 2983 2984 DESC_PRINT(sk_ctl); 2985 DESC_PRINT(sk_next); 2986 DESC_PRINT(sk_data_lo); 2987 DESC_PRINT(sk_data_hi); 2988 DESC_PRINT(sk_xmac_txstat); 2989 DESC_PRINT(sk_rsvd0); 2990 DESC_PRINT(sk_csum_startval); 2991 DESC_PRINT(sk_csum_startpos); 2992 DESC_PRINT(sk_csum_writepos); 2993 DESC_PRINT(sk_rsvd1); 2994 #undef PRINT 2995 } 2996 2997 void 2998 sk_dump_bytes(const char *data, int len) 2999 { 3000 int c, i, j; 3001 3002 for (i = 0; i < len; i += 16) { 3003 printf("%08x ", i); 3004 c = len - i; 3005 if (c > 16) c = 16; 3006 3007 for (j = 0; j < c; j++) { 3008 printf("%02x ", data[i + j] & 0xff); 3009 if ((j & 0xf) == 7 && j > 0) 3010 printf(" "); 3011 } 3012 3013 for (; j < 16; j++) 3014 printf(" "); 3015 printf(" "); 3016 3017 for (j = 0; j < c; j++) { 3018 int ch = data[i + j] & 0xff; 3019 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3020 } 3021 3022 printf("\n"); 3023 3024 if (c < 16) 3025 break; 3026 } 3027 } 3028 3029 void 3030 sk_dump_mbuf(struct mbuf *m) 3031 { 3032 int count = m->m_pkthdr.len; 3033 3034 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3035 3036 while (count > 0 && m) { 3037 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3038 m, m->m_data, m->m_len); 3039 sk_dump_bytes(mtod(m, char *), m->m_len); 3040 3041 count -= m->m_len; 3042 m = m->m_next; 3043 } 3044 } 3045 #endif 3046 3047 static int 3048 sk_sysctl_handler(SYSCTLFN_ARGS) 3049 { 3050 int error, t; 3051 struct sysctlnode node; 3052 struct sk_softc *sc; 3053 3054 node = *rnode; 3055 sc = node.sysctl_data; 3056 t = sc->sk_int_mod; 3057 node.sysctl_data = &t; 3058 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3059 if (error || newp == NULL) 3060 return (error); 3061 3062 if (t < SK_IM_MIN || t > SK_IM_MAX) 3063 return (EINVAL); 3064 3065 /* update the softc with sysctl-changed value, and mark 3066 for hardware update */ 3067 sc->sk_int_mod = t; 3068 sc->sk_int_mod_pending = 1; 3069 return (0); 3070 } 3071 3072 /* 3073 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3074 * set up in skc_attach() 3075 */ 3076 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3077 { 3078 int rc; 3079 const struct sysctlnode *node; 3080 3081 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3082 0, CTLTYPE_NODE, "hw", NULL, 3083 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3084 goto err; 3085 } 3086 3087 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3088 0, CTLTYPE_NODE, "sk", 3089 SYSCTL_DESCR("sk interface controls"), 3090 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3091 goto err; 3092 } 3093 3094 sk_root_num = node->sysctl_num; 3095 return; 3096 3097 err: 3098 printf("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3099 } 3100
Indexes created Tue Sep 23 07:09:52 GMT 2025