if_sk.c revision 1.29
1 /* $NetBSD: if_sk.c,v 1.29 2006/08/22 06:24:10 riz Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 #include "rnd.h" 126 127 #include <sys/param.h> 128 #include <sys/systm.h> 129 #include <sys/sockio.h> 130 #include <sys/mbuf.h> 131 #include <sys/malloc.h> 132 #include <sys/kernel.h> 133 #include <sys/socket.h> 134 #include <sys/device.h> 135 #include <sys/queue.h> 136 #include <sys/callout.h> 137 #include <sys/sysctl.h> 138 #include <sys/endian.h> 139 140 #include <net/if.h> 141 #include <net/if_dl.h> 142 #include <net/if_types.h> 143 144 #ifdef INET 145 #include <netinet/in.h> 146 #include <netinet/in_systm.h> 147 #include <netinet/in_var.h> 148 #include <netinet/ip.h> 149 #include <netinet/if_ether.h> 150 #endif 151 152 #include <net/if_media.h> 153 154 #if NBPFILTER > 0 155 #include <net/bpf.h> 156 #endif 157 #if NRND > 0 158 #include <sys/rnd.h> 159 #endif 160 161 #include <dev/mii/mii.h> 162 #include <dev/mii/miivar.h> 163 #include <dev/mii/brgphyreg.h> 164 165 #include <dev/pci/pcireg.h> 166 #include <dev/pci/pcivar.h> 167 #include <dev/pci/pcidevs.h> 168 169 #define SK_VERBOSE 170 /* #define SK_USEIOSPACE */ 171 172 #include <dev/pci/if_skreg.h> 173 #include <dev/pci/if_skvar.h> 174 175 int skc_probe(struct device *, struct cfdata *, void *); 176 void skc_attach(struct device *, struct device *self, void *aux); 177 int sk_probe(struct device *, struct cfdata *, void *); 178 void sk_attach(struct device *, struct device *self, void *aux); 179 int skcprint(void *, const char *); 180 int sk_intr(void *); 181 void sk_intr_bcom(struct sk_if_softc *); 182 void sk_intr_xmac(struct sk_if_softc *); 183 void sk_intr_yukon(struct sk_if_softc *); 184 void sk_rxeof(struct sk_if_softc *); 185 void sk_txeof(struct sk_if_softc *); 186 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 187 void sk_start(struct ifnet *); 188 int sk_ioctl(struct ifnet *, u_long, caddr_t); 189 int sk_init(struct ifnet *); 190 void sk_init_xmac(struct sk_if_softc *); 191 void sk_init_yukon(struct sk_if_softc *); 192 void sk_stop(struct ifnet *, int); 193 void sk_watchdog(struct ifnet *); 194 void sk_shutdown(void *); 195 int sk_ifmedia_upd(struct ifnet *); 196 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 197 void sk_reset(struct sk_softc *); 198 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 199 int sk_alloc_jumbo_mem(struct sk_if_softc *); 200 void sk_free_jumbo_mem(struct sk_if_softc *); 201 void *sk_jalloc(struct sk_if_softc *); 202 void sk_jfree(struct mbuf *, caddr_t, size_t, void *); 203 int sk_init_rx_ring(struct sk_if_softc *); 204 int sk_init_tx_ring(struct sk_if_softc *); 205 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 206 void sk_vpd_read_res(struct sk_softc *, 207 struct vpd_res *, int); 208 void sk_vpd_read(struct sk_softc *); 209 210 void sk_update_int_mod(struct sk_softc *); 211 212 int sk_xmac_miibus_readreg(struct device *, int, int); 213 void sk_xmac_miibus_writereg(struct device *, int, int, int); 214 void sk_xmac_miibus_statchg(struct device *); 215 216 int sk_marv_miibus_readreg(struct device *, int, int); 217 void sk_marv_miibus_writereg(struct device *, int, int, int); 218 void sk_marv_miibus_statchg(struct device *); 219 220 u_int32_t sk_xmac_hash(caddr_t); 221 u_int32_t sk_yukon_hash(caddr_t); 222 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 223 void sk_setmulti(struct sk_if_softc *); 224 void sk_tick(void *); 225 226 /* #define SK_DEBUG 2 */ 227 #ifdef SK_DEBUG 228 #define DPRINTF(x) if (skdebug) printf x 229 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 230 int skdebug = SK_DEBUG; 231 232 void sk_dump_txdesc(struct sk_tx_desc *, int); 233 void sk_dump_mbuf(struct mbuf *); 234 void sk_dump_bytes(const char *, int); 235 #else 236 #define DPRINTF(x) 237 #define DPRINTFN(n,x) 238 #endif 239 240 #define SK_SETBIT(sc, reg, x) \ 241 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 242 243 #define SK_CLRBIT(sc, reg, x) \ 244 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 245 246 #define SK_WIN_SETBIT_4(sc, reg, x) \ 247 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 248 249 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 250 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 251 252 #define SK_WIN_SETBIT_2(sc, reg, x) \ 253 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 254 255 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 256 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 257 258 static int sk_sysctl_handler(SYSCTLFN_PROTO); 259 static int sk_root_num; 260 261 /* supported device vendors */ 262 static const struct sk_product { 263 pci_vendor_id_t sk_vendor; 264 pci_product_id_t sk_product; 265 } sk_products[] = { 266 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 267 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 268 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T, }, 269 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 270 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 271 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 272 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 273 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_SKNET, }, 274 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_BELKIN, }, 275 { 0, 0, } 276 }; 277 278 #define SK_LINKSYS_EG1032_SUBID 0x00151737 279 280 static inline u_int32_t 281 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 282 { 283 #ifdef SK_USEIOSPACE 284 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 285 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 286 #else 287 return CSR_READ_4(sc, reg); 288 #endif 289 } 290 291 static inline u_int16_t 292 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 293 { 294 #ifdef SK_USEIOSPACE 295 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 296 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 297 #else 298 return CSR_READ_2(sc, reg); 299 #endif 300 } 301 302 static inline u_int8_t 303 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 304 { 305 #ifdef SK_USEIOSPACE 306 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 307 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 308 #else 309 return CSR_READ_1(sc, reg); 310 #endif 311 } 312 313 static inline void 314 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 315 { 316 #ifdef SK_USEIOSPACE 317 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 318 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 319 #else 320 CSR_WRITE_4(sc, reg, x); 321 #endif 322 } 323 324 static inline void 325 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 326 { 327 #ifdef SK_USEIOSPACE 328 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 329 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 330 #else 331 CSR_WRITE_2(sc, reg, x); 332 #endif 333 } 334 335 static inline void 336 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 337 { 338 #ifdef SK_USEIOSPACE 339 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 340 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 341 #else 342 CSR_WRITE_1(sc, reg, x); 343 #endif 344 } 345 346 /* 347 * The VPD EEPROM contains Vital Product Data, as suggested in 348 * the PCI 2.1 specification. The VPD data is separared into areas 349 * denoted by resource IDs. The SysKonnect VPD contains an ID string 350 * resource (the name of the adapter), a read-only area resource 351 * containing various key/data fields and a read/write area which 352 * can be used to store asset management information or log messages. 353 * We read the ID string and read-only into buffers attached to 354 * the controller softc structure for later use. At the moment, 355 * we only use the ID string during sk_attach(). 356 */ 357 u_int8_t 358 sk_vpd_readbyte(struct sk_softc *sc, int addr) 359 { 360 int i; 361 362 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 363 for (i = 0; i < SK_TIMEOUT; i++) { 364 DELAY(1); 365 if (sk_win_read_2(sc, 366 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 367 break; 368 } 369 370 if (i == SK_TIMEOUT) 371 return(0); 372 373 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 374 } 375 376 void 377 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 378 { 379 int i; 380 u_int8_t *ptr; 381 382 ptr = (u_int8_t *)res; 383 for (i = 0; i < sizeof(struct vpd_res); i++) 384 ptr[i] = sk_vpd_readbyte(sc, i + addr); 385 } 386 387 void 388 sk_vpd_read(struct sk_softc *sc) 389 { 390 int pos = 0, i; 391 struct vpd_res res; 392 393 if (sc->sk_vpd_prodname != NULL) 394 free(sc->sk_vpd_prodname, M_DEVBUF); 395 if (sc->sk_vpd_readonly != NULL) 396 free(sc->sk_vpd_readonly, M_DEVBUF); 397 sc->sk_vpd_prodname = NULL; 398 sc->sk_vpd_readonly = NULL; 399 400 sk_vpd_read_res(sc, &res, pos); 401 402 if (res.vr_id != VPD_RES_ID) { 403 printf("%s: bad VPD resource id: expected %x got %x\n", 404 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 405 return; 406 } 407 408 pos += sizeof(res); 409 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 410 if (sc->sk_vpd_prodname == NULL) 411 panic("sk_vpd_read"); 412 for (i = 0; i < res.vr_len; i++) 413 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 414 sc->sk_vpd_prodname[i] = '\0'; 415 pos += i; 416 417 sk_vpd_read_res(sc, &res, pos); 418 419 if (res.vr_id != VPD_RES_READ) { 420 printf("%s: bad VPD resource id: expected %x got %x\n", 421 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 422 return; 423 } 424 425 pos += sizeof(res); 426 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 427 if (sc->sk_vpd_readonly == NULL) 428 panic("sk_vpd_read"); 429 for (i = 0; i < res.vr_len ; i++) 430 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 431 } 432 433 int 434 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 435 { 436 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 437 int i; 438 439 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 440 441 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 442 return(0); 443 444 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 445 SK_XM_READ_2(sc_if, XM_PHY_DATA); 446 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 447 for (i = 0; i < SK_TIMEOUT; i++) { 448 DELAY(1); 449 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 450 XM_MMUCMD_PHYDATARDY) 451 break; 452 } 453 454 if (i == SK_TIMEOUT) { 455 printf("%s: phy failed to come ready\n", 456 sc_if->sk_dev.dv_xname); 457 return(0); 458 } 459 } 460 DELAY(1); 461 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 462 } 463 464 void 465 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 466 { 467 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 468 int i; 469 470 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 471 472 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 473 for (i = 0; i < SK_TIMEOUT; i++) { 474 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 475 break; 476 } 477 478 if (i == SK_TIMEOUT) { 479 printf("%s: phy failed to come ready\n", 480 sc_if->sk_dev.dv_xname); 481 return; 482 } 483 484 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 485 for (i = 0; i < SK_TIMEOUT; i++) { 486 DELAY(1); 487 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 488 break; 489 } 490 491 if (i == SK_TIMEOUT) 492 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 493 } 494 495 void 496 sk_xmac_miibus_statchg(struct device *dev) 497 { 498 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 499 struct mii_data *mii = &sc_if->sk_mii; 500 501 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 502 503 /* 504 * If this is a GMII PHY, manually set the XMAC's 505 * duplex mode accordingly. 506 */ 507 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 508 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 509 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 510 } else { 511 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 512 } 513 } 514 } 515 516 int 517 sk_marv_miibus_readreg(dev, phy, reg) 518 struct device *dev; 519 int phy, reg; 520 { 521 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 522 u_int16_t val; 523 int i; 524 525 if (phy != 0 || 526 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 527 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 528 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 529 phy, reg)); 530 return(0); 531 } 532 533 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 534 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 535 536 for (i = 0; i < SK_TIMEOUT; i++) { 537 DELAY(1); 538 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 539 if (val & YU_SMICR_READ_VALID) 540 break; 541 } 542 543 if (i == SK_TIMEOUT) { 544 printf("%s: phy failed to come ready\n", 545 sc_if->sk_dev.dv_xname); 546 return 0; 547 } 548 549 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 550 SK_TIMEOUT)); 551 552 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 553 554 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 555 phy, reg, val)); 556 557 return val; 558 } 559 560 void 561 sk_marv_miibus_writereg(dev, phy, reg, val) 562 struct device *dev; 563 int phy, reg, val; 564 { 565 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 566 int i; 567 568 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 569 phy, reg, val)); 570 571 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 572 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 573 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 574 575 for (i = 0; i < SK_TIMEOUT; i++) { 576 DELAY(1); 577 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 578 break; 579 } 580 } 581 582 void 583 sk_marv_miibus_statchg(dev) 584 struct device *dev; 585 { 586 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 587 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 588 } 589 590 #define SK_HASH_BITS 6 591 592 u_int32_t 593 sk_xmac_hash(caddr_t addr) 594 { 595 u_int32_t crc; 596 597 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 598 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 599 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 600 return (crc); 601 } 602 603 u_int32_t 604 sk_yukon_hash(caddr_t addr) 605 { 606 u_int32_t crc; 607 608 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 609 crc &= ((1 << SK_HASH_BITS) - 1); 610 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 611 return (crc); 612 } 613 614 void 615 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 616 { 617 int base = XM_RXFILT_ENTRY(slot); 618 619 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 620 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 621 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 622 } 623 624 void 625 sk_setmulti(struct sk_if_softc *sc_if) 626 { 627 struct sk_softc *sc = sc_if->sk_softc; 628 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 629 u_int32_t hashes[2] = { 0, 0 }; 630 int h = 0, i; 631 struct ethercom *ec = &sc_if->sk_ethercom; 632 struct ether_multi *enm; 633 struct ether_multistep step; 634 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 635 636 /* First, zot all the existing filters. */ 637 switch(sc->sk_type) { 638 case SK_GENESIS: 639 for (i = 1; i < XM_RXFILT_MAX; i++) 640 sk_setfilt(sc_if, (caddr_t)&dummy, i); 641 642 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 643 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 644 break; 645 case SK_YUKON: 646 case SK_YUKON_LITE: 647 case SK_YUKON_LP: 648 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 649 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 650 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 651 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 652 break; 653 } 654 655 /* Now program new ones. */ 656 allmulti: 657 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 658 hashes[0] = 0xFFFFFFFF; 659 hashes[1] = 0xFFFFFFFF; 660 } else { 661 i = 1; 662 /* First find the tail of the list. */ 663 ETHER_FIRST_MULTI(step, ec, enm); 664 while (enm != NULL) { 665 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 666 ETHER_ADDR_LEN)) { 667 ifp->if_flags |= IFF_ALLMULTI; 668 goto allmulti; 669 } 670 DPRINTFN(2,("multicast address %s\n", 671 ether_sprintf(enm->enm_addrlo))); 672 /* 673 * Program the first XM_RXFILT_MAX multicast groups 674 * into the perfect filter. For all others, 675 * use the hash table. 676 */ 677 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 678 sk_setfilt(sc_if, enm->enm_addrlo, i); 679 i++; 680 } 681 else { 682 switch (sc->sk_type) { 683 case SK_GENESIS: 684 h = sk_xmac_hash(enm->enm_addrlo); 685 break; 686 case SK_YUKON: 687 case SK_YUKON_LITE: 688 case SK_YUKON_LP: 689 h = sk_yukon_hash(enm->enm_addrlo); 690 break; 691 } 692 if (h < 32) 693 hashes[0] |= (1 << h); 694 else 695 hashes[1] |= (1 << (h - 32)); 696 } 697 698 ETHER_NEXT_MULTI(step, enm); 699 } 700 } 701 702 switch(sc->sk_type) { 703 case SK_GENESIS: 704 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 705 XM_MODE_RX_USE_PERFECT); 706 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 707 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 708 break; 709 case SK_YUKON: 710 case SK_YUKON_LITE: 711 case SK_YUKON_LP: 712 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 713 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 714 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 715 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 716 break; 717 } 718 } 719 720 int 721 sk_init_rx_ring(struct sk_if_softc *sc_if) 722 { 723 struct sk_chain_data *cd = &sc_if->sk_cdata; 724 struct sk_ring_data *rd = sc_if->sk_rdata; 725 int i; 726 727 bzero((char *)rd->sk_rx_ring, 728 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 729 730 for (i = 0; i < SK_RX_RING_CNT; i++) { 731 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 732 if (i == (SK_RX_RING_CNT - 1)) { 733 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 734 rd->sk_rx_ring[i].sk_next = 735 htole32(SK_RX_RING_ADDR(sc_if, 0)); 736 } else { 737 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 738 rd->sk_rx_ring[i].sk_next = 739 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 740 } 741 } 742 743 for (i = 0; i < SK_RX_RING_CNT; i++) { 744 if (sk_newbuf(sc_if, i, NULL, 745 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 746 printf("%s: failed alloc of %dth mbuf\n", 747 sc_if->sk_dev.dv_xname, i); 748 return(ENOBUFS); 749 } 750 } 751 sc_if->sk_cdata.sk_rx_prod = 0; 752 sc_if->sk_cdata.sk_rx_cons = 0; 753 754 return(0); 755 } 756 757 int 758 sk_init_tx_ring(struct sk_if_softc *sc_if) 759 { 760 struct sk_chain_data *cd = &sc_if->sk_cdata; 761 struct sk_ring_data *rd = sc_if->sk_rdata; 762 int i; 763 764 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 765 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 766 767 for (i = 0; i < SK_TX_RING_CNT; i++) { 768 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 769 if (i == (SK_TX_RING_CNT - 1)) { 770 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 771 rd->sk_tx_ring[i].sk_next = 772 htole32(SK_TX_RING_ADDR(sc_if, 0)); 773 } else { 774 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 775 rd->sk_tx_ring[i].sk_next = 776 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 777 } 778 } 779 780 sc_if->sk_cdata.sk_tx_prod = 0; 781 sc_if->sk_cdata.sk_tx_cons = 0; 782 sc_if->sk_cdata.sk_tx_cnt = 0; 783 784 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 785 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 786 787 return (0); 788 } 789 790 int 791 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 792 bus_dmamap_t dmamap) 793 { 794 struct mbuf *m_new = NULL; 795 struct sk_chain *c; 796 struct sk_rx_desc *r; 797 798 if (m == NULL) { 799 caddr_t buf = NULL; 800 801 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 802 if (m_new == NULL) { 803 printf("%s: no memory for rx list -- " 804 "packet dropped!\n", sc_if->sk_dev.dv_xname); 805 return(ENOBUFS); 806 } 807 808 /* Allocate the jumbo buffer */ 809 buf = sk_jalloc(sc_if); 810 if (buf == NULL) { 811 m_freem(m_new); 812 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 813 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 814 return(ENOBUFS); 815 } 816 817 /* Attach the buffer to the mbuf */ 818 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 819 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 820 821 } else { 822 /* 823 * We're re-using a previously allocated mbuf; 824 * be sure to re-init pointers and lengths to 825 * default values. 826 */ 827 m_new = m; 828 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 829 m_new->m_data = m_new->m_ext.ext_buf; 830 } 831 m_adj(m_new, ETHER_ALIGN); 832 833 c = &sc_if->sk_cdata.sk_rx_chain[i]; 834 r = c->sk_desc; 835 c->sk_mbuf = m_new; 836 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 837 (((vaddr_t)m_new->m_data 838 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 839 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 840 841 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 842 843 return(0); 844 } 845 846 /* 847 * Memory management for jumbo frames. 848 */ 849 850 int 851 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 852 { 853 struct sk_softc *sc = sc_if->sk_softc; 854 caddr_t ptr, kva; 855 bus_dma_segment_t seg; 856 int i, rseg, state, error; 857 struct sk_jpool_entry *entry; 858 859 state = error = 0; 860 861 /* Grab a big chunk o' storage. */ 862 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 863 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 864 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 865 return (ENOBUFS); 866 } 867 868 state = 1; 869 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, &kva, 870 BUS_DMA_NOWAIT)) { 871 printf("%s: can't map dma buffers (%d bytes)\n", 872 sc->sk_dev.dv_xname, SK_JMEM); 873 error = ENOBUFS; 874 goto out; 875 } 876 877 state = 2; 878 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 879 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 880 printf("%s: can't create dma map\n", sc->sk_dev.dv_xname); 881 error = ENOBUFS; 882 goto out; 883 } 884 885 state = 3; 886 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 887 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 888 printf("%s: can't load dma map\n", sc->sk_dev.dv_xname); 889 error = ENOBUFS; 890 goto out; 891 } 892 893 state = 4; 894 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 895 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 896 897 LIST_INIT(&sc_if->sk_jfree_listhead); 898 LIST_INIT(&sc_if->sk_jinuse_listhead); 899 900 /* 901 * Now divide it up into 9K pieces and save the addresses 902 * in an array. 903 */ 904 ptr = sc_if->sk_cdata.sk_jumbo_buf; 905 for (i = 0; i < SK_JSLOTS; i++) { 906 sc_if->sk_cdata.sk_jslots[i] = ptr; 907 ptr += SK_JLEN; 908 entry = malloc(sizeof(struct sk_jpool_entry), 909 M_DEVBUF, M_NOWAIT); 910 if (entry == NULL) { 911 printf("%s: no memory for jumbo buffer queue!\n", 912 sc->sk_dev.dv_xname); 913 error = ENOBUFS; 914 goto out; 915 } 916 entry->slot = i; 917 if (i) 918 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 919 entry, jpool_entries); 920 else 921 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 922 entry, jpool_entries); 923 } 924 out: 925 if (error != 0) { 926 switch (state) { 927 case 4: 928 bus_dmamap_unload(sc->sc_dmatag, 929 sc_if->sk_cdata.sk_rx_jumbo_map); 930 case 3: 931 bus_dmamap_destroy(sc->sc_dmatag, 932 sc_if->sk_cdata.sk_rx_jumbo_map); 933 case 2: 934 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 935 case 1: 936 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 937 break; 938 default: 939 break; 940 } 941 } 942 943 return (error); 944 } 945 946 /* 947 * Allocate a jumbo buffer. 948 */ 949 void * 950 sk_jalloc(struct sk_if_softc *sc_if) 951 { 952 struct sk_jpool_entry *entry; 953 954 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 955 956 if (entry == NULL) 957 return (NULL); 958 959 LIST_REMOVE(entry, jpool_entries); 960 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 961 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 962 } 963 964 /* 965 * Release a jumbo buffer. 966 */ 967 void 968 sk_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 969 { 970 struct sk_jpool_entry *entry; 971 struct sk_if_softc *sc; 972 int i, s; 973 974 /* Extract the softc struct pointer. */ 975 sc = (struct sk_if_softc *)arg; 976 977 if (sc == NULL) 978 panic("sk_jfree: can't find softc pointer!"); 979 980 /* calculate the slot this buffer belongs to */ 981 982 i = ((vaddr_t)buf 983 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 984 985 if ((i < 0) || (i >= SK_JSLOTS)) 986 panic("sk_jfree: asked to free buffer that we don't manage!"); 987 988 s = splvm(); 989 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 990 if (entry == NULL) 991 panic("sk_jfree: buffer not in use!"); 992 entry->slot = i; 993 LIST_REMOVE(entry, jpool_entries); 994 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 995 996 if (__predict_true(m != NULL)) 997 pool_cache_put(&mbpool_cache, m); 998 splx(s); 999 } 1000 1001 /* 1002 * Set media options. 1003 */ 1004 int 1005 sk_ifmedia_upd(struct ifnet *ifp) 1006 { 1007 struct sk_if_softc *sc_if = ifp->if_softc; 1008 1009 (void) sk_init(ifp); 1010 mii_mediachg(&sc_if->sk_mii); 1011 return(0); 1012 } 1013 1014 /* 1015 * Report current media status. 1016 */ 1017 void 1018 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1019 { 1020 struct sk_if_softc *sc_if = ifp->if_softc; 1021 1022 mii_pollstat(&sc_if->sk_mii); 1023 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 1024 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 1025 } 1026 1027 int 1028 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1029 { 1030 struct sk_if_softc *sc_if = ifp->if_softc; 1031 struct sk_softc *sc = sc_if->sk_softc; 1032 struct ifreq *ifr = (struct ifreq *) data; 1033 /* struct ifaddr *ifa = (struct ifaddr *) data; */ 1034 struct mii_data *mii; 1035 int s, error = 0; 1036 1037 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1038 1039 s = splnet(); 1040 1041 switch(command) { 1042 1043 case SIOCSIFFLAGS: 1044 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1045 if (ifp->if_flags & IFF_UP) { 1046 if (ifp->if_flags & IFF_RUNNING && 1047 ifp->if_flags & IFF_PROMISC && 1048 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1049 switch(sc->sk_type) { 1050 case SK_GENESIS: 1051 SK_XM_SETBIT_4(sc_if, XM_MODE, 1052 XM_MODE_RX_PROMISC); 1053 break; 1054 case SK_YUKON: 1055 case SK_YUKON_LITE: 1056 case SK_YUKON_LP: 1057 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1058 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1059 break; 1060 } 1061 sk_setmulti(sc_if); 1062 } else if (ifp->if_flags & IFF_RUNNING && 1063 !(ifp->if_flags & IFF_PROMISC) && 1064 sc_if->sk_if_flags & IFF_PROMISC) { 1065 switch(sc->sk_type) { 1066 case SK_GENESIS: 1067 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1068 XM_MODE_RX_PROMISC); 1069 break; 1070 case SK_YUKON: 1071 case SK_YUKON_LITE: 1072 case SK_YUKON_LP: 1073 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1074 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1075 break; 1076 } 1077 1078 sk_setmulti(sc_if); 1079 } else 1080 (void) sk_init(ifp); 1081 } else { 1082 if (ifp->if_flags & IFF_RUNNING) 1083 sk_stop(ifp,0); 1084 } 1085 sc_if->sk_if_flags = ifp->if_flags; 1086 error = 0; 1087 break; 1088 1089 case SIOCGIFMEDIA: 1090 case SIOCSIFMEDIA: 1091 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 1092 mii = &sc_if->sk_mii; 1093 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1094 break; 1095 default: 1096 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1097 error = ether_ioctl(ifp, command, data); 1098 1099 if ( error == ENETRESET) { 1100 if (ifp->if_flags & IFF_RUNNING) { 1101 sk_setmulti(sc_if); 1102 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1103 } 1104 error = 0; 1105 } else if ( error ) { 1106 splx(s); 1107 return error; 1108 } 1109 break; 1110 } 1111 1112 splx(s); 1113 return(error); 1114 } 1115 1116 void 1117 sk_update_int_mod(struct sk_softc *sc) 1118 { 1119 u_int32_t sk_imtimer_ticks; 1120 1121 /* 1122 * Configure interrupt moderation. The moderation timer 1123 * defers interrupts specified in the interrupt moderation 1124 * timer mask based on the timeout specified in the interrupt 1125 * moderation timer init register. Each bit in the timer 1126 * register represents one tick, so to specify a timeout in 1127 * microseconds, we have to multiply by the correct number of 1128 * ticks-per-microsecond. 1129 */ 1130 switch (sc->sk_type) { 1131 case SK_GENESIS: 1132 sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1133 break; 1134 case SK_YUKON_EC: 1135 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1136 break; 1137 default: 1138 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1139 } 1140 aprint_verbose("%s: interrupt moderation is %d us\n", 1141 sc->sk_dev.dv_xname, sc->sk_int_mod); 1142 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1143 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1144 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1145 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1146 sc->sk_int_mod_pending = 0; 1147 } 1148 1149 /* 1150 * Lookup: Check the PCI vendor and device, and return a pointer to 1151 * The structure if the IDs match against our list. 1152 */ 1153 1154 static const struct sk_product * 1155 sk_lookup(const struct pci_attach_args *pa) 1156 { 1157 const struct sk_product *psk; 1158 1159 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1160 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1161 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1162 return (psk); 1163 } 1164 return (NULL); 1165 } 1166 1167 /* 1168 * Probe for a SysKonnect GEnesis chip. 1169 */ 1170 1171 int 1172 skc_probe(struct device *parent, struct cfdata *match, void *aux) 1173 { 1174 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1175 const struct sk_product *psk; 1176 pcireg_t subid; 1177 1178 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1179 1180 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1181 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1182 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1183 subid == SK_LINKSYS_EG1032_SUBID) 1184 return(1); 1185 1186 if ((psk = sk_lookup(pa))) { 1187 return(1); 1188 } 1189 return(0); 1190 } 1191 1192 /* 1193 * Force the GEnesis into reset, then bring it out of reset. 1194 */ 1195 void sk_reset(struct sk_softc *sc) 1196 { 1197 DPRINTFN(2, ("sk_reset\n")); 1198 1199 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1200 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1201 if (SK_YUKON_FAMILY(sc->sk_type)) 1202 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1203 1204 DELAY(1000); 1205 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1206 DELAY(2); 1207 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1208 if (SK_YUKON_FAMILY(sc->sk_type)) 1209 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1210 1211 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1212 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1213 CSR_READ_2(sc, SK_LINK_CTRL))); 1214 1215 if (sc->sk_type == SK_GENESIS) { 1216 /* Configure packet arbiter */ 1217 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1218 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1219 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1220 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1221 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1222 } 1223 1224 /* Enable RAM interface */ 1225 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1226 1227 sk_update_int_mod(sc); 1228 } 1229 1230 int 1231 sk_probe(struct device *parent, struct cfdata *match, void *aux) 1232 { 1233 struct skc_attach_args *sa = aux; 1234 1235 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1236 return(0); 1237 1238 return (1); 1239 } 1240 1241 /* 1242 * Each XMAC chip is attached as a separate logical IP interface. 1243 * Single port cards will have only one logical interface of course. 1244 */ 1245 void 1246 sk_attach(struct device *parent, struct device *self, void *aux) 1247 { 1248 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1249 struct sk_softc *sc = (struct sk_softc *)parent; 1250 struct skc_attach_args *sa = aux; 1251 struct sk_txmap_entry *entry; 1252 struct ifnet *ifp; 1253 bus_dma_segment_t seg; 1254 bus_dmamap_t dmamap; 1255 caddr_t kva; 1256 int i, rseg; 1257 1258 sc_if->sk_port = sa->skc_port; 1259 sc_if->sk_softc = sc; 1260 sc->sk_if[sa->skc_port] = sc_if; 1261 1262 if (sa->skc_port == SK_PORT_A) 1263 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1264 if (sa->skc_port == SK_PORT_B) 1265 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1266 1267 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1268 1269 /* 1270 * Get station address for this interface. Note that 1271 * dual port cards actually come with three station 1272 * addresses: one for each port, plus an extra. The 1273 * extra one is used by the SysKonnect driver software 1274 * as a 'virtual' station address for when both ports 1275 * are operating in failover mode. Currently we don't 1276 * use this extra address. 1277 */ 1278 for (i = 0; i < ETHER_ADDR_LEN; i++) 1279 sc_if->sk_enaddr[i] = 1280 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1281 1282 1283 aprint_normal(": Ethernet address %s\n", 1284 ether_sprintf(sc_if->sk_enaddr)); 1285 1286 /* 1287 * Set up RAM buffer addresses. The NIC will have a certain 1288 * amount of SRAM on it, somewhere between 512K and 2MB. We 1289 * need to divide this up a) between the transmitter and 1290 * receiver and b) between the two XMACs, if this is a 1291 * dual port NIC. Our algorithm is to divide up the memory 1292 * evenly so that everyone gets a fair share. 1293 */ 1294 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1295 u_int32_t chunk, val; 1296 1297 chunk = sc->sk_ramsize / 2; 1298 val = sc->sk_rboff / sizeof(u_int64_t); 1299 sc_if->sk_rx_ramstart = val; 1300 val += (chunk / sizeof(u_int64_t)); 1301 sc_if->sk_rx_ramend = val - 1; 1302 sc_if->sk_tx_ramstart = val; 1303 val += (chunk / sizeof(u_int64_t)); 1304 sc_if->sk_tx_ramend = val - 1; 1305 } else { 1306 u_int32_t chunk, val; 1307 1308 chunk = sc->sk_ramsize / 4; 1309 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1310 sizeof(u_int64_t); 1311 sc_if->sk_rx_ramstart = val; 1312 val += (chunk / sizeof(u_int64_t)); 1313 sc_if->sk_rx_ramend = val - 1; 1314 sc_if->sk_tx_ramstart = val; 1315 val += (chunk / sizeof(u_int64_t)); 1316 sc_if->sk_tx_ramend = val - 1; 1317 } 1318 1319 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1320 " tx_ramstart=%#x tx_ramend=%#x\n", 1321 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1322 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1323 1324 /* Read and save PHY type and set PHY address */ 1325 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1326 switch (sc_if->sk_phytype) { 1327 case SK_PHYTYPE_XMAC: 1328 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1329 break; 1330 case SK_PHYTYPE_BCOM: 1331 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1332 break; 1333 case SK_PHYTYPE_MARV_COPPER: 1334 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1335 break; 1336 default: 1337 aprint_error("%s: unsupported PHY type: %d\n", 1338 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1339 return; 1340 } 1341 1342 /* Allocate the descriptor queues. */ 1343 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1344 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1345 aprint_error("%s: can't alloc rx buffers\n", 1346 sc->sk_dev.dv_xname); 1347 goto fail; 1348 } 1349 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1350 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1351 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1352 sc_if->sk_dev.dv_xname, 1353 (u_long) sizeof(struct sk_ring_data)); 1354 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1355 goto fail; 1356 } 1357 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1358 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1359 &sc_if->sk_ring_map)) { 1360 aprint_error("%s: can't create dma map\n", 1361 sc_if->sk_dev.dv_xname); 1362 bus_dmamem_unmap(sc->sc_dmatag, kva, 1363 sizeof(struct sk_ring_data)); 1364 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1365 goto fail; 1366 } 1367 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1368 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1369 aprint_error("%s: can't load dma map\n", 1370 sc_if->sk_dev.dv_xname); 1371 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1372 bus_dmamem_unmap(sc->sc_dmatag, kva, 1373 sizeof(struct sk_ring_data)); 1374 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1375 goto fail; 1376 } 1377 1378 for (i = 0; i < SK_RX_RING_CNT; i++) 1379 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1380 1381 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1382 for (i = 0; i < SK_TX_RING_CNT; i++) { 1383 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1384 1385 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1386 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1387 aprint_error("%s: Can't create TX dmamap\n", 1388 sc_if->sk_dev.dv_xname); 1389 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1390 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1391 bus_dmamem_unmap(sc->sc_dmatag, kva, 1392 sizeof(struct sk_ring_data)); 1393 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1394 goto fail; 1395 } 1396 1397 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1398 if (!entry) { 1399 aprint_error("%s: Can't alloc txmap entry\n", 1400 sc_if->sk_dev.dv_xname); 1401 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1402 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1403 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1404 bus_dmamem_unmap(sc->sc_dmatag, kva, 1405 sizeof(struct sk_ring_data)); 1406 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1407 goto fail; 1408 } 1409 entry->dmamap = dmamap; 1410 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1411 } 1412 1413 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1414 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1415 1416 ifp = &sc_if->sk_ethercom.ec_if; 1417 /* Try to allocate memory for jumbo buffers. */ 1418 if (sk_alloc_jumbo_mem(sc_if)) { 1419 printf("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1420 goto fail; 1421 } 1422 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1423 | ETHERCAP_JUMBO_MTU; 1424 1425 ifp->if_softc = sc_if; 1426 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1427 ifp->if_ioctl = sk_ioctl; 1428 ifp->if_start = sk_start; 1429 ifp->if_stop = sk_stop; 1430 ifp->if_init = sk_init; 1431 ifp->if_watchdog = sk_watchdog; 1432 ifp->if_capabilities = 0; 1433 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1434 IFQ_SET_READY(&ifp->if_snd); 1435 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1436 1437 /* 1438 * Do miibus setup. 1439 */ 1440 switch (sc->sk_type) { 1441 case SK_GENESIS: 1442 sk_init_xmac(sc_if); 1443 break; 1444 case SK_YUKON: 1445 case SK_YUKON_LITE: 1446 case SK_YUKON_LP: 1447 sk_init_yukon(sc_if); 1448 break; 1449 default: 1450 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1451 sc->sk_type); 1452 } 1453 1454 DPRINTFN(2, ("sk_attach: 1\n")); 1455 1456 sc_if->sk_mii.mii_ifp = ifp; 1457 switch (sc->sk_type) { 1458 case SK_GENESIS: 1459 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1460 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1461 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1462 break; 1463 case SK_YUKON: 1464 case SK_YUKON_LITE: 1465 case SK_YUKON_LP: 1466 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1467 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1468 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1469 break; 1470 } 1471 1472 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1473 sk_ifmedia_upd, sk_ifmedia_sts); 1474 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1475 MII_OFFSET_ANY, 0); 1476 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1477 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1478 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1479 0, NULL); 1480 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1481 } 1482 else 1483 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1484 1485 callout_init(&sc_if->sk_tick_ch); 1486 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1487 1488 DPRINTFN(2, ("sk_attach: 1\n")); 1489 1490 /* 1491 * Call MI attach routines. 1492 */ 1493 if_attach(ifp); 1494 1495 ether_ifattach(ifp, sc_if->sk_enaddr); 1496 1497 #if NRND > 0 1498 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1499 RND_TYPE_NET, 0); 1500 #endif 1501 1502 DPRINTFN(2, ("sk_attach: end\n")); 1503 1504 return; 1505 1506 fail: 1507 sc->sk_if[sa->skc_port] = NULL; 1508 } 1509 1510 int 1511 skcprint(void *aux, const char *pnp) 1512 { 1513 struct skc_attach_args *sa = aux; 1514 1515 if (pnp) 1516 aprint_normal("sk port %c at %s", 1517 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1518 else 1519 aprint_normal(" port %c", 1520 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1521 return (UNCONF); 1522 } 1523 1524 /* 1525 * Attach the interface. Allocate softc structures, do ifmedia 1526 * setup and ethernet/BPF attach. 1527 */ 1528 void 1529 skc_attach(struct device *parent, struct device *self, void *aux) 1530 { 1531 struct sk_softc *sc = (struct sk_softc *)self; 1532 struct pci_attach_args *pa = aux; 1533 struct skc_attach_args skca; 1534 pci_chipset_tag_t pc = pa->pa_pc; 1535 #ifndef SK_USEIOSPACE 1536 pcireg_t memtype; 1537 #endif 1538 pci_intr_handle_t ih; 1539 const char *intrstr = NULL; 1540 bus_addr_t iobase; 1541 bus_size_t iosize; 1542 int rc, sk_nodenum; 1543 u_int32_t command; 1544 const char *revstr; 1545 const struct sysctlnode *node; 1546 1547 DPRINTFN(2, ("begin skc_attach\n")); 1548 1549 /* 1550 * Handle power management nonsense. 1551 */ 1552 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1553 1554 if (command == 0x01) { 1555 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1556 if (command & SK_PSTATE_MASK) { 1557 u_int32_t xiobase, membase, irq; 1558 1559 /* Save important PCI config data. */ 1560 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1561 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1562 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1563 1564 /* Reset the power state. */ 1565 aprint_normal("%s chip is in D%d power mode " 1566 "-- setting to D0\n", sc->sk_dev.dv_xname, 1567 command & SK_PSTATE_MASK); 1568 command &= 0xFFFFFFFC; 1569 pci_conf_write(pc, pa->pa_tag, 1570 SK_PCI_PWRMGMTCTRL, command); 1571 1572 /* Restore PCI config data. */ 1573 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1574 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1575 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1576 } 1577 } 1578 1579 /* 1580 * Map control/status registers. 1581 */ 1582 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1583 command |= PCI_COMMAND_IO_ENABLE | 1584 PCI_COMMAND_MEM_ENABLE | 1585 PCI_COMMAND_MASTER_ENABLE; 1586 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1587 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1588 1589 #ifdef SK_USEIOSPACE 1590 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1591 aprint_error(": failed to enable I/O ports!\n"); 1592 return; 1593 } 1594 /* 1595 * Map control/status registers. 1596 */ 1597 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1598 &sc->sk_btag, &sc->sk_bhandle, 1599 &iobase, &iosize)) { 1600 aprint_error(": can't find i/o space\n"); 1601 return; 1602 } 1603 #else 1604 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1605 aprint_error(": failed to enable memory mapping!\n"); 1606 return; 1607 } 1608 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1609 switch (memtype) { 1610 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1611 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1612 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1613 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1614 &iobase, &iosize) == 0) 1615 break; 1616 default: 1617 aprint_error("%s: can't find mem space\n", 1618 sc->sk_dev.dv_xname); 1619 return; 1620 } 1621 1622 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1623 #endif 1624 sc->sc_dmatag = pa->pa_dmat; 1625 1626 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1627 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1628 1629 /* bail out here if chip is not recognized */ 1630 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1631 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1632 goto fail; 1633 } 1634 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1635 1636 /* Allocate interrupt */ 1637 if (pci_intr_map(pa, &ih)) { 1638 aprint_error(": couldn't map interrupt\n"); 1639 goto fail; 1640 } 1641 1642 intrstr = pci_intr_string(pc, ih); 1643 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1644 if (sc->sk_intrhand == NULL) { 1645 aprint_error(": couldn't establish interrupt"); 1646 if (intrstr != NULL) 1647 aprint_normal(" at %s", intrstr); 1648 goto fail; 1649 } 1650 aprint_normal(": %s\n", intrstr); 1651 1652 /* Reset the adapter. */ 1653 sk_reset(sc); 1654 1655 /* Read and save vital product data from EEPROM. */ 1656 sk_vpd_read(sc); 1657 1658 if (sc->sk_type == SK_GENESIS) { 1659 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1660 /* Read and save RAM size and RAMbuffer offset */ 1661 switch(val) { 1662 case SK_RAMSIZE_512K_64: 1663 sc->sk_ramsize = 0x80000; 1664 sc->sk_rboff = SK_RBOFF_0; 1665 break; 1666 case SK_RAMSIZE_1024K_64: 1667 sc->sk_ramsize = 0x100000; 1668 sc->sk_rboff = SK_RBOFF_80000; 1669 break; 1670 case SK_RAMSIZE_1024K_128: 1671 sc->sk_ramsize = 0x100000; 1672 sc->sk_rboff = SK_RBOFF_0; 1673 break; 1674 case SK_RAMSIZE_2048K_128: 1675 sc->sk_ramsize = 0x200000; 1676 sc->sk_rboff = SK_RBOFF_0; 1677 break; 1678 default: 1679 aprint_error("%s: unknown ram size: %d\n", 1680 sc->sk_dev.dv_xname, val); 1681 goto fail_1; 1682 break; 1683 } 1684 1685 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1686 sc->sk_ramsize, sc->sk_ramsize / 1024, 1687 sc->sk_rboff)); 1688 } else { 1689 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1690 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1691 sc->sk_rboff = SK_RBOFF_0; 1692 1693 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1694 sc->sk_ramsize / 1024, sc->sk_ramsize, 1695 sc->sk_rboff)); 1696 } 1697 1698 /* Read and save physical media type */ 1699 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1700 case SK_PMD_1000BASESX: 1701 sc->sk_pmd = IFM_1000_SX; 1702 break; 1703 case SK_PMD_1000BASELX: 1704 sc->sk_pmd = IFM_1000_LX; 1705 break; 1706 case SK_PMD_1000BASECX: 1707 sc->sk_pmd = IFM_1000_CX; 1708 break; 1709 case SK_PMD_1000BASETX: 1710 case SK_PMD_1000BASETX_ALT: 1711 sc->sk_pmd = IFM_1000_T; 1712 break; 1713 default: 1714 aprint_error("%s: unknown media type: 0x%x\n", 1715 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1716 goto fail_1; 1717 } 1718 1719 /* determine whether to name it with vpd or just make it up */ 1720 /* Marvell Yukon VPD's can freqently be bogus */ 1721 1722 switch (pa->pa_id) { 1723 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1724 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1725 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1726 case PCI_PRODUCT_3COM_3C940: 1727 case PCI_PRODUCT_DLINK_DGE530T: 1728 case PCI_PRODUCT_DLINK_DGE560T: 1729 case PCI_PRODUCT_DLINK_DGE560T_2: 1730 case PCI_PRODUCT_LINKSYS_EG1032: 1731 case PCI_PRODUCT_LINKSYS_EG1064: 1732 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1733 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1734 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1735 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1736 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1737 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1738 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1739 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1740 sc->sk_name = sc->sk_vpd_prodname; 1741 break; 1742 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_SKNET): 1743 /* whoops yukon vpd prodname bears no resemblance to reality */ 1744 switch (sc->sk_type) { 1745 case SK_GENESIS: 1746 sc->sk_name = sc->sk_vpd_prodname; 1747 break; 1748 case SK_YUKON: 1749 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1750 break; 1751 case SK_YUKON_LITE: 1752 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1753 break; 1754 case SK_YUKON_LP: 1755 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1756 break; 1757 default: 1758 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1759 } 1760 1761 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1762 1763 if ( sc->sk_type == SK_YUKON ) { 1764 uint32_t flashaddr; 1765 uint8_t testbyte; 1766 1767 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1768 1769 /* test Flash-Address Register */ 1770 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1771 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1772 1773 if (testbyte != 0) { 1774 /* this is yukon lite Rev. A0 */ 1775 sc->sk_type = SK_YUKON_LITE; 1776 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1777 /* restore Flash-Address Register */ 1778 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1779 } 1780 } 1781 break; 1782 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_BELKIN): 1783 sc->sk_name = sc->sk_vpd_prodname; 1784 break; 1785 default: 1786 sc->sk_name = "Unknown Marvell"; 1787 } 1788 1789 1790 if ( sc->sk_type == SK_YUKON_LITE ) { 1791 switch (sc->sk_rev) { 1792 case SK_YUKON_LITE_REV_A0: 1793 revstr = "A0"; 1794 break; 1795 case SK_YUKON_LITE_REV_A1: 1796 revstr = "A1"; 1797 break; 1798 case SK_YUKON_LITE_REV_A3: 1799 revstr = "A3"; 1800 break; 1801 default: 1802 revstr = ""; 1803 } 1804 } else { 1805 revstr = ""; 1806 } 1807 1808 /* Announce the product name. */ 1809 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1810 sc->sk_name, revstr, sc->sk_rev); 1811 1812 skca.skc_port = SK_PORT_A; 1813 (void)config_found(&sc->sk_dev, &skca, skcprint); 1814 1815 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1816 skca.skc_port = SK_PORT_B; 1817 (void)config_found(&sc->sk_dev, &skca, skcprint); 1818 } 1819 1820 /* Turn on the 'driver is loaded' LED. */ 1821 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1822 1823 /* skc sysctl setup */ 1824 1825 sc->sk_int_mod = SK_IM_DEFAULT; 1826 sc->sk_int_mod_pending = 0; 1827 1828 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1829 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1830 SYSCTL_DESCR("skc per-controller controls"), 1831 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1832 CTL_EOL)) != 0) { 1833 aprint_normal("%s: couldn't create sysctl node\n", 1834 sc->sk_dev.dv_xname); 1835 goto fail_1; 1836 } 1837 1838 sk_nodenum = node->sysctl_num; 1839 1840 /* interrupt moderation time in usecs */ 1841 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1842 CTLFLAG_READWRITE, 1843 CTLTYPE_INT, "int_mod", 1844 SYSCTL_DESCR("sk interrupt moderation timer"), 1845 sk_sysctl_handler, 0, sc, 1846 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1847 CTL_EOL)) != 0) { 1848 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1849 sc->sk_dev.dv_xname); 1850 goto fail_1; 1851 } 1852 1853 return; 1854 1855 fail_1: 1856 pci_intr_disestablish(pc, sc->sk_intrhand); 1857 fail: 1858 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1859 } 1860 1861 int 1862 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1863 { 1864 struct sk_softc *sc = sc_if->sk_softc; 1865 struct sk_tx_desc *f = NULL; 1866 u_int32_t frag, cur, cnt = 0, sk_ctl; 1867 int i; 1868 struct sk_txmap_entry *entry; 1869 bus_dmamap_t txmap; 1870 1871 DPRINTFN(3, ("sk_encap\n")); 1872 1873 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1874 if (entry == NULL) { 1875 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1876 return ENOBUFS; 1877 } 1878 txmap = entry->dmamap; 1879 1880 cur = frag = *txidx; 1881 1882 #ifdef SK_DEBUG 1883 if (skdebug >= 3) 1884 sk_dump_mbuf(m_head); 1885 #endif 1886 1887 /* 1888 * Start packing the mbufs in this chain into 1889 * the fragment pointers. Stop when we run out 1890 * of fragments or hit the end of the mbuf chain. 1891 */ 1892 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1893 BUS_DMA_NOWAIT)) { 1894 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1895 return(ENOBUFS); 1896 } 1897 1898 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1899 1900 /* Sync the DMA map. */ 1901 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1902 BUS_DMASYNC_PREWRITE); 1903 1904 for (i = 0; i < txmap->dm_nsegs; i++) { 1905 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1906 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1907 return(ENOBUFS); 1908 } 1909 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1910 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1911 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1912 if (cnt == 0) 1913 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1914 else 1915 sk_ctl |= SK_TXCTL_OWN; 1916 f->sk_ctl = htole32(sk_ctl); 1917 cur = frag; 1918 SK_INC(frag, SK_TX_RING_CNT); 1919 cnt++; 1920 } 1921 1922 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1923 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1924 1925 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1926 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1927 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1928 1929 /* Sync descriptors before handing to chip */ 1930 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1931 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1932 1933 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1934 htole32(SK_TXCTL_OWN); 1935 1936 /* Sync first descriptor to hand it off */ 1937 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1938 1939 sc_if->sk_cdata.sk_tx_cnt += cnt; 1940 1941 #ifdef SK_DEBUG 1942 if (skdebug >= 3) { 1943 struct sk_tx_desc *desc; 1944 u_int32_t idx; 1945 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1946 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1947 sk_dump_txdesc(desc, idx); 1948 } 1949 } 1950 #endif 1951 1952 *txidx = frag; 1953 1954 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1955 1956 return(0); 1957 } 1958 1959 void 1960 sk_start(struct ifnet *ifp) 1961 { 1962 struct sk_if_softc *sc_if = ifp->if_softc; 1963 struct sk_softc *sc = sc_if->sk_softc; 1964 struct mbuf *m_head = NULL; 1965 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1966 int pkts = 0; 1967 1968 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1969 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1970 1971 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1972 1973 IFQ_POLL(&ifp->if_snd, m_head); 1974 if (m_head == NULL) 1975 break; 1976 1977 /* 1978 * Pack the data into the transmit ring. If we 1979 * don't have room, set the OACTIVE flag and wait 1980 * for the NIC to drain the ring. 1981 */ 1982 if (sk_encap(sc_if, m_head, &idx)) { 1983 ifp->if_flags |= IFF_OACTIVE; 1984 break; 1985 } 1986 1987 /* now we are committed to transmit the packet */ 1988 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1989 pkts++; 1990 1991 /* 1992 * If there's a BPF listener, bounce a copy of this frame 1993 * to him. 1994 */ 1995 #if NBPFILTER > 0 1996 if (ifp->if_bpf) 1997 bpf_mtap(ifp->if_bpf, m_head); 1998 #endif 1999 } 2000 if (pkts == 0) 2001 return; 2002 2003 /* Transmit */ 2004 if (idx != sc_if->sk_cdata.sk_tx_prod) { 2005 sc_if->sk_cdata.sk_tx_prod = idx; 2006 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2007 2008 /* Set a timeout in case the chip goes out to lunch. */ 2009 ifp->if_timer = 5; 2010 } 2011 } 2012 2013 2014 void 2015 sk_watchdog(struct ifnet *ifp) 2016 { 2017 struct sk_if_softc *sc_if = ifp->if_softc; 2018 2019 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 2020 (void) sk_init(ifp); 2021 } 2022 2023 void 2024 sk_shutdown(void * v) 2025 { 2026 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2027 struct sk_softc *sc = sc_if->sk_softc; 2028 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2029 2030 DPRINTFN(2, ("sk_shutdown\n")); 2031 sk_stop(ifp,1); 2032 2033 /* Turn off the 'driver is loaded' LED. */ 2034 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2035 2036 /* 2037 * Reset the GEnesis controller. Doing this should also 2038 * assert the resets on the attached XMAC(s). 2039 */ 2040 sk_reset(sc); 2041 } 2042 2043 void 2044 sk_rxeof(struct sk_if_softc *sc_if) 2045 { 2046 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2047 struct mbuf *m; 2048 struct sk_chain *cur_rx; 2049 struct sk_rx_desc *cur_desc; 2050 int i, cur, total_len = 0; 2051 u_int32_t rxstat, sk_ctl; 2052 bus_dmamap_t dmamap; 2053 2054 i = sc_if->sk_cdata.sk_rx_prod; 2055 2056 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2057 2058 for (;;) { 2059 cur = i; 2060 2061 /* Sync the descriptor */ 2062 SK_CDRXSYNC(sc_if, cur, 2063 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2064 2065 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2066 if (sk_ctl & SK_RXCTL_OWN) { 2067 /* Invalidate the descriptor -- it's not ready yet */ 2068 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2069 sc_if->sk_cdata.sk_rx_prod = i; 2070 break; 2071 } 2072 2073 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2074 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2075 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2076 2077 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2078 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2079 2080 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2081 m = cur_rx->sk_mbuf; 2082 cur_rx->sk_mbuf = NULL; 2083 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2084 2085 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2086 2087 SK_INC(i, SK_RX_RING_CNT); 2088 2089 if (rxstat & XM_RXSTAT_ERRFRAME) { 2090 ifp->if_ierrors++; 2091 sk_newbuf(sc_if, cur, m, dmamap); 2092 continue; 2093 } 2094 2095 /* 2096 * Try to allocate a new jumbo buffer. If that 2097 * fails, copy the packet to mbufs and put the 2098 * jumbo buffer back in the ring so it can be 2099 * re-used. If allocating mbufs fails, then we 2100 * have to drop the packet. 2101 */ 2102 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2103 struct mbuf *m0; 2104 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2105 total_len + ETHER_ALIGN, 0, ifp, NULL); 2106 sk_newbuf(sc_if, cur, m, dmamap); 2107 if (m0 == NULL) { 2108 printf("%s: no receive buffers " 2109 "available -- packet dropped!\n", 2110 sc_if->sk_dev.dv_xname); 2111 ifp->if_ierrors++; 2112 continue; 2113 } 2114 m_adj(m0, ETHER_ALIGN); 2115 m = m0; 2116 } else { 2117 m->m_pkthdr.rcvif = ifp; 2118 m->m_pkthdr.len = m->m_len = total_len; 2119 } 2120 2121 ifp->if_ipackets++; 2122 2123 #if NBPFILTER > 0 2124 if (ifp->if_bpf) 2125 bpf_mtap(ifp->if_bpf, m); 2126 #endif 2127 /* pass it on. */ 2128 (*ifp->if_input)(ifp, m); 2129 } 2130 } 2131 2132 void 2133 sk_txeof(struct sk_if_softc *sc_if) 2134 { 2135 struct sk_softc *sc = sc_if->sk_softc; 2136 struct sk_tx_desc *cur_tx; 2137 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2138 u_int32_t idx, sk_ctl; 2139 struct sk_txmap_entry *entry; 2140 2141 DPRINTFN(3, ("sk_txeof\n")); 2142 2143 /* 2144 * Go through our tx ring and free mbufs for those 2145 * frames that have been sent. 2146 */ 2147 idx = sc_if->sk_cdata.sk_tx_cons; 2148 while(idx != sc_if->sk_cdata.sk_tx_prod) { 2149 SK_CDTXSYNC(sc_if, idx, 1, 2150 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2151 2152 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2153 sk_ctl = le32toh(cur_tx->sk_ctl); 2154 #ifdef SK_DEBUG 2155 if (skdebug >= 3) 2156 sk_dump_txdesc(cur_tx, idx); 2157 #endif 2158 if (sk_ctl & SK_TXCTL_OWN) { 2159 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2160 break; 2161 } 2162 if (sk_ctl & SK_TXCTL_LASTFRAG) 2163 ifp->if_opackets++; 2164 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2165 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2166 2167 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2168 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2169 2170 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2171 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2172 2173 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2174 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2175 link); 2176 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2177 } 2178 sc_if->sk_cdata.sk_tx_cnt--; 2179 SK_INC(idx, SK_TX_RING_CNT); 2180 } 2181 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2182 ifp->if_timer = 0; 2183 else /* nudge chip to keep tx ring moving */ 2184 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2185 2186 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2187 ifp->if_flags &= ~IFF_OACTIVE; 2188 2189 sc_if->sk_cdata.sk_tx_cons = idx; 2190 } 2191 2192 void 2193 sk_tick(void *xsc_if) 2194 { 2195 struct sk_if_softc *sc_if = xsc_if; 2196 struct mii_data *mii = &sc_if->sk_mii; 2197 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2198 int i; 2199 2200 DPRINTFN(3, ("sk_tick\n")); 2201 2202 if (!(ifp->if_flags & IFF_UP)) 2203 return; 2204 2205 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2206 sk_intr_bcom(sc_if); 2207 return; 2208 } 2209 2210 /* 2211 * According to SysKonnect, the correct way to verify that 2212 * the link has come back up is to poll bit 0 of the GPIO 2213 * register three times. This pin has the signal from the 2214 * link sync pin connected to it; if we read the same link 2215 * state 3 times in a row, we know the link is up. 2216 */ 2217 for (i = 0; i < 3; i++) { 2218 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2219 break; 2220 } 2221 2222 if (i != 3) { 2223 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2224 return; 2225 } 2226 2227 /* Turn the GP0 interrupt back on. */ 2228 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2229 SK_XM_READ_2(sc_if, XM_ISR); 2230 mii_tick(mii); 2231 mii_pollstat(mii); 2232 callout_stop(&sc_if->sk_tick_ch); 2233 } 2234 2235 void 2236 sk_intr_bcom(struct sk_if_softc *sc_if) 2237 { 2238 struct mii_data *mii = &sc_if->sk_mii; 2239 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2240 int status; 2241 2242 2243 DPRINTFN(3, ("sk_intr_bcom\n")); 2244 2245 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2246 2247 /* 2248 * Read the PHY interrupt register to make sure 2249 * we clear any pending interrupts. 2250 */ 2251 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2252 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2253 2254 if (!(ifp->if_flags & IFF_RUNNING)) { 2255 sk_init_xmac(sc_if); 2256 return; 2257 } 2258 2259 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2260 int lstat; 2261 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2262 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2263 2264 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2265 mii_mediachg(mii); 2266 /* Turn off the link LED. */ 2267 SK_IF_WRITE_1(sc_if, 0, 2268 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2269 sc_if->sk_link = 0; 2270 } else if (status & BRGPHY_ISR_LNK_CHG) { 2271 sk_xmac_miibus_writereg((struct device *)sc_if, 2272 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2273 mii_tick(mii); 2274 sc_if->sk_link = 1; 2275 /* Turn on the link LED. */ 2276 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2277 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2278 SK_LINKLED_BLINK_OFF); 2279 mii_pollstat(mii); 2280 } else { 2281 mii_tick(mii); 2282 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2283 } 2284 } 2285 2286 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2287 } 2288 2289 void 2290 sk_intr_xmac(struct sk_if_softc *sc_if) 2291 { 2292 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2293 2294 DPRINTFN(3, ("sk_intr_xmac\n")); 2295 2296 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2297 if (status & XM_ISR_GP0_SET) { 2298 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2299 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2300 } 2301 2302 if (status & XM_ISR_AUTONEG_DONE) { 2303 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2304 } 2305 } 2306 2307 if (status & XM_IMR_TX_UNDERRUN) 2308 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2309 2310 if (status & XM_IMR_RX_OVERRUN) 2311 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2312 } 2313 2314 void 2315 sk_intr_yukon(sc_if) 2316 struct sk_if_softc *sc_if; 2317 { 2318 int status; 2319 2320 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2321 2322 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2323 } 2324 2325 int 2326 sk_intr(void *xsc) 2327 { 2328 struct sk_softc *sc = xsc; 2329 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2330 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2331 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2332 u_int32_t status; 2333 int claimed = 0; 2334 2335 if (sc_if0 != NULL) 2336 ifp0 = &sc_if0->sk_ethercom.ec_if; 2337 if (sc_if1 != NULL) 2338 ifp1 = &sc_if1->sk_ethercom.ec_if; 2339 2340 for (;;) { 2341 status = CSR_READ_4(sc, SK_ISSR); 2342 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2343 2344 if (!(status & sc->sk_intrmask)) 2345 break; 2346 2347 claimed = 1; 2348 2349 /* Handle receive interrupts first. */ 2350 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2351 sk_rxeof(sc_if0); 2352 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2353 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2354 } 2355 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2356 sk_rxeof(sc_if1); 2357 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2358 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2359 } 2360 2361 /* Then transmit interrupts. */ 2362 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2363 sk_txeof(sc_if0); 2364 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2365 SK_TXBMU_CLR_IRQ_EOF); 2366 } 2367 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2368 sk_txeof(sc_if1); 2369 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2370 SK_TXBMU_CLR_IRQ_EOF); 2371 } 2372 2373 /* Then MAC interrupts. */ 2374 if (sc_if0 && (status & SK_ISR_MAC1) && 2375 (ifp0->if_flags & IFF_RUNNING)) { 2376 if (sc->sk_type == SK_GENESIS) 2377 sk_intr_xmac(sc_if0); 2378 else 2379 sk_intr_yukon(sc_if0); 2380 } 2381 2382 if (sc_if1 && (status & SK_ISR_MAC2) && 2383 (ifp1->if_flags & IFF_RUNNING)) { 2384 if (sc->sk_type == SK_GENESIS) 2385 sk_intr_xmac(sc_if1); 2386 else 2387 sk_intr_yukon(sc_if1); 2388 2389 } 2390 2391 if (status & SK_ISR_EXTERNAL_REG) { 2392 if (sc_if0 != NULL && 2393 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2394 sk_intr_bcom(sc_if0); 2395 2396 if (sc_if1 != NULL && 2397 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2398 sk_intr_bcom(sc_if1); 2399 } 2400 } 2401 2402 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2403 2404 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2405 sk_start(ifp0); 2406 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2407 sk_start(ifp1); 2408 2409 #if NRND > 0 2410 if (RND_ENABLED(&sc->rnd_source)) 2411 rnd_add_uint32(&sc->rnd_source, status); 2412 #endif 2413 2414 if (sc->sk_int_mod_pending) 2415 sk_update_int_mod(sc); 2416 2417 return (claimed); 2418 } 2419 2420 void 2421 sk_init_xmac(struct sk_if_softc *sc_if) 2422 { 2423 struct sk_softc *sc = sc_if->sk_softc; 2424 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2425 static const struct sk_bcom_hack bhack[] = { 2426 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2427 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2428 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2429 { 0, 0 } }; 2430 2431 DPRINTFN(1, ("sk_init_xmac\n")); 2432 2433 /* Unreset the XMAC. */ 2434 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2435 DELAY(1000); 2436 2437 /* Reset the XMAC's internal state. */ 2438 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2439 2440 /* Save the XMAC II revision */ 2441 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2442 2443 /* 2444 * Perform additional initialization for external PHYs, 2445 * namely for the 1000baseTX cards that use the XMAC's 2446 * GMII mode. 2447 */ 2448 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2449 int i = 0; 2450 u_int32_t val; 2451 2452 /* Take PHY out of reset. */ 2453 val = sk_win_read_4(sc, SK_GPIO); 2454 if (sc_if->sk_port == SK_PORT_A) 2455 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2456 else 2457 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2458 sk_win_write_4(sc, SK_GPIO, val); 2459 2460 /* Enable GMII mode on the XMAC. */ 2461 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2462 2463 sk_xmac_miibus_writereg((struct device *)sc_if, 2464 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2465 DELAY(10000); 2466 sk_xmac_miibus_writereg((struct device *)sc_if, 2467 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2468 2469 /* 2470 * Early versions of the BCM5400 apparently have 2471 * a bug that requires them to have their reserved 2472 * registers initialized to some magic values. I don't 2473 * know what the numbers do, I'm just the messenger. 2474 */ 2475 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2476 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2477 while(bhack[i].reg) { 2478 sk_xmac_miibus_writereg((struct device *)sc_if, 2479 SK_PHYADDR_BCOM, bhack[i].reg, 2480 bhack[i].val); 2481 i++; 2482 } 2483 } 2484 } 2485 2486 /* Set station address */ 2487 SK_XM_WRITE_2(sc_if, XM_PAR0, 2488 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2489 SK_XM_WRITE_2(sc_if, XM_PAR1, 2490 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2491 SK_XM_WRITE_2(sc_if, XM_PAR2, 2492 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2493 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2494 2495 if (ifp->if_flags & IFF_PROMISC) { 2496 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2497 } else { 2498 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2499 } 2500 2501 if (ifp->if_flags & IFF_BROADCAST) { 2502 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2503 } else { 2504 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2505 } 2506 2507 /* We don't need the FCS appended to the packet. */ 2508 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2509 2510 /* We want short frames padded to 60 bytes. */ 2511 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2512 2513 /* 2514 * Enable the reception of all error frames. This is is 2515 * a necessary evil due to the design of the XMAC. The 2516 * XMAC's receive FIFO is only 8K in size, however jumbo 2517 * frames can be up to 9000 bytes in length. When bad 2518 * frame filtering is enabled, the XMAC's RX FIFO operates 2519 * in 'store and forward' mode. For this to work, the 2520 * entire frame has to fit into the FIFO, but that means 2521 * that jumbo frames larger than 8192 bytes will be 2522 * truncated. Disabling all bad frame filtering causes 2523 * the RX FIFO to operate in streaming mode, in which 2524 * case the XMAC will start transfering frames out of the 2525 * RX FIFO as soon as the FIFO threshold is reached. 2526 */ 2527 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2528 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2529 XM_MODE_RX_INRANGELEN); 2530 2531 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2532 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2533 else 2534 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2535 2536 /* 2537 * Bump up the transmit threshold. This helps hold off transmit 2538 * underruns when we're blasting traffic from both ports at once. 2539 */ 2540 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2541 2542 /* Set multicast filter */ 2543 sk_setmulti(sc_if); 2544 2545 /* Clear and enable interrupts */ 2546 SK_XM_READ_2(sc_if, XM_ISR); 2547 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2548 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2549 else 2550 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2551 2552 /* Configure MAC arbiter */ 2553 switch(sc_if->sk_xmac_rev) { 2554 case XM_XMAC_REV_B2: 2555 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2556 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2557 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2558 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2559 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2560 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2561 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2562 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2563 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2564 break; 2565 case XM_XMAC_REV_C1: 2566 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2567 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2568 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2569 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2570 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2571 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2572 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2573 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2574 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2575 break; 2576 default: 2577 break; 2578 } 2579 sk_win_write_2(sc, SK_MACARB_CTL, 2580 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2581 2582 sc_if->sk_link = 1; 2583 } 2584 2585 void sk_init_yukon(sc_if) 2586 struct sk_if_softc *sc_if; 2587 { 2588 u_int32_t /*mac, */phy; 2589 u_int16_t reg; 2590 struct sk_softc *sc; 2591 int i; 2592 2593 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2594 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2595 2596 sc = sc_if->sk_softc; 2597 if (sc->sk_type == SK_YUKON_LITE && 2598 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2599 /* Take PHY out of reset. */ 2600 sk_win_write_4(sc, SK_GPIO, 2601 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2602 } 2603 2604 2605 /* GMAC and GPHY Reset */ 2606 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2607 2608 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2609 2610 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2611 DELAY(1000); 2612 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2613 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2614 DELAY(1000); 2615 2616 2617 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2618 2619 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2620 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2621 2622 switch(sc_if->sk_softc->sk_pmd) { 2623 case IFM_1000_SX: 2624 case IFM_1000_LX: 2625 phy |= SK_GPHY_FIBER; 2626 break; 2627 2628 case IFM_1000_CX: 2629 case IFM_1000_T: 2630 phy |= SK_GPHY_COPPER; 2631 break; 2632 } 2633 2634 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2635 2636 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2637 DELAY(1000); 2638 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2639 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2640 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2641 2642 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2643 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2644 2645 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2646 2647 /* unused read of the interrupt source register */ 2648 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2649 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2650 2651 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2652 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2653 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2654 2655 /* MIB Counter Clear Mode set */ 2656 reg |= YU_PAR_MIB_CLR; 2657 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2658 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2659 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2660 2661 /* MIB Counter Clear Mode clear */ 2662 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2663 reg &= ~YU_PAR_MIB_CLR; 2664 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2665 2666 /* receive control reg */ 2667 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2668 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2669 YU_RCR_CRCR); 2670 2671 /* transmit parameter register */ 2672 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2673 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2674 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2675 2676 /* serial mode register */ 2677 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2678 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2679 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2680 YU_SMR_IPG_DATA(0x1e)); 2681 2682 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2683 /* Setup Yukon's address */ 2684 for (i = 0; i < 3; i++) { 2685 /* Write Source Address 1 (unicast filter) */ 2686 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2687 sc_if->sk_enaddr[i * 2] | 2688 sc_if->sk_enaddr[i * 2 + 1] << 8); 2689 } 2690 2691 for (i = 0; i < 3; i++) { 2692 reg = sk_win_read_2(sc_if->sk_softc, 2693 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2694 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2695 } 2696 2697 /* Set multicast filter */ 2698 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2699 sk_setmulti(sc_if); 2700 2701 /* enable interrupt mask for counter overflows */ 2702 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2703 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2704 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2705 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2706 2707 /* Configure RX MAC FIFO */ 2708 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2709 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2710 2711 /* Configure TX MAC FIFO */ 2712 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2713 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2714 2715 DPRINTFN(6, ("sk_init_yukon: end\n")); 2716 } 2717 2718 /* 2719 * Note that to properly initialize any part of the GEnesis chip, 2720 * you first have to take it out of reset mode. 2721 */ 2722 int 2723 sk_init(struct ifnet *ifp) 2724 { 2725 struct sk_if_softc *sc_if = ifp->if_softc; 2726 struct sk_softc *sc = sc_if->sk_softc; 2727 struct mii_data *mii = &sc_if->sk_mii; 2728 int s; 2729 u_int32_t imr, sk_imtimer_ticks; 2730 2731 DPRINTFN(1, ("sk_init\n")); 2732 2733 s = splnet(); 2734 2735 if (ifp->if_flags & IFF_RUNNING) { 2736 splx(s); 2737 return 0; 2738 } 2739 2740 /* Cancel pending I/O and free all RX/TX buffers. */ 2741 sk_stop(ifp,0); 2742 2743 if (sc->sk_type == SK_GENESIS) { 2744 /* Configure LINK_SYNC LED */ 2745 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2746 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2747 SK_LINKLED_LINKSYNC_ON); 2748 2749 /* Configure RX LED */ 2750 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2751 SK_RXLEDCTL_COUNTER_START); 2752 2753 /* Configure TX LED */ 2754 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2755 SK_TXLEDCTL_COUNTER_START); 2756 } 2757 2758 /* Configure I2C registers */ 2759 2760 /* Configure XMAC(s) */ 2761 switch (sc->sk_type) { 2762 case SK_GENESIS: 2763 sk_init_xmac(sc_if); 2764 break; 2765 case SK_YUKON: 2766 case SK_YUKON_LITE: 2767 case SK_YUKON_LP: 2768 sk_init_yukon(sc_if); 2769 break; 2770 } 2771 mii_mediachg(mii); 2772 2773 if (sc->sk_type == SK_GENESIS) { 2774 /* Configure MAC FIFOs */ 2775 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2776 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2777 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2778 2779 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2780 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2781 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2782 } 2783 2784 /* Configure transmit arbiter(s) */ 2785 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2786 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2787 2788 /* Configure RAMbuffers */ 2789 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2790 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2791 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2792 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2793 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2794 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2795 2796 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2797 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2798 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2799 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2800 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2801 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2802 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2803 2804 /* Configure BMUs */ 2805 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2806 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2807 SK_RX_RING_ADDR(sc_if, 0)); 2808 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2809 2810 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2811 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2812 SK_TX_RING_ADDR(sc_if, 0)); 2813 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2814 2815 /* Init descriptors */ 2816 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2817 printf("%s: initialization failed: no " 2818 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2819 sk_stop(ifp,0); 2820 splx(s); 2821 return(ENOBUFS); 2822 } 2823 2824 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2825 printf("%s: initialization failed: no " 2826 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2827 sk_stop(ifp,0); 2828 splx(s); 2829 return(ENOBUFS); 2830 } 2831 2832 /* Set interrupt moderation if changed via sysctl. */ 2833 switch (sc->sk_type) { 2834 case SK_GENESIS: 2835 sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2836 break; 2837 case SK_YUKON_EC: 2838 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2839 break; 2840 default: 2841 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2842 } 2843 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2844 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2845 sk_win_write_4(sc, SK_IMTIMERINIT, 2846 SK_IM_USECS(sc->sk_int_mod)); 2847 aprint_verbose("%s: interrupt moderation is %d us\n", 2848 sc->sk_dev.dv_xname, sc->sk_int_mod); 2849 } 2850 2851 /* Configure interrupt handling */ 2852 CSR_READ_4(sc, SK_ISSR); 2853 if (sc_if->sk_port == SK_PORT_A) 2854 sc->sk_intrmask |= SK_INTRS1; 2855 else 2856 sc->sk_intrmask |= SK_INTRS2; 2857 2858 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2859 2860 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2861 2862 /* Start BMUs. */ 2863 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2864 2865 if (sc->sk_type == SK_GENESIS) { 2866 /* Enable XMACs TX and RX state machines */ 2867 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2868 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2869 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2870 } 2871 2872 if (SK_YUKON_FAMILY(sc->sk_type)) { 2873 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2874 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2875 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2876 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2877 } 2878 2879 2880 ifp->if_flags |= IFF_RUNNING; 2881 ifp->if_flags &= ~IFF_OACTIVE; 2882 2883 splx(s); 2884 return(0); 2885 } 2886 2887 void 2888 sk_stop(struct ifnet *ifp, int disable) 2889 { 2890 struct sk_if_softc *sc_if = ifp->if_softc; 2891 struct sk_softc *sc = sc_if->sk_softc; 2892 //struct sk_txmap_entry *dma; 2893 int i; 2894 2895 DPRINTFN(1, ("sk_stop\n")); 2896 2897 callout_stop(&sc_if->sk_tick_ch); 2898 2899 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2900 u_int32_t val; 2901 2902 /* Put PHY back into reset. */ 2903 val = sk_win_read_4(sc, SK_GPIO); 2904 if (sc_if->sk_port == SK_PORT_A) { 2905 val |= SK_GPIO_DIR0; 2906 val &= ~SK_GPIO_DAT0; 2907 } else { 2908 val |= SK_GPIO_DIR2; 2909 val &= ~SK_GPIO_DAT2; 2910 } 2911 sk_win_write_4(sc, SK_GPIO, val); 2912 } 2913 2914 /* Turn off various components of this interface. */ 2915 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2916 switch (sc->sk_type) { 2917 case SK_GENESIS: 2918 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2919 SK_TXMACCTL_XMAC_RESET); 2920 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2921 break; 2922 case SK_YUKON: 2923 case SK_YUKON_LITE: 2924 case SK_YUKON_LP: 2925 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2926 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2927 break; 2928 } 2929 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2930 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2931 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2932 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2933 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2934 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2935 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2936 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2937 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2938 2939 /* Disable interrupts */ 2940 if (sc_if->sk_port == SK_PORT_A) 2941 sc->sk_intrmask &= ~SK_INTRS1; 2942 else 2943 sc->sk_intrmask &= ~SK_INTRS2; 2944 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2945 2946 SK_XM_READ_2(sc_if, XM_ISR); 2947 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2948 2949 /* Free RX and TX mbufs still in the queues. */ 2950 for (i = 0; i < SK_RX_RING_CNT; i++) { 2951 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2952 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2953 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2954 } 2955 } 2956 2957 for (i = 0; i < SK_TX_RING_CNT; i++) { 2958 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2959 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2960 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2961 } 2962 } 2963 2964 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2965 } 2966 2967 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2968 2969 /* 2970 struct cfdriver skc_cd = { 2971 0, "skc", DV_DULL 2972 }; 2973 */ 2974 2975 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2976 2977 /* 2978 struct cfdriver sk_cd = { 2979 0, "sk", DV_IFNET 2980 }; 2981 */ 2982 2983 #ifdef SK_DEBUG 2984 void 2985 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2986 { 2987 #define DESC_PRINT(X) \ 2988 if (X) \ 2989 printf("txdesc[%d]." #X "=%#x\n", \ 2990 idx, X); 2991 2992 DESC_PRINT(le32toh(desc->sk_ctl)); 2993 DESC_PRINT(le32toh(desc->sk_next)); 2994 DESC_PRINT(le32toh(desc->sk_data_lo)); 2995 DESC_PRINT(le32toh(desc->sk_data_hi)); 2996 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2997 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2998 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2999 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 3000 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 3001 DESC_PRINT(le16toh(desc->sk_rsvd1)); 3002 #undef PRINT 3003 } 3004 3005 void 3006 sk_dump_bytes(const char *data, int len) 3007 { 3008 int c, i, j; 3009 3010 for (i = 0; i < len; i += 16) { 3011 printf("%08x ", i); 3012 c = len - i; 3013 if (c > 16) c = 16; 3014 3015 for (j = 0; j < c; j++) { 3016 printf("%02x ", data[i + j] & 0xff); 3017 if ((j & 0xf) == 7 && j > 0) 3018 printf(" "); 3019 } 3020 3021 for (; j < 16; j++) 3022 printf(" "); 3023 printf(" "); 3024 3025 for (j = 0; j < c; j++) { 3026 int ch = data[i + j] & 0xff; 3027 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3028 } 3029 3030 printf("\n"); 3031 3032 if (c < 16) 3033 break; 3034 } 3035 } 3036 3037 void 3038 sk_dump_mbuf(struct mbuf *m) 3039 { 3040 int count = m->m_pkthdr.len; 3041 3042 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3043 3044 while (count > 0 && m) { 3045 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3046 m, m->m_data, m->m_len); 3047 sk_dump_bytes(mtod(m, char *), m->m_len); 3048 3049 count -= m->m_len; 3050 m = m->m_next; 3051 } 3052 } 3053 #endif 3054 3055 static int 3056 sk_sysctl_handler(SYSCTLFN_ARGS) 3057 { 3058 int error, t; 3059 struct sysctlnode node; 3060 struct sk_softc *sc; 3061 3062 node = *rnode; 3063 sc = node.sysctl_data; 3064 t = sc->sk_int_mod; 3065 node.sysctl_data = &t; 3066 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3067 if (error || newp == NULL) 3068 return (error); 3069 3070 if (t < SK_IM_MIN || t > SK_IM_MAX) 3071 return (EINVAL); 3072 3073 /* update the softc with sysctl-changed value, and mark 3074 for hardware update */ 3075 sc->sk_int_mod = t; 3076 sc->sk_int_mod_pending = 1; 3077 return (0); 3078 } 3079 3080 /* 3081 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3082 * set up in skc_attach() 3083 */ 3084 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3085 { 3086 int rc; 3087 const struct sysctlnode *node; 3088 3089 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3090 0, CTLTYPE_NODE, "hw", NULL, 3091 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3092 goto err; 3093 } 3094 3095 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3096 0, CTLTYPE_NODE, "sk", 3097 SYSCTL_DESCR("sk interface controls"), 3098 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3099 goto err; 3100 } 3101 3102 sk_root_num = node->sysctl_num; 3103 return; 3104 3105 err: 3106 printf("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3107 } 3108
Indexes created Mon Sep 22 21:09:42 GMT 2025