if_sk.c revision 1.3
1 /* $NetBSD: if_sk.c,v 1.3 2003/10/15 02:18:52 briggs Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 126 #include <sys/param.h> 127 #include <sys/systm.h> 128 #include <sys/sockio.h> 129 #include <sys/mbuf.h> 130 #include <sys/malloc.h> 131 #include <sys/kernel.h> 132 #include <sys/socket.h> 133 #include <sys/device.h> 134 #include <sys/queue.h> 135 #include <sys/callout.h> 136 137 #include <net/if.h> 138 #include <net/if_dl.h> 139 #include <net/if_types.h> 140 141 #ifdef INET 142 #include <netinet/in.h> 143 #include <netinet/in_systm.h> 144 #include <netinet/in_var.h> 145 #include <netinet/ip.h> 146 #include <netinet/if_ether.h> 147 #endif 148 149 #include <net/if_media.h> 150 151 #if NBPFILTER > 0 152 #include <net/bpf.h> 153 #endif 154 155 #include <dev/mii/mii.h> 156 #include <dev/mii/miivar.h> 157 #include <dev/mii/brgphyreg.h> 158 159 #include <dev/pci/pcireg.h> 160 #include <dev/pci/pcivar.h> 161 #include <dev/pci/pcidevs.h> 162 163 #define SK_VERBOSE 164 /* #define SK_USEIOSPACE */ 165 166 #include <dev/pci/if_skreg.h> 167 #include <dev/pci/if_skvar.h> 168 169 int skc_probe(struct device *, struct cfdata *, void *); 170 void skc_attach(struct device *, struct device *self, void *aux); 171 int sk_probe(struct device *, struct cfdata *, void *); 172 void sk_attach(struct device *, struct device *self, void *aux); 173 int skcprint(void *, const char *); 174 int sk_intr(void *); 175 void sk_intr_bcom(struct sk_if_softc *); 176 void sk_intr_xmac(struct sk_if_softc *); 177 void sk_intr_yukon(struct sk_if_softc *); 178 void sk_rxeof(struct sk_if_softc *); 179 void sk_txeof(struct sk_if_softc *); 180 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 181 void sk_start(struct ifnet *); 182 int sk_ioctl(struct ifnet *, u_long, caddr_t); 183 int sk_init(struct ifnet *); 184 void sk_init_xmac(struct sk_if_softc *); 185 void sk_init_yukon(struct sk_if_softc *); 186 void sk_stop(struct ifnet *, int); 187 void sk_watchdog(struct ifnet *); 188 void sk_shutdown(void *); 189 int sk_ifmedia_upd(struct ifnet *); 190 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 191 void sk_reset(struct sk_softc *); 192 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 193 int sk_init_rx_ring(struct sk_if_softc *); 194 int sk_init_tx_ring(struct sk_if_softc *); 195 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 196 void sk_vpd_read_res(struct sk_softc *, 197 struct vpd_res *, int); 198 void sk_vpd_read(struct sk_softc *); 199 200 int sk_xmac_miibus_readreg(struct device *, int, int); 201 void sk_xmac_miibus_writereg(struct device *, int, int, int); 202 void sk_xmac_miibus_statchg(struct device *); 203 204 int sk_marv_miibus_readreg(struct device *, int, int); 205 void sk_marv_miibus_writereg(struct device *, int, int, int); 206 void sk_marv_miibus_statchg(struct device *); 207 208 u_int32_t sk_calchash(caddr_t); 209 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 210 void sk_setmulti(struct sk_if_softc *); 211 void sk_tick(void *); 212 213 /* #define SK_DEBUG 2 */ 214 #ifdef SK_DEBUG 215 #define DPRINTF(x) if (skdebug) printf x 216 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 217 int skdebug = SK_DEBUG; 218 219 void sk_dump_txdesc(struct sk_tx_desc *, int); 220 void sk_dump_mbuf(struct mbuf *); 221 void sk_dump_bytes(const char *, int); 222 #else 223 #define DPRINTF(x) 224 #define DPRINTFN(n,x) 225 #endif 226 227 #define SK_SETBIT(sc, reg, x) \ 228 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 229 230 #define SK_CLRBIT(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 232 233 #define SK_WIN_SETBIT_4(sc, reg, x) \ 234 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 235 236 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 237 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 238 239 #define SK_WIN_SETBIT_2(sc, reg, x) \ 240 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 241 242 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 243 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 244 245 /* supported device vendors */ 246 static const struct sk_product { 247 pci_vendor_id_t sk_vendor; 248 pci_product_id_t sk_product; 249 } sk_products[] = { 250 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 251 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 252 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 253 { 0, 0, } 254 }; 255 256 static inline u_int32_t 257 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 258 { 259 #ifdef SK_USEIOSPACE 260 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 261 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 262 #else 263 return CSR_READ_4(sc, reg); 264 #endif 265 } 266 267 static inline u_int16_t 268 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 269 { 270 #ifdef SK_USEIOSPACE 271 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 272 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 273 #else 274 return CSR_READ_2(sc, reg); 275 #endif 276 } 277 278 static inline u_int8_t 279 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 280 { 281 #ifdef SK_USEIOSPACE 282 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 283 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 284 #else 285 return CSR_READ_1(sc, reg); 286 #endif 287 } 288 289 static inline void 290 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 291 { 292 #ifdef SK_USEIOSPACE 293 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 294 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 295 #else 296 CSR_WRITE_4(sc, reg, x); 297 #endif 298 } 299 300 static inline void 301 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 302 { 303 #ifdef SK_USEIOSPACE 304 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 305 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 306 #else 307 CSR_WRITE_2(sc, reg, x); 308 #endif 309 } 310 311 static inline void 312 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 313 { 314 #ifdef SK_USEIOSPACE 315 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 316 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 317 #else 318 CSR_WRITE_1(sc, reg, x); 319 #endif 320 } 321 322 /* 323 * The VPD EEPROM contains Vital Product Data, as suggested in 324 * the PCI 2.1 specification. The VPD data is separared into areas 325 * denoted by resource IDs. The SysKonnect VPD contains an ID string 326 * resource (the name of the adapter), a read-only area resource 327 * containing various key/data fields and a read/write area which 328 * can be used to store asset management information or log messages. 329 * We read the ID string and read-only into buffers attached to 330 * the controller softc structure for later use. At the moment, 331 * we only use the ID string during sk_attach(). 332 */ 333 u_int8_t 334 sk_vpd_readbyte(struct sk_softc *sc, int addr) 335 { 336 int i; 337 338 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 339 for (i = 0; i < SK_TIMEOUT; i++) { 340 DELAY(1); 341 if (sk_win_read_2(sc, 342 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 343 break; 344 } 345 346 if (i == SK_TIMEOUT) 347 return(0); 348 349 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 350 } 351 352 void 353 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 354 { 355 int i; 356 u_int8_t *ptr; 357 358 ptr = (u_int8_t *)res; 359 for (i = 0; i < sizeof(struct vpd_res); i++) 360 ptr[i] = sk_vpd_readbyte(sc, i + addr); 361 } 362 363 void 364 sk_vpd_read(struct sk_softc *sc) 365 { 366 int pos = 0, i; 367 struct vpd_res res; 368 369 if (sc->sk_vpd_prodname != NULL) 370 free(sc->sk_vpd_prodname, M_DEVBUF); 371 if (sc->sk_vpd_readonly != NULL) 372 free(sc->sk_vpd_readonly, M_DEVBUF); 373 sc->sk_vpd_prodname = NULL; 374 sc->sk_vpd_readonly = NULL; 375 376 sk_vpd_read_res(sc, &res, pos); 377 378 if (res.vr_id != VPD_RES_ID) { 379 printf("%s: bad VPD resource id: expected %x got %x\n", 380 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 381 return; 382 } 383 384 pos += sizeof(res); 385 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 386 if (sc->sk_vpd_prodname == NULL) 387 panic("sk_vpd_read"); 388 for (i = 0; i < res.vr_len; i++) 389 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 390 sc->sk_vpd_prodname[i] = '\0'; 391 pos += i; 392 393 sk_vpd_read_res(sc, &res, pos); 394 395 if (res.vr_id != VPD_RES_READ) { 396 printf("%s: bad VPD resource id: expected %x got %x\n", 397 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 398 return; 399 } 400 401 pos += sizeof(res); 402 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 403 if (sc->sk_vpd_readonly == NULL) 404 panic("sk_vpd_read"); 405 for (i = 0; i < res.vr_len + 1; i++) 406 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 407 } 408 409 int 410 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 411 { 412 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 413 int i; 414 415 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 416 417 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 418 return(0); 419 420 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 421 SK_XM_READ_2(sc_if, XM_PHY_DATA); 422 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 423 for (i = 0; i < SK_TIMEOUT; i++) { 424 DELAY(1); 425 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 426 XM_MMUCMD_PHYDATARDY) 427 break; 428 } 429 430 if (i == SK_TIMEOUT) { 431 printf("%s: phy failed to come ready\n", 432 sc_if->sk_dev.dv_xname); 433 return(0); 434 } 435 } 436 DELAY(1); 437 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 438 } 439 440 void 441 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 442 { 443 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 444 int i; 445 446 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 447 448 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 449 for (i = 0; i < SK_TIMEOUT; i++) { 450 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 451 break; 452 } 453 454 if (i == SK_TIMEOUT) { 455 printf("%s: phy failed to come ready\n", 456 sc_if->sk_dev.dv_xname); 457 return; 458 } 459 460 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 461 for (i = 0; i < SK_TIMEOUT; i++) { 462 DELAY(1); 463 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 464 break; 465 } 466 467 if (i == SK_TIMEOUT) 468 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 469 } 470 471 void 472 sk_xmac_miibus_statchg(struct device *dev) 473 { 474 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 475 struct mii_data *mii = &sc_if->sk_mii; 476 477 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 478 479 /* 480 * If this is a GMII PHY, manually set the XMAC's 481 * duplex mode accordingly. 482 */ 483 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 484 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 485 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 486 } else { 487 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 488 } 489 } 490 } 491 492 int 493 sk_marv_miibus_readreg(dev, phy, reg) 494 struct device *dev; 495 int phy, reg; 496 { 497 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 498 u_int16_t val; 499 int i; 500 501 if (phy != 0 || 502 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 503 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 504 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 505 phy, reg)); 506 return(0); 507 } 508 509 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 510 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 511 512 for (i = 0; i < SK_TIMEOUT; i++) { 513 DELAY(1); 514 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 515 if (val & YU_SMICR_READ_VALID) 516 break; 517 } 518 519 if (i == SK_TIMEOUT) { 520 printf("%s: phy failed to come ready\n", 521 sc_if->sk_dev.dv_xname); 522 return 0; 523 } 524 525 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 526 SK_TIMEOUT)); 527 528 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 529 530 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 531 phy, reg, val)); 532 533 return val; 534 } 535 536 void 537 sk_marv_miibus_writereg(dev, phy, reg, val) 538 struct device *dev; 539 int phy, reg, val; 540 { 541 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 542 int i; 543 544 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 545 phy, reg, val)); 546 547 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 548 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 549 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 550 551 for (i = 0; i < SK_TIMEOUT; i++) { 552 DELAY(1); 553 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 554 break; 555 } 556 } 557 558 void 559 sk_marv_miibus_statchg(dev) 560 struct device *dev; 561 { 562 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 563 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 564 } 565 566 #define SK_BITS 6 567 #define SK_POLY 0xEDB88320 568 569 u_int32_t 570 sk_calchash(caddr_t addr) 571 { 572 u_int32_t crc; 573 574 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 575 crc = ~crc & ((1<< SK_BITS) - 1); 576 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 577 return (crc); 578 } 579 580 void 581 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 582 { 583 int base = XM_RXFILT_ENTRY(slot); 584 585 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 586 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 587 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 588 } 589 590 void 591 sk_setmulti(struct sk_if_softc *sc_if) 592 { 593 struct sk_softc *sc = sc_if->sk_softc; 594 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 595 u_int32_t hashes[2] = { 0, 0 }; 596 int h, i; 597 struct ethercom *ec = &sc_if->sk_ethercom; 598 struct ether_multi *enm; 599 struct ether_multistep step; 600 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 601 602 /* First, zot all the existing filters. */ 603 switch(sc->sk_type) { 604 case SK_GENESIS: 605 for (i = 1; i < XM_RXFILT_MAX; i++) 606 sk_setfilt(sc_if, (caddr_t)&dummy, i); 607 608 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 609 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 610 break; 611 case SK_YUKON: 612 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 613 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 614 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 615 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 616 break; 617 } 618 619 /* Now program new ones. */ 620 allmulti: 621 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 622 hashes[0] = 0xFFFFFFFF; 623 hashes[1] = 0xFFFFFFFF; 624 } else { 625 i = 1; 626 /* First find the tail of the list. */ 627 ETHER_FIRST_MULTI(step, ec, enm); 628 while (enm != NULL) { 629 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 630 ETHER_ADDR_LEN)) { 631 ifp->if_flags |= IFF_ALLMULTI; 632 goto allmulti; 633 } 634 DPRINTFN(2,("multicast address %s\n", 635 ether_sprintf(enm->enm_addrlo))); 636 /* 637 * Program the first XM_RXFILT_MAX multicast groups 638 * into the perfect filter. For all others, 639 * use the hash table. 640 */ 641 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 642 sk_setfilt(sc_if, enm->enm_addrlo, i); 643 i++; 644 } 645 else { 646 h = sk_calchash(enm->enm_addrlo); 647 if (h < 32) 648 hashes[0] |= (1 << h); 649 else 650 hashes[1] |= (1 << (h - 32)); 651 } 652 653 ETHER_NEXT_MULTI(step, enm); 654 } 655 } 656 657 switch(sc->sk_type) { 658 case SK_GENESIS: 659 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 660 XM_MODE_RX_USE_PERFECT); 661 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 662 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 663 break; 664 case SK_YUKON: 665 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 666 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 667 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 668 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 669 break; 670 } 671 } 672 673 int 674 sk_init_rx_ring(struct sk_if_softc *sc_if) 675 { 676 struct sk_chain_data *cd = &sc_if->sk_cdata; 677 struct sk_ring_data *rd = sc_if->sk_rdata; 678 int i; 679 680 bzero((char *)rd->sk_rx_ring, 681 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 682 683 for (i = 0; i < SK_RX_RING_CNT; i++) { 684 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 685 if (i == (SK_RX_RING_CNT - 1)) { 686 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 687 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 688 } else { 689 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 690 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 691 } 692 } 693 694 for (i = 0; i < SK_RX_RING_CNT; i++) { 695 if (sk_newbuf(sc_if, i, NULL, NULL) == ENOBUFS) { 696 printf("%s: failed alloc of %dth mbuf\n", 697 sc_if->sk_dev.dv_xname, i); 698 return(ENOBUFS); 699 } 700 } 701 sc_if->sk_cdata.sk_rx_prod = 0; 702 sc_if->sk_cdata.sk_rx_cons = 0; 703 704 return(0); 705 } 706 707 int 708 sk_init_tx_ring(struct sk_if_softc *sc_if) 709 { 710 struct sk_chain_data *cd = &sc_if->sk_cdata; 711 struct sk_ring_data *rd = sc_if->sk_rdata; 712 int i; 713 714 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 715 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 716 717 for (i = 0; i < SK_TX_RING_CNT; i++) { 718 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 719 if (i == (SK_TX_RING_CNT - 1)) { 720 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 721 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 722 } else { 723 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 724 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 725 } 726 } 727 728 sc_if->sk_cdata.sk_tx_prod = 0; 729 sc_if->sk_cdata.sk_tx_cons = 0; 730 sc_if->sk_cdata.sk_tx_cnt = 0; 731 732 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 733 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 734 735 return (0); 736 } 737 738 int 739 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 740 bus_dmamap_t dmamap) 741 { 742 struct sk_softc *sc = sc_if->sk_softc; 743 struct mbuf *m_new = NULL; 744 struct sk_chain *c; 745 struct sk_rx_desc *r; 746 747 if (dmamap == NULL) { 748 /* if (m) panic() */ 749 750 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES, 751 0, BUS_DMA_NOWAIT, &dmamap)) { 752 printf("%s: can't create recv map\n", 753 sc_if->sk_dev.dv_xname); 754 return(ENOMEM); 755 } 756 } else if (m == NULL) 757 bus_dmamap_unload(sc->sc_dmatag, dmamap); 758 759 sc_if->sk_cdata.sk_rx_map[i] = dmamap; 760 761 if (m == NULL) { 762 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 763 if (m_new == NULL) { 764 printf("%s: no memory for rx list -- " 765 "packet dropped!\n", sc_if->sk_dev.dv_xname); 766 return(ENOBUFS); 767 } 768 769 /* Allocate the jumbo buffer */ 770 MCLGET(m_new, M_DONTWAIT); 771 if (!(m_new->m_flags & M_EXT)) { 772 m_freem(m_new); 773 return (ENOBUFS); 774 } 775 776 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 777 778 m_adj(m_new, ETHER_ALIGN); 779 780 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new, 781 BUS_DMA_NOWAIT)) 782 return(ENOBUFS); 783 } else { 784 /* 785 * We're re-using a previously allocated mbuf; 786 * be sure to re-init pointers and lengths to 787 * default values. 788 */ 789 m_new = m; 790 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 791 m_adj(m_new, ETHER_ALIGN); 792 m_new->m_data = m_new->m_ext.ext_buf; 793 } 794 795 c = &sc_if->sk_cdata.sk_rx_chain[i]; 796 r = c->sk_desc; 797 c->sk_mbuf = m_new; 798 r->sk_data_lo = dmamap->dm_segs[0].ds_addr; 799 r->sk_ctl = dmamap->dm_segs[0].ds_len | SK_RXSTAT; 800 801 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 802 803 return(0); 804 } 805 806 /* 807 * Set media options. 808 */ 809 int 810 sk_ifmedia_upd(struct ifnet *ifp) 811 { 812 struct sk_if_softc *sc_if = ifp->if_softc; 813 814 (void) sk_init(ifp); 815 mii_mediachg(&sc_if->sk_mii); 816 return(0); 817 } 818 819 /* 820 * Report current media status. 821 */ 822 void 823 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 824 { 825 struct sk_if_softc *sc_if = ifp->if_softc; 826 827 mii_pollstat(&sc_if->sk_mii); 828 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 829 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 830 } 831 832 int 833 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 834 { 835 struct sk_if_softc *sc_if = ifp->if_softc; 836 struct sk_softc *sc = sc_if->sk_softc; 837 struct ifreq *ifr = (struct ifreq *) data; 838 /* struct ifaddr *ifa = (struct ifaddr *) data; */ 839 struct mii_data *mii; 840 int s, error = 0; 841 842 /* DPRINTFN(2, ("sk_ioctl\n")); */ 843 844 s = splnet(); 845 846 switch(command) { 847 848 case SIOCSIFFLAGS: 849 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 850 if (ifp->if_flags & IFF_UP) { 851 if (ifp->if_flags & IFF_RUNNING && 852 ifp->if_flags & IFF_PROMISC && 853 !(sc_if->sk_if_flags & IFF_PROMISC)) { 854 switch(sc->sk_type) { 855 case SK_GENESIS: 856 SK_XM_SETBIT_4(sc_if, XM_MODE, 857 XM_MODE_RX_PROMISC); 858 break; 859 case SK_YUKON: 860 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 861 YU_RCR_UFLEN | YU_RCR_MUFLEN); 862 break; 863 } 864 sk_setmulti(sc_if); 865 } else if (ifp->if_flags & IFF_RUNNING && 866 !(ifp->if_flags & IFF_PROMISC) && 867 sc_if->sk_if_flags & IFF_PROMISC) { 868 switch(sc->sk_type) { 869 case SK_GENESIS: 870 SK_XM_CLRBIT_4(sc_if, XM_MODE, 871 XM_MODE_RX_PROMISC); 872 break; 873 case SK_YUKON: 874 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 875 YU_RCR_UFLEN | YU_RCR_MUFLEN); 876 break; 877 } 878 879 sk_setmulti(sc_if); 880 } else 881 (void) sk_init(ifp); 882 } else { 883 if (ifp->if_flags & IFF_RUNNING) 884 sk_stop(ifp,0); 885 } 886 sc_if->sk_if_flags = ifp->if_flags; 887 error = 0; 888 break; 889 890 case SIOCGIFMEDIA: 891 case SIOCSIFMEDIA: 892 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 893 mii = &sc_if->sk_mii; 894 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 895 break; 896 default: 897 DPRINTFN(2, ("sk_ioctl ETHER\n")); 898 error = ether_ioctl(ifp, command, data); 899 900 if ( error == ENETRESET) { 901 sk_setmulti(sc_if); 902 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 903 error = 0; 904 } else if ( error ) { 905 splx(s); 906 return error; 907 } 908 break; 909 } 910 911 splx(s); 912 return(error); 913 } 914 915 /* 916 * Lookup: Check the PCI vendor and device, and return a pointer to 917 * The structure if the IDs match against our list. 918 */ 919 920 static const struct sk_product * 921 sk_lookup(const struct pci_attach_args *pa) 922 { 923 const struct sk_product *psk; 924 925 for ( psk = &sk_products[0]; psk->sk_vendor != NULL; psk++ ) { 926 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 927 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 928 return (psk); 929 } 930 return (NULL); 931 } 932 933 /* 934 * Probe for a SysKonnect GEnesis chip. 935 */ 936 937 int 938 skc_probe(struct device *parent, struct cfdata *match, void *aux) 939 { 940 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 941 const struct sk_product *psk; 942 943 if ((psk = sk_lookup(pa))) { 944 return(1); 945 } 946 return(0); 947 } 948 949 /* 950 * Force the GEnesis into reset, then bring it out of reset. 951 */ 952 void sk_reset(struct sk_softc *sc) 953 { 954 DPRINTFN(2, ("sk_reset\n")); 955 956 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 957 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 958 if (sc->sk_type == SK_YUKON) 959 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 960 961 DELAY(1000); 962 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 963 DELAY(2); 964 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 965 if (sc->sk_type == SK_YUKON) 966 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 967 968 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 969 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 970 CSR_READ_2(sc, SK_LINK_CTRL))); 971 972 if (sc->sk_type == SK_GENESIS) { 973 /* Configure packet arbiter */ 974 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 975 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 976 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 977 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 978 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 979 } 980 981 /* Enable RAM interface */ 982 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 983 984 /* 985 * Configure interrupt moderation. The moderation timer 986 * defers interrupts specified in the interrupt moderation 987 * timer mask based on the timeout specified in the interrupt 988 * moderation timer init register. Each bit in the timer 989 * register represents 18.825ns, so to specify a timeout in 990 * microseconds, we have to multiply by 54. 991 */ 992 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 993 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 994 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 995 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 996 } 997 998 int 999 sk_probe(struct device *parent, struct cfdata *match, void *aux) 1000 { 1001 struct skc_attach_args *sa = aux; 1002 1003 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1004 return(0); 1005 1006 return (1); 1007 } 1008 1009 /* 1010 * Each XMAC chip is attached as a separate logical IP interface. 1011 * Single port cards will have only one logical interface of course. 1012 */ 1013 void 1014 sk_attach(struct device *parent, struct device *self, void *aux) 1015 { 1016 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1017 struct sk_softc *sc = (struct sk_softc *)parent; 1018 struct skc_attach_args *sa = aux; 1019 struct sk_txmap_entry *entry; 1020 struct ifnet *ifp; 1021 bus_dma_segment_t seg; 1022 bus_dmamap_t dmamap; 1023 caddr_t kva; 1024 int i, rseg; 1025 1026 sc_if->sk_port = sa->skc_port; 1027 sc_if->sk_softc = sc; 1028 sc->sk_if[sa->skc_port] = sc_if; 1029 1030 if (sa->skc_port == SK_PORT_A) 1031 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1032 if (sa->skc_port == SK_PORT_B) 1033 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1034 1035 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1036 1037 /* 1038 * Get station address for this interface. Note that 1039 * dual port cards actually come with three station 1040 * addresses: one for each port, plus an extra. The 1041 * extra one is used by the SysKonnect driver software 1042 * as a 'virtual' station address for when both ports 1043 * are operating in failover mode. Currently we don't 1044 * use this extra address. 1045 */ 1046 for (i = 0; i < ETHER_ADDR_LEN; i++) 1047 sc_if->sk_enaddr[i] = 1048 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1049 1050 1051 aprint_normal(": Ethernet address %s\n", 1052 ether_sprintf(sc_if->sk_enaddr)); 1053 1054 /* 1055 * Set up RAM buffer addresses. The NIC will have a certain 1056 * amount of SRAM on it, somewhere between 512K and 2MB. We 1057 * need to divide this up a) between the transmitter and 1058 * receiver and b) between the two XMACs, if this is a 1059 * dual port NIC. Our algotithm is to divide up the memory 1060 * evenly so that everyone gets a fair share. 1061 */ 1062 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1063 u_int32_t chunk, val; 1064 1065 chunk = sc->sk_ramsize / 2; 1066 val = sc->sk_rboff / sizeof(u_int64_t); 1067 sc_if->sk_rx_ramstart = val; 1068 val += (chunk / sizeof(u_int64_t)); 1069 sc_if->sk_rx_ramend = val - 1; 1070 sc_if->sk_tx_ramstart = val; 1071 val += (chunk / sizeof(u_int64_t)); 1072 sc_if->sk_tx_ramend = val - 1; 1073 } else { 1074 u_int32_t chunk, val; 1075 1076 chunk = sc->sk_ramsize / 4; 1077 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1078 sizeof(u_int64_t); 1079 sc_if->sk_rx_ramstart = val; 1080 val += (chunk / sizeof(u_int64_t)); 1081 sc_if->sk_rx_ramend = val - 1; 1082 sc_if->sk_tx_ramstart = val; 1083 val += (chunk / sizeof(u_int64_t)); 1084 sc_if->sk_tx_ramend = val - 1; 1085 } 1086 1087 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1088 " tx_ramstart=%#x tx_ramend=%#x\n", 1089 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1090 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1091 1092 /* Read and save PHY type and set PHY address */ 1093 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1094 switch (sc_if->sk_phytype) { 1095 case SK_PHYTYPE_XMAC: 1096 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1097 break; 1098 case SK_PHYTYPE_BCOM: 1099 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1100 break; 1101 case SK_PHYTYPE_MARV_COPPER: 1102 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1103 break; 1104 default: 1105 aprint_error("%s: unsupported PHY type: %d\n", 1106 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1107 return; 1108 } 1109 1110 /* Allocate the descriptor queues. */ 1111 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1112 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1113 aprint_error("%s: can't alloc rx buffers\n", 1114 sc->sk_dev.dv_xname); 1115 goto fail; 1116 } 1117 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1118 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1119 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1120 sc_if->sk_dev.dv_xname, 1121 (u_long) sizeof(struct sk_ring_data)); 1122 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1123 goto fail; 1124 } 1125 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1126 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1127 &sc_if->sk_ring_map)) { 1128 aprint_error("%s: can't create dma map\n", 1129 sc_if->sk_dev.dv_xname); 1130 bus_dmamem_unmap(sc->sc_dmatag, kva, 1131 sizeof(struct sk_ring_data)); 1132 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1133 goto fail; 1134 } 1135 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1136 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1137 aprint_error("%s: can't load dma map\n", 1138 sc_if->sk_dev.dv_xname); 1139 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1140 bus_dmamem_unmap(sc->sc_dmatag, kva, 1141 sizeof(struct sk_ring_data)); 1142 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1143 goto fail; 1144 } 1145 1146 for (i = 0; i < SK_RX_RING_CNT; i++) 1147 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1148 1149 SLIST_INIT(&sc_if->sk_txmap_listhead); 1150 for (i = 0; i < SK_TX_RING_CNT; i++) { 1151 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1152 1153 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, SK_NTXSEG, 1154 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap)) { 1155 aprint_error("%s: Can't create TX dmamap\n", 1156 sc_if->sk_dev.dv_xname); 1157 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1158 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1159 bus_dmamem_unmap(sc->sc_dmatag, kva, 1160 sizeof(struct sk_ring_data)); 1161 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1162 goto fail; 1163 } 1164 1165 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1166 if (!entry) { 1167 aprint_error("%s: Can't alloc txmap entry\n", 1168 sc_if->sk_dev.dv_xname); 1169 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1170 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1171 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1172 bus_dmamem_unmap(sc->sc_dmatag, kva, 1173 sizeof(struct sk_ring_data)); 1174 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1175 goto fail; 1176 } 1177 entry->dmamap = dmamap; 1178 SLIST_INSERT_HEAD(&sc_if->sk_txmap_listhead, entry, link); 1179 } 1180 1181 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1182 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1183 1184 ifp = &sc_if->sk_ethercom.ec_if; 1185 ifp->if_softc = sc_if; 1186 ifp->if_mtu = ETHERMTU; 1187 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1188 ifp->if_ioctl = sk_ioctl; 1189 ifp->if_start = sk_start; 1190 ifp->if_stop = sk_stop; 1191 ifp->if_init = sk_init; 1192 ifp->if_watchdog = sk_watchdog; 1193 ifp->if_baudrate = 1000000000; 1194 ifp->if_capabilities |= ETHERCAP_VLAN_MTU; 1195 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1196 IFQ_SET_READY(&ifp->if_snd); 1197 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1198 1199 /* 1200 * Do miibus setup. 1201 */ 1202 switch (sc->sk_type) { 1203 case SK_GENESIS: 1204 sk_init_xmac(sc_if); 1205 break; 1206 case SK_YUKON: 1207 sk_init_yukon(sc_if); 1208 break; 1209 default: 1210 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1211 sc->sk_type); 1212 } 1213 1214 DPRINTFN(2, ("sk_attach: 1\n")); 1215 1216 sc_if->sk_mii.mii_ifp = ifp; 1217 switch (sc->sk_type) { 1218 case SK_GENESIS: 1219 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1220 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1221 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1222 break; 1223 case SK_YUKON: 1224 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1225 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1226 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1227 break; 1228 } 1229 1230 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1231 sk_ifmedia_upd, sk_ifmedia_sts); 1232 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1233 MII_OFFSET_ANY, 0); 1234 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1235 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1236 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1237 0, NULL); 1238 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1239 } 1240 else 1241 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1242 1243 callout_init(&sc_if->sk_tick_ch); 1244 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1245 1246 DPRINTFN(2, ("sk_attach: 1\n")); 1247 1248 /* 1249 * Call MI attach routines. 1250 */ 1251 if_attach(ifp); 1252 1253 ether_ifattach(ifp, sc_if->sk_enaddr); 1254 1255 #if NRND > 0 1256 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1257 RND_TYPE_NET, 0); 1258 #endif 1259 1260 DPRINTFN(2, ("sk_attach: end\n")); 1261 1262 return; 1263 1264 fail: 1265 sc->sk_if[sa->skc_port] = NULL; 1266 } 1267 1268 int 1269 skcprint(void *aux, const char *pnp) 1270 { 1271 struct skc_attach_args *sa = aux; 1272 1273 if (pnp) 1274 aprint_normal("sk port %c at %s", 1275 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1276 else 1277 aprint_normal(" port %c", 1278 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1279 return (UNCONF); 1280 } 1281 1282 /* 1283 * Attach the interface. Allocate softc structures, do ifmedia 1284 * setup and ethernet/BPF attach. 1285 */ 1286 void 1287 skc_attach(struct device *parent, struct device *self, void *aux) 1288 { 1289 struct sk_softc *sc = (struct sk_softc *)self; 1290 struct pci_attach_args *pa = aux; 1291 struct skc_attach_args skca; 1292 pci_chipset_tag_t pc = pa->pa_pc; 1293 pcireg_t memtype; 1294 pci_intr_handle_t ih; 1295 const char *intrstr = NULL; 1296 bus_addr_t iobase; 1297 bus_size_t iosize; 1298 int s; 1299 u_int32_t command; 1300 1301 DPRINTFN(2, ("begin skc_attach\n")); 1302 1303 s = splnet(); 1304 1305 /* 1306 * Handle power management nonsense. 1307 */ 1308 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1309 1310 if (command == 0x01) { 1311 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1312 if (command & SK_PSTATE_MASK) { 1313 u_int32_t iobase, membase, irq; 1314 1315 /* Save important PCI config data. */ 1316 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1317 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1318 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1319 1320 /* Reset the power state. */ 1321 aprint_normal("%s chip is in D%d power mode " 1322 "-- setting to D0\n", sc->sk_dev.dv_xname, 1323 command & SK_PSTATE_MASK); 1324 command &= 0xFFFFFFFC; 1325 pci_conf_write(pc, pa->pa_tag, 1326 SK_PCI_PWRMGMTCTRL, command); 1327 1328 /* Restore PCI config data. */ 1329 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1330 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1331 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1332 } 1333 } 1334 1335 /* 1336 * Map control/status registers. 1337 */ 1338 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1339 command |= PCI_COMMAND_IO_ENABLE | 1340 PCI_COMMAND_MEM_ENABLE | 1341 PCI_COMMAND_MASTER_ENABLE; 1342 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1343 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1344 1345 switch (PCI_PRODUCT(pa->pa_id)) { 1346 case PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE: 1347 sc->sk_type = SK_GENESIS; 1348 break; 1349 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1350 case PCI_PRODUCT_3COM_3C940: 1351 sc->sk_type = SK_YUKON; 1352 break; 1353 default: 1354 aprint_error(": unknown device!\n"); 1355 goto fail; 1356 } 1357 1358 #ifdef SK_USEIOSPACE 1359 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1360 aprint_error(": failed to enable I/O ports!\n"); 1361 goto fail; 1362 } 1363 /* 1364 * Map control/status registers. 1365 */ 1366 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1367 &iobase, &iosize)) { 1368 aprint_error(": can't find i/o space\n"); 1369 goto fail; 1370 } 1371 #else 1372 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1373 aprint_error(": failed to enable memory mapping!\n"); 1374 goto fail; 1375 } 1376 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1377 switch (memtype) { 1378 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1379 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1380 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1381 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1382 &iobase, &iosize) == 0) 1383 break; 1384 default: 1385 aprint_error("%s: can't find mem space\n", 1386 sc->sk_dev.dv_xname); 1387 return; 1388 } 1389 1390 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1391 #endif 1392 sc->sc_dmatag = pa->pa_dmat; 1393 1394 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1395 1396 /* Allocate interrupt */ 1397 if (pci_intr_map(pa, &ih)) { 1398 aprint_error(": couldn't map interrupt\n"); 1399 goto fail; 1400 } 1401 1402 intrstr = pci_intr_string(pc, ih); 1403 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1404 if (sc->sk_intrhand == NULL) { 1405 aprint_error(": couldn't establish interrupt"); 1406 if (intrstr != NULL) 1407 aprint_normal(" at %s", intrstr); 1408 goto fail; 1409 } 1410 aprint_normal(": %s\n", intrstr); 1411 1412 /* Reset the adapter. */ 1413 sk_reset(sc); 1414 1415 /* Read and save vital product data from EEPROM. */ 1416 sk_vpd_read(sc); 1417 1418 if (sc->sk_type == SK_GENESIS) { 1419 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1420 /* Read and save RAM size and RAMbuffer offset */ 1421 switch(val) { 1422 case SK_RAMSIZE_512K_64: 1423 sc->sk_ramsize = 0x80000; 1424 sc->sk_rboff = SK_RBOFF_0; 1425 break; 1426 case SK_RAMSIZE_1024K_64: 1427 sc->sk_ramsize = 0x100000; 1428 sc->sk_rboff = SK_RBOFF_80000; 1429 break; 1430 case SK_RAMSIZE_1024K_128: 1431 sc->sk_ramsize = 0x100000; 1432 sc->sk_rboff = SK_RBOFF_0; 1433 break; 1434 case SK_RAMSIZE_2048K_128: 1435 sc->sk_ramsize = 0x200000; 1436 sc->sk_rboff = SK_RBOFF_0; 1437 break; 1438 default: 1439 aprint_error("%s: unknown ram size: %d\n", 1440 sc->sk_dev.dv_xname, val); 1441 goto fail; 1442 break; 1443 } 1444 1445 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1446 sc->sk_ramsize, sc->sk_ramsize / 1024, 1447 sc->sk_rboff)); 1448 } else { 1449 sc->sk_ramsize = 0x20000; 1450 sc->sk_rboff = SK_RBOFF_0; 1451 1452 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1453 sc->sk_ramsize / 1024, sc->sk_ramsize, 1454 sc->sk_rboff)); 1455 } 1456 1457 /* Read and save physical media type */ 1458 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1459 case SK_PMD_1000BASESX: 1460 sc->sk_pmd = IFM_1000_SX; 1461 break; 1462 case SK_PMD_1000BASELX: 1463 sc->sk_pmd = IFM_1000_LX; 1464 break; 1465 case SK_PMD_1000BASECX: 1466 sc->sk_pmd = IFM_1000_CX; 1467 break; 1468 case SK_PMD_1000BASETX: 1469 sc->sk_pmd = IFM_1000_T; 1470 break; 1471 default: 1472 aprint_error("%s: unknown media type: 0x%x\n", 1473 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1474 goto fail; 1475 } 1476 1477 /* Announce the product name. */ 1478 aprint_normal("%s: %s\n", sc->sk_dev.dv_xname, sc->sk_vpd_prodname); 1479 1480 skca.skc_port = SK_PORT_A; 1481 (void)config_found(&sc->sk_dev, &skca, skcprint); 1482 1483 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1484 skca.skc_port = SK_PORT_B; 1485 (void)config_found(&sc->sk_dev, &skca, skcprint); 1486 } 1487 1488 /* Turn on the 'driver is loaded' LED. */ 1489 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1490 1491 fail: 1492 splx(s); 1493 } 1494 1495 int 1496 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1497 { 1498 struct sk_softc *sc = sc_if->sk_softc; 1499 struct sk_tx_desc *f = NULL; 1500 u_int32_t frag, cur, cnt = 0; 1501 int i; 1502 struct sk_txmap_entry *entry; 1503 bus_dmamap_t txmap; 1504 1505 DPRINTFN(3, ("sk_encap\n")); 1506 1507 entry = SLIST_FIRST(&sc_if->sk_txmap_listhead); 1508 if (entry == NULL) { 1509 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1510 return ENOBUFS; 1511 } 1512 txmap = entry->dmamap; 1513 1514 cur = frag = *txidx; 1515 1516 #ifdef SK_DEBUG 1517 if (skdebug >= 3) 1518 sk_dump_mbuf(m_head); 1519 #endif 1520 1521 /* 1522 * Start packing the mbufs in this chain into 1523 * the fragment pointers. Stop when we run out 1524 * of fragments or hit the end of the mbuf chain. 1525 */ 1526 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1527 BUS_DMA_NOWAIT)) { 1528 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1529 return(ENOBUFS); 1530 } 1531 1532 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1533 1534 /* Sync the DMA map. */ 1535 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1536 BUS_DMASYNC_PREWRITE); 1537 1538 for (i = 0; i < txmap->dm_nsegs; i++) { 1539 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1540 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1541 return(ENOBUFS); 1542 } 1543 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1544 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1545 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1546 if (cnt == 0) 1547 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1548 else 1549 f->sk_ctl |= SK_TXCTL_OWN; 1550 1551 cur = frag; 1552 SK_INC(frag, SK_TX_RING_CNT); 1553 cnt++; 1554 } 1555 1556 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1557 SLIST_REMOVE_HEAD(&sc_if->sk_txmap_listhead, link); 1558 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1559 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1560 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1561 1562 /* Sync descriptors before handing to chip */ 1563 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1564 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1565 1566 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1567 1568 /* Sync first descriptor to hand it off */ 1569 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1570 1571 sc_if->sk_cdata.sk_tx_cnt += cnt; 1572 1573 #ifdef SK_DEBUG 1574 if (skdebug >= 3) { 1575 struct sk_tx_desc *desc; 1576 u_int32_t idx; 1577 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1578 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1579 sk_dump_txdesc(desc, idx); 1580 } 1581 } 1582 #endif 1583 1584 *txidx = frag; 1585 1586 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1587 1588 return(0); 1589 } 1590 1591 void 1592 sk_start(struct ifnet *ifp) 1593 { 1594 struct sk_if_softc *sc_if = ifp->if_softc; 1595 struct sk_softc *sc = sc_if->sk_softc; 1596 struct mbuf *m_head = NULL; 1597 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1598 int pkts = 0; 1599 1600 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1601 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1602 1603 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1604 1605 IFQ_POLL(&ifp->if_snd, m_head); 1606 if (m_head == NULL) 1607 break; 1608 1609 /* 1610 * Pack the data into the transmit ring. If we 1611 * don't have room, set the OACTIVE flag and wait 1612 * for the NIC to drain the ring. 1613 */ 1614 if (sk_encap(sc_if, m_head, &idx)) { 1615 ifp->if_flags |= IFF_OACTIVE; 1616 break; 1617 } 1618 1619 /* now we are committed to transmit the packet */ 1620 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1621 pkts++; 1622 1623 /* 1624 * If there's a BPF listener, bounce a copy of this frame 1625 * to him. 1626 */ 1627 #if NBPFILTER > 0 1628 if (ifp->if_bpf) 1629 bpf_mtap(ifp->if_bpf, m_head); 1630 #endif 1631 } 1632 if (pkts == 0) 1633 return; 1634 1635 /* Transmit */ 1636 sc_if->sk_cdata.sk_tx_prod = idx; 1637 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1638 1639 /* Set a timeout in case the chip goes out to lunch. */ 1640 ifp->if_timer = 5; 1641 } 1642 1643 1644 void 1645 sk_watchdog(struct ifnet *ifp) 1646 { 1647 struct sk_if_softc *sc_if = ifp->if_softc; 1648 1649 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1650 (void) sk_init(ifp); 1651 } 1652 1653 void 1654 sk_shutdown(void * v) 1655 { 1656 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1657 struct sk_softc *sc = sc_if->sk_softc; 1658 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1659 1660 DPRINTFN(2, ("sk_shutdown\n")); 1661 sk_stop(ifp,1); 1662 1663 /* Turn off the 'driver is loaded' LED. */ 1664 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1665 1666 /* 1667 * Reset the GEnesis controller. Doing this should also 1668 * assert the resets on the attached XMAC(s). 1669 */ 1670 sk_reset(sc); 1671 } 1672 1673 void 1674 sk_rxeof(struct sk_if_softc *sc_if) 1675 { 1676 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1677 struct mbuf *m; 1678 struct sk_chain *cur_rx; 1679 struct sk_rx_desc *cur_desc; 1680 int i, cur, total_len = 0; 1681 u_int32_t rxstat; 1682 bus_dmamap_t dmamap; 1683 1684 i = sc_if->sk_cdata.sk_rx_prod; 1685 1686 DPRINTFN(3, ("sk_rxeof %d\n", i)); 1687 1688 for (;;) { 1689 cur = i; 1690 1691 /* Sync the descriptor */ 1692 SK_CDRXSYNC(sc_if, cur, 1693 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1694 1695 if (sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl & SK_RXCTL_OWN) { 1696 /* Invalidate the descriptor -- it's not ready yet */ 1697 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 1698 sc_if->sk_cdata.sk_rx_prod = i; 1699 break; 1700 } 1701 1702 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1703 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1704 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1705 1706 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1707 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1708 1709 rxstat = cur_desc->sk_xmac_rxstat; 1710 m = cur_rx->sk_mbuf; 1711 cur_rx->sk_mbuf = NULL; 1712 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1713 1714 sc_if->sk_cdata.sk_rx_map[cur] = 0; 1715 1716 SK_INC(i, SK_RX_RING_CNT); 1717 1718 if (rxstat & XM_RXSTAT_ERRFRAME) { 1719 ifp->if_ierrors++; 1720 sk_newbuf(sc_if, cur, m, dmamap); 1721 continue; 1722 } 1723 1724 /* 1725 * Try to allocate a new jumbo buffer. If that 1726 * fails, copy the packet to mbufs and put the 1727 * jumbo buffer back in the ring so it can be 1728 * re-used. If allocating mbufs fails, then we 1729 * have to drop the packet. 1730 */ 1731 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1732 struct mbuf *m0; 1733 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1734 total_len + ETHER_ALIGN, 0, ifp, NULL); 1735 sk_newbuf(sc_if, cur, m, dmamap); 1736 if (m0 == NULL) { 1737 printf("%s: no receive buffers " 1738 "available -- packet dropped!\n", 1739 sc_if->sk_dev.dv_xname); 1740 ifp->if_ierrors++; 1741 continue; 1742 } 1743 m_adj(m0, ETHER_ALIGN); 1744 m = m0; 1745 } else { 1746 m->m_pkthdr.rcvif = ifp; 1747 m->m_pkthdr.len = m->m_len = total_len; 1748 } 1749 1750 ifp->if_ipackets++; 1751 1752 #if NBPFILTER > 0 1753 if (ifp->if_bpf) 1754 bpf_mtap(ifp->if_bpf, m); 1755 #endif 1756 /* pass it on. */ 1757 (*ifp->if_input)(ifp, m); 1758 } 1759 } 1760 1761 void 1762 sk_txeof(struct sk_if_softc *sc_if) 1763 { 1764 struct sk_softc *sc = sc_if->sk_softc; 1765 struct sk_tx_desc *cur_tx = NULL; 1766 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1767 u_int32_t idx, nsegs; 1768 struct sk_txmap_entry *entry; 1769 1770 DPRINTFN(3, ("sk_txeof\n")); 1771 1772 /* 1773 * Go through our tx ring and free mbufs for those 1774 * frames that have been sent. 1775 */ 1776 idx = sc_if->sk_cdata.sk_tx_cons; 1777 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1778 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1779 if (!entry) 1780 break; 1781 1782 nsegs = entry->dmamap->dm_nsegs; 1783 SK_CDTXSYNC(sc_if, idx, nsegs, 1784 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1785 1786 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1787 #ifdef SK_DEBUG 1788 if (skdebug >= 3) 1789 sk_dump_txdesc(cur_tx, idx); 1790 #endif 1791 if (cur_tx->sk_ctl & SK_TXCTL_OWN) { 1792 SK_CDTXSYNC(sc_if, idx, nsegs, BUS_DMASYNC_PREREAD); 1793 break; 1794 } 1795 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1796 ifp->if_opackets++; 1797 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1798 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1799 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1800 1801 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1802 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1803 1804 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1805 SLIST_INSERT_HEAD(&sc_if->sk_txmap_listhead, entry, 1806 link); 1807 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1808 } 1809 sc_if->sk_cdata.sk_tx_cnt--; 1810 SK_INC(idx, SK_TX_RING_CNT); 1811 ifp->if_timer = 0; 1812 } 1813 1814 sc_if->sk_cdata.sk_tx_cons = idx; 1815 1816 if (cur_tx != NULL) 1817 ifp->if_flags &= ~IFF_OACTIVE; 1818 } 1819 1820 void 1821 sk_tick(void *xsc_if) 1822 { 1823 struct sk_if_softc *sc_if = xsc_if; 1824 struct mii_data *mii = &sc_if->sk_mii; 1825 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1826 int i; 1827 1828 DPRINTFN(3, ("sk_tick\n")); 1829 1830 if (!(ifp->if_flags & IFF_UP)) 1831 return; 1832 1833 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1834 sk_intr_bcom(sc_if); 1835 return; 1836 } 1837 1838 /* 1839 * According to SysKonnect, the correct way to verify that 1840 * the link has come back up is to poll bit 0 of the GPIO 1841 * register three times. This pin has the signal from the 1842 * link sync pin connected to it; if we read the same link 1843 * state 3 times in a row, we know the link is up. 1844 */ 1845 for (i = 0; i < 3; i++) { 1846 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1847 break; 1848 } 1849 1850 if (i != 3) { 1851 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1852 return; 1853 } 1854 1855 /* Turn the GP0 interrupt back on. */ 1856 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1857 SK_XM_READ_2(sc_if, XM_ISR); 1858 mii_tick(mii); 1859 mii_pollstat(mii); 1860 callout_stop(&sc_if->sk_tick_ch); 1861 } 1862 1863 void 1864 sk_intr_bcom(struct sk_if_softc *sc_if) 1865 { 1866 struct mii_data *mii = &sc_if->sk_mii; 1867 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1868 int status; 1869 1870 1871 DPRINTFN(3, ("sk_intr_bcom\n")); 1872 1873 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1874 1875 /* 1876 * Read the PHY interrupt register to make sure 1877 * we clear any pending interrupts. 1878 */ 1879 status = sk_xmac_miibus_readreg((struct device *)sc_if, 1880 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1881 1882 if (!(ifp->if_flags & IFF_RUNNING)) { 1883 sk_init_xmac(sc_if); 1884 return; 1885 } 1886 1887 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1888 int lstat; 1889 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 1890 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 1891 1892 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1893 mii_mediachg(mii); 1894 /* Turn off the link LED. */ 1895 SK_IF_WRITE_1(sc_if, 0, 1896 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1897 sc_if->sk_link = 0; 1898 } else if (status & BRGPHY_ISR_LNK_CHG) { 1899 sk_xmac_miibus_writereg((struct device *)sc_if, 1900 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 1901 mii_tick(mii); 1902 sc_if->sk_link = 1; 1903 /* Turn on the link LED. */ 1904 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1905 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1906 SK_LINKLED_BLINK_OFF); 1907 mii_pollstat(mii); 1908 } else { 1909 mii_tick(mii); 1910 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 1911 } 1912 } 1913 1914 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1915 } 1916 1917 void 1918 sk_intr_xmac(struct sk_if_softc *sc_if) 1919 { 1920 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 1921 1922 DPRINTFN(3, ("sk_intr_xmac\n")); 1923 1924 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1925 if (status & XM_ISR_GP0_SET) { 1926 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1927 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1928 } 1929 1930 if (status & XM_ISR_AUTONEG_DONE) { 1931 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1932 } 1933 } 1934 1935 if (status & XM_IMR_TX_UNDERRUN) 1936 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1937 1938 if (status & XM_IMR_RX_OVERRUN) 1939 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1940 } 1941 1942 void 1943 sk_intr_yukon(sc_if) 1944 struct sk_if_softc *sc_if; 1945 { 1946 int status; 1947 1948 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1949 1950 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 1951 } 1952 1953 int 1954 sk_intr(void *xsc) 1955 { 1956 struct sk_softc *sc = xsc; 1957 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1958 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1959 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1960 u_int32_t status; 1961 int claimed = 0; 1962 1963 if (sc_if0 != NULL) 1964 ifp0 = &sc_if0->sk_ethercom.ec_if; 1965 if (sc_if1 != NULL) 1966 ifp1 = &sc_if1->sk_ethercom.ec_if; 1967 1968 for (;;) { 1969 status = CSR_READ_4(sc, SK_ISSR); 1970 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 1971 1972 if (!(status & sc->sk_intrmask)) 1973 break; 1974 1975 claimed = 1; 1976 1977 /* Handle receive interrupts first. */ 1978 if (status & SK_ISR_RX1_EOF) { 1979 sk_rxeof(sc_if0); 1980 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1981 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1982 } 1983 if (status & SK_ISR_RX2_EOF) { 1984 sk_rxeof(sc_if1); 1985 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1986 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1987 } 1988 1989 /* Then transmit interrupts. */ 1990 if (status & SK_ISR_TX1_S_EOF) { 1991 sk_txeof(sc_if0); 1992 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1993 SK_TXBMU_CLR_IRQ_EOF); 1994 } 1995 if (status & SK_ISR_TX2_S_EOF) { 1996 sk_txeof(sc_if1); 1997 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1998 SK_TXBMU_CLR_IRQ_EOF); 1999 } 2000 2001 /* Then MAC interrupts. */ 2002 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 2003 if (sc->sk_type == SK_GENESIS) 2004 sk_intr_xmac(sc_if0); 2005 else 2006 sk_intr_yukon(sc_if0); 2007 } 2008 2009 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 2010 if (sc->sk_type == SK_GENESIS) 2011 sk_intr_xmac(sc_if1); 2012 else 2013 sk_intr_yukon(sc_if1); 2014 2015 } 2016 2017 if (status & SK_ISR_EXTERNAL_REG) { 2018 if (ifp0 != NULL && 2019 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2020 sk_intr_bcom(sc_if0); 2021 2022 if (ifp1 != NULL && 2023 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2024 sk_intr_bcom(sc_if1); 2025 } 2026 } 2027 2028 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2029 2030 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2031 sk_start(ifp0); 2032 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2033 sk_start(ifp1); 2034 2035 return (claimed); 2036 } 2037 2038 void 2039 sk_init_xmac(struct sk_if_softc *sc_if) 2040 { 2041 struct sk_softc *sc = sc_if->sk_softc; 2042 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2043 static const struct sk_bcom_hack bhack[] = { 2044 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2045 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2046 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2047 { 0, 0 } }; 2048 2049 DPRINTFN(1, ("sk_init_xmac\n")); 2050 2051 /* Unreset the XMAC. */ 2052 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2053 DELAY(1000); 2054 2055 /* Reset the XMAC's internal state. */ 2056 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2057 2058 /* Save the XMAC II revision */ 2059 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2060 2061 /* 2062 * Perform additional initialization for external PHYs, 2063 * namely for the 1000baseTX cards that use the XMAC's 2064 * GMII mode. 2065 */ 2066 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2067 int i = 0; 2068 u_int32_t val; 2069 2070 /* Take PHY out of reset. */ 2071 val = sk_win_read_4(sc, SK_GPIO); 2072 if (sc_if->sk_port == SK_PORT_A) 2073 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2074 else 2075 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2076 sk_win_write_4(sc, SK_GPIO, val); 2077 2078 /* Enable GMII mode on the XMAC. */ 2079 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2080 2081 sk_xmac_miibus_writereg((struct device *)sc_if, 2082 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2083 DELAY(10000); 2084 sk_xmac_miibus_writereg((struct device *)sc_if, 2085 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2086 2087 /* 2088 * Early versions of the BCM5400 apparently have 2089 * a bug that requires them to have their reserved 2090 * registers initialized to some magic values. I don't 2091 * know what the numbers do, I'm just the messenger. 2092 */ 2093 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2094 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2095 while(bhack[i].reg) { 2096 sk_xmac_miibus_writereg((struct device *)sc_if, 2097 SK_PHYADDR_BCOM, bhack[i].reg, 2098 bhack[i].val); 2099 i++; 2100 } 2101 } 2102 } 2103 2104 /* Set station address */ 2105 SK_XM_WRITE_2(sc_if, XM_PAR0, 2106 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2107 SK_XM_WRITE_2(sc_if, XM_PAR1, 2108 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2109 SK_XM_WRITE_2(sc_if, XM_PAR2, 2110 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2111 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2112 2113 if (ifp->if_flags & IFF_PROMISC) { 2114 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2115 } else { 2116 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2117 } 2118 2119 if (ifp->if_flags & IFF_BROADCAST) { 2120 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2121 } else { 2122 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2123 } 2124 2125 /* We don't need the FCS appended to the packet. */ 2126 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2127 2128 /* We want short frames padded to 60 bytes. */ 2129 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2130 2131 /* 2132 * Enable the reception of all error frames. This is is 2133 * a necessary evil due to the design of the XMAC. The 2134 * XMAC's receive FIFO is only 8K in size, however jumbo 2135 * frames can be up to 9000 bytes in length. When bad 2136 * frame filtering is enabled, the XMAC's RX FIFO operates 2137 * in 'store and forward' mode. For this to work, the 2138 * entire frame has to fit into the FIFO, but that means 2139 * that jumbo frames larger than 8192 bytes will be 2140 * truncated. Disabling all bad frame filtering causes 2141 * the RX FIFO to operate in streaming mode, in which 2142 * case the XMAC will start transfering frames out of the 2143 * RX FIFO as soon as the FIFO threshold is reached. 2144 */ 2145 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2146 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2147 XM_MODE_RX_INRANGELEN); 2148 2149 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2150 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2151 else 2152 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2153 2154 /* 2155 * Bump up the transmit threshold. This helps hold off transmit 2156 * underruns when we're blasting traffic from both ports at once. 2157 */ 2158 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2159 2160 /* Set multicast filter */ 2161 sk_setmulti(sc_if); 2162 2163 /* Clear and enable interrupts */ 2164 SK_XM_READ_2(sc_if, XM_ISR); 2165 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2166 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2167 else 2168 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2169 2170 /* Configure MAC arbiter */ 2171 switch(sc_if->sk_xmac_rev) { 2172 case XM_XMAC_REV_B2: 2173 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2174 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2175 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2176 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2177 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2178 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2179 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2180 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2181 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2182 break; 2183 case XM_XMAC_REV_C1: 2184 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2185 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2186 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2187 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2188 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2189 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2190 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2191 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2192 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2193 break; 2194 default: 2195 break; 2196 } 2197 sk_win_write_2(sc, SK_MACARB_CTL, 2198 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2199 2200 sc_if->sk_link = 1; 2201 } 2202 2203 void sk_init_yukon(sc_if) 2204 struct sk_if_softc *sc_if; 2205 { 2206 u_int32_t /*mac, */phy; 2207 u_int16_t reg; 2208 int i; 2209 2210 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2211 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2212 2213 /* GMAC and GPHY Reset */ 2214 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2215 2216 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2217 2218 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2219 DELAY(1000); 2220 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2221 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2222 DELAY(1000); 2223 2224 2225 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2226 2227 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2228 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2229 2230 switch(sc_if->sk_softc->sk_pmd) { 2231 case IFM_1000_SX: 2232 case IFM_1000_LX: 2233 phy |= SK_GPHY_FIBER; 2234 break; 2235 2236 case IFM_1000_CX: 2237 case IFM_1000_T: 2238 phy |= SK_GPHY_COPPER; 2239 break; 2240 } 2241 2242 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2243 2244 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2245 DELAY(1000); 2246 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2247 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2248 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2249 2250 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2251 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2252 2253 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2254 2255 /* unused read of the interrupt source register */ 2256 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2257 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2258 2259 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2260 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2261 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2262 2263 /* MIB Counter Clear Mode set */ 2264 reg |= YU_PAR_MIB_CLR; 2265 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2266 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2267 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2268 2269 /* MIB Counter Clear Mode clear */ 2270 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2271 reg &= ~YU_PAR_MIB_CLR; 2272 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2273 2274 /* receive control reg */ 2275 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2276 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2277 YU_RCR_CRCR); 2278 2279 /* transmit parameter register */ 2280 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2281 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2282 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2283 2284 /* serial mode register */ 2285 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2286 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2287 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2288 2289 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2290 /* Setup Yukon's address */ 2291 for (i = 0; i < 3; i++) { 2292 /* Write Source Address 1 (unicast filter) */ 2293 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2294 sc_if->sk_enaddr[i * 2] | 2295 sc_if->sk_enaddr[i * 2 + 1] << 8); 2296 } 2297 2298 for (i = 0; i < 3; i++) { 2299 reg = sk_win_read_2(sc_if->sk_softc, 2300 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2301 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2302 } 2303 2304 /* clear all Multicast filter hash registers */ 2305 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2306 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 2307 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 2308 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 2309 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 2310 2311 /* enable interrupt mask for counter overflows */ 2312 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2313 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2314 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2315 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2316 2317 /* Configure RX MAC FIFO */ 2318 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2319 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2320 2321 /* Configure TX MAC FIFO */ 2322 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2323 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2324 2325 DPRINTFN(6, ("sk_init_yukon: end\n")); 2326 } 2327 2328 /* 2329 * Note that to properly initialize any part of the GEnesis chip, 2330 * you first have to take it out of reset mode. 2331 */ 2332 int 2333 sk_init(struct ifnet *ifp) 2334 { 2335 struct sk_if_softc *sc_if = ifp->if_softc; 2336 struct sk_softc *sc = sc_if->sk_softc; 2337 struct mii_data *mii = &sc_if->sk_mii; 2338 int s; 2339 2340 DPRINTFN(1, ("sk_init\n")); 2341 2342 s = splnet(); 2343 2344 /* Cancel pending I/O and free all RX/TX buffers. */ 2345 sk_stop(ifp,0); 2346 2347 if (sc->sk_type == SK_GENESIS) { 2348 /* Configure LINK_SYNC LED */ 2349 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2350 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2351 SK_LINKLED_LINKSYNC_ON); 2352 2353 /* Configure RX LED */ 2354 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2355 SK_RXLEDCTL_COUNTER_START); 2356 2357 /* Configure TX LED */ 2358 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2359 SK_TXLEDCTL_COUNTER_START); 2360 } 2361 2362 /* Configure I2C registers */ 2363 2364 /* Configure XMAC(s) */ 2365 switch (sc->sk_type) { 2366 case SK_GENESIS: 2367 sk_init_xmac(sc_if); 2368 break; 2369 case SK_YUKON: 2370 sk_init_yukon(sc_if); 2371 break; 2372 } 2373 mii_mediachg(mii); 2374 2375 if (sc->sk_type == SK_GENESIS) { 2376 /* Configure MAC FIFOs */ 2377 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2378 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2379 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2380 2381 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2382 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2383 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2384 } 2385 2386 /* Configure transmit arbiter(s) */ 2387 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2388 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2389 2390 /* Configure RAMbuffers */ 2391 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2392 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2393 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2394 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2395 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2396 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2397 2398 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2399 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2400 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2401 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2402 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2403 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2404 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2405 2406 /* Configure BMUs */ 2407 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2408 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2409 SK_RX_RING_ADDR(sc_if, 0)); 2410 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2411 2412 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2413 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2414 SK_TX_RING_ADDR(sc_if, 0)); 2415 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2416 2417 /* Init descriptors */ 2418 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2419 printf("%s: initialization failed: no " 2420 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2421 sk_stop(ifp,0); 2422 splx(s); 2423 return(ENOBUFS); 2424 } 2425 2426 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2427 printf("%s: initialization failed: no " 2428 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2429 sk_stop(ifp,0); 2430 splx(s); 2431 return(ENOBUFS); 2432 } 2433 2434 /* Configure interrupt handling */ 2435 CSR_READ_4(sc, SK_ISSR); 2436 if (sc_if->sk_port == SK_PORT_A) 2437 sc->sk_intrmask |= SK_INTRS1; 2438 else 2439 sc->sk_intrmask |= SK_INTRS2; 2440 2441 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2442 2443 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2444 2445 /* Start BMUs. */ 2446 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2447 2448 if (sc->sk_type == SK_GENESIS) { 2449 /* Enable XMACs TX and RX state machines */ 2450 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2451 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2452 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2453 } 2454 2455 if (sc->sk_type == SK_YUKON) { 2456 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2457 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2458 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2459 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2460 } 2461 2462 2463 ifp->if_flags |= IFF_RUNNING; 2464 ifp->if_flags &= ~IFF_OACTIVE; 2465 2466 splx(s); 2467 return(0); 2468 } 2469 2470 void 2471 sk_stop(struct ifnet *ifp, int disable) 2472 { 2473 struct sk_if_softc *sc_if = ifp->if_softc; 2474 struct sk_softc *sc = sc_if->sk_softc; 2475 int i; 2476 2477 DPRINTFN(1, ("sk_stop\n")); 2478 2479 callout_stop(&sc_if->sk_tick_ch); 2480 2481 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2482 u_int32_t val; 2483 2484 /* Put PHY back into reset. */ 2485 val = sk_win_read_4(sc, SK_GPIO); 2486 if (sc_if->sk_port == SK_PORT_A) { 2487 val |= SK_GPIO_DIR0; 2488 val &= ~SK_GPIO_DAT0; 2489 } else { 2490 val |= SK_GPIO_DIR2; 2491 val &= ~SK_GPIO_DAT2; 2492 } 2493 sk_win_write_4(sc, SK_GPIO, val); 2494 } 2495 2496 /* Turn off various components of this interface. */ 2497 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2498 switch (sc->sk_type) { 2499 case SK_GENESIS: 2500 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2501 SK_TXMACCTL_XMAC_RESET); 2502 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2503 break; 2504 case SK_YUKON: 2505 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2506 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2507 break; 2508 } 2509 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2510 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2511 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2512 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2513 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2514 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2515 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2516 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2517 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2518 2519 /* Disable interrupts */ 2520 if (sc_if->sk_port == SK_PORT_A) 2521 sc->sk_intrmask &= ~SK_INTRS1; 2522 else 2523 sc->sk_intrmask &= ~SK_INTRS2; 2524 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2525 2526 SK_XM_READ_2(sc_if, XM_ISR); 2527 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2528 2529 /* Free RX and TX mbufs still in the queues. */ 2530 for (i = 0; i < SK_RX_RING_CNT; i++) { 2531 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2532 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2533 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2534 } 2535 } 2536 2537 for (i = 0; i < SK_TX_RING_CNT; i++) { 2538 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2539 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2540 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2541 } 2542 } 2543 2544 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2545 } 2546 2547 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2548 2549 /* 2550 struct cfdriver skc_cd = { 2551 0, "skc", DV_DULL 2552 }; 2553 */ 2554 2555 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2556 2557 /* 2558 struct cfdriver sk_cd = { 2559 0, "sk", DV_IFNET 2560 }; 2561 */ 2562 2563 #ifdef SK_DEBUG 2564 void 2565 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2566 { 2567 #define DESC_PRINT(X) \ 2568 if (desc->X) \ 2569 printf("txdesc[%d]." #X "=%#x\n", \ 2570 idx, desc->X); 2571 2572 DESC_PRINT(sk_ctl); 2573 DESC_PRINT(sk_next); 2574 DESC_PRINT(sk_data_lo); 2575 DESC_PRINT(sk_data_hi); 2576 DESC_PRINT(sk_xmac_txstat); 2577 DESC_PRINT(sk_rsvd0); 2578 DESC_PRINT(sk_csum_startval); 2579 DESC_PRINT(sk_csum_startpos); 2580 DESC_PRINT(sk_csum_writepos); 2581 DESC_PRINT(sk_rsvd1); 2582 #undef PRINT 2583 } 2584 2585 void 2586 sk_dump_bytes(const char *data, int len) 2587 { 2588 int c, i, j; 2589 2590 for (i = 0; i < len; i += 16) { 2591 printf("%08x ", i); 2592 c = len - i; 2593 if (c > 16) c = 16; 2594 2595 for (j = 0; j < c; j++) { 2596 printf("%02x ", data[i + j] & 0xff); 2597 if ((j & 0xf) == 7 && j > 0) 2598 printf(" "); 2599 } 2600 2601 for (; j < 16; j++) 2602 printf(" "); 2603 printf(" "); 2604 2605 for (j = 0; j < c; j++) { 2606 int ch = data[i + j] & 0xff; 2607 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2608 } 2609 2610 printf("\n"); 2611 2612 if (c < 16) 2613 break; 2614 } 2615 } 2616 2617 void 2618 sk_dump_mbuf(struct mbuf *m) 2619 { 2620 int count = m->m_pkthdr.len; 2621 2622 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2623 2624 while (count > 0 && m) { 2625 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2626 m, m->m_data, m->m_len); 2627 sk_dump_bytes(mtod(m, char *), m->m_len); 2628 2629 count -= m->m_len; 2630 m = m->m_next; 2631 } 2632 } 2633 #endif 2634
Indexes created Tue Sep 23 07:09:52 GMT 2025