if_sk.c revision 1.31
1 /* $NetBSD: if_sk.c,v 1.31 2006/08/25 02:34:30 riz Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 #include "rnd.h" 126 127 #include <sys/param.h> 128 #include <sys/systm.h> 129 #include <sys/sockio.h> 130 #include <sys/mbuf.h> 131 #include <sys/malloc.h> 132 #include <sys/kernel.h> 133 #include <sys/socket.h> 134 #include <sys/device.h> 135 #include <sys/queue.h> 136 #include <sys/callout.h> 137 #include <sys/sysctl.h> 138 #include <sys/endian.h> 139 140 #include <net/if.h> 141 #include <net/if_dl.h> 142 #include <net/if_types.h> 143 144 #include <net/if_media.h> 145 146 #if NBPFILTER > 0 147 #include <net/bpf.h> 148 #endif 149 #if NRND > 0 150 #include <sys/rnd.h> 151 #endif 152 153 #include <dev/mii/mii.h> 154 #include <dev/mii/miivar.h> 155 #include <dev/mii/brgphyreg.h> 156 157 #include <dev/pci/pcireg.h> 158 #include <dev/pci/pcivar.h> 159 #include <dev/pci/pcidevs.h> 160 161 /* #define SK_USEIOSPACE */ 162 163 #include <dev/pci/if_skreg.h> 164 #include <dev/pci/if_skvar.h> 165 166 int skc_probe(struct device *, struct cfdata *, void *); 167 void skc_attach(struct device *, struct device *self, void *aux); 168 int sk_probe(struct device *, struct cfdata *, void *); 169 void sk_attach(struct device *, struct device *self, void *aux); 170 int skcprint(void *, const char *); 171 int sk_intr(void *); 172 void sk_intr_bcom(struct sk_if_softc *); 173 void sk_intr_xmac(struct sk_if_softc *); 174 void sk_intr_yukon(struct sk_if_softc *); 175 void sk_rxeof(struct sk_if_softc *); 176 void sk_txeof(struct sk_if_softc *); 177 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 178 void sk_start(struct ifnet *); 179 int sk_ioctl(struct ifnet *, u_long, caddr_t); 180 int sk_init(struct ifnet *); 181 void sk_init_xmac(struct sk_if_softc *); 182 void sk_init_yukon(struct sk_if_softc *); 183 void sk_stop(struct ifnet *, int); 184 void sk_watchdog(struct ifnet *); 185 void sk_shutdown(void *); 186 int sk_ifmedia_upd(struct ifnet *); 187 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 188 void sk_reset(struct sk_softc *); 189 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 190 int sk_alloc_jumbo_mem(struct sk_if_softc *); 191 void sk_free_jumbo_mem(struct sk_if_softc *); 192 void *sk_jalloc(struct sk_if_softc *); 193 void sk_jfree(struct mbuf *, caddr_t, size_t, void *); 194 int sk_init_rx_ring(struct sk_if_softc *); 195 int sk_init_tx_ring(struct sk_if_softc *); 196 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 197 void sk_vpd_read_res(struct sk_softc *, 198 struct vpd_res *, int); 199 void sk_vpd_read(struct sk_softc *); 200 201 void sk_update_int_mod(struct sk_softc *); 202 203 int sk_xmac_miibus_readreg(struct device *, int, int); 204 void sk_xmac_miibus_writereg(struct device *, int, int, int); 205 void sk_xmac_miibus_statchg(struct device *); 206 207 int sk_marv_miibus_readreg(struct device *, int, int); 208 void sk_marv_miibus_writereg(struct device *, int, int, int); 209 void sk_marv_miibus_statchg(struct device *); 210 211 u_int32_t sk_xmac_hash(caddr_t); 212 u_int32_t sk_yukon_hash(caddr_t); 213 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 214 void sk_setmulti(struct sk_if_softc *); 215 void sk_tick(void *); 216 217 /* #define SK_DEBUG 2 */ 218 #ifdef SK_DEBUG 219 #define DPRINTF(x) if (skdebug) printf x 220 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 221 int skdebug = SK_DEBUG; 222 223 void sk_dump_txdesc(struct sk_tx_desc *, int); 224 void sk_dump_mbuf(struct mbuf *); 225 void sk_dump_bytes(const char *, int); 226 #else 227 #define DPRINTF(x) 228 #define DPRINTFN(n,x) 229 #endif 230 231 #define SK_SETBIT(sc, reg, x) \ 232 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 233 234 #define SK_CLRBIT(sc, reg, x) \ 235 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 236 237 #define SK_WIN_SETBIT_4(sc, reg, x) \ 238 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 239 240 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 241 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 242 243 #define SK_WIN_SETBIT_2(sc, reg, x) \ 244 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 245 246 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 247 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 248 249 static int sk_sysctl_handler(SYSCTLFN_PROTO); 250 static int sk_root_num; 251 252 /* supported device vendors */ 253 static const struct sk_product { 254 pci_vendor_id_t sk_vendor; 255 pci_product_id_t sk_product; 256 } sk_products[] = { 257 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 258 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 259 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T, }, 260 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 261 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 262 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 263 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 264 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 265 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 266 { 0, 0, } 267 }; 268 269 #define SK_LINKSYS_EG1032_SUBID 0x00151737 270 271 static inline u_int32_t 272 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 273 { 274 #ifdef SK_USEIOSPACE 275 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 276 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 277 #else 278 return CSR_READ_4(sc, reg); 279 #endif 280 } 281 282 static inline u_int16_t 283 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 284 { 285 #ifdef SK_USEIOSPACE 286 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 287 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 288 #else 289 return CSR_READ_2(sc, reg); 290 #endif 291 } 292 293 static inline u_int8_t 294 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 295 { 296 #ifdef SK_USEIOSPACE 297 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 298 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 299 #else 300 return CSR_READ_1(sc, reg); 301 #endif 302 } 303 304 static inline void 305 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 306 { 307 #ifdef SK_USEIOSPACE 308 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 309 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 310 #else 311 CSR_WRITE_4(sc, reg, x); 312 #endif 313 } 314 315 static inline void 316 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 317 { 318 #ifdef SK_USEIOSPACE 319 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 320 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 321 #else 322 CSR_WRITE_2(sc, reg, x); 323 #endif 324 } 325 326 static inline void 327 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 328 { 329 #ifdef SK_USEIOSPACE 330 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 331 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 332 #else 333 CSR_WRITE_1(sc, reg, x); 334 #endif 335 } 336 337 /* 338 * The VPD EEPROM contains Vital Product Data, as suggested in 339 * the PCI 2.1 specification. The VPD data is separared into areas 340 * denoted by resource IDs. The SysKonnect VPD contains an ID string 341 * resource (the name of the adapter), a read-only area resource 342 * containing various key/data fields and a read/write area which 343 * can be used to store asset management information or log messages. 344 * We read the ID string and read-only into buffers attached to 345 * the controller softc structure for later use. At the moment, 346 * we only use the ID string during sk_attach(). 347 */ 348 u_int8_t 349 sk_vpd_readbyte(struct sk_softc *sc, int addr) 350 { 351 int i; 352 353 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 354 for (i = 0; i < SK_TIMEOUT; i++) { 355 DELAY(1); 356 if (sk_win_read_2(sc, 357 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 358 break; 359 } 360 361 if (i == SK_TIMEOUT) 362 return 0; 363 364 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 365 } 366 367 void 368 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 369 { 370 int i; 371 u_int8_t *ptr; 372 373 ptr = (u_int8_t *)res; 374 for (i = 0; i < sizeof(struct vpd_res); i++) 375 ptr[i] = sk_vpd_readbyte(sc, i + addr); 376 } 377 378 void 379 sk_vpd_read(struct sk_softc *sc) 380 { 381 int pos = 0, i; 382 struct vpd_res res; 383 384 if (sc->sk_vpd_prodname != NULL) 385 free(sc->sk_vpd_prodname, M_DEVBUF); 386 if (sc->sk_vpd_readonly != NULL) 387 free(sc->sk_vpd_readonly, M_DEVBUF); 388 sc->sk_vpd_prodname = NULL; 389 sc->sk_vpd_readonly = NULL; 390 391 sk_vpd_read_res(sc, &res, pos); 392 393 if (res.vr_id != VPD_RES_ID) { 394 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 395 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 396 return; 397 } 398 399 pos += sizeof(res); 400 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 401 if (sc->sk_vpd_prodname == NULL) 402 panic("sk_vpd_read"); 403 for (i = 0; i < res.vr_len; i++) 404 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 405 sc->sk_vpd_prodname[i] = '\0'; 406 pos += i; 407 408 sk_vpd_read_res(sc, &res, pos); 409 410 if (res.vr_id != VPD_RES_READ) { 411 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 412 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 413 return; 414 } 415 416 pos += sizeof(res); 417 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 418 if (sc->sk_vpd_readonly == NULL) 419 panic("sk_vpd_read"); 420 for (i = 0; i < res.vr_len ; i++) 421 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 422 } 423 424 int 425 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 426 { 427 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 428 int i; 429 430 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 431 432 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 433 return 0; 434 435 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 436 SK_XM_READ_2(sc_if, XM_PHY_DATA); 437 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 438 for (i = 0; i < SK_TIMEOUT; i++) { 439 DELAY(1); 440 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 441 XM_MMUCMD_PHYDATARDY) 442 break; 443 } 444 445 if (i == SK_TIMEOUT) { 446 aprint_error("%s: phy failed to come ready\n", 447 sc_if->sk_dev.dv_xname); 448 return 0; 449 } 450 } 451 DELAY(1); 452 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 453 } 454 455 void 456 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 457 { 458 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 459 int i; 460 461 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 462 463 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 464 for (i = 0; i < SK_TIMEOUT; i++) { 465 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 466 break; 467 } 468 469 if (i == SK_TIMEOUT) { 470 aprint_error("%s: phy failed to come ready\n", 471 sc_if->sk_dev.dv_xname); 472 return; 473 } 474 475 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 476 for (i = 0; i < SK_TIMEOUT; i++) { 477 DELAY(1); 478 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 479 break; 480 } 481 482 if (i == SK_TIMEOUT) 483 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 484 } 485 486 void 487 sk_xmac_miibus_statchg(struct device *dev) 488 { 489 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 490 struct mii_data *mii = &sc_if->sk_mii; 491 492 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 493 494 /* 495 * If this is a GMII PHY, manually set the XMAC's 496 * duplex mode accordingly. 497 */ 498 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 499 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 500 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 501 else 502 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 503 } 504 } 505 506 int 507 sk_marv_miibus_readreg(struct device *dev, int phy, int reg) 508 { 509 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 510 u_int16_t val; 511 int i; 512 513 if (phy != 0 || 514 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 515 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 516 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 517 phy, reg)); 518 return 0; 519 } 520 521 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 522 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 523 524 for (i = 0; i < SK_TIMEOUT; i++) { 525 DELAY(1); 526 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 527 if (val & YU_SMICR_READ_VALID) 528 break; 529 } 530 531 if (i == SK_TIMEOUT) { 532 aprint_error("%s: phy failed to come ready\n", 533 sc_if->sk_dev.dv_xname); 534 return 0; 535 } 536 537 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 538 SK_TIMEOUT)); 539 540 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 541 542 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 543 phy, reg, val)); 544 545 return val; 546 } 547 548 void 549 sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 550 { 551 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 552 int i; 553 554 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 555 phy, reg, val)); 556 557 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 558 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 559 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 560 561 for (i = 0; i < SK_TIMEOUT; i++) { 562 DELAY(1); 563 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 564 break; 565 } 566 } 567 568 void 569 sk_marv_miibus_statchg(struct device *dev) 570 { 571 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 572 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 573 } 574 575 #define SK_HASH_BITS 6 576 577 u_int32_t 578 sk_xmac_hash(caddr_t addr) 579 { 580 u_int32_t crc; 581 582 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 583 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 584 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 585 return crc; 586 } 587 588 u_int32_t 589 sk_yukon_hash(caddr_t addr) 590 { 591 u_int32_t crc; 592 593 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 594 crc &= ((1 << SK_HASH_BITS) - 1); 595 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 596 return crc; 597 } 598 599 void 600 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 601 { 602 int base = XM_RXFILT_ENTRY(slot); 603 604 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 605 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 606 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 607 } 608 609 void 610 sk_setmulti(struct sk_if_softc *sc_if) 611 { 612 struct sk_softc *sc = sc_if->sk_softc; 613 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 614 u_int32_t hashes[2] = { 0, 0 }; 615 int h = 0, i; 616 struct ethercom *ec = &sc_if->sk_ethercom; 617 struct ether_multi *enm; 618 struct ether_multistep step; 619 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 620 621 /* First, zot all the existing filters. */ 622 switch (sc->sk_type) { 623 case SK_GENESIS: 624 for (i = 1; i < XM_RXFILT_MAX; i++) 625 sk_setfilt(sc_if, (caddr_t)&dummy, i); 626 627 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 628 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 629 break; 630 case SK_YUKON: 631 case SK_YUKON_LITE: 632 case SK_YUKON_LP: 633 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 634 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 635 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 636 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 637 break; 638 } 639 640 /* Now program new ones. */ 641 allmulti: 642 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 643 hashes[0] = 0xFFFFFFFF; 644 hashes[1] = 0xFFFFFFFF; 645 } else { 646 i = 1; 647 /* First find the tail of the list. */ 648 ETHER_FIRST_MULTI(step, ec, enm); 649 while (enm != NULL) { 650 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 651 ETHER_ADDR_LEN)) { 652 ifp->if_flags |= IFF_ALLMULTI; 653 goto allmulti; 654 } 655 DPRINTFN(2,("multicast address %s\n", 656 ether_sprintf(enm->enm_addrlo))); 657 /* 658 * Program the first XM_RXFILT_MAX multicast groups 659 * into the perfect filter. For all others, 660 * use the hash table. 661 */ 662 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 663 sk_setfilt(sc_if, enm->enm_addrlo, i); 664 i++; 665 } 666 else { 667 switch (sc->sk_type) { 668 case SK_GENESIS: 669 h = sk_xmac_hash(enm->enm_addrlo); 670 break; 671 case SK_YUKON: 672 case SK_YUKON_LITE: 673 case SK_YUKON_LP: 674 h = sk_yukon_hash(enm->enm_addrlo); 675 break; 676 } 677 if (h < 32) 678 hashes[0] |= (1 << h); 679 else 680 hashes[1] |= (1 << (h - 32)); 681 } 682 683 ETHER_NEXT_MULTI(step, enm); 684 } 685 } 686 687 switch (sc->sk_type) { 688 case SK_GENESIS: 689 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 690 XM_MODE_RX_USE_PERFECT); 691 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 692 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 693 break; 694 case SK_YUKON: 695 case SK_YUKON_LITE: 696 case SK_YUKON_LP: 697 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 698 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 699 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 700 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 701 break; 702 } 703 } 704 705 int 706 sk_init_rx_ring(struct sk_if_softc *sc_if) 707 { 708 struct sk_chain_data *cd = &sc_if->sk_cdata; 709 struct sk_ring_data *rd = sc_if->sk_rdata; 710 int i; 711 712 bzero((char *)rd->sk_rx_ring, 713 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 714 715 for (i = 0; i < SK_RX_RING_CNT; i++) { 716 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 717 if (i == (SK_RX_RING_CNT - 1)) { 718 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 719 rd->sk_rx_ring[i].sk_next = 720 htole32(SK_RX_RING_ADDR(sc_if, 0)); 721 } else { 722 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 723 rd->sk_rx_ring[i].sk_next = 724 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 725 } 726 } 727 728 for (i = 0; i < SK_RX_RING_CNT; i++) { 729 if (sk_newbuf(sc_if, i, NULL, 730 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 731 aprint_error("%s: failed alloc of %dth mbuf\n", 732 sc_if->sk_dev.dv_xname, i); 733 return ENOBUFS; 734 } 735 } 736 sc_if->sk_cdata.sk_rx_prod = 0; 737 sc_if->sk_cdata.sk_rx_cons = 0; 738 739 return 0; 740 } 741 742 int 743 sk_init_tx_ring(struct sk_if_softc *sc_if) 744 { 745 struct sk_chain_data *cd = &sc_if->sk_cdata; 746 struct sk_ring_data *rd = sc_if->sk_rdata; 747 int i; 748 749 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 750 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 751 752 for (i = 0; i < SK_TX_RING_CNT; i++) { 753 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 754 if (i == (SK_TX_RING_CNT - 1)) { 755 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 756 rd->sk_tx_ring[i].sk_next = 757 htole32(SK_TX_RING_ADDR(sc_if, 0)); 758 } else { 759 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 760 rd->sk_tx_ring[i].sk_next = 761 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 762 } 763 } 764 765 sc_if->sk_cdata.sk_tx_prod = 0; 766 sc_if->sk_cdata.sk_tx_cons = 0; 767 sc_if->sk_cdata.sk_tx_cnt = 0; 768 769 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 770 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 771 772 return 0; 773 } 774 775 int 776 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 777 bus_dmamap_t dmamap) 778 { 779 struct mbuf *m_new = NULL; 780 struct sk_chain *c; 781 struct sk_rx_desc *r; 782 783 if (m == NULL) { 784 caddr_t buf = NULL; 785 786 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 787 if (m_new == NULL) { 788 aprint_error("%s: no memory for rx list -- " 789 "packet dropped!\n", sc_if->sk_dev.dv_xname); 790 return ENOBUFS; 791 } 792 793 /* Allocate the jumbo buffer */ 794 buf = sk_jalloc(sc_if); 795 if (buf == NULL) { 796 m_freem(m_new); 797 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 798 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 799 return ENOBUFS; 800 } 801 802 /* Attach the buffer to the mbuf */ 803 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 804 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 805 806 } else { 807 /* 808 * We're re-using a previously allocated mbuf; 809 * be sure to re-init pointers and lengths to 810 * default values. 811 */ 812 m_new = m; 813 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 814 m_new->m_data = m_new->m_ext.ext_buf; 815 } 816 m_adj(m_new, ETHER_ALIGN); 817 818 c = &sc_if->sk_cdata.sk_rx_chain[i]; 819 r = c->sk_desc; 820 c->sk_mbuf = m_new; 821 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 822 (((vaddr_t)m_new->m_data 823 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 824 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 825 826 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 827 828 return 0; 829 } 830 831 /* 832 * Memory management for jumbo frames. 833 */ 834 835 int 836 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 837 { 838 struct sk_softc *sc = sc_if->sk_softc; 839 caddr_t ptr, kva; 840 bus_dma_segment_t seg; 841 int i, rseg, state, error; 842 struct sk_jpool_entry *entry; 843 844 state = error = 0; 845 846 /* Grab a big chunk o' storage. */ 847 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 848 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 849 aprint_error("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 850 return ENOBUFS; 851 } 852 853 state = 1; 854 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, &kva, 855 BUS_DMA_NOWAIT)) { 856 aprint_error("%s: can't map dma buffers (%d bytes)\n", 857 sc->sk_dev.dv_xname, SK_JMEM); 858 error = ENOBUFS; 859 goto out; 860 } 861 862 state = 2; 863 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 864 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 865 aprint_error("%s: can't create dma map\n", sc->sk_dev.dv_xname); 866 error = ENOBUFS; 867 goto out; 868 } 869 870 state = 3; 871 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 872 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 873 aprint_error("%s: can't load dma map\n", sc->sk_dev.dv_xname); 874 error = ENOBUFS; 875 goto out; 876 } 877 878 state = 4; 879 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 880 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 881 882 LIST_INIT(&sc_if->sk_jfree_listhead); 883 LIST_INIT(&sc_if->sk_jinuse_listhead); 884 885 /* 886 * Now divide it up into 9K pieces and save the addresses 887 * in an array. 888 */ 889 ptr = sc_if->sk_cdata.sk_jumbo_buf; 890 for (i = 0; i < SK_JSLOTS; i++) { 891 sc_if->sk_cdata.sk_jslots[i] = ptr; 892 ptr += SK_JLEN; 893 entry = malloc(sizeof(struct sk_jpool_entry), 894 M_DEVBUF, M_NOWAIT); 895 if (entry == NULL) { 896 aprint_error("%s: no memory for jumbo buffer queue!\n", 897 sc->sk_dev.dv_xname); 898 error = ENOBUFS; 899 goto out; 900 } 901 entry->slot = i; 902 if (i) 903 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 904 entry, jpool_entries); 905 else 906 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 907 entry, jpool_entries); 908 } 909 out: 910 if (error != 0) { 911 switch (state) { 912 case 4: 913 bus_dmamap_unload(sc->sc_dmatag, 914 sc_if->sk_cdata.sk_rx_jumbo_map); 915 case 3: 916 bus_dmamap_destroy(sc->sc_dmatag, 917 sc_if->sk_cdata.sk_rx_jumbo_map); 918 case 2: 919 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 920 case 1: 921 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 922 break; 923 default: 924 break; 925 } 926 } 927 928 return error; 929 } 930 931 /* 932 * Allocate a jumbo buffer. 933 */ 934 void * 935 sk_jalloc(struct sk_if_softc *sc_if) 936 { 937 struct sk_jpool_entry *entry; 938 939 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 940 941 if (entry == NULL) 942 return NULL; 943 944 LIST_REMOVE(entry, jpool_entries); 945 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 946 return sc_if->sk_cdata.sk_jslots[entry->slot]; 947 } 948 949 /* 950 * Release a jumbo buffer. 951 */ 952 void 953 sk_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 954 { 955 struct sk_jpool_entry *entry; 956 struct sk_if_softc *sc; 957 int i, s; 958 959 /* Extract the softc struct pointer. */ 960 sc = (struct sk_if_softc *)arg; 961 962 if (sc == NULL) 963 panic("sk_jfree: can't find softc pointer!"); 964 965 /* calculate the slot this buffer belongs to */ 966 967 i = ((vaddr_t)buf 968 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 969 970 if ((i < 0) || (i >= SK_JSLOTS)) 971 panic("sk_jfree: asked to free buffer that we don't manage!"); 972 973 s = splvm(); 974 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 975 if (entry == NULL) 976 panic("sk_jfree: buffer not in use!"); 977 entry->slot = i; 978 LIST_REMOVE(entry, jpool_entries); 979 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 980 981 if (__predict_true(m != NULL)) 982 pool_cache_put(&mbpool_cache, m); 983 splx(s); 984 } 985 986 /* 987 * Set media options. 988 */ 989 int 990 sk_ifmedia_upd(struct ifnet *ifp) 991 { 992 struct sk_if_softc *sc_if = ifp->if_softc; 993 994 (void) sk_init(ifp); 995 mii_mediachg(&sc_if->sk_mii); 996 return 0; 997 } 998 999 /* 1000 * Report current media status. 1001 */ 1002 void 1003 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1004 { 1005 struct sk_if_softc *sc_if = ifp->if_softc; 1006 1007 mii_pollstat(&sc_if->sk_mii); 1008 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 1009 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 1010 } 1011 1012 int 1013 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1014 { 1015 struct sk_if_softc *sc_if = ifp->if_softc; 1016 struct sk_softc *sc = sc_if->sk_softc; 1017 struct ifreq *ifr = (struct ifreq *) data; 1018 struct mii_data *mii; 1019 int s, error = 0; 1020 1021 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1022 1023 s = splnet(); 1024 1025 switch (command) { 1026 1027 case SIOCSIFFLAGS: 1028 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1029 if (ifp->if_flags & IFF_UP) { 1030 if (ifp->if_flags & IFF_RUNNING && 1031 ifp->if_flags & IFF_PROMISC && 1032 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1033 switch (sc->sk_type) { 1034 case SK_GENESIS: 1035 SK_XM_SETBIT_4(sc_if, XM_MODE, 1036 XM_MODE_RX_PROMISC); 1037 break; 1038 case SK_YUKON: 1039 case SK_YUKON_LITE: 1040 case SK_YUKON_LP: 1041 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1042 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1043 break; 1044 } 1045 sk_setmulti(sc_if); 1046 } else if (ifp->if_flags & IFF_RUNNING && 1047 !(ifp->if_flags & IFF_PROMISC) && 1048 sc_if->sk_if_flags & IFF_PROMISC) { 1049 switch (sc->sk_type) { 1050 case SK_GENESIS: 1051 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1052 XM_MODE_RX_PROMISC); 1053 break; 1054 case SK_YUKON: 1055 case SK_YUKON_LITE: 1056 case SK_YUKON_LP: 1057 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1058 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1059 break; 1060 } 1061 1062 sk_setmulti(sc_if); 1063 } else 1064 (void) sk_init(ifp); 1065 } else { 1066 if (ifp->if_flags & IFF_RUNNING) 1067 sk_stop(ifp,0); 1068 } 1069 sc_if->sk_if_flags = ifp->if_flags; 1070 error = 0; 1071 break; 1072 1073 case SIOCGIFMEDIA: 1074 case SIOCSIFMEDIA: 1075 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 1076 mii = &sc_if->sk_mii; 1077 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1078 break; 1079 default: 1080 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1081 error = ether_ioctl(ifp, command, data); 1082 1083 if ( error == ENETRESET) { 1084 if (ifp->if_flags & IFF_RUNNING) { 1085 sk_setmulti(sc_if); 1086 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1087 } 1088 error = 0; 1089 } else if ( error ) { 1090 splx(s); 1091 return error; 1092 } 1093 break; 1094 } 1095 1096 splx(s); 1097 return error; 1098 } 1099 1100 void 1101 sk_update_int_mod(struct sk_softc *sc) 1102 { 1103 u_int32_t sk_imtimer_ticks; 1104 1105 /* 1106 * Configure interrupt moderation. The moderation timer 1107 * defers interrupts specified in the interrupt moderation 1108 * timer mask based on the timeout specified in the interrupt 1109 * moderation timer init register. Each bit in the timer 1110 * register represents one tick, so to specify a timeout in 1111 * microseconds, we have to multiply by the correct number of 1112 * ticks-per-microsecond. 1113 */ 1114 switch (sc->sk_type) { 1115 case SK_GENESIS: 1116 sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1117 break; 1118 case SK_YUKON_EC: 1119 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1120 break; 1121 default: 1122 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1123 } 1124 aprint_verbose("%s: interrupt moderation is %d us\n", 1125 sc->sk_dev.dv_xname, sc->sk_int_mod); 1126 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1127 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1128 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1129 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1130 sc->sk_int_mod_pending = 0; 1131 } 1132 1133 /* 1134 * Lookup: Check the PCI vendor and device, and return a pointer to 1135 * The structure if the IDs match against our list. 1136 */ 1137 1138 static const struct sk_product * 1139 sk_lookup(const struct pci_attach_args *pa) 1140 { 1141 const struct sk_product *psk; 1142 1143 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1144 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1145 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1146 return psk; 1147 } 1148 return NULL; 1149 } 1150 1151 /* 1152 * Probe for a SysKonnect GEnesis chip. 1153 */ 1154 1155 int 1156 skc_probe(struct device *parent, struct cfdata *match, void *aux) 1157 { 1158 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1159 const struct sk_product *psk; 1160 pcireg_t subid; 1161 1162 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1163 1164 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1165 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1166 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1167 subid == SK_LINKSYS_EG1032_SUBID) 1168 return 1; 1169 1170 if ((psk = sk_lookup(pa))) { 1171 return 1; 1172 } 1173 return 0; 1174 } 1175 1176 /* 1177 * Force the GEnesis into reset, then bring it out of reset. 1178 */ 1179 void sk_reset(struct sk_softc *sc) 1180 { 1181 DPRINTFN(2, ("sk_reset\n")); 1182 1183 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1184 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1185 if (SK_YUKON_FAMILY(sc->sk_type)) 1186 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1187 1188 DELAY(1000); 1189 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1190 DELAY(2); 1191 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1192 if (SK_YUKON_FAMILY(sc->sk_type)) 1193 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1194 1195 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1196 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1197 CSR_READ_2(sc, SK_LINK_CTRL))); 1198 1199 if (sc->sk_type == SK_GENESIS) { 1200 /* Configure packet arbiter */ 1201 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1202 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1203 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1204 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1205 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1206 } 1207 1208 /* Enable RAM interface */ 1209 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1210 1211 sk_update_int_mod(sc); 1212 } 1213 1214 int 1215 sk_probe(struct device *parent, struct cfdata *match, void *aux) 1216 { 1217 struct skc_attach_args *sa = aux; 1218 1219 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1220 return 0; 1221 1222 return 1; 1223 } 1224 1225 /* 1226 * Each XMAC chip is attached as a separate logical IP interface. 1227 * Single port cards will have only one logical interface of course. 1228 */ 1229 void 1230 sk_attach(struct device *parent, struct device *self, void *aux) 1231 { 1232 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1233 struct sk_softc *sc = (struct sk_softc *)parent; 1234 struct skc_attach_args *sa = aux; 1235 struct sk_txmap_entry *entry; 1236 struct ifnet *ifp; 1237 bus_dma_segment_t seg; 1238 bus_dmamap_t dmamap; 1239 caddr_t kva; 1240 int i, rseg; 1241 1242 sc_if->sk_port = sa->skc_port; 1243 sc_if->sk_softc = sc; 1244 sc->sk_if[sa->skc_port] = sc_if; 1245 1246 if (sa->skc_port == SK_PORT_A) 1247 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1248 if (sa->skc_port == SK_PORT_B) 1249 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1250 1251 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1252 1253 /* 1254 * Get station address for this interface. Note that 1255 * dual port cards actually come with three station 1256 * addresses: one for each port, plus an extra. The 1257 * extra one is used by the SysKonnect driver software 1258 * as a 'virtual' station address for when both ports 1259 * are operating in failover mode. Currently we don't 1260 * use this extra address. 1261 */ 1262 for (i = 0; i < ETHER_ADDR_LEN; i++) 1263 sc_if->sk_enaddr[i] = 1264 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1265 1266 1267 aprint_normal(": Ethernet address %s\n", 1268 ether_sprintf(sc_if->sk_enaddr)); 1269 1270 /* 1271 * Set up RAM buffer addresses. The NIC will have a certain 1272 * amount of SRAM on it, somewhere between 512K and 2MB. We 1273 * need to divide this up a) between the transmitter and 1274 * receiver and b) between the two XMACs, if this is a 1275 * dual port NIC. Our algorithm is to divide up the memory 1276 * evenly so that everyone gets a fair share. 1277 */ 1278 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1279 u_int32_t chunk, val; 1280 1281 chunk = sc->sk_ramsize / 2; 1282 val = sc->sk_rboff / sizeof(u_int64_t); 1283 sc_if->sk_rx_ramstart = val; 1284 val += (chunk / sizeof(u_int64_t)); 1285 sc_if->sk_rx_ramend = val - 1; 1286 sc_if->sk_tx_ramstart = val; 1287 val += (chunk / sizeof(u_int64_t)); 1288 sc_if->sk_tx_ramend = val - 1; 1289 } else { 1290 u_int32_t chunk, val; 1291 1292 chunk = sc->sk_ramsize / 4; 1293 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1294 sizeof(u_int64_t); 1295 sc_if->sk_rx_ramstart = val; 1296 val += (chunk / sizeof(u_int64_t)); 1297 sc_if->sk_rx_ramend = val - 1; 1298 sc_if->sk_tx_ramstart = val; 1299 val += (chunk / sizeof(u_int64_t)); 1300 sc_if->sk_tx_ramend = val - 1; 1301 } 1302 1303 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1304 " tx_ramstart=%#x tx_ramend=%#x\n", 1305 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1306 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1307 1308 /* Read and save PHY type and set PHY address */ 1309 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1310 switch (sc_if->sk_phytype) { 1311 case SK_PHYTYPE_XMAC: 1312 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1313 break; 1314 case SK_PHYTYPE_BCOM: 1315 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1316 break; 1317 case SK_PHYTYPE_MARV_COPPER: 1318 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1319 break; 1320 default: 1321 aprint_error("%s: unsupported PHY type: %d\n", 1322 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1323 return; 1324 } 1325 1326 /* Allocate the descriptor queues. */ 1327 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1328 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1329 aprint_error("%s: can't alloc rx buffers\n", 1330 sc->sk_dev.dv_xname); 1331 goto fail; 1332 } 1333 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1334 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1335 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1336 sc_if->sk_dev.dv_xname, 1337 (u_long) sizeof(struct sk_ring_data)); 1338 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1339 goto fail; 1340 } 1341 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1342 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1343 &sc_if->sk_ring_map)) { 1344 aprint_error("%s: can't create dma map\n", 1345 sc_if->sk_dev.dv_xname); 1346 bus_dmamem_unmap(sc->sc_dmatag, kva, 1347 sizeof(struct sk_ring_data)); 1348 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1349 goto fail; 1350 } 1351 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1352 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1353 aprint_error("%s: can't load dma map\n", 1354 sc_if->sk_dev.dv_xname); 1355 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1356 bus_dmamem_unmap(sc->sc_dmatag, kva, 1357 sizeof(struct sk_ring_data)); 1358 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1359 goto fail; 1360 } 1361 1362 for (i = 0; i < SK_RX_RING_CNT; i++) 1363 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1364 1365 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1366 for (i = 0; i < SK_TX_RING_CNT; i++) { 1367 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1368 1369 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1370 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1371 aprint_error("%s: Can't create TX dmamap\n", 1372 sc_if->sk_dev.dv_xname); 1373 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1374 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1375 bus_dmamem_unmap(sc->sc_dmatag, kva, 1376 sizeof(struct sk_ring_data)); 1377 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1378 goto fail; 1379 } 1380 1381 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1382 if (!entry) { 1383 aprint_error("%s: Can't alloc txmap entry\n", 1384 sc_if->sk_dev.dv_xname); 1385 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1386 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1387 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1388 bus_dmamem_unmap(sc->sc_dmatag, kva, 1389 sizeof(struct sk_ring_data)); 1390 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1391 goto fail; 1392 } 1393 entry->dmamap = dmamap; 1394 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1395 } 1396 1397 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1398 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1399 1400 ifp = &sc_if->sk_ethercom.ec_if; 1401 /* Try to allocate memory for jumbo buffers. */ 1402 if (sk_alloc_jumbo_mem(sc_if)) { 1403 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1404 goto fail; 1405 } 1406 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1407 | ETHERCAP_JUMBO_MTU; 1408 1409 ifp->if_softc = sc_if; 1410 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1411 ifp->if_ioctl = sk_ioctl; 1412 ifp->if_start = sk_start; 1413 ifp->if_stop = sk_stop; 1414 ifp->if_init = sk_init; 1415 ifp->if_watchdog = sk_watchdog; 1416 ifp->if_capabilities = 0; 1417 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1418 IFQ_SET_READY(&ifp->if_snd); 1419 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1420 1421 /* 1422 * Do miibus setup. 1423 */ 1424 switch (sc->sk_type) { 1425 case SK_GENESIS: 1426 sk_init_xmac(sc_if); 1427 break; 1428 case SK_YUKON: 1429 case SK_YUKON_LITE: 1430 case SK_YUKON_LP: 1431 sk_init_yukon(sc_if); 1432 break; 1433 default: 1434 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1435 sc->sk_type); 1436 } 1437 1438 DPRINTFN(2, ("sk_attach: 1\n")); 1439 1440 sc_if->sk_mii.mii_ifp = ifp; 1441 switch (sc->sk_type) { 1442 case SK_GENESIS: 1443 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1444 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1445 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1446 break; 1447 case SK_YUKON: 1448 case SK_YUKON_LITE: 1449 case SK_YUKON_LP: 1450 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1451 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1452 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1453 break; 1454 } 1455 1456 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1457 sk_ifmedia_upd, sk_ifmedia_sts); 1458 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1459 MII_OFFSET_ANY, 0); 1460 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1461 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1462 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1463 0, NULL); 1464 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1465 } else 1466 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1467 1468 callout_init(&sc_if->sk_tick_ch); 1469 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1470 1471 DPRINTFN(2, ("sk_attach: 1\n")); 1472 1473 /* 1474 * Call MI attach routines. 1475 */ 1476 if_attach(ifp); 1477 1478 ether_ifattach(ifp, sc_if->sk_enaddr); 1479 1480 #if NRND > 0 1481 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1482 RND_TYPE_NET, 0); 1483 #endif 1484 1485 DPRINTFN(2, ("sk_attach: end\n")); 1486 1487 return; 1488 1489 fail: 1490 sc->sk_if[sa->skc_port] = NULL; 1491 } 1492 1493 int 1494 skcprint(void *aux, const char *pnp) 1495 { 1496 struct skc_attach_args *sa = aux; 1497 1498 if (pnp) 1499 aprint_normal("sk port %c at %s", 1500 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1501 else 1502 aprint_normal(" port %c", 1503 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1504 return UNCONF; 1505 } 1506 1507 /* 1508 * Attach the interface. Allocate softc structures, do ifmedia 1509 * setup and ethernet/BPF attach. 1510 */ 1511 void 1512 skc_attach(struct device *parent, struct device *self, void *aux) 1513 { 1514 struct sk_softc *sc = (struct sk_softc *)self; 1515 struct pci_attach_args *pa = aux; 1516 struct skc_attach_args skca; 1517 pci_chipset_tag_t pc = pa->pa_pc; 1518 #ifndef SK_USEIOSPACE 1519 pcireg_t memtype; 1520 #endif 1521 pci_intr_handle_t ih; 1522 const char *intrstr = NULL; 1523 bus_addr_t iobase; 1524 bus_size_t iosize; 1525 int rc, sk_nodenum; 1526 u_int32_t command; 1527 const char *revstr; 1528 const struct sysctlnode *node; 1529 1530 DPRINTFN(2, ("begin skc_attach\n")); 1531 1532 /* 1533 * Handle power management nonsense. 1534 */ 1535 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1536 1537 if (command == 0x01) { 1538 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1539 if (command & SK_PSTATE_MASK) { 1540 u_int32_t xiobase, membase, irq; 1541 1542 /* Save important PCI config data. */ 1543 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1544 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1545 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1546 1547 /* Reset the power state. */ 1548 aprint_normal("%s chip is in D%d power mode " 1549 "-- setting to D0\n", sc->sk_dev.dv_xname, 1550 command & SK_PSTATE_MASK); 1551 command &= 0xFFFFFFFC; 1552 pci_conf_write(pc, pa->pa_tag, 1553 SK_PCI_PWRMGMTCTRL, command); 1554 1555 /* Restore PCI config data. */ 1556 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1557 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1558 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1559 } 1560 } 1561 1562 /* 1563 * Map control/status registers. 1564 */ 1565 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1566 command |= PCI_COMMAND_IO_ENABLE | 1567 PCI_COMMAND_MEM_ENABLE | 1568 PCI_COMMAND_MASTER_ENABLE; 1569 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1570 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1571 1572 #ifdef SK_USEIOSPACE 1573 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1574 aprint_error(": failed to enable I/O ports!\n"); 1575 return; 1576 } 1577 /* 1578 * Map control/status registers. 1579 */ 1580 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1581 &sc->sk_btag, &sc->sk_bhandle, 1582 &iobase, &iosize)) { 1583 aprint_error(": can't find i/o space\n"); 1584 return; 1585 } 1586 #else 1587 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1588 aprint_error(": failed to enable memory mapping!\n"); 1589 return; 1590 } 1591 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1592 switch (memtype) { 1593 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1594 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1595 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1596 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1597 &iobase, &iosize) == 0) 1598 break; 1599 default: 1600 aprint_error("%s: can't find mem space\n", 1601 sc->sk_dev.dv_xname); 1602 return; 1603 } 1604 1605 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1606 #endif 1607 sc->sc_dmatag = pa->pa_dmat; 1608 1609 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1610 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1611 1612 /* bail out here if chip is not recognized */ 1613 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1614 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1615 goto fail; 1616 } 1617 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1618 1619 /* Allocate interrupt */ 1620 if (pci_intr_map(pa, &ih)) { 1621 aprint_error(": couldn't map interrupt\n"); 1622 goto fail; 1623 } 1624 1625 intrstr = pci_intr_string(pc, ih); 1626 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1627 if (sc->sk_intrhand == NULL) { 1628 aprint_error(": couldn't establish interrupt"); 1629 if (intrstr != NULL) 1630 aprint_normal(" at %s", intrstr); 1631 goto fail; 1632 } 1633 aprint_normal(": %s\n", intrstr); 1634 1635 /* Reset the adapter. */ 1636 sk_reset(sc); 1637 1638 /* Read and save vital product data from EEPROM. */ 1639 sk_vpd_read(sc); 1640 1641 if (sc->sk_type == SK_GENESIS) { 1642 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1643 /* Read and save RAM size and RAMbuffer offset */ 1644 switch (val) { 1645 case SK_RAMSIZE_512K_64: 1646 sc->sk_ramsize = 0x80000; 1647 sc->sk_rboff = SK_RBOFF_0; 1648 break; 1649 case SK_RAMSIZE_1024K_64: 1650 sc->sk_ramsize = 0x100000; 1651 sc->sk_rboff = SK_RBOFF_80000; 1652 break; 1653 case SK_RAMSIZE_1024K_128: 1654 sc->sk_ramsize = 0x100000; 1655 sc->sk_rboff = SK_RBOFF_0; 1656 break; 1657 case SK_RAMSIZE_2048K_128: 1658 sc->sk_ramsize = 0x200000; 1659 sc->sk_rboff = SK_RBOFF_0; 1660 break; 1661 default: 1662 aprint_error("%s: unknown ram size: %d\n", 1663 sc->sk_dev.dv_xname, val); 1664 goto fail_1; 1665 break; 1666 } 1667 1668 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1669 sc->sk_ramsize, sc->sk_ramsize / 1024, 1670 sc->sk_rboff)); 1671 } else { 1672 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1673 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1674 sc->sk_rboff = SK_RBOFF_0; 1675 1676 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1677 sc->sk_ramsize / 1024, sc->sk_ramsize, 1678 sc->sk_rboff)); 1679 } 1680 1681 /* Read and save physical media type */ 1682 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1683 case SK_PMD_1000BASESX: 1684 sc->sk_pmd = IFM_1000_SX; 1685 break; 1686 case SK_PMD_1000BASELX: 1687 sc->sk_pmd = IFM_1000_LX; 1688 break; 1689 case SK_PMD_1000BASECX: 1690 sc->sk_pmd = IFM_1000_CX; 1691 break; 1692 case SK_PMD_1000BASETX: 1693 case SK_PMD_1000BASETX_ALT: 1694 sc->sk_pmd = IFM_1000_T; 1695 break; 1696 default: 1697 aprint_error("%s: unknown media type: 0x%x\n", 1698 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1699 goto fail_1; 1700 } 1701 1702 /* determine whether to name it with vpd or just make it up */ 1703 /* Marvell Yukon VPD's can freqently be bogus */ 1704 1705 switch (pa->pa_id) { 1706 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1707 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1708 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1709 case PCI_PRODUCT_3COM_3C940: 1710 case PCI_PRODUCT_DLINK_DGE530T: 1711 case PCI_PRODUCT_DLINK_DGE560T: 1712 case PCI_PRODUCT_DLINK_DGE560T_2: 1713 case PCI_PRODUCT_LINKSYS_EG1032: 1714 case PCI_PRODUCT_LINKSYS_EG1064: 1715 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1716 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1717 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1718 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1719 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1720 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1721 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1722 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1723 sc->sk_name = sc->sk_vpd_prodname; 1724 break; 1725 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1726 /* whoops yukon vpd prodname bears no resemblance to reality */ 1727 switch (sc->sk_type) { 1728 case SK_GENESIS: 1729 sc->sk_name = sc->sk_vpd_prodname; 1730 break; 1731 case SK_YUKON: 1732 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1733 break; 1734 case SK_YUKON_LITE: 1735 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1736 break; 1737 case SK_YUKON_LP: 1738 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1739 break; 1740 default: 1741 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1742 } 1743 1744 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1745 1746 if ( sc->sk_type == SK_YUKON ) { 1747 uint32_t flashaddr; 1748 uint8_t testbyte; 1749 1750 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1751 1752 /* test Flash-Address Register */ 1753 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1754 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1755 1756 if (testbyte != 0) { 1757 /* this is yukon lite Rev. A0 */ 1758 sc->sk_type = SK_YUKON_LITE; 1759 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1760 /* restore Flash-Address Register */ 1761 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1762 } 1763 } 1764 break; 1765 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1766 sc->sk_name = sc->sk_vpd_prodname; 1767 break; 1768 default: 1769 sc->sk_name = "Unknown Marvell"; 1770 } 1771 1772 1773 if ( sc->sk_type == SK_YUKON_LITE ) { 1774 switch (sc->sk_rev) { 1775 case SK_YUKON_LITE_REV_A0: 1776 revstr = "A0"; 1777 break; 1778 case SK_YUKON_LITE_REV_A1: 1779 revstr = "A1"; 1780 break; 1781 case SK_YUKON_LITE_REV_A3: 1782 revstr = "A3"; 1783 break; 1784 default: 1785 revstr = ""; 1786 } 1787 } else { 1788 revstr = ""; 1789 } 1790 1791 /* Announce the product name. */ 1792 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1793 sc->sk_name, revstr, sc->sk_rev); 1794 1795 skca.skc_port = SK_PORT_A; 1796 (void)config_found(&sc->sk_dev, &skca, skcprint); 1797 1798 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1799 skca.skc_port = SK_PORT_B; 1800 (void)config_found(&sc->sk_dev, &skca, skcprint); 1801 } 1802 1803 /* Turn on the 'driver is loaded' LED. */ 1804 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1805 1806 /* skc sysctl setup */ 1807 1808 sc->sk_int_mod = SK_IM_DEFAULT; 1809 sc->sk_int_mod_pending = 0; 1810 1811 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1812 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1813 SYSCTL_DESCR("skc per-controller controls"), 1814 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1815 CTL_EOL)) != 0) { 1816 aprint_normal("%s: couldn't create sysctl node\n", 1817 sc->sk_dev.dv_xname); 1818 goto fail_1; 1819 } 1820 1821 sk_nodenum = node->sysctl_num; 1822 1823 /* interrupt moderation time in usecs */ 1824 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1825 CTLFLAG_READWRITE, 1826 CTLTYPE_INT, "int_mod", 1827 SYSCTL_DESCR("sk interrupt moderation timer"), 1828 sk_sysctl_handler, 0, sc, 1829 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1830 CTL_EOL)) != 0) { 1831 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1832 sc->sk_dev.dv_xname); 1833 goto fail_1; 1834 } 1835 1836 return; 1837 1838 fail_1: 1839 pci_intr_disestablish(pc, sc->sk_intrhand); 1840 fail: 1841 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1842 } 1843 1844 int 1845 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1846 { 1847 struct sk_softc *sc = sc_if->sk_softc; 1848 struct sk_tx_desc *f = NULL; 1849 u_int32_t frag, cur, cnt = 0, sk_ctl; 1850 int i; 1851 struct sk_txmap_entry *entry; 1852 bus_dmamap_t txmap; 1853 1854 DPRINTFN(3, ("sk_encap\n")); 1855 1856 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1857 if (entry == NULL) { 1858 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1859 return ENOBUFS; 1860 } 1861 txmap = entry->dmamap; 1862 1863 cur = frag = *txidx; 1864 1865 #ifdef SK_DEBUG 1866 if (skdebug >= 3) 1867 sk_dump_mbuf(m_head); 1868 #endif 1869 1870 /* 1871 * Start packing the mbufs in this chain into 1872 * the fragment pointers. Stop when we run out 1873 * of fragments or hit the end of the mbuf chain. 1874 */ 1875 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1876 BUS_DMA_NOWAIT)) { 1877 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1878 return ENOBUFS; 1879 } 1880 1881 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1882 1883 /* Sync the DMA map. */ 1884 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1885 BUS_DMASYNC_PREWRITE); 1886 1887 for (i = 0; i < txmap->dm_nsegs; i++) { 1888 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1889 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1890 return ENOBUFS; 1891 } 1892 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1893 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1894 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1895 if (cnt == 0) 1896 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1897 else 1898 sk_ctl |= SK_TXCTL_OWN; 1899 f->sk_ctl = htole32(sk_ctl); 1900 cur = frag; 1901 SK_INC(frag, SK_TX_RING_CNT); 1902 cnt++; 1903 } 1904 1905 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1906 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1907 1908 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1909 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1910 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1911 1912 /* Sync descriptors before handing to chip */ 1913 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1914 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1915 1916 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1917 htole32(SK_TXCTL_OWN); 1918 1919 /* Sync first descriptor to hand it off */ 1920 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1921 1922 sc_if->sk_cdata.sk_tx_cnt += cnt; 1923 1924 #ifdef SK_DEBUG 1925 if (skdebug >= 3) { 1926 struct sk_tx_desc *desc; 1927 u_int32_t idx; 1928 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1929 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1930 sk_dump_txdesc(desc, idx); 1931 } 1932 } 1933 #endif 1934 1935 *txidx = frag; 1936 1937 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1938 1939 return 0; 1940 } 1941 1942 void 1943 sk_start(struct ifnet *ifp) 1944 { 1945 struct sk_if_softc *sc_if = ifp->if_softc; 1946 struct sk_softc *sc = sc_if->sk_softc; 1947 struct mbuf *m_head = NULL; 1948 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1949 int pkts = 0; 1950 1951 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1952 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1953 1954 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1955 IFQ_POLL(&ifp->if_snd, m_head); 1956 if (m_head == NULL) 1957 break; 1958 1959 /* 1960 * Pack the data into the transmit ring. If we 1961 * don't have room, set the OACTIVE flag and wait 1962 * for the NIC to drain the ring. 1963 */ 1964 if (sk_encap(sc_if, m_head, &idx)) { 1965 ifp->if_flags |= IFF_OACTIVE; 1966 break; 1967 } 1968 1969 /* now we are committed to transmit the packet */ 1970 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1971 pkts++; 1972 1973 /* 1974 * If there's a BPF listener, bounce a copy of this frame 1975 * to him. 1976 */ 1977 #if NBPFILTER > 0 1978 if (ifp->if_bpf) 1979 bpf_mtap(ifp->if_bpf, m_head); 1980 #endif 1981 } 1982 if (pkts == 0) 1983 return; 1984 1985 /* Transmit */ 1986 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1987 sc_if->sk_cdata.sk_tx_prod = idx; 1988 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1989 1990 /* Set a timeout in case the chip goes out to lunch. */ 1991 ifp->if_timer = 5; 1992 } 1993 } 1994 1995 1996 void 1997 sk_watchdog(struct ifnet *ifp) 1998 { 1999 struct sk_if_softc *sc_if = ifp->if_softc; 2000 2001 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 2002 (void) sk_init(ifp); 2003 } 2004 2005 void 2006 sk_shutdown(void * v) 2007 { 2008 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2009 struct sk_softc *sc = sc_if->sk_softc; 2010 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2011 2012 DPRINTFN(2, ("sk_shutdown\n")); 2013 sk_stop(ifp,1); 2014 2015 /* Turn off the 'driver is loaded' LED. */ 2016 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2017 2018 /* 2019 * Reset the GEnesis controller. Doing this should also 2020 * assert the resets on the attached XMAC(s). 2021 */ 2022 sk_reset(sc); 2023 } 2024 2025 void 2026 sk_rxeof(struct sk_if_softc *sc_if) 2027 { 2028 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2029 struct mbuf *m; 2030 struct sk_chain *cur_rx; 2031 struct sk_rx_desc *cur_desc; 2032 int i, cur, total_len = 0; 2033 u_int32_t rxstat, sk_ctl; 2034 bus_dmamap_t dmamap; 2035 2036 i = sc_if->sk_cdata.sk_rx_prod; 2037 2038 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2039 2040 for (;;) { 2041 cur = i; 2042 2043 /* Sync the descriptor */ 2044 SK_CDRXSYNC(sc_if, cur, 2045 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2046 2047 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2048 if (sk_ctl & SK_RXCTL_OWN) { 2049 /* Invalidate the descriptor -- it's not ready yet */ 2050 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2051 sc_if->sk_cdata.sk_rx_prod = i; 2052 break; 2053 } 2054 2055 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2056 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2057 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2058 2059 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2060 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2061 2062 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2063 m = cur_rx->sk_mbuf; 2064 cur_rx->sk_mbuf = NULL; 2065 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2066 2067 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2068 2069 SK_INC(i, SK_RX_RING_CNT); 2070 2071 if (rxstat & XM_RXSTAT_ERRFRAME) { 2072 ifp->if_ierrors++; 2073 sk_newbuf(sc_if, cur, m, dmamap); 2074 continue; 2075 } 2076 2077 /* 2078 * Try to allocate a new jumbo buffer. If that 2079 * fails, copy the packet to mbufs and put the 2080 * jumbo buffer back in the ring so it can be 2081 * re-used. If allocating mbufs fails, then we 2082 * have to drop the packet. 2083 */ 2084 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2085 struct mbuf *m0; 2086 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2087 total_len + ETHER_ALIGN, 0, ifp, NULL); 2088 sk_newbuf(sc_if, cur, m, dmamap); 2089 if (m0 == NULL) { 2090 aprint_error("%s: no receive buffers " 2091 "available -- packet dropped!\n", 2092 sc_if->sk_dev.dv_xname); 2093 ifp->if_ierrors++; 2094 continue; 2095 } 2096 m_adj(m0, ETHER_ALIGN); 2097 m = m0; 2098 } else { 2099 m->m_pkthdr.rcvif = ifp; 2100 m->m_pkthdr.len = m->m_len = total_len; 2101 } 2102 2103 ifp->if_ipackets++; 2104 2105 #if NBPFILTER > 0 2106 if (ifp->if_bpf) 2107 bpf_mtap(ifp->if_bpf, m); 2108 #endif 2109 /* pass it on. */ 2110 (*ifp->if_input)(ifp, m); 2111 } 2112 } 2113 2114 void 2115 sk_txeof(struct sk_if_softc *sc_if) 2116 { 2117 struct sk_softc *sc = sc_if->sk_softc; 2118 struct sk_tx_desc *cur_tx; 2119 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2120 u_int32_t idx, sk_ctl; 2121 struct sk_txmap_entry *entry; 2122 2123 DPRINTFN(3, ("sk_txeof\n")); 2124 2125 /* 2126 * Go through our tx ring and free mbufs for those 2127 * frames that have been sent. 2128 */ 2129 idx = sc_if->sk_cdata.sk_tx_cons; 2130 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2131 SK_CDTXSYNC(sc_if, idx, 1, 2132 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2133 2134 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2135 sk_ctl = le32toh(cur_tx->sk_ctl); 2136 #ifdef SK_DEBUG 2137 if (skdebug >= 3) 2138 sk_dump_txdesc(cur_tx, idx); 2139 #endif 2140 if (sk_ctl & SK_TXCTL_OWN) { 2141 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2142 break; 2143 } 2144 if (sk_ctl & SK_TXCTL_LASTFRAG) 2145 ifp->if_opackets++; 2146 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2147 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2148 2149 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2150 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2151 2152 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2153 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2154 2155 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2156 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2157 link); 2158 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2159 } 2160 sc_if->sk_cdata.sk_tx_cnt--; 2161 SK_INC(idx, SK_TX_RING_CNT); 2162 } 2163 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2164 ifp->if_timer = 0; 2165 else /* nudge chip to keep tx ring moving */ 2166 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2167 2168 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2169 ifp->if_flags &= ~IFF_OACTIVE; 2170 2171 sc_if->sk_cdata.sk_tx_cons = idx; 2172 } 2173 2174 void 2175 sk_tick(void *xsc_if) 2176 { 2177 struct sk_if_softc *sc_if = xsc_if; 2178 struct mii_data *mii = &sc_if->sk_mii; 2179 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2180 int i; 2181 2182 DPRINTFN(3, ("sk_tick\n")); 2183 2184 if (!(ifp->if_flags & IFF_UP)) 2185 return; 2186 2187 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2188 sk_intr_bcom(sc_if); 2189 return; 2190 } 2191 2192 /* 2193 * According to SysKonnect, the correct way to verify that 2194 * the link has come back up is to poll bit 0 of the GPIO 2195 * register three times. This pin has the signal from the 2196 * link sync pin connected to it; if we read the same link 2197 * state 3 times in a row, we know the link is up. 2198 */ 2199 for (i = 0; i < 3; i++) { 2200 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2201 break; 2202 } 2203 2204 if (i != 3) { 2205 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2206 return; 2207 } 2208 2209 /* Turn the GP0 interrupt back on. */ 2210 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2211 SK_XM_READ_2(sc_if, XM_ISR); 2212 mii_tick(mii); 2213 mii_pollstat(mii); 2214 callout_stop(&sc_if->sk_tick_ch); 2215 } 2216 2217 void 2218 sk_intr_bcom(struct sk_if_softc *sc_if) 2219 { 2220 struct mii_data *mii = &sc_if->sk_mii; 2221 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2222 int status; 2223 2224 2225 DPRINTFN(3, ("sk_intr_bcom\n")); 2226 2227 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2228 2229 /* 2230 * Read the PHY interrupt register to make sure 2231 * we clear any pending interrupts. 2232 */ 2233 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2234 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2235 2236 if (!(ifp->if_flags & IFF_RUNNING)) { 2237 sk_init_xmac(sc_if); 2238 return; 2239 } 2240 2241 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2242 int lstat; 2243 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2244 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2245 2246 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2247 mii_mediachg(mii); 2248 /* Turn off the link LED. */ 2249 SK_IF_WRITE_1(sc_if, 0, 2250 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2251 sc_if->sk_link = 0; 2252 } else if (status & BRGPHY_ISR_LNK_CHG) { 2253 sk_xmac_miibus_writereg((struct device *)sc_if, 2254 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2255 mii_tick(mii); 2256 sc_if->sk_link = 1; 2257 /* Turn on the link LED. */ 2258 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2259 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2260 SK_LINKLED_BLINK_OFF); 2261 mii_pollstat(mii); 2262 } else { 2263 mii_tick(mii); 2264 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2265 } 2266 } 2267 2268 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2269 } 2270 2271 void 2272 sk_intr_xmac(struct sk_if_softc *sc_if) 2273 { 2274 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2275 2276 DPRINTFN(3, ("sk_intr_xmac\n")); 2277 2278 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2279 if (status & XM_ISR_GP0_SET) { 2280 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2281 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2282 } 2283 2284 if (status & XM_ISR_AUTONEG_DONE) { 2285 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2286 } 2287 } 2288 2289 if (status & XM_IMR_TX_UNDERRUN) 2290 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2291 2292 if (status & XM_IMR_RX_OVERRUN) 2293 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2294 } 2295 2296 void 2297 sk_intr_yukon(struct sk_if_softc *sc_if) 2298 { 2299 int status; 2300 2301 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2302 2303 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2304 } 2305 2306 int 2307 sk_intr(void *xsc) 2308 { 2309 struct sk_softc *sc = xsc; 2310 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2311 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2312 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2313 u_int32_t status; 2314 int claimed = 0; 2315 2316 if (sc_if0 != NULL) 2317 ifp0 = &sc_if0->sk_ethercom.ec_if; 2318 if (sc_if1 != NULL) 2319 ifp1 = &sc_if1->sk_ethercom.ec_if; 2320 2321 for (;;) { 2322 status = CSR_READ_4(sc, SK_ISSR); 2323 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2324 2325 if (!(status & sc->sk_intrmask)) 2326 break; 2327 2328 claimed = 1; 2329 2330 /* Handle receive interrupts first. */ 2331 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2332 sk_rxeof(sc_if0); 2333 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2334 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2335 } 2336 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2337 sk_rxeof(sc_if1); 2338 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2339 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2340 } 2341 2342 /* Then transmit interrupts. */ 2343 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2344 sk_txeof(sc_if0); 2345 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2346 SK_TXBMU_CLR_IRQ_EOF); 2347 } 2348 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2349 sk_txeof(sc_if1); 2350 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2351 SK_TXBMU_CLR_IRQ_EOF); 2352 } 2353 2354 /* Then MAC interrupts. */ 2355 if (sc_if0 && (status & SK_ISR_MAC1) && 2356 (ifp0->if_flags & IFF_RUNNING)) { 2357 if (sc->sk_type == SK_GENESIS) 2358 sk_intr_xmac(sc_if0); 2359 else 2360 sk_intr_yukon(sc_if0); 2361 } 2362 2363 if (sc_if1 && (status & SK_ISR_MAC2) && 2364 (ifp1->if_flags & IFF_RUNNING)) { 2365 if (sc->sk_type == SK_GENESIS) 2366 sk_intr_xmac(sc_if1); 2367 else 2368 sk_intr_yukon(sc_if1); 2369 2370 } 2371 2372 if (status & SK_ISR_EXTERNAL_REG) { 2373 if (sc_if0 != NULL && 2374 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2375 sk_intr_bcom(sc_if0); 2376 2377 if (sc_if1 != NULL && 2378 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2379 sk_intr_bcom(sc_if1); 2380 } 2381 } 2382 2383 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2384 2385 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2386 sk_start(ifp0); 2387 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2388 sk_start(ifp1); 2389 2390 #if NRND > 0 2391 if (RND_ENABLED(&sc->rnd_source)) 2392 rnd_add_uint32(&sc->rnd_source, status); 2393 #endif 2394 2395 if (sc->sk_int_mod_pending) 2396 sk_update_int_mod(sc); 2397 2398 return claimed; 2399 } 2400 2401 void 2402 sk_init_xmac(struct sk_if_softc *sc_if) 2403 { 2404 struct sk_softc *sc = sc_if->sk_softc; 2405 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2406 static const struct sk_bcom_hack bhack[] = { 2407 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2408 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2409 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2410 { 0, 0 } }; 2411 2412 DPRINTFN(1, ("sk_init_xmac\n")); 2413 2414 /* Unreset the XMAC. */ 2415 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2416 DELAY(1000); 2417 2418 /* Reset the XMAC's internal state. */ 2419 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2420 2421 /* Save the XMAC II revision */ 2422 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2423 2424 /* 2425 * Perform additional initialization for external PHYs, 2426 * namely for the 1000baseTX cards that use the XMAC's 2427 * GMII mode. 2428 */ 2429 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2430 int i = 0; 2431 u_int32_t val; 2432 2433 /* Take PHY out of reset. */ 2434 val = sk_win_read_4(sc, SK_GPIO); 2435 if (sc_if->sk_port == SK_PORT_A) 2436 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2437 else 2438 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2439 sk_win_write_4(sc, SK_GPIO, val); 2440 2441 /* Enable GMII mode on the XMAC. */ 2442 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2443 2444 sk_xmac_miibus_writereg((struct device *)sc_if, 2445 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2446 DELAY(10000); 2447 sk_xmac_miibus_writereg((struct device *)sc_if, 2448 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2449 2450 /* 2451 * Early versions of the BCM5400 apparently have 2452 * a bug that requires them to have their reserved 2453 * registers initialized to some magic values. I don't 2454 * know what the numbers do, I'm just the messenger. 2455 */ 2456 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2457 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2458 while (bhack[i].reg) { 2459 sk_xmac_miibus_writereg((struct device *)sc_if, 2460 SK_PHYADDR_BCOM, bhack[i].reg, 2461 bhack[i].val); 2462 i++; 2463 } 2464 } 2465 } 2466 2467 /* Set station address */ 2468 SK_XM_WRITE_2(sc_if, XM_PAR0, 2469 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2470 SK_XM_WRITE_2(sc_if, XM_PAR1, 2471 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2472 SK_XM_WRITE_2(sc_if, XM_PAR2, 2473 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2474 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2475 2476 if (ifp->if_flags & IFF_PROMISC) 2477 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2478 else 2479 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2480 2481 if (ifp->if_flags & IFF_BROADCAST) 2482 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2483 else 2484 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2485 2486 /* We don't need the FCS appended to the packet. */ 2487 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2488 2489 /* We want short frames padded to 60 bytes. */ 2490 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2491 2492 /* 2493 * Enable the reception of all error frames. This is is 2494 * a necessary evil due to the design of the XMAC. The 2495 * XMAC's receive FIFO is only 8K in size, however jumbo 2496 * frames can be up to 9000 bytes in length. When bad 2497 * frame filtering is enabled, the XMAC's RX FIFO operates 2498 * in 'store and forward' mode. For this to work, the 2499 * entire frame has to fit into the FIFO, but that means 2500 * that jumbo frames larger than 8192 bytes will be 2501 * truncated. Disabling all bad frame filtering causes 2502 * the RX FIFO to operate in streaming mode, in which 2503 * case the XMAC will start transfering frames out of the 2504 * RX FIFO as soon as the FIFO threshold is reached. 2505 */ 2506 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2507 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2508 XM_MODE_RX_INRANGELEN); 2509 2510 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2511 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2512 else 2513 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2514 2515 /* 2516 * Bump up the transmit threshold. This helps hold off transmit 2517 * underruns when we're blasting traffic from both ports at once. 2518 */ 2519 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2520 2521 /* Set multicast filter */ 2522 sk_setmulti(sc_if); 2523 2524 /* Clear and enable interrupts */ 2525 SK_XM_READ_2(sc_if, XM_ISR); 2526 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2527 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2528 else 2529 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2530 2531 /* Configure MAC arbiter */ 2532 switch (sc_if->sk_xmac_rev) { 2533 case XM_XMAC_REV_B2: 2534 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2535 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2536 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2537 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2538 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2539 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2540 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2541 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2542 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2543 break; 2544 case XM_XMAC_REV_C1: 2545 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2546 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2547 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2548 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2549 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2550 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2551 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2552 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2553 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2554 break; 2555 default: 2556 break; 2557 } 2558 sk_win_write_2(sc, SK_MACARB_CTL, 2559 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2560 2561 sc_if->sk_link = 1; 2562 } 2563 2564 void sk_init_yukon(struct sk_if_softc *sc_if) 2565 { 2566 u_int32_t /*mac, */phy; 2567 u_int16_t reg; 2568 struct sk_softc *sc; 2569 int i; 2570 2571 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2572 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2573 2574 sc = sc_if->sk_softc; 2575 if (sc->sk_type == SK_YUKON_LITE && 2576 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2577 /* Take PHY out of reset. */ 2578 sk_win_write_4(sc, SK_GPIO, 2579 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2580 } 2581 2582 2583 /* GMAC and GPHY Reset */ 2584 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2585 2586 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2587 2588 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2589 DELAY(1000); 2590 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2591 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2592 DELAY(1000); 2593 2594 2595 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2596 2597 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2598 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2599 2600 switch (sc_if->sk_softc->sk_pmd) { 2601 case IFM_1000_SX: 2602 case IFM_1000_LX: 2603 phy |= SK_GPHY_FIBER; 2604 break; 2605 2606 case IFM_1000_CX: 2607 case IFM_1000_T: 2608 phy |= SK_GPHY_COPPER; 2609 break; 2610 } 2611 2612 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2613 2614 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2615 DELAY(1000); 2616 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2617 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2618 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2619 2620 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2621 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2622 2623 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2624 2625 /* unused read of the interrupt source register */ 2626 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2627 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2628 2629 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2630 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2631 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2632 2633 /* MIB Counter Clear Mode set */ 2634 reg |= YU_PAR_MIB_CLR; 2635 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2636 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2637 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2638 2639 /* MIB Counter Clear Mode clear */ 2640 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2641 reg &= ~YU_PAR_MIB_CLR; 2642 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2643 2644 /* receive control reg */ 2645 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2646 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2647 YU_RCR_CRCR); 2648 2649 /* transmit parameter register */ 2650 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2651 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2652 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2653 2654 /* serial mode register */ 2655 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2656 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2657 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2658 YU_SMR_IPG_DATA(0x1e)); 2659 2660 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2661 /* Setup Yukon's address */ 2662 for (i = 0; i < 3; i++) { 2663 /* Write Source Address 1 (unicast filter) */ 2664 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2665 sc_if->sk_enaddr[i * 2] | 2666 sc_if->sk_enaddr[i * 2 + 1] << 8); 2667 } 2668 2669 for (i = 0; i < 3; i++) { 2670 reg = sk_win_read_2(sc_if->sk_softc, 2671 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2672 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2673 } 2674 2675 /* Set multicast filter */ 2676 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2677 sk_setmulti(sc_if); 2678 2679 /* enable interrupt mask for counter overflows */ 2680 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2681 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2682 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2683 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2684 2685 /* Configure RX MAC FIFO */ 2686 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2687 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2688 2689 /* Configure TX MAC FIFO */ 2690 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2691 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2692 2693 DPRINTFN(6, ("sk_init_yukon: end\n")); 2694 } 2695 2696 /* 2697 * Note that to properly initialize any part of the GEnesis chip, 2698 * you first have to take it out of reset mode. 2699 */ 2700 int 2701 sk_init(struct ifnet *ifp) 2702 { 2703 struct sk_if_softc *sc_if = ifp->if_softc; 2704 struct sk_softc *sc = sc_if->sk_softc; 2705 struct mii_data *mii = &sc_if->sk_mii; 2706 int s; 2707 u_int32_t imr, sk_imtimer_ticks; 2708 2709 DPRINTFN(1, ("sk_init\n")); 2710 2711 s = splnet(); 2712 2713 if (ifp->if_flags & IFF_RUNNING) { 2714 splx(s); 2715 return 0; 2716 } 2717 2718 /* Cancel pending I/O and free all RX/TX buffers. */ 2719 sk_stop(ifp,0); 2720 2721 if (sc->sk_type == SK_GENESIS) { 2722 /* Configure LINK_SYNC LED */ 2723 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2724 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2725 SK_LINKLED_LINKSYNC_ON); 2726 2727 /* Configure RX LED */ 2728 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2729 SK_RXLEDCTL_COUNTER_START); 2730 2731 /* Configure TX LED */ 2732 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2733 SK_TXLEDCTL_COUNTER_START); 2734 } 2735 2736 /* Configure I2C registers */ 2737 2738 /* Configure XMAC(s) */ 2739 switch (sc->sk_type) { 2740 case SK_GENESIS: 2741 sk_init_xmac(sc_if); 2742 break; 2743 case SK_YUKON: 2744 case SK_YUKON_LITE: 2745 case SK_YUKON_LP: 2746 sk_init_yukon(sc_if); 2747 break; 2748 } 2749 mii_mediachg(mii); 2750 2751 if (sc->sk_type == SK_GENESIS) { 2752 /* Configure MAC FIFOs */ 2753 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2754 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2755 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2756 2757 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2758 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2759 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2760 } 2761 2762 /* Configure transmit arbiter(s) */ 2763 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2764 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2765 2766 /* Configure RAMbuffers */ 2767 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2768 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2769 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2770 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2771 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2772 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2773 2774 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2775 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2776 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2777 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2778 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2779 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2780 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2781 2782 /* Configure BMUs */ 2783 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2784 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2785 SK_RX_RING_ADDR(sc_if, 0)); 2786 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2787 2788 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2789 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2790 SK_TX_RING_ADDR(sc_if, 0)); 2791 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2792 2793 /* Init descriptors */ 2794 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2795 aprint_error("%s: initialization failed: no " 2796 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2797 sk_stop(ifp,0); 2798 splx(s); 2799 return ENOBUFS; 2800 } 2801 2802 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2803 aprint_error("%s: initialization failed: no " 2804 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2805 sk_stop(ifp,0); 2806 splx(s); 2807 return ENOBUFS; 2808 } 2809 2810 /* Set interrupt moderation if changed via sysctl. */ 2811 switch (sc->sk_type) { 2812 case SK_GENESIS: 2813 sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2814 break; 2815 case SK_YUKON_EC: 2816 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2817 break; 2818 default: 2819 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2820 } 2821 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2822 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2823 sk_win_write_4(sc, SK_IMTIMERINIT, 2824 SK_IM_USECS(sc->sk_int_mod)); 2825 aprint_verbose("%s: interrupt moderation is %d us\n", 2826 sc->sk_dev.dv_xname, sc->sk_int_mod); 2827 } 2828 2829 /* Configure interrupt handling */ 2830 CSR_READ_4(sc, SK_ISSR); 2831 if (sc_if->sk_port == SK_PORT_A) 2832 sc->sk_intrmask |= SK_INTRS1; 2833 else 2834 sc->sk_intrmask |= SK_INTRS2; 2835 2836 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2837 2838 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2839 2840 /* Start BMUs. */ 2841 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2842 2843 if (sc->sk_type == SK_GENESIS) { 2844 /* Enable XMACs TX and RX state machines */ 2845 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2846 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2847 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2848 } 2849 2850 if (SK_YUKON_FAMILY(sc->sk_type)) { 2851 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2852 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2853 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2854 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2855 } 2856 2857 2858 ifp->if_flags |= IFF_RUNNING; 2859 ifp->if_flags &= ~IFF_OACTIVE; 2860 2861 splx(s); 2862 return 0; 2863 } 2864 2865 void 2866 sk_stop(struct ifnet *ifp, int disable) 2867 { 2868 struct sk_if_softc *sc_if = ifp->if_softc; 2869 struct sk_softc *sc = sc_if->sk_softc; 2870 int i; 2871 2872 DPRINTFN(1, ("sk_stop\n")); 2873 2874 callout_stop(&sc_if->sk_tick_ch); 2875 2876 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2877 u_int32_t val; 2878 2879 /* Put PHY back into reset. */ 2880 val = sk_win_read_4(sc, SK_GPIO); 2881 if (sc_if->sk_port == SK_PORT_A) { 2882 val |= SK_GPIO_DIR0; 2883 val &= ~SK_GPIO_DAT0; 2884 } else { 2885 val |= SK_GPIO_DIR2; 2886 val &= ~SK_GPIO_DAT2; 2887 } 2888 sk_win_write_4(sc, SK_GPIO, val); 2889 } 2890 2891 /* Turn off various components of this interface. */ 2892 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2893 switch (sc->sk_type) { 2894 case SK_GENESIS: 2895 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2896 SK_TXMACCTL_XMAC_RESET); 2897 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2898 break; 2899 case SK_YUKON: 2900 case SK_YUKON_LITE: 2901 case SK_YUKON_LP: 2902 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2903 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2904 break; 2905 } 2906 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2907 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2908 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2909 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2910 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2911 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2912 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2913 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2914 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2915 2916 /* Disable interrupts */ 2917 if (sc_if->sk_port == SK_PORT_A) 2918 sc->sk_intrmask &= ~SK_INTRS1; 2919 else 2920 sc->sk_intrmask &= ~SK_INTRS2; 2921 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2922 2923 SK_XM_READ_2(sc_if, XM_ISR); 2924 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2925 2926 /* Free RX and TX mbufs still in the queues. */ 2927 for (i = 0; i < SK_RX_RING_CNT; i++) { 2928 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2929 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2930 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2931 } 2932 } 2933 2934 for (i = 0; i < SK_TX_RING_CNT; i++) { 2935 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2936 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2937 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2938 } 2939 } 2940 2941 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2942 } 2943 2944 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2945 2946 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2947 2948 #ifdef SK_DEBUG 2949 void 2950 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2951 { 2952 #define DESC_PRINT(X) \ 2953 if (X) \ 2954 printf("txdesc[%d]." #X "=%#x\n", \ 2955 idx, X); 2956 2957 DESC_PRINT(le32toh(desc->sk_ctl)); 2958 DESC_PRINT(le32toh(desc->sk_next)); 2959 DESC_PRINT(le32toh(desc->sk_data_lo)); 2960 DESC_PRINT(le32toh(desc->sk_data_hi)); 2961 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2962 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2963 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2964 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2965 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2966 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2967 #undef PRINT 2968 } 2969 2970 void 2971 sk_dump_bytes(const char *data, int len) 2972 { 2973 int c, i, j; 2974 2975 for (i = 0; i < len; i += 16) { 2976 printf("%08x ", i); 2977 c = len - i; 2978 if (c > 16) c = 16; 2979 2980 for (j = 0; j < c; j++) { 2981 printf("%02x ", data[i + j] & 0xff); 2982 if ((j & 0xf) == 7 && j > 0) 2983 printf(" "); 2984 } 2985 2986 for (; j < 16; j++) 2987 printf(" "); 2988 printf(" "); 2989 2990 for (j = 0; j < c; j++) { 2991 int ch = data[i + j] & 0xff; 2992 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2993 } 2994 2995 printf("\n"); 2996 2997 if (c < 16) 2998 break; 2999 } 3000 } 3001 3002 void 3003 sk_dump_mbuf(struct mbuf *m) 3004 { 3005 int count = m->m_pkthdr.len; 3006 3007 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3008 3009 while (count > 0 && m) { 3010 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3011 m, m->m_data, m->m_len); 3012 sk_dump_bytes(mtod(m, char *), m->m_len); 3013 3014 count -= m->m_len; 3015 m = m->m_next; 3016 } 3017 } 3018 #endif 3019 3020 static int 3021 sk_sysctl_handler(SYSCTLFN_ARGS) 3022 { 3023 int error, t; 3024 struct sysctlnode node; 3025 struct sk_softc *sc; 3026 3027 node = *rnode; 3028 sc = node.sysctl_data; 3029 t = sc->sk_int_mod; 3030 node.sysctl_data = &t; 3031 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3032 if (error || newp == NULL) 3033 return error; 3034 3035 if (t < SK_IM_MIN || t > SK_IM_MAX) 3036 return EINVAL; 3037 3038 /* update the softc with sysctl-changed value, and mark 3039 for hardware update */ 3040 sc->sk_int_mod = t; 3041 sc->sk_int_mod_pending = 1; 3042 return 0; 3043 } 3044 3045 /* 3046 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3047 * set up in skc_attach() 3048 */ 3049 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3050 { 3051 int rc; 3052 const struct sysctlnode *node; 3053 3054 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3055 0, CTLTYPE_NODE, "hw", NULL, 3056 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3057 goto err; 3058 } 3059 3060 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3061 0, CTLTYPE_NODE, "sk", 3062 SYSCTL_DESCR("sk interface controls"), 3063 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3064 goto err; 3065 } 3066 3067 sk_root_num = node->sysctl_num; 3068 return; 3069 3070 err: 3071 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3072 } 3073
Indexes created Tue Sep 23 07:09:52 GMT 2025