if_sk.c revision 1.35.2.1.2.1
1 /* $NetBSD: if_sk.c,v 1.35.2.1.2.1 2007/09/03 07:04:31 wrstuden Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 #include "rnd.h" 126 127 #include <sys/param.h> 128 #include <sys/systm.h> 129 #include <sys/sockio.h> 130 #include <sys/mbuf.h> 131 #include <sys/malloc.h> 132 #include <sys/kernel.h> 133 #include <sys/socket.h> 134 #include <sys/device.h> 135 #include <sys/queue.h> 136 #include <sys/callout.h> 137 #include <sys/sysctl.h> 138 #include <sys/endian.h> 139 140 #include <net/if.h> 141 #include <net/if_dl.h> 142 #include <net/if_types.h> 143 144 #include <net/if_media.h> 145 146 #if NBPFILTER > 0 147 #include <net/bpf.h> 148 #endif 149 #if NRND > 0 150 #include <sys/rnd.h> 151 #endif 152 153 #include <dev/mii/mii.h> 154 #include <dev/mii/miivar.h> 155 #include <dev/mii/brgphyreg.h> 156 157 #include <dev/pci/pcireg.h> 158 #include <dev/pci/pcivar.h> 159 #include <dev/pci/pcidevs.h> 160 161 /* #define SK_USEIOSPACE */ 162 163 #include <dev/pci/if_skreg.h> 164 #include <dev/pci/if_skvar.h> 165 166 int skc_probe(struct device *, struct cfdata *, void *); 167 void skc_attach(struct device *, struct device *self, void *aux); 168 int sk_probe(struct device *, struct cfdata *, void *); 169 void sk_attach(struct device *, struct device *self, void *aux); 170 int skcprint(void *, const char *); 171 int sk_intr(void *); 172 void sk_intr_bcom(struct sk_if_softc *); 173 void sk_intr_xmac(struct sk_if_softc *); 174 void sk_intr_yukon(struct sk_if_softc *); 175 void sk_rxeof(struct sk_if_softc *); 176 void sk_txeof(struct sk_if_softc *); 177 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 178 void sk_start(struct ifnet *); 179 int sk_ioctl(struct ifnet *, u_long, caddr_t); 180 int sk_init(struct ifnet *); 181 void sk_init_xmac(struct sk_if_softc *); 182 void sk_init_yukon(struct sk_if_softc *); 183 void sk_stop(struct ifnet *, int); 184 void sk_watchdog(struct ifnet *); 185 void sk_shutdown(void *); 186 int sk_ifmedia_upd(struct ifnet *); 187 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 188 void sk_reset(struct sk_softc *); 189 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 190 int sk_alloc_jumbo_mem(struct sk_if_softc *); 191 void sk_free_jumbo_mem(struct sk_if_softc *); 192 void *sk_jalloc(struct sk_if_softc *); 193 void sk_jfree(struct mbuf *, caddr_t, size_t, void *); 194 int sk_init_rx_ring(struct sk_if_softc *); 195 int sk_init_tx_ring(struct sk_if_softc *); 196 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 197 void sk_vpd_read_res(struct sk_softc *, 198 struct vpd_res *, int); 199 void sk_vpd_read(struct sk_softc *); 200 201 void sk_update_int_mod(struct sk_softc *); 202 203 int sk_xmac_miibus_readreg(struct device *, int, int); 204 void sk_xmac_miibus_writereg(struct device *, int, int, int); 205 void sk_xmac_miibus_statchg(struct device *); 206 207 int sk_marv_miibus_readreg(struct device *, int, int); 208 void sk_marv_miibus_writereg(struct device *, int, int, int); 209 void sk_marv_miibus_statchg(struct device *); 210 211 u_int32_t sk_xmac_hash(caddr_t); 212 u_int32_t sk_yukon_hash(caddr_t); 213 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 214 void sk_setmulti(struct sk_if_softc *); 215 void sk_tick(void *); 216 217 /* #define SK_DEBUG 2 */ 218 #ifdef SK_DEBUG 219 #define DPRINTF(x) if (skdebug) printf x 220 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 221 int skdebug = SK_DEBUG; 222 223 void sk_dump_txdesc(struct sk_tx_desc *, int); 224 void sk_dump_mbuf(struct mbuf *); 225 void sk_dump_bytes(const char *, int); 226 #else 227 #define DPRINTF(x) 228 #define DPRINTFN(n,x) 229 #endif 230 231 static int sk_sysctl_handler(SYSCTLFN_PROTO); 232 static int sk_root_num; 233 234 /* supported device vendors */ 235 static const struct sk_product { 236 pci_vendor_id_t sk_vendor; 237 pci_product_id_t sk_product; 238 } sk_products[] = { 239 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 240 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 241 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T, }, 242 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 243 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 244 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 245 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 246 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 247 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 248 { 0, 0, } 249 }; 250 251 #define SK_LINKSYS_EG1032_SUBID 0x00151737 252 253 static inline u_int32_t 254 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 255 { 256 #ifdef SK_USEIOSPACE 257 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 258 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 259 #else 260 return CSR_READ_4(sc, reg); 261 #endif 262 } 263 264 static inline u_int16_t 265 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 266 { 267 #ifdef SK_USEIOSPACE 268 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 269 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 270 #else 271 return CSR_READ_2(sc, reg); 272 #endif 273 } 274 275 static inline u_int8_t 276 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 277 { 278 #ifdef SK_USEIOSPACE 279 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 280 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 281 #else 282 return CSR_READ_1(sc, reg); 283 #endif 284 } 285 286 static inline void 287 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 288 { 289 #ifdef SK_USEIOSPACE 290 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 291 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 292 #else 293 CSR_WRITE_4(sc, reg, x); 294 #endif 295 } 296 297 static inline void 298 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 299 { 300 #ifdef SK_USEIOSPACE 301 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 302 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 303 #else 304 CSR_WRITE_2(sc, reg, x); 305 #endif 306 } 307 308 static inline void 309 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 310 { 311 #ifdef SK_USEIOSPACE 312 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 313 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 314 #else 315 CSR_WRITE_1(sc, reg, x); 316 #endif 317 } 318 319 /* 320 * The VPD EEPROM contains Vital Product Data, as suggested in 321 * the PCI 2.1 specification. The VPD data is separared into areas 322 * denoted by resource IDs. The SysKonnect VPD contains an ID string 323 * resource (the name of the adapter), a read-only area resource 324 * containing various key/data fields and a read/write area which 325 * can be used to store asset management information or log messages. 326 * We read the ID string and read-only into buffers attached to 327 * the controller softc structure for later use. At the moment, 328 * we only use the ID string during sk_attach(). 329 */ 330 u_int8_t 331 sk_vpd_readbyte(struct sk_softc *sc, int addr) 332 { 333 int i; 334 335 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 336 for (i = 0; i < SK_TIMEOUT; i++) { 337 DELAY(1); 338 if (sk_win_read_2(sc, 339 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 340 break; 341 } 342 343 if (i == SK_TIMEOUT) 344 return 0; 345 346 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 347 } 348 349 void 350 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 351 { 352 int i; 353 u_int8_t *ptr; 354 355 ptr = (u_int8_t *)res; 356 for (i = 0; i < sizeof(struct vpd_res); i++) 357 ptr[i] = sk_vpd_readbyte(sc, i + addr); 358 } 359 360 void 361 sk_vpd_read(struct sk_softc *sc) 362 { 363 int pos = 0, i; 364 struct vpd_res res; 365 366 if (sc->sk_vpd_prodname != NULL) 367 free(sc->sk_vpd_prodname, M_DEVBUF); 368 if (sc->sk_vpd_readonly != NULL) 369 free(sc->sk_vpd_readonly, M_DEVBUF); 370 sc->sk_vpd_prodname = NULL; 371 sc->sk_vpd_readonly = NULL; 372 373 sk_vpd_read_res(sc, &res, pos); 374 375 if (res.vr_id != VPD_RES_ID) { 376 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 377 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 378 return; 379 } 380 381 pos += sizeof(res); 382 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 383 if (sc->sk_vpd_prodname == NULL) 384 panic("sk_vpd_read"); 385 for (i = 0; i < res.vr_len; i++) 386 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 387 sc->sk_vpd_prodname[i] = '\0'; 388 pos += i; 389 390 sk_vpd_read_res(sc, &res, pos); 391 392 if (res.vr_id != VPD_RES_READ) { 393 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 394 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 395 return; 396 } 397 398 pos += sizeof(res); 399 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 400 if (sc->sk_vpd_readonly == NULL) 401 panic("sk_vpd_read"); 402 for (i = 0; i < res.vr_len ; i++) 403 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 404 } 405 406 int 407 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 408 { 409 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 410 int i; 411 412 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 413 414 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 415 return 0; 416 417 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 418 SK_XM_READ_2(sc_if, XM_PHY_DATA); 419 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 420 for (i = 0; i < SK_TIMEOUT; i++) { 421 DELAY(1); 422 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 423 XM_MMUCMD_PHYDATARDY) 424 break; 425 } 426 427 if (i == SK_TIMEOUT) { 428 aprint_error("%s: phy failed to come ready\n", 429 sc_if->sk_dev.dv_xname); 430 return 0; 431 } 432 } 433 DELAY(1); 434 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 435 } 436 437 void 438 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 439 { 440 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 441 int i; 442 443 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 444 445 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 446 for (i = 0; i < SK_TIMEOUT; i++) { 447 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 448 break; 449 } 450 451 if (i == SK_TIMEOUT) { 452 aprint_error("%s: phy failed to come ready\n", 453 sc_if->sk_dev.dv_xname); 454 return; 455 } 456 457 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 458 for (i = 0; i < SK_TIMEOUT; i++) { 459 DELAY(1); 460 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 461 break; 462 } 463 464 if (i == SK_TIMEOUT) 465 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 466 } 467 468 void 469 sk_xmac_miibus_statchg(struct device *dev) 470 { 471 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 472 struct mii_data *mii = &sc_if->sk_mii; 473 474 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 475 476 /* 477 * If this is a GMII PHY, manually set the XMAC's 478 * duplex mode accordingly. 479 */ 480 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 481 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 482 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 483 else 484 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 485 } 486 } 487 488 int 489 sk_marv_miibus_readreg(struct device *dev, int phy, int reg) 490 { 491 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 492 u_int16_t val; 493 int i; 494 495 if (phy != 0 || 496 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 497 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 498 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 499 phy, reg)); 500 return 0; 501 } 502 503 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 504 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 505 506 for (i = 0; i < SK_TIMEOUT; i++) { 507 DELAY(1); 508 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 509 if (val & YU_SMICR_READ_VALID) 510 break; 511 } 512 513 if (i == SK_TIMEOUT) { 514 aprint_error("%s: phy failed to come ready\n", 515 sc_if->sk_dev.dv_xname); 516 return 0; 517 } 518 519 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 520 SK_TIMEOUT)); 521 522 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 523 524 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 525 phy, reg, val)); 526 527 return val; 528 } 529 530 void 531 sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 532 { 533 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 534 int i; 535 536 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 537 phy, reg, val)); 538 539 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 540 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 541 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 542 543 for (i = 0; i < SK_TIMEOUT; i++) { 544 DELAY(1); 545 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 546 break; 547 } 548 549 if (i == SK_TIMEOUT) 550 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 551 } 552 553 void 554 sk_marv_miibus_statchg(struct device *dev) 555 { 556 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 557 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 558 } 559 560 #define SK_HASH_BITS 6 561 562 u_int32_t 563 sk_xmac_hash(caddr_t addr) 564 { 565 u_int32_t crc; 566 567 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 568 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 569 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 570 return crc; 571 } 572 573 u_int32_t 574 sk_yukon_hash(caddr_t addr) 575 { 576 u_int32_t crc; 577 578 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 579 crc &= ((1 << SK_HASH_BITS) - 1); 580 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 581 return crc; 582 } 583 584 void 585 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 586 { 587 int base = XM_RXFILT_ENTRY(slot); 588 589 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 590 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 591 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 592 } 593 594 void 595 sk_setmulti(struct sk_if_softc *sc_if) 596 { 597 struct sk_softc *sc = sc_if->sk_softc; 598 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 599 u_int32_t hashes[2] = { 0, 0 }; 600 int h = 0, i; 601 struct ethercom *ec = &sc_if->sk_ethercom; 602 struct ether_multi *enm; 603 struct ether_multistep step; 604 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 605 606 /* First, zot all the existing filters. */ 607 switch (sc->sk_type) { 608 case SK_GENESIS: 609 for (i = 1; i < XM_RXFILT_MAX; i++) 610 sk_setfilt(sc_if, (caddr_t)&dummy, i); 611 612 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 613 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 614 break; 615 case SK_YUKON: 616 case SK_YUKON_LITE: 617 case SK_YUKON_LP: 618 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 619 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 620 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 621 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 622 break; 623 } 624 625 /* Now program new ones. */ 626 allmulti: 627 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 628 hashes[0] = 0xFFFFFFFF; 629 hashes[1] = 0xFFFFFFFF; 630 } else { 631 i = 1; 632 /* First find the tail of the list. */ 633 ETHER_FIRST_MULTI(step, ec, enm); 634 while (enm != NULL) { 635 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 636 ETHER_ADDR_LEN)) { 637 ifp->if_flags |= IFF_ALLMULTI; 638 goto allmulti; 639 } 640 DPRINTFN(2,("multicast address %s\n", 641 ether_sprintf(enm->enm_addrlo))); 642 /* 643 * Program the first XM_RXFILT_MAX multicast groups 644 * into the perfect filter. For all others, 645 * use the hash table. 646 */ 647 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 648 sk_setfilt(sc_if, enm->enm_addrlo, i); 649 i++; 650 } 651 else { 652 switch (sc->sk_type) { 653 case SK_GENESIS: 654 h = sk_xmac_hash(enm->enm_addrlo); 655 break; 656 case SK_YUKON: 657 case SK_YUKON_LITE: 658 case SK_YUKON_LP: 659 h = sk_yukon_hash(enm->enm_addrlo); 660 break; 661 } 662 if (h < 32) 663 hashes[0] |= (1 << h); 664 else 665 hashes[1] |= (1 << (h - 32)); 666 } 667 668 ETHER_NEXT_MULTI(step, enm); 669 } 670 } 671 672 switch (sc->sk_type) { 673 case SK_GENESIS: 674 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 675 XM_MODE_RX_USE_PERFECT); 676 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 677 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 678 break; 679 case SK_YUKON: 680 case SK_YUKON_LITE: 681 case SK_YUKON_LP: 682 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 683 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 684 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 685 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 686 break; 687 } 688 } 689 690 int 691 sk_init_rx_ring(struct sk_if_softc *sc_if) 692 { 693 struct sk_chain_data *cd = &sc_if->sk_cdata; 694 struct sk_ring_data *rd = sc_if->sk_rdata; 695 int i; 696 697 bzero((char *)rd->sk_rx_ring, 698 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 699 700 for (i = 0; i < SK_RX_RING_CNT; i++) { 701 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 702 if (i == (SK_RX_RING_CNT - 1)) { 703 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 704 rd->sk_rx_ring[i].sk_next = 705 htole32(SK_RX_RING_ADDR(sc_if, 0)); 706 } else { 707 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 708 rd->sk_rx_ring[i].sk_next = 709 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 710 } 711 } 712 713 for (i = 0; i < SK_RX_RING_CNT; i++) { 714 if (sk_newbuf(sc_if, i, NULL, 715 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 716 aprint_error("%s: failed alloc of %dth mbuf\n", 717 sc_if->sk_dev.dv_xname, i); 718 return ENOBUFS; 719 } 720 } 721 sc_if->sk_cdata.sk_rx_prod = 0; 722 sc_if->sk_cdata.sk_rx_cons = 0; 723 724 return 0; 725 } 726 727 int 728 sk_init_tx_ring(struct sk_if_softc *sc_if) 729 { 730 struct sk_chain_data *cd = &sc_if->sk_cdata; 731 struct sk_ring_data *rd = sc_if->sk_rdata; 732 int i; 733 734 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 735 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 736 737 for (i = 0; i < SK_TX_RING_CNT; i++) { 738 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 739 if (i == (SK_TX_RING_CNT - 1)) { 740 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 741 rd->sk_tx_ring[i].sk_next = 742 htole32(SK_TX_RING_ADDR(sc_if, 0)); 743 } else { 744 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 745 rd->sk_tx_ring[i].sk_next = 746 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 747 } 748 } 749 750 sc_if->sk_cdata.sk_tx_prod = 0; 751 sc_if->sk_cdata.sk_tx_cons = 0; 752 sc_if->sk_cdata.sk_tx_cnt = 0; 753 754 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 755 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 756 757 return 0; 758 } 759 760 int 761 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 762 bus_dmamap_t dmamap) 763 { 764 struct mbuf *m_new = NULL; 765 struct sk_chain *c; 766 struct sk_rx_desc *r; 767 768 if (m == NULL) { 769 caddr_t buf = NULL; 770 771 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 772 if (m_new == NULL) { 773 aprint_error("%s: no memory for rx list -- " 774 "packet dropped!\n", sc_if->sk_dev.dv_xname); 775 return ENOBUFS; 776 } 777 778 /* Allocate the jumbo buffer */ 779 buf = sk_jalloc(sc_if); 780 if (buf == NULL) { 781 m_freem(m_new); 782 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 783 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 784 return ENOBUFS; 785 } 786 787 /* Attach the buffer to the mbuf */ 788 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 789 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 790 791 } else { 792 /* 793 * We're re-using a previously allocated mbuf; 794 * be sure to re-init pointers and lengths to 795 * default values. 796 */ 797 m_new = m; 798 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 799 m_new->m_data = m_new->m_ext.ext_buf; 800 } 801 m_adj(m_new, ETHER_ALIGN); 802 803 c = &sc_if->sk_cdata.sk_rx_chain[i]; 804 r = c->sk_desc; 805 c->sk_mbuf = m_new; 806 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 807 (((vaddr_t)m_new->m_data 808 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 809 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 810 811 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 812 813 return 0; 814 } 815 816 /* 817 * Memory management for jumbo frames. 818 */ 819 820 int 821 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 822 { 823 struct sk_softc *sc = sc_if->sk_softc; 824 caddr_t ptr, kva; 825 bus_dma_segment_t seg; 826 int i, rseg, state, error; 827 struct sk_jpool_entry *entry; 828 829 state = error = 0; 830 831 /* Grab a big chunk o' storage. */ 832 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 833 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 834 aprint_error("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 835 return ENOBUFS; 836 } 837 838 state = 1; 839 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, &kva, 840 BUS_DMA_NOWAIT)) { 841 aprint_error("%s: can't map dma buffers (%d bytes)\n", 842 sc->sk_dev.dv_xname, SK_JMEM); 843 error = ENOBUFS; 844 goto out; 845 } 846 847 state = 2; 848 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 849 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 850 aprint_error("%s: can't create dma map\n", sc->sk_dev.dv_xname); 851 error = ENOBUFS; 852 goto out; 853 } 854 855 state = 3; 856 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 857 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 858 aprint_error("%s: can't load dma map\n", sc->sk_dev.dv_xname); 859 error = ENOBUFS; 860 goto out; 861 } 862 863 state = 4; 864 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 865 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 866 867 LIST_INIT(&sc_if->sk_jfree_listhead); 868 LIST_INIT(&sc_if->sk_jinuse_listhead); 869 870 /* 871 * Now divide it up into 9K pieces and save the addresses 872 * in an array. 873 */ 874 ptr = sc_if->sk_cdata.sk_jumbo_buf; 875 for (i = 0; i < SK_JSLOTS; i++) { 876 sc_if->sk_cdata.sk_jslots[i] = ptr; 877 ptr += SK_JLEN; 878 entry = malloc(sizeof(struct sk_jpool_entry), 879 M_DEVBUF, M_NOWAIT); 880 if (entry == NULL) { 881 aprint_error("%s: no memory for jumbo buffer queue!\n", 882 sc->sk_dev.dv_xname); 883 error = ENOBUFS; 884 goto out; 885 } 886 entry->slot = i; 887 if (i) 888 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 889 entry, jpool_entries); 890 else 891 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 892 entry, jpool_entries); 893 } 894 out: 895 if (error != 0) { 896 switch (state) { 897 case 4: 898 bus_dmamap_unload(sc->sc_dmatag, 899 sc_if->sk_cdata.sk_rx_jumbo_map); 900 case 3: 901 bus_dmamap_destroy(sc->sc_dmatag, 902 sc_if->sk_cdata.sk_rx_jumbo_map); 903 case 2: 904 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 905 case 1: 906 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 907 break; 908 default: 909 break; 910 } 911 } 912 913 return error; 914 } 915 916 /* 917 * Allocate a jumbo buffer. 918 */ 919 void * 920 sk_jalloc(struct sk_if_softc *sc_if) 921 { 922 struct sk_jpool_entry *entry; 923 924 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 925 926 if (entry == NULL) 927 return NULL; 928 929 LIST_REMOVE(entry, jpool_entries); 930 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 931 return sc_if->sk_cdata.sk_jslots[entry->slot]; 932 } 933 934 /* 935 * Release a jumbo buffer. 936 */ 937 void 938 sk_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 939 { 940 struct sk_jpool_entry *entry; 941 struct sk_if_softc *sc; 942 int i, s; 943 944 /* Extract the softc struct pointer. */ 945 sc = (struct sk_if_softc *)arg; 946 947 if (sc == NULL) 948 panic("sk_jfree: can't find softc pointer!"); 949 950 /* calculate the slot this buffer belongs to */ 951 952 i = ((vaddr_t)buf 953 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 954 955 if ((i < 0) || (i >= SK_JSLOTS)) 956 panic("sk_jfree: asked to free buffer that we don't manage!"); 957 958 s = splvm(); 959 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 960 if (entry == NULL) 961 panic("sk_jfree: buffer not in use!"); 962 entry->slot = i; 963 LIST_REMOVE(entry, jpool_entries); 964 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 965 966 if (__predict_true(m != NULL)) 967 pool_cache_put(&mbpool_cache, m); 968 splx(s); 969 } 970 971 /* 972 * Set media options. 973 */ 974 int 975 sk_ifmedia_upd(struct ifnet *ifp) 976 { 977 struct sk_if_softc *sc_if = ifp->if_softc; 978 979 (void) sk_init(ifp); 980 mii_mediachg(&sc_if->sk_mii); 981 return 0; 982 } 983 984 /* 985 * Report current media status. 986 */ 987 void 988 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 989 { 990 struct sk_if_softc *sc_if = ifp->if_softc; 991 992 mii_pollstat(&sc_if->sk_mii); 993 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 994 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 995 } 996 997 int 998 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 999 { 1000 struct sk_if_softc *sc_if = ifp->if_softc; 1001 struct sk_softc *sc = sc_if->sk_softc; 1002 struct ifreq *ifr = (struct ifreq *) data; 1003 struct mii_data *mii; 1004 int s, error = 0; 1005 1006 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1007 1008 s = splnet(); 1009 1010 switch (command) { 1011 1012 case SIOCSIFFLAGS: 1013 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1014 if (ifp->if_flags & IFF_UP) { 1015 if (ifp->if_flags & IFF_RUNNING && 1016 ifp->if_flags & IFF_PROMISC && 1017 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1018 switch (sc->sk_type) { 1019 case SK_GENESIS: 1020 SK_XM_SETBIT_4(sc_if, XM_MODE, 1021 XM_MODE_RX_PROMISC); 1022 break; 1023 case SK_YUKON: 1024 case SK_YUKON_LITE: 1025 case SK_YUKON_LP: 1026 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1027 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1028 break; 1029 } 1030 sk_setmulti(sc_if); 1031 } else if (ifp->if_flags & IFF_RUNNING && 1032 !(ifp->if_flags & IFF_PROMISC) && 1033 sc_if->sk_if_flags & IFF_PROMISC) { 1034 switch (sc->sk_type) { 1035 case SK_GENESIS: 1036 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1037 XM_MODE_RX_PROMISC); 1038 break; 1039 case SK_YUKON: 1040 case SK_YUKON_LITE: 1041 case SK_YUKON_LP: 1042 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1043 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1044 break; 1045 } 1046 1047 sk_setmulti(sc_if); 1048 } else 1049 (void) sk_init(ifp); 1050 } else { 1051 if (ifp->if_flags & IFF_RUNNING) 1052 sk_stop(ifp,0); 1053 } 1054 sc_if->sk_if_flags = ifp->if_flags; 1055 error = 0; 1056 break; 1057 1058 case SIOCGIFMEDIA: 1059 case SIOCSIFMEDIA: 1060 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 1061 mii = &sc_if->sk_mii; 1062 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1063 break; 1064 default: 1065 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1066 error = ether_ioctl(ifp, command, data); 1067 1068 if ( error == ENETRESET) { 1069 if (ifp->if_flags & IFF_RUNNING) { 1070 sk_setmulti(sc_if); 1071 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1072 } 1073 error = 0; 1074 } else if ( error ) { 1075 splx(s); 1076 return error; 1077 } 1078 break; 1079 } 1080 1081 splx(s); 1082 return error; 1083 } 1084 1085 void 1086 sk_update_int_mod(struct sk_softc *sc) 1087 { 1088 u_int32_t imtimer_ticks; 1089 1090 /* 1091 * Configure interrupt moderation. The moderation timer 1092 * defers interrupts specified in the interrupt moderation 1093 * timer mask based on the timeout specified in the interrupt 1094 * moderation timer init register. Each bit in the timer 1095 * register represents one tick, so to specify a timeout in 1096 * microseconds, we have to multiply by the correct number of 1097 * ticks-per-microsecond. 1098 */ 1099 switch (sc->sk_type) { 1100 case SK_GENESIS: 1101 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1102 break; 1103 case SK_YUKON_EC: 1104 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1105 break; 1106 default: 1107 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1108 } 1109 aprint_verbose("%s: interrupt moderation is %d us\n", 1110 sc->sk_dev.dv_xname, sc->sk_int_mod); 1111 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1112 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1113 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1114 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1115 sc->sk_int_mod_pending = 0; 1116 } 1117 1118 /* 1119 * Lookup: Check the PCI vendor and device, and return a pointer to 1120 * The structure if the IDs match against our list. 1121 */ 1122 1123 static const struct sk_product * 1124 sk_lookup(const struct pci_attach_args *pa) 1125 { 1126 const struct sk_product *psk; 1127 1128 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1129 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1130 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1131 return psk; 1132 } 1133 return NULL; 1134 } 1135 1136 /* 1137 * Probe for a SysKonnect GEnesis chip. 1138 */ 1139 1140 int 1141 skc_probe(struct device *parent, struct cfdata *match, 1142 void *aux) 1143 { 1144 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1145 const struct sk_product *psk; 1146 pcireg_t subid; 1147 1148 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1149 1150 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1151 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1152 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1153 subid == SK_LINKSYS_EG1032_SUBID) 1154 return 1; 1155 1156 if ((psk = sk_lookup(pa))) { 1157 return 1; 1158 } 1159 return 0; 1160 } 1161 1162 /* 1163 * Force the GEnesis into reset, then bring it out of reset. 1164 */ 1165 void sk_reset(struct sk_softc *sc) 1166 { 1167 DPRINTFN(2, ("sk_reset\n")); 1168 1169 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1170 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1171 if (SK_YUKON_FAMILY(sc->sk_type)) 1172 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1173 1174 DELAY(1000); 1175 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1176 DELAY(2); 1177 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1178 if (SK_YUKON_FAMILY(sc->sk_type)) 1179 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1180 1181 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1182 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1183 CSR_READ_2(sc, SK_LINK_CTRL))); 1184 1185 if (sc->sk_type == SK_GENESIS) { 1186 /* Configure packet arbiter */ 1187 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1188 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1189 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1190 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1191 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1192 } 1193 1194 /* Enable RAM interface */ 1195 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1196 1197 sk_update_int_mod(sc); 1198 } 1199 1200 int 1201 sk_probe(struct device *parent, struct cfdata *match, 1202 void *aux) 1203 { 1204 struct skc_attach_args *sa = aux; 1205 1206 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1207 return 0; 1208 1209 return 1; 1210 } 1211 1212 /* 1213 * Each XMAC chip is attached as a separate logical IP interface. 1214 * Single port cards will have only one logical interface of course. 1215 */ 1216 void 1217 sk_attach(struct device *parent, struct device *self, void *aux) 1218 { 1219 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1220 struct sk_softc *sc = (struct sk_softc *)parent; 1221 struct skc_attach_args *sa = aux; 1222 struct sk_txmap_entry *entry; 1223 struct ifnet *ifp; 1224 bus_dma_segment_t seg; 1225 bus_dmamap_t dmamap; 1226 caddr_t kva; 1227 int i, rseg; 1228 1229 sc_if->sk_port = sa->skc_port; 1230 sc_if->sk_softc = sc; 1231 sc->sk_if[sa->skc_port] = sc_if; 1232 1233 if (sa->skc_port == SK_PORT_A) 1234 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1235 if (sa->skc_port == SK_PORT_B) 1236 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1237 1238 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1239 1240 /* 1241 * Get station address for this interface. Note that 1242 * dual port cards actually come with three station 1243 * addresses: one for each port, plus an extra. The 1244 * extra one is used by the SysKonnect driver software 1245 * as a 'virtual' station address for when both ports 1246 * are operating in failover mode. Currently we don't 1247 * use this extra address. 1248 */ 1249 for (i = 0; i < ETHER_ADDR_LEN; i++) 1250 sc_if->sk_enaddr[i] = 1251 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1252 1253 1254 aprint_normal(": Ethernet address %s\n", 1255 ether_sprintf(sc_if->sk_enaddr)); 1256 1257 /* 1258 * Set up RAM buffer addresses. The NIC will have a certain 1259 * amount of SRAM on it, somewhere between 512K and 2MB. We 1260 * need to divide this up a) between the transmitter and 1261 * receiver and b) between the two XMACs, if this is a 1262 * dual port NIC. Our algorithm is to divide up the memory 1263 * evenly so that everyone gets a fair share. 1264 */ 1265 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1266 u_int32_t chunk, val; 1267 1268 chunk = sc->sk_ramsize / 2; 1269 val = sc->sk_rboff / sizeof(u_int64_t); 1270 sc_if->sk_rx_ramstart = val; 1271 val += (chunk / sizeof(u_int64_t)); 1272 sc_if->sk_rx_ramend = val - 1; 1273 sc_if->sk_tx_ramstart = val; 1274 val += (chunk / sizeof(u_int64_t)); 1275 sc_if->sk_tx_ramend = val - 1; 1276 } else { 1277 u_int32_t chunk, val; 1278 1279 chunk = sc->sk_ramsize / 4; 1280 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1281 sizeof(u_int64_t); 1282 sc_if->sk_rx_ramstart = val; 1283 val += (chunk / sizeof(u_int64_t)); 1284 sc_if->sk_rx_ramend = val - 1; 1285 sc_if->sk_tx_ramstart = val; 1286 val += (chunk / sizeof(u_int64_t)); 1287 sc_if->sk_tx_ramend = val - 1; 1288 } 1289 1290 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1291 " tx_ramstart=%#x tx_ramend=%#x\n", 1292 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1293 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1294 1295 /* Read and save PHY type and set PHY address */ 1296 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1297 switch (sc_if->sk_phytype) { 1298 case SK_PHYTYPE_XMAC: 1299 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1300 break; 1301 case SK_PHYTYPE_BCOM: 1302 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1303 break; 1304 case SK_PHYTYPE_MARV_COPPER: 1305 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1306 break; 1307 default: 1308 aprint_error("%s: unsupported PHY type: %d\n", 1309 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1310 return; 1311 } 1312 1313 /* Allocate the descriptor queues. */ 1314 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1315 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1316 aprint_error("%s: can't alloc rx buffers\n", 1317 sc->sk_dev.dv_xname); 1318 goto fail; 1319 } 1320 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1321 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1322 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1323 sc_if->sk_dev.dv_xname, 1324 (u_long) sizeof(struct sk_ring_data)); 1325 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1326 goto fail; 1327 } 1328 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1329 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1330 &sc_if->sk_ring_map)) { 1331 aprint_error("%s: can't create dma map\n", 1332 sc_if->sk_dev.dv_xname); 1333 bus_dmamem_unmap(sc->sc_dmatag, kva, 1334 sizeof(struct sk_ring_data)); 1335 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1336 goto fail; 1337 } 1338 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1339 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1340 aprint_error("%s: can't load dma map\n", 1341 sc_if->sk_dev.dv_xname); 1342 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1343 bus_dmamem_unmap(sc->sc_dmatag, kva, 1344 sizeof(struct sk_ring_data)); 1345 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1346 goto fail; 1347 } 1348 1349 for (i = 0; i < SK_RX_RING_CNT; i++) 1350 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1351 1352 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1353 for (i = 0; i < SK_TX_RING_CNT; i++) { 1354 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1355 1356 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1357 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1358 aprint_error("%s: Can't create TX dmamap\n", 1359 sc_if->sk_dev.dv_xname); 1360 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1361 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1362 bus_dmamem_unmap(sc->sc_dmatag, kva, 1363 sizeof(struct sk_ring_data)); 1364 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1365 goto fail; 1366 } 1367 1368 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1369 if (!entry) { 1370 aprint_error("%s: Can't alloc txmap entry\n", 1371 sc_if->sk_dev.dv_xname); 1372 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1373 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1374 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1375 bus_dmamem_unmap(sc->sc_dmatag, kva, 1376 sizeof(struct sk_ring_data)); 1377 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1378 goto fail; 1379 } 1380 entry->dmamap = dmamap; 1381 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1382 } 1383 1384 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1385 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1386 1387 ifp = &sc_if->sk_ethercom.ec_if; 1388 /* Try to allocate memory for jumbo buffers. */ 1389 if (sk_alloc_jumbo_mem(sc_if)) { 1390 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1391 goto fail; 1392 } 1393 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1394 | ETHERCAP_JUMBO_MTU; 1395 1396 ifp->if_softc = sc_if; 1397 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1398 ifp->if_ioctl = sk_ioctl; 1399 ifp->if_start = sk_start; 1400 ifp->if_stop = sk_stop; 1401 ifp->if_init = sk_init; 1402 ifp->if_watchdog = sk_watchdog; 1403 ifp->if_capabilities = 0; 1404 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1405 IFQ_SET_READY(&ifp->if_snd); 1406 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1407 1408 /* 1409 * Do miibus setup. 1410 */ 1411 switch (sc->sk_type) { 1412 case SK_GENESIS: 1413 sk_init_xmac(sc_if); 1414 break; 1415 case SK_YUKON: 1416 case SK_YUKON_LITE: 1417 case SK_YUKON_LP: 1418 sk_init_yukon(sc_if); 1419 break; 1420 default: 1421 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1422 sc->sk_type); 1423 } 1424 1425 DPRINTFN(2, ("sk_attach: 1\n")); 1426 1427 sc_if->sk_mii.mii_ifp = ifp; 1428 switch (sc->sk_type) { 1429 case SK_GENESIS: 1430 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1431 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1432 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1433 break; 1434 case SK_YUKON: 1435 case SK_YUKON_LITE: 1436 case SK_YUKON_LP: 1437 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1438 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1439 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1440 break; 1441 } 1442 1443 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1444 sk_ifmedia_upd, sk_ifmedia_sts); 1445 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1446 MII_OFFSET_ANY, 0); 1447 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1448 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1449 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1450 0, NULL); 1451 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1452 } else 1453 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1454 1455 callout_init(&sc_if->sk_tick_ch); 1456 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1457 1458 DPRINTFN(2, ("sk_attach: 1\n")); 1459 1460 /* 1461 * Call MI attach routines. 1462 */ 1463 if_attach(ifp); 1464 1465 ether_ifattach(ifp, sc_if->sk_enaddr); 1466 1467 #if NRND > 0 1468 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1469 RND_TYPE_NET, 0); 1470 #endif 1471 1472 DPRINTFN(2, ("sk_attach: end\n")); 1473 1474 return; 1475 1476 fail: 1477 sc->sk_if[sa->skc_port] = NULL; 1478 } 1479 1480 int 1481 skcprint(void *aux, const char *pnp) 1482 { 1483 struct skc_attach_args *sa = aux; 1484 1485 if (pnp) 1486 aprint_normal("sk port %c at %s", 1487 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1488 else 1489 aprint_normal(" port %c", 1490 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1491 return UNCONF; 1492 } 1493 1494 /* 1495 * Attach the interface. Allocate softc structures, do ifmedia 1496 * setup and ethernet/BPF attach. 1497 */ 1498 void 1499 skc_attach(struct device *parent, struct device *self, void *aux) 1500 { 1501 struct sk_softc *sc = (struct sk_softc *)self; 1502 struct pci_attach_args *pa = aux; 1503 struct skc_attach_args skca; 1504 pci_chipset_tag_t pc = pa->pa_pc; 1505 #ifndef SK_USEIOSPACE 1506 pcireg_t memtype; 1507 #endif 1508 pci_intr_handle_t ih; 1509 const char *intrstr = NULL; 1510 bus_addr_t iobase; 1511 bus_size_t iosize; 1512 int rc, sk_nodenum; 1513 u_int32_t command; 1514 const char *revstr; 1515 const struct sysctlnode *node; 1516 1517 DPRINTFN(2, ("begin skc_attach\n")); 1518 1519 /* 1520 * Handle power management nonsense. 1521 */ 1522 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1523 1524 if (command == 0x01) { 1525 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1526 if (command & SK_PSTATE_MASK) { 1527 u_int32_t xiobase, membase, irq; 1528 1529 /* Save important PCI config data. */ 1530 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1531 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1532 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1533 1534 /* Reset the power state. */ 1535 aprint_normal("%s chip is in D%d power mode " 1536 "-- setting to D0\n", sc->sk_dev.dv_xname, 1537 command & SK_PSTATE_MASK); 1538 command &= 0xFFFFFFFC; 1539 pci_conf_write(pc, pa->pa_tag, 1540 SK_PCI_PWRMGMTCTRL, command); 1541 1542 /* Restore PCI config data. */ 1543 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1544 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1545 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1546 } 1547 } 1548 1549 /* 1550 * Map control/status registers. 1551 */ 1552 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1553 command |= PCI_COMMAND_IO_ENABLE | 1554 PCI_COMMAND_MEM_ENABLE | 1555 PCI_COMMAND_MASTER_ENABLE; 1556 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1557 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1558 1559 #ifdef SK_USEIOSPACE 1560 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1561 aprint_error(": failed to enable I/O ports!\n"); 1562 return; 1563 } 1564 /* 1565 * Map control/status registers. 1566 */ 1567 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1568 &sc->sk_btag, &sc->sk_bhandle, 1569 &iobase, &iosize)) { 1570 aprint_error(": can't find i/o space\n"); 1571 return; 1572 } 1573 #else 1574 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1575 aprint_error(": failed to enable memory mapping!\n"); 1576 return; 1577 } 1578 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1579 switch (memtype) { 1580 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1581 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1582 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1583 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1584 &iobase, &iosize) == 0) 1585 break; 1586 default: 1587 aprint_error("%s: can't find mem space\n", 1588 sc->sk_dev.dv_xname); 1589 return; 1590 } 1591 1592 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1593 #endif 1594 sc->sc_dmatag = pa->pa_dmat; 1595 1596 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1597 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1598 1599 /* bail out here if chip is not recognized */ 1600 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1601 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1602 goto fail; 1603 } 1604 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1605 1606 /* Allocate interrupt */ 1607 if (pci_intr_map(pa, &ih)) { 1608 aprint_error(": couldn't map interrupt\n"); 1609 goto fail; 1610 } 1611 1612 intrstr = pci_intr_string(pc, ih); 1613 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1614 if (sc->sk_intrhand == NULL) { 1615 aprint_error(": couldn't establish interrupt"); 1616 if (intrstr != NULL) 1617 aprint_normal(" at %s", intrstr); 1618 goto fail; 1619 } 1620 aprint_normal(": %s\n", intrstr); 1621 1622 /* Reset the adapter. */ 1623 sk_reset(sc); 1624 1625 /* Read and save vital product data from EEPROM. */ 1626 sk_vpd_read(sc); 1627 1628 if (sc->sk_type == SK_GENESIS) { 1629 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1630 /* Read and save RAM size and RAMbuffer offset */ 1631 switch (val) { 1632 case SK_RAMSIZE_512K_64: 1633 sc->sk_ramsize = 0x80000; 1634 sc->sk_rboff = SK_RBOFF_0; 1635 break; 1636 case SK_RAMSIZE_1024K_64: 1637 sc->sk_ramsize = 0x100000; 1638 sc->sk_rboff = SK_RBOFF_80000; 1639 break; 1640 case SK_RAMSIZE_1024K_128: 1641 sc->sk_ramsize = 0x100000; 1642 sc->sk_rboff = SK_RBOFF_0; 1643 break; 1644 case SK_RAMSIZE_2048K_128: 1645 sc->sk_ramsize = 0x200000; 1646 sc->sk_rboff = SK_RBOFF_0; 1647 break; 1648 default: 1649 aprint_error("%s: unknown ram size: %d\n", 1650 sc->sk_dev.dv_xname, val); 1651 goto fail_1; 1652 break; 1653 } 1654 1655 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1656 sc->sk_ramsize, sc->sk_ramsize / 1024, 1657 sc->sk_rboff)); 1658 } else { 1659 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1660 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1661 sc->sk_rboff = SK_RBOFF_0; 1662 1663 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1664 sc->sk_ramsize / 1024, sc->sk_ramsize, 1665 sc->sk_rboff)); 1666 } 1667 1668 /* Read and save physical media type */ 1669 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1670 case SK_PMD_1000BASESX: 1671 sc->sk_pmd = IFM_1000_SX; 1672 break; 1673 case SK_PMD_1000BASELX: 1674 sc->sk_pmd = IFM_1000_LX; 1675 break; 1676 case SK_PMD_1000BASECX: 1677 sc->sk_pmd = IFM_1000_CX; 1678 break; 1679 case SK_PMD_1000BASETX: 1680 case SK_PMD_1000BASETX_ALT: 1681 sc->sk_pmd = IFM_1000_T; 1682 break; 1683 default: 1684 aprint_error("%s: unknown media type: 0x%x\n", 1685 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1686 goto fail_1; 1687 } 1688 1689 /* determine whether to name it with vpd or just make it up */ 1690 /* Marvell Yukon VPD's can freqently be bogus */ 1691 1692 switch (pa->pa_id) { 1693 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1694 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1695 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1696 case PCI_PRODUCT_3COM_3C940: 1697 case PCI_PRODUCT_DLINK_DGE530T: 1698 case PCI_PRODUCT_DLINK_DGE560T: 1699 case PCI_PRODUCT_DLINK_DGE560T_2: 1700 case PCI_PRODUCT_LINKSYS_EG1032: 1701 case PCI_PRODUCT_LINKSYS_EG1064: 1702 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1703 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1704 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1705 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1706 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1707 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1708 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1709 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1710 sc->sk_name = sc->sk_vpd_prodname; 1711 break; 1712 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1713 /* whoops yukon vpd prodname bears no resemblance to reality */ 1714 switch (sc->sk_type) { 1715 case SK_GENESIS: 1716 sc->sk_name = sc->sk_vpd_prodname; 1717 break; 1718 case SK_YUKON: 1719 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1720 break; 1721 case SK_YUKON_LITE: 1722 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1723 break; 1724 case SK_YUKON_LP: 1725 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1726 break; 1727 default: 1728 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1729 } 1730 1731 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1732 1733 if ( sc->sk_type == SK_YUKON ) { 1734 uint32_t flashaddr; 1735 uint8_t testbyte; 1736 1737 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1738 1739 /* test Flash-Address Register */ 1740 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1741 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1742 1743 if (testbyte != 0) { 1744 /* this is yukon lite Rev. A0 */ 1745 sc->sk_type = SK_YUKON_LITE; 1746 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1747 /* restore Flash-Address Register */ 1748 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1749 } 1750 } 1751 break; 1752 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1753 sc->sk_name = sc->sk_vpd_prodname; 1754 break; 1755 default: 1756 sc->sk_name = "Unknown Marvell"; 1757 } 1758 1759 1760 if ( sc->sk_type == SK_YUKON_LITE ) { 1761 switch (sc->sk_rev) { 1762 case SK_YUKON_LITE_REV_A0: 1763 revstr = "A0"; 1764 break; 1765 case SK_YUKON_LITE_REV_A1: 1766 revstr = "A1"; 1767 break; 1768 case SK_YUKON_LITE_REV_A3: 1769 revstr = "A3"; 1770 break; 1771 default: 1772 revstr = ""; 1773 } 1774 } else { 1775 revstr = ""; 1776 } 1777 1778 /* Announce the product name. */ 1779 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1780 sc->sk_name, revstr, sc->sk_rev); 1781 1782 skca.skc_port = SK_PORT_A; 1783 (void)config_found(&sc->sk_dev, &skca, skcprint); 1784 1785 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1786 skca.skc_port = SK_PORT_B; 1787 (void)config_found(&sc->sk_dev, &skca, skcprint); 1788 } 1789 1790 /* Turn on the 'driver is loaded' LED. */ 1791 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1792 1793 /* skc sysctl setup */ 1794 1795 sc->sk_int_mod = SK_IM_DEFAULT; 1796 sc->sk_int_mod_pending = 0; 1797 1798 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1799 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1800 SYSCTL_DESCR("skc per-controller controls"), 1801 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1802 CTL_EOL)) != 0) { 1803 aprint_normal("%s: couldn't create sysctl node\n", 1804 sc->sk_dev.dv_xname); 1805 goto fail_1; 1806 } 1807 1808 sk_nodenum = node->sysctl_num; 1809 1810 /* interrupt moderation time in usecs */ 1811 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1812 CTLFLAG_READWRITE, 1813 CTLTYPE_INT, "int_mod", 1814 SYSCTL_DESCR("sk interrupt moderation timer"), 1815 sk_sysctl_handler, 0, sc, 1816 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1817 CTL_EOL)) != 0) { 1818 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1819 sc->sk_dev.dv_xname); 1820 goto fail_1; 1821 } 1822 1823 return; 1824 1825 fail_1: 1826 pci_intr_disestablish(pc, sc->sk_intrhand); 1827 fail: 1828 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1829 } 1830 1831 int 1832 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1833 { 1834 struct sk_softc *sc = sc_if->sk_softc; 1835 struct sk_tx_desc *f = NULL; 1836 u_int32_t frag, cur, cnt = 0, sk_ctl; 1837 int i; 1838 struct sk_txmap_entry *entry; 1839 bus_dmamap_t txmap; 1840 1841 DPRINTFN(3, ("sk_encap\n")); 1842 1843 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1844 if (entry == NULL) { 1845 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1846 return ENOBUFS; 1847 } 1848 txmap = entry->dmamap; 1849 1850 cur = frag = *txidx; 1851 1852 #ifdef SK_DEBUG 1853 if (skdebug >= 3) 1854 sk_dump_mbuf(m_head); 1855 #endif 1856 1857 /* 1858 * Start packing the mbufs in this chain into 1859 * the fragment pointers. Stop when we run out 1860 * of fragments or hit the end of the mbuf chain. 1861 */ 1862 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1863 BUS_DMA_NOWAIT)) { 1864 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1865 return ENOBUFS; 1866 } 1867 1868 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1869 1870 /* Sync the DMA map. */ 1871 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1872 BUS_DMASYNC_PREWRITE); 1873 1874 for (i = 0; i < txmap->dm_nsegs; i++) { 1875 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1876 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1877 return ENOBUFS; 1878 } 1879 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1880 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1881 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1882 if (cnt == 0) 1883 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1884 else 1885 sk_ctl |= SK_TXCTL_OWN; 1886 f->sk_ctl = htole32(sk_ctl); 1887 cur = frag; 1888 SK_INC(frag, SK_TX_RING_CNT); 1889 cnt++; 1890 } 1891 1892 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1893 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1894 1895 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1896 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1897 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1898 1899 /* Sync descriptors before handing to chip */ 1900 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1901 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1902 1903 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1904 htole32(SK_TXCTL_OWN); 1905 1906 /* Sync first descriptor to hand it off */ 1907 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1908 1909 sc_if->sk_cdata.sk_tx_cnt += cnt; 1910 1911 #ifdef SK_DEBUG 1912 if (skdebug >= 3) { 1913 struct sk_tx_desc *desc; 1914 u_int32_t idx; 1915 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1916 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1917 sk_dump_txdesc(desc, idx); 1918 } 1919 } 1920 #endif 1921 1922 *txidx = frag; 1923 1924 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1925 1926 return 0; 1927 } 1928 1929 void 1930 sk_start(struct ifnet *ifp) 1931 { 1932 struct sk_if_softc *sc_if = ifp->if_softc; 1933 struct sk_softc *sc = sc_if->sk_softc; 1934 struct mbuf *m_head = NULL; 1935 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1936 int pkts = 0; 1937 1938 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1939 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1940 1941 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1942 IFQ_POLL(&ifp->if_snd, m_head); 1943 if (m_head == NULL) 1944 break; 1945 1946 /* 1947 * Pack the data into the transmit ring. If we 1948 * don't have room, set the OACTIVE flag and wait 1949 * for the NIC to drain the ring. 1950 */ 1951 if (sk_encap(sc_if, m_head, &idx)) { 1952 ifp->if_flags |= IFF_OACTIVE; 1953 break; 1954 } 1955 1956 /* now we are committed to transmit the packet */ 1957 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1958 pkts++; 1959 1960 /* 1961 * If there's a BPF listener, bounce a copy of this frame 1962 * to him. 1963 */ 1964 #if NBPFILTER > 0 1965 if (ifp->if_bpf) 1966 bpf_mtap(ifp->if_bpf, m_head); 1967 #endif 1968 } 1969 if (pkts == 0) 1970 return; 1971 1972 /* Transmit */ 1973 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1974 sc_if->sk_cdata.sk_tx_prod = idx; 1975 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1976 1977 /* Set a timeout in case the chip goes out to lunch. */ 1978 ifp->if_timer = 5; 1979 } 1980 } 1981 1982 1983 void 1984 sk_watchdog(struct ifnet *ifp) 1985 { 1986 struct sk_if_softc *sc_if = ifp->if_softc; 1987 1988 /* 1989 * Reclaim first as there is a possibility of losing Tx completion 1990 * interrupts. 1991 */ 1992 sk_txeof(sc_if); 1993 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1994 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1995 1996 ifp->if_oerrors++; 1997 1998 sk_init(ifp); 1999 } 2000 } 2001 2002 void 2003 sk_shutdown(void * v) 2004 { 2005 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2006 struct sk_softc *sc = sc_if->sk_softc; 2007 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2008 2009 DPRINTFN(2, ("sk_shutdown\n")); 2010 sk_stop(ifp,1); 2011 2012 /* Turn off the 'driver is loaded' LED. */ 2013 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2014 2015 /* 2016 * Reset the GEnesis controller. Doing this should also 2017 * assert the resets on the attached XMAC(s). 2018 */ 2019 sk_reset(sc); 2020 } 2021 2022 void 2023 sk_rxeof(struct sk_if_softc *sc_if) 2024 { 2025 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2026 struct mbuf *m; 2027 struct sk_chain *cur_rx; 2028 struct sk_rx_desc *cur_desc; 2029 int i, cur, total_len = 0; 2030 u_int32_t rxstat, sk_ctl; 2031 bus_dmamap_t dmamap; 2032 2033 i = sc_if->sk_cdata.sk_rx_prod; 2034 2035 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2036 2037 for (;;) { 2038 cur = i; 2039 2040 /* Sync the descriptor */ 2041 SK_CDRXSYNC(sc_if, cur, 2042 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2043 2044 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2045 if (sk_ctl & SK_RXCTL_OWN) { 2046 /* Invalidate the descriptor -- it's not ready yet */ 2047 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2048 sc_if->sk_cdata.sk_rx_prod = i; 2049 break; 2050 } 2051 2052 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2053 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2054 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2055 2056 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2057 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2058 2059 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2060 m = cur_rx->sk_mbuf; 2061 cur_rx->sk_mbuf = NULL; 2062 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2063 2064 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2065 2066 SK_INC(i, SK_RX_RING_CNT); 2067 2068 if (rxstat & XM_RXSTAT_ERRFRAME) { 2069 ifp->if_ierrors++; 2070 sk_newbuf(sc_if, cur, m, dmamap); 2071 continue; 2072 } 2073 2074 /* 2075 * Try to allocate a new jumbo buffer. If that 2076 * fails, copy the packet to mbufs and put the 2077 * jumbo buffer back in the ring so it can be 2078 * re-used. If allocating mbufs fails, then we 2079 * have to drop the packet. 2080 */ 2081 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2082 struct mbuf *m0; 2083 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2084 total_len + ETHER_ALIGN, 0, ifp, NULL); 2085 sk_newbuf(sc_if, cur, m, dmamap); 2086 if (m0 == NULL) { 2087 aprint_error("%s: no receive buffers " 2088 "available -- packet dropped!\n", 2089 sc_if->sk_dev.dv_xname); 2090 ifp->if_ierrors++; 2091 continue; 2092 } 2093 m_adj(m0, ETHER_ALIGN); 2094 m = m0; 2095 } else { 2096 m->m_pkthdr.rcvif = ifp; 2097 m->m_pkthdr.len = m->m_len = total_len; 2098 } 2099 2100 ifp->if_ipackets++; 2101 2102 #if NBPFILTER > 0 2103 if (ifp->if_bpf) 2104 bpf_mtap(ifp->if_bpf, m); 2105 #endif 2106 /* pass it on. */ 2107 (*ifp->if_input)(ifp, m); 2108 } 2109 } 2110 2111 void 2112 sk_txeof(struct sk_if_softc *sc_if) 2113 { 2114 struct sk_softc *sc = sc_if->sk_softc; 2115 struct sk_tx_desc *cur_tx; 2116 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2117 u_int32_t idx, sk_ctl; 2118 struct sk_txmap_entry *entry; 2119 2120 DPRINTFN(3, ("sk_txeof\n")); 2121 2122 /* 2123 * Go through our tx ring and free mbufs for those 2124 * frames that have been sent. 2125 */ 2126 idx = sc_if->sk_cdata.sk_tx_cons; 2127 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2128 SK_CDTXSYNC(sc_if, idx, 1, 2129 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2130 2131 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2132 sk_ctl = le32toh(cur_tx->sk_ctl); 2133 #ifdef SK_DEBUG 2134 if (skdebug >= 3) 2135 sk_dump_txdesc(cur_tx, idx); 2136 #endif 2137 if (sk_ctl & SK_TXCTL_OWN) { 2138 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2139 break; 2140 } 2141 if (sk_ctl & SK_TXCTL_LASTFRAG) 2142 ifp->if_opackets++; 2143 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2144 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2145 2146 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2147 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2148 2149 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2150 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2151 2152 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2153 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2154 link); 2155 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2156 } 2157 sc_if->sk_cdata.sk_tx_cnt--; 2158 SK_INC(idx, SK_TX_RING_CNT); 2159 } 2160 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2161 ifp->if_timer = 0; 2162 else /* nudge chip to keep tx ring moving */ 2163 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2164 2165 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2166 ifp->if_flags &= ~IFF_OACTIVE; 2167 2168 sc_if->sk_cdata.sk_tx_cons = idx; 2169 } 2170 2171 void 2172 sk_tick(void *xsc_if) 2173 { 2174 struct sk_if_softc *sc_if = xsc_if; 2175 struct mii_data *mii = &sc_if->sk_mii; 2176 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2177 int i; 2178 2179 DPRINTFN(3, ("sk_tick\n")); 2180 2181 if (!(ifp->if_flags & IFF_UP)) 2182 return; 2183 2184 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2185 sk_intr_bcom(sc_if); 2186 return; 2187 } 2188 2189 /* 2190 * According to SysKonnect, the correct way to verify that 2191 * the link has come back up is to poll bit 0 of the GPIO 2192 * register three times. This pin has the signal from the 2193 * link sync pin connected to it; if we read the same link 2194 * state 3 times in a row, we know the link is up. 2195 */ 2196 for (i = 0; i < 3; i++) { 2197 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2198 break; 2199 } 2200 2201 if (i != 3) { 2202 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2203 return; 2204 } 2205 2206 /* Turn the GP0 interrupt back on. */ 2207 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2208 SK_XM_READ_2(sc_if, XM_ISR); 2209 mii_tick(mii); 2210 mii_pollstat(mii); 2211 callout_stop(&sc_if->sk_tick_ch); 2212 } 2213 2214 void 2215 sk_intr_bcom(struct sk_if_softc *sc_if) 2216 { 2217 struct mii_data *mii = &sc_if->sk_mii; 2218 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2219 int status; 2220 2221 2222 DPRINTFN(3, ("sk_intr_bcom\n")); 2223 2224 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2225 2226 /* 2227 * Read the PHY interrupt register to make sure 2228 * we clear any pending interrupts. 2229 */ 2230 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2231 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2232 2233 if (!(ifp->if_flags & IFF_RUNNING)) { 2234 sk_init_xmac(sc_if); 2235 return; 2236 } 2237 2238 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2239 int lstat; 2240 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2241 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2242 2243 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2244 mii_mediachg(mii); 2245 /* Turn off the link LED. */ 2246 SK_IF_WRITE_1(sc_if, 0, 2247 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2248 sc_if->sk_link = 0; 2249 } else if (status & BRGPHY_ISR_LNK_CHG) { 2250 sk_xmac_miibus_writereg((struct device *)sc_if, 2251 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2252 mii_tick(mii); 2253 sc_if->sk_link = 1; 2254 /* Turn on the link LED. */ 2255 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2256 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2257 SK_LINKLED_BLINK_OFF); 2258 mii_pollstat(mii); 2259 } else { 2260 mii_tick(mii); 2261 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2262 } 2263 } 2264 2265 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2266 } 2267 2268 void 2269 sk_intr_xmac(struct sk_if_softc *sc_if) 2270 { 2271 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2272 2273 DPRINTFN(3, ("sk_intr_xmac\n")); 2274 2275 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2276 if (status & XM_ISR_GP0_SET) { 2277 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2278 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2279 } 2280 2281 if (status & XM_ISR_AUTONEG_DONE) { 2282 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2283 } 2284 } 2285 2286 if (status & XM_IMR_TX_UNDERRUN) 2287 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2288 2289 if (status & XM_IMR_RX_OVERRUN) 2290 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2291 } 2292 2293 void 2294 sk_intr_yukon(struct sk_if_softc *sc_if) 2295 { 2296 int status; 2297 2298 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2299 2300 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2301 } 2302 2303 int 2304 sk_intr(void *xsc) 2305 { 2306 struct sk_softc *sc = xsc; 2307 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2308 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2309 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2310 u_int32_t status; 2311 int claimed = 0; 2312 2313 if (sc_if0 != NULL) 2314 ifp0 = &sc_if0->sk_ethercom.ec_if; 2315 if (sc_if1 != NULL) 2316 ifp1 = &sc_if1->sk_ethercom.ec_if; 2317 2318 for (;;) { 2319 status = CSR_READ_4(sc, SK_ISSR); 2320 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2321 2322 if (!(status & sc->sk_intrmask)) 2323 break; 2324 2325 claimed = 1; 2326 2327 /* Handle receive interrupts first. */ 2328 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2329 sk_rxeof(sc_if0); 2330 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2331 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2332 } 2333 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2334 sk_rxeof(sc_if1); 2335 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2336 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2337 } 2338 2339 /* Then transmit interrupts. */ 2340 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2341 sk_txeof(sc_if0); 2342 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2343 SK_TXBMU_CLR_IRQ_EOF); 2344 } 2345 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2346 sk_txeof(sc_if1); 2347 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2348 SK_TXBMU_CLR_IRQ_EOF); 2349 } 2350 2351 /* Then MAC interrupts. */ 2352 if (sc_if0 && (status & SK_ISR_MAC1) && 2353 (ifp0->if_flags & IFF_RUNNING)) { 2354 if (sc->sk_type == SK_GENESIS) 2355 sk_intr_xmac(sc_if0); 2356 else 2357 sk_intr_yukon(sc_if0); 2358 } 2359 2360 if (sc_if1 && (status & SK_ISR_MAC2) && 2361 (ifp1->if_flags & IFF_RUNNING)) { 2362 if (sc->sk_type == SK_GENESIS) 2363 sk_intr_xmac(sc_if1); 2364 else 2365 sk_intr_yukon(sc_if1); 2366 2367 } 2368 2369 if (status & SK_ISR_EXTERNAL_REG) { 2370 if (sc_if0 != NULL && 2371 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2372 sk_intr_bcom(sc_if0); 2373 2374 if (sc_if1 != NULL && 2375 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2376 sk_intr_bcom(sc_if1); 2377 } 2378 } 2379 2380 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2381 2382 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2383 sk_start(ifp0); 2384 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2385 sk_start(ifp1); 2386 2387 #if NRND > 0 2388 if (RND_ENABLED(&sc->rnd_source)) 2389 rnd_add_uint32(&sc->rnd_source, status); 2390 #endif 2391 2392 if (sc->sk_int_mod_pending) 2393 sk_update_int_mod(sc); 2394 2395 return claimed; 2396 } 2397 2398 void 2399 sk_init_xmac(struct sk_if_softc *sc_if) 2400 { 2401 struct sk_softc *sc = sc_if->sk_softc; 2402 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2403 static const struct sk_bcom_hack bhack[] = { 2404 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2405 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2406 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2407 { 0, 0 } }; 2408 2409 DPRINTFN(1, ("sk_init_xmac\n")); 2410 2411 /* Unreset the XMAC. */ 2412 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2413 DELAY(1000); 2414 2415 /* Reset the XMAC's internal state. */ 2416 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2417 2418 /* Save the XMAC II revision */ 2419 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2420 2421 /* 2422 * Perform additional initialization for external PHYs, 2423 * namely for the 1000baseTX cards that use the XMAC's 2424 * GMII mode. 2425 */ 2426 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2427 int i = 0; 2428 u_int32_t val; 2429 2430 /* Take PHY out of reset. */ 2431 val = sk_win_read_4(sc, SK_GPIO); 2432 if (sc_if->sk_port == SK_PORT_A) 2433 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2434 else 2435 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2436 sk_win_write_4(sc, SK_GPIO, val); 2437 2438 /* Enable GMII mode on the XMAC. */ 2439 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2440 2441 sk_xmac_miibus_writereg((struct device *)sc_if, 2442 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2443 DELAY(10000); 2444 sk_xmac_miibus_writereg((struct device *)sc_if, 2445 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2446 2447 /* 2448 * Early versions of the BCM5400 apparently have 2449 * a bug that requires them to have their reserved 2450 * registers initialized to some magic values. I don't 2451 * know what the numbers do, I'm just the messenger. 2452 */ 2453 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2454 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2455 while (bhack[i].reg) { 2456 sk_xmac_miibus_writereg((struct device *)sc_if, 2457 SK_PHYADDR_BCOM, bhack[i].reg, 2458 bhack[i].val); 2459 i++; 2460 } 2461 } 2462 } 2463 2464 /* Set station address */ 2465 SK_XM_WRITE_2(sc_if, XM_PAR0, 2466 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2467 SK_XM_WRITE_2(sc_if, XM_PAR1, 2468 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2469 SK_XM_WRITE_2(sc_if, XM_PAR2, 2470 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2471 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2472 2473 if (ifp->if_flags & IFF_PROMISC) 2474 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2475 else 2476 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2477 2478 if (ifp->if_flags & IFF_BROADCAST) 2479 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2480 else 2481 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2482 2483 /* We don't need the FCS appended to the packet. */ 2484 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2485 2486 /* We want short frames padded to 60 bytes. */ 2487 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2488 2489 /* 2490 * Enable the reception of all error frames. This is is 2491 * a necessary evil due to the design of the XMAC. The 2492 * XMAC's receive FIFO is only 8K in size, however jumbo 2493 * frames can be up to 9000 bytes in length. When bad 2494 * frame filtering is enabled, the XMAC's RX FIFO operates 2495 * in 'store and forward' mode. For this to work, the 2496 * entire frame has to fit into the FIFO, but that means 2497 * that jumbo frames larger than 8192 bytes will be 2498 * truncated. Disabling all bad frame filtering causes 2499 * the RX FIFO to operate in streaming mode, in which 2500 * case the XMAC will start transfering frames out of the 2501 * RX FIFO as soon as the FIFO threshold is reached. 2502 */ 2503 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2504 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2505 XM_MODE_RX_INRANGELEN); 2506 2507 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2508 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2509 else 2510 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2511 2512 /* 2513 * Bump up the transmit threshold. This helps hold off transmit 2514 * underruns when we're blasting traffic from both ports at once. 2515 */ 2516 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2517 2518 /* Set multicast filter */ 2519 sk_setmulti(sc_if); 2520 2521 /* Clear and enable interrupts */ 2522 SK_XM_READ_2(sc_if, XM_ISR); 2523 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2524 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2525 else 2526 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2527 2528 /* Configure MAC arbiter */ 2529 switch (sc_if->sk_xmac_rev) { 2530 case XM_XMAC_REV_B2: 2531 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2532 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2533 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2534 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2535 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2536 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2537 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2538 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2539 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2540 break; 2541 case XM_XMAC_REV_C1: 2542 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2543 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2544 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2545 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2546 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2547 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2548 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2549 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2550 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2551 break; 2552 default: 2553 break; 2554 } 2555 sk_win_write_2(sc, SK_MACARB_CTL, 2556 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2557 2558 sc_if->sk_link = 1; 2559 } 2560 2561 void sk_init_yukon(struct sk_if_softc *sc_if) 2562 { 2563 u_int32_t /*mac, */phy; 2564 u_int16_t reg; 2565 struct sk_softc *sc; 2566 int i; 2567 2568 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2569 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2570 2571 sc = sc_if->sk_softc; 2572 if (sc->sk_type == SK_YUKON_LITE && 2573 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2574 /* Take PHY out of reset. */ 2575 sk_win_write_4(sc, SK_GPIO, 2576 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2577 } 2578 2579 2580 /* GMAC and GPHY Reset */ 2581 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2582 2583 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2584 2585 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2586 DELAY(1000); 2587 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2588 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2589 DELAY(1000); 2590 2591 2592 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2593 2594 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2595 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2596 2597 switch (sc_if->sk_softc->sk_pmd) { 2598 case IFM_1000_SX: 2599 case IFM_1000_LX: 2600 phy |= SK_GPHY_FIBER; 2601 break; 2602 2603 case IFM_1000_CX: 2604 case IFM_1000_T: 2605 phy |= SK_GPHY_COPPER; 2606 break; 2607 } 2608 2609 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2610 2611 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2612 DELAY(1000); 2613 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2614 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2615 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2616 2617 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2618 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2619 2620 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2621 2622 /* unused read of the interrupt source register */ 2623 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2624 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2625 2626 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2627 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2628 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2629 2630 /* MIB Counter Clear Mode set */ 2631 reg |= YU_PAR_MIB_CLR; 2632 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2633 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2634 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2635 2636 /* MIB Counter Clear Mode clear */ 2637 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2638 reg &= ~YU_PAR_MIB_CLR; 2639 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2640 2641 /* receive control reg */ 2642 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2643 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2644 YU_RCR_CRCR); 2645 2646 /* transmit parameter register */ 2647 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2648 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2649 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2650 2651 /* serial mode register */ 2652 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2653 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2654 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2655 YU_SMR_IPG_DATA(0x1e)); 2656 2657 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2658 /* Setup Yukon's address */ 2659 for (i = 0; i < 3; i++) { 2660 /* Write Source Address 1 (unicast filter) */ 2661 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2662 sc_if->sk_enaddr[i * 2] | 2663 sc_if->sk_enaddr[i * 2 + 1] << 8); 2664 } 2665 2666 for (i = 0; i < 3; i++) { 2667 reg = sk_win_read_2(sc_if->sk_softc, 2668 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2669 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2670 } 2671 2672 /* Set multicast filter */ 2673 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2674 sk_setmulti(sc_if); 2675 2676 /* enable interrupt mask for counter overflows */ 2677 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2678 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2679 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2680 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2681 2682 /* Configure RX MAC FIFO */ 2683 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2684 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2685 2686 /* Configure TX MAC FIFO */ 2687 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2688 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2689 2690 DPRINTFN(6, ("sk_init_yukon: end\n")); 2691 } 2692 2693 /* 2694 * Note that to properly initialize any part of the GEnesis chip, 2695 * you first have to take it out of reset mode. 2696 */ 2697 int 2698 sk_init(struct ifnet *ifp) 2699 { 2700 struct sk_if_softc *sc_if = ifp->if_softc; 2701 struct sk_softc *sc = sc_if->sk_softc; 2702 struct mii_data *mii = &sc_if->sk_mii; 2703 int s; 2704 u_int32_t imr, imtimer_ticks; 2705 2706 DPRINTFN(1, ("sk_init\n")); 2707 2708 s = splnet(); 2709 2710 if (ifp->if_flags & IFF_RUNNING) { 2711 splx(s); 2712 return 0; 2713 } 2714 2715 /* Cancel pending I/O and free all RX/TX buffers. */ 2716 sk_stop(ifp,0); 2717 2718 if (sc->sk_type == SK_GENESIS) { 2719 /* Configure LINK_SYNC LED */ 2720 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2721 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2722 SK_LINKLED_LINKSYNC_ON); 2723 2724 /* Configure RX LED */ 2725 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2726 SK_RXLEDCTL_COUNTER_START); 2727 2728 /* Configure TX LED */ 2729 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2730 SK_TXLEDCTL_COUNTER_START); 2731 } 2732 2733 /* Configure I2C registers */ 2734 2735 /* Configure XMAC(s) */ 2736 switch (sc->sk_type) { 2737 case SK_GENESIS: 2738 sk_init_xmac(sc_if); 2739 break; 2740 case SK_YUKON: 2741 case SK_YUKON_LITE: 2742 case SK_YUKON_LP: 2743 sk_init_yukon(sc_if); 2744 break; 2745 } 2746 mii_mediachg(mii); 2747 2748 if (sc->sk_type == SK_GENESIS) { 2749 /* Configure MAC FIFOs */ 2750 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2751 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2752 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2753 2754 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2755 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2756 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2757 } 2758 2759 /* Configure transmit arbiter(s) */ 2760 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2761 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2762 2763 /* Configure RAMbuffers */ 2764 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2765 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2766 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2767 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2768 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2769 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2770 2771 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2772 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2773 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2774 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2775 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2776 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2777 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2778 2779 /* Configure BMUs */ 2780 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2781 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2782 SK_RX_RING_ADDR(sc_if, 0)); 2783 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2784 2785 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2786 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2787 SK_TX_RING_ADDR(sc_if, 0)); 2788 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2789 2790 /* Init descriptors */ 2791 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2792 aprint_error("%s: initialization failed: no " 2793 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2794 sk_stop(ifp,0); 2795 splx(s); 2796 return ENOBUFS; 2797 } 2798 2799 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2800 aprint_error("%s: initialization failed: no " 2801 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2802 sk_stop(ifp,0); 2803 splx(s); 2804 return ENOBUFS; 2805 } 2806 2807 /* Set interrupt moderation if changed via sysctl. */ 2808 switch (sc->sk_type) { 2809 case SK_GENESIS: 2810 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2811 break; 2812 case SK_YUKON_EC: 2813 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2814 break; 2815 default: 2816 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2817 } 2818 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2819 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2820 sk_win_write_4(sc, SK_IMTIMERINIT, 2821 SK_IM_USECS(sc->sk_int_mod)); 2822 aprint_verbose("%s: interrupt moderation is %d us\n", 2823 sc->sk_dev.dv_xname, sc->sk_int_mod); 2824 } 2825 2826 /* Configure interrupt handling */ 2827 CSR_READ_4(sc, SK_ISSR); 2828 if (sc_if->sk_port == SK_PORT_A) 2829 sc->sk_intrmask |= SK_INTRS1; 2830 else 2831 sc->sk_intrmask |= SK_INTRS2; 2832 2833 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2834 2835 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2836 2837 /* Start BMUs. */ 2838 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2839 2840 if (sc->sk_type == SK_GENESIS) { 2841 /* Enable XMACs TX and RX state machines */ 2842 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2843 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2844 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2845 } 2846 2847 if (SK_YUKON_FAMILY(sc->sk_type)) { 2848 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2849 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2850 #if 0 2851 /* XXX disable 100Mbps and full duplex mode? */ 2852 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2853 #endif 2854 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2855 } 2856 2857 2858 ifp->if_flags |= IFF_RUNNING; 2859 ifp->if_flags &= ~IFF_OACTIVE; 2860 2861 splx(s); 2862 return 0; 2863 } 2864 2865 void 2866 sk_stop(struct ifnet *ifp, int disable) 2867 { 2868 struct sk_if_softc *sc_if = ifp->if_softc; 2869 struct sk_softc *sc = sc_if->sk_softc; 2870 int i; 2871 2872 DPRINTFN(1, ("sk_stop\n")); 2873 2874 callout_stop(&sc_if->sk_tick_ch); 2875 2876 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2877 u_int32_t val; 2878 2879 /* Put PHY back into reset. */ 2880 val = sk_win_read_4(sc, SK_GPIO); 2881 if (sc_if->sk_port == SK_PORT_A) { 2882 val |= SK_GPIO_DIR0; 2883 val &= ~SK_GPIO_DAT0; 2884 } else { 2885 val |= SK_GPIO_DIR2; 2886 val &= ~SK_GPIO_DAT2; 2887 } 2888 sk_win_write_4(sc, SK_GPIO, val); 2889 } 2890 2891 /* Turn off various components of this interface. */ 2892 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2893 switch (sc->sk_type) { 2894 case SK_GENESIS: 2895 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2896 SK_TXMACCTL_XMAC_RESET); 2897 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2898 break; 2899 case SK_YUKON: 2900 case SK_YUKON_LITE: 2901 case SK_YUKON_LP: 2902 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2903 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2904 break; 2905 } 2906 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2907 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2908 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2909 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2910 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2911 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2912 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2913 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2914 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2915 2916 /* Disable interrupts */ 2917 if (sc_if->sk_port == SK_PORT_A) 2918 sc->sk_intrmask &= ~SK_INTRS1; 2919 else 2920 sc->sk_intrmask &= ~SK_INTRS2; 2921 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2922 2923 SK_XM_READ_2(sc_if, XM_ISR); 2924 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2925 2926 /* Free RX and TX mbufs still in the queues. */ 2927 for (i = 0; i < SK_RX_RING_CNT; i++) { 2928 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2929 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2930 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2931 } 2932 } 2933 2934 for (i = 0; i < SK_TX_RING_CNT; i++) { 2935 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2936 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2937 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2938 } 2939 } 2940 2941 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2942 } 2943 2944 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2945 2946 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2947 2948 #ifdef SK_DEBUG 2949 void 2950 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2951 { 2952 #define DESC_PRINT(X) \ 2953 if (X) \ 2954 printf("txdesc[%d]." #X "=%#x\n", \ 2955 idx, X); 2956 2957 DESC_PRINT(le32toh(desc->sk_ctl)); 2958 DESC_PRINT(le32toh(desc->sk_next)); 2959 DESC_PRINT(le32toh(desc->sk_data_lo)); 2960 DESC_PRINT(le32toh(desc->sk_data_hi)); 2961 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2962 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2963 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2964 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2965 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2966 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2967 #undef PRINT 2968 } 2969 2970 void 2971 sk_dump_bytes(const char *data, int len) 2972 { 2973 int c, i, j; 2974 2975 for (i = 0; i < len; i += 16) { 2976 printf("%08x ", i); 2977 c = len - i; 2978 if (c > 16) c = 16; 2979 2980 for (j = 0; j < c; j++) { 2981 printf("%02x ", data[i + j] & 0xff); 2982 if ((j & 0xf) == 7 && j > 0) 2983 printf(" "); 2984 } 2985 2986 for (; j < 16; j++) 2987 printf(" "); 2988 printf(" "); 2989 2990 for (j = 0; j < c; j++) { 2991 int ch = data[i + j] & 0xff; 2992 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2993 } 2994 2995 printf("\n"); 2996 2997 if (c < 16) 2998 break; 2999 } 3000 } 3001 3002 void 3003 sk_dump_mbuf(struct mbuf *m) 3004 { 3005 int count = m->m_pkthdr.len; 3006 3007 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3008 3009 while (count > 0 && m) { 3010 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3011 m, m->m_data, m->m_len); 3012 sk_dump_bytes(mtod(m, char *), m->m_len); 3013 3014 count -= m->m_len; 3015 m = m->m_next; 3016 } 3017 } 3018 #endif 3019 3020 static int 3021 sk_sysctl_handler(SYSCTLFN_ARGS) 3022 { 3023 int error, t; 3024 struct sysctlnode node; 3025 struct sk_softc *sc; 3026 3027 node = *rnode; 3028 sc = node.sysctl_data; 3029 t = sc->sk_int_mod; 3030 node.sysctl_data = &t; 3031 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3032 if (error || newp == NULL) 3033 return error; 3034 3035 if (t < SK_IM_MIN || t > SK_IM_MAX) 3036 return EINVAL; 3037 3038 /* update the softc with sysctl-changed value, and mark 3039 for hardware update */ 3040 sc->sk_int_mod = t; 3041 sc->sk_int_mod_pending = 1; 3042 return 0; 3043 } 3044 3045 /* 3046 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3047 * set up in skc_attach() 3048 */ 3049 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3050 { 3051 int rc; 3052 const struct sysctlnode *node; 3053 3054 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3055 0, CTLTYPE_NODE, "hw", NULL, 3056 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3057 goto err; 3058 } 3059 3060 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3061 0, CTLTYPE_NODE, "sk", 3062 SYSCTL_DESCR("sk interface controls"), 3063 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3064 goto err; 3065 } 3066 3067 sk_root_num = node->sysctl_num; 3068 return; 3069 3070 err: 3071 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3072 } 3073
Indexes created Mon Oct 13 15:10:03 GMT 2025