if_sk.c revision 1.36
1 /* $NetBSD: if_sk.c,v 1.36 2007/01/30 11:42:06 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 #include "rnd.h" 126 127 #include <sys/param.h> 128 #include <sys/systm.h> 129 #include <sys/sockio.h> 130 #include <sys/mbuf.h> 131 #include <sys/malloc.h> 132 #include <sys/kernel.h> 133 #include <sys/socket.h> 134 #include <sys/device.h> 135 #include <sys/queue.h> 136 #include <sys/callout.h> 137 #include <sys/sysctl.h> 138 #include <sys/endian.h> 139 140 #include <net/if.h> 141 #include <net/if_dl.h> 142 #include <net/if_types.h> 143 144 #include <net/if_media.h> 145 146 #if NBPFILTER > 0 147 #include <net/bpf.h> 148 #endif 149 #if NRND > 0 150 #include <sys/rnd.h> 151 #endif 152 153 #include <dev/mii/mii.h> 154 #include <dev/mii/miivar.h> 155 #include <dev/mii/brgphyreg.h> 156 157 #include <dev/pci/pcireg.h> 158 #include <dev/pci/pcivar.h> 159 #include <dev/pci/pcidevs.h> 160 161 /* #define SK_USEIOSPACE */ 162 163 #include <dev/pci/if_skreg.h> 164 #include <dev/pci/if_skvar.h> 165 166 int skc_probe(struct device *, struct cfdata *, void *); 167 void skc_attach(struct device *, struct device *self, void *aux); 168 int sk_probe(struct device *, struct cfdata *, void *); 169 void sk_attach(struct device *, struct device *self, void *aux); 170 int skcprint(void *, const char *); 171 int sk_intr(void *); 172 void sk_intr_bcom(struct sk_if_softc *); 173 void sk_intr_xmac(struct sk_if_softc *); 174 void sk_intr_yukon(struct sk_if_softc *); 175 void sk_rxeof(struct sk_if_softc *); 176 void sk_txeof(struct sk_if_softc *); 177 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 178 void sk_start(struct ifnet *); 179 int sk_ioctl(struct ifnet *, u_long, caddr_t); 180 int sk_init(struct ifnet *); 181 void sk_init_xmac(struct sk_if_softc *); 182 void sk_init_yukon(struct sk_if_softc *); 183 void sk_stop(struct ifnet *, int); 184 void sk_watchdog(struct ifnet *); 185 void sk_shutdown(void *); 186 int sk_ifmedia_upd(struct ifnet *); 187 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 188 void sk_reset(struct sk_softc *); 189 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 190 int sk_alloc_jumbo_mem(struct sk_if_softc *); 191 void sk_free_jumbo_mem(struct sk_if_softc *); 192 void *sk_jalloc(struct sk_if_softc *); 193 void sk_jfree(struct mbuf *, caddr_t, size_t, void *); 194 int sk_init_rx_ring(struct sk_if_softc *); 195 int sk_init_tx_ring(struct sk_if_softc *); 196 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 197 void sk_vpd_read_res(struct sk_softc *, 198 struct vpd_res *, int); 199 void sk_vpd_read(struct sk_softc *); 200 201 void sk_update_int_mod(struct sk_softc *); 202 203 int sk_xmac_miibus_readreg(struct device *, int, int); 204 void sk_xmac_miibus_writereg(struct device *, int, int, int); 205 void sk_xmac_miibus_statchg(struct device *); 206 207 int sk_marv_miibus_readreg(struct device *, int, int); 208 void sk_marv_miibus_writereg(struct device *, int, int, int); 209 void sk_marv_miibus_statchg(struct device *); 210 211 u_int32_t sk_xmac_hash(caddr_t); 212 u_int32_t sk_yukon_hash(caddr_t); 213 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 214 void sk_setmulti(struct sk_if_softc *); 215 void sk_tick(void *); 216 217 /* #define SK_DEBUG 2 */ 218 #ifdef SK_DEBUG 219 #define DPRINTF(x) if (skdebug) printf x 220 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 221 int skdebug = SK_DEBUG; 222 223 void sk_dump_txdesc(struct sk_tx_desc *, int); 224 void sk_dump_mbuf(struct mbuf *); 225 void sk_dump_bytes(const char *, int); 226 #else 227 #define DPRINTF(x) 228 #define DPRINTFN(n,x) 229 #endif 230 231 static int sk_sysctl_handler(SYSCTLFN_PROTO); 232 static int sk_root_num; 233 234 /* supported device vendors */ 235 static const struct sk_product { 236 pci_vendor_id_t sk_vendor; 237 pci_product_id_t sk_product; 238 } sk_products[] = { 239 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 240 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 241 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T, }, 242 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 243 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 244 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 245 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 246 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 247 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 248 { 0, 0, } 249 }; 250 251 #define SK_LINKSYS_EG1032_SUBID 0x00151737 252 253 static inline u_int32_t 254 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 255 { 256 #ifdef SK_USEIOSPACE 257 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 258 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 259 #else 260 return CSR_READ_4(sc, reg); 261 #endif 262 } 263 264 static inline u_int16_t 265 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 266 { 267 #ifdef SK_USEIOSPACE 268 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 269 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 270 #else 271 return CSR_READ_2(sc, reg); 272 #endif 273 } 274 275 static inline u_int8_t 276 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 277 { 278 #ifdef SK_USEIOSPACE 279 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 280 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 281 #else 282 return CSR_READ_1(sc, reg); 283 #endif 284 } 285 286 static inline void 287 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 288 { 289 #ifdef SK_USEIOSPACE 290 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 291 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 292 #else 293 CSR_WRITE_4(sc, reg, x); 294 #endif 295 } 296 297 static inline void 298 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 299 { 300 #ifdef SK_USEIOSPACE 301 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 302 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 303 #else 304 CSR_WRITE_2(sc, reg, x); 305 #endif 306 } 307 308 static inline void 309 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 310 { 311 #ifdef SK_USEIOSPACE 312 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 313 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 314 #else 315 CSR_WRITE_1(sc, reg, x); 316 #endif 317 } 318 319 /* 320 * The VPD EEPROM contains Vital Product Data, as suggested in 321 * the PCI 2.1 specification. The VPD data is separared into areas 322 * denoted by resource IDs. The SysKonnect VPD contains an ID string 323 * resource (the name of the adapter), a read-only area resource 324 * containing various key/data fields and a read/write area which 325 * can be used to store asset management information or log messages. 326 * We read the ID string and read-only into buffers attached to 327 * the controller softc structure for later use. At the moment, 328 * we only use the ID string during sk_attach(). 329 */ 330 u_int8_t 331 sk_vpd_readbyte(struct sk_softc *sc, int addr) 332 { 333 int i; 334 335 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 336 for (i = 0; i < SK_TIMEOUT; i++) { 337 DELAY(1); 338 if (sk_win_read_2(sc, 339 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 340 break; 341 } 342 343 if (i == SK_TIMEOUT) 344 return 0; 345 346 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 347 } 348 349 void 350 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 351 { 352 int i; 353 u_int8_t *ptr; 354 355 ptr = (u_int8_t *)res; 356 for (i = 0; i < sizeof(struct vpd_res); i++) 357 ptr[i] = sk_vpd_readbyte(sc, i + addr); 358 } 359 360 void 361 sk_vpd_read(struct sk_softc *sc) 362 { 363 int pos = 0, i; 364 struct vpd_res res; 365 366 if (sc->sk_vpd_prodname != NULL) 367 free(sc->sk_vpd_prodname, M_DEVBUF); 368 if (sc->sk_vpd_readonly != NULL) 369 free(sc->sk_vpd_readonly, M_DEVBUF); 370 sc->sk_vpd_prodname = NULL; 371 sc->sk_vpd_readonly = NULL; 372 373 sk_vpd_read_res(sc, &res, pos); 374 375 if (res.vr_id != VPD_RES_ID) { 376 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 377 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 378 return; 379 } 380 381 pos += sizeof(res); 382 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 383 if (sc->sk_vpd_prodname == NULL) 384 panic("sk_vpd_read"); 385 for (i = 0; i < res.vr_len; i++) 386 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 387 sc->sk_vpd_prodname[i] = '\0'; 388 pos += i; 389 390 sk_vpd_read_res(sc, &res, pos); 391 392 if (res.vr_id != VPD_RES_READ) { 393 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 394 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 395 return; 396 } 397 398 pos += sizeof(res); 399 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 400 if (sc->sk_vpd_readonly == NULL) 401 panic("sk_vpd_read"); 402 for (i = 0; i < res.vr_len ; i++) 403 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 404 } 405 406 int 407 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 408 { 409 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 410 int i; 411 412 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 413 414 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 415 return 0; 416 417 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 418 SK_XM_READ_2(sc_if, XM_PHY_DATA); 419 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 420 for (i = 0; i < SK_TIMEOUT; i++) { 421 DELAY(1); 422 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 423 XM_MMUCMD_PHYDATARDY) 424 break; 425 } 426 427 if (i == SK_TIMEOUT) { 428 aprint_error("%s: phy failed to come ready\n", 429 sc_if->sk_dev.dv_xname); 430 return 0; 431 } 432 } 433 DELAY(1); 434 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 435 } 436 437 void 438 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 439 { 440 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 441 int i; 442 443 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 444 445 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 446 for (i = 0; i < SK_TIMEOUT; i++) { 447 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 448 break; 449 } 450 451 if (i == SK_TIMEOUT) { 452 aprint_error("%s: phy failed to come ready\n", 453 sc_if->sk_dev.dv_xname); 454 return; 455 } 456 457 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 458 for (i = 0; i < SK_TIMEOUT; i++) { 459 DELAY(1); 460 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 461 break; 462 } 463 464 if (i == SK_TIMEOUT) 465 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 466 } 467 468 void 469 sk_xmac_miibus_statchg(struct device *dev) 470 { 471 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 472 struct mii_data *mii = &sc_if->sk_mii; 473 474 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 475 476 /* 477 * If this is a GMII PHY, manually set the XMAC's 478 * duplex mode accordingly. 479 */ 480 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 481 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 482 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 483 else 484 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 485 } 486 } 487 488 int 489 sk_marv_miibus_readreg(struct device *dev, int phy, int reg) 490 { 491 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 492 u_int16_t val; 493 int i; 494 495 if (phy != 0 || 496 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 497 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 498 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 499 phy, reg)); 500 return 0; 501 } 502 503 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 504 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 505 506 for (i = 0; i < SK_TIMEOUT; i++) { 507 DELAY(1); 508 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 509 if (val & YU_SMICR_READ_VALID) 510 break; 511 } 512 513 if (i == SK_TIMEOUT) { 514 aprint_error("%s: phy failed to come ready\n", 515 sc_if->sk_dev.dv_xname); 516 return 0; 517 } 518 519 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 520 SK_TIMEOUT)); 521 522 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 523 524 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 525 phy, reg, val)); 526 527 return val; 528 } 529 530 void 531 sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 532 { 533 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 534 int i; 535 536 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 537 phy, reg, val)); 538 539 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 540 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 541 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 542 543 for (i = 0; i < SK_TIMEOUT; i++) { 544 DELAY(1); 545 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 546 break; 547 } 548 } 549 550 void 551 sk_marv_miibus_statchg(struct device *dev) 552 { 553 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 554 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 555 } 556 557 #define SK_HASH_BITS 6 558 559 u_int32_t 560 sk_xmac_hash(caddr_t addr) 561 { 562 u_int32_t crc; 563 564 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 565 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 566 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 567 return crc; 568 } 569 570 u_int32_t 571 sk_yukon_hash(caddr_t addr) 572 { 573 u_int32_t crc; 574 575 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 576 crc &= ((1 << SK_HASH_BITS) - 1); 577 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 578 return crc; 579 } 580 581 void 582 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 583 { 584 int base = XM_RXFILT_ENTRY(slot); 585 586 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 587 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 588 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 589 } 590 591 void 592 sk_setmulti(struct sk_if_softc *sc_if) 593 { 594 struct sk_softc *sc = sc_if->sk_softc; 595 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 596 u_int32_t hashes[2] = { 0, 0 }; 597 int h = 0, i; 598 struct ethercom *ec = &sc_if->sk_ethercom; 599 struct ether_multi *enm; 600 struct ether_multistep step; 601 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 602 603 /* First, zot all the existing filters. */ 604 switch (sc->sk_type) { 605 case SK_GENESIS: 606 for (i = 1; i < XM_RXFILT_MAX; i++) 607 sk_setfilt(sc_if, (caddr_t)&dummy, i); 608 609 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 610 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 611 break; 612 case SK_YUKON: 613 case SK_YUKON_LITE: 614 case SK_YUKON_LP: 615 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 616 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 617 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 618 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 619 break; 620 } 621 622 /* Now program new ones. */ 623 allmulti: 624 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 625 hashes[0] = 0xFFFFFFFF; 626 hashes[1] = 0xFFFFFFFF; 627 } else { 628 i = 1; 629 /* First find the tail of the list. */ 630 ETHER_FIRST_MULTI(step, ec, enm); 631 while (enm != NULL) { 632 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 633 ETHER_ADDR_LEN)) { 634 ifp->if_flags |= IFF_ALLMULTI; 635 goto allmulti; 636 } 637 DPRINTFN(2,("multicast address %s\n", 638 ether_sprintf(enm->enm_addrlo))); 639 /* 640 * Program the first XM_RXFILT_MAX multicast groups 641 * into the perfect filter. For all others, 642 * use the hash table. 643 */ 644 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 645 sk_setfilt(sc_if, enm->enm_addrlo, i); 646 i++; 647 } 648 else { 649 switch (sc->sk_type) { 650 case SK_GENESIS: 651 h = sk_xmac_hash(enm->enm_addrlo); 652 break; 653 case SK_YUKON: 654 case SK_YUKON_LITE: 655 case SK_YUKON_LP: 656 h = sk_yukon_hash(enm->enm_addrlo); 657 break; 658 } 659 if (h < 32) 660 hashes[0] |= (1 << h); 661 else 662 hashes[1] |= (1 << (h - 32)); 663 } 664 665 ETHER_NEXT_MULTI(step, enm); 666 } 667 } 668 669 switch (sc->sk_type) { 670 case SK_GENESIS: 671 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 672 XM_MODE_RX_USE_PERFECT); 673 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 674 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 675 break; 676 case SK_YUKON: 677 case SK_YUKON_LITE: 678 case SK_YUKON_LP: 679 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 680 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 681 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 682 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 683 break; 684 } 685 } 686 687 int 688 sk_init_rx_ring(struct sk_if_softc *sc_if) 689 { 690 struct sk_chain_data *cd = &sc_if->sk_cdata; 691 struct sk_ring_data *rd = sc_if->sk_rdata; 692 int i; 693 694 bzero((char *)rd->sk_rx_ring, 695 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 696 697 for (i = 0; i < SK_RX_RING_CNT; i++) { 698 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 699 if (i == (SK_RX_RING_CNT - 1)) { 700 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 701 rd->sk_rx_ring[i].sk_next = 702 htole32(SK_RX_RING_ADDR(sc_if, 0)); 703 } else { 704 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 705 rd->sk_rx_ring[i].sk_next = 706 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 707 } 708 } 709 710 for (i = 0; i < SK_RX_RING_CNT; i++) { 711 if (sk_newbuf(sc_if, i, NULL, 712 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 713 aprint_error("%s: failed alloc of %dth mbuf\n", 714 sc_if->sk_dev.dv_xname, i); 715 return ENOBUFS; 716 } 717 } 718 sc_if->sk_cdata.sk_rx_prod = 0; 719 sc_if->sk_cdata.sk_rx_cons = 0; 720 721 return 0; 722 } 723 724 int 725 sk_init_tx_ring(struct sk_if_softc *sc_if) 726 { 727 struct sk_chain_data *cd = &sc_if->sk_cdata; 728 struct sk_ring_data *rd = sc_if->sk_rdata; 729 int i; 730 731 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 732 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 733 734 for (i = 0; i < SK_TX_RING_CNT; i++) { 735 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 736 if (i == (SK_TX_RING_CNT - 1)) { 737 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 738 rd->sk_tx_ring[i].sk_next = 739 htole32(SK_TX_RING_ADDR(sc_if, 0)); 740 } else { 741 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 742 rd->sk_tx_ring[i].sk_next = 743 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 744 } 745 } 746 747 sc_if->sk_cdata.sk_tx_prod = 0; 748 sc_if->sk_cdata.sk_tx_cons = 0; 749 sc_if->sk_cdata.sk_tx_cnt = 0; 750 751 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 752 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 753 754 return 0; 755 } 756 757 int 758 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 759 bus_dmamap_t dmamap) 760 { 761 struct mbuf *m_new = NULL; 762 struct sk_chain *c; 763 struct sk_rx_desc *r; 764 765 if (m == NULL) { 766 caddr_t buf = NULL; 767 768 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 769 if (m_new == NULL) { 770 aprint_error("%s: no memory for rx list -- " 771 "packet dropped!\n", sc_if->sk_dev.dv_xname); 772 return ENOBUFS; 773 } 774 775 /* Allocate the jumbo buffer */ 776 buf = sk_jalloc(sc_if); 777 if (buf == NULL) { 778 m_freem(m_new); 779 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 780 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 781 return ENOBUFS; 782 } 783 784 /* Attach the buffer to the mbuf */ 785 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 786 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 787 788 } else { 789 /* 790 * We're re-using a previously allocated mbuf; 791 * be sure to re-init pointers and lengths to 792 * default values. 793 */ 794 m_new = m; 795 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 796 m_new->m_data = m_new->m_ext.ext_buf; 797 } 798 m_adj(m_new, ETHER_ALIGN); 799 800 c = &sc_if->sk_cdata.sk_rx_chain[i]; 801 r = c->sk_desc; 802 c->sk_mbuf = m_new; 803 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 804 (((vaddr_t)m_new->m_data 805 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 806 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 807 808 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 809 810 return 0; 811 } 812 813 /* 814 * Memory management for jumbo frames. 815 */ 816 817 int 818 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 819 { 820 struct sk_softc *sc = sc_if->sk_softc; 821 caddr_t ptr, kva; 822 bus_dma_segment_t seg; 823 int i, rseg, state, error; 824 struct sk_jpool_entry *entry; 825 826 state = error = 0; 827 828 /* Grab a big chunk o' storage. */ 829 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 830 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 831 aprint_error("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 832 return ENOBUFS; 833 } 834 835 state = 1; 836 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, &kva, 837 BUS_DMA_NOWAIT)) { 838 aprint_error("%s: can't map dma buffers (%d bytes)\n", 839 sc->sk_dev.dv_xname, SK_JMEM); 840 error = ENOBUFS; 841 goto out; 842 } 843 844 state = 2; 845 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 846 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 847 aprint_error("%s: can't create dma map\n", sc->sk_dev.dv_xname); 848 error = ENOBUFS; 849 goto out; 850 } 851 852 state = 3; 853 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 854 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 855 aprint_error("%s: can't load dma map\n", sc->sk_dev.dv_xname); 856 error = ENOBUFS; 857 goto out; 858 } 859 860 state = 4; 861 sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva; 862 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 863 864 LIST_INIT(&sc_if->sk_jfree_listhead); 865 LIST_INIT(&sc_if->sk_jinuse_listhead); 866 867 /* 868 * Now divide it up into 9K pieces and save the addresses 869 * in an array. 870 */ 871 ptr = sc_if->sk_cdata.sk_jumbo_buf; 872 for (i = 0; i < SK_JSLOTS; i++) { 873 sc_if->sk_cdata.sk_jslots[i] = ptr; 874 ptr += SK_JLEN; 875 entry = malloc(sizeof(struct sk_jpool_entry), 876 M_DEVBUF, M_NOWAIT); 877 if (entry == NULL) { 878 aprint_error("%s: no memory for jumbo buffer queue!\n", 879 sc->sk_dev.dv_xname); 880 error = ENOBUFS; 881 goto out; 882 } 883 entry->slot = i; 884 if (i) 885 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 886 entry, jpool_entries); 887 else 888 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 889 entry, jpool_entries); 890 } 891 out: 892 if (error != 0) { 893 switch (state) { 894 case 4: 895 bus_dmamap_unload(sc->sc_dmatag, 896 sc_if->sk_cdata.sk_rx_jumbo_map); 897 case 3: 898 bus_dmamap_destroy(sc->sc_dmatag, 899 sc_if->sk_cdata.sk_rx_jumbo_map); 900 case 2: 901 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 902 case 1: 903 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 904 break; 905 default: 906 break; 907 } 908 } 909 910 return error; 911 } 912 913 /* 914 * Allocate a jumbo buffer. 915 */ 916 void * 917 sk_jalloc(struct sk_if_softc *sc_if) 918 { 919 struct sk_jpool_entry *entry; 920 921 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 922 923 if (entry == NULL) 924 return NULL; 925 926 LIST_REMOVE(entry, jpool_entries); 927 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 928 return sc_if->sk_cdata.sk_jslots[entry->slot]; 929 } 930 931 /* 932 * Release a jumbo buffer. 933 */ 934 void 935 sk_jfree(struct mbuf *m, caddr_t buf, size_t size, void *arg) 936 { 937 struct sk_jpool_entry *entry; 938 struct sk_if_softc *sc; 939 int i, s; 940 941 /* Extract the softc struct pointer. */ 942 sc = (struct sk_if_softc *)arg; 943 944 if (sc == NULL) 945 panic("sk_jfree: can't find softc pointer!"); 946 947 /* calculate the slot this buffer belongs to */ 948 949 i = ((vaddr_t)buf 950 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 951 952 if ((i < 0) || (i >= SK_JSLOTS)) 953 panic("sk_jfree: asked to free buffer that we don't manage!"); 954 955 s = splvm(); 956 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 957 if (entry == NULL) 958 panic("sk_jfree: buffer not in use!"); 959 entry->slot = i; 960 LIST_REMOVE(entry, jpool_entries); 961 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 962 963 if (__predict_true(m != NULL)) 964 pool_cache_put(&mbpool_cache, m); 965 splx(s); 966 } 967 968 /* 969 * Set media options. 970 */ 971 int 972 sk_ifmedia_upd(struct ifnet *ifp) 973 { 974 struct sk_if_softc *sc_if = ifp->if_softc; 975 976 (void) sk_init(ifp); 977 mii_mediachg(&sc_if->sk_mii); 978 return 0; 979 } 980 981 /* 982 * Report current media status. 983 */ 984 void 985 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 986 { 987 struct sk_if_softc *sc_if = ifp->if_softc; 988 989 mii_pollstat(&sc_if->sk_mii); 990 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 991 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 992 } 993 994 int 995 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 996 { 997 struct sk_if_softc *sc_if = ifp->if_softc; 998 struct sk_softc *sc = sc_if->sk_softc; 999 struct ifreq *ifr = (struct ifreq *) data; 1000 struct mii_data *mii; 1001 int s, error = 0; 1002 1003 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1004 1005 s = splnet(); 1006 1007 switch (command) { 1008 1009 case SIOCSIFFLAGS: 1010 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1011 if (ifp->if_flags & IFF_UP) { 1012 if (ifp->if_flags & IFF_RUNNING && 1013 ifp->if_flags & IFF_PROMISC && 1014 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1015 switch (sc->sk_type) { 1016 case SK_GENESIS: 1017 SK_XM_SETBIT_4(sc_if, XM_MODE, 1018 XM_MODE_RX_PROMISC); 1019 break; 1020 case SK_YUKON: 1021 case SK_YUKON_LITE: 1022 case SK_YUKON_LP: 1023 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1024 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1025 break; 1026 } 1027 sk_setmulti(sc_if); 1028 } else if (ifp->if_flags & IFF_RUNNING && 1029 !(ifp->if_flags & IFF_PROMISC) && 1030 sc_if->sk_if_flags & IFF_PROMISC) { 1031 switch (sc->sk_type) { 1032 case SK_GENESIS: 1033 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1034 XM_MODE_RX_PROMISC); 1035 break; 1036 case SK_YUKON: 1037 case SK_YUKON_LITE: 1038 case SK_YUKON_LP: 1039 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1040 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1041 break; 1042 } 1043 1044 sk_setmulti(sc_if); 1045 } else 1046 (void) sk_init(ifp); 1047 } else { 1048 if (ifp->if_flags & IFF_RUNNING) 1049 sk_stop(ifp,0); 1050 } 1051 sc_if->sk_if_flags = ifp->if_flags; 1052 error = 0; 1053 break; 1054 1055 case SIOCGIFMEDIA: 1056 case SIOCSIFMEDIA: 1057 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 1058 mii = &sc_if->sk_mii; 1059 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1060 break; 1061 default: 1062 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1063 error = ether_ioctl(ifp, command, data); 1064 1065 if ( error == ENETRESET) { 1066 if (ifp->if_flags & IFF_RUNNING) { 1067 sk_setmulti(sc_if); 1068 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1069 } 1070 error = 0; 1071 } else if ( error ) { 1072 splx(s); 1073 return error; 1074 } 1075 break; 1076 } 1077 1078 splx(s); 1079 return error; 1080 } 1081 1082 void 1083 sk_update_int_mod(struct sk_softc *sc) 1084 { 1085 u_int32_t imtimer_ticks; 1086 1087 /* 1088 * Configure interrupt moderation. The moderation timer 1089 * defers interrupts specified in the interrupt moderation 1090 * timer mask based on the timeout specified in the interrupt 1091 * moderation timer init register. Each bit in the timer 1092 * register represents one tick, so to specify a timeout in 1093 * microseconds, we have to multiply by the correct number of 1094 * ticks-per-microsecond. 1095 */ 1096 switch (sc->sk_type) { 1097 case SK_GENESIS: 1098 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1099 break; 1100 case SK_YUKON_EC: 1101 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1102 break; 1103 default: 1104 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1105 } 1106 aprint_verbose("%s: interrupt moderation is %d us\n", 1107 sc->sk_dev.dv_xname, sc->sk_int_mod); 1108 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1109 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1110 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1111 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1112 sc->sk_int_mod_pending = 0; 1113 } 1114 1115 /* 1116 * Lookup: Check the PCI vendor and device, and return a pointer to 1117 * The structure if the IDs match against our list. 1118 */ 1119 1120 static const struct sk_product * 1121 sk_lookup(const struct pci_attach_args *pa) 1122 { 1123 const struct sk_product *psk; 1124 1125 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1126 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1127 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1128 return psk; 1129 } 1130 return NULL; 1131 } 1132 1133 /* 1134 * Probe for a SysKonnect GEnesis chip. 1135 */ 1136 1137 int 1138 skc_probe(struct device *parent, struct cfdata *match, 1139 void *aux) 1140 { 1141 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1142 const struct sk_product *psk; 1143 pcireg_t subid; 1144 1145 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1146 1147 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1148 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1149 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1150 subid == SK_LINKSYS_EG1032_SUBID) 1151 return 1; 1152 1153 if ((psk = sk_lookup(pa))) { 1154 return 1; 1155 } 1156 return 0; 1157 } 1158 1159 /* 1160 * Force the GEnesis into reset, then bring it out of reset. 1161 */ 1162 void sk_reset(struct sk_softc *sc) 1163 { 1164 DPRINTFN(2, ("sk_reset\n")); 1165 1166 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1167 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1168 if (SK_YUKON_FAMILY(sc->sk_type)) 1169 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1170 1171 DELAY(1000); 1172 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1173 DELAY(2); 1174 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1175 if (SK_YUKON_FAMILY(sc->sk_type)) 1176 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1177 1178 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1179 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1180 CSR_READ_2(sc, SK_LINK_CTRL))); 1181 1182 if (sc->sk_type == SK_GENESIS) { 1183 /* Configure packet arbiter */ 1184 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1185 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1186 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1187 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1188 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1189 } 1190 1191 /* Enable RAM interface */ 1192 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1193 1194 sk_update_int_mod(sc); 1195 } 1196 1197 int 1198 sk_probe(struct device *parent, struct cfdata *match, 1199 void *aux) 1200 { 1201 struct skc_attach_args *sa = aux; 1202 1203 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1204 return 0; 1205 1206 return 1; 1207 } 1208 1209 /* 1210 * Each XMAC chip is attached as a separate logical IP interface. 1211 * Single port cards will have only one logical interface of course. 1212 */ 1213 void 1214 sk_attach(struct device *parent, struct device *self, void *aux) 1215 { 1216 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1217 struct sk_softc *sc = (struct sk_softc *)parent; 1218 struct skc_attach_args *sa = aux; 1219 struct sk_txmap_entry *entry; 1220 struct ifnet *ifp; 1221 bus_dma_segment_t seg; 1222 bus_dmamap_t dmamap; 1223 caddr_t kva; 1224 int i, rseg; 1225 1226 sc_if->sk_port = sa->skc_port; 1227 sc_if->sk_softc = sc; 1228 sc->sk_if[sa->skc_port] = sc_if; 1229 1230 if (sa->skc_port == SK_PORT_A) 1231 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1232 if (sa->skc_port == SK_PORT_B) 1233 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1234 1235 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1236 1237 /* 1238 * Get station address for this interface. Note that 1239 * dual port cards actually come with three station 1240 * addresses: one for each port, plus an extra. The 1241 * extra one is used by the SysKonnect driver software 1242 * as a 'virtual' station address for when both ports 1243 * are operating in failover mode. Currently we don't 1244 * use this extra address. 1245 */ 1246 for (i = 0; i < ETHER_ADDR_LEN; i++) 1247 sc_if->sk_enaddr[i] = 1248 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1249 1250 1251 aprint_normal(": Ethernet address %s\n", 1252 ether_sprintf(sc_if->sk_enaddr)); 1253 1254 /* 1255 * Set up RAM buffer addresses. The NIC will have a certain 1256 * amount of SRAM on it, somewhere between 512K and 2MB. We 1257 * need to divide this up a) between the transmitter and 1258 * receiver and b) between the two XMACs, if this is a 1259 * dual port NIC. Our algorithm is to divide up the memory 1260 * evenly so that everyone gets a fair share. 1261 */ 1262 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1263 u_int32_t chunk, val; 1264 1265 chunk = sc->sk_ramsize / 2; 1266 val = sc->sk_rboff / sizeof(u_int64_t); 1267 sc_if->sk_rx_ramstart = val; 1268 val += (chunk / sizeof(u_int64_t)); 1269 sc_if->sk_rx_ramend = val - 1; 1270 sc_if->sk_tx_ramstart = val; 1271 val += (chunk / sizeof(u_int64_t)); 1272 sc_if->sk_tx_ramend = val - 1; 1273 } else { 1274 u_int32_t chunk, val; 1275 1276 chunk = sc->sk_ramsize / 4; 1277 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1278 sizeof(u_int64_t); 1279 sc_if->sk_rx_ramstart = val; 1280 val += (chunk / sizeof(u_int64_t)); 1281 sc_if->sk_rx_ramend = val - 1; 1282 sc_if->sk_tx_ramstart = val; 1283 val += (chunk / sizeof(u_int64_t)); 1284 sc_if->sk_tx_ramend = val - 1; 1285 } 1286 1287 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1288 " tx_ramstart=%#x tx_ramend=%#x\n", 1289 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1290 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1291 1292 /* Read and save PHY type and set PHY address */ 1293 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1294 switch (sc_if->sk_phytype) { 1295 case SK_PHYTYPE_XMAC: 1296 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1297 break; 1298 case SK_PHYTYPE_BCOM: 1299 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1300 break; 1301 case SK_PHYTYPE_MARV_COPPER: 1302 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1303 break; 1304 default: 1305 aprint_error("%s: unsupported PHY type: %d\n", 1306 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1307 return; 1308 } 1309 1310 /* Allocate the descriptor queues. */ 1311 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1312 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1313 aprint_error("%s: can't alloc rx buffers\n", 1314 sc->sk_dev.dv_xname); 1315 goto fail; 1316 } 1317 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1318 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1319 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1320 sc_if->sk_dev.dv_xname, 1321 (u_long) sizeof(struct sk_ring_data)); 1322 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1323 goto fail; 1324 } 1325 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1326 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1327 &sc_if->sk_ring_map)) { 1328 aprint_error("%s: can't create dma map\n", 1329 sc_if->sk_dev.dv_xname); 1330 bus_dmamem_unmap(sc->sc_dmatag, kva, 1331 sizeof(struct sk_ring_data)); 1332 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1333 goto fail; 1334 } 1335 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1336 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1337 aprint_error("%s: can't load dma map\n", 1338 sc_if->sk_dev.dv_xname); 1339 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1340 bus_dmamem_unmap(sc->sc_dmatag, kva, 1341 sizeof(struct sk_ring_data)); 1342 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1343 goto fail; 1344 } 1345 1346 for (i = 0; i < SK_RX_RING_CNT; i++) 1347 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1348 1349 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1350 for (i = 0; i < SK_TX_RING_CNT; i++) { 1351 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1352 1353 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1354 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1355 aprint_error("%s: Can't create TX dmamap\n", 1356 sc_if->sk_dev.dv_xname); 1357 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1358 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1359 bus_dmamem_unmap(sc->sc_dmatag, kva, 1360 sizeof(struct sk_ring_data)); 1361 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1362 goto fail; 1363 } 1364 1365 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1366 if (!entry) { 1367 aprint_error("%s: Can't alloc txmap entry\n", 1368 sc_if->sk_dev.dv_xname); 1369 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1370 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1371 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1372 bus_dmamem_unmap(sc->sc_dmatag, kva, 1373 sizeof(struct sk_ring_data)); 1374 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1375 goto fail; 1376 } 1377 entry->dmamap = dmamap; 1378 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1379 } 1380 1381 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1382 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1383 1384 ifp = &sc_if->sk_ethercom.ec_if; 1385 /* Try to allocate memory for jumbo buffers. */ 1386 if (sk_alloc_jumbo_mem(sc_if)) { 1387 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1388 goto fail; 1389 } 1390 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1391 | ETHERCAP_JUMBO_MTU; 1392 1393 ifp->if_softc = sc_if; 1394 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1395 ifp->if_ioctl = sk_ioctl; 1396 ifp->if_start = sk_start; 1397 ifp->if_stop = sk_stop; 1398 ifp->if_init = sk_init; 1399 ifp->if_watchdog = sk_watchdog; 1400 ifp->if_capabilities = 0; 1401 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1402 IFQ_SET_READY(&ifp->if_snd); 1403 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1404 1405 /* 1406 * Do miibus setup. 1407 */ 1408 switch (sc->sk_type) { 1409 case SK_GENESIS: 1410 sk_init_xmac(sc_if); 1411 break; 1412 case SK_YUKON: 1413 case SK_YUKON_LITE: 1414 case SK_YUKON_LP: 1415 sk_init_yukon(sc_if); 1416 break; 1417 default: 1418 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1419 sc->sk_type); 1420 } 1421 1422 DPRINTFN(2, ("sk_attach: 1\n")); 1423 1424 sc_if->sk_mii.mii_ifp = ifp; 1425 switch (sc->sk_type) { 1426 case SK_GENESIS: 1427 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1428 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1429 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1430 break; 1431 case SK_YUKON: 1432 case SK_YUKON_LITE: 1433 case SK_YUKON_LP: 1434 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1435 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1436 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1437 break; 1438 } 1439 1440 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1441 sk_ifmedia_upd, sk_ifmedia_sts); 1442 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1443 MII_OFFSET_ANY, 0); 1444 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1445 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1446 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1447 0, NULL); 1448 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1449 } else 1450 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1451 1452 callout_init(&sc_if->sk_tick_ch); 1453 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1454 1455 DPRINTFN(2, ("sk_attach: 1\n")); 1456 1457 /* 1458 * Call MI attach routines. 1459 */ 1460 if_attach(ifp); 1461 1462 ether_ifattach(ifp, sc_if->sk_enaddr); 1463 1464 #if NRND > 0 1465 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1466 RND_TYPE_NET, 0); 1467 #endif 1468 1469 DPRINTFN(2, ("sk_attach: end\n")); 1470 1471 return; 1472 1473 fail: 1474 sc->sk_if[sa->skc_port] = NULL; 1475 } 1476 1477 int 1478 skcprint(void *aux, const char *pnp) 1479 { 1480 struct skc_attach_args *sa = aux; 1481 1482 if (pnp) 1483 aprint_normal("sk port %c at %s", 1484 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1485 else 1486 aprint_normal(" port %c", 1487 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1488 return UNCONF; 1489 } 1490 1491 /* 1492 * Attach the interface. Allocate softc structures, do ifmedia 1493 * setup and ethernet/BPF attach. 1494 */ 1495 void 1496 skc_attach(struct device *parent, struct device *self, void *aux) 1497 { 1498 struct sk_softc *sc = (struct sk_softc *)self; 1499 struct pci_attach_args *pa = aux; 1500 struct skc_attach_args skca; 1501 pci_chipset_tag_t pc = pa->pa_pc; 1502 #ifndef SK_USEIOSPACE 1503 pcireg_t memtype; 1504 #endif 1505 pci_intr_handle_t ih; 1506 const char *intrstr = NULL; 1507 bus_addr_t iobase; 1508 bus_size_t iosize; 1509 int rc, sk_nodenum; 1510 u_int32_t command; 1511 const char *revstr; 1512 const struct sysctlnode *node; 1513 1514 DPRINTFN(2, ("begin skc_attach\n")); 1515 1516 /* 1517 * Handle power management nonsense. 1518 */ 1519 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1520 1521 if (command == 0x01) { 1522 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1523 if (command & SK_PSTATE_MASK) { 1524 u_int32_t xiobase, membase, irq; 1525 1526 /* Save important PCI config data. */ 1527 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1528 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1529 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1530 1531 /* Reset the power state. */ 1532 aprint_normal("%s chip is in D%d power mode " 1533 "-- setting to D0\n", sc->sk_dev.dv_xname, 1534 command & SK_PSTATE_MASK); 1535 command &= 0xFFFFFFFC; 1536 pci_conf_write(pc, pa->pa_tag, 1537 SK_PCI_PWRMGMTCTRL, command); 1538 1539 /* Restore PCI config data. */ 1540 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1541 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1542 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1543 } 1544 } 1545 1546 /* 1547 * Map control/status registers. 1548 */ 1549 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1550 command |= PCI_COMMAND_IO_ENABLE | 1551 PCI_COMMAND_MEM_ENABLE | 1552 PCI_COMMAND_MASTER_ENABLE; 1553 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1554 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1555 1556 #ifdef SK_USEIOSPACE 1557 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1558 aprint_error(": failed to enable I/O ports!\n"); 1559 return; 1560 } 1561 /* 1562 * Map control/status registers. 1563 */ 1564 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1565 &sc->sk_btag, &sc->sk_bhandle, 1566 &iobase, &iosize)) { 1567 aprint_error(": can't find i/o space\n"); 1568 return; 1569 } 1570 #else 1571 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1572 aprint_error(": failed to enable memory mapping!\n"); 1573 return; 1574 } 1575 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1576 switch (memtype) { 1577 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1578 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1579 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1580 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1581 &iobase, &iosize) == 0) 1582 break; 1583 default: 1584 aprint_error("%s: can't find mem space\n", 1585 sc->sk_dev.dv_xname); 1586 return; 1587 } 1588 1589 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1590 #endif 1591 sc->sc_dmatag = pa->pa_dmat; 1592 1593 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1594 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1595 1596 /* bail out here if chip is not recognized */ 1597 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1598 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1599 goto fail; 1600 } 1601 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1602 1603 /* Allocate interrupt */ 1604 if (pci_intr_map(pa, &ih)) { 1605 aprint_error(": couldn't map interrupt\n"); 1606 goto fail; 1607 } 1608 1609 intrstr = pci_intr_string(pc, ih); 1610 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1611 if (sc->sk_intrhand == NULL) { 1612 aprint_error(": couldn't establish interrupt"); 1613 if (intrstr != NULL) 1614 aprint_normal(" at %s", intrstr); 1615 goto fail; 1616 } 1617 aprint_normal(": %s\n", intrstr); 1618 1619 /* Reset the adapter. */ 1620 sk_reset(sc); 1621 1622 /* Read and save vital product data from EEPROM. */ 1623 sk_vpd_read(sc); 1624 1625 if (sc->sk_type == SK_GENESIS) { 1626 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1627 /* Read and save RAM size and RAMbuffer offset */ 1628 switch (val) { 1629 case SK_RAMSIZE_512K_64: 1630 sc->sk_ramsize = 0x80000; 1631 sc->sk_rboff = SK_RBOFF_0; 1632 break; 1633 case SK_RAMSIZE_1024K_64: 1634 sc->sk_ramsize = 0x100000; 1635 sc->sk_rboff = SK_RBOFF_80000; 1636 break; 1637 case SK_RAMSIZE_1024K_128: 1638 sc->sk_ramsize = 0x100000; 1639 sc->sk_rboff = SK_RBOFF_0; 1640 break; 1641 case SK_RAMSIZE_2048K_128: 1642 sc->sk_ramsize = 0x200000; 1643 sc->sk_rboff = SK_RBOFF_0; 1644 break; 1645 default: 1646 aprint_error("%s: unknown ram size: %d\n", 1647 sc->sk_dev.dv_xname, val); 1648 goto fail_1; 1649 break; 1650 } 1651 1652 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1653 sc->sk_ramsize, sc->sk_ramsize / 1024, 1654 sc->sk_rboff)); 1655 } else { 1656 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1657 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1658 sc->sk_rboff = SK_RBOFF_0; 1659 1660 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1661 sc->sk_ramsize / 1024, sc->sk_ramsize, 1662 sc->sk_rboff)); 1663 } 1664 1665 /* Read and save physical media type */ 1666 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1667 case SK_PMD_1000BASESX: 1668 sc->sk_pmd = IFM_1000_SX; 1669 break; 1670 case SK_PMD_1000BASELX: 1671 sc->sk_pmd = IFM_1000_LX; 1672 break; 1673 case SK_PMD_1000BASECX: 1674 sc->sk_pmd = IFM_1000_CX; 1675 break; 1676 case SK_PMD_1000BASETX: 1677 case SK_PMD_1000BASETX_ALT: 1678 sc->sk_pmd = IFM_1000_T; 1679 break; 1680 default: 1681 aprint_error("%s: unknown media type: 0x%x\n", 1682 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1683 goto fail_1; 1684 } 1685 1686 /* determine whether to name it with vpd or just make it up */ 1687 /* Marvell Yukon VPD's can freqently be bogus */ 1688 1689 switch (pa->pa_id) { 1690 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1691 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1692 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1693 case PCI_PRODUCT_3COM_3C940: 1694 case PCI_PRODUCT_DLINK_DGE530T: 1695 case PCI_PRODUCT_DLINK_DGE560T: 1696 case PCI_PRODUCT_DLINK_DGE560T_2: 1697 case PCI_PRODUCT_LINKSYS_EG1032: 1698 case PCI_PRODUCT_LINKSYS_EG1064: 1699 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1700 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1701 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1702 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1703 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1704 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1705 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1706 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1707 sc->sk_name = sc->sk_vpd_prodname; 1708 break; 1709 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1710 /* whoops yukon vpd prodname bears no resemblance to reality */ 1711 switch (sc->sk_type) { 1712 case SK_GENESIS: 1713 sc->sk_name = sc->sk_vpd_prodname; 1714 break; 1715 case SK_YUKON: 1716 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1717 break; 1718 case SK_YUKON_LITE: 1719 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1720 break; 1721 case SK_YUKON_LP: 1722 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1723 break; 1724 default: 1725 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1726 } 1727 1728 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1729 1730 if ( sc->sk_type == SK_YUKON ) { 1731 uint32_t flashaddr; 1732 uint8_t testbyte; 1733 1734 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1735 1736 /* test Flash-Address Register */ 1737 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1738 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1739 1740 if (testbyte != 0) { 1741 /* this is yukon lite Rev. A0 */ 1742 sc->sk_type = SK_YUKON_LITE; 1743 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1744 /* restore Flash-Address Register */ 1745 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1746 } 1747 } 1748 break; 1749 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1750 sc->sk_name = sc->sk_vpd_prodname; 1751 break; 1752 default: 1753 sc->sk_name = "Unknown Marvell"; 1754 } 1755 1756 1757 if ( sc->sk_type == SK_YUKON_LITE ) { 1758 switch (sc->sk_rev) { 1759 case SK_YUKON_LITE_REV_A0: 1760 revstr = "A0"; 1761 break; 1762 case SK_YUKON_LITE_REV_A1: 1763 revstr = "A1"; 1764 break; 1765 case SK_YUKON_LITE_REV_A3: 1766 revstr = "A3"; 1767 break; 1768 default: 1769 revstr = ""; 1770 } 1771 } else { 1772 revstr = ""; 1773 } 1774 1775 /* Announce the product name. */ 1776 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1777 sc->sk_name, revstr, sc->sk_rev); 1778 1779 skca.skc_port = SK_PORT_A; 1780 (void)config_found(&sc->sk_dev, &skca, skcprint); 1781 1782 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1783 skca.skc_port = SK_PORT_B; 1784 (void)config_found(&sc->sk_dev, &skca, skcprint); 1785 } 1786 1787 /* Turn on the 'driver is loaded' LED. */ 1788 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1789 1790 /* skc sysctl setup */ 1791 1792 sc->sk_int_mod = SK_IM_DEFAULT; 1793 sc->sk_int_mod_pending = 0; 1794 1795 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1796 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1797 SYSCTL_DESCR("skc per-controller controls"), 1798 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1799 CTL_EOL)) != 0) { 1800 aprint_normal("%s: couldn't create sysctl node\n", 1801 sc->sk_dev.dv_xname); 1802 goto fail_1; 1803 } 1804 1805 sk_nodenum = node->sysctl_num; 1806 1807 /* interrupt moderation time in usecs */ 1808 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1809 CTLFLAG_READWRITE, 1810 CTLTYPE_INT, "int_mod", 1811 SYSCTL_DESCR("sk interrupt moderation timer"), 1812 sk_sysctl_handler, 0, sc, 1813 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1814 CTL_EOL)) != 0) { 1815 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1816 sc->sk_dev.dv_xname); 1817 goto fail_1; 1818 } 1819 1820 return; 1821 1822 fail_1: 1823 pci_intr_disestablish(pc, sc->sk_intrhand); 1824 fail: 1825 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1826 } 1827 1828 int 1829 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1830 { 1831 struct sk_softc *sc = sc_if->sk_softc; 1832 struct sk_tx_desc *f = NULL; 1833 u_int32_t frag, cur, cnt = 0, sk_ctl; 1834 int i; 1835 struct sk_txmap_entry *entry; 1836 bus_dmamap_t txmap; 1837 1838 DPRINTFN(3, ("sk_encap\n")); 1839 1840 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1841 if (entry == NULL) { 1842 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1843 return ENOBUFS; 1844 } 1845 txmap = entry->dmamap; 1846 1847 cur = frag = *txidx; 1848 1849 #ifdef SK_DEBUG 1850 if (skdebug >= 3) 1851 sk_dump_mbuf(m_head); 1852 #endif 1853 1854 /* 1855 * Start packing the mbufs in this chain into 1856 * the fragment pointers. Stop when we run out 1857 * of fragments or hit the end of the mbuf chain. 1858 */ 1859 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1860 BUS_DMA_NOWAIT)) { 1861 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1862 return ENOBUFS; 1863 } 1864 1865 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1866 1867 /* Sync the DMA map. */ 1868 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1869 BUS_DMASYNC_PREWRITE); 1870 1871 for (i = 0; i < txmap->dm_nsegs; i++) { 1872 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1873 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1874 return ENOBUFS; 1875 } 1876 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1877 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1878 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1879 if (cnt == 0) 1880 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1881 else 1882 sk_ctl |= SK_TXCTL_OWN; 1883 f->sk_ctl = htole32(sk_ctl); 1884 cur = frag; 1885 SK_INC(frag, SK_TX_RING_CNT); 1886 cnt++; 1887 } 1888 1889 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1890 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1891 1892 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1893 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1894 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1895 1896 /* Sync descriptors before handing to chip */ 1897 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1898 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1899 1900 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1901 htole32(SK_TXCTL_OWN); 1902 1903 /* Sync first descriptor to hand it off */ 1904 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1905 1906 sc_if->sk_cdata.sk_tx_cnt += cnt; 1907 1908 #ifdef SK_DEBUG 1909 if (skdebug >= 3) { 1910 struct sk_tx_desc *desc; 1911 u_int32_t idx; 1912 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1913 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1914 sk_dump_txdesc(desc, idx); 1915 } 1916 } 1917 #endif 1918 1919 *txidx = frag; 1920 1921 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1922 1923 return 0; 1924 } 1925 1926 void 1927 sk_start(struct ifnet *ifp) 1928 { 1929 struct sk_if_softc *sc_if = ifp->if_softc; 1930 struct sk_softc *sc = sc_if->sk_softc; 1931 struct mbuf *m_head = NULL; 1932 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1933 int pkts = 0; 1934 1935 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1936 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1937 1938 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1939 IFQ_POLL(&ifp->if_snd, m_head); 1940 if (m_head == NULL) 1941 break; 1942 1943 /* 1944 * Pack the data into the transmit ring. If we 1945 * don't have room, set the OACTIVE flag and wait 1946 * for the NIC to drain the ring. 1947 */ 1948 if (sk_encap(sc_if, m_head, &idx)) { 1949 ifp->if_flags |= IFF_OACTIVE; 1950 break; 1951 } 1952 1953 /* now we are committed to transmit the packet */ 1954 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1955 pkts++; 1956 1957 /* 1958 * If there's a BPF listener, bounce a copy of this frame 1959 * to him. 1960 */ 1961 #if NBPFILTER > 0 1962 if (ifp->if_bpf) 1963 bpf_mtap(ifp->if_bpf, m_head); 1964 #endif 1965 } 1966 if (pkts == 0) 1967 return; 1968 1969 /* Transmit */ 1970 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1971 sc_if->sk_cdata.sk_tx_prod = idx; 1972 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1973 1974 /* Set a timeout in case the chip goes out to lunch. */ 1975 ifp->if_timer = 5; 1976 } 1977 } 1978 1979 1980 void 1981 sk_watchdog(struct ifnet *ifp) 1982 { 1983 struct sk_if_softc *sc_if = ifp->if_softc; 1984 1985 /* 1986 * Reclaim first as there is a possibility of losing Tx completion 1987 * interrupts. 1988 */ 1989 sk_txeof(sc_if); 1990 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1991 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1992 1993 ifp->if_oerrors++; 1994 1995 sk_init(ifp); 1996 } 1997 } 1998 1999 void 2000 sk_shutdown(void * v) 2001 { 2002 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2003 struct sk_softc *sc = sc_if->sk_softc; 2004 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2005 2006 DPRINTFN(2, ("sk_shutdown\n")); 2007 sk_stop(ifp,1); 2008 2009 /* Turn off the 'driver is loaded' LED. */ 2010 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2011 2012 /* 2013 * Reset the GEnesis controller. Doing this should also 2014 * assert the resets on the attached XMAC(s). 2015 */ 2016 sk_reset(sc); 2017 } 2018 2019 void 2020 sk_rxeof(struct sk_if_softc *sc_if) 2021 { 2022 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2023 struct mbuf *m; 2024 struct sk_chain *cur_rx; 2025 struct sk_rx_desc *cur_desc; 2026 int i, cur, total_len = 0; 2027 u_int32_t rxstat, sk_ctl; 2028 bus_dmamap_t dmamap; 2029 2030 i = sc_if->sk_cdata.sk_rx_prod; 2031 2032 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2033 2034 for (;;) { 2035 cur = i; 2036 2037 /* Sync the descriptor */ 2038 SK_CDRXSYNC(sc_if, cur, 2039 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2040 2041 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2042 if (sk_ctl & SK_RXCTL_OWN) { 2043 /* Invalidate the descriptor -- it's not ready yet */ 2044 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2045 sc_if->sk_cdata.sk_rx_prod = i; 2046 break; 2047 } 2048 2049 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2050 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2051 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2052 2053 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2054 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2055 2056 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2057 m = cur_rx->sk_mbuf; 2058 cur_rx->sk_mbuf = NULL; 2059 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2060 2061 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2062 2063 SK_INC(i, SK_RX_RING_CNT); 2064 2065 if (rxstat & XM_RXSTAT_ERRFRAME) { 2066 ifp->if_ierrors++; 2067 sk_newbuf(sc_if, cur, m, dmamap); 2068 continue; 2069 } 2070 2071 /* 2072 * Try to allocate a new jumbo buffer. If that 2073 * fails, copy the packet to mbufs and put the 2074 * jumbo buffer back in the ring so it can be 2075 * re-used. If allocating mbufs fails, then we 2076 * have to drop the packet. 2077 */ 2078 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2079 struct mbuf *m0; 2080 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2081 total_len + ETHER_ALIGN, 0, ifp, NULL); 2082 sk_newbuf(sc_if, cur, m, dmamap); 2083 if (m0 == NULL) { 2084 aprint_error("%s: no receive buffers " 2085 "available -- packet dropped!\n", 2086 sc_if->sk_dev.dv_xname); 2087 ifp->if_ierrors++; 2088 continue; 2089 } 2090 m_adj(m0, ETHER_ALIGN); 2091 m = m0; 2092 } else { 2093 m->m_pkthdr.rcvif = ifp; 2094 m->m_pkthdr.len = m->m_len = total_len; 2095 } 2096 2097 ifp->if_ipackets++; 2098 2099 #if NBPFILTER > 0 2100 if (ifp->if_bpf) 2101 bpf_mtap(ifp->if_bpf, m); 2102 #endif 2103 /* pass it on. */ 2104 (*ifp->if_input)(ifp, m); 2105 } 2106 } 2107 2108 void 2109 sk_txeof(struct sk_if_softc *sc_if) 2110 { 2111 struct sk_softc *sc = sc_if->sk_softc; 2112 struct sk_tx_desc *cur_tx; 2113 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2114 u_int32_t idx, sk_ctl; 2115 struct sk_txmap_entry *entry; 2116 2117 DPRINTFN(3, ("sk_txeof\n")); 2118 2119 /* 2120 * Go through our tx ring and free mbufs for those 2121 * frames that have been sent. 2122 */ 2123 idx = sc_if->sk_cdata.sk_tx_cons; 2124 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2125 SK_CDTXSYNC(sc_if, idx, 1, 2126 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2127 2128 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2129 sk_ctl = le32toh(cur_tx->sk_ctl); 2130 #ifdef SK_DEBUG 2131 if (skdebug >= 3) 2132 sk_dump_txdesc(cur_tx, idx); 2133 #endif 2134 if (sk_ctl & SK_TXCTL_OWN) { 2135 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2136 break; 2137 } 2138 if (sk_ctl & SK_TXCTL_LASTFRAG) 2139 ifp->if_opackets++; 2140 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2141 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2142 2143 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2144 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2145 2146 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2147 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2148 2149 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2150 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2151 link); 2152 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2153 } 2154 sc_if->sk_cdata.sk_tx_cnt--; 2155 SK_INC(idx, SK_TX_RING_CNT); 2156 } 2157 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2158 ifp->if_timer = 0; 2159 else /* nudge chip to keep tx ring moving */ 2160 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2161 2162 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2163 ifp->if_flags &= ~IFF_OACTIVE; 2164 2165 sc_if->sk_cdata.sk_tx_cons = idx; 2166 } 2167 2168 void 2169 sk_tick(void *xsc_if) 2170 { 2171 struct sk_if_softc *sc_if = xsc_if; 2172 struct mii_data *mii = &sc_if->sk_mii; 2173 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2174 int i; 2175 2176 DPRINTFN(3, ("sk_tick\n")); 2177 2178 if (!(ifp->if_flags & IFF_UP)) 2179 return; 2180 2181 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2182 sk_intr_bcom(sc_if); 2183 return; 2184 } 2185 2186 /* 2187 * According to SysKonnect, the correct way to verify that 2188 * the link has come back up is to poll bit 0 of the GPIO 2189 * register three times. This pin has the signal from the 2190 * link sync pin connected to it; if we read the same link 2191 * state 3 times in a row, we know the link is up. 2192 */ 2193 for (i = 0; i < 3; i++) { 2194 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2195 break; 2196 } 2197 2198 if (i != 3) { 2199 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2200 return; 2201 } 2202 2203 /* Turn the GP0 interrupt back on. */ 2204 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2205 SK_XM_READ_2(sc_if, XM_ISR); 2206 mii_tick(mii); 2207 mii_pollstat(mii); 2208 callout_stop(&sc_if->sk_tick_ch); 2209 } 2210 2211 void 2212 sk_intr_bcom(struct sk_if_softc *sc_if) 2213 { 2214 struct mii_data *mii = &sc_if->sk_mii; 2215 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2216 int status; 2217 2218 2219 DPRINTFN(3, ("sk_intr_bcom\n")); 2220 2221 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2222 2223 /* 2224 * Read the PHY interrupt register to make sure 2225 * we clear any pending interrupts. 2226 */ 2227 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2228 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2229 2230 if (!(ifp->if_flags & IFF_RUNNING)) { 2231 sk_init_xmac(sc_if); 2232 return; 2233 } 2234 2235 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2236 int lstat; 2237 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2238 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2239 2240 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2241 mii_mediachg(mii); 2242 /* Turn off the link LED. */ 2243 SK_IF_WRITE_1(sc_if, 0, 2244 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2245 sc_if->sk_link = 0; 2246 } else if (status & BRGPHY_ISR_LNK_CHG) { 2247 sk_xmac_miibus_writereg((struct device *)sc_if, 2248 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2249 mii_tick(mii); 2250 sc_if->sk_link = 1; 2251 /* Turn on the link LED. */ 2252 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2253 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2254 SK_LINKLED_BLINK_OFF); 2255 mii_pollstat(mii); 2256 } else { 2257 mii_tick(mii); 2258 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2259 } 2260 } 2261 2262 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2263 } 2264 2265 void 2266 sk_intr_xmac(struct sk_if_softc *sc_if) 2267 { 2268 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2269 2270 DPRINTFN(3, ("sk_intr_xmac\n")); 2271 2272 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2273 if (status & XM_ISR_GP0_SET) { 2274 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2275 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2276 } 2277 2278 if (status & XM_ISR_AUTONEG_DONE) { 2279 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2280 } 2281 } 2282 2283 if (status & XM_IMR_TX_UNDERRUN) 2284 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2285 2286 if (status & XM_IMR_RX_OVERRUN) 2287 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2288 } 2289 2290 void 2291 sk_intr_yukon(struct sk_if_softc *sc_if) 2292 { 2293 int status; 2294 2295 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2296 2297 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2298 } 2299 2300 int 2301 sk_intr(void *xsc) 2302 { 2303 struct sk_softc *sc = xsc; 2304 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2305 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2306 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2307 u_int32_t status; 2308 int claimed = 0; 2309 2310 if (sc_if0 != NULL) 2311 ifp0 = &sc_if0->sk_ethercom.ec_if; 2312 if (sc_if1 != NULL) 2313 ifp1 = &sc_if1->sk_ethercom.ec_if; 2314 2315 for (;;) { 2316 status = CSR_READ_4(sc, SK_ISSR); 2317 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2318 2319 if (!(status & sc->sk_intrmask)) 2320 break; 2321 2322 claimed = 1; 2323 2324 /* Handle receive interrupts first. */ 2325 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2326 sk_rxeof(sc_if0); 2327 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2328 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2329 } 2330 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2331 sk_rxeof(sc_if1); 2332 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2333 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2334 } 2335 2336 /* Then transmit interrupts. */ 2337 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2338 sk_txeof(sc_if0); 2339 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2340 SK_TXBMU_CLR_IRQ_EOF); 2341 } 2342 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2343 sk_txeof(sc_if1); 2344 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2345 SK_TXBMU_CLR_IRQ_EOF); 2346 } 2347 2348 /* Then MAC interrupts. */ 2349 if (sc_if0 && (status & SK_ISR_MAC1) && 2350 (ifp0->if_flags & IFF_RUNNING)) { 2351 if (sc->sk_type == SK_GENESIS) 2352 sk_intr_xmac(sc_if0); 2353 else 2354 sk_intr_yukon(sc_if0); 2355 } 2356 2357 if (sc_if1 && (status & SK_ISR_MAC2) && 2358 (ifp1->if_flags & IFF_RUNNING)) { 2359 if (sc->sk_type == SK_GENESIS) 2360 sk_intr_xmac(sc_if1); 2361 else 2362 sk_intr_yukon(sc_if1); 2363 2364 } 2365 2366 if (status & SK_ISR_EXTERNAL_REG) { 2367 if (sc_if0 != NULL && 2368 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2369 sk_intr_bcom(sc_if0); 2370 2371 if (sc_if1 != NULL && 2372 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2373 sk_intr_bcom(sc_if1); 2374 } 2375 } 2376 2377 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2378 2379 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2380 sk_start(ifp0); 2381 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2382 sk_start(ifp1); 2383 2384 #if NRND > 0 2385 if (RND_ENABLED(&sc->rnd_source)) 2386 rnd_add_uint32(&sc->rnd_source, status); 2387 #endif 2388 2389 if (sc->sk_int_mod_pending) 2390 sk_update_int_mod(sc); 2391 2392 return claimed; 2393 } 2394 2395 void 2396 sk_init_xmac(struct sk_if_softc *sc_if) 2397 { 2398 struct sk_softc *sc = sc_if->sk_softc; 2399 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2400 static const struct sk_bcom_hack bhack[] = { 2401 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2402 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2403 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2404 { 0, 0 } }; 2405 2406 DPRINTFN(1, ("sk_init_xmac\n")); 2407 2408 /* Unreset the XMAC. */ 2409 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2410 DELAY(1000); 2411 2412 /* Reset the XMAC's internal state. */ 2413 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2414 2415 /* Save the XMAC II revision */ 2416 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2417 2418 /* 2419 * Perform additional initialization for external PHYs, 2420 * namely for the 1000baseTX cards that use the XMAC's 2421 * GMII mode. 2422 */ 2423 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2424 int i = 0; 2425 u_int32_t val; 2426 2427 /* Take PHY out of reset. */ 2428 val = sk_win_read_4(sc, SK_GPIO); 2429 if (sc_if->sk_port == SK_PORT_A) 2430 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2431 else 2432 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2433 sk_win_write_4(sc, SK_GPIO, val); 2434 2435 /* Enable GMII mode on the XMAC. */ 2436 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2437 2438 sk_xmac_miibus_writereg((struct device *)sc_if, 2439 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2440 DELAY(10000); 2441 sk_xmac_miibus_writereg((struct device *)sc_if, 2442 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2443 2444 /* 2445 * Early versions of the BCM5400 apparently have 2446 * a bug that requires them to have their reserved 2447 * registers initialized to some magic values. I don't 2448 * know what the numbers do, I'm just the messenger. 2449 */ 2450 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2451 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2452 while (bhack[i].reg) { 2453 sk_xmac_miibus_writereg((struct device *)sc_if, 2454 SK_PHYADDR_BCOM, bhack[i].reg, 2455 bhack[i].val); 2456 i++; 2457 } 2458 } 2459 } 2460 2461 /* Set station address */ 2462 SK_XM_WRITE_2(sc_if, XM_PAR0, 2463 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2464 SK_XM_WRITE_2(sc_if, XM_PAR1, 2465 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2466 SK_XM_WRITE_2(sc_if, XM_PAR2, 2467 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2468 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2469 2470 if (ifp->if_flags & IFF_PROMISC) 2471 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2472 else 2473 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2474 2475 if (ifp->if_flags & IFF_BROADCAST) 2476 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2477 else 2478 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2479 2480 /* We don't need the FCS appended to the packet. */ 2481 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2482 2483 /* We want short frames padded to 60 bytes. */ 2484 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2485 2486 /* 2487 * Enable the reception of all error frames. This is is 2488 * a necessary evil due to the design of the XMAC. The 2489 * XMAC's receive FIFO is only 8K in size, however jumbo 2490 * frames can be up to 9000 bytes in length. When bad 2491 * frame filtering is enabled, the XMAC's RX FIFO operates 2492 * in 'store and forward' mode. For this to work, the 2493 * entire frame has to fit into the FIFO, but that means 2494 * that jumbo frames larger than 8192 bytes will be 2495 * truncated. Disabling all bad frame filtering causes 2496 * the RX FIFO to operate in streaming mode, in which 2497 * case the XMAC will start transfering frames out of the 2498 * RX FIFO as soon as the FIFO threshold is reached. 2499 */ 2500 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2501 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2502 XM_MODE_RX_INRANGELEN); 2503 2504 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2505 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2506 else 2507 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2508 2509 /* 2510 * Bump up the transmit threshold. This helps hold off transmit 2511 * underruns when we're blasting traffic from both ports at once. 2512 */ 2513 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2514 2515 /* Set multicast filter */ 2516 sk_setmulti(sc_if); 2517 2518 /* Clear and enable interrupts */ 2519 SK_XM_READ_2(sc_if, XM_ISR); 2520 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2521 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2522 else 2523 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2524 2525 /* Configure MAC arbiter */ 2526 switch (sc_if->sk_xmac_rev) { 2527 case XM_XMAC_REV_B2: 2528 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2529 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2530 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2531 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2532 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2533 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2534 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2535 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2536 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2537 break; 2538 case XM_XMAC_REV_C1: 2539 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2540 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2541 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2542 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2543 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2544 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2545 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2546 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2547 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2548 break; 2549 default: 2550 break; 2551 } 2552 sk_win_write_2(sc, SK_MACARB_CTL, 2553 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2554 2555 sc_if->sk_link = 1; 2556 } 2557 2558 void sk_init_yukon(struct sk_if_softc *sc_if) 2559 { 2560 u_int32_t /*mac, */phy; 2561 u_int16_t reg; 2562 struct sk_softc *sc; 2563 int i; 2564 2565 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2566 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2567 2568 sc = sc_if->sk_softc; 2569 if (sc->sk_type == SK_YUKON_LITE && 2570 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2571 /* Take PHY out of reset. */ 2572 sk_win_write_4(sc, SK_GPIO, 2573 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2574 } 2575 2576 2577 /* GMAC and GPHY Reset */ 2578 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2579 2580 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2581 2582 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2583 DELAY(1000); 2584 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2585 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2586 DELAY(1000); 2587 2588 2589 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2590 2591 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2592 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2593 2594 switch (sc_if->sk_softc->sk_pmd) { 2595 case IFM_1000_SX: 2596 case IFM_1000_LX: 2597 phy |= SK_GPHY_FIBER; 2598 break; 2599 2600 case IFM_1000_CX: 2601 case IFM_1000_T: 2602 phy |= SK_GPHY_COPPER; 2603 break; 2604 } 2605 2606 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2607 2608 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2609 DELAY(1000); 2610 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2611 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2612 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2613 2614 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2615 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2616 2617 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2618 2619 /* unused read of the interrupt source register */ 2620 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2621 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2622 2623 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2624 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2625 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2626 2627 /* MIB Counter Clear Mode set */ 2628 reg |= YU_PAR_MIB_CLR; 2629 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2630 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2631 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2632 2633 /* MIB Counter Clear Mode clear */ 2634 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2635 reg &= ~YU_PAR_MIB_CLR; 2636 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2637 2638 /* receive control reg */ 2639 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2640 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2641 YU_RCR_CRCR); 2642 2643 /* transmit parameter register */ 2644 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2645 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2646 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2647 2648 /* serial mode register */ 2649 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2650 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2651 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2652 YU_SMR_IPG_DATA(0x1e)); 2653 2654 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2655 /* Setup Yukon's address */ 2656 for (i = 0; i < 3; i++) { 2657 /* Write Source Address 1 (unicast filter) */ 2658 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2659 sc_if->sk_enaddr[i * 2] | 2660 sc_if->sk_enaddr[i * 2 + 1] << 8); 2661 } 2662 2663 for (i = 0; i < 3; i++) { 2664 reg = sk_win_read_2(sc_if->sk_softc, 2665 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2666 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2667 } 2668 2669 /* Set multicast filter */ 2670 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2671 sk_setmulti(sc_if); 2672 2673 /* enable interrupt mask for counter overflows */ 2674 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2675 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2676 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2677 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2678 2679 /* Configure RX MAC FIFO */ 2680 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2681 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2682 2683 /* Configure TX MAC FIFO */ 2684 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2685 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2686 2687 DPRINTFN(6, ("sk_init_yukon: end\n")); 2688 } 2689 2690 /* 2691 * Note that to properly initialize any part of the GEnesis chip, 2692 * you first have to take it out of reset mode. 2693 */ 2694 int 2695 sk_init(struct ifnet *ifp) 2696 { 2697 struct sk_if_softc *sc_if = ifp->if_softc; 2698 struct sk_softc *sc = sc_if->sk_softc; 2699 struct mii_data *mii = &sc_if->sk_mii; 2700 int s; 2701 u_int32_t imr, imtimer_ticks; 2702 2703 DPRINTFN(1, ("sk_init\n")); 2704 2705 s = splnet(); 2706 2707 if (ifp->if_flags & IFF_RUNNING) { 2708 splx(s); 2709 return 0; 2710 } 2711 2712 /* Cancel pending I/O and free all RX/TX buffers. */ 2713 sk_stop(ifp,0); 2714 2715 if (sc->sk_type == SK_GENESIS) { 2716 /* Configure LINK_SYNC LED */ 2717 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2718 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2719 SK_LINKLED_LINKSYNC_ON); 2720 2721 /* Configure RX LED */ 2722 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2723 SK_RXLEDCTL_COUNTER_START); 2724 2725 /* Configure TX LED */ 2726 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2727 SK_TXLEDCTL_COUNTER_START); 2728 } 2729 2730 /* Configure I2C registers */ 2731 2732 /* Configure XMAC(s) */ 2733 switch (sc->sk_type) { 2734 case SK_GENESIS: 2735 sk_init_xmac(sc_if); 2736 break; 2737 case SK_YUKON: 2738 case SK_YUKON_LITE: 2739 case SK_YUKON_LP: 2740 sk_init_yukon(sc_if); 2741 break; 2742 } 2743 mii_mediachg(mii); 2744 2745 if (sc->sk_type == SK_GENESIS) { 2746 /* Configure MAC FIFOs */ 2747 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2748 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2749 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2750 2751 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2752 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2753 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2754 } 2755 2756 /* Configure transmit arbiter(s) */ 2757 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2758 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2759 2760 /* Configure RAMbuffers */ 2761 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2762 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2763 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2764 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2765 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2766 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2767 2768 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2769 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2770 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2771 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2772 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2773 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2774 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2775 2776 /* Configure BMUs */ 2777 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2778 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2779 SK_RX_RING_ADDR(sc_if, 0)); 2780 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2781 2782 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2783 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2784 SK_TX_RING_ADDR(sc_if, 0)); 2785 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2786 2787 /* Init descriptors */ 2788 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2789 aprint_error("%s: initialization failed: no " 2790 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2791 sk_stop(ifp,0); 2792 splx(s); 2793 return ENOBUFS; 2794 } 2795 2796 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2797 aprint_error("%s: initialization failed: no " 2798 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2799 sk_stop(ifp,0); 2800 splx(s); 2801 return ENOBUFS; 2802 } 2803 2804 /* Set interrupt moderation if changed via sysctl. */ 2805 switch (sc->sk_type) { 2806 case SK_GENESIS: 2807 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2808 break; 2809 case SK_YUKON_EC: 2810 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2811 break; 2812 default: 2813 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2814 } 2815 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2816 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2817 sk_win_write_4(sc, SK_IMTIMERINIT, 2818 SK_IM_USECS(sc->sk_int_mod)); 2819 aprint_verbose("%s: interrupt moderation is %d us\n", 2820 sc->sk_dev.dv_xname, sc->sk_int_mod); 2821 } 2822 2823 /* Configure interrupt handling */ 2824 CSR_READ_4(sc, SK_ISSR); 2825 if (sc_if->sk_port == SK_PORT_A) 2826 sc->sk_intrmask |= SK_INTRS1; 2827 else 2828 sc->sk_intrmask |= SK_INTRS2; 2829 2830 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2831 2832 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2833 2834 /* Start BMUs. */ 2835 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2836 2837 if (sc->sk_type == SK_GENESIS) { 2838 /* Enable XMACs TX and RX state machines */ 2839 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2840 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2841 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2842 } 2843 2844 if (SK_YUKON_FAMILY(sc->sk_type)) { 2845 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2846 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2847 #if 0 2848 /* XXX disable 100Mbps and full duplex mode? */ 2849 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2850 #endif 2851 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2852 } 2853 2854 2855 ifp->if_flags |= IFF_RUNNING; 2856 ifp->if_flags &= ~IFF_OACTIVE; 2857 2858 splx(s); 2859 return 0; 2860 } 2861 2862 void 2863 sk_stop(struct ifnet *ifp, int disable) 2864 { 2865 struct sk_if_softc *sc_if = ifp->if_softc; 2866 struct sk_softc *sc = sc_if->sk_softc; 2867 int i; 2868 2869 DPRINTFN(1, ("sk_stop\n")); 2870 2871 callout_stop(&sc_if->sk_tick_ch); 2872 2873 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2874 u_int32_t val; 2875 2876 /* Put PHY back into reset. */ 2877 val = sk_win_read_4(sc, SK_GPIO); 2878 if (sc_if->sk_port == SK_PORT_A) { 2879 val |= SK_GPIO_DIR0; 2880 val &= ~SK_GPIO_DAT0; 2881 } else { 2882 val |= SK_GPIO_DIR2; 2883 val &= ~SK_GPIO_DAT2; 2884 } 2885 sk_win_write_4(sc, SK_GPIO, val); 2886 } 2887 2888 /* Turn off various components of this interface. */ 2889 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2890 switch (sc->sk_type) { 2891 case SK_GENESIS: 2892 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2893 SK_TXMACCTL_XMAC_RESET); 2894 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2895 break; 2896 case SK_YUKON: 2897 case SK_YUKON_LITE: 2898 case SK_YUKON_LP: 2899 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2900 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2901 break; 2902 } 2903 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2904 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2905 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2906 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2907 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2908 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2909 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2910 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2911 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2912 2913 /* Disable interrupts */ 2914 if (sc_if->sk_port == SK_PORT_A) 2915 sc->sk_intrmask &= ~SK_INTRS1; 2916 else 2917 sc->sk_intrmask &= ~SK_INTRS2; 2918 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2919 2920 SK_XM_READ_2(sc_if, XM_ISR); 2921 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2922 2923 /* Free RX and TX mbufs still in the queues. */ 2924 for (i = 0; i < SK_RX_RING_CNT; i++) { 2925 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2926 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2927 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2928 } 2929 } 2930 2931 for (i = 0; i < SK_TX_RING_CNT; i++) { 2932 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2933 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2934 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2935 } 2936 } 2937 2938 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2939 } 2940 2941 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2942 2943 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2944 2945 #ifdef SK_DEBUG 2946 void 2947 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2948 { 2949 #define DESC_PRINT(X) \ 2950 if (X) \ 2951 printf("txdesc[%d]." #X "=%#x\n", \ 2952 idx, X); 2953 2954 DESC_PRINT(le32toh(desc->sk_ctl)); 2955 DESC_PRINT(le32toh(desc->sk_next)); 2956 DESC_PRINT(le32toh(desc->sk_data_lo)); 2957 DESC_PRINT(le32toh(desc->sk_data_hi)); 2958 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2959 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2960 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2961 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2962 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2963 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2964 #undef PRINT 2965 } 2966 2967 void 2968 sk_dump_bytes(const char *data, int len) 2969 { 2970 int c, i, j; 2971 2972 for (i = 0; i < len; i += 16) { 2973 printf("%08x ", i); 2974 c = len - i; 2975 if (c > 16) c = 16; 2976 2977 for (j = 0; j < c; j++) { 2978 printf("%02x ", data[i + j] & 0xff); 2979 if ((j & 0xf) == 7 && j > 0) 2980 printf(" "); 2981 } 2982 2983 for (; j < 16; j++) 2984 printf(" "); 2985 printf(" "); 2986 2987 for (j = 0; j < c; j++) { 2988 int ch = data[i + j] & 0xff; 2989 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2990 } 2991 2992 printf("\n"); 2993 2994 if (c < 16) 2995 break; 2996 } 2997 } 2998 2999 void 3000 sk_dump_mbuf(struct mbuf *m) 3001 { 3002 int count = m->m_pkthdr.len; 3003 3004 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3005 3006 while (count > 0 && m) { 3007 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3008 m, m->m_data, m->m_len); 3009 sk_dump_bytes(mtod(m, char *), m->m_len); 3010 3011 count -= m->m_len; 3012 m = m->m_next; 3013 } 3014 } 3015 #endif 3016 3017 static int 3018 sk_sysctl_handler(SYSCTLFN_ARGS) 3019 { 3020 int error, t; 3021 struct sysctlnode node; 3022 struct sk_softc *sc; 3023 3024 node = *rnode; 3025 sc = node.sysctl_data; 3026 t = sc->sk_int_mod; 3027 node.sysctl_data = &t; 3028 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3029 if (error || newp == NULL) 3030 return error; 3031 3032 if (t < SK_IM_MIN || t > SK_IM_MAX) 3033 return EINVAL; 3034 3035 /* update the softc with sysctl-changed value, and mark 3036 for hardware update */ 3037 sc->sk_int_mod = t; 3038 sc->sk_int_mod_pending = 1; 3039 return 0; 3040 } 3041 3042 /* 3043 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3044 * set up in skc_attach() 3045 */ 3046 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3047 { 3048 int rc; 3049 const struct sysctlnode *node; 3050 3051 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3052 0, CTLTYPE_NODE, "hw", NULL, 3053 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3054 goto err; 3055 } 3056 3057 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3058 0, CTLTYPE_NODE, "sk", 3059 SYSCTL_DESCR("sk interface controls"), 3060 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3061 goto err; 3062 } 3063 3064 sk_root_num = node->sysctl_num; 3065 return; 3066 3067 err: 3068 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3069 } 3070
Indexes created Tue Sep 23 14:10:03 GMT 2025