if_sk.c revision 1.37
1 /* $NetBSD: if_sk.c,v 1.37 2007/03/04 06:02:22 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 #include "rnd.h" 126 127 #include <sys/param.h> 128 #include <sys/systm.h> 129 #include <sys/sockio.h> 130 #include <sys/mbuf.h> 131 #include <sys/malloc.h> 132 #include <sys/kernel.h> 133 #include <sys/socket.h> 134 #include <sys/device.h> 135 #include <sys/queue.h> 136 #include <sys/callout.h> 137 #include <sys/sysctl.h> 138 #include <sys/endian.h> 139 140 #include <net/if.h> 141 #include <net/if_dl.h> 142 #include <net/if_types.h> 143 144 #include <net/if_media.h> 145 146 #if NBPFILTER > 0 147 #include <net/bpf.h> 148 #endif 149 #if NRND > 0 150 #include <sys/rnd.h> 151 #endif 152 153 #include <dev/mii/mii.h> 154 #include <dev/mii/miivar.h> 155 #include <dev/mii/brgphyreg.h> 156 157 #include <dev/pci/pcireg.h> 158 #include <dev/pci/pcivar.h> 159 #include <dev/pci/pcidevs.h> 160 161 /* #define SK_USEIOSPACE */ 162 163 #include <dev/pci/if_skreg.h> 164 #include <dev/pci/if_skvar.h> 165 166 int skc_probe(struct device *, struct cfdata *, void *); 167 void skc_attach(struct device *, struct device *self, void *aux); 168 int sk_probe(struct device *, struct cfdata *, void *); 169 void sk_attach(struct device *, struct device *self, void *aux); 170 int skcprint(void *, const char *); 171 int sk_intr(void *); 172 void sk_intr_bcom(struct sk_if_softc *); 173 void sk_intr_xmac(struct sk_if_softc *); 174 void sk_intr_yukon(struct sk_if_softc *); 175 void sk_rxeof(struct sk_if_softc *); 176 void sk_txeof(struct sk_if_softc *); 177 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 178 void sk_start(struct ifnet *); 179 int sk_ioctl(struct ifnet *, u_long, void *); 180 int sk_init(struct ifnet *); 181 void sk_init_xmac(struct sk_if_softc *); 182 void sk_init_yukon(struct sk_if_softc *); 183 void sk_stop(struct ifnet *, int); 184 void sk_watchdog(struct ifnet *); 185 void sk_shutdown(void *); 186 int sk_ifmedia_upd(struct ifnet *); 187 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 188 void sk_reset(struct sk_softc *); 189 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 190 int sk_alloc_jumbo_mem(struct sk_if_softc *); 191 void sk_free_jumbo_mem(struct sk_if_softc *); 192 void *sk_jalloc(struct sk_if_softc *); 193 void sk_jfree(struct mbuf *, void *, size_t, void *); 194 int sk_init_rx_ring(struct sk_if_softc *); 195 int sk_init_tx_ring(struct sk_if_softc *); 196 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 197 void sk_vpd_read_res(struct sk_softc *, 198 struct vpd_res *, int); 199 void sk_vpd_read(struct sk_softc *); 200 201 void sk_update_int_mod(struct sk_softc *); 202 203 int sk_xmac_miibus_readreg(struct device *, int, int); 204 void sk_xmac_miibus_writereg(struct device *, int, int, int); 205 void sk_xmac_miibus_statchg(struct device *); 206 207 int sk_marv_miibus_readreg(struct device *, int, int); 208 void sk_marv_miibus_writereg(struct device *, int, int, int); 209 void sk_marv_miibus_statchg(struct device *); 210 211 u_int32_t sk_xmac_hash(void *); 212 u_int32_t sk_yukon_hash(void *); 213 void sk_setfilt(struct sk_if_softc *, void *, int); 214 void sk_setmulti(struct sk_if_softc *); 215 void sk_tick(void *); 216 217 /* #define SK_DEBUG 2 */ 218 #ifdef SK_DEBUG 219 #define DPRINTF(x) if (skdebug) printf x 220 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 221 int skdebug = SK_DEBUG; 222 223 void sk_dump_txdesc(struct sk_tx_desc *, int); 224 void sk_dump_mbuf(struct mbuf *); 225 void sk_dump_bytes(const char *, int); 226 #else 227 #define DPRINTF(x) 228 #define DPRINTFN(n,x) 229 #endif 230 231 static int sk_sysctl_handler(SYSCTLFN_PROTO); 232 static int sk_root_num; 233 234 /* supported device vendors */ 235 static const struct sk_product { 236 pci_vendor_id_t sk_vendor; 237 pci_product_id_t sk_product; 238 } sk_products[] = { 239 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 240 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 241 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T, }, 242 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 243 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 244 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 245 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 246 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 247 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 248 { 0, 0, } 249 }; 250 251 #define SK_LINKSYS_EG1032_SUBID 0x00151737 252 253 static inline u_int32_t 254 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 255 { 256 #ifdef SK_USEIOSPACE 257 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 258 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 259 #else 260 return CSR_READ_4(sc, reg); 261 #endif 262 } 263 264 static inline u_int16_t 265 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 266 { 267 #ifdef SK_USEIOSPACE 268 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 269 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 270 #else 271 return CSR_READ_2(sc, reg); 272 #endif 273 } 274 275 static inline u_int8_t 276 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 277 { 278 #ifdef SK_USEIOSPACE 279 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 280 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 281 #else 282 return CSR_READ_1(sc, reg); 283 #endif 284 } 285 286 static inline void 287 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 288 { 289 #ifdef SK_USEIOSPACE 290 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 291 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 292 #else 293 CSR_WRITE_4(sc, reg, x); 294 #endif 295 } 296 297 static inline void 298 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 299 { 300 #ifdef SK_USEIOSPACE 301 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 302 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 303 #else 304 CSR_WRITE_2(sc, reg, x); 305 #endif 306 } 307 308 static inline void 309 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 310 { 311 #ifdef SK_USEIOSPACE 312 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 313 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 314 #else 315 CSR_WRITE_1(sc, reg, x); 316 #endif 317 } 318 319 /* 320 * The VPD EEPROM contains Vital Product Data, as suggested in 321 * the PCI 2.1 specification. The VPD data is separared into areas 322 * denoted by resource IDs. The SysKonnect VPD contains an ID string 323 * resource (the name of the adapter), a read-only area resource 324 * containing various key/data fields and a read/write area which 325 * can be used to store asset management information or log messages. 326 * We read the ID string and read-only into buffers attached to 327 * the controller softc structure for later use. At the moment, 328 * we only use the ID string during sk_attach(). 329 */ 330 u_int8_t 331 sk_vpd_readbyte(struct sk_softc *sc, int addr) 332 { 333 int i; 334 335 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 336 for (i = 0; i < SK_TIMEOUT; i++) { 337 DELAY(1); 338 if (sk_win_read_2(sc, 339 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 340 break; 341 } 342 343 if (i == SK_TIMEOUT) 344 return 0; 345 346 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 347 } 348 349 void 350 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 351 { 352 int i; 353 u_int8_t *ptr; 354 355 ptr = (u_int8_t *)res; 356 for (i = 0; i < sizeof(struct vpd_res); i++) 357 ptr[i] = sk_vpd_readbyte(sc, i + addr); 358 } 359 360 void 361 sk_vpd_read(struct sk_softc *sc) 362 { 363 int pos = 0, i; 364 struct vpd_res res; 365 366 if (sc->sk_vpd_prodname != NULL) 367 free(sc->sk_vpd_prodname, M_DEVBUF); 368 if (sc->sk_vpd_readonly != NULL) 369 free(sc->sk_vpd_readonly, M_DEVBUF); 370 sc->sk_vpd_prodname = NULL; 371 sc->sk_vpd_readonly = NULL; 372 373 sk_vpd_read_res(sc, &res, pos); 374 375 if (res.vr_id != VPD_RES_ID) { 376 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 377 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 378 return; 379 } 380 381 pos += sizeof(res); 382 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 383 if (sc->sk_vpd_prodname == NULL) 384 panic("sk_vpd_read"); 385 for (i = 0; i < res.vr_len; i++) 386 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 387 sc->sk_vpd_prodname[i] = '\0'; 388 pos += i; 389 390 sk_vpd_read_res(sc, &res, pos); 391 392 if (res.vr_id != VPD_RES_READ) { 393 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 394 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 395 return; 396 } 397 398 pos += sizeof(res); 399 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 400 if (sc->sk_vpd_readonly == NULL) 401 panic("sk_vpd_read"); 402 for (i = 0; i < res.vr_len ; i++) 403 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 404 } 405 406 int 407 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 408 { 409 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 410 int i; 411 412 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 413 414 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 415 return 0; 416 417 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 418 SK_XM_READ_2(sc_if, XM_PHY_DATA); 419 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 420 for (i = 0; i < SK_TIMEOUT; i++) { 421 DELAY(1); 422 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 423 XM_MMUCMD_PHYDATARDY) 424 break; 425 } 426 427 if (i == SK_TIMEOUT) { 428 aprint_error("%s: phy failed to come ready\n", 429 sc_if->sk_dev.dv_xname); 430 return 0; 431 } 432 } 433 DELAY(1); 434 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 435 } 436 437 void 438 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 439 { 440 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 441 int i; 442 443 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 444 445 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 446 for (i = 0; i < SK_TIMEOUT; i++) { 447 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 448 break; 449 } 450 451 if (i == SK_TIMEOUT) { 452 aprint_error("%s: phy failed to come ready\n", 453 sc_if->sk_dev.dv_xname); 454 return; 455 } 456 457 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 458 for (i = 0; i < SK_TIMEOUT; i++) { 459 DELAY(1); 460 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 461 break; 462 } 463 464 if (i == SK_TIMEOUT) 465 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 466 } 467 468 void 469 sk_xmac_miibus_statchg(struct device *dev) 470 { 471 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 472 struct mii_data *mii = &sc_if->sk_mii; 473 474 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 475 476 /* 477 * If this is a GMII PHY, manually set the XMAC's 478 * duplex mode accordingly. 479 */ 480 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 481 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 482 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 483 else 484 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 485 } 486 } 487 488 int 489 sk_marv_miibus_readreg(struct device *dev, int phy, int reg) 490 { 491 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 492 u_int16_t val; 493 int i; 494 495 if (phy != 0 || 496 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 497 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 498 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 499 phy, reg)); 500 return 0; 501 } 502 503 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 504 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 505 506 for (i = 0; i < SK_TIMEOUT; i++) { 507 DELAY(1); 508 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 509 if (val & YU_SMICR_READ_VALID) 510 break; 511 } 512 513 if (i == SK_TIMEOUT) { 514 aprint_error("%s: phy failed to come ready\n", 515 sc_if->sk_dev.dv_xname); 516 return 0; 517 } 518 519 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 520 SK_TIMEOUT)); 521 522 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 523 524 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 525 phy, reg, val)); 526 527 return val; 528 } 529 530 void 531 sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 532 { 533 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 534 int i; 535 536 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 537 phy, reg, val)); 538 539 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 540 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 541 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 542 543 for (i = 0; i < SK_TIMEOUT; i++) { 544 DELAY(1); 545 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 546 break; 547 } 548 } 549 550 void 551 sk_marv_miibus_statchg(struct device *dev) 552 { 553 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 554 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 555 } 556 557 #define SK_HASH_BITS 6 558 559 u_int32_t 560 sk_xmac_hash(void *addr) 561 { 562 u_int32_t crc; 563 564 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 565 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 566 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 567 return crc; 568 } 569 570 u_int32_t 571 sk_yukon_hash(void *addr) 572 { 573 u_int32_t crc; 574 575 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 576 crc &= ((1 << SK_HASH_BITS) - 1); 577 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 578 return crc; 579 } 580 581 void 582 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 583 { 584 char *addr = addrv; 585 int base = XM_RXFILT_ENTRY(slot); 586 587 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 588 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 589 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 590 } 591 592 void 593 sk_setmulti(struct sk_if_softc *sc_if) 594 { 595 struct sk_softc *sc = sc_if->sk_softc; 596 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 597 u_int32_t hashes[2] = { 0, 0 }; 598 int h = 0, i; 599 struct ethercom *ec = &sc_if->sk_ethercom; 600 struct ether_multi *enm; 601 struct ether_multistep step; 602 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 603 604 /* First, zot all the existing filters. */ 605 switch (sc->sk_type) { 606 case SK_GENESIS: 607 for (i = 1; i < XM_RXFILT_MAX; i++) 608 sk_setfilt(sc_if, (void *)&dummy, i); 609 610 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 611 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 612 break; 613 case SK_YUKON: 614 case SK_YUKON_LITE: 615 case SK_YUKON_LP: 616 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 617 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 618 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 619 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 620 break; 621 } 622 623 /* Now program new ones. */ 624 allmulti: 625 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 626 hashes[0] = 0xFFFFFFFF; 627 hashes[1] = 0xFFFFFFFF; 628 } else { 629 i = 1; 630 /* First find the tail of the list. */ 631 ETHER_FIRST_MULTI(step, ec, enm); 632 while (enm != NULL) { 633 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 634 ETHER_ADDR_LEN)) { 635 ifp->if_flags |= IFF_ALLMULTI; 636 goto allmulti; 637 } 638 DPRINTFN(2,("multicast address %s\n", 639 ether_sprintf(enm->enm_addrlo))); 640 /* 641 * Program the first XM_RXFILT_MAX multicast groups 642 * into the perfect filter. For all others, 643 * use the hash table. 644 */ 645 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 646 sk_setfilt(sc_if, enm->enm_addrlo, i); 647 i++; 648 } 649 else { 650 switch (sc->sk_type) { 651 case SK_GENESIS: 652 h = sk_xmac_hash(enm->enm_addrlo); 653 break; 654 case SK_YUKON: 655 case SK_YUKON_LITE: 656 case SK_YUKON_LP: 657 h = sk_yukon_hash(enm->enm_addrlo); 658 break; 659 } 660 if (h < 32) 661 hashes[0] |= (1 << h); 662 else 663 hashes[1] |= (1 << (h - 32)); 664 } 665 666 ETHER_NEXT_MULTI(step, enm); 667 } 668 } 669 670 switch (sc->sk_type) { 671 case SK_GENESIS: 672 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 673 XM_MODE_RX_USE_PERFECT); 674 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 675 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 676 break; 677 case SK_YUKON: 678 case SK_YUKON_LITE: 679 case SK_YUKON_LP: 680 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 681 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 682 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 683 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 684 break; 685 } 686 } 687 688 int 689 sk_init_rx_ring(struct sk_if_softc *sc_if) 690 { 691 struct sk_chain_data *cd = &sc_if->sk_cdata; 692 struct sk_ring_data *rd = sc_if->sk_rdata; 693 int i; 694 695 bzero((char *)rd->sk_rx_ring, 696 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 697 698 for (i = 0; i < SK_RX_RING_CNT; i++) { 699 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 700 if (i == (SK_RX_RING_CNT - 1)) { 701 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 702 rd->sk_rx_ring[i].sk_next = 703 htole32(SK_RX_RING_ADDR(sc_if, 0)); 704 } else { 705 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 706 rd->sk_rx_ring[i].sk_next = 707 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 708 } 709 } 710 711 for (i = 0; i < SK_RX_RING_CNT; i++) { 712 if (sk_newbuf(sc_if, i, NULL, 713 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 714 aprint_error("%s: failed alloc of %dth mbuf\n", 715 sc_if->sk_dev.dv_xname, i); 716 return ENOBUFS; 717 } 718 } 719 sc_if->sk_cdata.sk_rx_prod = 0; 720 sc_if->sk_cdata.sk_rx_cons = 0; 721 722 return 0; 723 } 724 725 int 726 sk_init_tx_ring(struct sk_if_softc *sc_if) 727 { 728 struct sk_chain_data *cd = &sc_if->sk_cdata; 729 struct sk_ring_data *rd = sc_if->sk_rdata; 730 int i; 731 732 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 733 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 734 735 for (i = 0; i < SK_TX_RING_CNT; i++) { 736 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 737 if (i == (SK_TX_RING_CNT - 1)) { 738 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 739 rd->sk_tx_ring[i].sk_next = 740 htole32(SK_TX_RING_ADDR(sc_if, 0)); 741 } else { 742 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 743 rd->sk_tx_ring[i].sk_next = 744 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 745 } 746 } 747 748 sc_if->sk_cdata.sk_tx_prod = 0; 749 sc_if->sk_cdata.sk_tx_cons = 0; 750 sc_if->sk_cdata.sk_tx_cnt = 0; 751 752 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 753 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 754 755 return 0; 756 } 757 758 int 759 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 760 bus_dmamap_t dmamap) 761 { 762 struct mbuf *m_new = NULL; 763 struct sk_chain *c; 764 struct sk_rx_desc *r; 765 766 if (m == NULL) { 767 void *buf = NULL; 768 769 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 770 if (m_new == NULL) { 771 aprint_error("%s: no memory for rx list -- " 772 "packet dropped!\n", sc_if->sk_dev.dv_xname); 773 return ENOBUFS; 774 } 775 776 /* Allocate the jumbo buffer */ 777 buf = sk_jalloc(sc_if); 778 if (buf == NULL) { 779 m_freem(m_new); 780 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 781 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 782 return ENOBUFS; 783 } 784 785 /* Attach the buffer to the mbuf */ 786 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 787 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 788 789 } else { 790 /* 791 * We're re-using a previously allocated mbuf; 792 * be sure to re-init pointers and lengths to 793 * default values. 794 */ 795 m_new = m; 796 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 797 m_new->m_data = m_new->m_ext.ext_buf; 798 } 799 m_adj(m_new, ETHER_ALIGN); 800 801 c = &sc_if->sk_cdata.sk_rx_chain[i]; 802 r = c->sk_desc; 803 c->sk_mbuf = m_new; 804 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 805 (((vaddr_t)m_new->m_data 806 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 807 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 808 809 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 810 811 return 0; 812 } 813 814 /* 815 * Memory management for jumbo frames. 816 */ 817 818 int 819 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 820 { 821 struct sk_softc *sc = sc_if->sk_softc; 822 char *ptr, *kva; 823 bus_dma_segment_t seg; 824 int i, rseg, state, error; 825 struct sk_jpool_entry *entry; 826 827 state = error = 0; 828 829 /* Grab a big chunk o' storage. */ 830 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 831 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 832 aprint_error("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 833 return ENOBUFS; 834 } 835 836 state = 1; 837 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 838 BUS_DMA_NOWAIT)) { 839 aprint_error("%s: can't map dma buffers (%d bytes)\n", 840 sc->sk_dev.dv_xname, SK_JMEM); 841 error = ENOBUFS; 842 goto out; 843 } 844 845 state = 2; 846 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 847 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 848 aprint_error("%s: can't create dma map\n", sc->sk_dev.dv_xname); 849 error = ENOBUFS; 850 goto out; 851 } 852 853 state = 3; 854 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 855 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 856 aprint_error("%s: can't load dma map\n", sc->sk_dev.dv_xname); 857 error = ENOBUFS; 858 goto out; 859 } 860 861 state = 4; 862 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 863 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 864 865 LIST_INIT(&sc_if->sk_jfree_listhead); 866 LIST_INIT(&sc_if->sk_jinuse_listhead); 867 868 /* 869 * Now divide it up into 9K pieces and save the addresses 870 * in an array. 871 */ 872 ptr = sc_if->sk_cdata.sk_jumbo_buf; 873 for (i = 0; i < SK_JSLOTS; i++) { 874 sc_if->sk_cdata.sk_jslots[i] = ptr; 875 ptr += SK_JLEN; 876 entry = malloc(sizeof(struct sk_jpool_entry), 877 M_DEVBUF, M_NOWAIT); 878 if (entry == NULL) { 879 aprint_error("%s: no memory for jumbo buffer queue!\n", 880 sc->sk_dev.dv_xname); 881 error = ENOBUFS; 882 goto out; 883 } 884 entry->slot = i; 885 if (i) 886 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 887 entry, jpool_entries); 888 else 889 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 890 entry, jpool_entries); 891 } 892 out: 893 if (error != 0) { 894 switch (state) { 895 case 4: 896 bus_dmamap_unload(sc->sc_dmatag, 897 sc_if->sk_cdata.sk_rx_jumbo_map); 898 case 3: 899 bus_dmamap_destroy(sc->sc_dmatag, 900 sc_if->sk_cdata.sk_rx_jumbo_map); 901 case 2: 902 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 903 case 1: 904 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 905 break; 906 default: 907 break; 908 } 909 } 910 911 return error; 912 } 913 914 /* 915 * Allocate a jumbo buffer. 916 */ 917 void * 918 sk_jalloc(struct sk_if_softc *sc_if) 919 { 920 struct sk_jpool_entry *entry; 921 922 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 923 924 if (entry == NULL) 925 return NULL; 926 927 LIST_REMOVE(entry, jpool_entries); 928 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 929 return sc_if->sk_cdata.sk_jslots[entry->slot]; 930 } 931 932 /* 933 * Release a jumbo buffer. 934 */ 935 void 936 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 937 { 938 struct sk_jpool_entry *entry; 939 struct sk_if_softc *sc; 940 int i, s; 941 942 /* Extract the softc struct pointer. */ 943 sc = (struct sk_if_softc *)arg; 944 945 if (sc == NULL) 946 panic("sk_jfree: can't find softc pointer!"); 947 948 /* calculate the slot this buffer belongs to */ 949 950 i = ((vaddr_t)buf 951 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 952 953 if ((i < 0) || (i >= SK_JSLOTS)) 954 panic("sk_jfree: asked to free buffer that we don't manage!"); 955 956 s = splvm(); 957 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 958 if (entry == NULL) 959 panic("sk_jfree: buffer not in use!"); 960 entry->slot = i; 961 LIST_REMOVE(entry, jpool_entries); 962 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 963 964 if (__predict_true(m != NULL)) 965 pool_cache_put(&mbpool_cache, m); 966 splx(s); 967 } 968 969 /* 970 * Set media options. 971 */ 972 int 973 sk_ifmedia_upd(struct ifnet *ifp) 974 { 975 struct sk_if_softc *sc_if = ifp->if_softc; 976 977 (void) sk_init(ifp); 978 mii_mediachg(&sc_if->sk_mii); 979 return 0; 980 } 981 982 /* 983 * Report current media status. 984 */ 985 void 986 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 987 { 988 struct sk_if_softc *sc_if = ifp->if_softc; 989 990 mii_pollstat(&sc_if->sk_mii); 991 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 992 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 993 } 994 995 int 996 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 997 { 998 struct sk_if_softc *sc_if = ifp->if_softc; 999 struct sk_softc *sc = sc_if->sk_softc; 1000 struct ifreq *ifr = (struct ifreq *) data; 1001 struct mii_data *mii; 1002 int s, error = 0; 1003 1004 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1005 1006 s = splnet(); 1007 1008 switch (command) { 1009 1010 case SIOCSIFFLAGS: 1011 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1012 if (ifp->if_flags & IFF_UP) { 1013 if (ifp->if_flags & IFF_RUNNING && 1014 ifp->if_flags & IFF_PROMISC && 1015 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1016 switch (sc->sk_type) { 1017 case SK_GENESIS: 1018 SK_XM_SETBIT_4(sc_if, XM_MODE, 1019 XM_MODE_RX_PROMISC); 1020 break; 1021 case SK_YUKON: 1022 case SK_YUKON_LITE: 1023 case SK_YUKON_LP: 1024 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1025 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1026 break; 1027 } 1028 sk_setmulti(sc_if); 1029 } else if (ifp->if_flags & IFF_RUNNING && 1030 !(ifp->if_flags & IFF_PROMISC) && 1031 sc_if->sk_if_flags & IFF_PROMISC) { 1032 switch (sc->sk_type) { 1033 case SK_GENESIS: 1034 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1035 XM_MODE_RX_PROMISC); 1036 break; 1037 case SK_YUKON: 1038 case SK_YUKON_LITE: 1039 case SK_YUKON_LP: 1040 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1041 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1042 break; 1043 } 1044 1045 sk_setmulti(sc_if); 1046 } else 1047 (void) sk_init(ifp); 1048 } else { 1049 if (ifp->if_flags & IFF_RUNNING) 1050 sk_stop(ifp,0); 1051 } 1052 sc_if->sk_if_flags = ifp->if_flags; 1053 error = 0; 1054 break; 1055 1056 case SIOCGIFMEDIA: 1057 case SIOCSIFMEDIA: 1058 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 1059 mii = &sc_if->sk_mii; 1060 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1061 break; 1062 default: 1063 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1064 error = ether_ioctl(ifp, command, data); 1065 1066 if ( error == ENETRESET) { 1067 if (ifp->if_flags & IFF_RUNNING) { 1068 sk_setmulti(sc_if); 1069 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1070 } 1071 error = 0; 1072 } else if ( error ) { 1073 splx(s); 1074 return error; 1075 } 1076 break; 1077 } 1078 1079 splx(s); 1080 return error; 1081 } 1082 1083 void 1084 sk_update_int_mod(struct sk_softc *sc) 1085 { 1086 u_int32_t imtimer_ticks; 1087 1088 /* 1089 * Configure interrupt moderation. The moderation timer 1090 * defers interrupts specified in the interrupt moderation 1091 * timer mask based on the timeout specified in the interrupt 1092 * moderation timer init register. Each bit in the timer 1093 * register represents one tick, so to specify a timeout in 1094 * microseconds, we have to multiply by the correct number of 1095 * ticks-per-microsecond. 1096 */ 1097 switch (sc->sk_type) { 1098 case SK_GENESIS: 1099 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1100 break; 1101 case SK_YUKON_EC: 1102 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1103 break; 1104 default: 1105 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1106 } 1107 aprint_verbose("%s: interrupt moderation is %d us\n", 1108 sc->sk_dev.dv_xname, sc->sk_int_mod); 1109 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1110 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1111 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1112 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1113 sc->sk_int_mod_pending = 0; 1114 } 1115 1116 /* 1117 * Lookup: Check the PCI vendor and device, and return a pointer to 1118 * The structure if the IDs match against our list. 1119 */ 1120 1121 static const struct sk_product * 1122 sk_lookup(const struct pci_attach_args *pa) 1123 { 1124 const struct sk_product *psk; 1125 1126 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1127 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1128 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1129 return psk; 1130 } 1131 return NULL; 1132 } 1133 1134 /* 1135 * Probe for a SysKonnect GEnesis chip. 1136 */ 1137 1138 int 1139 skc_probe(struct device *parent, struct cfdata *match, 1140 void *aux) 1141 { 1142 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1143 const struct sk_product *psk; 1144 pcireg_t subid; 1145 1146 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1147 1148 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1149 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1150 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1151 subid == SK_LINKSYS_EG1032_SUBID) 1152 return 1; 1153 1154 if ((psk = sk_lookup(pa))) { 1155 return 1; 1156 } 1157 return 0; 1158 } 1159 1160 /* 1161 * Force the GEnesis into reset, then bring it out of reset. 1162 */ 1163 void sk_reset(struct sk_softc *sc) 1164 { 1165 DPRINTFN(2, ("sk_reset\n")); 1166 1167 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1168 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1169 if (SK_YUKON_FAMILY(sc->sk_type)) 1170 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1171 1172 DELAY(1000); 1173 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1174 DELAY(2); 1175 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1176 if (SK_YUKON_FAMILY(sc->sk_type)) 1177 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1178 1179 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1180 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1181 CSR_READ_2(sc, SK_LINK_CTRL))); 1182 1183 if (sc->sk_type == SK_GENESIS) { 1184 /* Configure packet arbiter */ 1185 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1186 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1187 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1188 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1189 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1190 } 1191 1192 /* Enable RAM interface */ 1193 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1194 1195 sk_update_int_mod(sc); 1196 } 1197 1198 int 1199 sk_probe(struct device *parent, struct cfdata *match, 1200 void *aux) 1201 { 1202 struct skc_attach_args *sa = aux; 1203 1204 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1205 return 0; 1206 1207 return 1; 1208 } 1209 1210 /* 1211 * Each XMAC chip is attached as a separate logical IP interface. 1212 * Single port cards will have only one logical interface of course. 1213 */ 1214 void 1215 sk_attach(struct device *parent, struct device *self, void *aux) 1216 { 1217 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1218 struct sk_softc *sc = (struct sk_softc *)parent; 1219 struct skc_attach_args *sa = aux; 1220 struct sk_txmap_entry *entry; 1221 struct ifnet *ifp; 1222 bus_dma_segment_t seg; 1223 bus_dmamap_t dmamap; 1224 void *kva; 1225 int i, rseg; 1226 1227 sc_if->sk_port = sa->skc_port; 1228 sc_if->sk_softc = sc; 1229 sc->sk_if[sa->skc_port] = sc_if; 1230 1231 if (sa->skc_port == SK_PORT_A) 1232 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1233 if (sa->skc_port == SK_PORT_B) 1234 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1235 1236 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1237 1238 /* 1239 * Get station address for this interface. Note that 1240 * dual port cards actually come with three station 1241 * addresses: one for each port, plus an extra. The 1242 * extra one is used by the SysKonnect driver software 1243 * as a 'virtual' station address for when both ports 1244 * are operating in failover mode. Currently we don't 1245 * use this extra address. 1246 */ 1247 for (i = 0; i < ETHER_ADDR_LEN; i++) 1248 sc_if->sk_enaddr[i] = 1249 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1250 1251 1252 aprint_normal(": Ethernet address %s\n", 1253 ether_sprintf(sc_if->sk_enaddr)); 1254 1255 /* 1256 * Set up RAM buffer addresses. The NIC will have a certain 1257 * amount of SRAM on it, somewhere between 512K and 2MB. We 1258 * need to divide this up a) between the transmitter and 1259 * receiver and b) between the two XMACs, if this is a 1260 * dual port NIC. Our algorithm is to divide up the memory 1261 * evenly so that everyone gets a fair share. 1262 */ 1263 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1264 u_int32_t chunk, val; 1265 1266 chunk = sc->sk_ramsize / 2; 1267 val = sc->sk_rboff / sizeof(u_int64_t); 1268 sc_if->sk_rx_ramstart = val; 1269 val += (chunk / sizeof(u_int64_t)); 1270 sc_if->sk_rx_ramend = val - 1; 1271 sc_if->sk_tx_ramstart = val; 1272 val += (chunk / sizeof(u_int64_t)); 1273 sc_if->sk_tx_ramend = val - 1; 1274 } else { 1275 u_int32_t chunk, val; 1276 1277 chunk = sc->sk_ramsize / 4; 1278 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1279 sizeof(u_int64_t); 1280 sc_if->sk_rx_ramstart = val; 1281 val += (chunk / sizeof(u_int64_t)); 1282 sc_if->sk_rx_ramend = val - 1; 1283 sc_if->sk_tx_ramstart = val; 1284 val += (chunk / sizeof(u_int64_t)); 1285 sc_if->sk_tx_ramend = val - 1; 1286 } 1287 1288 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1289 " tx_ramstart=%#x tx_ramend=%#x\n", 1290 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1291 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1292 1293 /* Read and save PHY type and set PHY address */ 1294 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1295 switch (sc_if->sk_phytype) { 1296 case SK_PHYTYPE_XMAC: 1297 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1298 break; 1299 case SK_PHYTYPE_BCOM: 1300 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1301 break; 1302 case SK_PHYTYPE_MARV_COPPER: 1303 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1304 break; 1305 default: 1306 aprint_error("%s: unsupported PHY type: %d\n", 1307 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1308 return; 1309 } 1310 1311 /* Allocate the descriptor queues. */ 1312 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1313 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1314 aprint_error("%s: can't alloc rx buffers\n", 1315 sc->sk_dev.dv_xname); 1316 goto fail; 1317 } 1318 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1319 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1320 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1321 sc_if->sk_dev.dv_xname, 1322 (u_long) sizeof(struct sk_ring_data)); 1323 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1324 goto fail; 1325 } 1326 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1327 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1328 &sc_if->sk_ring_map)) { 1329 aprint_error("%s: can't create dma map\n", 1330 sc_if->sk_dev.dv_xname); 1331 bus_dmamem_unmap(sc->sc_dmatag, kva, 1332 sizeof(struct sk_ring_data)); 1333 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1334 goto fail; 1335 } 1336 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1337 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1338 aprint_error("%s: can't load dma map\n", 1339 sc_if->sk_dev.dv_xname); 1340 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1341 bus_dmamem_unmap(sc->sc_dmatag, kva, 1342 sizeof(struct sk_ring_data)); 1343 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1344 goto fail; 1345 } 1346 1347 for (i = 0; i < SK_RX_RING_CNT; i++) 1348 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1349 1350 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1351 for (i = 0; i < SK_TX_RING_CNT; i++) { 1352 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1353 1354 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1355 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1356 aprint_error("%s: Can't create TX dmamap\n", 1357 sc_if->sk_dev.dv_xname); 1358 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1359 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1360 bus_dmamem_unmap(sc->sc_dmatag, kva, 1361 sizeof(struct sk_ring_data)); 1362 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1363 goto fail; 1364 } 1365 1366 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1367 if (!entry) { 1368 aprint_error("%s: Can't alloc txmap entry\n", 1369 sc_if->sk_dev.dv_xname); 1370 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1371 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1372 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1373 bus_dmamem_unmap(sc->sc_dmatag, kva, 1374 sizeof(struct sk_ring_data)); 1375 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1376 goto fail; 1377 } 1378 entry->dmamap = dmamap; 1379 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1380 } 1381 1382 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1383 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1384 1385 ifp = &sc_if->sk_ethercom.ec_if; 1386 /* Try to allocate memory for jumbo buffers. */ 1387 if (sk_alloc_jumbo_mem(sc_if)) { 1388 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1389 goto fail; 1390 } 1391 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1392 | ETHERCAP_JUMBO_MTU; 1393 1394 ifp->if_softc = sc_if; 1395 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1396 ifp->if_ioctl = sk_ioctl; 1397 ifp->if_start = sk_start; 1398 ifp->if_stop = sk_stop; 1399 ifp->if_init = sk_init; 1400 ifp->if_watchdog = sk_watchdog; 1401 ifp->if_capabilities = 0; 1402 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1403 IFQ_SET_READY(&ifp->if_snd); 1404 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1405 1406 /* 1407 * Do miibus setup. 1408 */ 1409 switch (sc->sk_type) { 1410 case SK_GENESIS: 1411 sk_init_xmac(sc_if); 1412 break; 1413 case SK_YUKON: 1414 case SK_YUKON_LITE: 1415 case SK_YUKON_LP: 1416 sk_init_yukon(sc_if); 1417 break; 1418 default: 1419 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1420 sc->sk_type); 1421 } 1422 1423 DPRINTFN(2, ("sk_attach: 1\n")); 1424 1425 sc_if->sk_mii.mii_ifp = ifp; 1426 switch (sc->sk_type) { 1427 case SK_GENESIS: 1428 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1429 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1430 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1431 break; 1432 case SK_YUKON: 1433 case SK_YUKON_LITE: 1434 case SK_YUKON_LP: 1435 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1436 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1437 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1438 break; 1439 } 1440 1441 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1442 sk_ifmedia_upd, sk_ifmedia_sts); 1443 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1444 MII_OFFSET_ANY, 0); 1445 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1446 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1447 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1448 0, NULL); 1449 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1450 } else 1451 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1452 1453 callout_init(&sc_if->sk_tick_ch); 1454 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1455 1456 DPRINTFN(2, ("sk_attach: 1\n")); 1457 1458 /* 1459 * Call MI attach routines. 1460 */ 1461 if_attach(ifp); 1462 1463 ether_ifattach(ifp, sc_if->sk_enaddr); 1464 1465 #if NRND > 0 1466 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1467 RND_TYPE_NET, 0); 1468 #endif 1469 1470 DPRINTFN(2, ("sk_attach: end\n")); 1471 1472 return; 1473 1474 fail: 1475 sc->sk_if[sa->skc_port] = NULL; 1476 } 1477 1478 int 1479 skcprint(void *aux, const char *pnp) 1480 { 1481 struct skc_attach_args *sa = aux; 1482 1483 if (pnp) 1484 aprint_normal("sk port %c at %s", 1485 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1486 else 1487 aprint_normal(" port %c", 1488 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1489 return UNCONF; 1490 } 1491 1492 /* 1493 * Attach the interface. Allocate softc structures, do ifmedia 1494 * setup and ethernet/BPF attach. 1495 */ 1496 void 1497 skc_attach(struct device *parent, struct device *self, void *aux) 1498 { 1499 struct sk_softc *sc = (struct sk_softc *)self; 1500 struct pci_attach_args *pa = aux; 1501 struct skc_attach_args skca; 1502 pci_chipset_tag_t pc = pa->pa_pc; 1503 #ifndef SK_USEIOSPACE 1504 pcireg_t memtype; 1505 #endif 1506 pci_intr_handle_t ih; 1507 const char *intrstr = NULL; 1508 bus_addr_t iobase; 1509 bus_size_t iosize; 1510 int rc, sk_nodenum; 1511 u_int32_t command; 1512 const char *revstr; 1513 const struct sysctlnode *node; 1514 1515 DPRINTFN(2, ("begin skc_attach\n")); 1516 1517 /* 1518 * Handle power management nonsense. 1519 */ 1520 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1521 1522 if (command == 0x01) { 1523 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1524 if (command & SK_PSTATE_MASK) { 1525 u_int32_t xiobase, membase, irq; 1526 1527 /* Save important PCI config data. */ 1528 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1529 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1530 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1531 1532 /* Reset the power state. */ 1533 aprint_normal("%s chip is in D%d power mode " 1534 "-- setting to D0\n", sc->sk_dev.dv_xname, 1535 command & SK_PSTATE_MASK); 1536 command &= 0xFFFFFFFC; 1537 pci_conf_write(pc, pa->pa_tag, 1538 SK_PCI_PWRMGMTCTRL, command); 1539 1540 /* Restore PCI config data. */ 1541 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1542 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1543 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1544 } 1545 } 1546 1547 /* 1548 * Map control/status registers. 1549 */ 1550 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1551 command |= PCI_COMMAND_IO_ENABLE | 1552 PCI_COMMAND_MEM_ENABLE | 1553 PCI_COMMAND_MASTER_ENABLE; 1554 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1555 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1556 1557 #ifdef SK_USEIOSPACE 1558 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1559 aprint_error(": failed to enable I/O ports!\n"); 1560 return; 1561 } 1562 /* 1563 * Map control/status registers. 1564 */ 1565 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1566 &sc->sk_btag, &sc->sk_bhandle, 1567 &iobase, &iosize)) { 1568 aprint_error(": can't find i/o space\n"); 1569 return; 1570 } 1571 #else 1572 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1573 aprint_error(": failed to enable memory mapping!\n"); 1574 return; 1575 } 1576 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1577 switch (memtype) { 1578 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1579 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1580 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1581 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1582 &iobase, &iosize) == 0) 1583 break; 1584 default: 1585 aprint_error("%s: can't find mem space\n", 1586 sc->sk_dev.dv_xname); 1587 return; 1588 } 1589 1590 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1591 #endif 1592 sc->sc_dmatag = pa->pa_dmat; 1593 1594 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1595 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1596 1597 /* bail out here if chip is not recognized */ 1598 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1599 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1600 goto fail; 1601 } 1602 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1603 1604 /* Allocate interrupt */ 1605 if (pci_intr_map(pa, &ih)) { 1606 aprint_error(": couldn't map interrupt\n"); 1607 goto fail; 1608 } 1609 1610 intrstr = pci_intr_string(pc, ih); 1611 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1612 if (sc->sk_intrhand == NULL) { 1613 aprint_error(": couldn't establish interrupt"); 1614 if (intrstr != NULL) 1615 aprint_normal(" at %s", intrstr); 1616 goto fail; 1617 } 1618 aprint_normal(": %s\n", intrstr); 1619 1620 /* Reset the adapter. */ 1621 sk_reset(sc); 1622 1623 /* Read and save vital product data from EEPROM. */ 1624 sk_vpd_read(sc); 1625 1626 if (sc->sk_type == SK_GENESIS) { 1627 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1628 /* Read and save RAM size and RAMbuffer offset */ 1629 switch (val) { 1630 case SK_RAMSIZE_512K_64: 1631 sc->sk_ramsize = 0x80000; 1632 sc->sk_rboff = SK_RBOFF_0; 1633 break; 1634 case SK_RAMSIZE_1024K_64: 1635 sc->sk_ramsize = 0x100000; 1636 sc->sk_rboff = SK_RBOFF_80000; 1637 break; 1638 case SK_RAMSIZE_1024K_128: 1639 sc->sk_ramsize = 0x100000; 1640 sc->sk_rboff = SK_RBOFF_0; 1641 break; 1642 case SK_RAMSIZE_2048K_128: 1643 sc->sk_ramsize = 0x200000; 1644 sc->sk_rboff = SK_RBOFF_0; 1645 break; 1646 default: 1647 aprint_error("%s: unknown ram size: %d\n", 1648 sc->sk_dev.dv_xname, val); 1649 goto fail_1; 1650 break; 1651 } 1652 1653 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1654 sc->sk_ramsize, sc->sk_ramsize / 1024, 1655 sc->sk_rboff)); 1656 } else { 1657 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1658 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1659 sc->sk_rboff = SK_RBOFF_0; 1660 1661 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1662 sc->sk_ramsize / 1024, sc->sk_ramsize, 1663 sc->sk_rboff)); 1664 } 1665 1666 /* Read and save physical media type */ 1667 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1668 case SK_PMD_1000BASESX: 1669 sc->sk_pmd = IFM_1000_SX; 1670 break; 1671 case SK_PMD_1000BASELX: 1672 sc->sk_pmd = IFM_1000_LX; 1673 break; 1674 case SK_PMD_1000BASECX: 1675 sc->sk_pmd = IFM_1000_CX; 1676 break; 1677 case SK_PMD_1000BASETX: 1678 case SK_PMD_1000BASETX_ALT: 1679 sc->sk_pmd = IFM_1000_T; 1680 break; 1681 default: 1682 aprint_error("%s: unknown media type: 0x%x\n", 1683 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1684 goto fail_1; 1685 } 1686 1687 /* determine whether to name it with vpd or just make it up */ 1688 /* Marvell Yukon VPD's can freqently be bogus */ 1689 1690 switch (pa->pa_id) { 1691 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1692 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1693 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1694 case PCI_PRODUCT_3COM_3C940: 1695 case PCI_PRODUCT_DLINK_DGE530T: 1696 case PCI_PRODUCT_DLINK_DGE560T: 1697 case PCI_PRODUCT_DLINK_DGE560T_2: 1698 case PCI_PRODUCT_LINKSYS_EG1032: 1699 case PCI_PRODUCT_LINKSYS_EG1064: 1700 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1701 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1702 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1703 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1704 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1705 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1706 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1707 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1708 sc->sk_name = sc->sk_vpd_prodname; 1709 break; 1710 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1711 /* whoops yukon vpd prodname bears no resemblance to reality */ 1712 switch (sc->sk_type) { 1713 case SK_GENESIS: 1714 sc->sk_name = sc->sk_vpd_prodname; 1715 break; 1716 case SK_YUKON: 1717 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1718 break; 1719 case SK_YUKON_LITE: 1720 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1721 break; 1722 case SK_YUKON_LP: 1723 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1724 break; 1725 default: 1726 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1727 } 1728 1729 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1730 1731 if ( sc->sk_type == SK_YUKON ) { 1732 uint32_t flashaddr; 1733 uint8_t testbyte; 1734 1735 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1736 1737 /* test Flash-Address Register */ 1738 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1739 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1740 1741 if (testbyte != 0) { 1742 /* this is yukon lite Rev. A0 */ 1743 sc->sk_type = SK_YUKON_LITE; 1744 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1745 /* restore Flash-Address Register */ 1746 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1747 } 1748 } 1749 break; 1750 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1751 sc->sk_name = sc->sk_vpd_prodname; 1752 break; 1753 default: 1754 sc->sk_name = "Unknown Marvell"; 1755 } 1756 1757 1758 if ( sc->sk_type == SK_YUKON_LITE ) { 1759 switch (sc->sk_rev) { 1760 case SK_YUKON_LITE_REV_A0: 1761 revstr = "A0"; 1762 break; 1763 case SK_YUKON_LITE_REV_A1: 1764 revstr = "A1"; 1765 break; 1766 case SK_YUKON_LITE_REV_A3: 1767 revstr = "A3"; 1768 break; 1769 default: 1770 revstr = ""; 1771 } 1772 } else { 1773 revstr = ""; 1774 } 1775 1776 /* Announce the product name. */ 1777 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1778 sc->sk_name, revstr, sc->sk_rev); 1779 1780 skca.skc_port = SK_PORT_A; 1781 (void)config_found(&sc->sk_dev, &skca, skcprint); 1782 1783 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1784 skca.skc_port = SK_PORT_B; 1785 (void)config_found(&sc->sk_dev, &skca, skcprint); 1786 } 1787 1788 /* Turn on the 'driver is loaded' LED. */ 1789 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1790 1791 /* skc sysctl setup */ 1792 1793 sc->sk_int_mod = SK_IM_DEFAULT; 1794 sc->sk_int_mod_pending = 0; 1795 1796 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1797 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1798 SYSCTL_DESCR("skc per-controller controls"), 1799 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1800 CTL_EOL)) != 0) { 1801 aprint_normal("%s: couldn't create sysctl node\n", 1802 sc->sk_dev.dv_xname); 1803 goto fail_1; 1804 } 1805 1806 sk_nodenum = node->sysctl_num; 1807 1808 /* interrupt moderation time in usecs */ 1809 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1810 CTLFLAG_READWRITE, 1811 CTLTYPE_INT, "int_mod", 1812 SYSCTL_DESCR("sk interrupt moderation timer"), 1813 sk_sysctl_handler, 0, sc, 1814 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1815 CTL_EOL)) != 0) { 1816 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1817 sc->sk_dev.dv_xname); 1818 goto fail_1; 1819 } 1820 1821 return; 1822 1823 fail_1: 1824 pci_intr_disestablish(pc, sc->sk_intrhand); 1825 fail: 1826 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1827 } 1828 1829 int 1830 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1831 { 1832 struct sk_softc *sc = sc_if->sk_softc; 1833 struct sk_tx_desc *f = NULL; 1834 u_int32_t frag, cur, cnt = 0, sk_ctl; 1835 int i; 1836 struct sk_txmap_entry *entry; 1837 bus_dmamap_t txmap; 1838 1839 DPRINTFN(3, ("sk_encap\n")); 1840 1841 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1842 if (entry == NULL) { 1843 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1844 return ENOBUFS; 1845 } 1846 txmap = entry->dmamap; 1847 1848 cur = frag = *txidx; 1849 1850 #ifdef SK_DEBUG 1851 if (skdebug >= 3) 1852 sk_dump_mbuf(m_head); 1853 #endif 1854 1855 /* 1856 * Start packing the mbufs in this chain into 1857 * the fragment pointers. Stop when we run out 1858 * of fragments or hit the end of the mbuf chain. 1859 */ 1860 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1861 BUS_DMA_NOWAIT)) { 1862 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1863 return ENOBUFS; 1864 } 1865 1866 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1867 1868 /* Sync the DMA map. */ 1869 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1870 BUS_DMASYNC_PREWRITE); 1871 1872 for (i = 0; i < txmap->dm_nsegs; i++) { 1873 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1874 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1875 return ENOBUFS; 1876 } 1877 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1878 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1879 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1880 if (cnt == 0) 1881 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1882 else 1883 sk_ctl |= SK_TXCTL_OWN; 1884 f->sk_ctl = htole32(sk_ctl); 1885 cur = frag; 1886 SK_INC(frag, SK_TX_RING_CNT); 1887 cnt++; 1888 } 1889 1890 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1891 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1892 1893 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1894 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1895 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1896 1897 /* Sync descriptors before handing to chip */ 1898 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1899 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1900 1901 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1902 htole32(SK_TXCTL_OWN); 1903 1904 /* Sync first descriptor to hand it off */ 1905 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1906 1907 sc_if->sk_cdata.sk_tx_cnt += cnt; 1908 1909 #ifdef SK_DEBUG 1910 if (skdebug >= 3) { 1911 struct sk_tx_desc *desc; 1912 u_int32_t idx; 1913 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1914 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1915 sk_dump_txdesc(desc, idx); 1916 } 1917 } 1918 #endif 1919 1920 *txidx = frag; 1921 1922 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1923 1924 return 0; 1925 } 1926 1927 void 1928 sk_start(struct ifnet *ifp) 1929 { 1930 struct sk_if_softc *sc_if = ifp->if_softc; 1931 struct sk_softc *sc = sc_if->sk_softc; 1932 struct mbuf *m_head = NULL; 1933 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1934 int pkts = 0; 1935 1936 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1937 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1938 1939 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1940 IFQ_POLL(&ifp->if_snd, m_head); 1941 if (m_head == NULL) 1942 break; 1943 1944 /* 1945 * Pack the data into the transmit ring. If we 1946 * don't have room, set the OACTIVE flag and wait 1947 * for the NIC to drain the ring. 1948 */ 1949 if (sk_encap(sc_if, m_head, &idx)) { 1950 ifp->if_flags |= IFF_OACTIVE; 1951 break; 1952 } 1953 1954 /* now we are committed to transmit the packet */ 1955 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1956 pkts++; 1957 1958 /* 1959 * If there's a BPF listener, bounce a copy of this frame 1960 * to him. 1961 */ 1962 #if NBPFILTER > 0 1963 if (ifp->if_bpf) 1964 bpf_mtap(ifp->if_bpf, m_head); 1965 #endif 1966 } 1967 if (pkts == 0) 1968 return; 1969 1970 /* Transmit */ 1971 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1972 sc_if->sk_cdata.sk_tx_prod = idx; 1973 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1974 1975 /* Set a timeout in case the chip goes out to lunch. */ 1976 ifp->if_timer = 5; 1977 } 1978 } 1979 1980 1981 void 1982 sk_watchdog(struct ifnet *ifp) 1983 { 1984 struct sk_if_softc *sc_if = ifp->if_softc; 1985 1986 /* 1987 * Reclaim first as there is a possibility of losing Tx completion 1988 * interrupts. 1989 */ 1990 sk_txeof(sc_if); 1991 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1992 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1993 1994 ifp->if_oerrors++; 1995 1996 sk_init(ifp); 1997 } 1998 } 1999 2000 void 2001 sk_shutdown(void *v) 2002 { 2003 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2004 struct sk_softc *sc = sc_if->sk_softc; 2005 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2006 2007 DPRINTFN(2, ("sk_shutdown\n")); 2008 sk_stop(ifp,1); 2009 2010 /* Turn off the 'driver is loaded' LED. */ 2011 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2012 2013 /* 2014 * Reset the GEnesis controller. Doing this should also 2015 * assert the resets on the attached XMAC(s). 2016 */ 2017 sk_reset(sc); 2018 } 2019 2020 void 2021 sk_rxeof(struct sk_if_softc *sc_if) 2022 { 2023 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2024 struct mbuf *m; 2025 struct sk_chain *cur_rx; 2026 struct sk_rx_desc *cur_desc; 2027 int i, cur, total_len = 0; 2028 u_int32_t rxstat, sk_ctl; 2029 bus_dmamap_t dmamap; 2030 2031 i = sc_if->sk_cdata.sk_rx_prod; 2032 2033 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2034 2035 for (;;) { 2036 cur = i; 2037 2038 /* Sync the descriptor */ 2039 SK_CDRXSYNC(sc_if, cur, 2040 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2041 2042 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2043 if (sk_ctl & SK_RXCTL_OWN) { 2044 /* Invalidate the descriptor -- it's not ready yet */ 2045 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2046 sc_if->sk_cdata.sk_rx_prod = i; 2047 break; 2048 } 2049 2050 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2051 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2052 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2053 2054 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2055 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2056 2057 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2058 m = cur_rx->sk_mbuf; 2059 cur_rx->sk_mbuf = NULL; 2060 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2061 2062 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2063 2064 SK_INC(i, SK_RX_RING_CNT); 2065 2066 if (rxstat & XM_RXSTAT_ERRFRAME) { 2067 ifp->if_ierrors++; 2068 sk_newbuf(sc_if, cur, m, dmamap); 2069 continue; 2070 } 2071 2072 /* 2073 * Try to allocate a new jumbo buffer. If that 2074 * fails, copy the packet to mbufs and put the 2075 * jumbo buffer back in the ring so it can be 2076 * re-used. If allocating mbufs fails, then we 2077 * have to drop the packet. 2078 */ 2079 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2080 struct mbuf *m0; 2081 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2082 total_len + ETHER_ALIGN, 0, ifp, NULL); 2083 sk_newbuf(sc_if, cur, m, dmamap); 2084 if (m0 == NULL) { 2085 aprint_error("%s: no receive buffers " 2086 "available -- packet dropped!\n", 2087 sc_if->sk_dev.dv_xname); 2088 ifp->if_ierrors++; 2089 continue; 2090 } 2091 m_adj(m0, ETHER_ALIGN); 2092 m = m0; 2093 } else { 2094 m->m_pkthdr.rcvif = ifp; 2095 m->m_pkthdr.len = m->m_len = total_len; 2096 } 2097 2098 ifp->if_ipackets++; 2099 2100 #if NBPFILTER > 0 2101 if (ifp->if_bpf) 2102 bpf_mtap(ifp->if_bpf, m); 2103 #endif 2104 /* pass it on. */ 2105 (*ifp->if_input)(ifp, m); 2106 } 2107 } 2108 2109 void 2110 sk_txeof(struct sk_if_softc *sc_if) 2111 { 2112 struct sk_softc *sc = sc_if->sk_softc; 2113 struct sk_tx_desc *cur_tx; 2114 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2115 u_int32_t idx, sk_ctl; 2116 struct sk_txmap_entry *entry; 2117 2118 DPRINTFN(3, ("sk_txeof\n")); 2119 2120 /* 2121 * Go through our tx ring and free mbufs for those 2122 * frames that have been sent. 2123 */ 2124 idx = sc_if->sk_cdata.sk_tx_cons; 2125 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2126 SK_CDTXSYNC(sc_if, idx, 1, 2127 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2128 2129 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2130 sk_ctl = le32toh(cur_tx->sk_ctl); 2131 #ifdef SK_DEBUG 2132 if (skdebug >= 3) 2133 sk_dump_txdesc(cur_tx, idx); 2134 #endif 2135 if (sk_ctl & SK_TXCTL_OWN) { 2136 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2137 break; 2138 } 2139 if (sk_ctl & SK_TXCTL_LASTFRAG) 2140 ifp->if_opackets++; 2141 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2142 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2143 2144 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2145 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2146 2147 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2148 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2149 2150 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2151 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2152 link); 2153 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2154 } 2155 sc_if->sk_cdata.sk_tx_cnt--; 2156 SK_INC(idx, SK_TX_RING_CNT); 2157 } 2158 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2159 ifp->if_timer = 0; 2160 else /* nudge chip to keep tx ring moving */ 2161 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2162 2163 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2164 ifp->if_flags &= ~IFF_OACTIVE; 2165 2166 sc_if->sk_cdata.sk_tx_cons = idx; 2167 } 2168 2169 void 2170 sk_tick(void *xsc_if) 2171 { 2172 struct sk_if_softc *sc_if = xsc_if; 2173 struct mii_data *mii = &sc_if->sk_mii; 2174 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2175 int i; 2176 2177 DPRINTFN(3, ("sk_tick\n")); 2178 2179 if (!(ifp->if_flags & IFF_UP)) 2180 return; 2181 2182 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2183 sk_intr_bcom(sc_if); 2184 return; 2185 } 2186 2187 /* 2188 * According to SysKonnect, the correct way to verify that 2189 * the link has come back up is to poll bit 0 of the GPIO 2190 * register three times. This pin has the signal from the 2191 * link sync pin connected to it; if we read the same link 2192 * state 3 times in a row, we know the link is up. 2193 */ 2194 for (i = 0; i < 3; i++) { 2195 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2196 break; 2197 } 2198 2199 if (i != 3) { 2200 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2201 return; 2202 } 2203 2204 /* Turn the GP0 interrupt back on. */ 2205 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2206 SK_XM_READ_2(sc_if, XM_ISR); 2207 mii_tick(mii); 2208 mii_pollstat(mii); 2209 callout_stop(&sc_if->sk_tick_ch); 2210 } 2211 2212 void 2213 sk_intr_bcom(struct sk_if_softc *sc_if) 2214 { 2215 struct mii_data *mii = &sc_if->sk_mii; 2216 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2217 int status; 2218 2219 2220 DPRINTFN(3, ("sk_intr_bcom\n")); 2221 2222 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2223 2224 /* 2225 * Read the PHY interrupt register to make sure 2226 * we clear any pending interrupts. 2227 */ 2228 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2229 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2230 2231 if (!(ifp->if_flags & IFF_RUNNING)) { 2232 sk_init_xmac(sc_if); 2233 return; 2234 } 2235 2236 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2237 int lstat; 2238 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2239 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2240 2241 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2242 mii_mediachg(mii); 2243 /* Turn off the link LED. */ 2244 SK_IF_WRITE_1(sc_if, 0, 2245 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2246 sc_if->sk_link = 0; 2247 } else if (status & BRGPHY_ISR_LNK_CHG) { 2248 sk_xmac_miibus_writereg((struct device *)sc_if, 2249 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2250 mii_tick(mii); 2251 sc_if->sk_link = 1; 2252 /* Turn on the link LED. */ 2253 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2254 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2255 SK_LINKLED_BLINK_OFF); 2256 mii_pollstat(mii); 2257 } else { 2258 mii_tick(mii); 2259 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2260 } 2261 } 2262 2263 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2264 } 2265 2266 void 2267 sk_intr_xmac(struct sk_if_softc *sc_if) 2268 { 2269 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2270 2271 DPRINTFN(3, ("sk_intr_xmac\n")); 2272 2273 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2274 if (status & XM_ISR_GP0_SET) { 2275 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2276 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2277 } 2278 2279 if (status & XM_ISR_AUTONEG_DONE) { 2280 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2281 } 2282 } 2283 2284 if (status & XM_IMR_TX_UNDERRUN) 2285 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2286 2287 if (status & XM_IMR_RX_OVERRUN) 2288 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2289 } 2290 2291 void 2292 sk_intr_yukon(struct sk_if_softc *sc_if) 2293 { 2294 int status; 2295 2296 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2297 2298 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2299 } 2300 2301 int 2302 sk_intr(void *xsc) 2303 { 2304 struct sk_softc *sc = xsc; 2305 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2306 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2307 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2308 u_int32_t status; 2309 int claimed = 0; 2310 2311 if (sc_if0 != NULL) 2312 ifp0 = &sc_if0->sk_ethercom.ec_if; 2313 if (sc_if1 != NULL) 2314 ifp1 = &sc_if1->sk_ethercom.ec_if; 2315 2316 for (;;) { 2317 status = CSR_READ_4(sc, SK_ISSR); 2318 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2319 2320 if (!(status & sc->sk_intrmask)) 2321 break; 2322 2323 claimed = 1; 2324 2325 /* Handle receive interrupts first. */ 2326 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2327 sk_rxeof(sc_if0); 2328 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2329 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2330 } 2331 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2332 sk_rxeof(sc_if1); 2333 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2334 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2335 } 2336 2337 /* Then transmit interrupts. */ 2338 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2339 sk_txeof(sc_if0); 2340 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2341 SK_TXBMU_CLR_IRQ_EOF); 2342 } 2343 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2344 sk_txeof(sc_if1); 2345 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2346 SK_TXBMU_CLR_IRQ_EOF); 2347 } 2348 2349 /* Then MAC interrupts. */ 2350 if (sc_if0 && (status & SK_ISR_MAC1) && 2351 (ifp0->if_flags & IFF_RUNNING)) { 2352 if (sc->sk_type == SK_GENESIS) 2353 sk_intr_xmac(sc_if0); 2354 else 2355 sk_intr_yukon(sc_if0); 2356 } 2357 2358 if (sc_if1 && (status & SK_ISR_MAC2) && 2359 (ifp1->if_flags & IFF_RUNNING)) { 2360 if (sc->sk_type == SK_GENESIS) 2361 sk_intr_xmac(sc_if1); 2362 else 2363 sk_intr_yukon(sc_if1); 2364 2365 } 2366 2367 if (status & SK_ISR_EXTERNAL_REG) { 2368 if (sc_if0 != NULL && 2369 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2370 sk_intr_bcom(sc_if0); 2371 2372 if (sc_if1 != NULL && 2373 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2374 sk_intr_bcom(sc_if1); 2375 } 2376 } 2377 2378 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2379 2380 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2381 sk_start(ifp0); 2382 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2383 sk_start(ifp1); 2384 2385 #if NRND > 0 2386 if (RND_ENABLED(&sc->rnd_source)) 2387 rnd_add_uint32(&sc->rnd_source, status); 2388 #endif 2389 2390 if (sc->sk_int_mod_pending) 2391 sk_update_int_mod(sc); 2392 2393 return claimed; 2394 } 2395 2396 void 2397 sk_init_xmac(struct sk_if_softc *sc_if) 2398 { 2399 struct sk_softc *sc = sc_if->sk_softc; 2400 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2401 static const struct sk_bcom_hack bhack[] = { 2402 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2403 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2404 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2405 { 0, 0 } }; 2406 2407 DPRINTFN(1, ("sk_init_xmac\n")); 2408 2409 /* Unreset the XMAC. */ 2410 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2411 DELAY(1000); 2412 2413 /* Reset the XMAC's internal state. */ 2414 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2415 2416 /* Save the XMAC II revision */ 2417 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2418 2419 /* 2420 * Perform additional initialization for external PHYs, 2421 * namely for the 1000baseTX cards that use the XMAC's 2422 * GMII mode. 2423 */ 2424 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2425 int i = 0; 2426 u_int32_t val; 2427 2428 /* Take PHY out of reset. */ 2429 val = sk_win_read_4(sc, SK_GPIO); 2430 if (sc_if->sk_port == SK_PORT_A) 2431 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2432 else 2433 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2434 sk_win_write_4(sc, SK_GPIO, val); 2435 2436 /* Enable GMII mode on the XMAC. */ 2437 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2438 2439 sk_xmac_miibus_writereg((struct device *)sc_if, 2440 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2441 DELAY(10000); 2442 sk_xmac_miibus_writereg((struct device *)sc_if, 2443 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2444 2445 /* 2446 * Early versions of the BCM5400 apparently have 2447 * a bug that requires them to have their reserved 2448 * registers initialized to some magic values. I don't 2449 * know what the numbers do, I'm just the messenger. 2450 */ 2451 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2452 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2453 while (bhack[i].reg) { 2454 sk_xmac_miibus_writereg((struct device *)sc_if, 2455 SK_PHYADDR_BCOM, bhack[i].reg, 2456 bhack[i].val); 2457 i++; 2458 } 2459 } 2460 } 2461 2462 /* Set station address */ 2463 SK_XM_WRITE_2(sc_if, XM_PAR0, 2464 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2465 SK_XM_WRITE_2(sc_if, XM_PAR1, 2466 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2467 SK_XM_WRITE_2(sc_if, XM_PAR2, 2468 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2469 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2470 2471 if (ifp->if_flags & IFF_PROMISC) 2472 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2473 else 2474 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2475 2476 if (ifp->if_flags & IFF_BROADCAST) 2477 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2478 else 2479 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2480 2481 /* We don't need the FCS appended to the packet. */ 2482 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2483 2484 /* We want short frames padded to 60 bytes. */ 2485 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2486 2487 /* 2488 * Enable the reception of all error frames. This is is 2489 * a necessary evil due to the design of the XMAC. The 2490 * XMAC's receive FIFO is only 8K in size, however jumbo 2491 * frames can be up to 9000 bytes in length. When bad 2492 * frame filtering is enabled, the XMAC's RX FIFO operates 2493 * in 'store and forward' mode. For this to work, the 2494 * entire frame has to fit into the FIFO, but that means 2495 * that jumbo frames larger than 8192 bytes will be 2496 * truncated. Disabling all bad frame filtering causes 2497 * the RX FIFO to operate in streaming mode, in which 2498 * case the XMAC will start transfering frames out of the 2499 * RX FIFO as soon as the FIFO threshold is reached. 2500 */ 2501 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2502 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2503 XM_MODE_RX_INRANGELEN); 2504 2505 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2506 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2507 else 2508 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2509 2510 /* 2511 * Bump up the transmit threshold. This helps hold off transmit 2512 * underruns when we're blasting traffic from both ports at once. 2513 */ 2514 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2515 2516 /* Set multicast filter */ 2517 sk_setmulti(sc_if); 2518 2519 /* Clear and enable interrupts */ 2520 SK_XM_READ_2(sc_if, XM_ISR); 2521 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2522 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2523 else 2524 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2525 2526 /* Configure MAC arbiter */ 2527 switch (sc_if->sk_xmac_rev) { 2528 case XM_XMAC_REV_B2: 2529 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2530 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2531 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2532 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2533 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2534 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2535 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2536 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2537 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2538 break; 2539 case XM_XMAC_REV_C1: 2540 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2541 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2542 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2543 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2544 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2545 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2546 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2547 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2548 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2549 break; 2550 default: 2551 break; 2552 } 2553 sk_win_write_2(sc, SK_MACARB_CTL, 2554 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2555 2556 sc_if->sk_link = 1; 2557 } 2558 2559 void sk_init_yukon(struct sk_if_softc *sc_if) 2560 { 2561 u_int32_t /*mac, */phy; 2562 u_int16_t reg; 2563 struct sk_softc *sc; 2564 int i; 2565 2566 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2567 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2568 2569 sc = sc_if->sk_softc; 2570 if (sc->sk_type == SK_YUKON_LITE && 2571 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2572 /* Take PHY out of reset. */ 2573 sk_win_write_4(sc, SK_GPIO, 2574 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2575 } 2576 2577 2578 /* GMAC and GPHY Reset */ 2579 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2580 2581 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2582 2583 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2584 DELAY(1000); 2585 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2586 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2587 DELAY(1000); 2588 2589 2590 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2591 2592 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2593 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2594 2595 switch (sc_if->sk_softc->sk_pmd) { 2596 case IFM_1000_SX: 2597 case IFM_1000_LX: 2598 phy |= SK_GPHY_FIBER; 2599 break; 2600 2601 case IFM_1000_CX: 2602 case IFM_1000_T: 2603 phy |= SK_GPHY_COPPER; 2604 break; 2605 } 2606 2607 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2608 2609 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2610 DELAY(1000); 2611 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2612 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2613 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2614 2615 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2616 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2617 2618 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2619 2620 /* unused read of the interrupt source register */ 2621 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2622 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2623 2624 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2625 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2626 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2627 2628 /* MIB Counter Clear Mode set */ 2629 reg |= YU_PAR_MIB_CLR; 2630 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2631 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2632 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2633 2634 /* MIB Counter Clear Mode clear */ 2635 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2636 reg &= ~YU_PAR_MIB_CLR; 2637 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2638 2639 /* receive control reg */ 2640 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2641 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2642 YU_RCR_CRCR); 2643 2644 /* transmit parameter register */ 2645 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2646 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2647 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2648 2649 /* serial mode register */ 2650 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2651 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2652 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2653 YU_SMR_IPG_DATA(0x1e)); 2654 2655 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2656 /* Setup Yukon's address */ 2657 for (i = 0; i < 3; i++) { 2658 /* Write Source Address 1 (unicast filter) */ 2659 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2660 sc_if->sk_enaddr[i * 2] | 2661 sc_if->sk_enaddr[i * 2 + 1] << 8); 2662 } 2663 2664 for (i = 0; i < 3; i++) { 2665 reg = sk_win_read_2(sc_if->sk_softc, 2666 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2667 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2668 } 2669 2670 /* Set multicast filter */ 2671 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2672 sk_setmulti(sc_if); 2673 2674 /* enable interrupt mask for counter overflows */ 2675 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2676 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2677 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2678 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2679 2680 /* Configure RX MAC FIFO */ 2681 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2682 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2683 2684 /* Configure TX MAC FIFO */ 2685 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2686 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2687 2688 DPRINTFN(6, ("sk_init_yukon: end\n")); 2689 } 2690 2691 /* 2692 * Note that to properly initialize any part of the GEnesis chip, 2693 * you first have to take it out of reset mode. 2694 */ 2695 int 2696 sk_init(struct ifnet *ifp) 2697 { 2698 struct sk_if_softc *sc_if = ifp->if_softc; 2699 struct sk_softc *sc = sc_if->sk_softc; 2700 struct mii_data *mii = &sc_if->sk_mii; 2701 int s; 2702 u_int32_t imr, imtimer_ticks; 2703 2704 DPRINTFN(1, ("sk_init\n")); 2705 2706 s = splnet(); 2707 2708 if (ifp->if_flags & IFF_RUNNING) { 2709 splx(s); 2710 return 0; 2711 } 2712 2713 /* Cancel pending I/O and free all RX/TX buffers. */ 2714 sk_stop(ifp,0); 2715 2716 if (sc->sk_type == SK_GENESIS) { 2717 /* Configure LINK_SYNC LED */ 2718 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2719 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2720 SK_LINKLED_LINKSYNC_ON); 2721 2722 /* Configure RX LED */ 2723 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2724 SK_RXLEDCTL_COUNTER_START); 2725 2726 /* Configure TX LED */ 2727 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2728 SK_TXLEDCTL_COUNTER_START); 2729 } 2730 2731 /* Configure I2C registers */ 2732 2733 /* Configure XMAC(s) */ 2734 switch (sc->sk_type) { 2735 case SK_GENESIS: 2736 sk_init_xmac(sc_if); 2737 break; 2738 case SK_YUKON: 2739 case SK_YUKON_LITE: 2740 case SK_YUKON_LP: 2741 sk_init_yukon(sc_if); 2742 break; 2743 } 2744 mii_mediachg(mii); 2745 2746 if (sc->sk_type == SK_GENESIS) { 2747 /* Configure MAC FIFOs */ 2748 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2749 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2750 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2751 2752 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2753 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2754 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2755 } 2756 2757 /* Configure transmit arbiter(s) */ 2758 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2759 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2760 2761 /* Configure RAMbuffers */ 2762 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2763 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2764 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2765 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2766 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2767 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2768 2769 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2770 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2771 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2772 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2773 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2774 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2775 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2776 2777 /* Configure BMUs */ 2778 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2779 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2780 SK_RX_RING_ADDR(sc_if, 0)); 2781 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2782 2783 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2784 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2785 SK_TX_RING_ADDR(sc_if, 0)); 2786 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2787 2788 /* Init descriptors */ 2789 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2790 aprint_error("%s: initialization failed: no " 2791 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2792 sk_stop(ifp,0); 2793 splx(s); 2794 return ENOBUFS; 2795 } 2796 2797 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2798 aprint_error("%s: initialization failed: no " 2799 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2800 sk_stop(ifp,0); 2801 splx(s); 2802 return ENOBUFS; 2803 } 2804 2805 /* Set interrupt moderation if changed via sysctl. */ 2806 switch (sc->sk_type) { 2807 case SK_GENESIS: 2808 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2809 break; 2810 case SK_YUKON_EC: 2811 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2812 break; 2813 default: 2814 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2815 } 2816 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2817 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2818 sk_win_write_4(sc, SK_IMTIMERINIT, 2819 SK_IM_USECS(sc->sk_int_mod)); 2820 aprint_verbose("%s: interrupt moderation is %d us\n", 2821 sc->sk_dev.dv_xname, sc->sk_int_mod); 2822 } 2823 2824 /* Configure interrupt handling */ 2825 CSR_READ_4(sc, SK_ISSR); 2826 if (sc_if->sk_port == SK_PORT_A) 2827 sc->sk_intrmask |= SK_INTRS1; 2828 else 2829 sc->sk_intrmask |= SK_INTRS2; 2830 2831 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2832 2833 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2834 2835 /* Start BMUs. */ 2836 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2837 2838 if (sc->sk_type == SK_GENESIS) { 2839 /* Enable XMACs TX and RX state machines */ 2840 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2841 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2842 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2843 } 2844 2845 if (SK_YUKON_FAMILY(sc->sk_type)) { 2846 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2847 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2848 #if 0 2849 /* XXX disable 100Mbps and full duplex mode? */ 2850 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2851 #endif 2852 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2853 } 2854 2855 2856 ifp->if_flags |= IFF_RUNNING; 2857 ifp->if_flags &= ~IFF_OACTIVE; 2858 2859 splx(s); 2860 return 0; 2861 } 2862 2863 void 2864 sk_stop(struct ifnet *ifp, int disable) 2865 { 2866 struct sk_if_softc *sc_if = ifp->if_softc; 2867 struct sk_softc *sc = sc_if->sk_softc; 2868 int i; 2869 2870 DPRINTFN(1, ("sk_stop\n")); 2871 2872 callout_stop(&sc_if->sk_tick_ch); 2873 2874 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2875 u_int32_t val; 2876 2877 /* Put PHY back into reset. */ 2878 val = sk_win_read_4(sc, SK_GPIO); 2879 if (sc_if->sk_port == SK_PORT_A) { 2880 val |= SK_GPIO_DIR0; 2881 val &= ~SK_GPIO_DAT0; 2882 } else { 2883 val |= SK_GPIO_DIR2; 2884 val &= ~SK_GPIO_DAT2; 2885 } 2886 sk_win_write_4(sc, SK_GPIO, val); 2887 } 2888 2889 /* Turn off various components of this interface. */ 2890 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2891 switch (sc->sk_type) { 2892 case SK_GENESIS: 2893 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2894 SK_TXMACCTL_XMAC_RESET); 2895 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2896 break; 2897 case SK_YUKON: 2898 case SK_YUKON_LITE: 2899 case SK_YUKON_LP: 2900 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2901 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2902 break; 2903 } 2904 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2905 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2906 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2907 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2908 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2909 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2910 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2911 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2912 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2913 2914 /* Disable interrupts */ 2915 if (sc_if->sk_port == SK_PORT_A) 2916 sc->sk_intrmask &= ~SK_INTRS1; 2917 else 2918 sc->sk_intrmask &= ~SK_INTRS2; 2919 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2920 2921 SK_XM_READ_2(sc_if, XM_ISR); 2922 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2923 2924 /* Free RX and TX mbufs still in the queues. */ 2925 for (i = 0; i < SK_RX_RING_CNT; i++) { 2926 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2927 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2928 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2929 } 2930 } 2931 2932 for (i = 0; i < SK_TX_RING_CNT; i++) { 2933 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2934 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2935 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2936 } 2937 } 2938 2939 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2940 } 2941 2942 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2943 2944 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2945 2946 #ifdef SK_DEBUG 2947 void 2948 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2949 { 2950 #define DESC_PRINT(X) \ 2951 if (X) \ 2952 printf("txdesc[%d]." #X "=%#x\n", \ 2953 idx, X); 2954 2955 DESC_PRINT(le32toh(desc->sk_ctl)); 2956 DESC_PRINT(le32toh(desc->sk_next)); 2957 DESC_PRINT(le32toh(desc->sk_data_lo)); 2958 DESC_PRINT(le32toh(desc->sk_data_hi)); 2959 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2960 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2961 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2962 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2963 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2964 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2965 #undef PRINT 2966 } 2967 2968 void 2969 sk_dump_bytes(const char *data, int len) 2970 { 2971 int c, i, j; 2972 2973 for (i = 0; i < len; i += 16) { 2974 printf("%08x ", i); 2975 c = len - i; 2976 if (c > 16) c = 16; 2977 2978 for (j = 0; j < c; j++) { 2979 printf("%02x ", data[i + j] & 0xff); 2980 if ((j & 0xf) == 7 && j > 0) 2981 printf(" "); 2982 } 2983 2984 for (; j < 16; j++) 2985 printf(" "); 2986 printf(" "); 2987 2988 for (j = 0; j < c; j++) { 2989 int ch = data[i + j] & 0xff; 2990 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2991 } 2992 2993 printf("\n"); 2994 2995 if (c < 16) 2996 break; 2997 } 2998 } 2999 3000 void 3001 sk_dump_mbuf(struct mbuf *m) 3002 { 3003 int count = m->m_pkthdr.len; 3004 3005 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3006 3007 while (count > 0 && m) { 3008 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3009 m, m->m_data, m->m_len); 3010 sk_dump_bytes(mtod(m, char *), m->m_len); 3011 3012 count -= m->m_len; 3013 m = m->m_next; 3014 } 3015 } 3016 #endif 3017 3018 static int 3019 sk_sysctl_handler(SYSCTLFN_ARGS) 3020 { 3021 int error, t; 3022 struct sysctlnode node; 3023 struct sk_softc *sc; 3024 3025 node = *rnode; 3026 sc = node.sysctl_data; 3027 t = sc->sk_int_mod; 3028 node.sysctl_data = &t; 3029 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3030 if (error || newp == NULL) 3031 return error; 3032 3033 if (t < SK_IM_MIN || t > SK_IM_MAX) 3034 return EINVAL; 3035 3036 /* update the softc with sysctl-changed value, and mark 3037 for hardware update */ 3038 sc->sk_int_mod = t; 3039 sc->sk_int_mod_pending = 1; 3040 return 0; 3041 } 3042 3043 /* 3044 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3045 * set up in skc_attach() 3046 */ 3047 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3048 { 3049 int rc; 3050 const struct sysctlnode *node; 3051 3052 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3053 0, CTLTYPE_NODE, "hw", NULL, 3054 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3055 goto err; 3056 } 3057 3058 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3059 0, CTLTYPE_NODE, "sk", 3060 SYSCTL_DESCR("sk interface controls"), 3061 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3062 goto err; 3063 } 3064 3065 sk_root_num = node->sysctl_num; 3066 return; 3067 3068 err: 3069 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3070 } 3071
Indexes created Mon Sep 22 21:09:42 GMT 2025