if_sk.c revision 1.40
1 /* $NetBSD: if_sk.c,v 1.40 2007/07/06 18:52:52 briggs Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 #include "rnd.h" 126 127 #include <sys/param.h> 128 #include <sys/systm.h> 129 #include <sys/sockio.h> 130 #include <sys/mbuf.h> 131 #include <sys/malloc.h> 132 #include <sys/kernel.h> 133 #include <sys/socket.h> 134 #include <sys/device.h> 135 #include <sys/queue.h> 136 #include <sys/callout.h> 137 #include <sys/sysctl.h> 138 #include <sys/endian.h> 139 140 #include <net/if.h> 141 #include <net/if_dl.h> 142 #include <net/if_types.h> 143 144 #include <net/if_media.h> 145 146 #if NBPFILTER > 0 147 #include <net/bpf.h> 148 #endif 149 #if NRND > 0 150 #include <sys/rnd.h> 151 #endif 152 153 #include <dev/mii/mii.h> 154 #include <dev/mii/miivar.h> 155 #include <dev/mii/brgphyreg.h> 156 157 #include <dev/pci/pcireg.h> 158 #include <dev/pci/pcivar.h> 159 #include <dev/pci/pcidevs.h> 160 161 /* #define SK_USEIOSPACE */ 162 163 #include <dev/pci/if_skreg.h> 164 #include <dev/pci/if_skvar.h> 165 166 int skc_probe(struct device *, struct cfdata *, void *); 167 void skc_attach(struct device *, struct device *self, void *aux); 168 int sk_probe(struct device *, struct cfdata *, void *); 169 void sk_attach(struct device *, struct device *self, void *aux); 170 int skcprint(void *, const char *); 171 int sk_intr(void *); 172 void sk_intr_bcom(struct sk_if_softc *); 173 void sk_intr_xmac(struct sk_if_softc *); 174 void sk_intr_yukon(struct sk_if_softc *); 175 void sk_rxeof(struct sk_if_softc *); 176 void sk_txeof(struct sk_if_softc *); 177 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 178 void sk_start(struct ifnet *); 179 int sk_ioctl(struct ifnet *, u_long, void *); 180 int sk_init(struct ifnet *); 181 void sk_init_xmac(struct sk_if_softc *); 182 void sk_init_yukon(struct sk_if_softc *); 183 void sk_stop(struct ifnet *, int); 184 void sk_watchdog(struct ifnet *); 185 void sk_shutdown(void *); 186 int sk_ifmedia_upd(struct ifnet *); 187 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 188 void sk_reset(struct sk_softc *); 189 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 190 int sk_alloc_jumbo_mem(struct sk_if_softc *); 191 void sk_free_jumbo_mem(struct sk_if_softc *); 192 void *sk_jalloc(struct sk_if_softc *); 193 void sk_jfree(struct mbuf *, void *, size_t, void *); 194 int sk_init_rx_ring(struct sk_if_softc *); 195 int sk_init_tx_ring(struct sk_if_softc *); 196 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 197 void sk_vpd_read_res(struct sk_softc *, 198 struct vpd_res *, int); 199 void sk_vpd_read(struct sk_softc *); 200 201 void sk_update_int_mod(struct sk_softc *); 202 203 int sk_xmac_miibus_readreg(struct device *, int, int); 204 void sk_xmac_miibus_writereg(struct device *, int, int, int); 205 void sk_xmac_miibus_statchg(struct device *); 206 207 int sk_marv_miibus_readreg(struct device *, int, int); 208 void sk_marv_miibus_writereg(struct device *, int, int, int); 209 void sk_marv_miibus_statchg(struct device *); 210 211 u_int32_t sk_xmac_hash(void *); 212 u_int32_t sk_yukon_hash(void *); 213 void sk_setfilt(struct sk_if_softc *, void *, int); 214 void sk_setmulti(struct sk_if_softc *); 215 void sk_tick(void *); 216 217 /* #define SK_DEBUG 2 */ 218 #ifdef SK_DEBUG 219 #define DPRINTF(x) if (skdebug) printf x 220 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 221 int skdebug = SK_DEBUG; 222 223 void sk_dump_txdesc(struct sk_tx_desc *, int); 224 void sk_dump_mbuf(struct mbuf *); 225 void sk_dump_bytes(const char *, int); 226 #else 227 #define DPRINTF(x) 228 #define DPRINTFN(n,x) 229 #endif 230 231 static int sk_sysctl_handler(SYSCTLFN_PROTO); 232 static int sk_root_num; 233 234 /* supported device vendors */ 235 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 236 static const struct sk_product { 237 pci_vendor_id_t sk_vendor; 238 pci_product_id_t sk_product; 239 } sk_products[] = { 240 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 241 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 242 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 243 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 244 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 245 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 246 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 247 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 248 { 0, 0, } 249 }; 250 251 #define SK_LINKSYS_EG1032_SUBID 0x00151737 252 253 static inline u_int32_t 254 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 255 { 256 #ifdef SK_USEIOSPACE 257 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 258 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 259 #else 260 return CSR_READ_4(sc, reg); 261 #endif 262 } 263 264 static inline u_int16_t 265 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 266 { 267 #ifdef SK_USEIOSPACE 268 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 269 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 270 #else 271 return CSR_READ_2(sc, reg); 272 #endif 273 } 274 275 static inline u_int8_t 276 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 277 { 278 #ifdef SK_USEIOSPACE 279 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 280 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 281 #else 282 return CSR_READ_1(sc, reg); 283 #endif 284 } 285 286 static inline void 287 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 288 { 289 #ifdef SK_USEIOSPACE 290 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 291 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 292 #else 293 CSR_WRITE_4(sc, reg, x); 294 #endif 295 } 296 297 static inline void 298 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 299 { 300 #ifdef SK_USEIOSPACE 301 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 302 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 303 #else 304 CSR_WRITE_2(sc, reg, x); 305 #endif 306 } 307 308 static inline void 309 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 310 { 311 #ifdef SK_USEIOSPACE 312 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 313 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 314 #else 315 CSR_WRITE_1(sc, reg, x); 316 #endif 317 } 318 319 /* 320 * The VPD EEPROM contains Vital Product Data, as suggested in 321 * the PCI 2.1 specification. The VPD data is separared into areas 322 * denoted by resource IDs. The SysKonnect VPD contains an ID string 323 * resource (the name of the adapter), a read-only area resource 324 * containing various key/data fields and a read/write area which 325 * can be used to store asset management information or log messages. 326 * We read the ID string and read-only into buffers attached to 327 * the controller softc structure for later use. At the moment, 328 * we only use the ID string during sk_attach(). 329 */ 330 u_int8_t 331 sk_vpd_readbyte(struct sk_softc *sc, int addr) 332 { 333 int i; 334 335 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 336 for (i = 0; i < SK_TIMEOUT; i++) { 337 DELAY(1); 338 if (sk_win_read_2(sc, 339 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 340 break; 341 } 342 343 if (i == SK_TIMEOUT) 344 return 0; 345 346 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 347 } 348 349 void 350 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 351 { 352 int i; 353 u_int8_t *ptr; 354 355 ptr = (u_int8_t *)res; 356 for (i = 0; i < sizeof(struct vpd_res); i++) 357 ptr[i] = sk_vpd_readbyte(sc, i + addr); 358 } 359 360 void 361 sk_vpd_read(struct sk_softc *sc) 362 { 363 int pos = 0, i; 364 struct vpd_res res; 365 366 if (sc->sk_vpd_prodname != NULL) 367 free(sc->sk_vpd_prodname, M_DEVBUF); 368 if (sc->sk_vpd_readonly != NULL) 369 free(sc->sk_vpd_readonly, M_DEVBUF); 370 sc->sk_vpd_prodname = NULL; 371 sc->sk_vpd_readonly = NULL; 372 373 sk_vpd_read_res(sc, &res, pos); 374 375 if (res.vr_id != VPD_RES_ID) { 376 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 377 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 378 return; 379 } 380 381 pos += sizeof(res); 382 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 383 if (sc->sk_vpd_prodname == NULL) 384 panic("sk_vpd_read"); 385 for (i = 0; i < res.vr_len; i++) 386 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 387 sc->sk_vpd_prodname[i] = '\0'; 388 pos += i; 389 390 sk_vpd_read_res(sc, &res, pos); 391 392 if (res.vr_id != VPD_RES_READ) { 393 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 394 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 395 return; 396 } 397 398 pos += sizeof(res); 399 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 400 if (sc->sk_vpd_readonly == NULL) 401 panic("sk_vpd_read"); 402 for (i = 0; i < res.vr_len ; i++) 403 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 404 } 405 406 int 407 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 408 { 409 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 410 int i; 411 412 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 413 414 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 415 return 0; 416 417 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 418 SK_XM_READ_2(sc_if, XM_PHY_DATA); 419 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 420 for (i = 0; i < SK_TIMEOUT; i++) { 421 DELAY(1); 422 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 423 XM_MMUCMD_PHYDATARDY) 424 break; 425 } 426 427 if (i == SK_TIMEOUT) { 428 aprint_error("%s: phy failed to come ready\n", 429 sc_if->sk_dev.dv_xname); 430 return 0; 431 } 432 } 433 DELAY(1); 434 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 435 } 436 437 void 438 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 439 { 440 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 441 int i; 442 443 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 444 445 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 446 for (i = 0; i < SK_TIMEOUT; i++) { 447 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 448 break; 449 } 450 451 if (i == SK_TIMEOUT) { 452 aprint_error("%s: phy failed to come ready\n", 453 sc_if->sk_dev.dv_xname); 454 return; 455 } 456 457 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 458 for (i = 0; i < SK_TIMEOUT; i++) { 459 DELAY(1); 460 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 461 break; 462 } 463 464 if (i == SK_TIMEOUT) 465 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 466 } 467 468 void 469 sk_xmac_miibus_statchg(struct device *dev) 470 { 471 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 472 struct mii_data *mii = &sc_if->sk_mii; 473 474 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 475 476 /* 477 * If this is a GMII PHY, manually set the XMAC's 478 * duplex mode accordingly. 479 */ 480 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 481 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 482 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 483 else 484 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 485 } 486 } 487 488 int 489 sk_marv_miibus_readreg(struct device *dev, int phy, int reg) 490 { 491 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 492 u_int16_t val; 493 int i; 494 495 if (phy != 0 || 496 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 497 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 498 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 499 phy, reg)); 500 return 0; 501 } 502 503 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 504 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 505 506 for (i = 0; i < SK_TIMEOUT; i++) { 507 DELAY(1); 508 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 509 if (val & YU_SMICR_READ_VALID) 510 break; 511 } 512 513 if (i == SK_TIMEOUT) { 514 aprint_error("%s: phy failed to come ready\n", 515 sc_if->sk_dev.dv_xname); 516 return 0; 517 } 518 519 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 520 SK_TIMEOUT)); 521 522 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 523 524 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 525 phy, reg, val)); 526 527 return val; 528 } 529 530 void 531 sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 532 { 533 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 534 int i; 535 536 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 537 phy, reg, val)); 538 539 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 540 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 541 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 542 543 for (i = 0; i < SK_TIMEOUT; i++) { 544 DELAY(1); 545 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 546 break; 547 } 548 549 if (i == SK_TIMEOUT) 550 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 551 } 552 553 void 554 sk_marv_miibus_statchg(struct device *dev) 555 { 556 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 557 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 558 } 559 560 #define SK_HASH_BITS 6 561 562 u_int32_t 563 sk_xmac_hash(void *addr) 564 { 565 u_int32_t crc; 566 567 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 568 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 569 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 570 return crc; 571 } 572 573 u_int32_t 574 sk_yukon_hash(void *addr) 575 { 576 u_int32_t crc; 577 578 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 579 crc &= ((1 << SK_HASH_BITS) - 1); 580 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 581 return crc; 582 } 583 584 void 585 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 586 { 587 char *addr = addrv; 588 int base = XM_RXFILT_ENTRY(slot); 589 590 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 591 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 592 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 593 } 594 595 void 596 sk_setmulti(struct sk_if_softc *sc_if) 597 { 598 struct sk_softc *sc = sc_if->sk_softc; 599 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 600 u_int32_t hashes[2] = { 0, 0 }; 601 int h = 0, i; 602 struct ethercom *ec = &sc_if->sk_ethercom; 603 struct ether_multi *enm; 604 struct ether_multistep step; 605 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 606 607 /* First, zot all the existing filters. */ 608 switch (sc->sk_type) { 609 case SK_GENESIS: 610 for (i = 1; i < XM_RXFILT_MAX; i++) 611 sk_setfilt(sc_if, (void *)&dummy, i); 612 613 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 614 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 615 break; 616 case SK_YUKON: 617 case SK_YUKON_LITE: 618 case SK_YUKON_LP: 619 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 620 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 621 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 622 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 623 break; 624 } 625 626 /* Now program new ones. */ 627 allmulti: 628 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 629 hashes[0] = 0xFFFFFFFF; 630 hashes[1] = 0xFFFFFFFF; 631 } else { 632 i = 1; 633 /* First find the tail of the list. */ 634 ETHER_FIRST_MULTI(step, ec, enm); 635 while (enm != NULL) { 636 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 637 ETHER_ADDR_LEN)) { 638 ifp->if_flags |= IFF_ALLMULTI; 639 goto allmulti; 640 } 641 DPRINTFN(2,("multicast address %s\n", 642 ether_sprintf(enm->enm_addrlo))); 643 /* 644 * Program the first XM_RXFILT_MAX multicast groups 645 * into the perfect filter. For all others, 646 * use the hash table. 647 */ 648 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 649 sk_setfilt(sc_if, enm->enm_addrlo, i); 650 i++; 651 } 652 else { 653 switch (sc->sk_type) { 654 case SK_GENESIS: 655 h = sk_xmac_hash(enm->enm_addrlo); 656 break; 657 case SK_YUKON: 658 case SK_YUKON_LITE: 659 case SK_YUKON_LP: 660 h = sk_yukon_hash(enm->enm_addrlo); 661 break; 662 } 663 if (h < 32) 664 hashes[0] |= (1 << h); 665 else 666 hashes[1] |= (1 << (h - 32)); 667 } 668 669 ETHER_NEXT_MULTI(step, enm); 670 } 671 } 672 673 switch (sc->sk_type) { 674 case SK_GENESIS: 675 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 676 XM_MODE_RX_USE_PERFECT); 677 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 678 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 679 break; 680 case SK_YUKON: 681 case SK_YUKON_LITE: 682 case SK_YUKON_LP: 683 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 684 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 685 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 686 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 687 break; 688 } 689 } 690 691 int 692 sk_init_rx_ring(struct sk_if_softc *sc_if) 693 { 694 struct sk_chain_data *cd = &sc_if->sk_cdata; 695 struct sk_ring_data *rd = sc_if->sk_rdata; 696 int i; 697 698 bzero((char *)rd->sk_rx_ring, 699 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 700 701 for (i = 0; i < SK_RX_RING_CNT; i++) { 702 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 703 if (i == (SK_RX_RING_CNT - 1)) { 704 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 705 rd->sk_rx_ring[i].sk_next = 706 htole32(SK_RX_RING_ADDR(sc_if, 0)); 707 } else { 708 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 709 rd->sk_rx_ring[i].sk_next = 710 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 711 } 712 } 713 714 for (i = 0; i < SK_RX_RING_CNT; i++) { 715 if (sk_newbuf(sc_if, i, NULL, 716 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 717 aprint_error("%s: failed alloc of %dth mbuf\n", 718 sc_if->sk_dev.dv_xname, i); 719 return ENOBUFS; 720 } 721 } 722 sc_if->sk_cdata.sk_rx_prod = 0; 723 sc_if->sk_cdata.sk_rx_cons = 0; 724 725 return 0; 726 } 727 728 int 729 sk_init_tx_ring(struct sk_if_softc *sc_if) 730 { 731 struct sk_chain_data *cd = &sc_if->sk_cdata; 732 struct sk_ring_data *rd = sc_if->sk_rdata; 733 int i; 734 735 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 736 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 737 738 for (i = 0; i < SK_TX_RING_CNT; i++) { 739 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 740 if (i == (SK_TX_RING_CNT - 1)) { 741 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 742 rd->sk_tx_ring[i].sk_next = 743 htole32(SK_TX_RING_ADDR(sc_if, 0)); 744 } else { 745 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 746 rd->sk_tx_ring[i].sk_next = 747 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 748 } 749 } 750 751 sc_if->sk_cdata.sk_tx_prod = 0; 752 sc_if->sk_cdata.sk_tx_cons = 0; 753 sc_if->sk_cdata.sk_tx_cnt = 0; 754 755 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 756 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 757 758 return 0; 759 } 760 761 int 762 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 763 bus_dmamap_t dmamap) 764 { 765 struct mbuf *m_new = NULL; 766 struct sk_chain *c; 767 struct sk_rx_desc *r; 768 769 if (m == NULL) { 770 void *buf = NULL; 771 772 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 773 if (m_new == NULL) { 774 aprint_error("%s: no memory for rx list -- " 775 "packet dropped!\n", sc_if->sk_dev.dv_xname); 776 return ENOBUFS; 777 } 778 779 /* Allocate the jumbo buffer */ 780 buf = sk_jalloc(sc_if); 781 if (buf == NULL) { 782 m_freem(m_new); 783 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 784 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 785 return ENOBUFS; 786 } 787 788 /* Attach the buffer to the mbuf */ 789 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 790 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 791 792 } else { 793 /* 794 * We're re-using a previously allocated mbuf; 795 * be sure to re-init pointers and lengths to 796 * default values. 797 */ 798 m_new = m; 799 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 800 m_new->m_data = m_new->m_ext.ext_buf; 801 } 802 m_adj(m_new, ETHER_ALIGN); 803 804 c = &sc_if->sk_cdata.sk_rx_chain[i]; 805 r = c->sk_desc; 806 c->sk_mbuf = m_new; 807 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 808 (((vaddr_t)m_new->m_data 809 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 810 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 811 812 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 813 814 return 0; 815 } 816 817 /* 818 * Memory management for jumbo frames. 819 */ 820 821 int 822 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 823 { 824 struct sk_softc *sc = sc_if->sk_softc; 825 char *ptr, *kva; 826 bus_dma_segment_t seg; 827 int i, rseg, state, error; 828 struct sk_jpool_entry *entry; 829 830 state = error = 0; 831 832 /* Grab a big chunk o' storage. */ 833 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 834 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 835 aprint_error("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 836 return ENOBUFS; 837 } 838 839 state = 1; 840 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 841 BUS_DMA_NOWAIT)) { 842 aprint_error("%s: can't map dma buffers (%d bytes)\n", 843 sc->sk_dev.dv_xname, SK_JMEM); 844 error = ENOBUFS; 845 goto out; 846 } 847 848 state = 2; 849 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 850 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 851 aprint_error("%s: can't create dma map\n", sc->sk_dev.dv_xname); 852 error = ENOBUFS; 853 goto out; 854 } 855 856 state = 3; 857 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 858 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 859 aprint_error("%s: can't load dma map\n", sc->sk_dev.dv_xname); 860 error = ENOBUFS; 861 goto out; 862 } 863 864 state = 4; 865 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 866 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 867 868 LIST_INIT(&sc_if->sk_jfree_listhead); 869 LIST_INIT(&sc_if->sk_jinuse_listhead); 870 871 /* 872 * Now divide it up into 9K pieces and save the addresses 873 * in an array. 874 */ 875 ptr = sc_if->sk_cdata.sk_jumbo_buf; 876 for (i = 0; i < SK_JSLOTS; i++) { 877 sc_if->sk_cdata.sk_jslots[i] = ptr; 878 ptr += SK_JLEN; 879 entry = malloc(sizeof(struct sk_jpool_entry), 880 M_DEVBUF, M_NOWAIT); 881 if (entry == NULL) { 882 aprint_error("%s: no memory for jumbo buffer queue!\n", 883 sc->sk_dev.dv_xname); 884 error = ENOBUFS; 885 goto out; 886 } 887 entry->slot = i; 888 if (i) 889 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 890 entry, jpool_entries); 891 else 892 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 893 entry, jpool_entries); 894 } 895 out: 896 if (error != 0) { 897 switch (state) { 898 case 4: 899 bus_dmamap_unload(sc->sc_dmatag, 900 sc_if->sk_cdata.sk_rx_jumbo_map); 901 case 3: 902 bus_dmamap_destroy(sc->sc_dmatag, 903 sc_if->sk_cdata.sk_rx_jumbo_map); 904 case 2: 905 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 906 case 1: 907 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 908 break; 909 default: 910 break; 911 } 912 } 913 914 return error; 915 } 916 917 /* 918 * Allocate a jumbo buffer. 919 */ 920 void * 921 sk_jalloc(struct sk_if_softc *sc_if) 922 { 923 struct sk_jpool_entry *entry; 924 925 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 926 927 if (entry == NULL) 928 return NULL; 929 930 LIST_REMOVE(entry, jpool_entries); 931 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 932 return sc_if->sk_cdata.sk_jslots[entry->slot]; 933 } 934 935 /* 936 * Release a jumbo buffer. 937 */ 938 void 939 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 940 { 941 struct sk_jpool_entry *entry; 942 struct sk_if_softc *sc; 943 int i, s; 944 945 /* Extract the softc struct pointer. */ 946 sc = (struct sk_if_softc *)arg; 947 948 if (sc == NULL) 949 panic("sk_jfree: can't find softc pointer!"); 950 951 /* calculate the slot this buffer belongs to */ 952 953 i = ((vaddr_t)buf 954 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 955 956 if ((i < 0) || (i >= SK_JSLOTS)) 957 panic("sk_jfree: asked to free buffer that we don't manage!"); 958 959 s = splvm(); 960 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 961 if (entry == NULL) 962 panic("sk_jfree: buffer not in use!"); 963 entry->slot = i; 964 LIST_REMOVE(entry, jpool_entries); 965 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 966 967 if (__predict_true(m != NULL)) 968 pool_cache_put(&mbpool_cache, m); 969 splx(s); 970 } 971 972 /* 973 * Set media options. 974 */ 975 int 976 sk_ifmedia_upd(struct ifnet *ifp) 977 { 978 struct sk_if_softc *sc_if = ifp->if_softc; 979 980 (void) sk_init(ifp); 981 mii_mediachg(&sc_if->sk_mii); 982 return 0; 983 } 984 985 /* 986 * Report current media status. 987 */ 988 void 989 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 990 { 991 struct sk_if_softc *sc_if = ifp->if_softc; 992 993 mii_pollstat(&sc_if->sk_mii); 994 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 995 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 996 } 997 998 int 999 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 1000 { 1001 struct sk_if_softc *sc_if = ifp->if_softc; 1002 struct sk_softc *sc = sc_if->sk_softc; 1003 struct ifreq *ifr = (struct ifreq *) data; 1004 struct mii_data *mii; 1005 int s, error = 0; 1006 1007 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1008 1009 s = splnet(); 1010 1011 switch (command) { 1012 1013 case SIOCSIFFLAGS: 1014 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1015 if (ifp->if_flags & IFF_UP) { 1016 if (ifp->if_flags & IFF_RUNNING && 1017 ifp->if_flags & IFF_PROMISC && 1018 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1019 switch (sc->sk_type) { 1020 case SK_GENESIS: 1021 SK_XM_SETBIT_4(sc_if, XM_MODE, 1022 XM_MODE_RX_PROMISC); 1023 break; 1024 case SK_YUKON: 1025 case SK_YUKON_LITE: 1026 case SK_YUKON_LP: 1027 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1028 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1029 break; 1030 } 1031 sk_setmulti(sc_if); 1032 } else if (ifp->if_flags & IFF_RUNNING && 1033 !(ifp->if_flags & IFF_PROMISC) && 1034 sc_if->sk_if_flags & IFF_PROMISC) { 1035 switch (sc->sk_type) { 1036 case SK_GENESIS: 1037 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1038 XM_MODE_RX_PROMISC); 1039 break; 1040 case SK_YUKON: 1041 case SK_YUKON_LITE: 1042 case SK_YUKON_LP: 1043 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1044 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1045 break; 1046 } 1047 1048 sk_setmulti(sc_if); 1049 } else 1050 (void) sk_init(ifp); 1051 } else { 1052 if (ifp->if_flags & IFF_RUNNING) 1053 sk_stop(ifp,0); 1054 } 1055 sc_if->sk_if_flags = ifp->if_flags; 1056 error = 0; 1057 break; 1058 1059 case SIOCGIFMEDIA: 1060 case SIOCSIFMEDIA: 1061 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 1062 mii = &sc_if->sk_mii; 1063 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1064 break; 1065 default: 1066 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1067 error = ether_ioctl(ifp, command, data); 1068 1069 if ( error == ENETRESET) { 1070 if (ifp->if_flags & IFF_RUNNING) { 1071 sk_setmulti(sc_if); 1072 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1073 } 1074 error = 0; 1075 } else if ( error ) { 1076 splx(s); 1077 return error; 1078 } 1079 break; 1080 } 1081 1082 splx(s); 1083 return error; 1084 } 1085 1086 void 1087 sk_update_int_mod(struct sk_softc *sc) 1088 { 1089 u_int32_t imtimer_ticks; 1090 1091 /* 1092 * Configure interrupt moderation. The moderation timer 1093 * defers interrupts specified in the interrupt moderation 1094 * timer mask based on the timeout specified in the interrupt 1095 * moderation timer init register. Each bit in the timer 1096 * register represents one tick, so to specify a timeout in 1097 * microseconds, we have to multiply by the correct number of 1098 * ticks-per-microsecond. 1099 */ 1100 switch (sc->sk_type) { 1101 case SK_GENESIS: 1102 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1103 break; 1104 case SK_YUKON_EC: 1105 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1106 break; 1107 default: 1108 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1109 } 1110 aprint_verbose("%s: interrupt moderation is %d us\n", 1111 sc->sk_dev.dv_xname, sc->sk_int_mod); 1112 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1113 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1114 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1115 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1116 sc->sk_int_mod_pending = 0; 1117 } 1118 1119 /* 1120 * Lookup: Check the PCI vendor and device, and return a pointer to 1121 * The structure if the IDs match against our list. 1122 */ 1123 1124 static const struct sk_product * 1125 sk_lookup(const struct pci_attach_args *pa) 1126 { 1127 const struct sk_product *psk; 1128 1129 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1130 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1131 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1132 return psk; 1133 } 1134 return NULL; 1135 } 1136 1137 /* 1138 * Probe for a SysKonnect GEnesis chip. 1139 */ 1140 1141 int 1142 skc_probe(struct device *parent, struct cfdata *match, 1143 void *aux) 1144 { 1145 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1146 const struct sk_product *psk; 1147 pcireg_t subid; 1148 1149 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1150 1151 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1152 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1153 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1154 subid == SK_LINKSYS_EG1032_SUBID) 1155 return 1; 1156 1157 if ((psk = sk_lookup(pa))) { 1158 return 1; 1159 } 1160 return 0; 1161 } 1162 1163 /* 1164 * Force the GEnesis into reset, then bring it out of reset. 1165 */ 1166 void sk_reset(struct sk_softc *sc) 1167 { 1168 DPRINTFN(2, ("sk_reset\n")); 1169 1170 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1171 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1172 if (SK_YUKON_FAMILY(sc->sk_type)) 1173 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1174 1175 DELAY(1000); 1176 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1177 DELAY(2); 1178 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1179 if (SK_YUKON_FAMILY(sc->sk_type)) 1180 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1181 1182 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1183 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1184 CSR_READ_2(sc, SK_LINK_CTRL))); 1185 1186 if (sc->sk_type == SK_GENESIS) { 1187 /* Configure packet arbiter */ 1188 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1189 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1190 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1191 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1192 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1193 } 1194 1195 /* Enable RAM interface */ 1196 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1197 1198 sk_update_int_mod(sc); 1199 } 1200 1201 int 1202 sk_probe(struct device *parent, struct cfdata *match, 1203 void *aux) 1204 { 1205 struct skc_attach_args *sa = aux; 1206 1207 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1208 return 0; 1209 1210 return 1; 1211 } 1212 1213 /* 1214 * Each XMAC chip is attached as a separate logical IP interface. 1215 * Single port cards will have only one logical interface of course. 1216 */ 1217 void 1218 sk_attach(struct device *parent, struct device *self, void *aux) 1219 { 1220 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1221 struct sk_softc *sc = (struct sk_softc *)parent; 1222 struct skc_attach_args *sa = aux; 1223 struct sk_txmap_entry *entry; 1224 struct ifnet *ifp; 1225 bus_dma_segment_t seg; 1226 bus_dmamap_t dmamap; 1227 void *kva; 1228 int i, rseg; 1229 1230 sc_if->sk_port = sa->skc_port; 1231 sc_if->sk_softc = sc; 1232 sc->sk_if[sa->skc_port] = sc_if; 1233 1234 if (sa->skc_port == SK_PORT_A) 1235 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1236 if (sa->skc_port == SK_PORT_B) 1237 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1238 1239 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1240 1241 /* 1242 * Get station address for this interface. Note that 1243 * dual port cards actually come with three station 1244 * addresses: one for each port, plus an extra. The 1245 * extra one is used by the SysKonnect driver software 1246 * as a 'virtual' station address for when both ports 1247 * are operating in failover mode. Currently we don't 1248 * use this extra address. 1249 */ 1250 for (i = 0; i < ETHER_ADDR_LEN; i++) 1251 sc_if->sk_enaddr[i] = 1252 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1253 1254 1255 aprint_normal(": Ethernet address %s\n", 1256 ether_sprintf(sc_if->sk_enaddr)); 1257 1258 /* 1259 * Set up RAM buffer addresses. The NIC will have a certain 1260 * amount of SRAM on it, somewhere between 512K and 2MB. We 1261 * need to divide this up a) between the transmitter and 1262 * receiver and b) between the two XMACs, if this is a 1263 * dual port NIC. Our algorithm is to divide up the memory 1264 * evenly so that everyone gets a fair share. 1265 */ 1266 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1267 u_int32_t chunk, val; 1268 1269 chunk = sc->sk_ramsize / 2; 1270 val = sc->sk_rboff / sizeof(u_int64_t); 1271 sc_if->sk_rx_ramstart = val; 1272 val += (chunk / sizeof(u_int64_t)); 1273 sc_if->sk_rx_ramend = val - 1; 1274 sc_if->sk_tx_ramstart = val; 1275 val += (chunk / sizeof(u_int64_t)); 1276 sc_if->sk_tx_ramend = val - 1; 1277 } else { 1278 u_int32_t chunk, val; 1279 1280 chunk = sc->sk_ramsize / 4; 1281 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1282 sizeof(u_int64_t); 1283 sc_if->sk_rx_ramstart = val; 1284 val += (chunk / sizeof(u_int64_t)); 1285 sc_if->sk_rx_ramend = val - 1; 1286 sc_if->sk_tx_ramstart = val; 1287 val += (chunk / sizeof(u_int64_t)); 1288 sc_if->sk_tx_ramend = val - 1; 1289 } 1290 1291 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1292 " tx_ramstart=%#x tx_ramend=%#x\n", 1293 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1294 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1295 1296 /* Read and save PHY type and set PHY address */ 1297 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1298 switch (sc_if->sk_phytype) { 1299 case SK_PHYTYPE_XMAC: 1300 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1301 break; 1302 case SK_PHYTYPE_BCOM: 1303 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1304 break; 1305 case SK_PHYTYPE_MARV_COPPER: 1306 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1307 break; 1308 default: 1309 aprint_error("%s: unsupported PHY type: %d\n", 1310 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1311 return; 1312 } 1313 1314 /* Allocate the descriptor queues. */ 1315 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1316 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1317 aprint_error("%s: can't alloc rx buffers\n", 1318 sc->sk_dev.dv_xname); 1319 goto fail; 1320 } 1321 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1322 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1323 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1324 sc_if->sk_dev.dv_xname, 1325 (u_long) sizeof(struct sk_ring_data)); 1326 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1327 goto fail; 1328 } 1329 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1330 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1331 &sc_if->sk_ring_map)) { 1332 aprint_error("%s: can't create dma map\n", 1333 sc_if->sk_dev.dv_xname); 1334 bus_dmamem_unmap(sc->sc_dmatag, kva, 1335 sizeof(struct sk_ring_data)); 1336 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1337 goto fail; 1338 } 1339 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1340 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1341 aprint_error("%s: can't load dma map\n", 1342 sc_if->sk_dev.dv_xname); 1343 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1344 bus_dmamem_unmap(sc->sc_dmatag, kva, 1345 sizeof(struct sk_ring_data)); 1346 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1347 goto fail; 1348 } 1349 1350 for (i = 0; i < SK_RX_RING_CNT; i++) 1351 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1352 1353 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1354 for (i = 0; i < SK_TX_RING_CNT; i++) { 1355 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1356 1357 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1358 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1359 aprint_error("%s: Can't create TX dmamap\n", 1360 sc_if->sk_dev.dv_xname); 1361 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1362 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1363 bus_dmamem_unmap(sc->sc_dmatag, kva, 1364 sizeof(struct sk_ring_data)); 1365 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1366 goto fail; 1367 } 1368 1369 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1370 if (!entry) { 1371 aprint_error("%s: Can't alloc txmap entry\n", 1372 sc_if->sk_dev.dv_xname); 1373 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1374 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1375 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1376 bus_dmamem_unmap(sc->sc_dmatag, kva, 1377 sizeof(struct sk_ring_data)); 1378 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1379 goto fail; 1380 } 1381 entry->dmamap = dmamap; 1382 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1383 } 1384 1385 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1386 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1387 1388 ifp = &sc_if->sk_ethercom.ec_if; 1389 /* Try to allocate memory for jumbo buffers. */ 1390 if (sk_alloc_jumbo_mem(sc_if)) { 1391 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1392 goto fail; 1393 } 1394 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1395 | ETHERCAP_JUMBO_MTU; 1396 1397 ifp->if_softc = sc_if; 1398 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1399 ifp->if_ioctl = sk_ioctl; 1400 ifp->if_start = sk_start; 1401 ifp->if_stop = sk_stop; 1402 ifp->if_init = sk_init; 1403 ifp->if_watchdog = sk_watchdog; 1404 ifp->if_capabilities = 0; 1405 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1406 IFQ_SET_READY(&ifp->if_snd); 1407 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1408 1409 /* 1410 * Do miibus setup. 1411 */ 1412 switch (sc->sk_type) { 1413 case SK_GENESIS: 1414 sk_init_xmac(sc_if); 1415 break; 1416 case SK_YUKON: 1417 case SK_YUKON_LITE: 1418 case SK_YUKON_LP: 1419 sk_init_yukon(sc_if); 1420 break; 1421 default: 1422 aprint_error("%s: unknown device type %d\n", 1423 sc->sk_dev.dv_xname, sc->sk_type); 1424 goto fail; 1425 } 1426 1427 DPRINTFN(2, ("sk_attach: 1\n")); 1428 1429 sc_if->sk_mii.mii_ifp = ifp; 1430 switch (sc->sk_type) { 1431 case SK_GENESIS: 1432 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1433 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1434 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1435 break; 1436 case SK_YUKON: 1437 case SK_YUKON_LITE: 1438 case SK_YUKON_LP: 1439 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1440 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1441 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1442 break; 1443 } 1444 1445 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1446 sk_ifmedia_upd, sk_ifmedia_sts); 1447 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1448 MII_OFFSET_ANY, 0); 1449 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1450 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1451 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1452 0, NULL); 1453 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1454 } else 1455 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1456 1457 callout_init(&sc_if->sk_tick_ch); 1458 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1459 1460 DPRINTFN(2, ("sk_attach: 1\n")); 1461 1462 /* 1463 * Call MI attach routines. 1464 */ 1465 if_attach(ifp); 1466 1467 ether_ifattach(ifp, sc_if->sk_enaddr); 1468 1469 #if NRND > 0 1470 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1471 RND_TYPE_NET, 0); 1472 #endif 1473 1474 DPRINTFN(2, ("sk_attach: end\n")); 1475 1476 return; 1477 1478 fail: 1479 sc->sk_if[sa->skc_port] = NULL; 1480 } 1481 1482 int 1483 skcprint(void *aux, const char *pnp) 1484 { 1485 struct skc_attach_args *sa = aux; 1486 1487 if (pnp) 1488 aprint_normal("sk port %c at %s", 1489 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1490 else 1491 aprint_normal(" port %c", 1492 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1493 return UNCONF; 1494 } 1495 1496 /* 1497 * Attach the interface. Allocate softc structures, do ifmedia 1498 * setup and ethernet/BPF attach. 1499 */ 1500 void 1501 skc_attach(struct device *parent, struct device *self, void *aux) 1502 { 1503 struct sk_softc *sc = (struct sk_softc *)self; 1504 struct pci_attach_args *pa = aux; 1505 struct skc_attach_args skca; 1506 pci_chipset_tag_t pc = pa->pa_pc; 1507 #ifndef SK_USEIOSPACE 1508 pcireg_t memtype; 1509 #endif 1510 pci_intr_handle_t ih; 1511 const char *intrstr = NULL; 1512 bus_addr_t iobase; 1513 bus_size_t iosize; 1514 int rc, sk_nodenum; 1515 u_int32_t command; 1516 const char *revstr; 1517 const struct sysctlnode *node; 1518 1519 DPRINTFN(2, ("begin skc_attach\n")); 1520 1521 /* 1522 * Handle power management nonsense. 1523 */ 1524 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1525 1526 if (command == 0x01) { 1527 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1528 if (command & SK_PSTATE_MASK) { 1529 u_int32_t xiobase, membase, irq; 1530 1531 /* Save important PCI config data. */ 1532 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1533 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1534 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1535 1536 /* Reset the power state. */ 1537 aprint_normal("%s chip is in D%d power mode " 1538 "-- setting to D0\n", sc->sk_dev.dv_xname, 1539 command & SK_PSTATE_MASK); 1540 command &= 0xFFFFFFFC; 1541 pci_conf_write(pc, pa->pa_tag, 1542 SK_PCI_PWRMGMTCTRL, command); 1543 1544 /* Restore PCI config data. */ 1545 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1546 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1547 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1548 } 1549 } 1550 1551 /* 1552 * Map control/status registers. 1553 */ 1554 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1555 command |= PCI_COMMAND_IO_ENABLE | 1556 PCI_COMMAND_MEM_ENABLE | 1557 PCI_COMMAND_MASTER_ENABLE; 1558 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1559 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1560 1561 #ifdef SK_USEIOSPACE 1562 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1563 aprint_error(": failed to enable I/O ports!\n"); 1564 return; 1565 } 1566 /* 1567 * Map control/status registers. 1568 */ 1569 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1570 &sc->sk_btag, &sc->sk_bhandle, 1571 &iobase, &iosize)) { 1572 aprint_error(": can't find i/o space\n"); 1573 return; 1574 } 1575 #else 1576 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1577 aprint_error(": failed to enable memory mapping!\n"); 1578 return; 1579 } 1580 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1581 switch (memtype) { 1582 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1583 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1584 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1585 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1586 &iobase, &iosize) == 0) 1587 break; 1588 default: 1589 aprint_error("%s: can't find mem space\n", 1590 sc->sk_dev.dv_xname); 1591 return; 1592 } 1593 1594 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1595 #endif 1596 sc->sc_dmatag = pa->pa_dmat; 1597 1598 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1599 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1600 1601 /* bail out here if chip is not recognized */ 1602 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1603 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1604 goto fail; 1605 } 1606 if (SK_IS_YUKON2(sc)) { 1607 aprint_error("%s: Does not support Yukon2--try msk(4).\n", 1608 sc->sk_dev.dv_xname); 1609 goto fail; 1610 } 1611 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1612 1613 /* Allocate interrupt */ 1614 if (pci_intr_map(pa, &ih)) { 1615 aprint_error(": couldn't map interrupt\n"); 1616 goto fail; 1617 } 1618 1619 intrstr = pci_intr_string(pc, ih); 1620 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1621 if (sc->sk_intrhand == NULL) { 1622 aprint_error(": couldn't establish interrupt"); 1623 if (intrstr != NULL) 1624 aprint_normal(" at %s", intrstr); 1625 goto fail; 1626 } 1627 aprint_normal(": %s\n", intrstr); 1628 1629 /* Reset the adapter. */ 1630 sk_reset(sc); 1631 1632 /* Read and save vital product data from EEPROM. */ 1633 sk_vpd_read(sc); 1634 1635 if (sc->sk_type == SK_GENESIS) { 1636 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1637 /* Read and save RAM size and RAMbuffer offset */ 1638 switch (val) { 1639 case SK_RAMSIZE_512K_64: 1640 sc->sk_ramsize = 0x80000; 1641 sc->sk_rboff = SK_RBOFF_0; 1642 break; 1643 case SK_RAMSIZE_1024K_64: 1644 sc->sk_ramsize = 0x100000; 1645 sc->sk_rboff = SK_RBOFF_80000; 1646 break; 1647 case SK_RAMSIZE_1024K_128: 1648 sc->sk_ramsize = 0x100000; 1649 sc->sk_rboff = SK_RBOFF_0; 1650 break; 1651 case SK_RAMSIZE_2048K_128: 1652 sc->sk_ramsize = 0x200000; 1653 sc->sk_rboff = SK_RBOFF_0; 1654 break; 1655 default: 1656 aprint_error("%s: unknown ram size: %d\n", 1657 sc->sk_dev.dv_xname, val); 1658 goto fail_1; 1659 break; 1660 } 1661 1662 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1663 sc->sk_ramsize, sc->sk_ramsize / 1024, 1664 sc->sk_rboff)); 1665 } else { 1666 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1667 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1668 sc->sk_rboff = SK_RBOFF_0; 1669 1670 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1671 sc->sk_ramsize / 1024, sc->sk_ramsize, 1672 sc->sk_rboff)); 1673 } 1674 1675 /* Read and save physical media type */ 1676 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1677 case SK_PMD_1000BASESX: 1678 sc->sk_pmd = IFM_1000_SX; 1679 break; 1680 case SK_PMD_1000BASELX: 1681 sc->sk_pmd = IFM_1000_LX; 1682 break; 1683 case SK_PMD_1000BASECX: 1684 sc->sk_pmd = IFM_1000_CX; 1685 break; 1686 case SK_PMD_1000BASETX: 1687 case SK_PMD_1000BASETX_ALT: 1688 sc->sk_pmd = IFM_1000_T; 1689 break; 1690 default: 1691 aprint_error("%s: unknown media type: 0x%x\n", 1692 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1693 goto fail_1; 1694 } 1695 1696 /* determine whether to name it with vpd or just make it up */ 1697 /* Marvell Yukon VPD's can freqently be bogus */ 1698 1699 switch (pa->pa_id) { 1700 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1701 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1702 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1703 case PCI_PRODUCT_3COM_3C940: 1704 case PCI_PRODUCT_DLINK_DGE530T: 1705 case PCI_PRODUCT_DLINK_DGE560T: 1706 case PCI_PRODUCT_DLINK_DGE560T_2: 1707 case PCI_PRODUCT_LINKSYS_EG1032: 1708 case PCI_PRODUCT_LINKSYS_EG1064: 1709 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1710 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1711 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1712 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1713 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1714 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1715 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1716 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1717 sc->sk_name = sc->sk_vpd_prodname; 1718 break; 1719 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1720 /* whoops yukon vpd prodname bears no resemblance to reality */ 1721 switch (sc->sk_type) { 1722 case SK_GENESIS: 1723 sc->sk_name = sc->sk_vpd_prodname; 1724 break; 1725 case SK_YUKON: 1726 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1727 break; 1728 case SK_YUKON_LITE: 1729 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1730 break; 1731 case SK_YUKON_LP: 1732 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1733 break; 1734 default: 1735 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1736 } 1737 1738 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1739 1740 if ( sc->sk_type == SK_YUKON ) { 1741 uint32_t flashaddr; 1742 uint8_t testbyte; 1743 1744 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1745 1746 /* test Flash-Address Register */ 1747 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1748 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1749 1750 if (testbyte != 0) { 1751 /* this is yukon lite Rev. A0 */ 1752 sc->sk_type = SK_YUKON_LITE; 1753 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1754 /* restore Flash-Address Register */ 1755 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1756 } 1757 } 1758 break; 1759 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1760 sc->sk_name = sc->sk_vpd_prodname; 1761 break; 1762 default: 1763 sc->sk_name = "Unknown Marvell"; 1764 } 1765 1766 1767 if ( sc->sk_type == SK_YUKON_LITE ) { 1768 switch (sc->sk_rev) { 1769 case SK_YUKON_LITE_REV_A0: 1770 revstr = "A0"; 1771 break; 1772 case SK_YUKON_LITE_REV_A1: 1773 revstr = "A1"; 1774 break; 1775 case SK_YUKON_LITE_REV_A3: 1776 revstr = "A3"; 1777 break; 1778 default: 1779 revstr = ""; 1780 } 1781 } else { 1782 revstr = ""; 1783 } 1784 1785 /* Announce the product name. */ 1786 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1787 sc->sk_name, revstr, sc->sk_rev); 1788 1789 skca.skc_port = SK_PORT_A; 1790 (void)config_found(&sc->sk_dev, &skca, skcprint); 1791 1792 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1793 skca.skc_port = SK_PORT_B; 1794 (void)config_found(&sc->sk_dev, &skca, skcprint); 1795 } 1796 1797 /* Turn on the 'driver is loaded' LED. */ 1798 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1799 1800 /* skc sysctl setup */ 1801 1802 sc->sk_int_mod = SK_IM_DEFAULT; 1803 sc->sk_int_mod_pending = 0; 1804 1805 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1806 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1807 SYSCTL_DESCR("skc per-controller controls"), 1808 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1809 CTL_EOL)) != 0) { 1810 aprint_normal("%s: couldn't create sysctl node\n", 1811 sc->sk_dev.dv_xname); 1812 goto fail_1; 1813 } 1814 1815 sk_nodenum = node->sysctl_num; 1816 1817 /* interrupt moderation time in usecs */ 1818 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1819 CTLFLAG_READWRITE, 1820 CTLTYPE_INT, "int_mod", 1821 SYSCTL_DESCR("sk interrupt moderation timer"), 1822 sk_sysctl_handler, 0, sc, 1823 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1824 CTL_EOL)) != 0) { 1825 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1826 sc->sk_dev.dv_xname); 1827 goto fail_1; 1828 } 1829 1830 return; 1831 1832 fail_1: 1833 pci_intr_disestablish(pc, sc->sk_intrhand); 1834 fail: 1835 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1836 } 1837 1838 int 1839 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1840 { 1841 struct sk_softc *sc = sc_if->sk_softc; 1842 struct sk_tx_desc *f = NULL; 1843 u_int32_t frag, cur, cnt = 0, sk_ctl; 1844 int i; 1845 struct sk_txmap_entry *entry; 1846 bus_dmamap_t txmap; 1847 1848 DPRINTFN(3, ("sk_encap\n")); 1849 1850 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1851 if (entry == NULL) { 1852 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1853 return ENOBUFS; 1854 } 1855 txmap = entry->dmamap; 1856 1857 cur = frag = *txidx; 1858 1859 #ifdef SK_DEBUG 1860 if (skdebug >= 3) 1861 sk_dump_mbuf(m_head); 1862 #endif 1863 1864 /* 1865 * Start packing the mbufs in this chain into 1866 * the fragment pointers. Stop when we run out 1867 * of fragments or hit the end of the mbuf chain. 1868 */ 1869 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1870 BUS_DMA_NOWAIT)) { 1871 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1872 return ENOBUFS; 1873 } 1874 1875 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1876 1877 /* Sync the DMA map. */ 1878 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1879 BUS_DMASYNC_PREWRITE); 1880 1881 for (i = 0; i < txmap->dm_nsegs; i++) { 1882 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1883 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1884 return ENOBUFS; 1885 } 1886 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1887 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1888 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1889 if (cnt == 0) 1890 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1891 else 1892 sk_ctl |= SK_TXCTL_OWN; 1893 f->sk_ctl = htole32(sk_ctl); 1894 cur = frag; 1895 SK_INC(frag, SK_TX_RING_CNT); 1896 cnt++; 1897 } 1898 1899 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1900 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1901 1902 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1903 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1904 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1905 1906 /* Sync descriptors before handing to chip */ 1907 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1908 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1909 1910 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1911 htole32(SK_TXCTL_OWN); 1912 1913 /* Sync first descriptor to hand it off */ 1914 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1915 1916 sc_if->sk_cdata.sk_tx_cnt += cnt; 1917 1918 #ifdef SK_DEBUG 1919 if (skdebug >= 3) { 1920 struct sk_tx_desc *desc; 1921 u_int32_t idx; 1922 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1923 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1924 sk_dump_txdesc(desc, idx); 1925 } 1926 } 1927 #endif 1928 1929 *txidx = frag; 1930 1931 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1932 1933 return 0; 1934 } 1935 1936 void 1937 sk_start(struct ifnet *ifp) 1938 { 1939 struct sk_if_softc *sc_if = ifp->if_softc; 1940 struct sk_softc *sc = sc_if->sk_softc; 1941 struct mbuf *m_head = NULL; 1942 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1943 int pkts = 0; 1944 1945 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1946 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1947 1948 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1949 IFQ_POLL(&ifp->if_snd, m_head); 1950 if (m_head == NULL) 1951 break; 1952 1953 /* 1954 * Pack the data into the transmit ring. If we 1955 * don't have room, set the OACTIVE flag and wait 1956 * for the NIC to drain the ring. 1957 */ 1958 if (sk_encap(sc_if, m_head, &idx)) { 1959 ifp->if_flags |= IFF_OACTIVE; 1960 break; 1961 } 1962 1963 /* now we are committed to transmit the packet */ 1964 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1965 pkts++; 1966 1967 /* 1968 * If there's a BPF listener, bounce a copy of this frame 1969 * to him. 1970 */ 1971 #if NBPFILTER > 0 1972 if (ifp->if_bpf) 1973 bpf_mtap(ifp->if_bpf, m_head); 1974 #endif 1975 } 1976 if (pkts == 0) 1977 return; 1978 1979 /* Transmit */ 1980 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1981 sc_if->sk_cdata.sk_tx_prod = idx; 1982 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1983 1984 /* Set a timeout in case the chip goes out to lunch. */ 1985 ifp->if_timer = 5; 1986 } 1987 } 1988 1989 1990 void 1991 sk_watchdog(struct ifnet *ifp) 1992 { 1993 struct sk_if_softc *sc_if = ifp->if_softc; 1994 1995 /* 1996 * Reclaim first as there is a possibility of losing Tx completion 1997 * interrupts. 1998 */ 1999 sk_txeof(sc_if); 2000 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2001 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 2002 2003 ifp->if_oerrors++; 2004 2005 sk_init(ifp); 2006 } 2007 } 2008 2009 void 2010 sk_shutdown(void *v) 2011 { 2012 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2013 struct sk_softc *sc = sc_if->sk_softc; 2014 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2015 2016 DPRINTFN(2, ("sk_shutdown\n")); 2017 sk_stop(ifp,1); 2018 2019 /* Turn off the 'driver is loaded' LED. */ 2020 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2021 2022 /* 2023 * Reset the GEnesis controller. Doing this should also 2024 * assert the resets on the attached XMAC(s). 2025 */ 2026 sk_reset(sc); 2027 } 2028 2029 void 2030 sk_rxeof(struct sk_if_softc *sc_if) 2031 { 2032 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2033 struct mbuf *m; 2034 struct sk_chain *cur_rx; 2035 struct sk_rx_desc *cur_desc; 2036 int i, cur, total_len = 0; 2037 u_int32_t rxstat, sk_ctl; 2038 bus_dmamap_t dmamap; 2039 2040 i = sc_if->sk_cdata.sk_rx_prod; 2041 2042 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2043 2044 for (;;) { 2045 cur = i; 2046 2047 /* Sync the descriptor */ 2048 SK_CDRXSYNC(sc_if, cur, 2049 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2050 2051 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2052 if (sk_ctl & SK_RXCTL_OWN) { 2053 /* Invalidate the descriptor -- it's not ready yet */ 2054 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2055 sc_if->sk_cdata.sk_rx_prod = i; 2056 break; 2057 } 2058 2059 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2060 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2061 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2062 2063 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2064 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2065 2066 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2067 m = cur_rx->sk_mbuf; 2068 cur_rx->sk_mbuf = NULL; 2069 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2070 2071 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2072 2073 SK_INC(i, SK_RX_RING_CNT); 2074 2075 if (rxstat & XM_RXSTAT_ERRFRAME) { 2076 ifp->if_ierrors++; 2077 sk_newbuf(sc_if, cur, m, dmamap); 2078 continue; 2079 } 2080 2081 /* 2082 * Try to allocate a new jumbo buffer. If that 2083 * fails, copy the packet to mbufs and put the 2084 * jumbo buffer back in the ring so it can be 2085 * re-used. If allocating mbufs fails, then we 2086 * have to drop the packet. 2087 */ 2088 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2089 struct mbuf *m0; 2090 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2091 total_len + ETHER_ALIGN, 0, ifp, NULL); 2092 sk_newbuf(sc_if, cur, m, dmamap); 2093 if (m0 == NULL) { 2094 aprint_error("%s: no receive buffers " 2095 "available -- packet dropped!\n", 2096 sc_if->sk_dev.dv_xname); 2097 ifp->if_ierrors++; 2098 continue; 2099 } 2100 m_adj(m0, ETHER_ALIGN); 2101 m = m0; 2102 } else { 2103 m->m_pkthdr.rcvif = ifp; 2104 m->m_pkthdr.len = m->m_len = total_len; 2105 } 2106 2107 ifp->if_ipackets++; 2108 2109 #if NBPFILTER > 0 2110 if (ifp->if_bpf) 2111 bpf_mtap(ifp->if_bpf, m); 2112 #endif 2113 /* pass it on. */ 2114 (*ifp->if_input)(ifp, m); 2115 } 2116 } 2117 2118 void 2119 sk_txeof(struct sk_if_softc *sc_if) 2120 { 2121 struct sk_softc *sc = sc_if->sk_softc; 2122 struct sk_tx_desc *cur_tx; 2123 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2124 u_int32_t idx, sk_ctl; 2125 struct sk_txmap_entry *entry; 2126 2127 DPRINTFN(3, ("sk_txeof\n")); 2128 2129 /* 2130 * Go through our tx ring and free mbufs for those 2131 * frames that have been sent. 2132 */ 2133 idx = sc_if->sk_cdata.sk_tx_cons; 2134 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2135 SK_CDTXSYNC(sc_if, idx, 1, 2136 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2137 2138 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2139 sk_ctl = le32toh(cur_tx->sk_ctl); 2140 #ifdef SK_DEBUG 2141 if (skdebug >= 3) 2142 sk_dump_txdesc(cur_tx, idx); 2143 #endif 2144 if (sk_ctl & SK_TXCTL_OWN) { 2145 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2146 break; 2147 } 2148 if (sk_ctl & SK_TXCTL_LASTFRAG) 2149 ifp->if_opackets++; 2150 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2151 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2152 2153 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2154 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2155 2156 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2157 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2158 2159 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2160 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2161 link); 2162 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2163 } 2164 sc_if->sk_cdata.sk_tx_cnt--; 2165 SK_INC(idx, SK_TX_RING_CNT); 2166 } 2167 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2168 ifp->if_timer = 0; 2169 else /* nudge chip to keep tx ring moving */ 2170 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2171 2172 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2173 ifp->if_flags &= ~IFF_OACTIVE; 2174 2175 sc_if->sk_cdata.sk_tx_cons = idx; 2176 } 2177 2178 void 2179 sk_tick(void *xsc_if) 2180 { 2181 struct sk_if_softc *sc_if = xsc_if; 2182 struct mii_data *mii = &sc_if->sk_mii; 2183 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2184 int i; 2185 2186 DPRINTFN(3, ("sk_tick\n")); 2187 2188 if (!(ifp->if_flags & IFF_UP)) 2189 return; 2190 2191 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2192 sk_intr_bcom(sc_if); 2193 return; 2194 } 2195 2196 /* 2197 * According to SysKonnect, the correct way to verify that 2198 * the link has come back up is to poll bit 0 of the GPIO 2199 * register three times. This pin has the signal from the 2200 * link sync pin connected to it; if we read the same link 2201 * state 3 times in a row, we know the link is up. 2202 */ 2203 for (i = 0; i < 3; i++) { 2204 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2205 break; 2206 } 2207 2208 if (i != 3) { 2209 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2210 return; 2211 } 2212 2213 /* Turn the GP0 interrupt back on. */ 2214 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2215 SK_XM_READ_2(sc_if, XM_ISR); 2216 mii_tick(mii); 2217 mii_pollstat(mii); 2218 callout_stop(&sc_if->sk_tick_ch); 2219 } 2220 2221 void 2222 sk_intr_bcom(struct sk_if_softc *sc_if) 2223 { 2224 struct mii_data *mii = &sc_if->sk_mii; 2225 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2226 int status; 2227 2228 2229 DPRINTFN(3, ("sk_intr_bcom\n")); 2230 2231 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2232 2233 /* 2234 * Read the PHY interrupt register to make sure 2235 * we clear any pending interrupts. 2236 */ 2237 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2238 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2239 2240 if (!(ifp->if_flags & IFF_RUNNING)) { 2241 sk_init_xmac(sc_if); 2242 return; 2243 } 2244 2245 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2246 int lstat; 2247 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2248 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2249 2250 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2251 mii_mediachg(mii); 2252 /* Turn off the link LED. */ 2253 SK_IF_WRITE_1(sc_if, 0, 2254 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2255 sc_if->sk_link = 0; 2256 } else if (status & BRGPHY_ISR_LNK_CHG) { 2257 sk_xmac_miibus_writereg((struct device *)sc_if, 2258 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2259 mii_tick(mii); 2260 sc_if->sk_link = 1; 2261 /* Turn on the link LED. */ 2262 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2263 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2264 SK_LINKLED_BLINK_OFF); 2265 mii_pollstat(mii); 2266 } else { 2267 mii_tick(mii); 2268 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2269 } 2270 } 2271 2272 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2273 } 2274 2275 void 2276 sk_intr_xmac(struct sk_if_softc *sc_if) 2277 { 2278 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2279 2280 DPRINTFN(3, ("sk_intr_xmac\n")); 2281 2282 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2283 if (status & XM_ISR_GP0_SET) { 2284 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2285 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2286 } 2287 2288 if (status & XM_ISR_AUTONEG_DONE) { 2289 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2290 } 2291 } 2292 2293 if (status & XM_IMR_TX_UNDERRUN) 2294 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2295 2296 if (status & XM_IMR_RX_OVERRUN) 2297 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2298 } 2299 2300 void 2301 sk_intr_yukon(struct sk_if_softc *sc_if) 2302 { 2303 int status; 2304 2305 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2306 2307 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2308 } 2309 2310 int 2311 sk_intr(void *xsc) 2312 { 2313 struct sk_softc *sc = xsc; 2314 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2315 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2316 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2317 u_int32_t status; 2318 int claimed = 0; 2319 2320 if (sc_if0 != NULL) 2321 ifp0 = &sc_if0->sk_ethercom.ec_if; 2322 if (sc_if1 != NULL) 2323 ifp1 = &sc_if1->sk_ethercom.ec_if; 2324 2325 for (;;) { 2326 status = CSR_READ_4(sc, SK_ISSR); 2327 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2328 2329 if (!(status & sc->sk_intrmask)) 2330 break; 2331 2332 claimed = 1; 2333 2334 /* Handle receive interrupts first. */ 2335 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2336 sk_rxeof(sc_if0); 2337 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2338 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2339 } 2340 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2341 sk_rxeof(sc_if1); 2342 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2343 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2344 } 2345 2346 /* Then transmit interrupts. */ 2347 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2348 sk_txeof(sc_if0); 2349 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2350 SK_TXBMU_CLR_IRQ_EOF); 2351 } 2352 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2353 sk_txeof(sc_if1); 2354 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2355 SK_TXBMU_CLR_IRQ_EOF); 2356 } 2357 2358 /* Then MAC interrupts. */ 2359 if (sc_if0 && (status & SK_ISR_MAC1) && 2360 (ifp0->if_flags & IFF_RUNNING)) { 2361 if (sc->sk_type == SK_GENESIS) 2362 sk_intr_xmac(sc_if0); 2363 else 2364 sk_intr_yukon(sc_if0); 2365 } 2366 2367 if (sc_if1 && (status & SK_ISR_MAC2) && 2368 (ifp1->if_flags & IFF_RUNNING)) { 2369 if (sc->sk_type == SK_GENESIS) 2370 sk_intr_xmac(sc_if1); 2371 else 2372 sk_intr_yukon(sc_if1); 2373 2374 } 2375 2376 if (status & SK_ISR_EXTERNAL_REG) { 2377 if (sc_if0 != NULL && 2378 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2379 sk_intr_bcom(sc_if0); 2380 2381 if (sc_if1 != NULL && 2382 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2383 sk_intr_bcom(sc_if1); 2384 } 2385 } 2386 2387 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2388 2389 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2390 sk_start(ifp0); 2391 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2392 sk_start(ifp1); 2393 2394 #if NRND > 0 2395 if (RND_ENABLED(&sc->rnd_source)) 2396 rnd_add_uint32(&sc->rnd_source, status); 2397 #endif 2398 2399 if (sc->sk_int_mod_pending) 2400 sk_update_int_mod(sc); 2401 2402 return claimed; 2403 } 2404 2405 void 2406 sk_init_xmac(struct sk_if_softc *sc_if) 2407 { 2408 struct sk_softc *sc = sc_if->sk_softc; 2409 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2410 static const struct sk_bcom_hack bhack[] = { 2411 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2412 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2413 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2414 { 0, 0 } }; 2415 2416 DPRINTFN(1, ("sk_init_xmac\n")); 2417 2418 /* Unreset the XMAC. */ 2419 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2420 DELAY(1000); 2421 2422 /* Reset the XMAC's internal state. */ 2423 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2424 2425 /* Save the XMAC II revision */ 2426 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2427 2428 /* 2429 * Perform additional initialization for external PHYs, 2430 * namely for the 1000baseTX cards that use the XMAC's 2431 * GMII mode. 2432 */ 2433 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2434 int i = 0; 2435 u_int32_t val; 2436 2437 /* Take PHY out of reset. */ 2438 val = sk_win_read_4(sc, SK_GPIO); 2439 if (sc_if->sk_port == SK_PORT_A) 2440 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2441 else 2442 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2443 sk_win_write_4(sc, SK_GPIO, val); 2444 2445 /* Enable GMII mode on the XMAC. */ 2446 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2447 2448 sk_xmac_miibus_writereg((struct device *)sc_if, 2449 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2450 DELAY(10000); 2451 sk_xmac_miibus_writereg((struct device *)sc_if, 2452 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2453 2454 /* 2455 * Early versions of the BCM5400 apparently have 2456 * a bug that requires them to have their reserved 2457 * registers initialized to some magic values. I don't 2458 * know what the numbers do, I'm just the messenger. 2459 */ 2460 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2461 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2462 while (bhack[i].reg) { 2463 sk_xmac_miibus_writereg((struct device *)sc_if, 2464 SK_PHYADDR_BCOM, bhack[i].reg, 2465 bhack[i].val); 2466 i++; 2467 } 2468 } 2469 } 2470 2471 /* Set station address */ 2472 SK_XM_WRITE_2(sc_if, XM_PAR0, 2473 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2474 SK_XM_WRITE_2(sc_if, XM_PAR1, 2475 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2476 SK_XM_WRITE_2(sc_if, XM_PAR2, 2477 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2478 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2479 2480 if (ifp->if_flags & IFF_PROMISC) 2481 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2482 else 2483 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2484 2485 if (ifp->if_flags & IFF_BROADCAST) 2486 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2487 else 2488 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2489 2490 /* We don't need the FCS appended to the packet. */ 2491 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2492 2493 /* We want short frames padded to 60 bytes. */ 2494 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2495 2496 /* 2497 * Enable the reception of all error frames. This is is 2498 * a necessary evil due to the design of the XMAC. The 2499 * XMAC's receive FIFO is only 8K in size, however jumbo 2500 * frames can be up to 9000 bytes in length. When bad 2501 * frame filtering is enabled, the XMAC's RX FIFO operates 2502 * in 'store and forward' mode. For this to work, the 2503 * entire frame has to fit into the FIFO, but that means 2504 * that jumbo frames larger than 8192 bytes will be 2505 * truncated. Disabling all bad frame filtering causes 2506 * the RX FIFO to operate in streaming mode, in which 2507 * case the XMAC will start transfering frames out of the 2508 * RX FIFO as soon as the FIFO threshold is reached. 2509 */ 2510 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2511 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2512 XM_MODE_RX_INRANGELEN); 2513 2514 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2515 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2516 else 2517 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2518 2519 /* 2520 * Bump up the transmit threshold. This helps hold off transmit 2521 * underruns when we're blasting traffic from both ports at once. 2522 */ 2523 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2524 2525 /* Set multicast filter */ 2526 sk_setmulti(sc_if); 2527 2528 /* Clear and enable interrupts */ 2529 SK_XM_READ_2(sc_if, XM_ISR); 2530 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2531 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2532 else 2533 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2534 2535 /* Configure MAC arbiter */ 2536 switch (sc_if->sk_xmac_rev) { 2537 case XM_XMAC_REV_B2: 2538 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2539 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2540 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2541 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2542 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2543 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2544 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2545 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2546 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2547 break; 2548 case XM_XMAC_REV_C1: 2549 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2550 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2551 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2552 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2553 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2554 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2555 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2556 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2557 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2558 break; 2559 default: 2560 break; 2561 } 2562 sk_win_write_2(sc, SK_MACARB_CTL, 2563 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2564 2565 sc_if->sk_link = 1; 2566 } 2567 2568 void sk_init_yukon(struct sk_if_softc *sc_if) 2569 { 2570 u_int32_t /*mac, */phy; 2571 u_int16_t reg; 2572 struct sk_softc *sc; 2573 int i; 2574 2575 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2576 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2577 2578 sc = sc_if->sk_softc; 2579 if (sc->sk_type == SK_YUKON_LITE && 2580 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2581 /* Take PHY out of reset. */ 2582 sk_win_write_4(sc, SK_GPIO, 2583 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2584 } 2585 2586 2587 /* GMAC and GPHY Reset */ 2588 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2589 2590 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2591 2592 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2593 DELAY(1000); 2594 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2595 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2596 DELAY(1000); 2597 2598 2599 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2600 2601 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2602 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2603 2604 switch (sc_if->sk_softc->sk_pmd) { 2605 case IFM_1000_SX: 2606 case IFM_1000_LX: 2607 phy |= SK_GPHY_FIBER; 2608 break; 2609 2610 case IFM_1000_CX: 2611 case IFM_1000_T: 2612 phy |= SK_GPHY_COPPER; 2613 break; 2614 } 2615 2616 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2617 2618 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2619 DELAY(1000); 2620 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2621 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2622 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2623 2624 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2625 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2626 2627 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2628 2629 /* unused read of the interrupt source register */ 2630 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2631 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2632 2633 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2634 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2635 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2636 2637 /* MIB Counter Clear Mode set */ 2638 reg |= YU_PAR_MIB_CLR; 2639 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2640 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2641 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2642 2643 /* MIB Counter Clear Mode clear */ 2644 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2645 reg &= ~YU_PAR_MIB_CLR; 2646 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2647 2648 /* receive control reg */ 2649 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2650 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2651 YU_RCR_CRCR); 2652 2653 /* transmit parameter register */ 2654 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2655 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2656 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2657 2658 /* serial mode register */ 2659 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2660 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2661 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2662 YU_SMR_IPG_DATA(0x1e)); 2663 2664 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2665 /* Setup Yukon's address */ 2666 for (i = 0; i < 3; i++) { 2667 /* Write Source Address 1 (unicast filter) */ 2668 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2669 sc_if->sk_enaddr[i * 2] | 2670 sc_if->sk_enaddr[i * 2 + 1] << 8); 2671 } 2672 2673 for (i = 0; i < 3; i++) { 2674 reg = sk_win_read_2(sc_if->sk_softc, 2675 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2676 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2677 } 2678 2679 /* Set multicast filter */ 2680 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2681 sk_setmulti(sc_if); 2682 2683 /* enable interrupt mask for counter overflows */ 2684 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2685 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2686 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2687 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2688 2689 /* Configure RX MAC FIFO */ 2690 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2691 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2692 2693 /* Configure TX MAC FIFO */ 2694 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2695 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2696 2697 DPRINTFN(6, ("sk_init_yukon: end\n")); 2698 } 2699 2700 /* 2701 * Note that to properly initialize any part of the GEnesis chip, 2702 * you first have to take it out of reset mode. 2703 */ 2704 int 2705 sk_init(struct ifnet *ifp) 2706 { 2707 struct sk_if_softc *sc_if = ifp->if_softc; 2708 struct sk_softc *sc = sc_if->sk_softc; 2709 struct mii_data *mii = &sc_if->sk_mii; 2710 int s; 2711 u_int32_t imr, imtimer_ticks; 2712 2713 DPRINTFN(1, ("sk_init\n")); 2714 2715 s = splnet(); 2716 2717 if (ifp->if_flags & IFF_RUNNING) { 2718 splx(s); 2719 return 0; 2720 } 2721 2722 /* Cancel pending I/O and free all RX/TX buffers. */ 2723 sk_stop(ifp,0); 2724 2725 if (sc->sk_type == SK_GENESIS) { 2726 /* Configure LINK_SYNC LED */ 2727 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2728 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2729 SK_LINKLED_LINKSYNC_ON); 2730 2731 /* Configure RX LED */ 2732 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2733 SK_RXLEDCTL_COUNTER_START); 2734 2735 /* Configure TX LED */ 2736 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2737 SK_TXLEDCTL_COUNTER_START); 2738 } 2739 2740 /* Configure I2C registers */ 2741 2742 /* Configure XMAC(s) */ 2743 switch (sc->sk_type) { 2744 case SK_GENESIS: 2745 sk_init_xmac(sc_if); 2746 break; 2747 case SK_YUKON: 2748 case SK_YUKON_LITE: 2749 case SK_YUKON_LP: 2750 sk_init_yukon(sc_if); 2751 break; 2752 } 2753 mii_mediachg(mii); 2754 2755 if (sc->sk_type == SK_GENESIS) { 2756 /* Configure MAC FIFOs */ 2757 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2758 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2759 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2760 2761 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2762 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2763 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2764 } 2765 2766 /* Configure transmit arbiter(s) */ 2767 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2768 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2769 2770 /* Configure RAMbuffers */ 2771 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2772 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2773 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2774 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2775 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2776 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2777 2778 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2779 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2780 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2781 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2782 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2783 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2784 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2785 2786 /* Configure BMUs */ 2787 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2788 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2789 SK_RX_RING_ADDR(sc_if, 0)); 2790 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2791 2792 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2793 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2794 SK_TX_RING_ADDR(sc_if, 0)); 2795 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2796 2797 /* Init descriptors */ 2798 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2799 aprint_error("%s: initialization failed: no " 2800 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2801 sk_stop(ifp,0); 2802 splx(s); 2803 return ENOBUFS; 2804 } 2805 2806 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2807 aprint_error("%s: initialization failed: no " 2808 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2809 sk_stop(ifp,0); 2810 splx(s); 2811 return ENOBUFS; 2812 } 2813 2814 /* Set interrupt moderation if changed via sysctl. */ 2815 switch (sc->sk_type) { 2816 case SK_GENESIS: 2817 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2818 break; 2819 case SK_YUKON_EC: 2820 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2821 break; 2822 default: 2823 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2824 } 2825 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2826 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2827 sk_win_write_4(sc, SK_IMTIMERINIT, 2828 SK_IM_USECS(sc->sk_int_mod)); 2829 aprint_verbose("%s: interrupt moderation is %d us\n", 2830 sc->sk_dev.dv_xname, sc->sk_int_mod); 2831 } 2832 2833 /* Configure interrupt handling */ 2834 CSR_READ_4(sc, SK_ISSR); 2835 if (sc_if->sk_port == SK_PORT_A) 2836 sc->sk_intrmask |= SK_INTRS1; 2837 else 2838 sc->sk_intrmask |= SK_INTRS2; 2839 2840 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2841 2842 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2843 2844 /* Start BMUs. */ 2845 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2846 2847 if (sc->sk_type == SK_GENESIS) { 2848 /* Enable XMACs TX and RX state machines */ 2849 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2850 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2851 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2852 } 2853 2854 if (SK_YUKON_FAMILY(sc->sk_type)) { 2855 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2856 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2857 #if 0 2858 /* XXX disable 100Mbps and full duplex mode? */ 2859 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2860 #endif 2861 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2862 } 2863 2864 2865 ifp->if_flags |= IFF_RUNNING; 2866 ifp->if_flags &= ~IFF_OACTIVE; 2867 2868 splx(s); 2869 return 0; 2870 } 2871 2872 void 2873 sk_stop(struct ifnet *ifp, int disable) 2874 { 2875 struct sk_if_softc *sc_if = ifp->if_softc; 2876 struct sk_softc *sc = sc_if->sk_softc; 2877 int i; 2878 2879 DPRINTFN(1, ("sk_stop\n")); 2880 2881 callout_stop(&sc_if->sk_tick_ch); 2882 2883 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2884 u_int32_t val; 2885 2886 /* Put PHY back into reset. */ 2887 val = sk_win_read_4(sc, SK_GPIO); 2888 if (sc_if->sk_port == SK_PORT_A) { 2889 val |= SK_GPIO_DIR0; 2890 val &= ~SK_GPIO_DAT0; 2891 } else { 2892 val |= SK_GPIO_DIR2; 2893 val &= ~SK_GPIO_DAT2; 2894 } 2895 sk_win_write_4(sc, SK_GPIO, val); 2896 } 2897 2898 /* Turn off various components of this interface. */ 2899 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2900 switch (sc->sk_type) { 2901 case SK_GENESIS: 2902 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2903 SK_TXMACCTL_XMAC_RESET); 2904 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2905 break; 2906 case SK_YUKON: 2907 case SK_YUKON_LITE: 2908 case SK_YUKON_LP: 2909 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2910 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2911 break; 2912 } 2913 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2914 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2915 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2916 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2917 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2918 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2919 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2920 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2921 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2922 2923 /* Disable interrupts */ 2924 if (sc_if->sk_port == SK_PORT_A) 2925 sc->sk_intrmask &= ~SK_INTRS1; 2926 else 2927 sc->sk_intrmask &= ~SK_INTRS2; 2928 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2929 2930 SK_XM_READ_2(sc_if, XM_ISR); 2931 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2932 2933 /* Free RX and TX mbufs still in the queues. */ 2934 for (i = 0; i < SK_RX_RING_CNT; i++) { 2935 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2936 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2937 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2938 } 2939 } 2940 2941 for (i = 0; i < SK_TX_RING_CNT; i++) { 2942 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2943 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2944 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2945 } 2946 } 2947 2948 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2949 } 2950 2951 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2952 2953 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2954 2955 #ifdef SK_DEBUG 2956 void 2957 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2958 { 2959 #define DESC_PRINT(X) \ 2960 if (X) \ 2961 printf("txdesc[%d]." #X "=%#x\n", \ 2962 idx, X); 2963 2964 DESC_PRINT(le32toh(desc->sk_ctl)); 2965 DESC_PRINT(le32toh(desc->sk_next)); 2966 DESC_PRINT(le32toh(desc->sk_data_lo)); 2967 DESC_PRINT(le32toh(desc->sk_data_hi)); 2968 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2969 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2970 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2971 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2972 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2973 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2974 #undef PRINT 2975 } 2976 2977 void 2978 sk_dump_bytes(const char *data, int len) 2979 { 2980 int c, i, j; 2981 2982 for (i = 0; i < len; i += 16) { 2983 printf("%08x ", i); 2984 c = len - i; 2985 if (c > 16) c = 16; 2986 2987 for (j = 0; j < c; j++) { 2988 printf("%02x ", data[i + j] & 0xff); 2989 if ((j & 0xf) == 7 && j > 0) 2990 printf(" "); 2991 } 2992 2993 for (; j < 16; j++) 2994 printf(" "); 2995 printf(" "); 2996 2997 for (j = 0; j < c; j++) { 2998 int ch = data[i + j] & 0xff; 2999 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3000 } 3001 3002 printf("\n"); 3003 3004 if (c < 16) 3005 break; 3006 } 3007 } 3008 3009 void 3010 sk_dump_mbuf(struct mbuf *m) 3011 { 3012 int count = m->m_pkthdr.len; 3013 3014 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3015 3016 while (count > 0 && m) { 3017 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3018 m, m->m_data, m->m_len); 3019 sk_dump_bytes(mtod(m, char *), m->m_len); 3020 3021 count -= m->m_len; 3022 m = m->m_next; 3023 } 3024 } 3025 #endif 3026 3027 static int 3028 sk_sysctl_handler(SYSCTLFN_ARGS) 3029 { 3030 int error, t; 3031 struct sysctlnode node; 3032 struct sk_softc *sc; 3033 3034 node = *rnode; 3035 sc = node.sysctl_data; 3036 t = sc->sk_int_mod; 3037 node.sysctl_data = &t; 3038 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3039 if (error || newp == NULL) 3040 return error; 3041 3042 if (t < SK_IM_MIN || t > SK_IM_MAX) 3043 return EINVAL; 3044 3045 /* update the softc with sysctl-changed value, and mark 3046 for hardware update */ 3047 sc->sk_int_mod = t; 3048 sc->sk_int_mod_pending = 1; 3049 return 0; 3050 } 3051 3052 /* 3053 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3054 * set up in skc_attach() 3055 */ 3056 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3057 { 3058 int rc; 3059 const struct sysctlnode *node; 3060 3061 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3062 0, CTLTYPE_NODE, "hw", NULL, 3063 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3064 goto err; 3065 } 3066 3067 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3068 0, CTLTYPE_NODE, "sk", 3069 SYSCTL_DESCR("sk interface controls"), 3070 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3071 goto err; 3072 } 3073 3074 sk_root_num = node->sysctl_num; 3075 return; 3076 3077 err: 3078 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3079 } 3080
Indexes created Tue Sep 23 07:09:52 GMT 2025