if_sk.c revision 1.44
1 /* $NetBSD: if_sk.c,v 1.44 2007/12/01 23:40:28 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include <sys/cdefs.h> 125 126 #include "bpfilter.h" 127 #include "rnd.h" 128 129 #include <sys/param.h> 130 #include <sys/systm.h> 131 #include <sys/sockio.h> 132 #include <sys/mbuf.h> 133 #include <sys/malloc.h> 134 #include <sys/kernel.h> 135 #include <sys/socket.h> 136 #include <sys/device.h> 137 #include <sys/queue.h> 138 #include <sys/callout.h> 139 #include <sys/sysctl.h> 140 #include <sys/endian.h> 141 142 #include <net/if.h> 143 #include <net/if_dl.h> 144 #include <net/if_types.h> 145 146 #include <net/if_media.h> 147 148 #if NBPFILTER > 0 149 #include <net/bpf.h> 150 #endif 151 #if NRND > 0 152 #include <sys/rnd.h> 153 #endif 154 155 #include <dev/mii/mii.h> 156 #include <dev/mii/miivar.h> 157 #include <dev/mii/brgphyreg.h> 158 159 #include <dev/pci/pcireg.h> 160 #include <dev/pci/pcivar.h> 161 #include <dev/pci/pcidevs.h> 162 163 /* #define SK_USEIOSPACE */ 164 165 #include <dev/pci/if_skreg.h> 166 #include <dev/pci/if_skvar.h> 167 168 int skc_probe(struct device *, struct cfdata *, void *); 169 void skc_attach(struct device *, struct device *self, void *aux); 170 int sk_probe(struct device *, struct cfdata *, void *); 171 void sk_attach(struct device *, struct device *self, void *aux); 172 int skcprint(void *, const char *); 173 int sk_intr(void *); 174 void sk_intr_bcom(struct sk_if_softc *); 175 void sk_intr_xmac(struct sk_if_softc *); 176 void sk_intr_yukon(struct sk_if_softc *); 177 void sk_rxeof(struct sk_if_softc *); 178 void sk_txeof(struct sk_if_softc *); 179 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 180 void sk_start(struct ifnet *); 181 int sk_ioctl(struct ifnet *, u_long, void *); 182 int sk_init(struct ifnet *); 183 void sk_init_xmac(struct sk_if_softc *); 184 void sk_init_yukon(struct sk_if_softc *); 185 void sk_stop(struct ifnet *, int); 186 void sk_watchdog(struct ifnet *); 187 void sk_shutdown(void *); 188 int sk_ifmedia_upd(struct ifnet *); 189 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 190 void sk_reset(struct sk_softc *); 191 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 192 int sk_alloc_jumbo_mem(struct sk_if_softc *); 193 void sk_free_jumbo_mem(struct sk_if_softc *); 194 void *sk_jalloc(struct sk_if_softc *); 195 void sk_jfree(struct mbuf *, void *, size_t, void *); 196 int sk_init_rx_ring(struct sk_if_softc *); 197 int sk_init_tx_ring(struct sk_if_softc *); 198 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 199 void sk_vpd_read_res(struct sk_softc *, 200 struct vpd_res *, int); 201 void sk_vpd_read(struct sk_softc *); 202 203 void sk_update_int_mod(struct sk_softc *); 204 205 int sk_xmac_miibus_readreg(struct device *, int, int); 206 void sk_xmac_miibus_writereg(struct device *, int, int, int); 207 void sk_xmac_miibus_statchg(struct device *); 208 209 int sk_marv_miibus_readreg(struct device *, int, int); 210 void sk_marv_miibus_writereg(struct device *, int, int, int); 211 void sk_marv_miibus_statchg(struct device *); 212 213 u_int32_t sk_xmac_hash(void *); 214 u_int32_t sk_yukon_hash(void *); 215 void sk_setfilt(struct sk_if_softc *, void *, int); 216 void sk_setmulti(struct sk_if_softc *); 217 void sk_tick(void *); 218 219 /* #define SK_DEBUG 2 */ 220 #ifdef SK_DEBUG 221 #define DPRINTF(x) if (skdebug) printf x 222 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 223 int skdebug = SK_DEBUG; 224 225 void sk_dump_txdesc(struct sk_tx_desc *, int); 226 void sk_dump_mbuf(struct mbuf *); 227 void sk_dump_bytes(const char *, int); 228 #else 229 #define DPRINTF(x) 230 #define DPRINTFN(n,x) 231 #endif 232 233 static int sk_sysctl_handler(SYSCTLFN_PROTO); 234 static int sk_root_num; 235 236 /* supported device vendors */ 237 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 238 static const struct sk_product { 239 pci_vendor_id_t sk_vendor; 240 pci_product_id_t sk_product; 241 } sk_products[] = { 242 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 243 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 244 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 245 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 246 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 247 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 248 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 249 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 250 { 0, 0, } 251 }; 252 253 #define SK_LINKSYS_EG1032_SUBID 0x00151737 254 255 static inline u_int32_t 256 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 257 { 258 #ifdef SK_USEIOSPACE 259 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 260 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 261 #else 262 return CSR_READ_4(sc, reg); 263 #endif 264 } 265 266 static inline u_int16_t 267 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 268 { 269 #ifdef SK_USEIOSPACE 270 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 271 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 272 #else 273 return CSR_READ_2(sc, reg); 274 #endif 275 } 276 277 static inline u_int8_t 278 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 279 { 280 #ifdef SK_USEIOSPACE 281 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 282 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 283 #else 284 return CSR_READ_1(sc, reg); 285 #endif 286 } 287 288 static inline void 289 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 290 { 291 #ifdef SK_USEIOSPACE 292 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 293 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 294 #else 295 CSR_WRITE_4(sc, reg, x); 296 #endif 297 } 298 299 static inline void 300 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 301 { 302 #ifdef SK_USEIOSPACE 303 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 304 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 305 #else 306 CSR_WRITE_2(sc, reg, x); 307 #endif 308 } 309 310 static inline void 311 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 312 { 313 #ifdef SK_USEIOSPACE 314 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 315 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 316 #else 317 CSR_WRITE_1(sc, reg, x); 318 #endif 319 } 320 321 /* 322 * The VPD EEPROM contains Vital Product Data, as suggested in 323 * the PCI 2.1 specification. The VPD data is separared into areas 324 * denoted by resource IDs. The SysKonnect VPD contains an ID string 325 * resource (the name of the adapter), a read-only area resource 326 * containing various key/data fields and a read/write area which 327 * can be used to store asset management information or log messages. 328 * We read the ID string and read-only into buffers attached to 329 * the controller softc structure for later use. At the moment, 330 * we only use the ID string during sk_attach(). 331 */ 332 u_int8_t 333 sk_vpd_readbyte(struct sk_softc *sc, int addr) 334 { 335 int i; 336 337 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 338 for (i = 0; i < SK_TIMEOUT; i++) { 339 DELAY(1); 340 if (sk_win_read_2(sc, 341 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 342 break; 343 } 344 345 if (i == SK_TIMEOUT) 346 return 0; 347 348 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 349 } 350 351 void 352 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 353 { 354 int i; 355 u_int8_t *ptr; 356 357 ptr = (u_int8_t *)res; 358 for (i = 0; i < sizeof(struct vpd_res); i++) 359 ptr[i] = sk_vpd_readbyte(sc, i + addr); 360 } 361 362 void 363 sk_vpd_read(struct sk_softc *sc) 364 { 365 int pos = 0, i; 366 struct vpd_res res; 367 368 if (sc->sk_vpd_prodname != NULL) 369 free(sc->sk_vpd_prodname, M_DEVBUF); 370 if (sc->sk_vpd_readonly != NULL) 371 free(sc->sk_vpd_readonly, M_DEVBUF); 372 sc->sk_vpd_prodname = NULL; 373 sc->sk_vpd_readonly = NULL; 374 375 sk_vpd_read_res(sc, &res, pos); 376 377 if (res.vr_id != VPD_RES_ID) { 378 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 379 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 380 return; 381 } 382 383 pos += sizeof(res); 384 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 385 if (sc->sk_vpd_prodname == NULL) 386 panic("sk_vpd_read"); 387 for (i = 0; i < res.vr_len; i++) 388 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 389 sc->sk_vpd_prodname[i] = '\0'; 390 pos += i; 391 392 sk_vpd_read_res(sc, &res, pos); 393 394 if (res.vr_id != VPD_RES_READ) { 395 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 396 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 397 return; 398 } 399 400 pos += sizeof(res); 401 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 402 if (sc->sk_vpd_readonly == NULL) 403 panic("sk_vpd_read"); 404 for (i = 0; i < res.vr_len ; i++) 405 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 406 } 407 408 int 409 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 410 { 411 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 412 int i; 413 414 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 415 416 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 417 return 0; 418 419 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 420 SK_XM_READ_2(sc_if, XM_PHY_DATA); 421 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 422 for (i = 0; i < SK_TIMEOUT; i++) { 423 DELAY(1); 424 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 425 XM_MMUCMD_PHYDATARDY) 426 break; 427 } 428 429 if (i == SK_TIMEOUT) { 430 aprint_error("%s: phy failed to come ready\n", 431 sc_if->sk_dev.dv_xname); 432 return 0; 433 } 434 } 435 DELAY(1); 436 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 437 } 438 439 void 440 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 441 { 442 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 443 int i; 444 445 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 446 447 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 448 for (i = 0; i < SK_TIMEOUT; i++) { 449 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 450 break; 451 } 452 453 if (i == SK_TIMEOUT) { 454 aprint_error("%s: phy failed to come ready\n", 455 sc_if->sk_dev.dv_xname); 456 return; 457 } 458 459 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 460 for (i = 0; i < SK_TIMEOUT; i++) { 461 DELAY(1); 462 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 463 break; 464 } 465 466 if (i == SK_TIMEOUT) 467 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 468 } 469 470 void 471 sk_xmac_miibus_statchg(struct device *dev) 472 { 473 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 474 struct mii_data *mii = &sc_if->sk_mii; 475 476 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 477 478 /* 479 * If this is a GMII PHY, manually set the XMAC's 480 * duplex mode accordingly. 481 */ 482 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 483 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 484 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 485 else 486 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 487 } 488 } 489 490 int 491 sk_marv_miibus_readreg(struct device *dev, int phy, int reg) 492 { 493 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 494 u_int16_t val; 495 int i; 496 497 if (phy != 0 || 498 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 499 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 500 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 501 phy, reg)); 502 return 0; 503 } 504 505 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 506 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 507 508 for (i = 0; i < SK_TIMEOUT; i++) { 509 DELAY(1); 510 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 511 if (val & YU_SMICR_READ_VALID) 512 break; 513 } 514 515 if (i == SK_TIMEOUT) { 516 aprint_error("%s: phy failed to come ready\n", 517 sc_if->sk_dev.dv_xname); 518 return 0; 519 } 520 521 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 522 SK_TIMEOUT)); 523 524 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 525 526 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 527 phy, reg, val)); 528 529 return val; 530 } 531 532 void 533 sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 534 { 535 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 536 int i; 537 538 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 539 phy, reg, val)); 540 541 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 542 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 543 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 544 545 for (i = 0; i < SK_TIMEOUT; i++) { 546 DELAY(1); 547 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 548 break; 549 } 550 551 if (i == SK_TIMEOUT) 552 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 553 } 554 555 void 556 sk_marv_miibus_statchg(struct device *dev) 557 { 558 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 559 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 560 } 561 562 #define SK_HASH_BITS 6 563 564 u_int32_t 565 sk_xmac_hash(void *addr) 566 { 567 u_int32_t crc; 568 569 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 570 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 571 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 572 return crc; 573 } 574 575 u_int32_t 576 sk_yukon_hash(void *addr) 577 { 578 u_int32_t crc; 579 580 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 581 crc &= ((1 << SK_HASH_BITS) - 1); 582 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 583 return crc; 584 } 585 586 void 587 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 588 { 589 char *addr = addrv; 590 int base = XM_RXFILT_ENTRY(slot); 591 592 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 593 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 594 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 595 } 596 597 void 598 sk_setmulti(struct sk_if_softc *sc_if) 599 { 600 struct sk_softc *sc = sc_if->sk_softc; 601 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 602 u_int32_t hashes[2] = { 0, 0 }; 603 int h = 0, i; 604 struct ethercom *ec = &sc_if->sk_ethercom; 605 struct ether_multi *enm; 606 struct ether_multistep step; 607 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 608 609 /* First, zot all the existing filters. */ 610 switch (sc->sk_type) { 611 case SK_GENESIS: 612 for (i = 1; i < XM_RXFILT_MAX; i++) 613 sk_setfilt(sc_if, (void *)&dummy, i); 614 615 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 616 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 617 break; 618 case SK_YUKON: 619 case SK_YUKON_LITE: 620 case SK_YUKON_LP: 621 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 622 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 623 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 624 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 625 break; 626 } 627 628 /* Now program new ones. */ 629 allmulti: 630 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 631 hashes[0] = 0xFFFFFFFF; 632 hashes[1] = 0xFFFFFFFF; 633 } else { 634 i = 1; 635 /* First find the tail of the list. */ 636 ETHER_FIRST_MULTI(step, ec, enm); 637 while (enm != NULL) { 638 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 639 ETHER_ADDR_LEN)) { 640 ifp->if_flags |= IFF_ALLMULTI; 641 goto allmulti; 642 } 643 DPRINTFN(2,("multicast address %s\n", 644 ether_sprintf(enm->enm_addrlo))); 645 /* 646 * Program the first XM_RXFILT_MAX multicast groups 647 * into the perfect filter. For all others, 648 * use the hash table. 649 */ 650 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 651 sk_setfilt(sc_if, enm->enm_addrlo, i); 652 i++; 653 } 654 else { 655 switch (sc->sk_type) { 656 case SK_GENESIS: 657 h = sk_xmac_hash(enm->enm_addrlo); 658 break; 659 case SK_YUKON: 660 case SK_YUKON_LITE: 661 case SK_YUKON_LP: 662 h = sk_yukon_hash(enm->enm_addrlo); 663 break; 664 } 665 if (h < 32) 666 hashes[0] |= (1 << h); 667 else 668 hashes[1] |= (1 << (h - 32)); 669 } 670 671 ETHER_NEXT_MULTI(step, enm); 672 } 673 } 674 675 switch (sc->sk_type) { 676 case SK_GENESIS: 677 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 678 XM_MODE_RX_USE_PERFECT); 679 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 680 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 681 break; 682 case SK_YUKON: 683 case SK_YUKON_LITE: 684 case SK_YUKON_LP: 685 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 686 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 687 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 688 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 689 break; 690 } 691 } 692 693 int 694 sk_init_rx_ring(struct sk_if_softc *sc_if) 695 { 696 struct sk_chain_data *cd = &sc_if->sk_cdata; 697 struct sk_ring_data *rd = sc_if->sk_rdata; 698 int i; 699 700 bzero((char *)rd->sk_rx_ring, 701 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 702 703 for (i = 0; i < SK_RX_RING_CNT; i++) { 704 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 705 if (i == (SK_RX_RING_CNT - 1)) { 706 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 707 rd->sk_rx_ring[i].sk_next = 708 htole32(SK_RX_RING_ADDR(sc_if, 0)); 709 } else { 710 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 711 rd->sk_rx_ring[i].sk_next = 712 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 713 } 714 } 715 716 for (i = 0; i < SK_RX_RING_CNT; i++) { 717 if (sk_newbuf(sc_if, i, NULL, 718 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 719 aprint_error("%s: failed alloc of %dth mbuf\n", 720 sc_if->sk_dev.dv_xname, i); 721 return ENOBUFS; 722 } 723 } 724 sc_if->sk_cdata.sk_rx_prod = 0; 725 sc_if->sk_cdata.sk_rx_cons = 0; 726 727 return 0; 728 } 729 730 int 731 sk_init_tx_ring(struct sk_if_softc *sc_if) 732 { 733 struct sk_chain_data *cd = &sc_if->sk_cdata; 734 struct sk_ring_data *rd = sc_if->sk_rdata; 735 int i; 736 737 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 738 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 739 740 for (i = 0; i < SK_TX_RING_CNT; i++) { 741 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 742 if (i == (SK_TX_RING_CNT - 1)) { 743 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 744 rd->sk_tx_ring[i].sk_next = 745 htole32(SK_TX_RING_ADDR(sc_if, 0)); 746 } else { 747 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 748 rd->sk_tx_ring[i].sk_next = 749 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 750 } 751 } 752 753 sc_if->sk_cdata.sk_tx_prod = 0; 754 sc_if->sk_cdata.sk_tx_cons = 0; 755 sc_if->sk_cdata.sk_tx_cnt = 0; 756 757 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 758 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 759 760 return 0; 761 } 762 763 int 764 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 765 bus_dmamap_t dmamap) 766 { 767 struct mbuf *m_new = NULL; 768 struct sk_chain *c; 769 struct sk_rx_desc *r; 770 771 if (m == NULL) { 772 void *buf = NULL; 773 774 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 775 if (m_new == NULL) { 776 aprint_error("%s: no memory for rx list -- " 777 "packet dropped!\n", sc_if->sk_dev.dv_xname); 778 return ENOBUFS; 779 } 780 781 /* Allocate the jumbo buffer */ 782 buf = sk_jalloc(sc_if); 783 if (buf == NULL) { 784 m_freem(m_new); 785 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 786 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 787 return ENOBUFS; 788 } 789 790 /* Attach the buffer to the mbuf */ 791 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 792 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 793 794 } else { 795 /* 796 * We're re-using a previously allocated mbuf; 797 * be sure to re-init pointers and lengths to 798 * default values. 799 */ 800 m_new = m; 801 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 802 m_new->m_data = m_new->m_ext.ext_buf; 803 } 804 m_adj(m_new, ETHER_ALIGN); 805 806 c = &sc_if->sk_cdata.sk_rx_chain[i]; 807 r = c->sk_desc; 808 c->sk_mbuf = m_new; 809 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 810 (((vaddr_t)m_new->m_data 811 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 812 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 813 814 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 815 816 return 0; 817 } 818 819 /* 820 * Memory management for jumbo frames. 821 */ 822 823 int 824 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 825 { 826 struct sk_softc *sc = sc_if->sk_softc; 827 char *ptr, *kva; 828 bus_dma_segment_t seg; 829 int i, rseg, state, error; 830 struct sk_jpool_entry *entry; 831 832 state = error = 0; 833 834 /* Grab a big chunk o' storage. */ 835 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 836 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 837 aprint_error("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 838 return ENOBUFS; 839 } 840 841 state = 1; 842 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 843 BUS_DMA_NOWAIT)) { 844 aprint_error("%s: can't map dma buffers (%d bytes)\n", 845 sc->sk_dev.dv_xname, SK_JMEM); 846 error = ENOBUFS; 847 goto out; 848 } 849 850 state = 2; 851 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 852 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 853 aprint_error("%s: can't create dma map\n", sc->sk_dev.dv_xname); 854 error = ENOBUFS; 855 goto out; 856 } 857 858 state = 3; 859 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 860 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 861 aprint_error("%s: can't load dma map\n", sc->sk_dev.dv_xname); 862 error = ENOBUFS; 863 goto out; 864 } 865 866 state = 4; 867 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 868 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 869 870 LIST_INIT(&sc_if->sk_jfree_listhead); 871 LIST_INIT(&sc_if->sk_jinuse_listhead); 872 873 /* 874 * Now divide it up into 9K pieces and save the addresses 875 * in an array. 876 */ 877 ptr = sc_if->sk_cdata.sk_jumbo_buf; 878 for (i = 0; i < SK_JSLOTS; i++) { 879 sc_if->sk_cdata.sk_jslots[i] = ptr; 880 ptr += SK_JLEN; 881 entry = malloc(sizeof(struct sk_jpool_entry), 882 M_DEVBUF, M_NOWAIT); 883 if (entry == NULL) { 884 aprint_error("%s: no memory for jumbo buffer queue!\n", 885 sc->sk_dev.dv_xname); 886 error = ENOBUFS; 887 goto out; 888 } 889 entry->slot = i; 890 if (i) 891 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 892 entry, jpool_entries); 893 else 894 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 895 entry, jpool_entries); 896 } 897 out: 898 if (error != 0) { 899 switch (state) { 900 case 4: 901 bus_dmamap_unload(sc->sc_dmatag, 902 sc_if->sk_cdata.sk_rx_jumbo_map); 903 case 3: 904 bus_dmamap_destroy(sc->sc_dmatag, 905 sc_if->sk_cdata.sk_rx_jumbo_map); 906 case 2: 907 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 908 case 1: 909 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 910 break; 911 default: 912 break; 913 } 914 } 915 916 return error; 917 } 918 919 /* 920 * Allocate a jumbo buffer. 921 */ 922 void * 923 sk_jalloc(struct sk_if_softc *sc_if) 924 { 925 struct sk_jpool_entry *entry; 926 927 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 928 929 if (entry == NULL) 930 return NULL; 931 932 LIST_REMOVE(entry, jpool_entries); 933 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 934 return sc_if->sk_cdata.sk_jslots[entry->slot]; 935 } 936 937 /* 938 * Release a jumbo buffer. 939 */ 940 void 941 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 942 { 943 struct sk_jpool_entry *entry; 944 struct sk_if_softc *sc; 945 int i, s; 946 947 /* Extract the softc struct pointer. */ 948 sc = (struct sk_if_softc *)arg; 949 950 if (sc == NULL) 951 panic("sk_jfree: can't find softc pointer!"); 952 953 /* calculate the slot this buffer belongs to */ 954 955 i = ((vaddr_t)buf 956 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 957 958 if ((i < 0) || (i >= SK_JSLOTS)) 959 panic("sk_jfree: asked to free buffer that we don't manage!"); 960 961 s = splvm(); 962 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 963 if (entry == NULL) 964 panic("sk_jfree: buffer not in use!"); 965 entry->slot = i; 966 LIST_REMOVE(entry, jpool_entries); 967 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 968 969 if (__predict_true(m != NULL)) 970 pool_cache_put(mb_cache, m); 971 splx(s); 972 } 973 974 /* 975 * Set media options. 976 */ 977 int 978 sk_ifmedia_upd(struct ifnet *ifp) 979 { 980 struct sk_if_softc *sc_if = ifp->if_softc; 981 982 (void) sk_init(ifp); 983 mii_mediachg(&sc_if->sk_mii); 984 return 0; 985 } 986 987 /* 988 * Report current media status. 989 */ 990 void 991 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 992 { 993 struct sk_if_softc *sc_if = ifp->if_softc; 994 995 mii_pollstat(&sc_if->sk_mii); 996 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 997 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 998 } 999 1000 int 1001 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 1002 { 1003 struct sk_if_softc *sc_if = ifp->if_softc; 1004 struct sk_softc *sc = sc_if->sk_softc; 1005 struct ifreq *ifr = (struct ifreq *) data; 1006 struct mii_data *mii; 1007 int s, error = 0; 1008 1009 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1010 1011 s = splnet(); 1012 1013 switch (command) { 1014 1015 case SIOCSIFFLAGS: 1016 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1017 if (ifp->if_flags & IFF_UP) { 1018 if (ifp->if_flags & IFF_RUNNING && 1019 ifp->if_flags & IFF_PROMISC && 1020 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1021 switch (sc->sk_type) { 1022 case SK_GENESIS: 1023 SK_XM_SETBIT_4(sc_if, XM_MODE, 1024 XM_MODE_RX_PROMISC); 1025 break; 1026 case SK_YUKON: 1027 case SK_YUKON_LITE: 1028 case SK_YUKON_LP: 1029 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1030 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1031 break; 1032 } 1033 sk_setmulti(sc_if); 1034 } else if (ifp->if_flags & IFF_RUNNING && 1035 !(ifp->if_flags & IFF_PROMISC) && 1036 sc_if->sk_if_flags & IFF_PROMISC) { 1037 switch (sc->sk_type) { 1038 case SK_GENESIS: 1039 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1040 XM_MODE_RX_PROMISC); 1041 break; 1042 case SK_YUKON: 1043 case SK_YUKON_LITE: 1044 case SK_YUKON_LP: 1045 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1046 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1047 break; 1048 } 1049 1050 sk_setmulti(sc_if); 1051 } else 1052 (void) sk_init(ifp); 1053 } else { 1054 if (ifp->if_flags & IFF_RUNNING) 1055 sk_stop(ifp,0); 1056 } 1057 sc_if->sk_if_flags = ifp->if_flags; 1058 error = 0; 1059 break; 1060 1061 case SIOCGIFMEDIA: 1062 case SIOCSIFMEDIA: 1063 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 1064 mii = &sc_if->sk_mii; 1065 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1066 break; 1067 default: 1068 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1069 error = ether_ioctl(ifp, command, data); 1070 1071 if ( error == ENETRESET) { 1072 if (ifp->if_flags & IFF_RUNNING) { 1073 sk_setmulti(sc_if); 1074 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1075 } 1076 error = 0; 1077 } else if ( error ) { 1078 splx(s); 1079 return error; 1080 } 1081 break; 1082 } 1083 1084 splx(s); 1085 return error; 1086 } 1087 1088 void 1089 sk_update_int_mod(struct sk_softc *sc) 1090 { 1091 u_int32_t imtimer_ticks; 1092 1093 /* 1094 * Configure interrupt moderation. The moderation timer 1095 * defers interrupts specified in the interrupt moderation 1096 * timer mask based on the timeout specified in the interrupt 1097 * moderation timer init register. Each bit in the timer 1098 * register represents one tick, so to specify a timeout in 1099 * microseconds, we have to multiply by the correct number of 1100 * ticks-per-microsecond. 1101 */ 1102 switch (sc->sk_type) { 1103 case SK_GENESIS: 1104 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1105 break; 1106 case SK_YUKON_EC: 1107 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1108 break; 1109 default: 1110 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1111 } 1112 aprint_verbose("%s: interrupt moderation is %d us\n", 1113 sc->sk_dev.dv_xname, sc->sk_int_mod); 1114 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1115 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1116 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1117 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1118 sc->sk_int_mod_pending = 0; 1119 } 1120 1121 /* 1122 * Lookup: Check the PCI vendor and device, and return a pointer to 1123 * The structure if the IDs match against our list. 1124 */ 1125 1126 static const struct sk_product * 1127 sk_lookup(const struct pci_attach_args *pa) 1128 { 1129 const struct sk_product *psk; 1130 1131 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1132 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1133 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1134 return psk; 1135 } 1136 return NULL; 1137 } 1138 1139 /* 1140 * Probe for a SysKonnect GEnesis chip. 1141 */ 1142 1143 int 1144 skc_probe(struct device *parent, struct cfdata *match, 1145 void *aux) 1146 { 1147 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1148 const struct sk_product *psk; 1149 pcireg_t subid; 1150 1151 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1152 1153 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1154 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1155 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1156 subid == SK_LINKSYS_EG1032_SUBID) 1157 return 1; 1158 1159 if ((psk = sk_lookup(pa))) { 1160 return 1; 1161 } 1162 return 0; 1163 } 1164 1165 /* 1166 * Force the GEnesis into reset, then bring it out of reset. 1167 */ 1168 void sk_reset(struct sk_softc *sc) 1169 { 1170 DPRINTFN(2, ("sk_reset\n")); 1171 1172 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1173 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1174 if (SK_YUKON_FAMILY(sc->sk_type)) 1175 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1176 1177 DELAY(1000); 1178 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1179 DELAY(2); 1180 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1181 if (SK_YUKON_FAMILY(sc->sk_type)) 1182 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1183 1184 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1185 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1186 CSR_READ_2(sc, SK_LINK_CTRL))); 1187 1188 if (sc->sk_type == SK_GENESIS) { 1189 /* Configure packet arbiter */ 1190 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1191 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1192 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1193 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1194 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1195 } 1196 1197 /* Enable RAM interface */ 1198 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1199 1200 sk_update_int_mod(sc); 1201 } 1202 1203 int 1204 sk_probe(struct device *parent, struct cfdata *match, 1205 void *aux) 1206 { 1207 struct skc_attach_args *sa = aux; 1208 1209 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1210 return 0; 1211 1212 return 1; 1213 } 1214 1215 /* 1216 * Each XMAC chip is attached as a separate logical IP interface. 1217 * Single port cards will have only one logical interface of course. 1218 */ 1219 void 1220 sk_attach(struct device *parent, struct device *self, void *aux) 1221 { 1222 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1223 struct sk_softc *sc = (struct sk_softc *)parent; 1224 struct skc_attach_args *sa = aux; 1225 struct sk_txmap_entry *entry; 1226 struct ifnet *ifp; 1227 bus_dma_segment_t seg; 1228 bus_dmamap_t dmamap; 1229 void *kva; 1230 int i, rseg; 1231 1232 aprint_naive("\n"); 1233 1234 sc_if->sk_port = sa->skc_port; 1235 sc_if->sk_softc = sc; 1236 sc->sk_if[sa->skc_port] = sc_if; 1237 1238 if (sa->skc_port == SK_PORT_A) 1239 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1240 if (sa->skc_port == SK_PORT_B) 1241 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1242 1243 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1244 1245 /* 1246 * Get station address for this interface. Note that 1247 * dual port cards actually come with three station 1248 * addresses: one for each port, plus an extra. The 1249 * extra one is used by the SysKonnect driver software 1250 * as a 'virtual' station address for when both ports 1251 * are operating in failover mode. Currently we don't 1252 * use this extra address. 1253 */ 1254 for (i = 0; i < ETHER_ADDR_LEN; i++) 1255 sc_if->sk_enaddr[i] = 1256 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1257 1258 1259 aprint_normal(": Ethernet address %s\n", 1260 ether_sprintf(sc_if->sk_enaddr)); 1261 1262 /* 1263 * Set up RAM buffer addresses. The NIC will have a certain 1264 * amount of SRAM on it, somewhere between 512K and 2MB. We 1265 * need to divide this up a) between the transmitter and 1266 * receiver and b) between the two XMACs, if this is a 1267 * dual port NIC. Our algorithm is to divide up the memory 1268 * evenly so that everyone gets a fair share. 1269 */ 1270 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1271 u_int32_t chunk, val; 1272 1273 chunk = sc->sk_ramsize / 2; 1274 val = sc->sk_rboff / sizeof(u_int64_t); 1275 sc_if->sk_rx_ramstart = val; 1276 val += (chunk / sizeof(u_int64_t)); 1277 sc_if->sk_rx_ramend = val - 1; 1278 sc_if->sk_tx_ramstart = val; 1279 val += (chunk / sizeof(u_int64_t)); 1280 sc_if->sk_tx_ramend = val - 1; 1281 } else { 1282 u_int32_t chunk, val; 1283 1284 chunk = sc->sk_ramsize / 4; 1285 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1286 sizeof(u_int64_t); 1287 sc_if->sk_rx_ramstart = val; 1288 val += (chunk / sizeof(u_int64_t)); 1289 sc_if->sk_rx_ramend = val - 1; 1290 sc_if->sk_tx_ramstart = val; 1291 val += (chunk / sizeof(u_int64_t)); 1292 sc_if->sk_tx_ramend = val - 1; 1293 } 1294 1295 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1296 " tx_ramstart=%#x tx_ramend=%#x\n", 1297 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1298 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1299 1300 /* Read and save PHY type and set PHY address */ 1301 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1302 switch (sc_if->sk_phytype) { 1303 case SK_PHYTYPE_XMAC: 1304 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1305 break; 1306 case SK_PHYTYPE_BCOM: 1307 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1308 break; 1309 case SK_PHYTYPE_MARV_COPPER: 1310 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1311 break; 1312 default: 1313 aprint_error("%s: unsupported PHY type: %d\n", 1314 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1315 return; 1316 } 1317 1318 /* Allocate the descriptor queues. */ 1319 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1320 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1321 aprint_error("%s: can't alloc rx buffers\n", 1322 sc->sk_dev.dv_xname); 1323 goto fail; 1324 } 1325 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1326 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1327 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1328 sc_if->sk_dev.dv_xname, 1329 (u_long) sizeof(struct sk_ring_data)); 1330 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1331 goto fail; 1332 } 1333 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1334 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1335 &sc_if->sk_ring_map)) { 1336 aprint_error("%s: can't create dma map\n", 1337 sc_if->sk_dev.dv_xname); 1338 bus_dmamem_unmap(sc->sc_dmatag, kva, 1339 sizeof(struct sk_ring_data)); 1340 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1341 goto fail; 1342 } 1343 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1344 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1345 aprint_error("%s: can't load dma map\n", 1346 sc_if->sk_dev.dv_xname); 1347 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1348 bus_dmamem_unmap(sc->sc_dmatag, kva, 1349 sizeof(struct sk_ring_data)); 1350 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1351 goto fail; 1352 } 1353 1354 for (i = 0; i < SK_RX_RING_CNT; i++) 1355 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1356 1357 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1358 for (i = 0; i < SK_TX_RING_CNT; i++) { 1359 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1360 1361 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1362 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1363 aprint_error("%s: Can't create TX dmamap\n", 1364 sc_if->sk_dev.dv_xname); 1365 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1366 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1367 bus_dmamem_unmap(sc->sc_dmatag, kva, 1368 sizeof(struct sk_ring_data)); 1369 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1370 goto fail; 1371 } 1372 1373 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1374 if (!entry) { 1375 aprint_error("%s: Can't alloc txmap entry\n", 1376 sc_if->sk_dev.dv_xname); 1377 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1378 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1379 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1380 bus_dmamem_unmap(sc->sc_dmatag, kva, 1381 sizeof(struct sk_ring_data)); 1382 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1383 goto fail; 1384 } 1385 entry->dmamap = dmamap; 1386 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1387 } 1388 1389 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1390 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1391 1392 ifp = &sc_if->sk_ethercom.ec_if; 1393 /* Try to allocate memory for jumbo buffers. */ 1394 if (sk_alloc_jumbo_mem(sc_if)) { 1395 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1396 goto fail; 1397 } 1398 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1399 | ETHERCAP_JUMBO_MTU; 1400 1401 ifp->if_softc = sc_if; 1402 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1403 ifp->if_ioctl = sk_ioctl; 1404 ifp->if_start = sk_start; 1405 ifp->if_stop = sk_stop; 1406 ifp->if_init = sk_init; 1407 ifp->if_watchdog = sk_watchdog; 1408 ifp->if_capabilities = 0; 1409 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1410 IFQ_SET_READY(&ifp->if_snd); 1411 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1412 1413 /* 1414 * Do miibus setup. 1415 */ 1416 switch (sc->sk_type) { 1417 case SK_GENESIS: 1418 sk_init_xmac(sc_if); 1419 break; 1420 case SK_YUKON: 1421 case SK_YUKON_LITE: 1422 case SK_YUKON_LP: 1423 sk_init_yukon(sc_if); 1424 break; 1425 default: 1426 aprint_error("%s: unknown device type %d\n", 1427 sc->sk_dev.dv_xname, sc->sk_type); 1428 goto fail; 1429 } 1430 1431 DPRINTFN(2, ("sk_attach: 1\n")); 1432 1433 sc_if->sk_mii.mii_ifp = ifp; 1434 switch (sc->sk_type) { 1435 case SK_GENESIS: 1436 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1437 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1438 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1439 break; 1440 case SK_YUKON: 1441 case SK_YUKON_LITE: 1442 case SK_YUKON_LP: 1443 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1444 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1445 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1446 break; 1447 } 1448 1449 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1450 sk_ifmedia_upd, sk_ifmedia_sts); 1451 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1452 MII_OFFSET_ANY, 0); 1453 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1454 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1455 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1456 0, NULL); 1457 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1458 } else 1459 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1460 1461 callout_init(&sc_if->sk_tick_ch, 0); 1462 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1463 1464 DPRINTFN(2, ("sk_attach: 1\n")); 1465 1466 /* 1467 * Call MI attach routines. 1468 */ 1469 if_attach(ifp); 1470 1471 ether_ifattach(ifp, sc_if->sk_enaddr); 1472 1473 #if NRND > 0 1474 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1475 RND_TYPE_NET, 0); 1476 #endif 1477 1478 DPRINTFN(2, ("sk_attach: end\n")); 1479 1480 return; 1481 1482 fail: 1483 sc->sk_if[sa->skc_port] = NULL; 1484 } 1485 1486 int 1487 skcprint(void *aux, const char *pnp) 1488 { 1489 struct skc_attach_args *sa = aux; 1490 1491 if (pnp) 1492 aprint_normal("sk port %c at %s", 1493 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1494 else 1495 aprint_normal(" port %c", 1496 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1497 return UNCONF; 1498 } 1499 1500 /* 1501 * Attach the interface. Allocate softc structures, do ifmedia 1502 * setup and ethernet/BPF attach. 1503 */ 1504 void 1505 skc_attach(struct device *parent, struct device *self, void *aux) 1506 { 1507 struct sk_softc *sc = (struct sk_softc *)self; 1508 struct pci_attach_args *pa = aux; 1509 struct skc_attach_args skca; 1510 pci_chipset_tag_t pc = pa->pa_pc; 1511 #ifndef SK_USEIOSPACE 1512 pcireg_t memtype; 1513 #endif 1514 pci_intr_handle_t ih; 1515 const char *intrstr = NULL; 1516 bus_addr_t iobase; 1517 bus_size_t iosize; 1518 int rc, sk_nodenum; 1519 u_int32_t command; 1520 const char *revstr; 1521 const struct sysctlnode *node; 1522 1523 aprint_naive("\n"); 1524 1525 DPRINTFN(2, ("begin skc_attach\n")); 1526 1527 /* 1528 * Handle power management nonsense. 1529 */ 1530 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1531 1532 if (command == 0x01) { 1533 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1534 if (command & SK_PSTATE_MASK) { 1535 u_int32_t xiobase, membase, irq; 1536 1537 /* Save important PCI config data. */ 1538 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1539 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1540 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1541 1542 /* Reset the power state. */ 1543 aprint_normal("%s chip is in D%d power mode " 1544 "-- setting to D0\n", sc->sk_dev.dv_xname, 1545 command & SK_PSTATE_MASK); 1546 command &= 0xFFFFFFFC; 1547 pci_conf_write(pc, pa->pa_tag, 1548 SK_PCI_PWRMGMTCTRL, command); 1549 1550 /* Restore PCI config data. */ 1551 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1552 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1553 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1554 } 1555 } 1556 1557 /* 1558 * Map control/status registers. 1559 */ 1560 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1561 command |= PCI_COMMAND_IO_ENABLE | 1562 PCI_COMMAND_MEM_ENABLE | 1563 PCI_COMMAND_MASTER_ENABLE; 1564 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1565 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1566 1567 #ifdef SK_USEIOSPACE 1568 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1569 aprint_error(": failed to enable I/O ports!\n"); 1570 return; 1571 } 1572 /* 1573 * Map control/status registers. 1574 */ 1575 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1576 &sc->sk_btag, &sc->sk_bhandle, 1577 &iobase, &iosize)) { 1578 aprint_error(": can't find i/o space\n"); 1579 return; 1580 } 1581 #else 1582 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1583 aprint_error(": failed to enable memory mapping!\n"); 1584 return; 1585 } 1586 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1587 switch (memtype) { 1588 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1589 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1590 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1591 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1592 &iobase, &iosize) == 0) 1593 break; 1594 default: 1595 aprint_error("%s: can't find mem space\n", 1596 sc->sk_dev.dv_xname); 1597 return; 1598 } 1599 1600 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1601 #endif 1602 sc->sc_dmatag = pa->pa_dmat; 1603 1604 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1605 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1606 1607 /* bail out here if chip is not recognized */ 1608 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1609 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1610 goto fail; 1611 } 1612 if (SK_IS_YUKON2(sc)) { 1613 aprint_error("%s: Does not support Yukon2--try msk(4).\n", 1614 sc->sk_dev.dv_xname); 1615 goto fail; 1616 } 1617 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1618 1619 /* Allocate interrupt */ 1620 if (pci_intr_map(pa, &ih)) { 1621 aprint_error(": couldn't map interrupt\n"); 1622 goto fail; 1623 } 1624 1625 intrstr = pci_intr_string(pc, ih); 1626 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1627 if (sc->sk_intrhand == NULL) { 1628 aprint_error(": couldn't establish interrupt"); 1629 if (intrstr != NULL) 1630 aprint_normal(" at %s", intrstr); 1631 goto fail; 1632 } 1633 aprint_normal(": %s\n", intrstr); 1634 1635 /* Reset the adapter. */ 1636 sk_reset(sc); 1637 1638 /* Read and save vital product data from EEPROM. */ 1639 sk_vpd_read(sc); 1640 1641 if (sc->sk_type == SK_GENESIS) { 1642 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1643 /* Read and save RAM size and RAMbuffer offset */ 1644 switch (val) { 1645 case SK_RAMSIZE_512K_64: 1646 sc->sk_ramsize = 0x80000; 1647 sc->sk_rboff = SK_RBOFF_0; 1648 break; 1649 case SK_RAMSIZE_1024K_64: 1650 sc->sk_ramsize = 0x100000; 1651 sc->sk_rboff = SK_RBOFF_80000; 1652 break; 1653 case SK_RAMSIZE_1024K_128: 1654 sc->sk_ramsize = 0x100000; 1655 sc->sk_rboff = SK_RBOFF_0; 1656 break; 1657 case SK_RAMSIZE_2048K_128: 1658 sc->sk_ramsize = 0x200000; 1659 sc->sk_rboff = SK_RBOFF_0; 1660 break; 1661 default: 1662 aprint_error("%s: unknown ram size: %d\n", 1663 sc->sk_dev.dv_xname, val); 1664 goto fail_1; 1665 break; 1666 } 1667 1668 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1669 sc->sk_ramsize, sc->sk_ramsize / 1024, 1670 sc->sk_rboff)); 1671 } else { 1672 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1673 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1674 sc->sk_rboff = SK_RBOFF_0; 1675 1676 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1677 sc->sk_ramsize / 1024, sc->sk_ramsize, 1678 sc->sk_rboff)); 1679 } 1680 1681 /* Read and save physical media type */ 1682 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1683 case SK_PMD_1000BASESX: 1684 sc->sk_pmd = IFM_1000_SX; 1685 break; 1686 case SK_PMD_1000BASELX: 1687 sc->sk_pmd = IFM_1000_LX; 1688 break; 1689 case SK_PMD_1000BASECX: 1690 sc->sk_pmd = IFM_1000_CX; 1691 break; 1692 case SK_PMD_1000BASETX: 1693 case SK_PMD_1000BASETX_ALT: 1694 sc->sk_pmd = IFM_1000_T; 1695 break; 1696 default: 1697 aprint_error("%s: unknown media type: 0x%x\n", 1698 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1699 goto fail_1; 1700 } 1701 1702 /* determine whether to name it with vpd or just make it up */ 1703 /* Marvell Yukon VPD's can freqently be bogus */ 1704 1705 switch (pa->pa_id) { 1706 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1707 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1708 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1709 case PCI_PRODUCT_3COM_3C940: 1710 case PCI_PRODUCT_DLINK_DGE530T: 1711 case PCI_PRODUCT_DLINK_DGE560T: 1712 case PCI_PRODUCT_DLINK_DGE560T_2: 1713 case PCI_PRODUCT_LINKSYS_EG1032: 1714 case PCI_PRODUCT_LINKSYS_EG1064: 1715 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1716 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1717 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1718 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1719 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1720 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1721 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1722 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1723 sc->sk_name = sc->sk_vpd_prodname; 1724 break; 1725 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1726 /* whoops yukon vpd prodname bears no resemblance to reality */ 1727 switch (sc->sk_type) { 1728 case SK_GENESIS: 1729 sc->sk_name = sc->sk_vpd_prodname; 1730 break; 1731 case SK_YUKON: 1732 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1733 break; 1734 case SK_YUKON_LITE: 1735 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1736 break; 1737 case SK_YUKON_LP: 1738 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1739 break; 1740 default: 1741 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1742 } 1743 1744 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1745 1746 if ( sc->sk_type == SK_YUKON ) { 1747 uint32_t flashaddr; 1748 uint8_t testbyte; 1749 1750 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1751 1752 /* test Flash-Address Register */ 1753 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1754 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1755 1756 if (testbyte != 0) { 1757 /* this is yukon lite Rev. A0 */ 1758 sc->sk_type = SK_YUKON_LITE; 1759 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1760 /* restore Flash-Address Register */ 1761 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1762 } 1763 } 1764 break; 1765 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1766 sc->sk_name = sc->sk_vpd_prodname; 1767 break; 1768 default: 1769 sc->sk_name = "Unknown Marvell"; 1770 } 1771 1772 1773 if ( sc->sk_type == SK_YUKON_LITE ) { 1774 switch (sc->sk_rev) { 1775 case SK_YUKON_LITE_REV_A0: 1776 revstr = "A0"; 1777 break; 1778 case SK_YUKON_LITE_REV_A1: 1779 revstr = "A1"; 1780 break; 1781 case SK_YUKON_LITE_REV_A3: 1782 revstr = "A3"; 1783 break; 1784 default: 1785 revstr = ""; 1786 } 1787 } else { 1788 revstr = ""; 1789 } 1790 1791 /* Announce the product name. */ 1792 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1793 sc->sk_name, revstr, sc->sk_rev); 1794 1795 skca.skc_port = SK_PORT_A; 1796 (void)config_found(&sc->sk_dev, &skca, skcprint); 1797 1798 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1799 skca.skc_port = SK_PORT_B; 1800 (void)config_found(&sc->sk_dev, &skca, skcprint); 1801 } 1802 1803 /* Turn on the 'driver is loaded' LED. */ 1804 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1805 1806 /* skc sysctl setup */ 1807 1808 sc->sk_int_mod = SK_IM_DEFAULT; 1809 sc->sk_int_mod_pending = 0; 1810 1811 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1812 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1813 SYSCTL_DESCR("skc per-controller controls"), 1814 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1815 CTL_EOL)) != 0) { 1816 aprint_normal("%s: couldn't create sysctl node\n", 1817 sc->sk_dev.dv_xname); 1818 goto fail_1; 1819 } 1820 1821 sk_nodenum = node->sysctl_num; 1822 1823 /* interrupt moderation time in usecs */ 1824 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1825 CTLFLAG_READWRITE, 1826 CTLTYPE_INT, "int_mod", 1827 SYSCTL_DESCR("sk interrupt moderation timer"), 1828 sk_sysctl_handler, 0, sc, 1829 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1830 CTL_EOL)) != 0) { 1831 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1832 sc->sk_dev.dv_xname); 1833 goto fail_1; 1834 } 1835 1836 return; 1837 1838 fail_1: 1839 pci_intr_disestablish(pc, sc->sk_intrhand); 1840 fail: 1841 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1842 } 1843 1844 int 1845 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1846 { 1847 struct sk_softc *sc = sc_if->sk_softc; 1848 struct sk_tx_desc *f = NULL; 1849 u_int32_t frag, cur, cnt = 0, sk_ctl; 1850 int i; 1851 struct sk_txmap_entry *entry; 1852 bus_dmamap_t txmap; 1853 1854 DPRINTFN(3, ("sk_encap\n")); 1855 1856 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1857 if (entry == NULL) { 1858 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1859 return ENOBUFS; 1860 } 1861 txmap = entry->dmamap; 1862 1863 cur = frag = *txidx; 1864 1865 #ifdef SK_DEBUG 1866 if (skdebug >= 3) 1867 sk_dump_mbuf(m_head); 1868 #endif 1869 1870 /* 1871 * Start packing the mbufs in this chain into 1872 * the fragment pointers. Stop when we run out 1873 * of fragments or hit the end of the mbuf chain. 1874 */ 1875 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1876 BUS_DMA_NOWAIT)) { 1877 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1878 return ENOBUFS; 1879 } 1880 1881 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1882 1883 /* Sync the DMA map. */ 1884 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1885 BUS_DMASYNC_PREWRITE); 1886 1887 for (i = 0; i < txmap->dm_nsegs; i++) { 1888 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1889 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1890 return ENOBUFS; 1891 } 1892 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1893 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1894 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1895 if (cnt == 0) 1896 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1897 else 1898 sk_ctl |= SK_TXCTL_OWN; 1899 f->sk_ctl = htole32(sk_ctl); 1900 cur = frag; 1901 SK_INC(frag, SK_TX_RING_CNT); 1902 cnt++; 1903 } 1904 1905 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1906 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1907 1908 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1909 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1910 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1911 1912 /* Sync descriptors before handing to chip */ 1913 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1914 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1915 1916 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1917 htole32(SK_TXCTL_OWN); 1918 1919 /* Sync first descriptor to hand it off */ 1920 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1921 1922 sc_if->sk_cdata.sk_tx_cnt += cnt; 1923 1924 #ifdef SK_DEBUG 1925 if (skdebug >= 3) { 1926 struct sk_tx_desc *desc; 1927 u_int32_t idx; 1928 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1929 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1930 sk_dump_txdesc(desc, idx); 1931 } 1932 } 1933 #endif 1934 1935 *txidx = frag; 1936 1937 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1938 1939 return 0; 1940 } 1941 1942 void 1943 sk_start(struct ifnet *ifp) 1944 { 1945 struct sk_if_softc *sc_if = ifp->if_softc; 1946 struct sk_softc *sc = sc_if->sk_softc; 1947 struct mbuf *m_head = NULL; 1948 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1949 int pkts = 0; 1950 1951 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1952 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1953 1954 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1955 IFQ_POLL(&ifp->if_snd, m_head); 1956 if (m_head == NULL) 1957 break; 1958 1959 /* 1960 * Pack the data into the transmit ring. If we 1961 * don't have room, set the OACTIVE flag and wait 1962 * for the NIC to drain the ring. 1963 */ 1964 if (sk_encap(sc_if, m_head, &idx)) { 1965 ifp->if_flags |= IFF_OACTIVE; 1966 break; 1967 } 1968 1969 /* now we are committed to transmit the packet */ 1970 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1971 pkts++; 1972 1973 /* 1974 * If there's a BPF listener, bounce a copy of this frame 1975 * to him. 1976 */ 1977 #if NBPFILTER > 0 1978 if (ifp->if_bpf) 1979 bpf_mtap(ifp->if_bpf, m_head); 1980 #endif 1981 } 1982 if (pkts == 0) 1983 return; 1984 1985 /* Transmit */ 1986 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1987 sc_if->sk_cdata.sk_tx_prod = idx; 1988 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1989 1990 /* Set a timeout in case the chip goes out to lunch. */ 1991 ifp->if_timer = 5; 1992 } 1993 } 1994 1995 1996 void 1997 sk_watchdog(struct ifnet *ifp) 1998 { 1999 struct sk_if_softc *sc_if = ifp->if_softc; 2000 2001 /* 2002 * Reclaim first as there is a possibility of losing Tx completion 2003 * interrupts. 2004 */ 2005 sk_txeof(sc_if); 2006 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2007 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 2008 2009 ifp->if_oerrors++; 2010 2011 sk_init(ifp); 2012 } 2013 } 2014 2015 void 2016 sk_shutdown(void *v) 2017 { 2018 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2019 struct sk_softc *sc = sc_if->sk_softc; 2020 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2021 2022 DPRINTFN(2, ("sk_shutdown\n")); 2023 sk_stop(ifp,1); 2024 2025 /* Turn off the 'driver is loaded' LED. */ 2026 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2027 2028 /* 2029 * Reset the GEnesis controller. Doing this should also 2030 * assert the resets on the attached XMAC(s). 2031 */ 2032 sk_reset(sc); 2033 } 2034 2035 void 2036 sk_rxeof(struct sk_if_softc *sc_if) 2037 { 2038 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2039 struct mbuf *m; 2040 struct sk_chain *cur_rx; 2041 struct sk_rx_desc *cur_desc; 2042 int i, cur, total_len = 0; 2043 u_int32_t rxstat, sk_ctl; 2044 bus_dmamap_t dmamap; 2045 2046 i = sc_if->sk_cdata.sk_rx_prod; 2047 2048 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2049 2050 for (;;) { 2051 cur = i; 2052 2053 /* Sync the descriptor */ 2054 SK_CDRXSYNC(sc_if, cur, 2055 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2056 2057 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2058 if (sk_ctl & SK_RXCTL_OWN) { 2059 /* Invalidate the descriptor -- it's not ready yet */ 2060 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2061 sc_if->sk_cdata.sk_rx_prod = i; 2062 break; 2063 } 2064 2065 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2066 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2067 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2068 2069 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2070 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2071 2072 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2073 m = cur_rx->sk_mbuf; 2074 cur_rx->sk_mbuf = NULL; 2075 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2076 2077 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2078 2079 SK_INC(i, SK_RX_RING_CNT); 2080 2081 if (rxstat & XM_RXSTAT_ERRFRAME) { 2082 ifp->if_ierrors++; 2083 sk_newbuf(sc_if, cur, m, dmamap); 2084 continue; 2085 } 2086 2087 /* 2088 * Try to allocate a new jumbo buffer. If that 2089 * fails, copy the packet to mbufs and put the 2090 * jumbo buffer back in the ring so it can be 2091 * re-used. If allocating mbufs fails, then we 2092 * have to drop the packet. 2093 */ 2094 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2095 struct mbuf *m0; 2096 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2097 total_len + ETHER_ALIGN, 0, ifp, NULL); 2098 sk_newbuf(sc_if, cur, m, dmamap); 2099 if (m0 == NULL) { 2100 aprint_error("%s: no receive buffers " 2101 "available -- packet dropped!\n", 2102 sc_if->sk_dev.dv_xname); 2103 ifp->if_ierrors++; 2104 continue; 2105 } 2106 m_adj(m0, ETHER_ALIGN); 2107 m = m0; 2108 } else { 2109 m->m_pkthdr.rcvif = ifp; 2110 m->m_pkthdr.len = m->m_len = total_len; 2111 } 2112 2113 ifp->if_ipackets++; 2114 2115 #if NBPFILTER > 0 2116 if (ifp->if_bpf) 2117 bpf_mtap(ifp->if_bpf, m); 2118 #endif 2119 /* pass it on. */ 2120 (*ifp->if_input)(ifp, m); 2121 } 2122 } 2123 2124 void 2125 sk_txeof(struct sk_if_softc *sc_if) 2126 { 2127 struct sk_softc *sc = sc_if->sk_softc; 2128 struct sk_tx_desc *cur_tx; 2129 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2130 u_int32_t idx, sk_ctl; 2131 struct sk_txmap_entry *entry; 2132 2133 DPRINTFN(3, ("sk_txeof\n")); 2134 2135 /* 2136 * Go through our tx ring and free mbufs for those 2137 * frames that have been sent. 2138 */ 2139 idx = sc_if->sk_cdata.sk_tx_cons; 2140 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2141 SK_CDTXSYNC(sc_if, idx, 1, 2142 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2143 2144 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2145 sk_ctl = le32toh(cur_tx->sk_ctl); 2146 #ifdef SK_DEBUG 2147 if (skdebug >= 3) 2148 sk_dump_txdesc(cur_tx, idx); 2149 #endif 2150 if (sk_ctl & SK_TXCTL_OWN) { 2151 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2152 break; 2153 } 2154 if (sk_ctl & SK_TXCTL_LASTFRAG) 2155 ifp->if_opackets++; 2156 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2157 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2158 2159 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2160 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2161 2162 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2163 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2164 2165 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2166 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2167 link); 2168 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2169 } 2170 sc_if->sk_cdata.sk_tx_cnt--; 2171 SK_INC(idx, SK_TX_RING_CNT); 2172 } 2173 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2174 ifp->if_timer = 0; 2175 else /* nudge chip to keep tx ring moving */ 2176 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2177 2178 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2179 ifp->if_flags &= ~IFF_OACTIVE; 2180 2181 sc_if->sk_cdata.sk_tx_cons = idx; 2182 } 2183 2184 void 2185 sk_tick(void *xsc_if) 2186 { 2187 struct sk_if_softc *sc_if = xsc_if; 2188 struct mii_data *mii = &sc_if->sk_mii; 2189 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2190 int i; 2191 2192 DPRINTFN(3, ("sk_tick\n")); 2193 2194 if (!(ifp->if_flags & IFF_UP)) 2195 return; 2196 2197 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2198 sk_intr_bcom(sc_if); 2199 return; 2200 } 2201 2202 /* 2203 * According to SysKonnect, the correct way to verify that 2204 * the link has come back up is to poll bit 0 of the GPIO 2205 * register three times. This pin has the signal from the 2206 * link sync pin connected to it; if we read the same link 2207 * state 3 times in a row, we know the link is up. 2208 */ 2209 for (i = 0; i < 3; i++) { 2210 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2211 break; 2212 } 2213 2214 if (i != 3) { 2215 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2216 return; 2217 } 2218 2219 /* Turn the GP0 interrupt back on. */ 2220 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2221 SK_XM_READ_2(sc_if, XM_ISR); 2222 mii_tick(mii); 2223 mii_pollstat(mii); 2224 callout_stop(&sc_if->sk_tick_ch); 2225 } 2226 2227 void 2228 sk_intr_bcom(struct sk_if_softc *sc_if) 2229 { 2230 struct mii_data *mii = &sc_if->sk_mii; 2231 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2232 int status; 2233 2234 2235 DPRINTFN(3, ("sk_intr_bcom\n")); 2236 2237 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2238 2239 /* 2240 * Read the PHY interrupt register to make sure 2241 * we clear any pending interrupts. 2242 */ 2243 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2244 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2245 2246 if (!(ifp->if_flags & IFF_RUNNING)) { 2247 sk_init_xmac(sc_if); 2248 return; 2249 } 2250 2251 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2252 int lstat; 2253 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2254 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2255 2256 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2257 mii_mediachg(mii); 2258 /* Turn off the link LED. */ 2259 SK_IF_WRITE_1(sc_if, 0, 2260 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2261 sc_if->sk_link = 0; 2262 } else if (status & BRGPHY_ISR_LNK_CHG) { 2263 sk_xmac_miibus_writereg((struct device *)sc_if, 2264 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2265 mii_tick(mii); 2266 sc_if->sk_link = 1; 2267 /* Turn on the link LED. */ 2268 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2269 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2270 SK_LINKLED_BLINK_OFF); 2271 mii_pollstat(mii); 2272 } else { 2273 mii_tick(mii); 2274 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2275 } 2276 } 2277 2278 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2279 } 2280 2281 void 2282 sk_intr_xmac(struct sk_if_softc *sc_if) 2283 { 2284 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2285 2286 DPRINTFN(3, ("sk_intr_xmac\n")); 2287 2288 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2289 if (status & XM_ISR_GP0_SET) { 2290 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2291 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2292 } 2293 2294 if (status & XM_ISR_AUTONEG_DONE) { 2295 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2296 } 2297 } 2298 2299 if (status & XM_IMR_TX_UNDERRUN) 2300 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2301 2302 if (status & XM_IMR_RX_OVERRUN) 2303 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2304 } 2305 2306 void 2307 sk_intr_yukon(struct sk_if_softc *sc_if) 2308 { 2309 int status; 2310 2311 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2312 2313 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2314 } 2315 2316 int 2317 sk_intr(void *xsc) 2318 { 2319 struct sk_softc *sc = xsc; 2320 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2321 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2322 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2323 u_int32_t status; 2324 int claimed = 0; 2325 2326 if (sc_if0 != NULL) 2327 ifp0 = &sc_if0->sk_ethercom.ec_if; 2328 if (sc_if1 != NULL) 2329 ifp1 = &sc_if1->sk_ethercom.ec_if; 2330 2331 for (;;) { 2332 status = CSR_READ_4(sc, SK_ISSR); 2333 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2334 2335 if (!(status & sc->sk_intrmask)) 2336 break; 2337 2338 claimed = 1; 2339 2340 /* Handle receive interrupts first. */ 2341 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2342 sk_rxeof(sc_if0); 2343 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2344 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2345 } 2346 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2347 sk_rxeof(sc_if1); 2348 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2349 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2350 } 2351 2352 /* Then transmit interrupts. */ 2353 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2354 sk_txeof(sc_if0); 2355 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2356 SK_TXBMU_CLR_IRQ_EOF); 2357 } 2358 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2359 sk_txeof(sc_if1); 2360 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2361 SK_TXBMU_CLR_IRQ_EOF); 2362 } 2363 2364 /* Then MAC interrupts. */ 2365 if (sc_if0 && (status & SK_ISR_MAC1) && 2366 (ifp0->if_flags & IFF_RUNNING)) { 2367 if (sc->sk_type == SK_GENESIS) 2368 sk_intr_xmac(sc_if0); 2369 else 2370 sk_intr_yukon(sc_if0); 2371 } 2372 2373 if (sc_if1 && (status & SK_ISR_MAC2) && 2374 (ifp1->if_flags & IFF_RUNNING)) { 2375 if (sc->sk_type == SK_GENESIS) 2376 sk_intr_xmac(sc_if1); 2377 else 2378 sk_intr_yukon(sc_if1); 2379 2380 } 2381 2382 if (status & SK_ISR_EXTERNAL_REG) { 2383 if (sc_if0 != NULL && 2384 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2385 sk_intr_bcom(sc_if0); 2386 2387 if (sc_if1 != NULL && 2388 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2389 sk_intr_bcom(sc_if1); 2390 } 2391 } 2392 2393 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2394 2395 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2396 sk_start(ifp0); 2397 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2398 sk_start(ifp1); 2399 2400 #if NRND > 0 2401 if (RND_ENABLED(&sc->rnd_source)) 2402 rnd_add_uint32(&sc->rnd_source, status); 2403 #endif 2404 2405 if (sc->sk_int_mod_pending) 2406 sk_update_int_mod(sc); 2407 2408 return claimed; 2409 } 2410 2411 void 2412 sk_init_xmac(struct sk_if_softc *sc_if) 2413 { 2414 struct sk_softc *sc = sc_if->sk_softc; 2415 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2416 static const struct sk_bcom_hack bhack[] = { 2417 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2418 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2419 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2420 { 0, 0 } }; 2421 2422 DPRINTFN(1, ("sk_init_xmac\n")); 2423 2424 /* Unreset the XMAC. */ 2425 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2426 DELAY(1000); 2427 2428 /* Reset the XMAC's internal state. */ 2429 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2430 2431 /* Save the XMAC II revision */ 2432 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2433 2434 /* 2435 * Perform additional initialization for external PHYs, 2436 * namely for the 1000baseTX cards that use the XMAC's 2437 * GMII mode. 2438 */ 2439 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2440 int i = 0; 2441 u_int32_t val; 2442 2443 /* Take PHY out of reset. */ 2444 val = sk_win_read_4(sc, SK_GPIO); 2445 if (sc_if->sk_port == SK_PORT_A) 2446 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2447 else 2448 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2449 sk_win_write_4(sc, SK_GPIO, val); 2450 2451 /* Enable GMII mode on the XMAC. */ 2452 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2453 2454 sk_xmac_miibus_writereg((struct device *)sc_if, 2455 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2456 DELAY(10000); 2457 sk_xmac_miibus_writereg((struct device *)sc_if, 2458 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2459 2460 /* 2461 * Early versions of the BCM5400 apparently have 2462 * a bug that requires them to have their reserved 2463 * registers initialized to some magic values. I don't 2464 * know what the numbers do, I'm just the messenger. 2465 */ 2466 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2467 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2468 while (bhack[i].reg) { 2469 sk_xmac_miibus_writereg((struct device *)sc_if, 2470 SK_PHYADDR_BCOM, bhack[i].reg, 2471 bhack[i].val); 2472 i++; 2473 } 2474 } 2475 } 2476 2477 /* Set station address */ 2478 SK_XM_WRITE_2(sc_if, XM_PAR0, 2479 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2480 SK_XM_WRITE_2(sc_if, XM_PAR1, 2481 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2482 SK_XM_WRITE_2(sc_if, XM_PAR2, 2483 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2484 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2485 2486 if (ifp->if_flags & IFF_PROMISC) 2487 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2488 else 2489 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2490 2491 if (ifp->if_flags & IFF_BROADCAST) 2492 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2493 else 2494 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2495 2496 /* We don't need the FCS appended to the packet. */ 2497 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2498 2499 /* We want short frames padded to 60 bytes. */ 2500 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2501 2502 /* 2503 * Enable the reception of all error frames. This is is 2504 * a necessary evil due to the design of the XMAC. The 2505 * XMAC's receive FIFO is only 8K in size, however jumbo 2506 * frames can be up to 9000 bytes in length. When bad 2507 * frame filtering is enabled, the XMAC's RX FIFO operates 2508 * in 'store and forward' mode. For this to work, the 2509 * entire frame has to fit into the FIFO, but that means 2510 * that jumbo frames larger than 8192 bytes will be 2511 * truncated. Disabling all bad frame filtering causes 2512 * the RX FIFO to operate in streaming mode, in which 2513 * case the XMAC will start transfering frames out of the 2514 * RX FIFO as soon as the FIFO threshold is reached. 2515 */ 2516 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2517 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2518 XM_MODE_RX_INRANGELEN); 2519 2520 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2521 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2522 else 2523 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2524 2525 /* 2526 * Bump up the transmit threshold. This helps hold off transmit 2527 * underruns when we're blasting traffic from both ports at once. 2528 */ 2529 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2530 2531 /* Set multicast filter */ 2532 sk_setmulti(sc_if); 2533 2534 /* Clear and enable interrupts */ 2535 SK_XM_READ_2(sc_if, XM_ISR); 2536 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2537 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2538 else 2539 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2540 2541 /* Configure MAC arbiter */ 2542 switch (sc_if->sk_xmac_rev) { 2543 case XM_XMAC_REV_B2: 2544 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2545 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2546 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2547 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2548 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2549 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2550 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2551 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2552 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2553 break; 2554 case XM_XMAC_REV_C1: 2555 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2556 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2557 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2558 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2559 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2560 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2561 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2562 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2563 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2564 break; 2565 default: 2566 break; 2567 } 2568 sk_win_write_2(sc, SK_MACARB_CTL, 2569 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2570 2571 sc_if->sk_link = 1; 2572 } 2573 2574 void sk_init_yukon(struct sk_if_softc *sc_if) 2575 { 2576 u_int32_t /*mac, */phy; 2577 u_int16_t reg; 2578 struct sk_softc *sc; 2579 int i; 2580 2581 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2582 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2583 2584 sc = sc_if->sk_softc; 2585 if (sc->sk_type == SK_YUKON_LITE && 2586 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2587 /* Take PHY out of reset. */ 2588 sk_win_write_4(sc, SK_GPIO, 2589 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2590 } 2591 2592 2593 /* GMAC and GPHY Reset */ 2594 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2595 2596 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2597 2598 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2599 DELAY(1000); 2600 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2601 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2602 DELAY(1000); 2603 2604 2605 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2606 2607 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2608 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2609 2610 switch (sc_if->sk_softc->sk_pmd) { 2611 case IFM_1000_SX: 2612 case IFM_1000_LX: 2613 phy |= SK_GPHY_FIBER; 2614 break; 2615 2616 case IFM_1000_CX: 2617 case IFM_1000_T: 2618 phy |= SK_GPHY_COPPER; 2619 break; 2620 } 2621 2622 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2623 2624 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2625 DELAY(1000); 2626 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2627 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2628 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2629 2630 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2631 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2632 2633 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2634 2635 /* unused read of the interrupt source register */ 2636 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2637 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2638 2639 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2640 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2641 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2642 2643 /* MIB Counter Clear Mode set */ 2644 reg |= YU_PAR_MIB_CLR; 2645 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2646 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2647 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2648 2649 /* MIB Counter Clear Mode clear */ 2650 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2651 reg &= ~YU_PAR_MIB_CLR; 2652 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2653 2654 /* receive control reg */ 2655 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2656 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2657 YU_RCR_CRCR); 2658 2659 /* transmit parameter register */ 2660 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2661 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2662 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2663 2664 /* serial mode register */ 2665 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2666 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2667 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2668 YU_SMR_IPG_DATA(0x1e)); 2669 2670 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2671 /* Setup Yukon's address */ 2672 for (i = 0; i < 3; i++) { 2673 /* Write Source Address 1 (unicast filter) */ 2674 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2675 sc_if->sk_enaddr[i * 2] | 2676 sc_if->sk_enaddr[i * 2 + 1] << 8); 2677 } 2678 2679 for (i = 0; i < 3; i++) { 2680 reg = sk_win_read_2(sc_if->sk_softc, 2681 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2682 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2683 } 2684 2685 /* Set multicast filter */ 2686 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2687 sk_setmulti(sc_if); 2688 2689 /* enable interrupt mask for counter overflows */ 2690 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2691 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2692 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2693 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2694 2695 /* Configure RX MAC FIFO */ 2696 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2697 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2698 2699 /* Configure TX MAC FIFO */ 2700 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2701 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2702 2703 DPRINTFN(6, ("sk_init_yukon: end\n")); 2704 } 2705 2706 /* 2707 * Note that to properly initialize any part of the GEnesis chip, 2708 * you first have to take it out of reset mode. 2709 */ 2710 int 2711 sk_init(struct ifnet *ifp) 2712 { 2713 struct sk_if_softc *sc_if = ifp->if_softc; 2714 struct sk_softc *sc = sc_if->sk_softc; 2715 struct mii_data *mii = &sc_if->sk_mii; 2716 int s; 2717 u_int32_t imr, imtimer_ticks; 2718 2719 DPRINTFN(1, ("sk_init\n")); 2720 2721 s = splnet(); 2722 2723 if (ifp->if_flags & IFF_RUNNING) { 2724 splx(s); 2725 return 0; 2726 } 2727 2728 /* Cancel pending I/O and free all RX/TX buffers. */ 2729 sk_stop(ifp,0); 2730 2731 if (sc->sk_type == SK_GENESIS) { 2732 /* Configure LINK_SYNC LED */ 2733 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2734 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2735 SK_LINKLED_LINKSYNC_ON); 2736 2737 /* Configure RX LED */ 2738 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2739 SK_RXLEDCTL_COUNTER_START); 2740 2741 /* Configure TX LED */ 2742 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2743 SK_TXLEDCTL_COUNTER_START); 2744 } 2745 2746 /* Configure I2C registers */ 2747 2748 /* Configure XMAC(s) */ 2749 switch (sc->sk_type) { 2750 case SK_GENESIS: 2751 sk_init_xmac(sc_if); 2752 break; 2753 case SK_YUKON: 2754 case SK_YUKON_LITE: 2755 case SK_YUKON_LP: 2756 sk_init_yukon(sc_if); 2757 break; 2758 } 2759 mii_mediachg(mii); 2760 2761 if (sc->sk_type == SK_GENESIS) { 2762 /* Configure MAC FIFOs */ 2763 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2764 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2765 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2766 2767 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2768 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2769 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2770 } 2771 2772 /* Configure transmit arbiter(s) */ 2773 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2774 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2775 2776 /* Configure RAMbuffers */ 2777 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2778 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2779 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2780 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2781 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2782 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2783 2784 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2785 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2786 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2787 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2788 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2789 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2790 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2791 2792 /* Configure BMUs */ 2793 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2794 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2795 SK_RX_RING_ADDR(sc_if, 0)); 2796 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2797 2798 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2799 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2800 SK_TX_RING_ADDR(sc_if, 0)); 2801 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2802 2803 /* Init descriptors */ 2804 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2805 aprint_error("%s: initialization failed: no " 2806 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2807 sk_stop(ifp,0); 2808 splx(s); 2809 return ENOBUFS; 2810 } 2811 2812 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2813 aprint_error("%s: initialization failed: no " 2814 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2815 sk_stop(ifp,0); 2816 splx(s); 2817 return ENOBUFS; 2818 } 2819 2820 /* Set interrupt moderation if changed via sysctl. */ 2821 switch (sc->sk_type) { 2822 case SK_GENESIS: 2823 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2824 break; 2825 case SK_YUKON_EC: 2826 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2827 break; 2828 default: 2829 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2830 } 2831 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2832 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2833 sk_win_write_4(sc, SK_IMTIMERINIT, 2834 SK_IM_USECS(sc->sk_int_mod)); 2835 aprint_verbose("%s: interrupt moderation is %d us\n", 2836 sc->sk_dev.dv_xname, sc->sk_int_mod); 2837 } 2838 2839 /* Configure interrupt handling */ 2840 CSR_READ_4(sc, SK_ISSR); 2841 if (sc_if->sk_port == SK_PORT_A) 2842 sc->sk_intrmask |= SK_INTRS1; 2843 else 2844 sc->sk_intrmask |= SK_INTRS2; 2845 2846 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2847 2848 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2849 2850 /* Start BMUs. */ 2851 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2852 2853 if (sc->sk_type == SK_GENESIS) { 2854 /* Enable XMACs TX and RX state machines */ 2855 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2856 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2857 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2858 } 2859 2860 if (SK_YUKON_FAMILY(sc->sk_type)) { 2861 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2862 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2863 #if 0 2864 /* XXX disable 100Mbps and full duplex mode? */ 2865 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2866 #endif 2867 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2868 } 2869 2870 2871 ifp->if_flags |= IFF_RUNNING; 2872 ifp->if_flags &= ~IFF_OACTIVE; 2873 2874 splx(s); 2875 return 0; 2876 } 2877 2878 void 2879 sk_stop(struct ifnet *ifp, int disable) 2880 { 2881 struct sk_if_softc *sc_if = ifp->if_softc; 2882 struct sk_softc *sc = sc_if->sk_softc; 2883 int i; 2884 2885 DPRINTFN(1, ("sk_stop\n")); 2886 2887 callout_stop(&sc_if->sk_tick_ch); 2888 2889 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2890 u_int32_t val; 2891 2892 /* Put PHY back into reset. */ 2893 val = sk_win_read_4(sc, SK_GPIO); 2894 if (sc_if->sk_port == SK_PORT_A) { 2895 val |= SK_GPIO_DIR0; 2896 val &= ~SK_GPIO_DAT0; 2897 } else { 2898 val |= SK_GPIO_DIR2; 2899 val &= ~SK_GPIO_DAT2; 2900 } 2901 sk_win_write_4(sc, SK_GPIO, val); 2902 } 2903 2904 /* Turn off various components of this interface. */ 2905 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2906 switch (sc->sk_type) { 2907 case SK_GENESIS: 2908 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2909 SK_TXMACCTL_XMAC_RESET); 2910 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2911 break; 2912 case SK_YUKON: 2913 case SK_YUKON_LITE: 2914 case SK_YUKON_LP: 2915 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2916 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2917 break; 2918 } 2919 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2920 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2921 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2922 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2923 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2924 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2925 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2926 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2927 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2928 2929 /* Disable interrupts */ 2930 if (sc_if->sk_port == SK_PORT_A) 2931 sc->sk_intrmask &= ~SK_INTRS1; 2932 else 2933 sc->sk_intrmask &= ~SK_INTRS2; 2934 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2935 2936 SK_XM_READ_2(sc_if, XM_ISR); 2937 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2938 2939 /* Free RX and TX mbufs still in the queues. */ 2940 for (i = 0; i < SK_RX_RING_CNT; i++) { 2941 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2942 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2943 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2944 } 2945 } 2946 2947 for (i = 0; i < SK_TX_RING_CNT; i++) { 2948 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2949 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2950 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2951 } 2952 } 2953 2954 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2955 } 2956 2957 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2958 2959 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2960 2961 #ifdef SK_DEBUG 2962 void 2963 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2964 { 2965 #define DESC_PRINT(X) \ 2966 if (X) \ 2967 printf("txdesc[%d]." #X "=%#x\n", \ 2968 idx, X); 2969 2970 DESC_PRINT(le32toh(desc->sk_ctl)); 2971 DESC_PRINT(le32toh(desc->sk_next)); 2972 DESC_PRINT(le32toh(desc->sk_data_lo)); 2973 DESC_PRINT(le32toh(desc->sk_data_hi)); 2974 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2975 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2976 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2977 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2978 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2979 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2980 #undef PRINT 2981 } 2982 2983 void 2984 sk_dump_bytes(const char *data, int len) 2985 { 2986 int c, i, j; 2987 2988 for (i = 0; i < len; i += 16) { 2989 printf("%08x ", i); 2990 c = len - i; 2991 if (c > 16) c = 16; 2992 2993 for (j = 0; j < c; j++) { 2994 printf("%02x ", data[i + j] & 0xff); 2995 if ((j & 0xf) == 7 && j > 0) 2996 printf(" "); 2997 } 2998 2999 for (; j < 16; j++) 3000 printf(" "); 3001 printf(" "); 3002 3003 for (j = 0; j < c; j++) { 3004 int ch = data[i + j] & 0xff; 3005 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3006 } 3007 3008 printf("\n"); 3009 3010 if (c < 16) 3011 break; 3012 } 3013 } 3014 3015 void 3016 sk_dump_mbuf(struct mbuf *m) 3017 { 3018 int count = m->m_pkthdr.len; 3019 3020 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3021 3022 while (count > 0 && m) { 3023 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3024 m, m->m_data, m->m_len); 3025 sk_dump_bytes(mtod(m, char *), m->m_len); 3026 3027 count -= m->m_len; 3028 m = m->m_next; 3029 } 3030 } 3031 #endif 3032 3033 static int 3034 sk_sysctl_handler(SYSCTLFN_ARGS) 3035 { 3036 int error, t; 3037 struct sysctlnode node; 3038 struct sk_softc *sc; 3039 3040 node = *rnode; 3041 sc = node.sysctl_data; 3042 t = sc->sk_int_mod; 3043 node.sysctl_data = &t; 3044 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3045 if (error || newp == NULL) 3046 return error; 3047 3048 if (t < SK_IM_MIN || t > SK_IM_MAX) 3049 return EINVAL; 3050 3051 /* update the softc with sysctl-changed value, and mark 3052 for hardware update */ 3053 sc->sk_int_mod = t; 3054 sc->sk_int_mod_pending = 1; 3055 return 0; 3056 } 3057 3058 /* 3059 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3060 * set up in skc_attach() 3061 */ 3062 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3063 { 3064 int rc; 3065 const struct sysctlnode *node; 3066 3067 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3068 0, CTLTYPE_NODE, "hw", NULL, 3069 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3070 goto err; 3071 } 3072 3073 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3074 0, CTLTYPE_NODE, "sk", 3075 SYSCTL_DESCR("sk interface controls"), 3076 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3077 goto err; 3078 } 3079 3080 sk_root_num = node->sysctl_num; 3081 return; 3082 3083 err: 3084 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3085 } 3086
Indexes created Tue Sep 23 14:10:03 GMT 2025