if_sk.c revision 1.44.6.1
1 /* $NetBSD: if_sk.c,v 1.44.6.1 2007/12/13 21:55:50 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include <sys/cdefs.h> 125 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.44.6.1 2007/12/13 21:55:50 bouyer Exp $"); 126 127 #include "bpfilter.h" 128 #include "rnd.h" 129 130 #include <sys/param.h> 131 #include <sys/systm.h> 132 #include <sys/sockio.h> 133 #include <sys/mbuf.h> 134 #include <sys/malloc.h> 135 #include <sys/kernel.h> 136 #include <sys/socket.h> 137 #include <sys/device.h> 138 #include <sys/queue.h> 139 #include <sys/callout.h> 140 #include <sys/sysctl.h> 141 #include <sys/endian.h> 142 143 #include <net/if.h> 144 #include <net/if_dl.h> 145 #include <net/if_types.h> 146 147 #include <net/if_media.h> 148 149 #if NBPFILTER > 0 150 #include <net/bpf.h> 151 #endif 152 #if NRND > 0 153 #include <sys/rnd.h> 154 #endif 155 156 #include <dev/mii/mii.h> 157 #include <dev/mii/miivar.h> 158 #include <dev/mii/brgphyreg.h> 159 160 #include <dev/pci/pcireg.h> 161 #include <dev/pci/pcivar.h> 162 #include <dev/pci/pcidevs.h> 163 164 /* #define SK_USEIOSPACE */ 165 166 #include <dev/pci/if_skreg.h> 167 #include <dev/pci/if_skvar.h> 168 169 int skc_probe(struct device *, struct cfdata *, void *); 170 void skc_attach(struct device *, struct device *self, void *aux); 171 int sk_probe(struct device *, struct cfdata *, void *); 172 void sk_attach(struct device *, struct device *self, void *aux); 173 int skcprint(void *, const char *); 174 int sk_intr(void *); 175 void sk_intr_bcom(struct sk_if_softc *); 176 void sk_intr_xmac(struct sk_if_softc *); 177 void sk_intr_yukon(struct sk_if_softc *); 178 void sk_rxeof(struct sk_if_softc *); 179 void sk_txeof(struct sk_if_softc *); 180 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 181 void sk_start(struct ifnet *); 182 int sk_ioctl(struct ifnet *, u_long, void *); 183 int sk_init(struct ifnet *); 184 void sk_init_xmac(struct sk_if_softc *); 185 void sk_init_yukon(struct sk_if_softc *); 186 void sk_stop(struct ifnet *, int); 187 void sk_watchdog(struct ifnet *); 188 void sk_shutdown(void *); 189 int sk_ifmedia_upd(struct ifnet *); 190 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 191 void sk_reset(struct sk_softc *); 192 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 193 int sk_alloc_jumbo_mem(struct sk_if_softc *); 194 void sk_free_jumbo_mem(struct sk_if_softc *); 195 void *sk_jalloc(struct sk_if_softc *); 196 void sk_jfree(struct mbuf *, void *, size_t, void *); 197 int sk_init_rx_ring(struct sk_if_softc *); 198 int sk_init_tx_ring(struct sk_if_softc *); 199 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 200 void sk_vpd_read_res(struct sk_softc *, 201 struct vpd_res *, int); 202 void sk_vpd_read(struct sk_softc *); 203 204 void sk_update_int_mod(struct sk_softc *); 205 206 int sk_xmac_miibus_readreg(struct device *, int, int); 207 void sk_xmac_miibus_writereg(struct device *, int, int, int); 208 void sk_xmac_miibus_statchg(struct device *); 209 210 int sk_marv_miibus_readreg(struct device *, int, int); 211 void sk_marv_miibus_writereg(struct device *, int, int, int); 212 void sk_marv_miibus_statchg(struct device *); 213 214 u_int32_t sk_xmac_hash(void *); 215 u_int32_t sk_yukon_hash(void *); 216 void sk_setfilt(struct sk_if_softc *, void *, int); 217 void sk_setmulti(struct sk_if_softc *); 218 void sk_tick(void *); 219 220 /* #define SK_DEBUG 2 */ 221 #ifdef SK_DEBUG 222 #define DPRINTF(x) if (skdebug) printf x 223 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 224 int skdebug = SK_DEBUG; 225 226 void sk_dump_txdesc(struct sk_tx_desc *, int); 227 void sk_dump_mbuf(struct mbuf *); 228 void sk_dump_bytes(const char *, int); 229 #else 230 #define DPRINTF(x) 231 #define DPRINTFN(n,x) 232 #endif 233 234 static int sk_sysctl_handler(SYSCTLFN_PROTO); 235 static int sk_root_num; 236 237 /* supported device vendors */ 238 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 239 static const struct sk_product { 240 pci_vendor_id_t sk_vendor; 241 pci_product_id_t sk_product; 242 } sk_products[] = { 243 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 244 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 245 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 246 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 247 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 248 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 249 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 250 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 251 { 0, 0, } 252 }; 253 254 #define SK_LINKSYS_EG1032_SUBID 0x00151737 255 256 static inline u_int32_t 257 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 258 { 259 #ifdef SK_USEIOSPACE 260 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 261 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 262 #else 263 return CSR_READ_4(sc, reg); 264 #endif 265 } 266 267 static inline u_int16_t 268 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 269 { 270 #ifdef SK_USEIOSPACE 271 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 272 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 273 #else 274 return CSR_READ_2(sc, reg); 275 #endif 276 } 277 278 static inline u_int8_t 279 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 280 { 281 #ifdef SK_USEIOSPACE 282 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 283 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 284 #else 285 return CSR_READ_1(sc, reg); 286 #endif 287 } 288 289 static inline void 290 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 291 { 292 #ifdef SK_USEIOSPACE 293 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 294 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 295 #else 296 CSR_WRITE_4(sc, reg, x); 297 #endif 298 } 299 300 static inline void 301 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 302 { 303 #ifdef SK_USEIOSPACE 304 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 305 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 306 #else 307 CSR_WRITE_2(sc, reg, x); 308 #endif 309 } 310 311 static inline void 312 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 313 { 314 #ifdef SK_USEIOSPACE 315 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 316 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 317 #else 318 CSR_WRITE_1(sc, reg, x); 319 #endif 320 } 321 322 /* 323 * The VPD EEPROM contains Vital Product Data, as suggested in 324 * the PCI 2.1 specification. The VPD data is separared into areas 325 * denoted by resource IDs. The SysKonnect VPD contains an ID string 326 * resource (the name of the adapter), a read-only area resource 327 * containing various key/data fields and a read/write area which 328 * can be used to store asset management information or log messages. 329 * We read the ID string and read-only into buffers attached to 330 * the controller softc structure for later use. At the moment, 331 * we only use the ID string during sk_attach(). 332 */ 333 u_int8_t 334 sk_vpd_readbyte(struct sk_softc *sc, int addr) 335 { 336 int i; 337 338 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 339 for (i = 0; i < SK_TIMEOUT; i++) { 340 DELAY(1); 341 if (sk_win_read_2(sc, 342 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 343 break; 344 } 345 346 if (i == SK_TIMEOUT) 347 return 0; 348 349 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 350 } 351 352 void 353 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 354 { 355 int i; 356 u_int8_t *ptr; 357 358 ptr = (u_int8_t *)res; 359 for (i = 0; i < sizeof(struct vpd_res); i++) 360 ptr[i] = sk_vpd_readbyte(sc, i + addr); 361 } 362 363 void 364 sk_vpd_read(struct sk_softc *sc) 365 { 366 int pos = 0, i; 367 struct vpd_res res; 368 369 if (sc->sk_vpd_prodname != NULL) 370 free(sc->sk_vpd_prodname, M_DEVBUF); 371 if (sc->sk_vpd_readonly != NULL) 372 free(sc->sk_vpd_readonly, M_DEVBUF); 373 sc->sk_vpd_prodname = NULL; 374 sc->sk_vpd_readonly = NULL; 375 376 sk_vpd_read_res(sc, &res, pos); 377 378 if (res.vr_id != VPD_RES_ID) { 379 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 380 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 381 return; 382 } 383 384 pos += sizeof(res); 385 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 386 if (sc->sk_vpd_prodname == NULL) 387 panic("sk_vpd_read"); 388 for (i = 0; i < res.vr_len; i++) 389 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 390 sc->sk_vpd_prodname[i] = '\0'; 391 pos += i; 392 393 sk_vpd_read_res(sc, &res, pos); 394 395 if (res.vr_id != VPD_RES_READ) { 396 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 397 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 398 return; 399 } 400 401 pos += sizeof(res); 402 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 403 if (sc->sk_vpd_readonly == NULL) 404 panic("sk_vpd_read"); 405 for (i = 0; i < res.vr_len ; i++) 406 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 407 } 408 409 int 410 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 411 { 412 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 413 int i; 414 415 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 416 417 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 418 return 0; 419 420 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 421 SK_XM_READ_2(sc_if, XM_PHY_DATA); 422 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 423 for (i = 0; i < SK_TIMEOUT; i++) { 424 DELAY(1); 425 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 426 XM_MMUCMD_PHYDATARDY) 427 break; 428 } 429 430 if (i == SK_TIMEOUT) { 431 aprint_error("%s: phy failed to come ready\n", 432 sc_if->sk_dev.dv_xname); 433 return 0; 434 } 435 } 436 DELAY(1); 437 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 438 } 439 440 void 441 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 442 { 443 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 444 int i; 445 446 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 447 448 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 449 for (i = 0; i < SK_TIMEOUT; i++) { 450 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 451 break; 452 } 453 454 if (i == SK_TIMEOUT) { 455 aprint_error("%s: phy failed to come ready\n", 456 sc_if->sk_dev.dv_xname); 457 return; 458 } 459 460 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 461 for (i = 0; i < SK_TIMEOUT; i++) { 462 DELAY(1); 463 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 464 break; 465 } 466 467 if (i == SK_TIMEOUT) 468 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 469 } 470 471 void 472 sk_xmac_miibus_statchg(struct device *dev) 473 { 474 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 475 struct mii_data *mii = &sc_if->sk_mii; 476 477 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 478 479 /* 480 * If this is a GMII PHY, manually set the XMAC's 481 * duplex mode accordingly. 482 */ 483 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 484 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 485 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 486 else 487 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 488 } 489 } 490 491 int 492 sk_marv_miibus_readreg(struct device *dev, int phy, int reg) 493 { 494 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 495 u_int16_t val; 496 int i; 497 498 if (phy != 0 || 499 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 500 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 501 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 502 phy, reg)); 503 return 0; 504 } 505 506 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 507 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 508 509 for (i = 0; i < SK_TIMEOUT; i++) { 510 DELAY(1); 511 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 512 if (val & YU_SMICR_READ_VALID) 513 break; 514 } 515 516 if (i == SK_TIMEOUT) { 517 aprint_error("%s: phy failed to come ready\n", 518 sc_if->sk_dev.dv_xname); 519 return 0; 520 } 521 522 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 523 SK_TIMEOUT)); 524 525 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 526 527 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 528 phy, reg, val)); 529 530 return val; 531 } 532 533 void 534 sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 535 { 536 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 537 int i; 538 539 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 540 phy, reg, val)); 541 542 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 543 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 544 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 545 546 for (i = 0; i < SK_TIMEOUT; i++) { 547 DELAY(1); 548 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 549 break; 550 } 551 552 if (i == SK_TIMEOUT) 553 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 554 } 555 556 void 557 sk_marv_miibus_statchg(struct device *dev) 558 { 559 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 560 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 561 } 562 563 #define SK_HASH_BITS 6 564 565 u_int32_t 566 sk_xmac_hash(void *addr) 567 { 568 u_int32_t crc; 569 570 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 571 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 572 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 573 return crc; 574 } 575 576 u_int32_t 577 sk_yukon_hash(void *addr) 578 { 579 u_int32_t crc; 580 581 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 582 crc &= ((1 << SK_HASH_BITS) - 1); 583 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 584 return crc; 585 } 586 587 void 588 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 589 { 590 char *addr = addrv; 591 int base = XM_RXFILT_ENTRY(slot); 592 593 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 594 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 595 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 596 } 597 598 void 599 sk_setmulti(struct sk_if_softc *sc_if) 600 { 601 struct sk_softc *sc = sc_if->sk_softc; 602 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 603 u_int32_t hashes[2] = { 0, 0 }; 604 int h = 0, i; 605 struct ethercom *ec = &sc_if->sk_ethercom; 606 struct ether_multi *enm; 607 struct ether_multistep step; 608 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 609 610 /* First, zot all the existing filters. */ 611 switch (sc->sk_type) { 612 case SK_GENESIS: 613 for (i = 1; i < XM_RXFILT_MAX; i++) 614 sk_setfilt(sc_if, (void *)&dummy, i); 615 616 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 617 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 618 break; 619 case SK_YUKON: 620 case SK_YUKON_LITE: 621 case SK_YUKON_LP: 622 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 623 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 624 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 625 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 626 break; 627 } 628 629 /* Now program new ones. */ 630 allmulti: 631 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 632 hashes[0] = 0xFFFFFFFF; 633 hashes[1] = 0xFFFFFFFF; 634 } else { 635 i = 1; 636 /* First find the tail of the list. */ 637 ETHER_FIRST_MULTI(step, ec, enm); 638 while (enm != NULL) { 639 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 640 ETHER_ADDR_LEN)) { 641 ifp->if_flags |= IFF_ALLMULTI; 642 goto allmulti; 643 } 644 DPRINTFN(2,("multicast address %s\n", 645 ether_sprintf(enm->enm_addrlo))); 646 /* 647 * Program the first XM_RXFILT_MAX multicast groups 648 * into the perfect filter. For all others, 649 * use the hash table. 650 */ 651 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 652 sk_setfilt(sc_if, enm->enm_addrlo, i); 653 i++; 654 } 655 else { 656 switch (sc->sk_type) { 657 case SK_GENESIS: 658 h = sk_xmac_hash(enm->enm_addrlo); 659 break; 660 case SK_YUKON: 661 case SK_YUKON_LITE: 662 case SK_YUKON_LP: 663 h = sk_yukon_hash(enm->enm_addrlo); 664 break; 665 } 666 if (h < 32) 667 hashes[0] |= (1 << h); 668 else 669 hashes[1] |= (1 << (h - 32)); 670 } 671 672 ETHER_NEXT_MULTI(step, enm); 673 } 674 } 675 676 switch (sc->sk_type) { 677 case SK_GENESIS: 678 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 679 XM_MODE_RX_USE_PERFECT); 680 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 681 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 682 break; 683 case SK_YUKON: 684 case SK_YUKON_LITE: 685 case SK_YUKON_LP: 686 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 687 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 688 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 689 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 690 break; 691 } 692 } 693 694 int 695 sk_init_rx_ring(struct sk_if_softc *sc_if) 696 { 697 struct sk_chain_data *cd = &sc_if->sk_cdata; 698 struct sk_ring_data *rd = sc_if->sk_rdata; 699 int i; 700 701 bzero((char *)rd->sk_rx_ring, 702 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 703 704 for (i = 0; i < SK_RX_RING_CNT; i++) { 705 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 706 if (i == (SK_RX_RING_CNT - 1)) { 707 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 708 rd->sk_rx_ring[i].sk_next = 709 htole32(SK_RX_RING_ADDR(sc_if, 0)); 710 } else { 711 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 712 rd->sk_rx_ring[i].sk_next = 713 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 714 } 715 } 716 717 for (i = 0; i < SK_RX_RING_CNT; i++) { 718 if (sk_newbuf(sc_if, i, NULL, 719 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 720 aprint_error("%s: failed alloc of %dth mbuf\n", 721 sc_if->sk_dev.dv_xname, i); 722 return ENOBUFS; 723 } 724 } 725 sc_if->sk_cdata.sk_rx_prod = 0; 726 sc_if->sk_cdata.sk_rx_cons = 0; 727 728 return 0; 729 } 730 731 int 732 sk_init_tx_ring(struct sk_if_softc *sc_if) 733 { 734 struct sk_chain_data *cd = &sc_if->sk_cdata; 735 struct sk_ring_data *rd = sc_if->sk_rdata; 736 int i; 737 738 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 739 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 740 741 for (i = 0; i < SK_TX_RING_CNT; i++) { 742 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 743 if (i == (SK_TX_RING_CNT - 1)) { 744 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 745 rd->sk_tx_ring[i].sk_next = 746 htole32(SK_TX_RING_ADDR(sc_if, 0)); 747 } else { 748 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 749 rd->sk_tx_ring[i].sk_next = 750 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 751 } 752 } 753 754 sc_if->sk_cdata.sk_tx_prod = 0; 755 sc_if->sk_cdata.sk_tx_cons = 0; 756 sc_if->sk_cdata.sk_tx_cnt = 0; 757 758 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 759 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 760 761 return 0; 762 } 763 764 int 765 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 766 bus_dmamap_t dmamap) 767 { 768 struct mbuf *m_new = NULL; 769 struct sk_chain *c; 770 struct sk_rx_desc *r; 771 772 if (m == NULL) { 773 void *buf = NULL; 774 775 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 776 if (m_new == NULL) { 777 aprint_error("%s: no memory for rx list -- " 778 "packet dropped!\n", sc_if->sk_dev.dv_xname); 779 return ENOBUFS; 780 } 781 782 /* Allocate the jumbo buffer */ 783 buf = sk_jalloc(sc_if); 784 if (buf == NULL) { 785 m_freem(m_new); 786 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 787 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 788 return ENOBUFS; 789 } 790 791 /* Attach the buffer to the mbuf */ 792 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 793 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 794 795 } else { 796 /* 797 * We're re-using a previously allocated mbuf; 798 * be sure to re-init pointers and lengths to 799 * default values. 800 */ 801 m_new = m; 802 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 803 m_new->m_data = m_new->m_ext.ext_buf; 804 } 805 m_adj(m_new, ETHER_ALIGN); 806 807 c = &sc_if->sk_cdata.sk_rx_chain[i]; 808 r = c->sk_desc; 809 c->sk_mbuf = m_new; 810 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 811 (((vaddr_t)m_new->m_data 812 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 813 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 814 815 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 816 817 return 0; 818 } 819 820 /* 821 * Memory management for jumbo frames. 822 */ 823 824 int 825 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 826 { 827 struct sk_softc *sc = sc_if->sk_softc; 828 char *ptr, *kva; 829 bus_dma_segment_t seg; 830 int i, rseg, state, error; 831 struct sk_jpool_entry *entry; 832 833 state = error = 0; 834 835 /* Grab a big chunk o' storage. */ 836 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 837 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 838 aprint_error("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 839 return ENOBUFS; 840 } 841 842 state = 1; 843 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 844 BUS_DMA_NOWAIT)) { 845 aprint_error("%s: can't map dma buffers (%d bytes)\n", 846 sc->sk_dev.dv_xname, SK_JMEM); 847 error = ENOBUFS; 848 goto out; 849 } 850 851 state = 2; 852 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 853 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 854 aprint_error("%s: can't create dma map\n", sc->sk_dev.dv_xname); 855 error = ENOBUFS; 856 goto out; 857 } 858 859 state = 3; 860 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 861 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 862 aprint_error("%s: can't load dma map\n", sc->sk_dev.dv_xname); 863 error = ENOBUFS; 864 goto out; 865 } 866 867 state = 4; 868 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 869 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 870 871 LIST_INIT(&sc_if->sk_jfree_listhead); 872 LIST_INIT(&sc_if->sk_jinuse_listhead); 873 874 /* 875 * Now divide it up into 9K pieces and save the addresses 876 * in an array. 877 */ 878 ptr = sc_if->sk_cdata.sk_jumbo_buf; 879 for (i = 0; i < SK_JSLOTS; i++) { 880 sc_if->sk_cdata.sk_jslots[i] = ptr; 881 ptr += SK_JLEN; 882 entry = malloc(sizeof(struct sk_jpool_entry), 883 M_DEVBUF, M_NOWAIT); 884 if (entry == NULL) { 885 aprint_error("%s: no memory for jumbo buffer queue!\n", 886 sc->sk_dev.dv_xname); 887 error = ENOBUFS; 888 goto out; 889 } 890 entry->slot = i; 891 if (i) 892 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 893 entry, jpool_entries); 894 else 895 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 896 entry, jpool_entries); 897 } 898 out: 899 if (error != 0) { 900 switch (state) { 901 case 4: 902 bus_dmamap_unload(sc->sc_dmatag, 903 sc_if->sk_cdata.sk_rx_jumbo_map); 904 case 3: 905 bus_dmamap_destroy(sc->sc_dmatag, 906 sc_if->sk_cdata.sk_rx_jumbo_map); 907 case 2: 908 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 909 case 1: 910 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 911 break; 912 default: 913 break; 914 } 915 } 916 917 return error; 918 } 919 920 /* 921 * Allocate a jumbo buffer. 922 */ 923 void * 924 sk_jalloc(struct sk_if_softc *sc_if) 925 { 926 struct sk_jpool_entry *entry; 927 928 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 929 930 if (entry == NULL) 931 return NULL; 932 933 LIST_REMOVE(entry, jpool_entries); 934 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 935 return sc_if->sk_cdata.sk_jslots[entry->slot]; 936 } 937 938 /* 939 * Release a jumbo buffer. 940 */ 941 void 942 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 943 { 944 struct sk_jpool_entry *entry; 945 struct sk_if_softc *sc; 946 int i, s; 947 948 /* Extract the softc struct pointer. */ 949 sc = (struct sk_if_softc *)arg; 950 951 if (sc == NULL) 952 panic("sk_jfree: can't find softc pointer!"); 953 954 /* calculate the slot this buffer belongs to */ 955 956 i = ((vaddr_t)buf 957 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 958 959 if ((i < 0) || (i >= SK_JSLOTS)) 960 panic("sk_jfree: asked to free buffer that we don't manage!"); 961 962 s = splvm(); 963 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 964 if (entry == NULL) 965 panic("sk_jfree: buffer not in use!"); 966 entry->slot = i; 967 LIST_REMOVE(entry, jpool_entries); 968 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 969 970 if (__predict_true(m != NULL)) 971 pool_cache_put(mb_cache, m); 972 splx(s); 973 } 974 975 /* 976 * Set media options. 977 */ 978 int 979 sk_ifmedia_upd(struct ifnet *ifp) 980 { 981 struct sk_if_softc *sc_if = ifp->if_softc; 982 983 (void) sk_init(ifp); 984 mii_mediachg(&sc_if->sk_mii); 985 return 0; 986 } 987 988 /* 989 * Report current media status. 990 */ 991 void 992 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 993 { 994 struct sk_if_softc *sc_if = ifp->if_softc; 995 996 mii_pollstat(&sc_if->sk_mii); 997 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 998 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 999 } 1000 1001 int 1002 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 1003 { 1004 struct sk_if_softc *sc_if = ifp->if_softc; 1005 struct sk_softc *sc = sc_if->sk_softc; 1006 struct ifreq *ifr = (struct ifreq *) data; 1007 struct mii_data *mii; 1008 int s, error = 0; 1009 1010 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1011 1012 s = splnet(); 1013 1014 switch (command) { 1015 1016 case SIOCSIFFLAGS: 1017 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1018 if (ifp->if_flags & IFF_UP) { 1019 if (ifp->if_flags & IFF_RUNNING && 1020 ifp->if_flags & IFF_PROMISC && 1021 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1022 switch (sc->sk_type) { 1023 case SK_GENESIS: 1024 SK_XM_SETBIT_4(sc_if, XM_MODE, 1025 XM_MODE_RX_PROMISC); 1026 break; 1027 case SK_YUKON: 1028 case SK_YUKON_LITE: 1029 case SK_YUKON_LP: 1030 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1031 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1032 break; 1033 } 1034 sk_setmulti(sc_if); 1035 } else if (ifp->if_flags & IFF_RUNNING && 1036 !(ifp->if_flags & IFF_PROMISC) && 1037 sc_if->sk_if_flags & IFF_PROMISC) { 1038 switch (sc->sk_type) { 1039 case SK_GENESIS: 1040 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1041 XM_MODE_RX_PROMISC); 1042 break; 1043 case SK_YUKON: 1044 case SK_YUKON_LITE: 1045 case SK_YUKON_LP: 1046 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1047 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1048 break; 1049 } 1050 1051 sk_setmulti(sc_if); 1052 } else 1053 (void) sk_init(ifp); 1054 } else { 1055 if (ifp->if_flags & IFF_RUNNING) 1056 sk_stop(ifp,0); 1057 } 1058 sc_if->sk_if_flags = ifp->if_flags; 1059 error = 0; 1060 break; 1061 1062 case SIOCGIFMEDIA: 1063 case SIOCSIFMEDIA: 1064 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 1065 mii = &sc_if->sk_mii; 1066 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1067 break; 1068 default: 1069 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1070 error = ether_ioctl(ifp, command, data); 1071 1072 if ( error == ENETRESET) { 1073 if (ifp->if_flags & IFF_RUNNING) { 1074 sk_setmulti(sc_if); 1075 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1076 } 1077 error = 0; 1078 } else if ( error ) { 1079 splx(s); 1080 return error; 1081 } 1082 break; 1083 } 1084 1085 splx(s); 1086 return error; 1087 } 1088 1089 void 1090 sk_update_int_mod(struct sk_softc *sc) 1091 { 1092 u_int32_t imtimer_ticks; 1093 1094 /* 1095 * Configure interrupt moderation. The moderation timer 1096 * defers interrupts specified in the interrupt moderation 1097 * timer mask based on the timeout specified in the interrupt 1098 * moderation timer init register. Each bit in the timer 1099 * register represents one tick, so to specify a timeout in 1100 * microseconds, we have to multiply by the correct number of 1101 * ticks-per-microsecond. 1102 */ 1103 switch (sc->sk_type) { 1104 case SK_GENESIS: 1105 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1106 break; 1107 case SK_YUKON_EC: 1108 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1109 break; 1110 default: 1111 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1112 } 1113 aprint_verbose("%s: interrupt moderation is %d us\n", 1114 sc->sk_dev.dv_xname, sc->sk_int_mod); 1115 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1116 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1117 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1118 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1119 sc->sk_int_mod_pending = 0; 1120 } 1121 1122 /* 1123 * Lookup: Check the PCI vendor and device, and return a pointer to 1124 * The structure if the IDs match against our list. 1125 */ 1126 1127 static const struct sk_product * 1128 sk_lookup(const struct pci_attach_args *pa) 1129 { 1130 const struct sk_product *psk; 1131 1132 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1133 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1134 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1135 return psk; 1136 } 1137 return NULL; 1138 } 1139 1140 /* 1141 * Probe for a SysKonnect GEnesis chip. 1142 */ 1143 1144 int 1145 skc_probe(struct device *parent, struct cfdata *match, 1146 void *aux) 1147 { 1148 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1149 const struct sk_product *psk; 1150 pcireg_t subid; 1151 1152 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1153 1154 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1155 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1156 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1157 subid == SK_LINKSYS_EG1032_SUBID) 1158 return 1; 1159 1160 if ((psk = sk_lookup(pa))) { 1161 return 1; 1162 } 1163 return 0; 1164 } 1165 1166 /* 1167 * Force the GEnesis into reset, then bring it out of reset. 1168 */ 1169 void sk_reset(struct sk_softc *sc) 1170 { 1171 DPRINTFN(2, ("sk_reset\n")); 1172 1173 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1174 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1175 if (SK_YUKON_FAMILY(sc->sk_type)) 1176 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1177 1178 DELAY(1000); 1179 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1180 DELAY(2); 1181 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1182 if (SK_YUKON_FAMILY(sc->sk_type)) 1183 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1184 1185 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1186 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1187 CSR_READ_2(sc, SK_LINK_CTRL))); 1188 1189 if (sc->sk_type == SK_GENESIS) { 1190 /* Configure packet arbiter */ 1191 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1192 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1193 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1194 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1195 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1196 } 1197 1198 /* Enable RAM interface */ 1199 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1200 1201 sk_update_int_mod(sc); 1202 } 1203 1204 int 1205 sk_probe(struct device *parent, struct cfdata *match, 1206 void *aux) 1207 { 1208 struct skc_attach_args *sa = aux; 1209 1210 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1211 return 0; 1212 1213 return 1; 1214 } 1215 1216 /* 1217 * Each XMAC chip is attached as a separate logical IP interface. 1218 * Single port cards will have only one logical interface of course. 1219 */ 1220 void 1221 sk_attach(struct device *parent, struct device *self, void *aux) 1222 { 1223 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1224 struct sk_softc *sc = (struct sk_softc *)parent; 1225 struct skc_attach_args *sa = aux; 1226 struct sk_txmap_entry *entry; 1227 struct ifnet *ifp; 1228 bus_dma_segment_t seg; 1229 bus_dmamap_t dmamap; 1230 void *kva; 1231 int i, rseg; 1232 1233 aprint_naive("\n"); 1234 1235 sc_if->sk_port = sa->skc_port; 1236 sc_if->sk_softc = sc; 1237 sc->sk_if[sa->skc_port] = sc_if; 1238 1239 if (sa->skc_port == SK_PORT_A) 1240 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1241 if (sa->skc_port == SK_PORT_B) 1242 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1243 1244 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1245 1246 /* 1247 * Get station address for this interface. Note that 1248 * dual port cards actually come with three station 1249 * addresses: one for each port, plus an extra. The 1250 * extra one is used by the SysKonnect driver software 1251 * as a 'virtual' station address for when both ports 1252 * are operating in failover mode. Currently we don't 1253 * use this extra address. 1254 */ 1255 for (i = 0; i < ETHER_ADDR_LEN; i++) 1256 sc_if->sk_enaddr[i] = 1257 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1258 1259 1260 aprint_normal(": Ethernet address %s\n", 1261 ether_sprintf(sc_if->sk_enaddr)); 1262 1263 /* 1264 * Set up RAM buffer addresses. The NIC will have a certain 1265 * amount of SRAM on it, somewhere between 512K and 2MB. We 1266 * need to divide this up a) between the transmitter and 1267 * receiver and b) between the two XMACs, if this is a 1268 * dual port NIC. Our algorithm is to divide up the memory 1269 * evenly so that everyone gets a fair share. 1270 */ 1271 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1272 u_int32_t chunk, val; 1273 1274 chunk = sc->sk_ramsize / 2; 1275 val = sc->sk_rboff / sizeof(u_int64_t); 1276 sc_if->sk_rx_ramstart = val; 1277 val += (chunk / sizeof(u_int64_t)); 1278 sc_if->sk_rx_ramend = val - 1; 1279 sc_if->sk_tx_ramstart = val; 1280 val += (chunk / sizeof(u_int64_t)); 1281 sc_if->sk_tx_ramend = val - 1; 1282 } else { 1283 u_int32_t chunk, val; 1284 1285 chunk = sc->sk_ramsize / 4; 1286 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1287 sizeof(u_int64_t); 1288 sc_if->sk_rx_ramstart = val; 1289 val += (chunk / sizeof(u_int64_t)); 1290 sc_if->sk_rx_ramend = val - 1; 1291 sc_if->sk_tx_ramstart = val; 1292 val += (chunk / sizeof(u_int64_t)); 1293 sc_if->sk_tx_ramend = val - 1; 1294 } 1295 1296 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1297 " tx_ramstart=%#x tx_ramend=%#x\n", 1298 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1299 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1300 1301 /* Read and save PHY type and set PHY address */ 1302 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1303 switch (sc_if->sk_phytype) { 1304 case SK_PHYTYPE_XMAC: 1305 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1306 break; 1307 case SK_PHYTYPE_BCOM: 1308 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1309 break; 1310 case SK_PHYTYPE_MARV_COPPER: 1311 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1312 break; 1313 default: 1314 aprint_error("%s: unsupported PHY type: %d\n", 1315 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1316 return; 1317 } 1318 1319 /* Allocate the descriptor queues. */ 1320 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1321 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1322 aprint_error("%s: can't alloc rx buffers\n", 1323 sc->sk_dev.dv_xname); 1324 goto fail; 1325 } 1326 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1327 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1328 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1329 sc_if->sk_dev.dv_xname, 1330 (u_long) sizeof(struct sk_ring_data)); 1331 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1332 goto fail; 1333 } 1334 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1335 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1336 &sc_if->sk_ring_map)) { 1337 aprint_error("%s: can't create dma map\n", 1338 sc_if->sk_dev.dv_xname); 1339 bus_dmamem_unmap(sc->sc_dmatag, kva, 1340 sizeof(struct sk_ring_data)); 1341 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1342 goto fail; 1343 } 1344 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1345 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1346 aprint_error("%s: can't load dma map\n", 1347 sc_if->sk_dev.dv_xname); 1348 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1349 bus_dmamem_unmap(sc->sc_dmatag, kva, 1350 sizeof(struct sk_ring_data)); 1351 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1352 goto fail; 1353 } 1354 1355 for (i = 0; i < SK_RX_RING_CNT; i++) 1356 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1357 1358 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1359 for (i = 0; i < SK_TX_RING_CNT; i++) { 1360 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1361 1362 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1363 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1364 aprint_error("%s: Can't create TX dmamap\n", 1365 sc_if->sk_dev.dv_xname); 1366 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1367 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1368 bus_dmamem_unmap(sc->sc_dmatag, kva, 1369 sizeof(struct sk_ring_data)); 1370 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1371 goto fail; 1372 } 1373 1374 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1375 if (!entry) { 1376 aprint_error("%s: Can't alloc txmap entry\n", 1377 sc_if->sk_dev.dv_xname); 1378 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1379 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1380 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1381 bus_dmamem_unmap(sc->sc_dmatag, kva, 1382 sizeof(struct sk_ring_data)); 1383 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1384 goto fail; 1385 } 1386 entry->dmamap = dmamap; 1387 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1388 } 1389 1390 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1391 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1392 1393 ifp = &sc_if->sk_ethercom.ec_if; 1394 /* Try to allocate memory for jumbo buffers. */ 1395 if (sk_alloc_jumbo_mem(sc_if)) { 1396 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1397 goto fail; 1398 } 1399 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1400 | ETHERCAP_JUMBO_MTU; 1401 1402 ifp->if_softc = sc_if; 1403 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1404 ifp->if_ioctl = sk_ioctl; 1405 ifp->if_start = sk_start; 1406 ifp->if_stop = sk_stop; 1407 ifp->if_init = sk_init; 1408 ifp->if_watchdog = sk_watchdog; 1409 ifp->if_capabilities = 0; 1410 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1411 IFQ_SET_READY(&ifp->if_snd); 1412 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1413 1414 /* 1415 * Do miibus setup. 1416 */ 1417 switch (sc->sk_type) { 1418 case SK_GENESIS: 1419 sk_init_xmac(sc_if); 1420 break; 1421 case SK_YUKON: 1422 case SK_YUKON_LITE: 1423 case SK_YUKON_LP: 1424 sk_init_yukon(sc_if); 1425 break; 1426 default: 1427 aprint_error("%s: unknown device type %d\n", 1428 sc->sk_dev.dv_xname, sc->sk_type); 1429 goto fail; 1430 } 1431 1432 DPRINTFN(2, ("sk_attach: 1\n")); 1433 1434 sc_if->sk_mii.mii_ifp = ifp; 1435 switch (sc->sk_type) { 1436 case SK_GENESIS: 1437 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1438 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1439 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1440 break; 1441 case SK_YUKON: 1442 case SK_YUKON_LITE: 1443 case SK_YUKON_LP: 1444 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1445 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1446 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1447 break; 1448 } 1449 1450 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1451 sk_ifmedia_upd, sk_ifmedia_sts); 1452 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1453 MII_OFFSET_ANY, 0); 1454 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1455 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1456 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1457 0, NULL); 1458 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1459 } else 1460 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1461 1462 callout_init(&sc_if->sk_tick_ch, 0); 1463 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1464 1465 DPRINTFN(2, ("sk_attach: 1\n")); 1466 1467 /* 1468 * Call MI attach routines. 1469 */ 1470 if_attach(ifp); 1471 1472 ether_ifattach(ifp, sc_if->sk_enaddr); 1473 1474 #if NRND > 0 1475 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1476 RND_TYPE_NET, 0); 1477 #endif 1478 1479 DPRINTFN(2, ("sk_attach: end\n")); 1480 1481 return; 1482 1483 fail: 1484 sc->sk_if[sa->skc_port] = NULL; 1485 } 1486 1487 int 1488 skcprint(void *aux, const char *pnp) 1489 { 1490 struct skc_attach_args *sa = aux; 1491 1492 if (pnp) 1493 aprint_normal("sk port %c at %s", 1494 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1495 else 1496 aprint_normal(" port %c", 1497 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1498 return UNCONF; 1499 } 1500 1501 /* 1502 * Attach the interface. Allocate softc structures, do ifmedia 1503 * setup and ethernet/BPF attach. 1504 */ 1505 void 1506 skc_attach(struct device *parent, struct device *self, void *aux) 1507 { 1508 struct sk_softc *sc = (struct sk_softc *)self; 1509 struct pci_attach_args *pa = aux; 1510 struct skc_attach_args skca; 1511 pci_chipset_tag_t pc = pa->pa_pc; 1512 #ifndef SK_USEIOSPACE 1513 pcireg_t memtype; 1514 #endif 1515 pci_intr_handle_t ih; 1516 const char *intrstr = NULL; 1517 bus_addr_t iobase; 1518 bus_size_t iosize; 1519 int rc, sk_nodenum; 1520 u_int32_t command; 1521 const char *revstr; 1522 const struct sysctlnode *node; 1523 1524 aprint_naive("\n"); 1525 1526 DPRINTFN(2, ("begin skc_attach\n")); 1527 1528 /* 1529 * Handle power management nonsense. 1530 */ 1531 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1532 1533 if (command == 0x01) { 1534 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1535 if (command & SK_PSTATE_MASK) { 1536 u_int32_t xiobase, membase, irq; 1537 1538 /* Save important PCI config data. */ 1539 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1540 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1541 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1542 1543 /* Reset the power state. */ 1544 aprint_normal("%s chip is in D%d power mode " 1545 "-- setting to D0\n", sc->sk_dev.dv_xname, 1546 command & SK_PSTATE_MASK); 1547 command &= 0xFFFFFFFC; 1548 pci_conf_write(pc, pa->pa_tag, 1549 SK_PCI_PWRMGMTCTRL, command); 1550 1551 /* Restore PCI config data. */ 1552 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1553 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1554 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1555 } 1556 } 1557 1558 /* 1559 * Map control/status registers. 1560 */ 1561 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1562 command |= PCI_COMMAND_IO_ENABLE | 1563 PCI_COMMAND_MEM_ENABLE | 1564 PCI_COMMAND_MASTER_ENABLE; 1565 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1566 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1567 1568 #ifdef SK_USEIOSPACE 1569 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1570 aprint_error(": failed to enable I/O ports!\n"); 1571 return; 1572 } 1573 /* 1574 * Map control/status registers. 1575 */ 1576 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1577 &sc->sk_btag, &sc->sk_bhandle, 1578 &iobase, &iosize)) { 1579 aprint_error(": can't find i/o space\n"); 1580 return; 1581 } 1582 #else 1583 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1584 aprint_error(": failed to enable memory mapping!\n"); 1585 return; 1586 } 1587 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1588 switch (memtype) { 1589 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1590 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1591 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1592 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1593 &iobase, &iosize) == 0) 1594 break; 1595 default: 1596 aprint_error("%s: can't find mem space\n", 1597 sc->sk_dev.dv_xname); 1598 return; 1599 } 1600 1601 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1602 #endif 1603 sc->sc_dmatag = pa->pa_dmat; 1604 1605 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1606 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1607 1608 /* bail out here if chip is not recognized */ 1609 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1610 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1611 goto fail; 1612 } 1613 if (SK_IS_YUKON2(sc)) { 1614 aprint_error("%s: Does not support Yukon2--try msk(4).\n", 1615 sc->sk_dev.dv_xname); 1616 goto fail; 1617 } 1618 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1619 1620 /* Allocate interrupt */ 1621 if (pci_intr_map(pa, &ih)) { 1622 aprint_error(": couldn't map interrupt\n"); 1623 goto fail; 1624 } 1625 1626 intrstr = pci_intr_string(pc, ih); 1627 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1628 if (sc->sk_intrhand == NULL) { 1629 aprint_error(": couldn't establish interrupt"); 1630 if (intrstr != NULL) 1631 aprint_normal(" at %s", intrstr); 1632 goto fail; 1633 } 1634 aprint_normal(": %s\n", intrstr); 1635 1636 /* Reset the adapter. */ 1637 sk_reset(sc); 1638 1639 /* Read and save vital product data from EEPROM. */ 1640 sk_vpd_read(sc); 1641 1642 if (sc->sk_type == SK_GENESIS) { 1643 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1644 /* Read and save RAM size and RAMbuffer offset */ 1645 switch (val) { 1646 case SK_RAMSIZE_512K_64: 1647 sc->sk_ramsize = 0x80000; 1648 sc->sk_rboff = SK_RBOFF_0; 1649 break; 1650 case SK_RAMSIZE_1024K_64: 1651 sc->sk_ramsize = 0x100000; 1652 sc->sk_rboff = SK_RBOFF_80000; 1653 break; 1654 case SK_RAMSIZE_1024K_128: 1655 sc->sk_ramsize = 0x100000; 1656 sc->sk_rboff = SK_RBOFF_0; 1657 break; 1658 case SK_RAMSIZE_2048K_128: 1659 sc->sk_ramsize = 0x200000; 1660 sc->sk_rboff = SK_RBOFF_0; 1661 break; 1662 default: 1663 aprint_error("%s: unknown ram size: %d\n", 1664 sc->sk_dev.dv_xname, val); 1665 goto fail_1; 1666 break; 1667 } 1668 1669 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1670 sc->sk_ramsize, sc->sk_ramsize / 1024, 1671 sc->sk_rboff)); 1672 } else { 1673 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1674 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1675 sc->sk_rboff = SK_RBOFF_0; 1676 1677 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1678 sc->sk_ramsize / 1024, sc->sk_ramsize, 1679 sc->sk_rboff)); 1680 } 1681 1682 /* Read and save physical media type */ 1683 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1684 case SK_PMD_1000BASESX: 1685 sc->sk_pmd = IFM_1000_SX; 1686 break; 1687 case SK_PMD_1000BASELX: 1688 sc->sk_pmd = IFM_1000_LX; 1689 break; 1690 case SK_PMD_1000BASECX: 1691 sc->sk_pmd = IFM_1000_CX; 1692 break; 1693 case SK_PMD_1000BASETX: 1694 case SK_PMD_1000BASETX_ALT: 1695 sc->sk_pmd = IFM_1000_T; 1696 break; 1697 default: 1698 aprint_error("%s: unknown media type: 0x%x\n", 1699 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1700 goto fail_1; 1701 } 1702 1703 /* determine whether to name it with vpd or just make it up */ 1704 /* Marvell Yukon VPD's can freqently be bogus */ 1705 1706 switch (pa->pa_id) { 1707 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1708 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1709 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1710 case PCI_PRODUCT_3COM_3C940: 1711 case PCI_PRODUCT_DLINK_DGE530T: 1712 case PCI_PRODUCT_DLINK_DGE560T: 1713 case PCI_PRODUCT_DLINK_DGE560T_2: 1714 case PCI_PRODUCT_LINKSYS_EG1032: 1715 case PCI_PRODUCT_LINKSYS_EG1064: 1716 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1717 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1718 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1719 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1720 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1721 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1722 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1723 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1724 sc->sk_name = sc->sk_vpd_prodname; 1725 break; 1726 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1727 /* whoops yukon vpd prodname bears no resemblance to reality */ 1728 switch (sc->sk_type) { 1729 case SK_GENESIS: 1730 sc->sk_name = sc->sk_vpd_prodname; 1731 break; 1732 case SK_YUKON: 1733 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1734 break; 1735 case SK_YUKON_LITE: 1736 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1737 break; 1738 case SK_YUKON_LP: 1739 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1740 break; 1741 default: 1742 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1743 } 1744 1745 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1746 1747 if ( sc->sk_type == SK_YUKON ) { 1748 uint32_t flashaddr; 1749 uint8_t testbyte; 1750 1751 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1752 1753 /* test Flash-Address Register */ 1754 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1755 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1756 1757 if (testbyte != 0) { 1758 /* this is yukon lite Rev. A0 */ 1759 sc->sk_type = SK_YUKON_LITE; 1760 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1761 /* restore Flash-Address Register */ 1762 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1763 } 1764 } 1765 break; 1766 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1767 sc->sk_name = sc->sk_vpd_prodname; 1768 break; 1769 default: 1770 sc->sk_name = "Unknown Marvell"; 1771 } 1772 1773 1774 if ( sc->sk_type == SK_YUKON_LITE ) { 1775 switch (sc->sk_rev) { 1776 case SK_YUKON_LITE_REV_A0: 1777 revstr = "A0"; 1778 break; 1779 case SK_YUKON_LITE_REV_A1: 1780 revstr = "A1"; 1781 break; 1782 case SK_YUKON_LITE_REV_A3: 1783 revstr = "A3"; 1784 break; 1785 default: 1786 revstr = ""; 1787 } 1788 } else { 1789 revstr = ""; 1790 } 1791 1792 /* Announce the product name. */ 1793 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1794 sc->sk_name, revstr, sc->sk_rev); 1795 1796 skca.skc_port = SK_PORT_A; 1797 (void)config_found(&sc->sk_dev, &skca, skcprint); 1798 1799 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1800 skca.skc_port = SK_PORT_B; 1801 (void)config_found(&sc->sk_dev, &skca, skcprint); 1802 } 1803 1804 /* Turn on the 'driver is loaded' LED. */ 1805 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1806 1807 /* skc sysctl setup */ 1808 1809 sc->sk_int_mod = SK_IM_DEFAULT; 1810 sc->sk_int_mod_pending = 0; 1811 1812 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1813 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1814 SYSCTL_DESCR("skc per-controller controls"), 1815 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1816 CTL_EOL)) != 0) { 1817 aprint_normal("%s: couldn't create sysctl node\n", 1818 sc->sk_dev.dv_xname); 1819 goto fail_1; 1820 } 1821 1822 sk_nodenum = node->sysctl_num; 1823 1824 /* interrupt moderation time in usecs */ 1825 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1826 CTLFLAG_READWRITE, 1827 CTLTYPE_INT, "int_mod", 1828 SYSCTL_DESCR("sk interrupt moderation timer"), 1829 sk_sysctl_handler, 0, sc, 1830 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1831 CTL_EOL)) != 0) { 1832 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1833 sc->sk_dev.dv_xname); 1834 goto fail_1; 1835 } 1836 1837 return; 1838 1839 fail_1: 1840 pci_intr_disestablish(pc, sc->sk_intrhand); 1841 fail: 1842 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1843 } 1844 1845 int 1846 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1847 { 1848 struct sk_softc *sc = sc_if->sk_softc; 1849 struct sk_tx_desc *f = NULL; 1850 u_int32_t frag, cur, cnt = 0, sk_ctl; 1851 int i; 1852 struct sk_txmap_entry *entry; 1853 bus_dmamap_t txmap; 1854 1855 DPRINTFN(3, ("sk_encap\n")); 1856 1857 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1858 if (entry == NULL) { 1859 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1860 return ENOBUFS; 1861 } 1862 txmap = entry->dmamap; 1863 1864 cur = frag = *txidx; 1865 1866 #ifdef SK_DEBUG 1867 if (skdebug >= 3) 1868 sk_dump_mbuf(m_head); 1869 #endif 1870 1871 /* 1872 * Start packing the mbufs in this chain into 1873 * the fragment pointers. Stop when we run out 1874 * of fragments or hit the end of the mbuf chain. 1875 */ 1876 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1877 BUS_DMA_NOWAIT)) { 1878 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1879 return ENOBUFS; 1880 } 1881 1882 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1883 1884 /* Sync the DMA map. */ 1885 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1886 BUS_DMASYNC_PREWRITE); 1887 1888 for (i = 0; i < txmap->dm_nsegs; i++) { 1889 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1890 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1891 return ENOBUFS; 1892 } 1893 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1894 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1895 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1896 if (cnt == 0) 1897 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1898 else 1899 sk_ctl |= SK_TXCTL_OWN; 1900 f->sk_ctl = htole32(sk_ctl); 1901 cur = frag; 1902 SK_INC(frag, SK_TX_RING_CNT); 1903 cnt++; 1904 } 1905 1906 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1907 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1908 1909 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1910 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1911 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1912 1913 /* Sync descriptors before handing to chip */ 1914 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1915 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1916 1917 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1918 htole32(SK_TXCTL_OWN); 1919 1920 /* Sync first descriptor to hand it off */ 1921 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1922 1923 sc_if->sk_cdata.sk_tx_cnt += cnt; 1924 1925 #ifdef SK_DEBUG 1926 if (skdebug >= 3) { 1927 struct sk_tx_desc *desc; 1928 u_int32_t idx; 1929 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1930 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1931 sk_dump_txdesc(desc, idx); 1932 } 1933 } 1934 #endif 1935 1936 *txidx = frag; 1937 1938 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1939 1940 return 0; 1941 } 1942 1943 void 1944 sk_start(struct ifnet *ifp) 1945 { 1946 struct sk_if_softc *sc_if = ifp->if_softc; 1947 struct sk_softc *sc = sc_if->sk_softc; 1948 struct mbuf *m_head = NULL; 1949 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1950 int pkts = 0; 1951 1952 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1953 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1954 1955 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1956 IFQ_POLL(&ifp->if_snd, m_head); 1957 if (m_head == NULL) 1958 break; 1959 1960 /* 1961 * Pack the data into the transmit ring. If we 1962 * don't have room, set the OACTIVE flag and wait 1963 * for the NIC to drain the ring. 1964 */ 1965 if (sk_encap(sc_if, m_head, &idx)) { 1966 ifp->if_flags |= IFF_OACTIVE; 1967 break; 1968 } 1969 1970 /* now we are committed to transmit the packet */ 1971 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1972 pkts++; 1973 1974 /* 1975 * If there's a BPF listener, bounce a copy of this frame 1976 * to him. 1977 */ 1978 #if NBPFILTER > 0 1979 if (ifp->if_bpf) 1980 bpf_mtap(ifp->if_bpf, m_head); 1981 #endif 1982 } 1983 if (pkts == 0) 1984 return; 1985 1986 /* Transmit */ 1987 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1988 sc_if->sk_cdata.sk_tx_prod = idx; 1989 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1990 1991 /* Set a timeout in case the chip goes out to lunch. */ 1992 ifp->if_timer = 5; 1993 } 1994 } 1995 1996 1997 void 1998 sk_watchdog(struct ifnet *ifp) 1999 { 2000 struct sk_if_softc *sc_if = ifp->if_softc; 2001 2002 /* 2003 * Reclaim first as there is a possibility of losing Tx completion 2004 * interrupts. 2005 */ 2006 sk_txeof(sc_if); 2007 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2008 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 2009 2010 ifp->if_oerrors++; 2011 2012 sk_init(ifp); 2013 } 2014 } 2015 2016 void 2017 sk_shutdown(void *v) 2018 { 2019 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2020 struct sk_softc *sc = sc_if->sk_softc; 2021 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2022 2023 DPRINTFN(2, ("sk_shutdown\n")); 2024 sk_stop(ifp,1); 2025 2026 /* Turn off the 'driver is loaded' LED. */ 2027 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2028 2029 /* 2030 * Reset the GEnesis controller. Doing this should also 2031 * assert the resets on the attached XMAC(s). 2032 */ 2033 sk_reset(sc); 2034 } 2035 2036 void 2037 sk_rxeof(struct sk_if_softc *sc_if) 2038 { 2039 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2040 struct mbuf *m; 2041 struct sk_chain *cur_rx; 2042 struct sk_rx_desc *cur_desc; 2043 int i, cur, total_len = 0; 2044 u_int32_t rxstat, sk_ctl; 2045 bus_dmamap_t dmamap; 2046 2047 i = sc_if->sk_cdata.sk_rx_prod; 2048 2049 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2050 2051 for (;;) { 2052 cur = i; 2053 2054 /* Sync the descriptor */ 2055 SK_CDRXSYNC(sc_if, cur, 2056 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2057 2058 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2059 if (sk_ctl & SK_RXCTL_OWN) { 2060 /* Invalidate the descriptor -- it's not ready yet */ 2061 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2062 sc_if->sk_cdata.sk_rx_prod = i; 2063 break; 2064 } 2065 2066 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2067 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2068 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2069 2070 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2071 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2072 2073 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2074 m = cur_rx->sk_mbuf; 2075 cur_rx->sk_mbuf = NULL; 2076 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2077 2078 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2079 2080 SK_INC(i, SK_RX_RING_CNT); 2081 2082 if (rxstat & XM_RXSTAT_ERRFRAME) { 2083 ifp->if_ierrors++; 2084 sk_newbuf(sc_if, cur, m, dmamap); 2085 continue; 2086 } 2087 2088 /* 2089 * Try to allocate a new jumbo buffer. If that 2090 * fails, copy the packet to mbufs and put the 2091 * jumbo buffer back in the ring so it can be 2092 * re-used. If allocating mbufs fails, then we 2093 * have to drop the packet. 2094 */ 2095 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2096 struct mbuf *m0; 2097 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2098 total_len + ETHER_ALIGN, 0, ifp, NULL); 2099 sk_newbuf(sc_if, cur, m, dmamap); 2100 if (m0 == NULL) { 2101 aprint_error("%s: no receive buffers " 2102 "available -- packet dropped!\n", 2103 sc_if->sk_dev.dv_xname); 2104 ifp->if_ierrors++; 2105 continue; 2106 } 2107 m_adj(m0, ETHER_ALIGN); 2108 m = m0; 2109 } else { 2110 m->m_pkthdr.rcvif = ifp; 2111 m->m_pkthdr.len = m->m_len = total_len; 2112 } 2113 2114 ifp->if_ipackets++; 2115 2116 #if NBPFILTER > 0 2117 if (ifp->if_bpf) 2118 bpf_mtap(ifp->if_bpf, m); 2119 #endif 2120 /* pass it on. */ 2121 (*ifp->if_input)(ifp, m); 2122 } 2123 } 2124 2125 void 2126 sk_txeof(struct sk_if_softc *sc_if) 2127 { 2128 struct sk_softc *sc = sc_if->sk_softc; 2129 struct sk_tx_desc *cur_tx; 2130 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2131 u_int32_t idx, sk_ctl; 2132 struct sk_txmap_entry *entry; 2133 2134 DPRINTFN(3, ("sk_txeof\n")); 2135 2136 /* 2137 * Go through our tx ring and free mbufs for those 2138 * frames that have been sent. 2139 */ 2140 idx = sc_if->sk_cdata.sk_tx_cons; 2141 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2142 SK_CDTXSYNC(sc_if, idx, 1, 2143 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2144 2145 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2146 sk_ctl = le32toh(cur_tx->sk_ctl); 2147 #ifdef SK_DEBUG 2148 if (skdebug >= 3) 2149 sk_dump_txdesc(cur_tx, idx); 2150 #endif 2151 if (sk_ctl & SK_TXCTL_OWN) { 2152 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2153 break; 2154 } 2155 if (sk_ctl & SK_TXCTL_LASTFRAG) 2156 ifp->if_opackets++; 2157 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2158 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2159 2160 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2161 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2162 2163 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2164 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2165 2166 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2167 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2168 link); 2169 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2170 } 2171 sc_if->sk_cdata.sk_tx_cnt--; 2172 SK_INC(idx, SK_TX_RING_CNT); 2173 } 2174 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2175 ifp->if_timer = 0; 2176 else /* nudge chip to keep tx ring moving */ 2177 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2178 2179 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2180 ifp->if_flags &= ~IFF_OACTIVE; 2181 2182 sc_if->sk_cdata.sk_tx_cons = idx; 2183 } 2184 2185 void 2186 sk_tick(void *xsc_if) 2187 { 2188 struct sk_if_softc *sc_if = xsc_if; 2189 struct mii_data *mii = &sc_if->sk_mii; 2190 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2191 int i; 2192 2193 DPRINTFN(3, ("sk_tick\n")); 2194 2195 if (!(ifp->if_flags & IFF_UP)) 2196 return; 2197 2198 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2199 sk_intr_bcom(sc_if); 2200 return; 2201 } 2202 2203 /* 2204 * According to SysKonnect, the correct way to verify that 2205 * the link has come back up is to poll bit 0 of the GPIO 2206 * register three times. This pin has the signal from the 2207 * link sync pin connected to it; if we read the same link 2208 * state 3 times in a row, we know the link is up. 2209 */ 2210 for (i = 0; i < 3; i++) { 2211 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2212 break; 2213 } 2214 2215 if (i != 3) { 2216 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2217 return; 2218 } 2219 2220 /* Turn the GP0 interrupt back on. */ 2221 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2222 SK_XM_READ_2(sc_if, XM_ISR); 2223 mii_tick(mii); 2224 mii_pollstat(mii); 2225 callout_stop(&sc_if->sk_tick_ch); 2226 } 2227 2228 void 2229 sk_intr_bcom(struct sk_if_softc *sc_if) 2230 { 2231 struct mii_data *mii = &sc_if->sk_mii; 2232 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2233 int status; 2234 2235 2236 DPRINTFN(3, ("sk_intr_bcom\n")); 2237 2238 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2239 2240 /* 2241 * Read the PHY interrupt register to make sure 2242 * we clear any pending interrupts. 2243 */ 2244 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2245 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2246 2247 if (!(ifp->if_flags & IFF_RUNNING)) { 2248 sk_init_xmac(sc_if); 2249 return; 2250 } 2251 2252 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2253 int lstat; 2254 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2255 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2256 2257 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2258 mii_mediachg(mii); 2259 /* Turn off the link LED. */ 2260 SK_IF_WRITE_1(sc_if, 0, 2261 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2262 sc_if->sk_link = 0; 2263 } else if (status & BRGPHY_ISR_LNK_CHG) { 2264 sk_xmac_miibus_writereg((struct device *)sc_if, 2265 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2266 mii_tick(mii); 2267 sc_if->sk_link = 1; 2268 /* Turn on the link LED. */ 2269 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2270 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2271 SK_LINKLED_BLINK_OFF); 2272 mii_pollstat(mii); 2273 } else { 2274 mii_tick(mii); 2275 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2276 } 2277 } 2278 2279 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2280 } 2281 2282 void 2283 sk_intr_xmac(struct sk_if_softc *sc_if) 2284 { 2285 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2286 2287 DPRINTFN(3, ("sk_intr_xmac\n")); 2288 2289 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2290 if (status & XM_ISR_GP0_SET) { 2291 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2292 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2293 } 2294 2295 if (status & XM_ISR_AUTONEG_DONE) { 2296 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2297 } 2298 } 2299 2300 if (status & XM_IMR_TX_UNDERRUN) 2301 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2302 2303 if (status & XM_IMR_RX_OVERRUN) 2304 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2305 } 2306 2307 void 2308 sk_intr_yukon(struct sk_if_softc *sc_if) 2309 { 2310 int status; 2311 2312 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2313 2314 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2315 } 2316 2317 int 2318 sk_intr(void *xsc) 2319 { 2320 struct sk_softc *sc = xsc; 2321 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2322 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2323 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2324 u_int32_t status; 2325 int claimed = 0; 2326 2327 if (sc_if0 != NULL) 2328 ifp0 = &sc_if0->sk_ethercom.ec_if; 2329 if (sc_if1 != NULL) 2330 ifp1 = &sc_if1->sk_ethercom.ec_if; 2331 2332 for (;;) { 2333 status = CSR_READ_4(sc, SK_ISSR); 2334 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2335 2336 if (!(status & sc->sk_intrmask)) 2337 break; 2338 2339 claimed = 1; 2340 2341 /* Handle receive interrupts first. */ 2342 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2343 sk_rxeof(sc_if0); 2344 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2345 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2346 } 2347 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2348 sk_rxeof(sc_if1); 2349 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2350 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2351 } 2352 2353 /* Then transmit interrupts. */ 2354 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2355 sk_txeof(sc_if0); 2356 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2357 SK_TXBMU_CLR_IRQ_EOF); 2358 } 2359 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2360 sk_txeof(sc_if1); 2361 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2362 SK_TXBMU_CLR_IRQ_EOF); 2363 } 2364 2365 /* Then MAC interrupts. */ 2366 if (sc_if0 && (status & SK_ISR_MAC1) && 2367 (ifp0->if_flags & IFF_RUNNING)) { 2368 if (sc->sk_type == SK_GENESIS) 2369 sk_intr_xmac(sc_if0); 2370 else 2371 sk_intr_yukon(sc_if0); 2372 } 2373 2374 if (sc_if1 && (status & SK_ISR_MAC2) && 2375 (ifp1->if_flags & IFF_RUNNING)) { 2376 if (sc->sk_type == SK_GENESIS) 2377 sk_intr_xmac(sc_if1); 2378 else 2379 sk_intr_yukon(sc_if1); 2380 2381 } 2382 2383 if (status & SK_ISR_EXTERNAL_REG) { 2384 if (sc_if0 != NULL && 2385 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2386 sk_intr_bcom(sc_if0); 2387 2388 if (sc_if1 != NULL && 2389 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2390 sk_intr_bcom(sc_if1); 2391 } 2392 } 2393 2394 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2395 2396 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2397 sk_start(ifp0); 2398 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2399 sk_start(ifp1); 2400 2401 #if NRND > 0 2402 if (RND_ENABLED(&sc->rnd_source)) 2403 rnd_add_uint32(&sc->rnd_source, status); 2404 #endif 2405 2406 if (sc->sk_int_mod_pending) 2407 sk_update_int_mod(sc); 2408 2409 return claimed; 2410 } 2411 2412 void 2413 sk_init_xmac(struct sk_if_softc *sc_if) 2414 { 2415 struct sk_softc *sc = sc_if->sk_softc; 2416 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2417 static const struct sk_bcom_hack bhack[] = { 2418 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2419 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2420 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2421 { 0, 0 } }; 2422 2423 DPRINTFN(1, ("sk_init_xmac\n")); 2424 2425 /* Unreset the XMAC. */ 2426 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2427 DELAY(1000); 2428 2429 /* Reset the XMAC's internal state. */ 2430 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2431 2432 /* Save the XMAC II revision */ 2433 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2434 2435 /* 2436 * Perform additional initialization for external PHYs, 2437 * namely for the 1000baseTX cards that use the XMAC's 2438 * GMII mode. 2439 */ 2440 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2441 int i = 0; 2442 u_int32_t val; 2443 2444 /* Take PHY out of reset. */ 2445 val = sk_win_read_4(sc, SK_GPIO); 2446 if (sc_if->sk_port == SK_PORT_A) 2447 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2448 else 2449 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2450 sk_win_write_4(sc, SK_GPIO, val); 2451 2452 /* Enable GMII mode on the XMAC. */ 2453 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2454 2455 sk_xmac_miibus_writereg((struct device *)sc_if, 2456 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2457 DELAY(10000); 2458 sk_xmac_miibus_writereg((struct device *)sc_if, 2459 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2460 2461 /* 2462 * Early versions of the BCM5400 apparently have 2463 * a bug that requires them to have their reserved 2464 * registers initialized to some magic values. I don't 2465 * know what the numbers do, I'm just the messenger. 2466 */ 2467 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2468 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2469 while (bhack[i].reg) { 2470 sk_xmac_miibus_writereg((struct device *)sc_if, 2471 SK_PHYADDR_BCOM, bhack[i].reg, 2472 bhack[i].val); 2473 i++; 2474 } 2475 } 2476 } 2477 2478 /* Set station address */ 2479 SK_XM_WRITE_2(sc_if, XM_PAR0, 2480 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2481 SK_XM_WRITE_2(sc_if, XM_PAR1, 2482 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2483 SK_XM_WRITE_2(sc_if, XM_PAR2, 2484 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2485 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2486 2487 if (ifp->if_flags & IFF_PROMISC) 2488 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2489 else 2490 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2491 2492 if (ifp->if_flags & IFF_BROADCAST) 2493 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2494 else 2495 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2496 2497 /* We don't need the FCS appended to the packet. */ 2498 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2499 2500 /* We want short frames padded to 60 bytes. */ 2501 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2502 2503 /* 2504 * Enable the reception of all error frames. This is is 2505 * a necessary evil due to the design of the XMAC. The 2506 * XMAC's receive FIFO is only 8K in size, however jumbo 2507 * frames can be up to 9000 bytes in length. When bad 2508 * frame filtering is enabled, the XMAC's RX FIFO operates 2509 * in 'store and forward' mode. For this to work, the 2510 * entire frame has to fit into the FIFO, but that means 2511 * that jumbo frames larger than 8192 bytes will be 2512 * truncated. Disabling all bad frame filtering causes 2513 * the RX FIFO to operate in streaming mode, in which 2514 * case the XMAC will start transfering frames out of the 2515 * RX FIFO as soon as the FIFO threshold is reached. 2516 */ 2517 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2518 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2519 XM_MODE_RX_INRANGELEN); 2520 2521 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2522 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2523 else 2524 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2525 2526 /* 2527 * Bump up the transmit threshold. This helps hold off transmit 2528 * underruns when we're blasting traffic from both ports at once. 2529 */ 2530 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2531 2532 /* Set multicast filter */ 2533 sk_setmulti(sc_if); 2534 2535 /* Clear and enable interrupts */ 2536 SK_XM_READ_2(sc_if, XM_ISR); 2537 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2538 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2539 else 2540 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2541 2542 /* Configure MAC arbiter */ 2543 switch (sc_if->sk_xmac_rev) { 2544 case XM_XMAC_REV_B2: 2545 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2546 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2547 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2548 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2549 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2550 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2551 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2552 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2553 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2554 break; 2555 case XM_XMAC_REV_C1: 2556 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2557 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2558 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2559 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2560 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2561 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2562 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2563 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2564 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2565 break; 2566 default: 2567 break; 2568 } 2569 sk_win_write_2(sc, SK_MACARB_CTL, 2570 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2571 2572 sc_if->sk_link = 1; 2573 } 2574 2575 void sk_init_yukon(struct sk_if_softc *sc_if) 2576 { 2577 u_int32_t /*mac, */phy; 2578 u_int16_t reg; 2579 struct sk_softc *sc; 2580 int i; 2581 2582 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2583 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2584 2585 sc = sc_if->sk_softc; 2586 if (sc->sk_type == SK_YUKON_LITE && 2587 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2588 /* Take PHY out of reset. */ 2589 sk_win_write_4(sc, SK_GPIO, 2590 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2591 } 2592 2593 2594 /* GMAC and GPHY Reset */ 2595 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2596 2597 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2598 2599 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2600 DELAY(1000); 2601 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2602 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2603 DELAY(1000); 2604 2605 2606 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2607 2608 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2609 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2610 2611 switch (sc_if->sk_softc->sk_pmd) { 2612 case IFM_1000_SX: 2613 case IFM_1000_LX: 2614 phy |= SK_GPHY_FIBER; 2615 break; 2616 2617 case IFM_1000_CX: 2618 case IFM_1000_T: 2619 phy |= SK_GPHY_COPPER; 2620 break; 2621 } 2622 2623 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2624 2625 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2626 DELAY(1000); 2627 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2628 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2629 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2630 2631 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2632 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2633 2634 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2635 2636 /* unused read of the interrupt source register */ 2637 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2638 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2639 2640 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2641 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2642 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2643 2644 /* MIB Counter Clear Mode set */ 2645 reg |= YU_PAR_MIB_CLR; 2646 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2647 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2648 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2649 2650 /* MIB Counter Clear Mode clear */ 2651 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2652 reg &= ~YU_PAR_MIB_CLR; 2653 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2654 2655 /* receive control reg */ 2656 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2657 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2658 YU_RCR_CRCR); 2659 2660 /* transmit parameter register */ 2661 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2662 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2663 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2664 2665 /* serial mode register */ 2666 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2667 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2668 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2669 YU_SMR_IPG_DATA(0x1e)); 2670 2671 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2672 /* Setup Yukon's address */ 2673 for (i = 0; i < 3; i++) { 2674 /* Write Source Address 1 (unicast filter) */ 2675 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2676 sc_if->sk_enaddr[i * 2] | 2677 sc_if->sk_enaddr[i * 2 + 1] << 8); 2678 } 2679 2680 for (i = 0; i < 3; i++) { 2681 reg = sk_win_read_2(sc_if->sk_softc, 2682 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2683 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2684 } 2685 2686 /* Set multicast filter */ 2687 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2688 sk_setmulti(sc_if); 2689 2690 /* enable interrupt mask for counter overflows */ 2691 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2692 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2693 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2694 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2695 2696 /* Configure RX MAC FIFO */ 2697 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2698 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2699 2700 /* Configure TX MAC FIFO */ 2701 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2702 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2703 2704 DPRINTFN(6, ("sk_init_yukon: end\n")); 2705 } 2706 2707 /* 2708 * Note that to properly initialize any part of the GEnesis chip, 2709 * you first have to take it out of reset mode. 2710 */ 2711 int 2712 sk_init(struct ifnet *ifp) 2713 { 2714 struct sk_if_softc *sc_if = ifp->if_softc; 2715 struct sk_softc *sc = sc_if->sk_softc; 2716 struct mii_data *mii = &sc_if->sk_mii; 2717 int s; 2718 u_int32_t imr, imtimer_ticks; 2719 2720 DPRINTFN(1, ("sk_init\n")); 2721 2722 s = splnet(); 2723 2724 if (ifp->if_flags & IFF_RUNNING) { 2725 splx(s); 2726 return 0; 2727 } 2728 2729 /* Cancel pending I/O and free all RX/TX buffers. */ 2730 sk_stop(ifp,0); 2731 2732 if (sc->sk_type == SK_GENESIS) { 2733 /* Configure LINK_SYNC LED */ 2734 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2735 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2736 SK_LINKLED_LINKSYNC_ON); 2737 2738 /* Configure RX LED */ 2739 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2740 SK_RXLEDCTL_COUNTER_START); 2741 2742 /* Configure TX LED */ 2743 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2744 SK_TXLEDCTL_COUNTER_START); 2745 } 2746 2747 /* Configure I2C registers */ 2748 2749 /* Configure XMAC(s) */ 2750 switch (sc->sk_type) { 2751 case SK_GENESIS: 2752 sk_init_xmac(sc_if); 2753 break; 2754 case SK_YUKON: 2755 case SK_YUKON_LITE: 2756 case SK_YUKON_LP: 2757 sk_init_yukon(sc_if); 2758 break; 2759 } 2760 mii_mediachg(mii); 2761 2762 if (sc->sk_type == SK_GENESIS) { 2763 /* Configure MAC FIFOs */ 2764 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2765 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2766 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2767 2768 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2769 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2770 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2771 } 2772 2773 /* Configure transmit arbiter(s) */ 2774 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2775 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2776 2777 /* Configure RAMbuffers */ 2778 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2779 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2780 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2781 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2782 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2783 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2784 2785 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2786 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2787 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2788 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2789 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2790 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2791 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2792 2793 /* Configure BMUs */ 2794 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2795 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2796 SK_RX_RING_ADDR(sc_if, 0)); 2797 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2798 2799 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2800 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2801 SK_TX_RING_ADDR(sc_if, 0)); 2802 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2803 2804 /* Init descriptors */ 2805 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2806 aprint_error("%s: initialization failed: no " 2807 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2808 sk_stop(ifp,0); 2809 splx(s); 2810 return ENOBUFS; 2811 } 2812 2813 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2814 aprint_error("%s: initialization failed: no " 2815 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2816 sk_stop(ifp,0); 2817 splx(s); 2818 return ENOBUFS; 2819 } 2820 2821 /* Set interrupt moderation if changed via sysctl. */ 2822 switch (sc->sk_type) { 2823 case SK_GENESIS: 2824 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2825 break; 2826 case SK_YUKON_EC: 2827 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2828 break; 2829 default: 2830 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2831 } 2832 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2833 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2834 sk_win_write_4(sc, SK_IMTIMERINIT, 2835 SK_IM_USECS(sc->sk_int_mod)); 2836 aprint_verbose("%s: interrupt moderation is %d us\n", 2837 sc->sk_dev.dv_xname, sc->sk_int_mod); 2838 } 2839 2840 /* Configure interrupt handling */ 2841 CSR_READ_4(sc, SK_ISSR); 2842 if (sc_if->sk_port == SK_PORT_A) 2843 sc->sk_intrmask |= SK_INTRS1; 2844 else 2845 sc->sk_intrmask |= SK_INTRS2; 2846 2847 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2848 2849 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2850 2851 /* Start BMUs. */ 2852 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2853 2854 if (sc->sk_type == SK_GENESIS) { 2855 /* Enable XMACs TX and RX state machines */ 2856 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2857 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2858 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2859 } 2860 2861 if (SK_YUKON_FAMILY(sc->sk_type)) { 2862 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2863 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2864 #if 0 2865 /* XXX disable 100Mbps and full duplex mode? */ 2866 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2867 #endif 2868 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2869 } 2870 2871 2872 ifp->if_flags |= IFF_RUNNING; 2873 ifp->if_flags &= ~IFF_OACTIVE; 2874 2875 splx(s); 2876 return 0; 2877 } 2878 2879 void 2880 sk_stop(struct ifnet *ifp, int disable) 2881 { 2882 struct sk_if_softc *sc_if = ifp->if_softc; 2883 struct sk_softc *sc = sc_if->sk_softc; 2884 int i; 2885 2886 DPRINTFN(1, ("sk_stop\n")); 2887 2888 callout_stop(&sc_if->sk_tick_ch); 2889 2890 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2891 u_int32_t val; 2892 2893 /* Put PHY back into reset. */ 2894 val = sk_win_read_4(sc, SK_GPIO); 2895 if (sc_if->sk_port == SK_PORT_A) { 2896 val |= SK_GPIO_DIR0; 2897 val &= ~SK_GPIO_DAT0; 2898 } else { 2899 val |= SK_GPIO_DIR2; 2900 val &= ~SK_GPIO_DAT2; 2901 } 2902 sk_win_write_4(sc, SK_GPIO, val); 2903 } 2904 2905 /* Turn off various components of this interface. */ 2906 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2907 switch (sc->sk_type) { 2908 case SK_GENESIS: 2909 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2910 SK_TXMACCTL_XMAC_RESET); 2911 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2912 break; 2913 case SK_YUKON: 2914 case SK_YUKON_LITE: 2915 case SK_YUKON_LP: 2916 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2917 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2918 break; 2919 } 2920 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2921 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2922 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2923 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2924 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2925 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2926 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2927 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2928 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2929 2930 /* Disable interrupts */ 2931 if (sc_if->sk_port == SK_PORT_A) 2932 sc->sk_intrmask &= ~SK_INTRS1; 2933 else 2934 sc->sk_intrmask &= ~SK_INTRS2; 2935 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2936 2937 SK_XM_READ_2(sc_if, XM_ISR); 2938 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2939 2940 /* Free RX and TX mbufs still in the queues. */ 2941 for (i = 0; i < SK_RX_RING_CNT; i++) { 2942 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2943 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2944 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2945 } 2946 } 2947 2948 for (i = 0; i < SK_TX_RING_CNT; i++) { 2949 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2950 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2951 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2952 } 2953 } 2954 2955 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2956 } 2957 2958 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2959 2960 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2961 2962 #ifdef SK_DEBUG 2963 void 2964 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2965 { 2966 #define DESC_PRINT(X) \ 2967 if (X) \ 2968 printf("txdesc[%d]." #X "=%#x\n", \ 2969 idx, X); 2970 2971 DESC_PRINT(le32toh(desc->sk_ctl)); 2972 DESC_PRINT(le32toh(desc->sk_next)); 2973 DESC_PRINT(le32toh(desc->sk_data_lo)); 2974 DESC_PRINT(le32toh(desc->sk_data_hi)); 2975 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2976 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2977 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2978 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2979 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2980 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2981 #undef PRINT 2982 } 2983 2984 void 2985 sk_dump_bytes(const char *data, int len) 2986 { 2987 int c, i, j; 2988 2989 for (i = 0; i < len; i += 16) { 2990 printf("%08x ", i); 2991 c = len - i; 2992 if (c > 16) c = 16; 2993 2994 for (j = 0; j < c; j++) { 2995 printf("%02x ", data[i + j] & 0xff); 2996 if ((j & 0xf) == 7 && j > 0) 2997 printf(" "); 2998 } 2999 3000 for (; j < 16; j++) 3001 printf(" "); 3002 printf(" "); 3003 3004 for (j = 0; j < c; j++) { 3005 int ch = data[i + j] & 0xff; 3006 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3007 } 3008 3009 printf("\n"); 3010 3011 if (c < 16) 3012 break; 3013 } 3014 } 3015 3016 void 3017 sk_dump_mbuf(struct mbuf *m) 3018 { 3019 int count = m->m_pkthdr.len; 3020 3021 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3022 3023 while (count > 0 && m) { 3024 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3025 m, m->m_data, m->m_len); 3026 sk_dump_bytes(mtod(m, char *), m->m_len); 3027 3028 count -= m->m_len; 3029 m = m->m_next; 3030 } 3031 } 3032 #endif 3033 3034 static int 3035 sk_sysctl_handler(SYSCTLFN_ARGS) 3036 { 3037 int error, t; 3038 struct sysctlnode node; 3039 struct sk_softc *sc; 3040 3041 node = *rnode; 3042 sc = node.sysctl_data; 3043 t = sc->sk_int_mod; 3044 node.sysctl_data = &t; 3045 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3046 if (error || newp == NULL) 3047 return error; 3048 3049 if (t < SK_IM_MIN || t > SK_IM_MAX) 3050 return EINVAL; 3051 3052 /* update the softc with sysctl-changed value, and mark 3053 for hardware update */ 3054 sc->sk_int_mod = t; 3055 sc->sk_int_mod_pending = 1; 3056 return 0; 3057 } 3058 3059 /* 3060 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3061 * set up in skc_attach() 3062 */ 3063 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3064 { 3065 int rc; 3066 const struct sysctlnode *node; 3067 3068 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3069 0, CTLTYPE_NODE, "hw", NULL, 3070 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3071 goto err; 3072 } 3073 3074 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3075 0, CTLTYPE_NODE, "sk", 3076 SYSCTL_DESCR("sk interface controls"), 3077 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3078 goto err; 3079 } 3080 3081 sk_root_num = node->sysctl_num; 3082 return; 3083 3084 err: 3085 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3086 } 3087
Indexes created Mon Oct 13 15:10:03 GMT 2025