if_sk.c revision 1.46
1 /* $NetBSD: if_sk.c,v 1.46 2008/01/19 22:10:18 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include <sys/cdefs.h> 125 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.46 2008/01/19 22:10:18 dyoung Exp $"); 126 127 #include "bpfilter.h" 128 #include "rnd.h" 129 130 #include <sys/param.h> 131 #include <sys/systm.h> 132 #include <sys/sockio.h> 133 #include <sys/mbuf.h> 134 #include <sys/malloc.h> 135 #include <sys/kernel.h> 136 #include <sys/socket.h> 137 #include <sys/device.h> 138 #include <sys/queue.h> 139 #include <sys/callout.h> 140 #include <sys/sysctl.h> 141 #include <sys/endian.h> 142 143 #include <net/if.h> 144 #include <net/if_dl.h> 145 #include <net/if_types.h> 146 147 #include <net/if_media.h> 148 149 #if NBPFILTER > 0 150 #include <net/bpf.h> 151 #endif 152 #if NRND > 0 153 #include <sys/rnd.h> 154 #endif 155 156 #include <dev/mii/mii.h> 157 #include <dev/mii/miivar.h> 158 #include <dev/mii/brgphyreg.h> 159 160 #include <dev/pci/pcireg.h> 161 #include <dev/pci/pcivar.h> 162 #include <dev/pci/pcidevs.h> 163 164 /* #define SK_USEIOSPACE */ 165 166 #include <dev/pci/if_skreg.h> 167 #include <dev/pci/if_skvar.h> 168 169 int skc_probe(struct device *, struct cfdata *, void *); 170 void skc_attach(struct device *, struct device *self, void *aux); 171 int sk_probe(struct device *, struct cfdata *, void *); 172 void sk_attach(struct device *, struct device *self, void *aux); 173 int skcprint(void *, const char *); 174 int sk_intr(void *); 175 void sk_intr_bcom(struct sk_if_softc *); 176 void sk_intr_xmac(struct sk_if_softc *); 177 void sk_intr_yukon(struct sk_if_softc *); 178 void sk_rxeof(struct sk_if_softc *); 179 void sk_txeof(struct sk_if_softc *); 180 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 181 void sk_start(struct ifnet *); 182 int sk_ioctl(struct ifnet *, u_long, void *); 183 int sk_init(struct ifnet *); 184 void sk_init_xmac(struct sk_if_softc *); 185 void sk_init_yukon(struct sk_if_softc *); 186 void sk_stop(struct ifnet *, int); 187 void sk_watchdog(struct ifnet *); 188 void sk_shutdown(void *); 189 int sk_ifmedia_upd(struct ifnet *); 190 void sk_reset(struct sk_softc *); 191 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 192 int sk_alloc_jumbo_mem(struct sk_if_softc *); 193 void sk_free_jumbo_mem(struct sk_if_softc *); 194 void *sk_jalloc(struct sk_if_softc *); 195 void sk_jfree(struct mbuf *, void *, size_t, void *); 196 int sk_init_rx_ring(struct sk_if_softc *); 197 int sk_init_tx_ring(struct sk_if_softc *); 198 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 199 void sk_vpd_read_res(struct sk_softc *, 200 struct vpd_res *, int); 201 void sk_vpd_read(struct sk_softc *); 202 203 void sk_update_int_mod(struct sk_softc *); 204 205 int sk_xmac_miibus_readreg(struct device *, int, int); 206 void sk_xmac_miibus_writereg(struct device *, int, int, int); 207 void sk_xmac_miibus_statchg(struct device *); 208 209 int sk_marv_miibus_readreg(struct device *, int, int); 210 void sk_marv_miibus_writereg(struct device *, int, int, int); 211 void sk_marv_miibus_statchg(struct device *); 212 213 u_int32_t sk_xmac_hash(void *); 214 u_int32_t sk_yukon_hash(void *); 215 void sk_setfilt(struct sk_if_softc *, void *, int); 216 void sk_setmulti(struct sk_if_softc *); 217 void sk_tick(void *); 218 219 /* #define SK_DEBUG 2 */ 220 #ifdef SK_DEBUG 221 #define DPRINTF(x) if (skdebug) printf x 222 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 223 int skdebug = SK_DEBUG; 224 225 void sk_dump_txdesc(struct sk_tx_desc *, int); 226 void sk_dump_mbuf(struct mbuf *); 227 void sk_dump_bytes(const char *, int); 228 #else 229 #define DPRINTF(x) 230 #define DPRINTFN(n,x) 231 #endif 232 233 static int sk_sysctl_handler(SYSCTLFN_PROTO); 234 static int sk_root_num; 235 236 /* supported device vendors */ 237 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 238 static const struct sk_product { 239 pci_vendor_id_t sk_vendor; 240 pci_product_id_t sk_product; 241 } sk_products[] = { 242 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 243 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 244 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 245 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 246 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 247 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 248 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 249 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 250 { 0, 0, } 251 }; 252 253 #define SK_LINKSYS_EG1032_SUBID 0x00151737 254 255 static inline u_int32_t 256 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 257 { 258 #ifdef SK_USEIOSPACE 259 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 260 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 261 #else 262 return CSR_READ_4(sc, reg); 263 #endif 264 } 265 266 static inline u_int16_t 267 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 268 { 269 #ifdef SK_USEIOSPACE 270 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 271 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 272 #else 273 return CSR_READ_2(sc, reg); 274 #endif 275 } 276 277 static inline u_int8_t 278 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 279 { 280 #ifdef SK_USEIOSPACE 281 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 282 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 283 #else 284 return CSR_READ_1(sc, reg); 285 #endif 286 } 287 288 static inline void 289 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 290 { 291 #ifdef SK_USEIOSPACE 292 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 293 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 294 #else 295 CSR_WRITE_4(sc, reg, x); 296 #endif 297 } 298 299 static inline void 300 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 301 { 302 #ifdef SK_USEIOSPACE 303 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 304 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 305 #else 306 CSR_WRITE_2(sc, reg, x); 307 #endif 308 } 309 310 static inline void 311 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 312 { 313 #ifdef SK_USEIOSPACE 314 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 315 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 316 #else 317 CSR_WRITE_1(sc, reg, x); 318 #endif 319 } 320 321 /* 322 * The VPD EEPROM contains Vital Product Data, as suggested in 323 * the PCI 2.1 specification. The VPD data is separared into areas 324 * denoted by resource IDs. The SysKonnect VPD contains an ID string 325 * resource (the name of the adapter), a read-only area resource 326 * containing various key/data fields and a read/write area which 327 * can be used to store asset management information or log messages. 328 * We read the ID string and read-only into buffers attached to 329 * the controller softc structure for later use. At the moment, 330 * we only use the ID string during sk_attach(). 331 */ 332 u_int8_t 333 sk_vpd_readbyte(struct sk_softc *sc, int addr) 334 { 335 int i; 336 337 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 338 for (i = 0; i < SK_TIMEOUT; i++) { 339 DELAY(1); 340 if (sk_win_read_2(sc, 341 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 342 break; 343 } 344 345 if (i == SK_TIMEOUT) 346 return 0; 347 348 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 349 } 350 351 void 352 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 353 { 354 int i; 355 u_int8_t *ptr; 356 357 ptr = (u_int8_t *)res; 358 for (i = 0; i < sizeof(struct vpd_res); i++) 359 ptr[i] = sk_vpd_readbyte(sc, i + addr); 360 } 361 362 void 363 sk_vpd_read(struct sk_softc *sc) 364 { 365 int pos = 0, i; 366 struct vpd_res res; 367 368 if (sc->sk_vpd_prodname != NULL) 369 free(sc->sk_vpd_prodname, M_DEVBUF); 370 if (sc->sk_vpd_readonly != NULL) 371 free(sc->sk_vpd_readonly, M_DEVBUF); 372 sc->sk_vpd_prodname = NULL; 373 sc->sk_vpd_readonly = NULL; 374 375 sk_vpd_read_res(sc, &res, pos); 376 377 if (res.vr_id != VPD_RES_ID) { 378 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 379 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 380 return; 381 } 382 383 pos += sizeof(res); 384 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 385 if (sc->sk_vpd_prodname == NULL) 386 panic("sk_vpd_read"); 387 for (i = 0; i < res.vr_len; i++) 388 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 389 sc->sk_vpd_prodname[i] = '\0'; 390 pos += i; 391 392 sk_vpd_read_res(sc, &res, pos); 393 394 if (res.vr_id != VPD_RES_READ) { 395 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 396 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 397 return; 398 } 399 400 pos += sizeof(res); 401 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 402 if (sc->sk_vpd_readonly == NULL) 403 panic("sk_vpd_read"); 404 for (i = 0; i < res.vr_len ; i++) 405 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 406 } 407 408 int 409 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 410 { 411 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 412 int i; 413 414 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 415 416 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 417 return 0; 418 419 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 420 SK_XM_READ_2(sc_if, XM_PHY_DATA); 421 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 422 for (i = 0; i < SK_TIMEOUT; i++) { 423 DELAY(1); 424 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 425 XM_MMUCMD_PHYDATARDY) 426 break; 427 } 428 429 if (i == SK_TIMEOUT) { 430 aprint_error("%s: phy failed to come ready\n", 431 sc_if->sk_dev.dv_xname); 432 return 0; 433 } 434 } 435 DELAY(1); 436 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 437 } 438 439 void 440 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 441 { 442 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 443 int i; 444 445 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 446 447 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 448 for (i = 0; i < SK_TIMEOUT; i++) { 449 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 450 break; 451 } 452 453 if (i == SK_TIMEOUT) { 454 aprint_error("%s: phy failed to come ready\n", 455 sc_if->sk_dev.dv_xname); 456 return; 457 } 458 459 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 460 for (i = 0; i < SK_TIMEOUT; i++) { 461 DELAY(1); 462 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 463 break; 464 } 465 466 if (i == SK_TIMEOUT) 467 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 468 } 469 470 void 471 sk_xmac_miibus_statchg(struct device *dev) 472 { 473 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 474 struct mii_data *mii = &sc_if->sk_mii; 475 476 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 477 478 /* 479 * If this is a GMII PHY, manually set the XMAC's 480 * duplex mode accordingly. 481 */ 482 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 483 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 484 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 485 else 486 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 487 } 488 } 489 490 int 491 sk_marv_miibus_readreg(struct device *dev, int phy, int reg) 492 { 493 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 494 u_int16_t val; 495 int i; 496 497 if (phy != 0 || 498 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 499 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 500 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 501 phy, reg)); 502 return 0; 503 } 504 505 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 506 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 507 508 for (i = 0; i < SK_TIMEOUT; i++) { 509 DELAY(1); 510 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 511 if (val & YU_SMICR_READ_VALID) 512 break; 513 } 514 515 if (i == SK_TIMEOUT) { 516 aprint_error("%s: phy failed to come ready\n", 517 sc_if->sk_dev.dv_xname); 518 return 0; 519 } 520 521 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 522 SK_TIMEOUT)); 523 524 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 525 526 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 527 phy, reg, val)); 528 529 return val; 530 } 531 532 void 533 sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 534 { 535 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 536 int i; 537 538 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 539 phy, reg, val)); 540 541 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 542 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 543 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 544 545 for (i = 0; i < SK_TIMEOUT; i++) { 546 DELAY(1); 547 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 548 break; 549 } 550 551 if (i == SK_TIMEOUT) 552 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 553 } 554 555 void 556 sk_marv_miibus_statchg(struct device *dev) 557 { 558 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 559 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 560 } 561 562 #define SK_HASH_BITS 6 563 564 u_int32_t 565 sk_xmac_hash(void *addr) 566 { 567 u_int32_t crc; 568 569 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 570 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 571 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 572 return crc; 573 } 574 575 u_int32_t 576 sk_yukon_hash(void *addr) 577 { 578 u_int32_t crc; 579 580 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 581 crc &= ((1 << SK_HASH_BITS) - 1); 582 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 583 return crc; 584 } 585 586 void 587 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 588 { 589 char *addr = addrv; 590 int base = XM_RXFILT_ENTRY(slot); 591 592 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 593 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 594 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 595 } 596 597 void 598 sk_setmulti(struct sk_if_softc *sc_if) 599 { 600 struct sk_softc *sc = sc_if->sk_softc; 601 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 602 u_int32_t hashes[2] = { 0, 0 }; 603 int h = 0, i; 604 struct ethercom *ec = &sc_if->sk_ethercom; 605 struct ether_multi *enm; 606 struct ether_multistep step; 607 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 608 609 /* First, zot all the existing filters. */ 610 switch (sc->sk_type) { 611 case SK_GENESIS: 612 for (i = 1; i < XM_RXFILT_MAX; i++) 613 sk_setfilt(sc_if, (void *)&dummy, i); 614 615 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 616 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 617 break; 618 case SK_YUKON: 619 case SK_YUKON_LITE: 620 case SK_YUKON_LP: 621 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 622 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 623 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 624 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 625 break; 626 } 627 628 /* Now program new ones. */ 629 allmulti: 630 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 631 hashes[0] = 0xFFFFFFFF; 632 hashes[1] = 0xFFFFFFFF; 633 } else { 634 i = 1; 635 /* First find the tail of the list. */ 636 ETHER_FIRST_MULTI(step, ec, enm); 637 while (enm != NULL) { 638 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 639 ETHER_ADDR_LEN)) { 640 ifp->if_flags |= IFF_ALLMULTI; 641 goto allmulti; 642 } 643 DPRINTFN(2,("multicast address %s\n", 644 ether_sprintf(enm->enm_addrlo))); 645 /* 646 * Program the first XM_RXFILT_MAX multicast groups 647 * into the perfect filter. For all others, 648 * use the hash table. 649 */ 650 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 651 sk_setfilt(sc_if, enm->enm_addrlo, i); 652 i++; 653 } 654 else { 655 switch (sc->sk_type) { 656 case SK_GENESIS: 657 h = sk_xmac_hash(enm->enm_addrlo); 658 break; 659 case SK_YUKON: 660 case SK_YUKON_LITE: 661 case SK_YUKON_LP: 662 h = sk_yukon_hash(enm->enm_addrlo); 663 break; 664 } 665 if (h < 32) 666 hashes[0] |= (1 << h); 667 else 668 hashes[1] |= (1 << (h - 32)); 669 } 670 671 ETHER_NEXT_MULTI(step, enm); 672 } 673 } 674 675 switch (sc->sk_type) { 676 case SK_GENESIS: 677 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 678 XM_MODE_RX_USE_PERFECT); 679 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 680 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 681 break; 682 case SK_YUKON: 683 case SK_YUKON_LITE: 684 case SK_YUKON_LP: 685 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 686 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 687 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 688 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 689 break; 690 } 691 } 692 693 int 694 sk_init_rx_ring(struct sk_if_softc *sc_if) 695 { 696 struct sk_chain_data *cd = &sc_if->sk_cdata; 697 struct sk_ring_data *rd = sc_if->sk_rdata; 698 int i; 699 700 bzero((char *)rd->sk_rx_ring, 701 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 702 703 for (i = 0; i < SK_RX_RING_CNT; i++) { 704 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 705 if (i == (SK_RX_RING_CNT - 1)) { 706 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 707 rd->sk_rx_ring[i].sk_next = 708 htole32(SK_RX_RING_ADDR(sc_if, 0)); 709 } else { 710 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 711 rd->sk_rx_ring[i].sk_next = 712 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 713 } 714 } 715 716 for (i = 0; i < SK_RX_RING_CNT; i++) { 717 if (sk_newbuf(sc_if, i, NULL, 718 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 719 aprint_error("%s: failed alloc of %dth mbuf\n", 720 sc_if->sk_dev.dv_xname, i); 721 return ENOBUFS; 722 } 723 } 724 sc_if->sk_cdata.sk_rx_prod = 0; 725 sc_if->sk_cdata.sk_rx_cons = 0; 726 727 return 0; 728 } 729 730 int 731 sk_init_tx_ring(struct sk_if_softc *sc_if) 732 { 733 struct sk_chain_data *cd = &sc_if->sk_cdata; 734 struct sk_ring_data *rd = sc_if->sk_rdata; 735 int i; 736 737 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 738 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 739 740 for (i = 0; i < SK_TX_RING_CNT; i++) { 741 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 742 if (i == (SK_TX_RING_CNT - 1)) { 743 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 744 rd->sk_tx_ring[i].sk_next = 745 htole32(SK_TX_RING_ADDR(sc_if, 0)); 746 } else { 747 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 748 rd->sk_tx_ring[i].sk_next = 749 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 750 } 751 } 752 753 sc_if->sk_cdata.sk_tx_prod = 0; 754 sc_if->sk_cdata.sk_tx_cons = 0; 755 sc_if->sk_cdata.sk_tx_cnt = 0; 756 757 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 758 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 759 760 return 0; 761 } 762 763 int 764 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 765 bus_dmamap_t dmamap) 766 { 767 struct mbuf *m_new = NULL; 768 struct sk_chain *c; 769 struct sk_rx_desc *r; 770 771 if (m == NULL) { 772 void *buf = NULL; 773 774 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 775 if (m_new == NULL) { 776 aprint_error("%s: no memory for rx list -- " 777 "packet dropped!\n", sc_if->sk_dev.dv_xname); 778 return ENOBUFS; 779 } 780 781 /* Allocate the jumbo buffer */ 782 buf = sk_jalloc(sc_if); 783 if (buf == NULL) { 784 m_freem(m_new); 785 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 786 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 787 return ENOBUFS; 788 } 789 790 /* Attach the buffer to the mbuf */ 791 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 792 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 793 794 } else { 795 /* 796 * We're re-using a previously allocated mbuf; 797 * be sure to re-init pointers and lengths to 798 * default values. 799 */ 800 m_new = m; 801 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 802 m_new->m_data = m_new->m_ext.ext_buf; 803 } 804 m_adj(m_new, ETHER_ALIGN); 805 806 c = &sc_if->sk_cdata.sk_rx_chain[i]; 807 r = c->sk_desc; 808 c->sk_mbuf = m_new; 809 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 810 (((vaddr_t)m_new->m_data 811 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 812 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 813 814 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 815 816 return 0; 817 } 818 819 /* 820 * Memory management for jumbo frames. 821 */ 822 823 int 824 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 825 { 826 struct sk_softc *sc = sc_if->sk_softc; 827 char *ptr, *kva; 828 bus_dma_segment_t seg; 829 int i, rseg, state, error; 830 struct sk_jpool_entry *entry; 831 832 state = error = 0; 833 834 /* Grab a big chunk o' storage. */ 835 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 836 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 837 aprint_error("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 838 return ENOBUFS; 839 } 840 841 state = 1; 842 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 843 BUS_DMA_NOWAIT)) { 844 aprint_error("%s: can't map dma buffers (%d bytes)\n", 845 sc->sk_dev.dv_xname, SK_JMEM); 846 error = ENOBUFS; 847 goto out; 848 } 849 850 state = 2; 851 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 852 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 853 aprint_error("%s: can't create dma map\n", sc->sk_dev.dv_xname); 854 error = ENOBUFS; 855 goto out; 856 } 857 858 state = 3; 859 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 860 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 861 aprint_error("%s: can't load dma map\n", sc->sk_dev.dv_xname); 862 error = ENOBUFS; 863 goto out; 864 } 865 866 state = 4; 867 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 868 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 869 870 LIST_INIT(&sc_if->sk_jfree_listhead); 871 LIST_INIT(&sc_if->sk_jinuse_listhead); 872 873 /* 874 * Now divide it up into 9K pieces and save the addresses 875 * in an array. 876 */ 877 ptr = sc_if->sk_cdata.sk_jumbo_buf; 878 for (i = 0; i < SK_JSLOTS; i++) { 879 sc_if->sk_cdata.sk_jslots[i] = ptr; 880 ptr += SK_JLEN; 881 entry = malloc(sizeof(struct sk_jpool_entry), 882 M_DEVBUF, M_NOWAIT); 883 if (entry == NULL) { 884 aprint_error("%s: no memory for jumbo buffer queue!\n", 885 sc->sk_dev.dv_xname); 886 error = ENOBUFS; 887 goto out; 888 } 889 entry->slot = i; 890 if (i) 891 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 892 entry, jpool_entries); 893 else 894 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 895 entry, jpool_entries); 896 } 897 out: 898 if (error != 0) { 899 switch (state) { 900 case 4: 901 bus_dmamap_unload(sc->sc_dmatag, 902 sc_if->sk_cdata.sk_rx_jumbo_map); 903 case 3: 904 bus_dmamap_destroy(sc->sc_dmatag, 905 sc_if->sk_cdata.sk_rx_jumbo_map); 906 case 2: 907 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 908 case 1: 909 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 910 break; 911 default: 912 break; 913 } 914 } 915 916 return error; 917 } 918 919 /* 920 * Allocate a jumbo buffer. 921 */ 922 void * 923 sk_jalloc(struct sk_if_softc *sc_if) 924 { 925 struct sk_jpool_entry *entry; 926 927 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 928 929 if (entry == NULL) 930 return NULL; 931 932 LIST_REMOVE(entry, jpool_entries); 933 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 934 return sc_if->sk_cdata.sk_jslots[entry->slot]; 935 } 936 937 /* 938 * Release a jumbo buffer. 939 */ 940 void 941 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 942 { 943 struct sk_jpool_entry *entry; 944 struct sk_if_softc *sc; 945 int i, s; 946 947 /* Extract the softc struct pointer. */ 948 sc = (struct sk_if_softc *)arg; 949 950 if (sc == NULL) 951 panic("sk_jfree: can't find softc pointer!"); 952 953 /* calculate the slot this buffer belongs to */ 954 955 i = ((vaddr_t)buf 956 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 957 958 if ((i < 0) || (i >= SK_JSLOTS)) 959 panic("sk_jfree: asked to free buffer that we don't manage!"); 960 961 s = splvm(); 962 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 963 if (entry == NULL) 964 panic("sk_jfree: buffer not in use!"); 965 entry->slot = i; 966 LIST_REMOVE(entry, jpool_entries); 967 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 968 969 if (__predict_true(m != NULL)) 970 pool_cache_put(mb_cache, m); 971 splx(s); 972 } 973 974 /* 975 * Set media options. 976 */ 977 int 978 sk_ifmedia_upd(struct ifnet *ifp) 979 { 980 struct sk_if_softc *sc_if = ifp->if_softc; 981 int rc; 982 983 (void) sk_init(ifp); 984 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 985 return 0; 986 return rc; 987 } 988 989 int 990 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 991 { 992 struct sk_if_softc *sc_if = ifp->if_softc; 993 struct sk_softc *sc = sc_if->sk_softc; 994 int s, error = 0; 995 996 /* DPRINTFN(2, ("sk_ioctl\n")); */ 997 998 s = splnet(); 999 1000 switch (command) { 1001 1002 case SIOCSIFFLAGS: 1003 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1004 if (ifp->if_flags & IFF_UP) { 1005 if (ifp->if_flags & IFF_RUNNING && 1006 ifp->if_flags & IFF_PROMISC && 1007 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1008 switch (sc->sk_type) { 1009 case SK_GENESIS: 1010 SK_XM_SETBIT_4(sc_if, XM_MODE, 1011 XM_MODE_RX_PROMISC); 1012 break; 1013 case SK_YUKON: 1014 case SK_YUKON_LITE: 1015 case SK_YUKON_LP: 1016 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1017 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1018 break; 1019 } 1020 sk_setmulti(sc_if); 1021 } else if (ifp->if_flags & IFF_RUNNING && 1022 !(ifp->if_flags & IFF_PROMISC) && 1023 sc_if->sk_if_flags & IFF_PROMISC) { 1024 switch (sc->sk_type) { 1025 case SK_GENESIS: 1026 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1027 XM_MODE_RX_PROMISC); 1028 break; 1029 case SK_YUKON: 1030 case SK_YUKON_LITE: 1031 case SK_YUKON_LP: 1032 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1033 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1034 break; 1035 } 1036 1037 sk_setmulti(sc_if); 1038 } else 1039 (void) sk_init(ifp); 1040 } else { 1041 if (ifp->if_flags & IFF_RUNNING) 1042 sk_stop(ifp,0); 1043 } 1044 sc_if->sk_if_flags = ifp->if_flags; 1045 error = 0; 1046 break; 1047 1048 default: 1049 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1050 error = ether_ioctl(ifp, command, data); 1051 1052 if ( error == ENETRESET) { 1053 if (ifp->if_flags & IFF_RUNNING) { 1054 sk_setmulti(sc_if); 1055 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1056 } 1057 error = 0; 1058 } 1059 break; 1060 } 1061 1062 splx(s); 1063 return error; 1064 } 1065 1066 void 1067 sk_update_int_mod(struct sk_softc *sc) 1068 { 1069 u_int32_t imtimer_ticks; 1070 1071 /* 1072 * Configure interrupt moderation. The moderation timer 1073 * defers interrupts specified in the interrupt moderation 1074 * timer mask based on the timeout specified in the interrupt 1075 * moderation timer init register. Each bit in the timer 1076 * register represents one tick, so to specify a timeout in 1077 * microseconds, we have to multiply by the correct number of 1078 * ticks-per-microsecond. 1079 */ 1080 switch (sc->sk_type) { 1081 case SK_GENESIS: 1082 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1083 break; 1084 case SK_YUKON_EC: 1085 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1086 break; 1087 default: 1088 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1089 } 1090 aprint_verbose("%s: interrupt moderation is %d us\n", 1091 sc->sk_dev.dv_xname, sc->sk_int_mod); 1092 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1093 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1094 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1095 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1096 sc->sk_int_mod_pending = 0; 1097 } 1098 1099 /* 1100 * Lookup: Check the PCI vendor and device, and return a pointer to 1101 * The structure if the IDs match against our list. 1102 */ 1103 1104 static const struct sk_product * 1105 sk_lookup(const struct pci_attach_args *pa) 1106 { 1107 const struct sk_product *psk; 1108 1109 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1110 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1111 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1112 return psk; 1113 } 1114 return NULL; 1115 } 1116 1117 /* 1118 * Probe for a SysKonnect GEnesis chip. 1119 */ 1120 1121 int 1122 skc_probe(struct device *parent, struct cfdata *match, 1123 void *aux) 1124 { 1125 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1126 const struct sk_product *psk; 1127 pcireg_t subid; 1128 1129 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1130 1131 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1132 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1133 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1134 subid == SK_LINKSYS_EG1032_SUBID) 1135 return 1; 1136 1137 if ((psk = sk_lookup(pa))) { 1138 return 1; 1139 } 1140 return 0; 1141 } 1142 1143 /* 1144 * Force the GEnesis into reset, then bring it out of reset. 1145 */ 1146 void sk_reset(struct sk_softc *sc) 1147 { 1148 DPRINTFN(2, ("sk_reset\n")); 1149 1150 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1151 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1152 if (SK_YUKON_FAMILY(sc->sk_type)) 1153 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1154 1155 DELAY(1000); 1156 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1157 DELAY(2); 1158 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1159 if (SK_YUKON_FAMILY(sc->sk_type)) 1160 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1161 1162 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1163 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1164 CSR_READ_2(sc, SK_LINK_CTRL))); 1165 1166 if (sc->sk_type == SK_GENESIS) { 1167 /* Configure packet arbiter */ 1168 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1169 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1170 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1171 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1172 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1173 } 1174 1175 /* Enable RAM interface */ 1176 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1177 1178 sk_update_int_mod(sc); 1179 } 1180 1181 int 1182 sk_probe(struct device *parent, struct cfdata *match, 1183 void *aux) 1184 { 1185 struct skc_attach_args *sa = aux; 1186 1187 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1188 return 0; 1189 1190 return 1; 1191 } 1192 1193 /* 1194 * Each XMAC chip is attached as a separate logical IP interface. 1195 * Single port cards will have only one logical interface of course. 1196 */ 1197 void 1198 sk_attach(struct device *parent, struct device *self, void *aux) 1199 { 1200 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1201 struct sk_softc *sc = (struct sk_softc *)parent; 1202 struct skc_attach_args *sa = aux; 1203 struct sk_txmap_entry *entry; 1204 struct ifnet *ifp; 1205 bus_dma_segment_t seg; 1206 bus_dmamap_t dmamap; 1207 void *kva; 1208 int i, rseg; 1209 1210 aprint_naive("\n"); 1211 1212 sc_if->sk_port = sa->skc_port; 1213 sc_if->sk_softc = sc; 1214 sc->sk_if[sa->skc_port] = sc_if; 1215 1216 if (sa->skc_port == SK_PORT_A) 1217 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1218 if (sa->skc_port == SK_PORT_B) 1219 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1220 1221 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1222 1223 /* 1224 * Get station address for this interface. Note that 1225 * dual port cards actually come with three station 1226 * addresses: one for each port, plus an extra. The 1227 * extra one is used by the SysKonnect driver software 1228 * as a 'virtual' station address for when both ports 1229 * are operating in failover mode. Currently we don't 1230 * use this extra address. 1231 */ 1232 for (i = 0; i < ETHER_ADDR_LEN; i++) 1233 sc_if->sk_enaddr[i] = 1234 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1235 1236 1237 aprint_normal(": Ethernet address %s\n", 1238 ether_sprintf(sc_if->sk_enaddr)); 1239 1240 /* 1241 * Set up RAM buffer addresses. The NIC will have a certain 1242 * amount of SRAM on it, somewhere between 512K and 2MB. We 1243 * need to divide this up a) between the transmitter and 1244 * receiver and b) between the two XMACs, if this is a 1245 * dual port NIC. Our algorithm is to divide up the memory 1246 * evenly so that everyone gets a fair share. 1247 */ 1248 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1249 u_int32_t chunk, val; 1250 1251 chunk = sc->sk_ramsize / 2; 1252 val = sc->sk_rboff / sizeof(u_int64_t); 1253 sc_if->sk_rx_ramstart = val; 1254 val += (chunk / sizeof(u_int64_t)); 1255 sc_if->sk_rx_ramend = val - 1; 1256 sc_if->sk_tx_ramstart = val; 1257 val += (chunk / sizeof(u_int64_t)); 1258 sc_if->sk_tx_ramend = val - 1; 1259 } else { 1260 u_int32_t chunk, val; 1261 1262 chunk = sc->sk_ramsize / 4; 1263 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1264 sizeof(u_int64_t); 1265 sc_if->sk_rx_ramstart = val; 1266 val += (chunk / sizeof(u_int64_t)); 1267 sc_if->sk_rx_ramend = val - 1; 1268 sc_if->sk_tx_ramstart = val; 1269 val += (chunk / sizeof(u_int64_t)); 1270 sc_if->sk_tx_ramend = val - 1; 1271 } 1272 1273 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1274 " tx_ramstart=%#x tx_ramend=%#x\n", 1275 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1276 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1277 1278 /* Read and save PHY type and set PHY address */ 1279 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1280 switch (sc_if->sk_phytype) { 1281 case SK_PHYTYPE_XMAC: 1282 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1283 break; 1284 case SK_PHYTYPE_BCOM: 1285 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1286 break; 1287 case SK_PHYTYPE_MARV_COPPER: 1288 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1289 break; 1290 default: 1291 aprint_error("%s: unsupported PHY type: %d\n", 1292 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1293 return; 1294 } 1295 1296 /* Allocate the descriptor queues. */ 1297 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1298 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1299 aprint_error("%s: can't alloc rx buffers\n", 1300 sc->sk_dev.dv_xname); 1301 goto fail; 1302 } 1303 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1304 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1305 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1306 sc_if->sk_dev.dv_xname, 1307 (u_long) sizeof(struct sk_ring_data)); 1308 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1309 goto fail; 1310 } 1311 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1312 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1313 &sc_if->sk_ring_map)) { 1314 aprint_error("%s: can't create dma map\n", 1315 sc_if->sk_dev.dv_xname); 1316 bus_dmamem_unmap(sc->sc_dmatag, kva, 1317 sizeof(struct sk_ring_data)); 1318 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1319 goto fail; 1320 } 1321 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1322 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1323 aprint_error("%s: can't load dma map\n", 1324 sc_if->sk_dev.dv_xname); 1325 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1326 bus_dmamem_unmap(sc->sc_dmatag, kva, 1327 sizeof(struct sk_ring_data)); 1328 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1329 goto fail; 1330 } 1331 1332 for (i = 0; i < SK_RX_RING_CNT; i++) 1333 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1334 1335 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1336 for (i = 0; i < SK_TX_RING_CNT; i++) { 1337 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1338 1339 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1340 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1341 aprint_error("%s: Can't create TX dmamap\n", 1342 sc_if->sk_dev.dv_xname); 1343 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1344 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1345 bus_dmamem_unmap(sc->sc_dmatag, kva, 1346 sizeof(struct sk_ring_data)); 1347 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1348 goto fail; 1349 } 1350 1351 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1352 if (!entry) { 1353 aprint_error("%s: Can't alloc txmap entry\n", 1354 sc_if->sk_dev.dv_xname); 1355 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1356 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1357 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1358 bus_dmamem_unmap(sc->sc_dmatag, kva, 1359 sizeof(struct sk_ring_data)); 1360 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1361 goto fail; 1362 } 1363 entry->dmamap = dmamap; 1364 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1365 } 1366 1367 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1368 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1369 1370 ifp = &sc_if->sk_ethercom.ec_if; 1371 /* Try to allocate memory for jumbo buffers. */ 1372 if (sk_alloc_jumbo_mem(sc_if)) { 1373 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1374 goto fail; 1375 } 1376 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1377 | ETHERCAP_JUMBO_MTU; 1378 1379 ifp->if_softc = sc_if; 1380 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1381 ifp->if_ioctl = sk_ioctl; 1382 ifp->if_start = sk_start; 1383 ifp->if_stop = sk_stop; 1384 ifp->if_init = sk_init; 1385 ifp->if_watchdog = sk_watchdog; 1386 ifp->if_capabilities = 0; 1387 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1388 IFQ_SET_READY(&ifp->if_snd); 1389 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1390 1391 /* 1392 * Do miibus setup. 1393 */ 1394 switch (sc->sk_type) { 1395 case SK_GENESIS: 1396 sk_init_xmac(sc_if); 1397 break; 1398 case SK_YUKON: 1399 case SK_YUKON_LITE: 1400 case SK_YUKON_LP: 1401 sk_init_yukon(sc_if); 1402 break; 1403 default: 1404 aprint_error("%s: unknown device type %d\n", 1405 sc->sk_dev.dv_xname, sc->sk_type); 1406 goto fail; 1407 } 1408 1409 DPRINTFN(2, ("sk_attach: 1\n")); 1410 1411 sc_if->sk_mii.mii_ifp = ifp; 1412 switch (sc->sk_type) { 1413 case SK_GENESIS: 1414 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1415 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1416 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1417 break; 1418 case SK_YUKON: 1419 case SK_YUKON_LITE: 1420 case SK_YUKON_LP: 1421 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1422 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1423 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1424 break; 1425 } 1426 1427 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1428 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1429 sk_ifmedia_upd, ether_mediastatus); 1430 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1431 MII_OFFSET_ANY, 0); 1432 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1433 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1434 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1435 0, NULL); 1436 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1437 } else 1438 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1439 1440 callout_init(&sc_if->sk_tick_ch, 0); 1441 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1442 1443 DPRINTFN(2, ("sk_attach: 1\n")); 1444 1445 /* 1446 * Call MI attach routines. 1447 */ 1448 if_attach(ifp); 1449 1450 ether_ifattach(ifp, sc_if->sk_enaddr); 1451 1452 #if NRND > 0 1453 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1454 RND_TYPE_NET, 0); 1455 #endif 1456 1457 DPRINTFN(2, ("sk_attach: end\n")); 1458 1459 return; 1460 1461 fail: 1462 sc->sk_if[sa->skc_port] = NULL; 1463 } 1464 1465 int 1466 skcprint(void *aux, const char *pnp) 1467 { 1468 struct skc_attach_args *sa = aux; 1469 1470 if (pnp) 1471 aprint_normal("sk port %c at %s", 1472 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1473 else 1474 aprint_normal(" port %c", 1475 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1476 return UNCONF; 1477 } 1478 1479 /* 1480 * Attach the interface. Allocate softc structures, do ifmedia 1481 * setup and ethernet/BPF attach. 1482 */ 1483 void 1484 skc_attach(struct device *parent, struct device *self, void *aux) 1485 { 1486 struct sk_softc *sc = (struct sk_softc *)self; 1487 struct pci_attach_args *pa = aux; 1488 struct skc_attach_args skca; 1489 pci_chipset_tag_t pc = pa->pa_pc; 1490 #ifndef SK_USEIOSPACE 1491 pcireg_t memtype; 1492 #endif 1493 pci_intr_handle_t ih; 1494 const char *intrstr = NULL; 1495 bus_addr_t iobase; 1496 bus_size_t iosize; 1497 int rc, sk_nodenum; 1498 u_int32_t command; 1499 const char *revstr; 1500 const struct sysctlnode *node; 1501 1502 aprint_naive("\n"); 1503 1504 DPRINTFN(2, ("begin skc_attach\n")); 1505 1506 /* 1507 * Handle power management nonsense. 1508 */ 1509 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1510 1511 if (command == 0x01) { 1512 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1513 if (command & SK_PSTATE_MASK) { 1514 u_int32_t xiobase, membase, irq; 1515 1516 /* Save important PCI config data. */ 1517 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1518 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1519 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1520 1521 /* Reset the power state. */ 1522 aprint_normal("%s chip is in D%d power mode " 1523 "-- setting to D0\n", sc->sk_dev.dv_xname, 1524 command & SK_PSTATE_MASK); 1525 command &= 0xFFFFFFFC; 1526 pci_conf_write(pc, pa->pa_tag, 1527 SK_PCI_PWRMGMTCTRL, command); 1528 1529 /* Restore PCI config data. */ 1530 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1531 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1532 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1533 } 1534 } 1535 1536 /* 1537 * Map control/status registers. 1538 */ 1539 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1540 command |= PCI_COMMAND_IO_ENABLE | 1541 PCI_COMMAND_MEM_ENABLE | 1542 PCI_COMMAND_MASTER_ENABLE; 1543 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1544 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1545 1546 #ifdef SK_USEIOSPACE 1547 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1548 aprint_error(": failed to enable I/O ports!\n"); 1549 return; 1550 } 1551 /* 1552 * Map control/status registers. 1553 */ 1554 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1555 &sc->sk_btag, &sc->sk_bhandle, 1556 &iobase, &iosize)) { 1557 aprint_error(": can't find i/o space\n"); 1558 return; 1559 } 1560 #else 1561 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1562 aprint_error(": failed to enable memory mapping!\n"); 1563 return; 1564 } 1565 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1566 switch (memtype) { 1567 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1568 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1569 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1570 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1571 &iobase, &iosize) == 0) 1572 break; 1573 default: 1574 aprint_error("%s: can't find mem space\n", 1575 sc->sk_dev.dv_xname); 1576 return; 1577 } 1578 1579 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1580 #endif 1581 sc->sc_dmatag = pa->pa_dmat; 1582 1583 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1584 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1585 1586 /* bail out here if chip is not recognized */ 1587 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1588 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1589 goto fail; 1590 } 1591 if (SK_IS_YUKON2(sc)) { 1592 aprint_error("%s: Does not support Yukon2--try msk(4).\n", 1593 sc->sk_dev.dv_xname); 1594 goto fail; 1595 } 1596 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1597 1598 /* Allocate interrupt */ 1599 if (pci_intr_map(pa, &ih)) { 1600 aprint_error(": couldn't map interrupt\n"); 1601 goto fail; 1602 } 1603 1604 intrstr = pci_intr_string(pc, ih); 1605 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1606 if (sc->sk_intrhand == NULL) { 1607 aprint_error(": couldn't establish interrupt"); 1608 if (intrstr != NULL) 1609 aprint_normal(" at %s", intrstr); 1610 goto fail; 1611 } 1612 aprint_normal(": %s\n", intrstr); 1613 1614 /* Reset the adapter. */ 1615 sk_reset(sc); 1616 1617 /* Read and save vital product data from EEPROM. */ 1618 sk_vpd_read(sc); 1619 1620 if (sc->sk_type == SK_GENESIS) { 1621 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1622 /* Read and save RAM size and RAMbuffer offset */ 1623 switch (val) { 1624 case SK_RAMSIZE_512K_64: 1625 sc->sk_ramsize = 0x80000; 1626 sc->sk_rboff = SK_RBOFF_0; 1627 break; 1628 case SK_RAMSIZE_1024K_64: 1629 sc->sk_ramsize = 0x100000; 1630 sc->sk_rboff = SK_RBOFF_80000; 1631 break; 1632 case SK_RAMSIZE_1024K_128: 1633 sc->sk_ramsize = 0x100000; 1634 sc->sk_rboff = SK_RBOFF_0; 1635 break; 1636 case SK_RAMSIZE_2048K_128: 1637 sc->sk_ramsize = 0x200000; 1638 sc->sk_rboff = SK_RBOFF_0; 1639 break; 1640 default: 1641 aprint_error("%s: unknown ram size: %d\n", 1642 sc->sk_dev.dv_xname, val); 1643 goto fail_1; 1644 break; 1645 } 1646 1647 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1648 sc->sk_ramsize, sc->sk_ramsize / 1024, 1649 sc->sk_rboff)); 1650 } else { 1651 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1652 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1653 sc->sk_rboff = SK_RBOFF_0; 1654 1655 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1656 sc->sk_ramsize / 1024, sc->sk_ramsize, 1657 sc->sk_rboff)); 1658 } 1659 1660 /* Read and save physical media type */ 1661 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1662 case SK_PMD_1000BASESX: 1663 sc->sk_pmd = IFM_1000_SX; 1664 break; 1665 case SK_PMD_1000BASELX: 1666 sc->sk_pmd = IFM_1000_LX; 1667 break; 1668 case SK_PMD_1000BASECX: 1669 sc->sk_pmd = IFM_1000_CX; 1670 break; 1671 case SK_PMD_1000BASETX: 1672 case SK_PMD_1000BASETX_ALT: 1673 sc->sk_pmd = IFM_1000_T; 1674 break; 1675 default: 1676 aprint_error("%s: unknown media type: 0x%x\n", 1677 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1678 goto fail_1; 1679 } 1680 1681 /* determine whether to name it with vpd or just make it up */ 1682 /* Marvell Yukon VPD's can freqently be bogus */ 1683 1684 switch (pa->pa_id) { 1685 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1686 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1687 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1688 case PCI_PRODUCT_3COM_3C940: 1689 case PCI_PRODUCT_DLINK_DGE530T: 1690 case PCI_PRODUCT_DLINK_DGE560T: 1691 case PCI_PRODUCT_DLINK_DGE560T_2: 1692 case PCI_PRODUCT_LINKSYS_EG1032: 1693 case PCI_PRODUCT_LINKSYS_EG1064: 1694 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1695 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1696 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1697 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1698 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1699 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1700 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1701 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1702 sc->sk_name = sc->sk_vpd_prodname; 1703 break; 1704 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1705 /* whoops yukon vpd prodname bears no resemblance to reality */ 1706 switch (sc->sk_type) { 1707 case SK_GENESIS: 1708 sc->sk_name = sc->sk_vpd_prodname; 1709 break; 1710 case SK_YUKON: 1711 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1712 break; 1713 case SK_YUKON_LITE: 1714 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1715 break; 1716 case SK_YUKON_LP: 1717 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1718 break; 1719 default: 1720 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1721 } 1722 1723 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1724 1725 if ( sc->sk_type == SK_YUKON ) { 1726 uint32_t flashaddr; 1727 uint8_t testbyte; 1728 1729 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1730 1731 /* test Flash-Address Register */ 1732 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1733 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1734 1735 if (testbyte != 0) { 1736 /* this is yukon lite Rev. A0 */ 1737 sc->sk_type = SK_YUKON_LITE; 1738 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1739 /* restore Flash-Address Register */ 1740 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1741 } 1742 } 1743 break; 1744 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1745 sc->sk_name = sc->sk_vpd_prodname; 1746 break; 1747 default: 1748 sc->sk_name = "Unknown Marvell"; 1749 } 1750 1751 1752 if ( sc->sk_type == SK_YUKON_LITE ) { 1753 switch (sc->sk_rev) { 1754 case SK_YUKON_LITE_REV_A0: 1755 revstr = "A0"; 1756 break; 1757 case SK_YUKON_LITE_REV_A1: 1758 revstr = "A1"; 1759 break; 1760 case SK_YUKON_LITE_REV_A3: 1761 revstr = "A3"; 1762 break; 1763 default: 1764 revstr = ""; 1765 } 1766 } else { 1767 revstr = ""; 1768 } 1769 1770 /* Announce the product name. */ 1771 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1772 sc->sk_name, revstr, sc->sk_rev); 1773 1774 skca.skc_port = SK_PORT_A; 1775 (void)config_found(&sc->sk_dev, &skca, skcprint); 1776 1777 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1778 skca.skc_port = SK_PORT_B; 1779 (void)config_found(&sc->sk_dev, &skca, skcprint); 1780 } 1781 1782 /* Turn on the 'driver is loaded' LED. */ 1783 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1784 1785 /* skc sysctl setup */ 1786 1787 sc->sk_int_mod = SK_IM_DEFAULT; 1788 sc->sk_int_mod_pending = 0; 1789 1790 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1791 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1792 SYSCTL_DESCR("skc per-controller controls"), 1793 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1794 CTL_EOL)) != 0) { 1795 aprint_normal("%s: couldn't create sysctl node\n", 1796 sc->sk_dev.dv_xname); 1797 goto fail_1; 1798 } 1799 1800 sk_nodenum = node->sysctl_num; 1801 1802 /* interrupt moderation time in usecs */ 1803 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1804 CTLFLAG_READWRITE, 1805 CTLTYPE_INT, "int_mod", 1806 SYSCTL_DESCR("sk interrupt moderation timer"), 1807 sk_sysctl_handler, 0, sc, 1808 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1809 CTL_EOL)) != 0) { 1810 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1811 sc->sk_dev.dv_xname); 1812 goto fail_1; 1813 } 1814 1815 return; 1816 1817 fail_1: 1818 pci_intr_disestablish(pc, sc->sk_intrhand); 1819 fail: 1820 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1821 } 1822 1823 int 1824 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1825 { 1826 struct sk_softc *sc = sc_if->sk_softc; 1827 struct sk_tx_desc *f = NULL; 1828 u_int32_t frag, cur, cnt = 0, sk_ctl; 1829 int i; 1830 struct sk_txmap_entry *entry; 1831 bus_dmamap_t txmap; 1832 1833 DPRINTFN(3, ("sk_encap\n")); 1834 1835 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1836 if (entry == NULL) { 1837 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1838 return ENOBUFS; 1839 } 1840 txmap = entry->dmamap; 1841 1842 cur = frag = *txidx; 1843 1844 #ifdef SK_DEBUG 1845 if (skdebug >= 3) 1846 sk_dump_mbuf(m_head); 1847 #endif 1848 1849 /* 1850 * Start packing the mbufs in this chain into 1851 * the fragment pointers. Stop when we run out 1852 * of fragments or hit the end of the mbuf chain. 1853 */ 1854 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1855 BUS_DMA_NOWAIT)) { 1856 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1857 return ENOBUFS; 1858 } 1859 1860 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1861 1862 /* Sync the DMA map. */ 1863 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1864 BUS_DMASYNC_PREWRITE); 1865 1866 for (i = 0; i < txmap->dm_nsegs; i++) { 1867 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1868 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1869 return ENOBUFS; 1870 } 1871 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1872 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1873 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1874 if (cnt == 0) 1875 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1876 else 1877 sk_ctl |= SK_TXCTL_OWN; 1878 f->sk_ctl = htole32(sk_ctl); 1879 cur = frag; 1880 SK_INC(frag, SK_TX_RING_CNT); 1881 cnt++; 1882 } 1883 1884 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1885 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1886 1887 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1888 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1889 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1890 1891 /* Sync descriptors before handing to chip */ 1892 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1893 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1894 1895 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1896 htole32(SK_TXCTL_OWN); 1897 1898 /* Sync first descriptor to hand it off */ 1899 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1900 1901 sc_if->sk_cdata.sk_tx_cnt += cnt; 1902 1903 #ifdef SK_DEBUG 1904 if (skdebug >= 3) { 1905 struct sk_tx_desc *desc; 1906 u_int32_t idx; 1907 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1908 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1909 sk_dump_txdesc(desc, idx); 1910 } 1911 } 1912 #endif 1913 1914 *txidx = frag; 1915 1916 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1917 1918 return 0; 1919 } 1920 1921 void 1922 sk_start(struct ifnet *ifp) 1923 { 1924 struct sk_if_softc *sc_if = ifp->if_softc; 1925 struct sk_softc *sc = sc_if->sk_softc; 1926 struct mbuf *m_head = NULL; 1927 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1928 int pkts = 0; 1929 1930 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1931 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1932 1933 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1934 IFQ_POLL(&ifp->if_snd, m_head); 1935 if (m_head == NULL) 1936 break; 1937 1938 /* 1939 * Pack the data into the transmit ring. If we 1940 * don't have room, set the OACTIVE flag and wait 1941 * for the NIC to drain the ring. 1942 */ 1943 if (sk_encap(sc_if, m_head, &idx)) { 1944 ifp->if_flags |= IFF_OACTIVE; 1945 break; 1946 } 1947 1948 /* now we are committed to transmit the packet */ 1949 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1950 pkts++; 1951 1952 /* 1953 * If there's a BPF listener, bounce a copy of this frame 1954 * to him. 1955 */ 1956 #if NBPFILTER > 0 1957 if (ifp->if_bpf) 1958 bpf_mtap(ifp->if_bpf, m_head); 1959 #endif 1960 } 1961 if (pkts == 0) 1962 return; 1963 1964 /* Transmit */ 1965 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1966 sc_if->sk_cdata.sk_tx_prod = idx; 1967 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1968 1969 /* Set a timeout in case the chip goes out to lunch. */ 1970 ifp->if_timer = 5; 1971 } 1972 } 1973 1974 1975 void 1976 sk_watchdog(struct ifnet *ifp) 1977 { 1978 struct sk_if_softc *sc_if = ifp->if_softc; 1979 1980 /* 1981 * Reclaim first as there is a possibility of losing Tx completion 1982 * interrupts. 1983 */ 1984 sk_txeof(sc_if); 1985 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1986 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1987 1988 ifp->if_oerrors++; 1989 1990 sk_init(ifp); 1991 } 1992 } 1993 1994 void 1995 sk_shutdown(void *v) 1996 { 1997 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1998 struct sk_softc *sc = sc_if->sk_softc; 1999 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2000 2001 DPRINTFN(2, ("sk_shutdown\n")); 2002 sk_stop(ifp,1); 2003 2004 /* Turn off the 'driver is loaded' LED. */ 2005 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2006 2007 /* 2008 * Reset the GEnesis controller. Doing this should also 2009 * assert the resets on the attached XMAC(s). 2010 */ 2011 sk_reset(sc); 2012 } 2013 2014 void 2015 sk_rxeof(struct sk_if_softc *sc_if) 2016 { 2017 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2018 struct mbuf *m; 2019 struct sk_chain *cur_rx; 2020 struct sk_rx_desc *cur_desc; 2021 int i, cur, total_len = 0; 2022 u_int32_t rxstat, sk_ctl; 2023 bus_dmamap_t dmamap; 2024 2025 i = sc_if->sk_cdata.sk_rx_prod; 2026 2027 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2028 2029 for (;;) { 2030 cur = i; 2031 2032 /* Sync the descriptor */ 2033 SK_CDRXSYNC(sc_if, cur, 2034 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2035 2036 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2037 if (sk_ctl & SK_RXCTL_OWN) { 2038 /* Invalidate the descriptor -- it's not ready yet */ 2039 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2040 sc_if->sk_cdata.sk_rx_prod = i; 2041 break; 2042 } 2043 2044 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2045 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2046 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2047 2048 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2049 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2050 2051 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2052 m = cur_rx->sk_mbuf; 2053 cur_rx->sk_mbuf = NULL; 2054 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2055 2056 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2057 2058 SK_INC(i, SK_RX_RING_CNT); 2059 2060 if (rxstat & XM_RXSTAT_ERRFRAME) { 2061 ifp->if_ierrors++; 2062 sk_newbuf(sc_if, cur, m, dmamap); 2063 continue; 2064 } 2065 2066 /* 2067 * Try to allocate a new jumbo buffer. If that 2068 * fails, copy the packet to mbufs and put the 2069 * jumbo buffer back in the ring so it can be 2070 * re-used. If allocating mbufs fails, then we 2071 * have to drop the packet. 2072 */ 2073 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2074 struct mbuf *m0; 2075 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2076 total_len + ETHER_ALIGN, 0, ifp, NULL); 2077 sk_newbuf(sc_if, cur, m, dmamap); 2078 if (m0 == NULL) { 2079 aprint_error("%s: no receive buffers " 2080 "available -- packet dropped!\n", 2081 sc_if->sk_dev.dv_xname); 2082 ifp->if_ierrors++; 2083 continue; 2084 } 2085 m_adj(m0, ETHER_ALIGN); 2086 m = m0; 2087 } else { 2088 m->m_pkthdr.rcvif = ifp; 2089 m->m_pkthdr.len = m->m_len = total_len; 2090 } 2091 2092 ifp->if_ipackets++; 2093 2094 #if NBPFILTER > 0 2095 if (ifp->if_bpf) 2096 bpf_mtap(ifp->if_bpf, m); 2097 #endif 2098 /* pass it on. */ 2099 (*ifp->if_input)(ifp, m); 2100 } 2101 } 2102 2103 void 2104 sk_txeof(struct sk_if_softc *sc_if) 2105 { 2106 struct sk_softc *sc = sc_if->sk_softc; 2107 struct sk_tx_desc *cur_tx; 2108 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2109 u_int32_t idx, sk_ctl; 2110 struct sk_txmap_entry *entry; 2111 2112 DPRINTFN(3, ("sk_txeof\n")); 2113 2114 /* 2115 * Go through our tx ring and free mbufs for those 2116 * frames that have been sent. 2117 */ 2118 idx = sc_if->sk_cdata.sk_tx_cons; 2119 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2120 SK_CDTXSYNC(sc_if, idx, 1, 2121 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2122 2123 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2124 sk_ctl = le32toh(cur_tx->sk_ctl); 2125 #ifdef SK_DEBUG 2126 if (skdebug >= 3) 2127 sk_dump_txdesc(cur_tx, idx); 2128 #endif 2129 if (sk_ctl & SK_TXCTL_OWN) { 2130 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2131 break; 2132 } 2133 if (sk_ctl & SK_TXCTL_LASTFRAG) 2134 ifp->if_opackets++; 2135 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2136 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2137 2138 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2139 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2140 2141 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2142 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2143 2144 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2145 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2146 link); 2147 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2148 } 2149 sc_if->sk_cdata.sk_tx_cnt--; 2150 SK_INC(idx, SK_TX_RING_CNT); 2151 } 2152 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2153 ifp->if_timer = 0; 2154 else /* nudge chip to keep tx ring moving */ 2155 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2156 2157 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2158 ifp->if_flags &= ~IFF_OACTIVE; 2159 2160 sc_if->sk_cdata.sk_tx_cons = idx; 2161 } 2162 2163 void 2164 sk_tick(void *xsc_if) 2165 { 2166 struct sk_if_softc *sc_if = xsc_if; 2167 struct mii_data *mii = &sc_if->sk_mii; 2168 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2169 int i; 2170 2171 DPRINTFN(3, ("sk_tick\n")); 2172 2173 if (!(ifp->if_flags & IFF_UP)) 2174 return; 2175 2176 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2177 sk_intr_bcom(sc_if); 2178 return; 2179 } 2180 2181 /* 2182 * According to SysKonnect, the correct way to verify that 2183 * the link has come back up is to poll bit 0 of the GPIO 2184 * register three times. This pin has the signal from the 2185 * link sync pin connected to it; if we read the same link 2186 * state 3 times in a row, we know the link is up. 2187 */ 2188 for (i = 0; i < 3; i++) { 2189 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2190 break; 2191 } 2192 2193 if (i != 3) { 2194 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2195 return; 2196 } 2197 2198 /* Turn the GP0 interrupt back on. */ 2199 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2200 SK_XM_READ_2(sc_if, XM_ISR); 2201 mii_tick(mii); 2202 mii_pollstat(mii); 2203 callout_stop(&sc_if->sk_tick_ch); 2204 } 2205 2206 void 2207 sk_intr_bcom(struct sk_if_softc *sc_if) 2208 { 2209 struct mii_data *mii = &sc_if->sk_mii; 2210 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2211 int status; 2212 2213 2214 DPRINTFN(3, ("sk_intr_bcom\n")); 2215 2216 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2217 2218 /* 2219 * Read the PHY interrupt register to make sure 2220 * we clear any pending interrupts. 2221 */ 2222 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2223 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2224 2225 if (!(ifp->if_flags & IFF_RUNNING)) { 2226 sk_init_xmac(sc_if); 2227 return; 2228 } 2229 2230 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2231 int lstat; 2232 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2233 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2234 2235 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2236 (void)mii_mediachg(mii); 2237 /* Turn off the link LED. */ 2238 SK_IF_WRITE_1(sc_if, 0, 2239 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2240 sc_if->sk_link = 0; 2241 } else if (status & BRGPHY_ISR_LNK_CHG) { 2242 sk_xmac_miibus_writereg((struct device *)sc_if, 2243 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2244 mii_tick(mii); 2245 sc_if->sk_link = 1; 2246 /* Turn on the link LED. */ 2247 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2248 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2249 SK_LINKLED_BLINK_OFF); 2250 mii_pollstat(mii); 2251 } else { 2252 mii_tick(mii); 2253 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2254 } 2255 } 2256 2257 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2258 } 2259 2260 void 2261 sk_intr_xmac(struct sk_if_softc *sc_if) 2262 { 2263 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2264 2265 DPRINTFN(3, ("sk_intr_xmac\n")); 2266 2267 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2268 if (status & XM_ISR_GP0_SET) { 2269 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2270 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2271 } 2272 2273 if (status & XM_ISR_AUTONEG_DONE) { 2274 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2275 } 2276 } 2277 2278 if (status & XM_IMR_TX_UNDERRUN) 2279 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2280 2281 if (status & XM_IMR_RX_OVERRUN) 2282 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2283 } 2284 2285 void 2286 sk_intr_yukon(struct sk_if_softc *sc_if) 2287 { 2288 int status; 2289 2290 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2291 2292 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2293 } 2294 2295 int 2296 sk_intr(void *xsc) 2297 { 2298 struct sk_softc *sc = xsc; 2299 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2300 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2301 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2302 u_int32_t status; 2303 int claimed = 0; 2304 2305 if (sc_if0 != NULL) 2306 ifp0 = &sc_if0->sk_ethercom.ec_if; 2307 if (sc_if1 != NULL) 2308 ifp1 = &sc_if1->sk_ethercom.ec_if; 2309 2310 for (;;) { 2311 status = CSR_READ_4(sc, SK_ISSR); 2312 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2313 2314 if (!(status & sc->sk_intrmask)) 2315 break; 2316 2317 claimed = 1; 2318 2319 /* Handle receive interrupts first. */ 2320 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2321 sk_rxeof(sc_if0); 2322 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2323 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2324 } 2325 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2326 sk_rxeof(sc_if1); 2327 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2328 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2329 } 2330 2331 /* Then transmit interrupts. */ 2332 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2333 sk_txeof(sc_if0); 2334 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2335 SK_TXBMU_CLR_IRQ_EOF); 2336 } 2337 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2338 sk_txeof(sc_if1); 2339 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2340 SK_TXBMU_CLR_IRQ_EOF); 2341 } 2342 2343 /* Then MAC interrupts. */ 2344 if (sc_if0 && (status & SK_ISR_MAC1) && 2345 (ifp0->if_flags & IFF_RUNNING)) { 2346 if (sc->sk_type == SK_GENESIS) 2347 sk_intr_xmac(sc_if0); 2348 else 2349 sk_intr_yukon(sc_if0); 2350 } 2351 2352 if (sc_if1 && (status & SK_ISR_MAC2) && 2353 (ifp1->if_flags & IFF_RUNNING)) { 2354 if (sc->sk_type == SK_GENESIS) 2355 sk_intr_xmac(sc_if1); 2356 else 2357 sk_intr_yukon(sc_if1); 2358 2359 } 2360 2361 if (status & SK_ISR_EXTERNAL_REG) { 2362 if (sc_if0 != NULL && 2363 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2364 sk_intr_bcom(sc_if0); 2365 2366 if (sc_if1 != NULL && 2367 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2368 sk_intr_bcom(sc_if1); 2369 } 2370 } 2371 2372 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2373 2374 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2375 sk_start(ifp0); 2376 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2377 sk_start(ifp1); 2378 2379 #if NRND > 0 2380 if (RND_ENABLED(&sc->rnd_source)) 2381 rnd_add_uint32(&sc->rnd_source, status); 2382 #endif 2383 2384 if (sc->sk_int_mod_pending) 2385 sk_update_int_mod(sc); 2386 2387 return claimed; 2388 } 2389 2390 void 2391 sk_init_xmac(struct sk_if_softc *sc_if) 2392 { 2393 struct sk_softc *sc = sc_if->sk_softc; 2394 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2395 static const struct sk_bcom_hack bhack[] = { 2396 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2397 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2398 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2399 { 0, 0 } }; 2400 2401 DPRINTFN(1, ("sk_init_xmac\n")); 2402 2403 /* Unreset the XMAC. */ 2404 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2405 DELAY(1000); 2406 2407 /* Reset the XMAC's internal state. */ 2408 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2409 2410 /* Save the XMAC II revision */ 2411 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2412 2413 /* 2414 * Perform additional initialization for external PHYs, 2415 * namely for the 1000baseTX cards that use the XMAC's 2416 * GMII mode. 2417 */ 2418 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2419 int i = 0; 2420 u_int32_t val; 2421 2422 /* Take PHY out of reset. */ 2423 val = sk_win_read_4(sc, SK_GPIO); 2424 if (sc_if->sk_port == SK_PORT_A) 2425 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2426 else 2427 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2428 sk_win_write_4(sc, SK_GPIO, val); 2429 2430 /* Enable GMII mode on the XMAC. */ 2431 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2432 2433 sk_xmac_miibus_writereg((struct device *)sc_if, 2434 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2435 DELAY(10000); 2436 sk_xmac_miibus_writereg((struct device *)sc_if, 2437 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2438 2439 /* 2440 * Early versions of the BCM5400 apparently have 2441 * a bug that requires them to have their reserved 2442 * registers initialized to some magic values. I don't 2443 * know what the numbers do, I'm just the messenger. 2444 */ 2445 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2446 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2447 while (bhack[i].reg) { 2448 sk_xmac_miibus_writereg((struct device *)sc_if, 2449 SK_PHYADDR_BCOM, bhack[i].reg, 2450 bhack[i].val); 2451 i++; 2452 } 2453 } 2454 } 2455 2456 /* Set station address */ 2457 SK_XM_WRITE_2(sc_if, XM_PAR0, 2458 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2459 SK_XM_WRITE_2(sc_if, XM_PAR1, 2460 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2461 SK_XM_WRITE_2(sc_if, XM_PAR2, 2462 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2463 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2464 2465 if (ifp->if_flags & IFF_PROMISC) 2466 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2467 else 2468 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2469 2470 if (ifp->if_flags & IFF_BROADCAST) 2471 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2472 else 2473 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2474 2475 /* We don't need the FCS appended to the packet. */ 2476 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2477 2478 /* We want short frames padded to 60 bytes. */ 2479 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2480 2481 /* 2482 * Enable the reception of all error frames. This is is 2483 * a necessary evil due to the design of the XMAC. The 2484 * XMAC's receive FIFO is only 8K in size, however jumbo 2485 * frames can be up to 9000 bytes in length. When bad 2486 * frame filtering is enabled, the XMAC's RX FIFO operates 2487 * in 'store and forward' mode. For this to work, the 2488 * entire frame has to fit into the FIFO, but that means 2489 * that jumbo frames larger than 8192 bytes will be 2490 * truncated. Disabling all bad frame filtering causes 2491 * the RX FIFO to operate in streaming mode, in which 2492 * case the XMAC will start transfering frames out of the 2493 * RX FIFO as soon as the FIFO threshold is reached. 2494 */ 2495 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2496 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2497 XM_MODE_RX_INRANGELEN); 2498 2499 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2500 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2501 else 2502 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2503 2504 /* 2505 * Bump up the transmit threshold. This helps hold off transmit 2506 * underruns when we're blasting traffic from both ports at once. 2507 */ 2508 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2509 2510 /* Set multicast filter */ 2511 sk_setmulti(sc_if); 2512 2513 /* Clear and enable interrupts */ 2514 SK_XM_READ_2(sc_if, XM_ISR); 2515 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2516 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2517 else 2518 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2519 2520 /* Configure MAC arbiter */ 2521 switch (sc_if->sk_xmac_rev) { 2522 case XM_XMAC_REV_B2: 2523 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2524 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2525 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2526 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2527 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2528 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2529 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2530 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2531 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2532 break; 2533 case XM_XMAC_REV_C1: 2534 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2535 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2536 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2537 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2538 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2539 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2540 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2541 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2542 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2543 break; 2544 default: 2545 break; 2546 } 2547 sk_win_write_2(sc, SK_MACARB_CTL, 2548 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2549 2550 sc_if->sk_link = 1; 2551 } 2552 2553 void sk_init_yukon(struct sk_if_softc *sc_if) 2554 { 2555 u_int32_t /*mac, */phy; 2556 u_int16_t reg; 2557 struct sk_softc *sc; 2558 int i; 2559 2560 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2561 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2562 2563 sc = sc_if->sk_softc; 2564 if (sc->sk_type == SK_YUKON_LITE && 2565 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2566 /* Take PHY out of reset. */ 2567 sk_win_write_4(sc, SK_GPIO, 2568 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2569 } 2570 2571 2572 /* GMAC and GPHY Reset */ 2573 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2574 2575 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2576 2577 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2578 DELAY(1000); 2579 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2580 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2581 DELAY(1000); 2582 2583 2584 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2585 2586 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2587 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2588 2589 switch (sc_if->sk_softc->sk_pmd) { 2590 case IFM_1000_SX: 2591 case IFM_1000_LX: 2592 phy |= SK_GPHY_FIBER; 2593 break; 2594 2595 case IFM_1000_CX: 2596 case IFM_1000_T: 2597 phy |= SK_GPHY_COPPER; 2598 break; 2599 } 2600 2601 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2602 2603 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2604 DELAY(1000); 2605 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2606 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2607 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2608 2609 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2610 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2611 2612 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2613 2614 /* unused read of the interrupt source register */ 2615 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2616 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2617 2618 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2619 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2620 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2621 2622 /* MIB Counter Clear Mode set */ 2623 reg |= YU_PAR_MIB_CLR; 2624 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2625 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2626 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2627 2628 /* MIB Counter Clear Mode clear */ 2629 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2630 reg &= ~YU_PAR_MIB_CLR; 2631 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2632 2633 /* receive control reg */ 2634 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2635 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2636 YU_RCR_CRCR); 2637 2638 /* transmit parameter register */ 2639 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2640 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2641 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2642 2643 /* serial mode register */ 2644 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2645 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2646 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2647 YU_SMR_IPG_DATA(0x1e)); 2648 2649 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2650 /* Setup Yukon's address */ 2651 for (i = 0; i < 3; i++) { 2652 /* Write Source Address 1 (unicast filter) */ 2653 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2654 sc_if->sk_enaddr[i * 2] | 2655 sc_if->sk_enaddr[i * 2 + 1] << 8); 2656 } 2657 2658 for (i = 0; i < 3; i++) { 2659 reg = sk_win_read_2(sc_if->sk_softc, 2660 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2661 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2662 } 2663 2664 /* Set multicast filter */ 2665 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2666 sk_setmulti(sc_if); 2667 2668 /* enable interrupt mask for counter overflows */ 2669 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2670 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2671 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2672 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2673 2674 /* Configure RX MAC FIFO */ 2675 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2676 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2677 2678 /* Configure TX MAC FIFO */ 2679 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2680 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2681 2682 DPRINTFN(6, ("sk_init_yukon: end\n")); 2683 } 2684 2685 /* 2686 * Note that to properly initialize any part of the GEnesis chip, 2687 * you first have to take it out of reset mode. 2688 */ 2689 int 2690 sk_init(struct ifnet *ifp) 2691 { 2692 struct sk_if_softc *sc_if = ifp->if_softc; 2693 struct sk_softc *sc = sc_if->sk_softc; 2694 struct mii_data *mii = &sc_if->sk_mii; 2695 int rc = 0, s; 2696 u_int32_t imr, imtimer_ticks; 2697 2698 DPRINTFN(1, ("sk_init\n")); 2699 2700 s = splnet(); 2701 2702 if (ifp->if_flags & IFF_RUNNING) { 2703 splx(s); 2704 return 0; 2705 } 2706 2707 /* Cancel pending I/O and free all RX/TX buffers. */ 2708 sk_stop(ifp,0); 2709 2710 if (sc->sk_type == SK_GENESIS) { 2711 /* Configure LINK_SYNC LED */ 2712 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2713 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2714 SK_LINKLED_LINKSYNC_ON); 2715 2716 /* Configure RX LED */ 2717 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2718 SK_RXLEDCTL_COUNTER_START); 2719 2720 /* Configure TX LED */ 2721 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2722 SK_TXLEDCTL_COUNTER_START); 2723 } 2724 2725 /* Configure I2C registers */ 2726 2727 /* Configure XMAC(s) */ 2728 switch (sc->sk_type) { 2729 case SK_GENESIS: 2730 sk_init_xmac(sc_if); 2731 break; 2732 case SK_YUKON: 2733 case SK_YUKON_LITE: 2734 case SK_YUKON_LP: 2735 sk_init_yukon(sc_if); 2736 break; 2737 } 2738 if ((rc = mii_mediachg(mii)) == ENXIO) 2739 rc = 0; 2740 else if (rc != 0) 2741 goto out; 2742 2743 if (sc->sk_type == SK_GENESIS) { 2744 /* Configure MAC FIFOs */ 2745 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2746 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2747 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2748 2749 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2750 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2751 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2752 } 2753 2754 /* Configure transmit arbiter(s) */ 2755 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2756 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2757 2758 /* Configure RAMbuffers */ 2759 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2760 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2761 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2762 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2763 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2764 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2765 2766 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2767 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2768 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2769 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2770 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2771 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2772 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2773 2774 /* Configure BMUs */ 2775 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2776 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2777 SK_RX_RING_ADDR(sc_if, 0)); 2778 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2779 2780 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2781 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2782 SK_TX_RING_ADDR(sc_if, 0)); 2783 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2784 2785 /* Init descriptors */ 2786 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2787 aprint_error("%s: initialization failed: no " 2788 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2789 sk_stop(ifp,0); 2790 splx(s); 2791 return ENOBUFS; 2792 } 2793 2794 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2795 aprint_error("%s: initialization failed: no " 2796 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2797 sk_stop(ifp,0); 2798 splx(s); 2799 return ENOBUFS; 2800 } 2801 2802 /* Set interrupt moderation if changed via sysctl. */ 2803 switch (sc->sk_type) { 2804 case SK_GENESIS: 2805 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2806 break; 2807 case SK_YUKON_EC: 2808 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2809 break; 2810 default: 2811 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2812 } 2813 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2814 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2815 sk_win_write_4(sc, SK_IMTIMERINIT, 2816 SK_IM_USECS(sc->sk_int_mod)); 2817 aprint_verbose("%s: interrupt moderation is %d us\n", 2818 sc->sk_dev.dv_xname, sc->sk_int_mod); 2819 } 2820 2821 /* Configure interrupt handling */ 2822 CSR_READ_4(sc, SK_ISSR); 2823 if (sc_if->sk_port == SK_PORT_A) 2824 sc->sk_intrmask |= SK_INTRS1; 2825 else 2826 sc->sk_intrmask |= SK_INTRS2; 2827 2828 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2829 2830 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2831 2832 /* Start BMUs. */ 2833 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2834 2835 if (sc->sk_type == SK_GENESIS) { 2836 /* Enable XMACs TX and RX state machines */ 2837 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2838 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2839 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2840 } 2841 2842 if (SK_YUKON_FAMILY(sc->sk_type)) { 2843 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2844 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2845 #if 0 2846 /* XXX disable 100Mbps and full duplex mode? */ 2847 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2848 #endif 2849 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2850 } 2851 2852 2853 ifp->if_flags |= IFF_RUNNING; 2854 ifp->if_flags &= ~IFF_OACTIVE; 2855 2856 out: 2857 splx(s); 2858 return rc; 2859 } 2860 2861 void 2862 sk_stop(struct ifnet *ifp, int disable) 2863 { 2864 struct sk_if_softc *sc_if = ifp->if_softc; 2865 struct sk_softc *sc = sc_if->sk_softc; 2866 int i; 2867 2868 DPRINTFN(1, ("sk_stop\n")); 2869 2870 callout_stop(&sc_if->sk_tick_ch); 2871 2872 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2873 u_int32_t val; 2874 2875 /* Put PHY back into reset. */ 2876 val = sk_win_read_4(sc, SK_GPIO); 2877 if (sc_if->sk_port == SK_PORT_A) { 2878 val |= SK_GPIO_DIR0; 2879 val &= ~SK_GPIO_DAT0; 2880 } else { 2881 val |= SK_GPIO_DIR2; 2882 val &= ~SK_GPIO_DAT2; 2883 } 2884 sk_win_write_4(sc, SK_GPIO, val); 2885 } 2886 2887 /* Turn off various components of this interface. */ 2888 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2889 switch (sc->sk_type) { 2890 case SK_GENESIS: 2891 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2892 SK_TXMACCTL_XMAC_RESET); 2893 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2894 break; 2895 case SK_YUKON: 2896 case SK_YUKON_LITE: 2897 case SK_YUKON_LP: 2898 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2899 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2900 break; 2901 } 2902 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2903 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2904 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2905 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2906 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2907 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2908 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2909 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2910 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2911 2912 /* Disable interrupts */ 2913 if (sc_if->sk_port == SK_PORT_A) 2914 sc->sk_intrmask &= ~SK_INTRS1; 2915 else 2916 sc->sk_intrmask &= ~SK_INTRS2; 2917 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2918 2919 SK_XM_READ_2(sc_if, XM_ISR); 2920 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2921 2922 /* Free RX and TX mbufs still in the queues. */ 2923 for (i = 0; i < SK_RX_RING_CNT; i++) { 2924 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2925 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2926 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2927 } 2928 } 2929 2930 for (i = 0; i < SK_TX_RING_CNT; i++) { 2931 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2932 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2933 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2934 } 2935 } 2936 2937 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2938 } 2939 2940 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2941 2942 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2943 2944 #ifdef SK_DEBUG 2945 void 2946 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2947 { 2948 #define DESC_PRINT(X) \ 2949 if (X) \ 2950 printf("txdesc[%d]." #X "=%#x\n", \ 2951 idx, X); 2952 2953 DESC_PRINT(le32toh(desc->sk_ctl)); 2954 DESC_PRINT(le32toh(desc->sk_next)); 2955 DESC_PRINT(le32toh(desc->sk_data_lo)); 2956 DESC_PRINT(le32toh(desc->sk_data_hi)); 2957 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2958 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2959 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2960 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2961 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2962 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2963 #undef PRINT 2964 } 2965 2966 void 2967 sk_dump_bytes(const char *data, int len) 2968 { 2969 int c, i, j; 2970 2971 for (i = 0; i < len; i += 16) { 2972 printf("%08x ", i); 2973 c = len - i; 2974 if (c > 16) c = 16; 2975 2976 for (j = 0; j < c; j++) { 2977 printf("%02x ", data[i + j] & 0xff); 2978 if ((j & 0xf) == 7 && j > 0) 2979 printf(" "); 2980 } 2981 2982 for (; j < 16; j++) 2983 printf(" "); 2984 printf(" "); 2985 2986 for (j = 0; j < c; j++) { 2987 int ch = data[i + j] & 0xff; 2988 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2989 } 2990 2991 printf("\n"); 2992 2993 if (c < 16) 2994 break; 2995 } 2996 } 2997 2998 void 2999 sk_dump_mbuf(struct mbuf *m) 3000 { 3001 int count = m->m_pkthdr.len; 3002 3003 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3004 3005 while (count > 0 && m) { 3006 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3007 m, m->m_data, m->m_len); 3008 sk_dump_bytes(mtod(m, char *), m->m_len); 3009 3010 count -= m->m_len; 3011 m = m->m_next; 3012 } 3013 } 3014 #endif 3015 3016 static int 3017 sk_sysctl_handler(SYSCTLFN_ARGS) 3018 { 3019 int error, t; 3020 struct sysctlnode node; 3021 struct sk_softc *sc; 3022 3023 node = *rnode; 3024 sc = node.sysctl_data; 3025 t = sc->sk_int_mod; 3026 node.sysctl_data = &t; 3027 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3028 if (error || newp == NULL) 3029 return error; 3030 3031 if (t < SK_IM_MIN || t > SK_IM_MAX) 3032 return EINVAL; 3033 3034 /* update the softc with sysctl-changed value, and mark 3035 for hardware update */ 3036 sc->sk_int_mod = t; 3037 sc->sk_int_mod_pending = 1; 3038 return 0; 3039 } 3040 3041 /* 3042 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3043 * set up in skc_attach() 3044 */ 3045 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3046 { 3047 int rc; 3048 const struct sysctlnode *node; 3049 3050 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3051 0, CTLTYPE_NODE, "hw", NULL, 3052 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3053 goto err; 3054 } 3055 3056 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3057 0, CTLTYPE_NODE, "sk", 3058 SYSCTL_DESCR("sk interface controls"), 3059 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3060 goto err; 3061 } 3062 3063 sk_root_num = node->sysctl_num; 3064 return; 3065 3066 err: 3067 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3068 } 3069
Indexes created Tue Sep 23 23:09:58 GMT 2025