if_sk.c revision 1.47
1 /* $NetBSD: if_sk.c,v 1.47 2008/02/07 01:21:57 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include <sys/cdefs.h> 125 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.47 2008/02/07 01:21:57 dyoung Exp $"); 126 127 #include "bpfilter.h" 128 #include "rnd.h" 129 130 #include <sys/param.h> 131 #include <sys/systm.h> 132 #include <sys/sockio.h> 133 #include <sys/mbuf.h> 134 #include <sys/malloc.h> 135 #include <sys/kernel.h> 136 #include <sys/socket.h> 137 #include <sys/device.h> 138 #include <sys/queue.h> 139 #include <sys/callout.h> 140 #include <sys/sysctl.h> 141 #include <sys/endian.h> 142 143 #include <net/if.h> 144 #include <net/if_dl.h> 145 #include <net/if_types.h> 146 147 #include <net/if_media.h> 148 149 #if NBPFILTER > 0 150 #include <net/bpf.h> 151 #endif 152 #if NRND > 0 153 #include <sys/rnd.h> 154 #endif 155 156 #include <dev/mii/mii.h> 157 #include <dev/mii/miivar.h> 158 #include <dev/mii/brgphyreg.h> 159 160 #include <dev/pci/pcireg.h> 161 #include <dev/pci/pcivar.h> 162 #include <dev/pci/pcidevs.h> 163 164 /* #define SK_USEIOSPACE */ 165 166 #include <dev/pci/if_skreg.h> 167 #include <dev/pci/if_skvar.h> 168 169 int skc_probe(struct device *, struct cfdata *, void *); 170 void skc_attach(struct device *, struct device *self, void *aux); 171 int sk_probe(struct device *, struct cfdata *, void *); 172 void sk_attach(struct device *, struct device *self, void *aux); 173 int skcprint(void *, const char *); 174 int sk_intr(void *); 175 void sk_intr_bcom(struct sk_if_softc *); 176 void sk_intr_xmac(struct sk_if_softc *); 177 void sk_intr_yukon(struct sk_if_softc *); 178 void sk_rxeof(struct sk_if_softc *); 179 void sk_txeof(struct sk_if_softc *); 180 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 181 void sk_start(struct ifnet *); 182 int sk_ioctl(struct ifnet *, u_long, void *); 183 int sk_init(struct ifnet *); 184 void sk_init_xmac(struct sk_if_softc *); 185 void sk_init_yukon(struct sk_if_softc *); 186 void sk_stop(struct ifnet *, int); 187 void sk_watchdog(struct ifnet *); 188 void sk_shutdown(void *); 189 int sk_ifmedia_upd(struct ifnet *); 190 void sk_reset(struct sk_softc *); 191 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 192 int sk_alloc_jumbo_mem(struct sk_if_softc *); 193 void sk_free_jumbo_mem(struct sk_if_softc *); 194 void *sk_jalloc(struct sk_if_softc *); 195 void sk_jfree(struct mbuf *, void *, size_t, void *); 196 int sk_init_rx_ring(struct sk_if_softc *); 197 int sk_init_tx_ring(struct sk_if_softc *); 198 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 199 void sk_vpd_read_res(struct sk_softc *, 200 struct vpd_res *, int); 201 void sk_vpd_read(struct sk_softc *); 202 203 void sk_update_int_mod(struct sk_softc *); 204 205 int sk_xmac_miibus_readreg(struct device *, int, int); 206 void sk_xmac_miibus_writereg(struct device *, int, int, int); 207 void sk_xmac_miibus_statchg(struct device *); 208 209 int sk_marv_miibus_readreg(struct device *, int, int); 210 void sk_marv_miibus_writereg(struct device *, int, int, int); 211 void sk_marv_miibus_statchg(struct device *); 212 213 u_int32_t sk_xmac_hash(void *); 214 u_int32_t sk_yukon_hash(void *); 215 void sk_setfilt(struct sk_if_softc *, void *, int); 216 void sk_setmulti(struct sk_if_softc *); 217 void sk_tick(void *); 218 219 /* #define SK_DEBUG 2 */ 220 #ifdef SK_DEBUG 221 #define DPRINTF(x) if (skdebug) printf x 222 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 223 int skdebug = SK_DEBUG; 224 225 void sk_dump_txdesc(struct sk_tx_desc *, int); 226 void sk_dump_mbuf(struct mbuf *); 227 void sk_dump_bytes(const char *, int); 228 #else 229 #define DPRINTF(x) 230 #define DPRINTFN(n,x) 231 #endif 232 233 static int sk_sysctl_handler(SYSCTLFN_PROTO); 234 static int sk_root_num; 235 236 /* supported device vendors */ 237 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 238 static const struct sk_product { 239 pci_vendor_id_t sk_vendor; 240 pci_product_id_t sk_product; 241 } sk_products[] = { 242 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 243 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 244 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 245 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 246 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 247 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 248 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 249 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 250 { 0, 0, } 251 }; 252 253 #define SK_LINKSYS_EG1032_SUBID 0x00151737 254 255 static inline u_int32_t 256 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 257 { 258 #ifdef SK_USEIOSPACE 259 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 260 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 261 #else 262 return CSR_READ_4(sc, reg); 263 #endif 264 } 265 266 static inline u_int16_t 267 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 268 { 269 #ifdef SK_USEIOSPACE 270 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 271 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 272 #else 273 return CSR_READ_2(sc, reg); 274 #endif 275 } 276 277 static inline u_int8_t 278 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 279 { 280 #ifdef SK_USEIOSPACE 281 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 282 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 283 #else 284 return CSR_READ_1(sc, reg); 285 #endif 286 } 287 288 static inline void 289 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 290 { 291 #ifdef SK_USEIOSPACE 292 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 293 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 294 #else 295 CSR_WRITE_4(sc, reg, x); 296 #endif 297 } 298 299 static inline void 300 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 301 { 302 #ifdef SK_USEIOSPACE 303 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 304 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 305 #else 306 CSR_WRITE_2(sc, reg, x); 307 #endif 308 } 309 310 static inline void 311 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 312 { 313 #ifdef SK_USEIOSPACE 314 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 315 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 316 #else 317 CSR_WRITE_1(sc, reg, x); 318 #endif 319 } 320 321 /* 322 * The VPD EEPROM contains Vital Product Data, as suggested in 323 * the PCI 2.1 specification. The VPD data is separared into areas 324 * denoted by resource IDs. The SysKonnect VPD contains an ID string 325 * resource (the name of the adapter), a read-only area resource 326 * containing various key/data fields and a read/write area which 327 * can be used to store asset management information or log messages. 328 * We read the ID string and read-only into buffers attached to 329 * the controller softc structure for later use. At the moment, 330 * we only use the ID string during sk_attach(). 331 */ 332 u_int8_t 333 sk_vpd_readbyte(struct sk_softc *sc, int addr) 334 { 335 int i; 336 337 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 338 for (i = 0; i < SK_TIMEOUT; i++) { 339 DELAY(1); 340 if (sk_win_read_2(sc, 341 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 342 break; 343 } 344 345 if (i == SK_TIMEOUT) 346 return 0; 347 348 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 349 } 350 351 void 352 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 353 { 354 int i; 355 u_int8_t *ptr; 356 357 ptr = (u_int8_t *)res; 358 for (i = 0; i < sizeof(struct vpd_res); i++) 359 ptr[i] = sk_vpd_readbyte(sc, i + addr); 360 } 361 362 void 363 sk_vpd_read(struct sk_softc *sc) 364 { 365 int pos = 0, i; 366 struct vpd_res res; 367 368 if (sc->sk_vpd_prodname != NULL) 369 free(sc->sk_vpd_prodname, M_DEVBUF); 370 if (sc->sk_vpd_readonly != NULL) 371 free(sc->sk_vpd_readonly, M_DEVBUF); 372 sc->sk_vpd_prodname = NULL; 373 sc->sk_vpd_readonly = NULL; 374 375 sk_vpd_read_res(sc, &res, pos); 376 377 if (res.vr_id != VPD_RES_ID) { 378 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 379 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 380 return; 381 } 382 383 pos += sizeof(res); 384 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 385 if (sc->sk_vpd_prodname == NULL) 386 panic("sk_vpd_read"); 387 for (i = 0; i < res.vr_len; i++) 388 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 389 sc->sk_vpd_prodname[i] = '\0'; 390 pos += i; 391 392 sk_vpd_read_res(sc, &res, pos); 393 394 if (res.vr_id != VPD_RES_READ) { 395 aprint_error("%s: bad VPD resource id: expected %x got %x\n", 396 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 397 return; 398 } 399 400 pos += sizeof(res); 401 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 402 if (sc->sk_vpd_readonly == NULL) 403 panic("sk_vpd_read"); 404 for (i = 0; i < res.vr_len ; i++) 405 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 406 } 407 408 int 409 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 410 { 411 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 412 int i; 413 414 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 415 416 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 417 return 0; 418 419 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 420 SK_XM_READ_2(sc_if, XM_PHY_DATA); 421 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 422 for (i = 0; i < SK_TIMEOUT; i++) { 423 DELAY(1); 424 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 425 XM_MMUCMD_PHYDATARDY) 426 break; 427 } 428 429 if (i == SK_TIMEOUT) { 430 aprint_error("%s: phy failed to come ready\n", 431 sc_if->sk_dev.dv_xname); 432 return 0; 433 } 434 } 435 DELAY(1); 436 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 437 } 438 439 void 440 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 441 { 442 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 443 int i; 444 445 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 446 447 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 448 for (i = 0; i < SK_TIMEOUT; i++) { 449 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 450 break; 451 } 452 453 if (i == SK_TIMEOUT) { 454 aprint_error("%s: phy failed to come ready\n", 455 sc_if->sk_dev.dv_xname); 456 return; 457 } 458 459 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 460 for (i = 0; i < SK_TIMEOUT; i++) { 461 DELAY(1); 462 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 463 break; 464 } 465 466 if (i == SK_TIMEOUT) 467 aprint_error("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 468 } 469 470 void 471 sk_xmac_miibus_statchg(struct device *dev) 472 { 473 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 474 struct mii_data *mii = &sc_if->sk_mii; 475 476 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 477 478 /* 479 * If this is a GMII PHY, manually set the XMAC's 480 * duplex mode accordingly. 481 */ 482 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 483 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 484 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 485 else 486 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 487 } 488 } 489 490 int 491 sk_marv_miibus_readreg(struct device *dev, int phy, int reg) 492 { 493 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 494 u_int16_t val; 495 int i; 496 497 if (phy != 0 || 498 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 499 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 500 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 501 phy, reg)); 502 return 0; 503 } 504 505 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 506 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 507 508 for (i = 0; i < SK_TIMEOUT; i++) { 509 DELAY(1); 510 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 511 if (val & YU_SMICR_READ_VALID) 512 break; 513 } 514 515 if (i == SK_TIMEOUT) { 516 aprint_error("%s: phy failed to come ready\n", 517 sc_if->sk_dev.dv_xname); 518 return 0; 519 } 520 521 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 522 SK_TIMEOUT)); 523 524 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 525 526 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 527 phy, reg, val)); 528 529 return val; 530 } 531 532 void 533 sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 534 { 535 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 536 int i; 537 538 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 539 phy, reg, val)); 540 541 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 542 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 543 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 544 545 for (i = 0; i < SK_TIMEOUT; i++) { 546 DELAY(1); 547 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 548 break; 549 } 550 551 if (i == SK_TIMEOUT) 552 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 553 } 554 555 void 556 sk_marv_miibus_statchg(struct device *dev) 557 { 558 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 559 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 560 } 561 562 #define SK_HASH_BITS 6 563 564 u_int32_t 565 sk_xmac_hash(void *addr) 566 { 567 u_int32_t crc; 568 569 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 570 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 571 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 572 return crc; 573 } 574 575 u_int32_t 576 sk_yukon_hash(void *addr) 577 { 578 u_int32_t crc; 579 580 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 581 crc &= ((1 << SK_HASH_BITS) - 1); 582 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 583 return crc; 584 } 585 586 void 587 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 588 { 589 char *addr = addrv; 590 int base = XM_RXFILT_ENTRY(slot); 591 592 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 593 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 594 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 595 } 596 597 void 598 sk_setmulti(struct sk_if_softc *sc_if) 599 { 600 struct sk_softc *sc = sc_if->sk_softc; 601 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 602 u_int32_t hashes[2] = { 0, 0 }; 603 int h = 0, i; 604 struct ethercom *ec = &sc_if->sk_ethercom; 605 struct ether_multi *enm; 606 struct ether_multistep step; 607 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 608 609 /* First, zot all the existing filters. */ 610 switch (sc->sk_type) { 611 case SK_GENESIS: 612 for (i = 1; i < XM_RXFILT_MAX; i++) 613 sk_setfilt(sc_if, (void *)&dummy, i); 614 615 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 616 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 617 break; 618 case SK_YUKON: 619 case SK_YUKON_LITE: 620 case SK_YUKON_LP: 621 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 622 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 623 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 624 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 625 break; 626 } 627 628 /* Now program new ones. */ 629 allmulti: 630 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 631 hashes[0] = 0xFFFFFFFF; 632 hashes[1] = 0xFFFFFFFF; 633 } else { 634 i = 1; 635 /* First find the tail of the list. */ 636 ETHER_FIRST_MULTI(step, ec, enm); 637 while (enm != NULL) { 638 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 639 ETHER_ADDR_LEN)) { 640 ifp->if_flags |= IFF_ALLMULTI; 641 goto allmulti; 642 } 643 DPRINTFN(2,("multicast address %s\n", 644 ether_sprintf(enm->enm_addrlo))); 645 /* 646 * Program the first XM_RXFILT_MAX multicast groups 647 * into the perfect filter. For all others, 648 * use the hash table. 649 */ 650 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 651 sk_setfilt(sc_if, enm->enm_addrlo, i); 652 i++; 653 } 654 else { 655 switch (sc->sk_type) { 656 case SK_GENESIS: 657 h = sk_xmac_hash(enm->enm_addrlo); 658 break; 659 case SK_YUKON: 660 case SK_YUKON_LITE: 661 case SK_YUKON_LP: 662 h = sk_yukon_hash(enm->enm_addrlo); 663 break; 664 } 665 if (h < 32) 666 hashes[0] |= (1 << h); 667 else 668 hashes[1] |= (1 << (h - 32)); 669 } 670 671 ETHER_NEXT_MULTI(step, enm); 672 } 673 } 674 675 switch (sc->sk_type) { 676 case SK_GENESIS: 677 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 678 XM_MODE_RX_USE_PERFECT); 679 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 680 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 681 break; 682 case SK_YUKON: 683 case SK_YUKON_LITE: 684 case SK_YUKON_LP: 685 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 686 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 687 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 688 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 689 break; 690 } 691 } 692 693 int 694 sk_init_rx_ring(struct sk_if_softc *sc_if) 695 { 696 struct sk_chain_data *cd = &sc_if->sk_cdata; 697 struct sk_ring_data *rd = sc_if->sk_rdata; 698 int i; 699 700 bzero((char *)rd->sk_rx_ring, 701 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 702 703 for (i = 0; i < SK_RX_RING_CNT; i++) { 704 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 705 if (i == (SK_RX_RING_CNT - 1)) { 706 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 707 rd->sk_rx_ring[i].sk_next = 708 htole32(SK_RX_RING_ADDR(sc_if, 0)); 709 } else { 710 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 711 rd->sk_rx_ring[i].sk_next = 712 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 713 } 714 } 715 716 for (i = 0; i < SK_RX_RING_CNT; i++) { 717 if (sk_newbuf(sc_if, i, NULL, 718 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 719 aprint_error("%s: failed alloc of %dth mbuf\n", 720 sc_if->sk_dev.dv_xname, i); 721 return ENOBUFS; 722 } 723 } 724 sc_if->sk_cdata.sk_rx_prod = 0; 725 sc_if->sk_cdata.sk_rx_cons = 0; 726 727 return 0; 728 } 729 730 int 731 sk_init_tx_ring(struct sk_if_softc *sc_if) 732 { 733 struct sk_chain_data *cd = &sc_if->sk_cdata; 734 struct sk_ring_data *rd = sc_if->sk_rdata; 735 int i; 736 737 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 738 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 739 740 for (i = 0; i < SK_TX_RING_CNT; i++) { 741 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 742 if (i == (SK_TX_RING_CNT - 1)) { 743 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 744 rd->sk_tx_ring[i].sk_next = 745 htole32(SK_TX_RING_ADDR(sc_if, 0)); 746 } else { 747 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 748 rd->sk_tx_ring[i].sk_next = 749 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 750 } 751 } 752 753 sc_if->sk_cdata.sk_tx_prod = 0; 754 sc_if->sk_cdata.sk_tx_cons = 0; 755 sc_if->sk_cdata.sk_tx_cnt = 0; 756 757 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 758 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 759 760 return 0; 761 } 762 763 int 764 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 765 bus_dmamap_t dmamap) 766 { 767 struct mbuf *m_new = NULL; 768 struct sk_chain *c; 769 struct sk_rx_desc *r; 770 771 if (m == NULL) { 772 void *buf = NULL; 773 774 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 775 if (m_new == NULL) { 776 aprint_error("%s: no memory for rx list -- " 777 "packet dropped!\n", sc_if->sk_dev.dv_xname); 778 return ENOBUFS; 779 } 780 781 /* Allocate the jumbo buffer */ 782 buf = sk_jalloc(sc_if); 783 if (buf == NULL) { 784 m_freem(m_new); 785 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 786 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 787 return ENOBUFS; 788 } 789 790 /* Attach the buffer to the mbuf */ 791 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 792 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 793 794 } else { 795 /* 796 * We're re-using a previously allocated mbuf; 797 * be sure to re-init pointers and lengths to 798 * default values. 799 */ 800 m_new = m; 801 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 802 m_new->m_data = m_new->m_ext.ext_buf; 803 } 804 m_adj(m_new, ETHER_ALIGN); 805 806 c = &sc_if->sk_cdata.sk_rx_chain[i]; 807 r = c->sk_desc; 808 c->sk_mbuf = m_new; 809 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 810 (((vaddr_t)m_new->m_data 811 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 812 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 813 814 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 815 816 return 0; 817 } 818 819 /* 820 * Memory management for jumbo frames. 821 */ 822 823 int 824 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 825 { 826 struct sk_softc *sc = sc_if->sk_softc; 827 char *ptr, *kva; 828 bus_dma_segment_t seg; 829 int i, rseg, state, error; 830 struct sk_jpool_entry *entry; 831 832 state = error = 0; 833 834 /* Grab a big chunk o' storage. */ 835 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 836 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 837 aprint_error("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 838 return ENOBUFS; 839 } 840 841 state = 1; 842 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 843 BUS_DMA_NOWAIT)) { 844 aprint_error("%s: can't map dma buffers (%d bytes)\n", 845 sc->sk_dev.dv_xname, SK_JMEM); 846 error = ENOBUFS; 847 goto out; 848 } 849 850 state = 2; 851 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 852 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 853 aprint_error("%s: can't create dma map\n", sc->sk_dev.dv_xname); 854 error = ENOBUFS; 855 goto out; 856 } 857 858 state = 3; 859 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 860 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 861 aprint_error("%s: can't load dma map\n", sc->sk_dev.dv_xname); 862 error = ENOBUFS; 863 goto out; 864 } 865 866 state = 4; 867 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 868 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 869 870 LIST_INIT(&sc_if->sk_jfree_listhead); 871 LIST_INIT(&sc_if->sk_jinuse_listhead); 872 873 /* 874 * Now divide it up into 9K pieces and save the addresses 875 * in an array. 876 */ 877 ptr = sc_if->sk_cdata.sk_jumbo_buf; 878 for (i = 0; i < SK_JSLOTS; i++) { 879 sc_if->sk_cdata.sk_jslots[i] = ptr; 880 ptr += SK_JLEN; 881 entry = malloc(sizeof(struct sk_jpool_entry), 882 M_DEVBUF, M_NOWAIT); 883 if (entry == NULL) { 884 aprint_error("%s: no memory for jumbo buffer queue!\n", 885 sc->sk_dev.dv_xname); 886 error = ENOBUFS; 887 goto out; 888 } 889 entry->slot = i; 890 if (i) 891 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 892 entry, jpool_entries); 893 else 894 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 895 entry, jpool_entries); 896 } 897 out: 898 if (error != 0) { 899 switch (state) { 900 case 4: 901 bus_dmamap_unload(sc->sc_dmatag, 902 sc_if->sk_cdata.sk_rx_jumbo_map); 903 case 3: 904 bus_dmamap_destroy(sc->sc_dmatag, 905 sc_if->sk_cdata.sk_rx_jumbo_map); 906 case 2: 907 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 908 case 1: 909 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 910 break; 911 default: 912 break; 913 } 914 } 915 916 return error; 917 } 918 919 /* 920 * Allocate a jumbo buffer. 921 */ 922 void * 923 sk_jalloc(struct sk_if_softc *sc_if) 924 { 925 struct sk_jpool_entry *entry; 926 927 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 928 929 if (entry == NULL) 930 return NULL; 931 932 LIST_REMOVE(entry, jpool_entries); 933 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 934 return sc_if->sk_cdata.sk_jslots[entry->slot]; 935 } 936 937 /* 938 * Release a jumbo buffer. 939 */ 940 void 941 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 942 { 943 struct sk_jpool_entry *entry; 944 struct sk_if_softc *sc; 945 int i, s; 946 947 /* Extract the softc struct pointer. */ 948 sc = (struct sk_if_softc *)arg; 949 950 if (sc == NULL) 951 panic("sk_jfree: can't find softc pointer!"); 952 953 /* calculate the slot this buffer belongs to */ 954 955 i = ((vaddr_t)buf 956 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 957 958 if ((i < 0) || (i >= SK_JSLOTS)) 959 panic("sk_jfree: asked to free buffer that we don't manage!"); 960 961 s = splvm(); 962 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 963 if (entry == NULL) 964 panic("sk_jfree: buffer not in use!"); 965 entry->slot = i; 966 LIST_REMOVE(entry, jpool_entries); 967 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 968 969 if (__predict_true(m != NULL)) 970 pool_cache_put(mb_cache, m); 971 splx(s); 972 } 973 974 /* 975 * Set media options. 976 */ 977 int 978 sk_ifmedia_upd(struct ifnet *ifp) 979 { 980 struct sk_if_softc *sc_if = ifp->if_softc; 981 int rc; 982 983 (void) sk_init(ifp); 984 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 985 return 0; 986 return rc; 987 } 988 989 int 990 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 991 { 992 struct sk_if_softc *sc_if = ifp->if_softc; 993 struct sk_softc *sc = sc_if->sk_softc; 994 int s, error = 0; 995 996 /* DPRINTFN(2, ("sk_ioctl\n")); */ 997 998 s = splnet(); 999 1000 switch (command) { 1001 1002 case SIOCSIFFLAGS: 1003 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1004 if (ifp->if_flags & IFF_UP) { 1005 if (ifp->if_flags & IFF_RUNNING && 1006 ifp->if_flags & IFF_PROMISC && 1007 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1008 switch (sc->sk_type) { 1009 case SK_GENESIS: 1010 SK_XM_SETBIT_4(sc_if, XM_MODE, 1011 XM_MODE_RX_PROMISC); 1012 break; 1013 case SK_YUKON: 1014 case SK_YUKON_LITE: 1015 case SK_YUKON_LP: 1016 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1017 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1018 break; 1019 } 1020 sk_setmulti(sc_if); 1021 } else if (ifp->if_flags & IFF_RUNNING && 1022 !(ifp->if_flags & IFF_PROMISC) && 1023 sc_if->sk_if_flags & IFF_PROMISC) { 1024 switch (sc->sk_type) { 1025 case SK_GENESIS: 1026 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1027 XM_MODE_RX_PROMISC); 1028 break; 1029 case SK_YUKON: 1030 case SK_YUKON_LITE: 1031 case SK_YUKON_LP: 1032 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1033 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1034 break; 1035 } 1036 1037 sk_setmulti(sc_if); 1038 } else 1039 (void) sk_init(ifp); 1040 } else { 1041 if (ifp->if_flags & IFF_RUNNING) 1042 sk_stop(ifp,0); 1043 } 1044 sc_if->sk_if_flags = ifp->if_flags; 1045 error = 0; 1046 break; 1047 1048 default: 1049 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1050 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1051 break; 1052 1053 error = 0; 1054 1055 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1056 ; 1057 else if (ifp->if_flags & IFF_RUNNING) { 1058 sk_setmulti(sc_if); 1059 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1060 } 1061 break; 1062 } 1063 1064 splx(s); 1065 return error; 1066 } 1067 1068 void 1069 sk_update_int_mod(struct sk_softc *sc) 1070 { 1071 u_int32_t imtimer_ticks; 1072 1073 /* 1074 * Configure interrupt moderation. The moderation timer 1075 * defers interrupts specified in the interrupt moderation 1076 * timer mask based on the timeout specified in the interrupt 1077 * moderation timer init register. Each bit in the timer 1078 * register represents one tick, so to specify a timeout in 1079 * microseconds, we have to multiply by the correct number of 1080 * ticks-per-microsecond. 1081 */ 1082 switch (sc->sk_type) { 1083 case SK_GENESIS: 1084 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1085 break; 1086 case SK_YUKON_EC: 1087 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1088 break; 1089 default: 1090 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1091 } 1092 aprint_verbose("%s: interrupt moderation is %d us\n", 1093 sc->sk_dev.dv_xname, sc->sk_int_mod); 1094 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1095 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1096 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1097 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1098 sc->sk_int_mod_pending = 0; 1099 } 1100 1101 /* 1102 * Lookup: Check the PCI vendor and device, and return a pointer to 1103 * The structure if the IDs match against our list. 1104 */ 1105 1106 static const struct sk_product * 1107 sk_lookup(const struct pci_attach_args *pa) 1108 { 1109 const struct sk_product *psk; 1110 1111 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1112 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1113 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1114 return psk; 1115 } 1116 return NULL; 1117 } 1118 1119 /* 1120 * Probe for a SysKonnect GEnesis chip. 1121 */ 1122 1123 int 1124 skc_probe(struct device *parent, struct cfdata *match, 1125 void *aux) 1126 { 1127 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1128 const struct sk_product *psk; 1129 pcireg_t subid; 1130 1131 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1132 1133 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1134 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1135 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1136 subid == SK_LINKSYS_EG1032_SUBID) 1137 return 1; 1138 1139 if ((psk = sk_lookup(pa))) { 1140 return 1; 1141 } 1142 return 0; 1143 } 1144 1145 /* 1146 * Force the GEnesis into reset, then bring it out of reset. 1147 */ 1148 void sk_reset(struct sk_softc *sc) 1149 { 1150 DPRINTFN(2, ("sk_reset\n")); 1151 1152 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1153 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1154 if (SK_YUKON_FAMILY(sc->sk_type)) 1155 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1156 1157 DELAY(1000); 1158 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1159 DELAY(2); 1160 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1161 if (SK_YUKON_FAMILY(sc->sk_type)) 1162 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1163 1164 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1165 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1166 CSR_READ_2(sc, SK_LINK_CTRL))); 1167 1168 if (sc->sk_type == SK_GENESIS) { 1169 /* Configure packet arbiter */ 1170 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1171 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1172 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1173 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1174 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1175 } 1176 1177 /* Enable RAM interface */ 1178 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1179 1180 sk_update_int_mod(sc); 1181 } 1182 1183 int 1184 sk_probe(struct device *parent, struct cfdata *match, 1185 void *aux) 1186 { 1187 struct skc_attach_args *sa = aux; 1188 1189 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1190 return 0; 1191 1192 return 1; 1193 } 1194 1195 /* 1196 * Each XMAC chip is attached as a separate logical IP interface. 1197 * Single port cards will have only one logical interface of course. 1198 */ 1199 void 1200 sk_attach(struct device *parent, struct device *self, void *aux) 1201 { 1202 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1203 struct sk_softc *sc = (struct sk_softc *)parent; 1204 struct skc_attach_args *sa = aux; 1205 struct sk_txmap_entry *entry; 1206 struct ifnet *ifp; 1207 bus_dma_segment_t seg; 1208 bus_dmamap_t dmamap; 1209 void *kva; 1210 int i, rseg; 1211 1212 aprint_naive("\n"); 1213 1214 sc_if->sk_port = sa->skc_port; 1215 sc_if->sk_softc = sc; 1216 sc->sk_if[sa->skc_port] = sc_if; 1217 1218 if (sa->skc_port == SK_PORT_A) 1219 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1220 if (sa->skc_port == SK_PORT_B) 1221 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1222 1223 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1224 1225 /* 1226 * Get station address for this interface. Note that 1227 * dual port cards actually come with three station 1228 * addresses: one for each port, plus an extra. The 1229 * extra one is used by the SysKonnect driver software 1230 * as a 'virtual' station address for when both ports 1231 * are operating in failover mode. Currently we don't 1232 * use this extra address. 1233 */ 1234 for (i = 0; i < ETHER_ADDR_LEN; i++) 1235 sc_if->sk_enaddr[i] = 1236 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1237 1238 1239 aprint_normal(": Ethernet address %s\n", 1240 ether_sprintf(sc_if->sk_enaddr)); 1241 1242 /* 1243 * Set up RAM buffer addresses. The NIC will have a certain 1244 * amount of SRAM on it, somewhere between 512K and 2MB. We 1245 * need to divide this up a) between the transmitter and 1246 * receiver and b) between the two XMACs, if this is a 1247 * dual port NIC. Our algorithm is to divide up the memory 1248 * evenly so that everyone gets a fair share. 1249 */ 1250 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1251 u_int32_t chunk, val; 1252 1253 chunk = sc->sk_ramsize / 2; 1254 val = sc->sk_rboff / sizeof(u_int64_t); 1255 sc_if->sk_rx_ramstart = val; 1256 val += (chunk / sizeof(u_int64_t)); 1257 sc_if->sk_rx_ramend = val - 1; 1258 sc_if->sk_tx_ramstart = val; 1259 val += (chunk / sizeof(u_int64_t)); 1260 sc_if->sk_tx_ramend = val - 1; 1261 } else { 1262 u_int32_t chunk, val; 1263 1264 chunk = sc->sk_ramsize / 4; 1265 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1266 sizeof(u_int64_t); 1267 sc_if->sk_rx_ramstart = val; 1268 val += (chunk / sizeof(u_int64_t)); 1269 sc_if->sk_rx_ramend = val - 1; 1270 sc_if->sk_tx_ramstart = val; 1271 val += (chunk / sizeof(u_int64_t)); 1272 sc_if->sk_tx_ramend = val - 1; 1273 } 1274 1275 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1276 " tx_ramstart=%#x tx_ramend=%#x\n", 1277 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1278 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1279 1280 /* Read and save PHY type and set PHY address */ 1281 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1282 switch (sc_if->sk_phytype) { 1283 case SK_PHYTYPE_XMAC: 1284 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1285 break; 1286 case SK_PHYTYPE_BCOM: 1287 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1288 break; 1289 case SK_PHYTYPE_MARV_COPPER: 1290 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1291 break; 1292 default: 1293 aprint_error("%s: unsupported PHY type: %d\n", 1294 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1295 return; 1296 } 1297 1298 /* Allocate the descriptor queues. */ 1299 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1300 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1301 aprint_error("%s: can't alloc rx buffers\n", 1302 sc->sk_dev.dv_xname); 1303 goto fail; 1304 } 1305 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1306 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1307 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1308 sc_if->sk_dev.dv_xname, 1309 (u_long) sizeof(struct sk_ring_data)); 1310 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1311 goto fail; 1312 } 1313 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1314 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1315 &sc_if->sk_ring_map)) { 1316 aprint_error("%s: can't create dma map\n", 1317 sc_if->sk_dev.dv_xname); 1318 bus_dmamem_unmap(sc->sc_dmatag, kva, 1319 sizeof(struct sk_ring_data)); 1320 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1321 goto fail; 1322 } 1323 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1324 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1325 aprint_error("%s: can't load dma map\n", 1326 sc_if->sk_dev.dv_xname); 1327 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1328 bus_dmamem_unmap(sc->sc_dmatag, kva, 1329 sizeof(struct sk_ring_data)); 1330 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1331 goto fail; 1332 } 1333 1334 for (i = 0; i < SK_RX_RING_CNT; i++) 1335 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1336 1337 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1338 for (i = 0; i < SK_TX_RING_CNT; i++) { 1339 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1340 1341 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1342 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1343 aprint_error("%s: Can't create TX dmamap\n", 1344 sc_if->sk_dev.dv_xname); 1345 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1346 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1347 bus_dmamem_unmap(sc->sc_dmatag, kva, 1348 sizeof(struct sk_ring_data)); 1349 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1350 goto fail; 1351 } 1352 1353 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1354 if (!entry) { 1355 aprint_error("%s: Can't alloc txmap entry\n", 1356 sc_if->sk_dev.dv_xname); 1357 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1358 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1359 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1360 bus_dmamem_unmap(sc->sc_dmatag, kva, 1361 sizeof(struct sk_ring_data)); 1362 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1363 goto fail; 1364 } 1365 entry->dmamap = dmamap; 1366 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1367 } 1368 1369 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1370 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1371 1372 ifp = &sc_if->sk_ethercom.ec_if; 1373 /* Try to allocate memory for jumbo buffers. */ 1374 if (sk_alloc_jumbo_mem(sc_if)) { 1375 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1376 goto fail; 1377 } 1378 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1379 | ETHERCAP_JUMBO_MTU; 1380 1381 ifp->if_softc = sc_if; 1382 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1383 ifp->if_ioctl = sk_ioctl; 1384 ifp->if_start = sk_start; 1385 ifp->if_stop = sk_stop; 1386 ifp->if_init = sk_init; 1387 ifp->if_watchdog = sk_watchdog; 1388 ifp->if_capabilities = 0; 1389 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1390 IFQ_SET_READY(&ifp->if_snd); 1391 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1392 1393 /* 1394 * Do miibus setup. 1395 */ 1396 switch (sc->sk_type) { 1397 case SK_GENESIS: 1398 sk_init_xmac(sc_if); 1399 break; 1400 case SK_YUKON: 1401 case SK_YUKON_LITE: 1402 case SK_YUKON_LP: 1403 sk_init_yukon(sc_if); 1404 break; 1405 default: 1406 aprint_error("%s: unknown device type %d\n", 1407 sc->sk_dev.dv_xname, sc->sk_type); 1408 goto fail; 1409 } 1410 1411 DPRINTFN(2, ("sk_attach: 1\n")); 1412 1413 sc_if->sk_mii.mii_ifp = ifp; 1414 switch (sc->sk_type) { 1415 case SK_GENESIS: 1416 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1417 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1418 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1419 break; 1420 case SK_YUKON: 1421 case SK_YUKON_LITE: 1422 case SK_YUKON_LP: 1423 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1424 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1425 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1426 break; 1427 } 1428 1429 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1430 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1431 sk_ifmedia_upd, ether_mediastatus); 1432 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1433 MII_OFFSET_ANY, 0); 1434 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1435 aprint_error("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1436 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1437 0, NULL); 1438 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1439 } else 1440 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1441 1442 callout_init(&sc_if->sk_tick_ch, 0); 1443 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1444 1445 DPRINTFN(2, ("sk_attach: 1\n")); 1446 1447 /* 1448 * Call MI attach routines. 1449 */ 1450 if_attach(ifp); 1451 1452 ether_ifattach(ifp, sc_if->sk_enaddr); 1453 1454 #if NRND > 0 1455 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1456 RND_TYPE_NET, 0); 1457 #endif 1458 1459 DPRINTFN(2, ("sk_attach: end\n")); 1460 1461 return; 1462 1463 fail: 1464 sc->sk_if[sa->skc_port] = NULL; 1465 } 1466 1467 int 1468 skcprint(void *aux, const char *pnp) 1469 { 1470 struct skc_attach_args *sa = aux; 1471 1472 if (pnp) 1473 aprint_normal("sk port %c at %s", 1474 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1475 else 1476 aprint_normal(" port %c", 1477 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1478 return UNCONF; 1479 } 1480 1481 /* 1482 * Attach the interface. Allocate softc structures, do ifmedia 1483 * setup and ethernet/BPF attach. 1484 */ 1485 void 1486 skc_attach(struct device *parent, struct device *self, void *aux) 1487 { 1488 struct sk_softc *sc = (struct sk_softc *)self; 1489 struct pci_attach_args *pa = aux; 1490 struct skc_attach_args skca; 1491 pci_chipset_tag_t pc = pa->pa_pc; 1492 #ifndef SK_USEIOSPACE 1493 pcireg_t memtype; 1494 #endif 1495 pci_intr_handle_t ih; 1496 const char *intrstr = NULL; 1497 bus_addr_t iobase; 1498 bus_size_t iosize; 1499 int rc, sk_nodenum; 1500 u_int32_t command; 1501 const char *revstr; 1502 const struct sysctlnode *node; 1503 1504 aprint_naive("\n"); 1505 1506 DPRINTFN(2, ("begin skc_attach\n")); 1507 1508 /* 1509 * Handle power management nonsense. 1510 */ 1511 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1512 1513 if (command == 0x01) { 1514 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1515 if (command & SK_PSTATE_MASK) { 1516 u_int32_t xiobase, membase, irq; 1517 1518 /* Save important PCI config data. */ 1519 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1520 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1521 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1522 1523 /* Reset the power state. */ 1524 aprint_normal("%s chip is in D%d power mode " 1525 "-- setting to D0\n", sc->sk_dev.dv_xname, 1526 command & SK_PSTATE_MASK); 1527 command &= 0xFFFFFFFC; 1528 pci_conf_write(pc, pa->pa_tag, 1529 SK_PCI_PWRMGMTCTRL, command); 1530 1531 /* Restore PCI config data. */ 1532 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1533 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1534 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1535 } 1536 } 1537 1538 /* 1539 * Map control/status registers. 1540 */ 1541 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1542 command |= PCI_COMMAND_IO_ENABLE | 1543 PCI_COMMAND_MEM_ENABLE | 1544 PCI_COMMAND_MASTER_ENABLE; 1545 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1546 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1547 1548 #ifdef SK_USEIOSPACE 1549 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1550 aprint_error(": failed to enable I/O ports!\n"); 1551 return; 1552 } 1553 /* 1554 * Map control/status registers. 1555 */ 1556 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1557 &sc->sk_btag, &sc->sk_bhandle, 1558 &iobase, &iosize)) { 1559 aprint_error(": can't find i/o space\n"); 1560 return; 1561 } 1562 #else 1563 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1564 aprint_error(": failed to enable memory mapping!\n"); 1565 return; 1566 } 1567 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1568 switch (memtype) { 1569 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1570 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1571 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1572 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1573 &iobase, &iosize) == 0) 1574 break; 1575 default: 1576 aprint_error("%s: can't find mem space\n", 1577 sc->sk_dev.dv_xname); 1578 return; 1579 } 1580 1581 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1582 #endif 1583 sc->sc_dmatag = pa->pa_dmat; 1584 1585 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1586 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1587 1588 /* bail out here if chip is not recognized */ 1589 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1590 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1591 goto fail; 1592 } 1593 if (SK_IS_YUKON2(sc)) { 1594 aprint_error("%s: Does not support Yukon2--try msk(4).\n", 1595 sc->sk_dev.dv_xname); 1596 goto fail; 1597 } 1598 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1599 1600 /* Allocate interrupt */ 1601 if (pci_intr_map(pa, &ih)) { 1602 aprint_error(": couldn't map interrupt\n"); 1603 goto fail; 1604 } 1605 1606 intrstr = pci_intr_string(pc, ih); 1607 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1608 if (sc->sk_intrhand == NULL) { 1609 aprint_error(": couldn't establish interrupt"); 1610 if (intrstr != NULL) 1611 aprint_normal(" at %s", intrstr); 1612 goto fail; 1613 } 1614 aprint_normal(": %s\n", intrstr); 1615 1616 /* Reset the adapter. */ 1617 sk_reset(sc); 1618 1619 /* Read and save vital product data from EEPROM. */ 1620 sk_vpd_read(sc); 1621 1622 if (sc->sk_type == SK_GENESIS) { 1623 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1624 /* Read and save RAM size and RAMbuffer offset */ 1625 switch (val) { 1626 case SK_RAMSIZE_512K_64: 1627 sc->sk_ramsize = 0x80000; 1628 sc->sk_rboff = SK_RBOFF_0; 1629 break; 1630 case SK_RAMSIZE_1024K_64: 1631 sc->sk_ramsize = 0x100000; 1632 sc->sk_rboff = SK_RBOFF_80000; 1633 break; 1634 case SK_RAMSIZE_1024K_128: 1635 sc->sk_ramsize = 0x100000; 1636 sc->sk_rboff = SK_RBOFF_0; 1637 break; 1638 case SK_RAMSIZE_2048K_128: 1639 sc->sk_ramsize = 0x200000; 1640 sc->sk_rboff = SK_RBOFF_0; 1641 break; 1642 default: 1643 aprint_error("%s: unknown ram size: %d\n", 1644 sc->sk_dev.dv_xname, val); 1645 goto fail_1; 1646 break; 1647 } 1648 1649 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1650 sc->sk_ramsize, sc->sk_ramsize / 1024, 1651 sc->sk_rboff)); 1652 } else { 1653 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1654 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1655 sc->sk_rboff = SK_RBOFF_0; 1656 1657 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1658 sc->sk_ramsize / 1024, sc->sk_ramsize, 1659 sc->sk_rboff)); 1660 } 1661 1662 /* Read and save physical media type */ 1663 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1664 case SK_PMD_1000BASESX: 1665 sc->sk_pmd = IFM_1000_SX; 1666 break; 1667 case SK_PMD_1000BASELX: 1668 sc->sk_pmd = IFM_1000_LX; 1669 break; 1670 case SK_PMD_1000BASECX: 1671 sc->sk_pmd = IFM_1000_CX; 1672 break; 1673 case SK_PMD_1000BASETX: 1674 case SK_PMD_1000BASETX_ALT: 1675 sc->sk_pmd = IFM_1000_T; 1676 break; 1677 default: 1678 aprint_error("%s: unknown media type: 0x%x\n", 1679 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1680 goto fail_1; 1681 } 1682 1683 /* determine whether to name it with vpd or just make it up */ 1684 /* Marvell Yukon VPD's can freqently be bogus */ 1685 1686 switch (pa->pa_id) { 1687 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1688 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1689 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1690 case PCI_PRODUCT_3COM_3C940: 1691 case PCI_PRODUCT_DLINK_DGE530T: 1692 case PCI_PRODUCT_DLINK_DGE560T: 1693 case PCI_PRODUCT_DLINK_DGE560T_2: 1694 case PCI_PRODUCT_LINKSYS_EG1032: 1695 case PCI_PRODUCT_LINKSYS_EG1064: 1696 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1697 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1698 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1699 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1700 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1701 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1702 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1703 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1704 sc->sk_name = sc->sk_vpd_prodname; 1705 break; 1706 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1707 /* whoops yukon vpd prodname bears no resemblance to reality */ 1708 switch (sc->sk_type) { 1709 case SK_GENESIS: 1710 sc->sk_name = sc->sk_vpd_prodname; 1711 break; 1712 case SK_YUKON: 1713 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1714 break; 1715 case SK_YUKON_LITE: 1716 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1717 break; 1718 case SK_YUKON_LP: 1719 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1720 break; 1721 default: 1722 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1723 } 1724 1725 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1726 1727 if ( sc->sk_type == SK_YUKON ) { 1728 uint32_t flashaddr; 1729 uint8_t testbyte; 1730 1731 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1732 1733 /* test Flash-Address Register */ 1734 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1735 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1736 1737 if (testbyte != 0) { 1738 /* this is yukon lite Rev. A0 */ 1739 sc->sk_type = SK_YUKON_LITE; 1740 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1741 /* restore Flash-Address Register */ 1742 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1743 } 1744 } 1745 break; 1746 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1747 sc->sk_name = sc->sk_vpd_prodname; 1748 break; 1749 default: 1750 sc->sk_name = "Unknown Marvell"; 1751 } 1752 1753 1754 if ( sc->sk_type == SK_YUKON_LITE ) { 1755 switch (sc->sk_rev) { 1756 case SK_YUKON_LITE_REV_A0: 1757 revstr = "A0"; 1758 break; 1759 case SK_YUKON_LITE_REV_A1: 1760 revstr = "A1"; 1761 break; 1762 case SK_YUKON_LITE_REV_A3: 1763 revstr = "A3"; 1764 break; 1765 default: 1766 revstr = ""; 1767 } 1768 } else { 1769 revstr = ""; 1770 } 1771 1772 /* Announce the product name. */ 1773 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1774 sc->sk_name, revstr, sc->sk_rev); 1775 1776 skca.skc_port = SK_PORT_A; 1777 (void)config_found(&sc->sk_dev, &skca, skcprint); 1778 1779 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1780 skca.skc_port = SK_PORT_B; 1781 (void)config_found(&sc->sk_dev, &skca, skcprint); 1782 } 1783 1784 /* Turn on the 'driver is loaded' LED. */ 1785 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1786 1787 /* skc sysctl setup */ 1788 1789 sc->sk_int_mod = SK_IM_DEFAULT; 1790 sc->sk_int_mod_pending = 0; 1791 1792 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1793 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1794 SYSCTL_DESCR("skc per-controller controls"), 1795 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1796 CTL_EOL)) != 0) { 1797 aprint_normal("%s: couldn't create sysctl node\n", 1798 sc->sk_dev.dv_xname); 1799 goto fail_1; 1800 } 1801 1802 sk_nodenum = node->sysctl_num; 1803 1804 /* interrupt moderation time in usecs */ 1805 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1806 CTLFLAG_READWRITE, 1807 CTLTYPE_INT, "int_mod", 1808 SYSCTL_DESCR("sk interrupt moderation timer"), 1809 sk_sysctl_handler, 0, sc, 1810 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1811 CTL_EOL)) != 0) { 1812 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1813 sc->sk_dev.dv_xname); 1814 goto fail_1; 1815 } 1816 1817 return; 1818 1819 fail_1: 1820 pci_intr_disestablish(pc, sc->sk_intrhand); 1821 fail: 1822 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1823 } 1824 1825 int 1826 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1827 { 1828 struct sk_softc *sc = sc_if->sk_softc; 1829 struct sk_tx_desc *f = NULL; 1830 u_int32_t frag, cur, cnt = 0, sk_ctl; 1831 int i; 1832 struct sk_txmap_entry *entry; 1833 bus_dmamap_t txmap; 1834 1835 DPRINTFN(3, ("sk_encap\n")); 1836 1837 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1838 if (entry == NULL) { 1839 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1840 return ENOBUFS; 1841 } 1842 txmap = entry->dmamap; 1843 1844 cur = frag = *txidx; 1845 1846 #ifdef SK_DEBUG 1847 if (skdebug >= 3) 1848 sk_dump_mbuf(m_head); 1849 #endif 1850 1851 /* 1852 * Start packing the mbufs in this chain into 1853 * the fragment pointers. Stop when we run out 1854 * of fragments or hit the end of the mbuf chain. 1855 */ 1856 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1857 BUS_DMA_NOWAIT)) { 1858 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1859 return ENOBUFS; 1860 } 1861 1862 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1863 1864 /* Sync the DMA map. */ 1865 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1866 BUS_DMASYNC_PREWRITE); 1867 1868 for (i = 0; i < txmap->dm_nsegs; i++) { 1869 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1870 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1871 return ENOBUFS; 1872 } 1873 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1874 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1875 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1876 if (cnt == 0) 1877 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1878 else 1879 sk_ctl |= SK_TXCTL_OWN; 1880 f->sk_ctl = htole32(sk_ctl); 1881 cur = frag; 1882 SK_INC(frag, SK_TX_RING_CNT); 1883 cnt++; 1884 } 1885 1886 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1887 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1888 1889 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1890 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1891 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1892 1893 /* Sync descriptors before handing to chip */ 1894 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1895 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1896 1897 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1898 htole32(SK_TXCTL_OWN); 1899 1900 /* Sync first descriptor to hand it off */ 1901 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1902 1903 sc_if->sk_cdata.sk_tx_cnt += cnt; 1904 1905 #ifdef SK_DEBUG 1906 if (skdebug >= 3) { 1907 struct sk_tx_desc *desc; 1908 u_int32_t idx; 1909 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1910 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1911 sk_dump_txdesc(desc, idx); 1912 } 1913 } 1914 #endif 1915 1916 *txidx = frag; 1917 1918 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1919 1920 return 0; 1921 } 1922 1923 void 1924 sk_start(struct ifnet *ifp) 1925 { 1926 struct sk_if_softc *sc_if = ifp->if_softc; 1927 struct sk_softc *sc = sc_if->sk_softc; 1928 struct mbuf *m_head = NULL; 1929 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1930 int pkts = 0; 1931 1932 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1933 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1934 1935 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1936 IFQ_POLL(&ifp->if_snd, m_head); 1937 if (m_head == NULL) 1938 break; 1939 1940 /* 1941 * Pack the data into the transmit ring. If we 1942 * don't have room, set the OACTIVE flag and wait 1943 * for the NIC to drain the ring. 1944 */ 1945 if (sk_encap(sc_if, m_head, &idx)) { 1946 ifp->if_flags |= IFF_OACTIVE; 1947 break; 1948 } 1949 1950 /* now we are committed to transmit the packet */ 1951 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1952 pkts++; 1953 1954 /* 1955 * If there's a BPF listener, bounce a copy of this frame 1956 * to him. 1957 */ 1958 #if NBPFILTER > 0 1959 if (ifp->if_bpf) 1960 bpf_mtap(ifp->if_bpf, m_head); 1961 #endif 1962 } 1963 if (pkts == 0) 1964 return; 1965 1966 /* Transmit */ 1967 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1968 sc_if->sk_cdata.sk_tx_prod = idx; 1969 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1970 1971 /* Set a timeout in case the chip goes out to lunch. */ 1972 ifp->if_timer = 5; 1973 } 1974 } 1975 1976 1977 void 1978 sk_watchdog(struct ifnet *ifp) 1979 { 1980 struct sk_if_softc *sc_if = ifp->if_softc; 1981 1982 /* 1983 * Reclaim first as there is a possibility of losing Tx completion 1984 * interrupts. 1985 */ 1986 sk_txeof(sc_if); 1987 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1988 aprint_error("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1989 1990 ifp->if_oerrors++; 1991 1992 sk_init(ifp); 1993 } 1994 } 1995 1996 void 1997 sk_shutdown(void *v) 1998 { 1999 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2000 struct sk_softc *sc = sc_if->sk_softc; 2001 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2002 2003 DPRINTFN(2, ("sk_shutdown\n")); 2004 sk_stop(ifp,1); 2005 2006 /* Turn off the 'driver is loaded' LED. */ 2007 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2008 2009 /* 2010 * Reset the GEnesis controller. Doing this should also 2011 * assert the resets on the attached XMAC(s). 2012 */ 2013 sk_reset(sc); 2014 } 2015 2016 void 2017 sk_rxeof(struct sk_if_softc *sc_if) 2018 { 2019 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2020 struct mbuf *m; 2021 struct sk_chain *cur_rx; 2022 struct sk_rx_desc *cur_desc; 2023 int i, cur, total_len = 0; 2024 u_int32_t rxstat, sk_ctl; 2025 bus_dmamap_t dmamap; 2026 2027 i = sc_if->sk_cdata.sk_rx_prod; 2028 2029 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2030 2031 for (;;) { 2032 cur = i; 2033 2034 /* Sync the descriptor */ 2035 SK_CDRXSYNC(sc_if, cur, 2036 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2037 2038 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2039 if (sk_ctl & SK_RXCTL_OWN) { 2040 /* Invalidate the descriptor -- it's not ready yet */ 2041 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2042 sc_if->sk_cdata.sk_rx_prod = i; 2043 break; 2044 } 2045 2046 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2047 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2048 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2049 2050 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2051 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2052 2053 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2054 m = cur_rx->sk_mbuf; 2055 cur_rx->sk_mbuf = NULL; 2056 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2057 2058 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2059 2060 SK_INC(i, SK_RX_RING_CNT); 2061 2062 if (rxstat & XM_RXSTAT_ERRFRAME) { 2063 ifp->if_ierrors++; 2064 sk_newbuf(sc_if, cur, m, dmamap); 2065 continue; 2066 } 2067 2068 /* 2069 * Try to allocate a new jumbo buffer. If that 2070 * fails, copy the packet to mbufs and put the 2071 * jumbo buffer back in the ring so it can be 2072 * re-used. If allocating mbufs fails, then we 2073 * have to drop the packet. 2074 */ 2075 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2076 struct mbuf *m0; 2077 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2078 total_len + ETHER_ALIGN, 0, ifp, NULL); 2079 sk_newbuf(sc_if, cur, m, dmamap); 2080 if (m0 == NULL) { 2081 aprint_error("%s: no receive buffers " 2082 "available -- packet dropped!\n", 2083 sc_if->sk_dev.dv_xname); 2084 ifp->if_ierrors++; 2085 continue; 2086 } 2087 m_adj(m0, ETHER_ALIGN); 2088 m = m0; 2089 } else { 2090 m->m_pkthdr.rcvif = ifp; 2091 m->m_pkthdr.len = m->m_len = total_len; 2092 } 2093 2094 ifp->if_ipackets++; 2095 2096 #if NBPFILTER > 0 2097 if (ifp->if_bpf) 2098 bpf_mtap(ifp->if_bpf, m); 2099 #endif 2100 /* pass it on. */ 2101 (*ifp->if_input)(ifp, m); 2102 } 2103 } 2104 2105 void 2106 sk_txeof(struct sk_if_softc *sc_if) 2107 { 2108 struct sk_softc *sc = sc_if->sk_softc; 2109 struct sk_tx_desc *cur_tx; 2110 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2111 u_int32_t idx, sk_ctl; 2112 struct sk_txmap_entry *entry; 2113 2114 DPRINTFN(3, ("sk_txeof\n")); 2115 2116 /* 2117 * Go through our tx ring and free mbufs for those 2118 * frames that have been sent. 2119 */ 2120 idx = sc_if->sk_cdata.sk_tx_cons; 2121 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2122 SK_CDTXSYNC(sc_if, idx, 1, 2123 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2124 2125 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2126 sk_ctl = le32toh(cur_tx->sk_ctl); 2127 #ifdef SK_DEBUG 2128 if (skdebug >= 3) 2129 sk_dump_txdesc(cur_tx, idx); 2130 #endif 2131 if (sk_ctl & SK_TXCTL_OWN) { 2132 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2133 break; 2134 } 2135 if (sk_ctl & SK_TXCTL_LASTFRAG) 2136 ifp->if_opackets++; 2137 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2138 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2139 2140 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2141 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2142 2143 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2144 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2145 2146 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2147 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2148 link); 2149 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2150 } 2151 sc_if->sk_cdata.sk_tx_cnt--; 2152 SK_INC(idx, SK_TX_RING_CNT); 2153 } 2154 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2155 ifp->if_timer = 0; 2156 else /* nudge chip to keep tx ring moving */ 2157 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2158 2159 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2160 ifp->if_flags &= ~IFF_OACTIVE; 2161 2162 sc_if->sk_cdata.sk_tx_cons = idx; 2163 } 2164 2165 void 2166 sk_tick(void *xsc_if) 2167 { 2168 struct sk_if_softc *sc_if = xsc_if; 2169 struct mii_data *mii = &sc_if->sk_mii; 2170 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2171 int i; 2172 2173 DPRINTFN(3, ("sk_tick\n")); 2174 2175 if (!(ifp->if_flags & IFF_UP)) 2176 return; 2177 2178 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2179 sk_intr_bcom(sc_if); 2180 return; 2181 } 2182 2183 /* 2184 * According to SysKonnect, the correct way to verify that 2185 * the link has come back up is to poll bit 0 of the GPIO 2186 * register three times. This pin has the signal from the 2187 * link sync pin connected to it; if we read the same link 2188 * state 3 times in a row, we know the link is up. 2189 */ 2190 for (i = 0; i < 3; i++) { 2191 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2192 break; 2193 } 2194 2195 if (i != 3) { 2196 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2197 return; 2198 } 2199 2200 /* Turn the GP0 interrupt back on. */ 2201 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2202 SK_XM_READ_2(sc_if, XM_ISR); 2203 mii_tick(mii); 2204 mii_pollstat(mii); 2205 callout_stop(&sc_if->sk_tick_ch); 2206 } 2207 2208 void 2209 sk_intr_bcom(struct sk_if_softc *sc_if) 2210 { 2211 struct mii_data *mii = &sc_if->sk_mii; 2212 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2213 int status; 2214 2215 2216 DPRINTFN(3, ("sk_intr_bcom\n")); 2217 2218 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2219 2220 /* 2221 * Read the PHY interrupt register to make sure 2222 * we clear any pending interrupts. 2223 */ 2224 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2225 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2226 2227 if (!(ifp->if_flags & IFF_RUNNING)) { 2228 sk_init_xmac(sc_if); 2229 return; 2230 } 2231 2232 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2233 int lstat; 2234 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2235 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2236 2237 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2238 (void)mii_mediachg(mii); 2239 /* Turn off the link LED. */ 2240 SK_IF_WRITE_1(sc_if, 0, 2241 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2242 sc_if->sk_link = 0; 2243 } else if (status & BRGPHY_ISR_LNK_CHG) { 2244 sk_xmac_miibus_writereg((struct device *)sc_if, 2245 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2246 mii_tick(mii); 2247 sc_if->sk_link = 1; 2248 /* Turn on the link LED. */ 2249 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2250 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2251 SK_LINKLED_BLINK_OFF); 2252 mii_pollstat(mii); 2253 } else { 2254 mii_tick(mii); 2255 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2256 } 2257 } 2258 2259 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2260 } 2261 2262 void 2263 sk_intr_xmac(struct sk_if_softc *sc_if) 2264 { 2265 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2266 2267 DPRINTFN(3, ("sk_intr_xmac\n")); 2268 2269 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2270 if (status & XM_ISR_GP0_SET) { 2271 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2272 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2273 } 2274 2275 if (status & XM_ISR_AUTONEG_DONE) { 2276 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2277 } 2278 } 2279 2280 if (status & XM_IMR_TX_UNDERRUN) 2281 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2282 2283 if (status & XM_IMR_RX_OVERRUN) 2284 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2285 } 2286 2287 void 2288 sk_intr_yukon(struct sk_if_softc *sc_if) 2289 { 2290 int status; 2291 2292 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2293 2294 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2295 } 2296 2297 int 2298 sk_intr(void *xsc) 2299 { 2300 struct sk_softc *sc = xsc; 2301 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2302 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2303 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2304 u_int32_t status; 2305 int claimed = 0; 2306 2307 if (sc_if0 != NULL) 2308 ifp0 = &sc_if0->sk_ethercom.ec_if; 2309 if (sc_if1 != NULL) 2310 ifp1 = &sc_if1->sk_ethercom.ec_if; 2311 2312 for (;;) { 2313 status = CSR_READ_4(sc, SK_ISSR); 2314 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2315 2316 if (!(status & sc->sk_intrmask)) 2317 break; 2318 2319 claimed = 1; 2320 2321 /* Handle receive interrupts first. */ 2322 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2323 sk_rxeof(sc_if0); 2324 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2325 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2326 } 2327 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2328 sk_rxeof(sc_if1); 2329 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2330 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2331 } 2332 2333 /* Then transmit interrupts. */ 2334 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2335 sk_txeof(sc_if0); 2336 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2337 SK_TXBMU_CLR_IRQ_EOF); 2338 } 2339 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2340 sk_txeof(sc_if1); 2341 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2342 SK_TXBMU_CLR_IRQ_EOF); 2343 } 2344 2345 /* Then MAC interrupts. */ 2346 if (sc_if0 && (status & SK_ISR_MAC1) && 2347 (ifp0->if_flags & IFF_RUNNING)) { 2348 if (sc->sk_type == SK_GENESIS) 2349 sk_intr_xmac(sc_if0); 2350 else 2351 sk_intr_yukon(sc_if0); 2352 } 2353 2354 if (sc_if1 && (status & SK_ISR_MAC2) && 2355 (ifp1->if_flags & IFF_RUNNING)) { 2356 if (sc->sk_type == SK_GENESIS) 2357 sk_intr_xmac(sc_if1); 2358 else 2359 sk_intr_yukon(sc_if1); 2360 2361 } 2362 2363 if (status & SK_ISR_EXTERNAL_REG) { 2364 if (sc_if0 != NULL && 2365 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2366 sk_intr_bcom(sc_if0); 2367 2368 if (sc_if1 != NULL && 2369 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2370 sk_intr_bcom(sc_if1); 2371 } 2372 } 2373 2374 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2375 2376 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2377 sk_start(ifp0); 2378 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2379 sk_start(ifp1); 2380 2381 #if NRND > 0 2382 if (RND_ENABLED(&sc->rnd_source)) 2383 rnd_add_uint32(&sc->rnd_source, status); 2384 #endif 2385 2386 if (sc->sk_int_mod_pending) 2387 sk_update_int_mod(sc); 2388 2389 return claimed; 2390 } 2391 2392 void 2393 sk_init_xmac(struct sk_if_softc *sc_if) 2394 { 2395 struct sk_softc *sc = sc_if->sk_softc; 2396 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2397 static const struct sk_bcom_hack bhack[] = { 2398 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2399 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2400 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2401 { 0, 0 } }; 2402 2403 DPRINTFN(1, ("sk_init_xmac\n")); 2404 2405 /* Unreset the XMAC. */ 2406 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2407 DELAY(1000); 2408 2409 /* Reset the XMAC's internal state. */ 2410 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2411 2412 /* Save the XMAC II revision */ 2413 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2414 2415 /* 2416 * Perform additional initialization for external PHYs, 2417 * namely for the 1000baseTX cards that use the XMAC's 2418 * GMII mode. 2419 */ 2420 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2421 int i = 0; 2422 u_int32_t val; 2423 2424 /* Take PHY out of reset. */ 2425 val = sk_win_read_4(sc, SK_GPIO); 2426 if (sc_if->sk_port == SK_PORT_A) 2427 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2428 else 2429 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2430 sk_win_write_4(sc, SK_GPIO, val); 2431 2432 /* Enable GMII mode on the XMAC. */ 2433 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2434 2435 sk_xmac_miibus_writereg((struct device *)sc_if, 2436 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2437 DELAY(10000); 2438 sk_xmac_miibus_writereg((struct device *)sc_if, 2439 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2440 2441 /* 2442 * Early versions of the BCM5400 apparently have 2443 * a bug that requires them to have their reserved 2444 * registers initialized to some magic values. I don't 2445 * know what the numbers do, I'm just the messenger. 2446 */ 2447 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2448 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2449 while (bhack[i].reg) { 2450 sk_xmac_miibus_writereg((struct device *)sc_if, 2451 SK_PHYADDR_BCOM, bhack[i].reg, 2452 bhack[i].val); 2453 i++; 2454 } 2455 } 2456 } 2457 2458 /* Set station address */ 2459 SK_XM_WRITE_2(sc_if, XM_PAR0, 2460 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2461 SK_XM_WRITE_2(sc_if, XM_PAR1, 2462 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2463 SK_XM_WRITE_2(sc_if, XM_PAR2, 2464 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2465 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2466 2467 if (ifp->if_flags & IFF_PROMISC) 2468 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2469 else 2470 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2471 2472 if (ifp->if_flags & IFF_BROADCAST) 2473 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2474 else 2475 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2476 2477 /* We don't need the FCS appended to the packet. */ 2478 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2479 2480 /* We want short frames padded to 60 bytes. */ 2481 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2482 2483 /* 2484 * Enable the reception of all error frames. This is is 2485 * a necessary evil due to the design of the XMAC. The 2486 * XMAC's receive FIFO is only 8K in size, however jumbo 2487 * frames can be up to 9000 bytes in length. When bad 2488 * frame filtering is enabled, the XMAC's RX FIFO operates 2489 * in 'store and forward' mode. For this to work, the 2490 * entire frame has to fit into the FIFO, but that means 2491 * that jumbo frames larger than 8192 bytes will be 2492 * truncated. Disabling all bad frame filtering causes 2493 * the RX FIFO to operate in streaming mode, in which 2494 * case the XMAC will start transfering frames out of the 2495 * RX FIFO as soon as the FIFO threshold is reached. 2496 */ 2497 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2498 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2499 XM_MODE_RX_INRANGELEN); 2500 2501 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2502 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2503 else 2504 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2505 2506 /* 2507 * Bump up the transmit threshold. This helps hold off transmit 2508 * underruns when we're blasting traffic from both ports at once. 2509 */ 2510 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2511 2512 /* Set multicast filter */ 2513 sk_setmulti(sc_if); 2514 2515 /* Clear and enable interrupts */ 2516 SK_XM_READ_2(sc_if, XM_ISR); 2517 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2518 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2519 else 2520 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2521 2522 /* Configure MAC arbiter */ 2523 switch (sc_if->sk_xmac_rev) { 2524 case XM_XMAC_REV_B2: 2525 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2526 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2527 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2528 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2529 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2530 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2531 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2532 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2533 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2534 break; 2535 case XM_XMAC_REV_C1: 2536 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2537 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2538 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2539 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2540 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2541 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2542 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2543 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2544 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2545 break; 2546 default: 2547 break; 2548 } 2549 sk_win_write_2(sc, SK_MACARB_CTL, 2550 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2551 2552 sc_if->sk_link = 1; 2553 } 2554 2555 void sk_init_yukon(struct sk_if_softc *sc_if) 2556 { 2557 u_int32_t /*mac, */phy; 2558 u_int16_t reg; 2559 struct sk_softc *sc; 2560 int i; 2561 2562 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2563 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2564 2565 sc = sc_if->sk_softc; 2566 if (sc->sk_type == SK_YUKON_LITE && 2567 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2568 /* Take PHY out of reset. */ 2569 sk_win_write_4(sc, SK_GPIO, 2570 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2571 } 2572 2573 2574 /* GMAC and GPHY Reset */ 2575 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2576 2577 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2578 2579 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2580 DELAY(1000); 2581 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2582 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2583 DELAY(1000); 2584 2585 2586 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2587 2588 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2589 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2590 2591 switch (sc_if->sk_softc->sk_pmd) { 2592 case IFM_1000_SX: 2593 case IFM_1000_LX: 2594 phy |= SK_GPHY_FIBER; 2595 break; 2596 2597 case IFM_1000_CX: 2598 case IFM_1000_T: 2599 phy |= SK_GPHY_COPPER; 2600 break; 2601 } 2602 2603 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2604 2605 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2606 DELAY(1000); 2607 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2608 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2609 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2610 2611 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2612 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2613 2614 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2615 2616 /* unused read of the interrupt source register */ 2617 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2618 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2619 2620 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2621 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2622 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2623 2624 /* MIB Counter Clear Mode set */ 2625 reg |= YU_PAR_MIB_CLR; 2626 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2627 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2628 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2629 2630 /* MIB Counter Clear Mode clear */ 2631 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2632 reg &= ~YU_PAR_MIB_CLR; 2633 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2634 2635 /* receive control reg */ 2636 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2637 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2638 YU_RCR_CRCR); 2639 2640 /* transmit parameter register */ 2641 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2642 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2643 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2644 2645 /* serial mode register */ 2646 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2647 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2648 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2649 YU_SMR_IPG_DATA(0x1e)); 2650 2651 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2652 /* Setup Yukon's address */ 2653 for (i = 0; i < 3; i++) { 2654 /* Write Source Address 1 (unicast filter) */ 2655 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2656 sc_if->sk_enaddr[i * 2] | 2657 sc_if->sk_enaddr[i * 2 + 1] << 8); 2658 } 2659 2660 for (i = 0; i < 3; i++) { 2661 reg = sk_win_read_2(sc_if->sk_softc, 2662 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2663 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2664 } 2665 2666 /* Set multicast filter */ 2667 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2668 sk_setmulti(sc_if); 2669 2670 /* enable interrupt mask for counter overflows */ 2671 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2672 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2673 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2674 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2675 2676 /* Configure RX MAC FIFO */ 2677 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2678 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2679 2680 /* Configure TX MAC FIFO */ 2681 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2682 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2683 2684 DPRINTFN(6, ("sk_init_yukon: end\n")); 2685 } 2686 2687 /* 2688 * Note that to properly initialize any part of the GEnesis chip, 2689 * you first have to take it out of reset mode. 2690 */ 2691 int 2692 sk_init(struct ifnet *ifp) 2693 { 2694 struct sk_if_softc *sc_if = ifp->if_softc; 2695 struct sk_softc *sc = sc_if->sk_softc; 2696 struct mii_data *mii = &sc_if->sk_mii; 2697 int rc = 0, s; 2698 u_int32_t imr, imtimer_ticks; 2699 2700 DPRINTFN(1, ("sk_init\n")); 2701 2702 s = splnet(); 2703 2704 if (ifp->if_flags & IFF_RUNNING) { 2705 splx(s); 2706 return 0; 2707 } 2708 2709 /* Cancel pending I/O and free all RX/TX buffers. */ 2710 sk_stop(ifp,0); 2711 2712 if (sc->sk_type == SK_GENESIS) { 2713 /* Configure LINK_SYNC LED */ 2714 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2715 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2716 SK_LINKLED_LINKSYNC_ON); 2717 2718 /* Configure RX LED */ 2719 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2720 SK_RXLEDCTL_COUNTER_START); 2721 2722 /* Configure TX LED */ 2723 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2724 SK_TXLEDCTL_COUNTER_START); 2725 } 2726 2727 /* Configure I2C registers */ 2728 2729 /* Configure XMAC(s) */ 2730 switch (sc->sk_type) { 2731 case SK_GENESIS: 2732 sk_init_xmac(sc_if); 2733 break; 2734 case SK_YUKON: 2735 case SK_YUKON_LITE: 2736 case SK_YUKON_LP: 2737 sk_init_yukon(sc_if); 2738 break; 2739 } 2740 if ((rc = mii_mediachg(mii)) == ENXIO) 2741 rc = 0; 2742 else if (rc != 0) 2743 goto out; 2744 2745 if (sc->sk_type == SK_GENESIS) { 2746 /* Configure MAC FIFOs */ 2747 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2748 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2749 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2750 2751 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2752 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2753 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2754 } 2755 2756 /* Configure transmit arbiter(s) */ 2757 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2758 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2759 2760 /* Configure RAMbuffers */ 2761 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2762 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2763 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2764 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2765 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2766 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2767 2768 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2769 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2770 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2771 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2772 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2773 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2774 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2775 2776 /* Configure BMUs */ 2777 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2778 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2779 SK_RX_RING_ADDR(sc_if, 0)); 2780 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2781 2782 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2783 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2784 SK_TX_RING_ADDR(sc_if, 0)); 2785 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2786 2787 /* Init descriptors */ 2788 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2789 aprint_error("%s: initialization failed: no " 2790 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2791 sk_stop(ifp,0); 2792 splx(s); 2793 return ENOBUFS; 2794 } 2795 2796 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2797 aprint_error("%s: initialization failed: no " 2798 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2799 sk_stop(ifp,0); 2800 splx(s); 2801 return ENOBUFS; 2802 } 2803 2804 /* Set interrupt moderation if changed via sysctl. */ 2805 switch (sc->sk_type) { 2806 case SK_GENESIS: 2807 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2808 break; 2809 case SK_YUKON_EC: 2810 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2811 break; 2812 default: 2813 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2814 } 2815 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2816 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2817 sk_win_write_4(sc, SK_IMTIMERINIT, 2818 SK_IM_USECS(sc->sk_int_mod)); 2819 aprint_verbose("%s: interrupt moderation is %d us\n", 2820 sc->sk_dev.dv_xname, sc->sk_int_mod); 2821 } 2822 2823 /* Configure interrupt handling */ 2824 CSR_READ_4(sc, SK_ISSR); 2825 if (sc_if->sk_port == SK_PORT_A) 2826 sc->sk_intrmask |= SK_INTRS1; 2827 else 2828 sc->sk_intrmask |= SK_INTRS2; 2829 2830 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2831 2832 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2833 2834 /* Start BMUs. */ 2835 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2836 2837 if (sc->sk_type == SK_GENESIS) { 2838 /* Enable XMACs TX and RX state machines */ 2839 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2840 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2841 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2842 } 2843 2844 if (SK_YUKON_FAMILY(sc->sk_type)) { 2845 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2846 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2847 #if 0 2848 /* XXX disable 100Mbps and full duplex mode? */ 2849 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2850 #endif 2851 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2852 } 2853 2854 2855 ifp->if_flags |= IFF_RUNNING; 2856 ifp->if_flags &= ~IFF_OACTIVE; 2857 2858 out: 2859 splx(s); 2860 return rc; 2861 } 2862 2863 void 2864 sk_stop(struct ifnet *ifp, int disable) 2865 { 2866 struct sk_if_softc *sc_if = ifp->if_softc; 2867 struct sk_softc *sc = sc_if->sk_softc; 2868 int i; 2869 2870 DPRINTFN(1, ("sk_stop\n")); 2871 2872 callout_stop(&sc_if->sk_tick_ch); 2873 2874 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2875 u_int32_t val; 2876 2877 /* Put PHY back into reset. */ 2878 val = sk_win_read_4(sc, SK_GPIO); 2879 if (sc_if->sk_port == SK_PORT_A) { 2880 val |= SK_GPIO_DIR0; 2881 val &= ~SK_GPIO_DAT0; 2882 } else { 2883 val |= SK_GPIO_DIR2; 2884 val &= ~SK_GPIO_DAT2; 2885 } 2886 sk_win_write_4(sc, SK_GPIO, val); 2887 } 2888 2889 /* Turn off various components of this interface. */ 2890 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2891 switch (sc->sk_type) { 2892 case SK_GENESIS: 2893 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2894 SK_TXMACCTL_XMAC_RESET); 2895 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2896 break; 2897 case SK_YUKON: 2898 case SK_YUKON_LITE: 2899 case SK_YUKON_LP: 2900 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2901 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2902 break; 2903 } 2904 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2905 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2906 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2907 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2908 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2909 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2910 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2911 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2912 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2913 2914 /* Disable interrupts */ 2915 if (sc_if->sk_port == SK_PORT_A) 2916 sc->sk_intrmask &= ~SK_INTRS1; 2917 else 2918 sc->sk_intrmask &= ~SK_INTRS2; 2919 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2920 2921 SK_XM_READ_2(sc_if, XM_ISR); 2922 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2923 2924 /* Free RX and TX mbufs still in the queues. */ 2925 for (i = 0; i < SK_RX_RING_CNT; i++) { 2926 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2927 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2928 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2929 } 2930 } 2931 2932 for (i = 0; i < SK_TX_RING_CNT; i++) { 2933 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2934 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2935 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2936 } 2937 } 2938 2939 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2940 } 2941 2942 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2943 2944 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2945 2946 #ifdef SK_DEBUG 2947 void 2948 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2949 { 2950 #define DESC_PRINT(X) \ 2951 if (X) \ 2952 printf("txdesc[%d]." #X "=%#x\n", \ 2953 idx, X); 2954 2955 DESC_PRINT(le32toh(desc->sk_ctl)); 2956 DESC_PRINT(le32toh(desc->sk_next)); 2957 DESC_PRINT(le32toh(desc->sk_data_lo)); 2958 DESC_PRINT(le32toh(desc->sk_data_hi)); 2959 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2960 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2961 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2962 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2963 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2964 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2965 #undef PRINT 2966 } 2967 2968 void 2969 sk_dump_bytes(const char *data, int len) 2970 { 2971 int c, i, j; 2972 2973 for (i = 0; i < len; i += 16) { 2974 printf("%08x ", i); 2975 c = len - i; 2976 if (c > 16) c = 16; 2977 2978 for (j = 0; j < c; j++) { 2979 printf("%02x ", data[i + j] & 0xff); 2980 if ((j & 0xf) == 7 && j > 0) 2981 printf(" "); 2982 } 2983 2984 for (; j < 16; j++) 2985 printf(" "); 2986 printf(" "); 2987 2988 for (j = 0; j < c; j++) { 2989 int ch = data[i + j] & 0xff; 2990 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2991 } 2992 2993 printf("\n"); 2994 2995 if (c < 16) 2996 break; 2997 } 2998 } 2999 3000 void 3001 sk_dump_mbuf(struct mbuf *m) 3002 { 3003 int count = m->m_pkthdr.len; 3004 3005 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3006 3007 while (count > 0 && m) { 3008 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3009 m, m->m_data, m->m_len); 3010 sk_dump_bytes(mtod(m, char *), m->m_len); 3011 3012 count -= m->m_len; 3013 m = m->m_next; 3014 } 3015 } 3016 #endif 3017 3018 static int 3019 sk_sysctl_handler(SYSCTLFN_ARGS) 3020 { 3021 int error, t; 3022 struct sysctlnode node; 3023 struct sk_softc *sc; 3024 3025 node = *rnode; 3026 sc = node.sysctl_data; 3027 t = sc->sk_int_mod; 3028 node.sysctl_data = &t; 3029 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3030 if (error || newp == NULL) 3031 return error; 3032 3033 if (t < SK_IM_MIN || t > SK_IM_MAX) 3034 return EINVAL; 3035 3036 /* update the softc with sysctl-changed value, and mark 3037 for hardware update */ 3038 sc->sk_int_mod = t; 3039 sc->sk_int_mod_pending = 1; 3040 return 0; 3041 } 3042 3043 /* 3044 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3045 * set up in skc_attach() 3046 */ 3047 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3048 { 3049 int rc; 3050 const struct sysctlnode *node; 3051 3052 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3053 0, CTLTYPE_NODE, "hw", NULL, 3054 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3055 goto err; 3056 } 3057 3058 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3059 0, CTLTYPE_NODE, "sk", 3060 SYSCTL_DESCR("sk interface controls"), 3061 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3062 goto err; 3063 } 3064 3065 sk_root_num = node->sysctl_num; 3066 return; 3067 3068 err: 3069 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3070 } 3071
Indexes created Thu Sep 25 02:09:54 GMT 2025