if_sk.c revision 1.48
1 /* $NetBSD: if_sk.c,v 1.48 2008/04/10 19:13:37 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include <sys/cdefs.h> 125 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.48 2008/04/10 19:13:37 cegger Exp $"); 126 127 #include "bpfilter.h" 128 #include "rnd.h" 129 130 #include <sys/param.h> 131 #include <sys/systm.h> 132 #include <sys/sockio.h> 133 #include <sys/mbuf.h> 134 #include <sys/malloc.h> 135 #include <sys/kernel.h> 136 #include <sys/socket.h> 137 #include <sys/device.h> 138 #include <sys/queue.h> 139 #include <sys/callout.h> 140 #include <sys/sysctl.h> 141 #include <sys/endian.h> 142 143 #include <net/if.h> 144 #include <net/if_dl.h> 145 #include <net/if_types.h> 146 147 #include <net/if_media.h> 148 149 #if NBPFILTER > 0 150 #include <net/bpf.h> 151 #endif 152 #if NRND > 0 153 #include <sys/rnd.h> 154 #endif 155 156 #include <dev/mii/mii.h> 157 #include <dev/mii/miivar.h> 158 #include <dev/mii/brgphyreg.h> 159 160 #include <dev/pci/pcireg.h> 161 #include <dev/pci/pcivar.h> 162 #include <dev/pci/pcidevs.h> 163 164 /* #define SK_USEIOSPACE */ 165 166 #include <dev/pci/if_skreg.h> 167 #include <dev/pci/if_skvar.h> 168 169 int skc_probe(struct device *, struct cfdata *, void *); 170 void skc_attach(struct device *, struct device *self, void *aux); 171 int sk_probe(struct device *, struct cfdata *, void *); 172 void sk_attach(struct device *, struct device *self, void *aux); 173 int skcprint(void *, const char *); 174 int sk_intr(void *); 175 void sk_intr_bcom(struct sk_if_softc *); 176 void sk_intr_xmac(struct sk_if_softc *); 177 void sk_intr_yukon(struct sk_if_softc *); 178 void sk_rxeof(struct sk_if_softc *); 179 void sk_txeof(struct sk_if_softc *); 180 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 181 void sk_start(struct ifnet *); 182 int sk_ioctl(struct ifnet *, u_long, void *); 183 int sk_init(struct ifnet *); 184 void sk_init_xmac(struct sk_if_softc *); 185 void sk_init_yukon(struct sk_if_softc *); 186 void sk_stop(struct ifnet *, int); 187 void sk_watchdog(struct ifnet *); 188 void sk_shutdown(void *); 189 int sk_ifmedia_upd(struct ifnet *); 190 void sk_reset(struct sk_softc *); 191 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 192 int sk_alloc_jumbo_mem(struct sk_if_softc *); 193 void sk_free_jumbo_mem(struct sk_if_softc *); 194 void *sk_jalloc(struct sk_if_softc *); 195 void sk_jfree(struct mbuf *, void *, size_t, void *); 196 int sk_init_rx_ring(struct sk_if_softc *); 197 int sk_init_tx_ring(struct sk_if_softc *); 198 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 199 void sk_vpd_read_res(struct sk_softc *, 200 struct vpd_res *, int); 201 void sk_vpd_read(struct sk_softc *); 202 203 void sk_update_int_mod(struct sk_softc *); 204 205 int sk_xmac_miibus_readreg(struct device *, int, int); 206 void sk_xmac_miibus_writereg(struct device *, int, int, int); 207 void sk_xmac_miibus_statchg(struct device *); 208 209 int sk_marv_miibus_readreg(struct device *, int, int); 210 void sk_marv_miibus_writereg(struct device *, int, int, int); 211 void sk_marv_miibus_statchg(struct device *); 212 213 u_int32_t sk_xmac_hash(void *); 214 u_int32_t sk_yukon_hash(void *); 215 void sk_setfilt(struct sk_if_softc *, void *, int); 216 void sk_setmulti(struct sk_if_softc *); 217 void sk_tick(void *); 218 219 /* #define SK_DEBUG 2 */ 220 #ifdef SK_DEBUG 221 #define DPRINTF(x) if (skdebug) printf x 222 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 223 int skdebug = SK_DEBUG; 224 225 void sk_dump_txdesc(struct sk_tx_desc *, int); 226 void sk_dump_mbuf(struct mbuf *); 227 void sk_dump_bytes(const char *, int); 228 #else 229 #define DPRINTF(x) 230 #define DPRINTFN(n,x) 231 #endif 232 233 static int sk_sysctl_handler(SYSCTLFN_PROTO); 234 static int sk_root_num; 235 236 /* supported device vendors */ 237 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 238 static const struct sk_product { 239 pci_vendor_id_t sk_vendor; 240 pci_product_id_t sk_product; 241 } sk_products[] = { 242 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 243 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 244 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 245 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 246 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 247 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 248 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 249 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 250 { 0, 0, } 251 }; 252 253 #define SK_LINKSYS_EG1032_SUBID 0x00151737 254 255 static inline u_int32_t 256 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 257 { 258 #ifdef SK_USEIOSPACE 259 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 260 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 261 #else 262 return CSR_READ_4(sc, reg); 263 #endif 264 } 265 266 static inline u_int16_t 267 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 268 { 269 #ifdef SK_USEIOSPACE 270 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 271 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 272 #else 273 return CSR_READ_2(sc, reg); 274 #endif 275 } 276 277 static inline u_int8_t 278 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 279 { 280 #ifdef SK_USEIOSPACE 281 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 282 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 283 #else 284 return CSR_READ_1(sc, reg); 285 #endif 286 } 287 288 static inline void 289 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 290 { 291 #ifdef SK_USEIOSPACE 292 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 293 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 294 #else 295 CSR_WRITE_4(sc, reg, x); 296 #endif 297 } 298 299 static inline void 300 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 301 { 302 #ifdef SK_USEIOSPACE 303 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 304 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 305 #else 306 CSR_WRITE_2(sc, reg, x); 307 #endif 308 } 309 310 static inline void 311 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 312 { 313 #ifdef SK_USEIOSPACE 314 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 315 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 316 #else 317 CSR_WRITE_1(sc, reg, x); 318 #endif 319 } 320 321 /* 322 * The VPD EEPROM contains Vital Product Data, as suggested in 323 * the PCI 2.1 specification. The VPD data is separared into areas 324 * denoted by resource IDs. The SysKonnect VPD contains an ID string 325 * resource (the name of the adapter), a read-only area resource 326 * containing various key/data fields and a read/write area which 327 * can be used to store asset management information or log messages. 328 * We read the ID string and read-only into buffers attached to 329 * the controller softc structure for later use. At the moment, 330 * we only use the ID string during sk_attach(). 331 */ 332 u_int8_t 333 sk_vpd_readbyte(struct sk_softc *sc, int addr) 334 { 335 int i; 336 337 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 338 for (i = 0; i < SK_TIMEOUT; i++) { 339 DELAY(1); 340 if (sk_win_read_2(sc, 341 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 342 break; 343 } 344 345 if (i == SK_TIMEOUT) 346 return 0; 347 348 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 349 } 350 351 void 352 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 353 { 354 int i; 355 u_int8_t *ptr; 356 357 ptr = (u_int8_t *)res; 358 for (i = 0; i < sizeof(struct vpd_res); i++) 359 ptr[i] = sk_vpd_readbyte(sc, i + addr); 360 } 361 362 void 363 sk_vpd_read(struct sk_softc *sc) 364 { 365 int pos = 0, i; 366 struct vpd_res res; 367 368 if (sc->sk_vpd_prodname != NULL) 369 free(sc->sk_vpd_prodname, M_DEVBUF); 370 if (sc->sk_vpd_readonly != NULL) 371 free(sc->sk_vpd_readonly, M_DEVBUF); 372 sc->sk_vpd_prodname = NULL; 373 sc->sk_vpd_readonly = NULL; 374 375 sk_vpd_read_res(sc, &res, pos); 376 377 if (res.vr_id != VPD_RES_ID) { 378 aprint_error_dev(&sc->sk_dev, "bad VPD resource id: expected %x got %x\n", 379 VPD_RES_ID, res.vr_id); 380 return; 381 } 382 383 pos += sizeof(res); 384 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 385 if (sc->sk_vpd_prodname == NULL) 386 panic("sk_vpd_read"); 387 for (i = 0; i < res.vr_len; i++) 388 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 389 sc->sk_vpd_prodname[i] = '\0'; 390 pos += i; 391 392 sk_vpd_read_res(sc, &res, pos); 393 394 if (res.vr_id != VPD_RES_READ) { 395 aprint_error_dev(&sc->sk_dev, "bad VPD resource id: expected %x got %x\n", 396 VPD_RES_READ, res.vr_id); 397 return; 398 } 399 400 pos += sizeof(res); 401 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 402 if (sc->sk_vpd_readonly == NULL) 403 panic("sk_vpd_read"); 404 for (i = 0; i < res.vr_len ; i++) 405 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 406 } 407 408 int 409 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 410 { 411 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 412 int i; 413 414 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 415 416 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 417 return 0; 418 419 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 420 SK_XM_READ_2(sc_if, XM_PHY_DATA); 421 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 422 for (i = 0; i < SK_TIMEOUT; i++) { 423 DELAY(1); 424 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 425 XM_MMUCMD_PHYDATARDY) 426 break; 427 } 428 429 if (i == SK_TIMEOUT) { 430 aprint_error_dev(&sc_if->sk_dev, "phy failed to come ready\n"); 431 return 0; 432 } 433 } 434 DELAY(1); 435 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 436 } 437 438 void 439 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 440 { 441 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 442 int i; 443 444 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 445 446 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 447 for (i = 0; i < SK_TIMEOUT; i++) { 448 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 449 break; 450 } 451 452 if (i == SK_TIMEOUT) { 453 aprint_error_dev(&sc_if->sk_dev, "phy failed to come ready\n"); 454 return; 455 } 456 457 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 458 for (i = 0; i < SK_TIMEOUT; i++) { 459 DELAY(1); 460 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 461 break; 462 } 463 464 if (i == SK_TIMEOUT) 465 aprint_error_dev(&sc_if->sk_dev, "phy write timed out\n"); 466 } 467 468 void 469 sk_xmac_miibus_statchg(struct device *dev) 470 { 471 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 472 struct mii_data *mii = &sc_if->sk_mii; 473 474 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 475 476 /* 477 * If this is a GMII PHY, manually set the XMAC's 478 * duplex mode accordingly. 479 */ 480 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 481 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 482 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 483 else 484 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 485 } 486 } 487 488 int 489 sk_marv_miibus_readreg(struct device *dev, int phy, int reg) 490 { 491 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 492 u_int16_t val; 493 int i; 494 495 if (phy != 0 || 496 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 497 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 498 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 499 phy, reg)); 500 return 0; 501 } 502 503 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 504 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 505 506 for (i = 0; i < SK_TIMEOUT; i++) { 507 DELAY(1); 508 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 509 if (val & YU_SMICR_READ_VALID) 510 break; 511 } 512 513 if (i == SK_TIMEOUT) { 514 aprint_error_dev(&sc_if->sk_dev, "phy failed to come ready\n"); 515 return 0; 516 } 517 518 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 519 SK_TIMEOUT)); 520 521 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 522 523 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 524 phy, reg, val)); 525 526 return val; 527 } 528 529 void 530 sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 531 { 532 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 533 int i; 534 535 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 536 phy, reg, val)); 537 538 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 539 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 540 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 541 542 for (i = 0; i < SK_TIMEOUT; i++) { 543 DELAY(1); 544 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 545 break; 546 } 547 548 if (i == SK_TIMEOUT) 549 printf("%s: phy write timed out\n", device_xname(&sc_if->sk_dev)); 550 } 551 552 void 553 sk_marv_miibus_statchg(struct device *dev) 554 { 555 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 556 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 557 } 558 559 #define SK_HASH_BITS 6 560 561 u_int32_t 562 sk_xmac_hash(void *addr) 563 { 564 u_int32_t crc; 565 566 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 567 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 568 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 569 return crc; 570 } 571 572 u_int32_t 573 sk_yukon_hash(void *addr) 574 { 575 u_int32_t crc; 576 577 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 578 crc &= ((1 << SK_HASH_BITS) - 1); 579 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 580 return crc; 581 } 582 583 void 584 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 585 { 586 char *addr = addrv; 587 int base = XM_RXFILT_ENTRY(slot); 588 589 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 590 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 591 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 592 } 593 594 void 595 sk_setmulti(struct sk_if_softc *sc_if) 596 { 597 struct sk_softc *sc = sc_if->sk_softc; 598 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 599 u_int32_t hashes[2] = { 0, 0 }; 600 int h = 0, i; 601 struct ethercom *ec = &sc_if->sk_ethercom; 602 struct ether_multi *enm; 603 struct ether_multistep step; 604 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 605 606 /* First, zot all the existing filters. */ 607 switch (sc->sk_type) { 608 case SK_GENESIS: 609 for (i = 1; i < XM_RXFILT_MAX; i++) 610 sk_setfilt(sc_if, (void *)&dummy, i); 611 612 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 613 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 614 break; 615 case SK_YUKON: 616 case SK_YUKON_LITE: 617 case SK_YUKON_LP: 618 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 619 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 620 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 621 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 622 break; 623 } 624 625 /* Now program new ones. */ 626 allmulti: 627 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 628 hashes[0] = 0xFFFFFFFF; 629 hashes[1] = 0xFFFFFFFF; 630 } else { 631 i = 1; 632 /* First find the tail of the list. */ 633 ETHER_FIRST_MULTI(step, ec, enm); 634 while (enm != NULL) { 635 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 636 ETHER_ADDR_LEN)) { 637 ifp->if_flags |= IFF_ALLMULTI; 638 goto allmulti; 639 } 640 DPRINTFN(2,("multicast address %s\n", 641 ether_sprintf(enm->enm_addrlo))); 642 /* 643 * Program the first XM_RXFILT_MAX multicast groups 644 * into the perfect filter. For all others, 645 * use the hash table. 646 */ 647 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 648 sk_setfilt(sc_if, enm->enm_addrlo, i); 649 i++; 650 } 651 else { 652 switch (sc->sk_type) { 653 case SK_GENESIS: 654 h = sk_xmac_hash(enm->enm_addrlo); 655 break; 656 case SK_YUKON: 657 case SK_YUKON_LITE: 658 case SK_YUKON_LP: 659 h = sk_yukon_hash(enm->enm_addrlo); 660 break; 661 } 662 if (h < 32) 663 hashes[0] |= (1 << h); 664 else 665 hashes[1] |= (1 << (h - 32)); 666 } 667 668 ETHER_NEXT_MULTI(step, enm); 669 } 670 } 671 672 switch (sc->sk_type) { 673 case SK_GENESIS: 674 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 675 XM_MODE_RX_USE_PERFECT); 676 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 677 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 678 break; 679 case SK_YUKON: 680 case SK_YUKON_LITE: 681 case SK_YUKON_LP: 682 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 683 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 684 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 685 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 686 break; 687 } 688 } 689 690 int 691 sk_init_rx_ring(struct sk_if_softc *sc_if) 692 { 693 struct sk_chain_data *cd = &sc_if->sk_cdata; 694 struct sk_ring_data *rd = sc_if->sk_rdata; 695 int i; 696 697 bzero((char *)rd->sk_rx_ring, 698 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 699 700 for (i = 0; i < SK_RX_RING_CNT; i++) { 701 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 702 if (i == (SK_RX_RING_CNT - 1)) { 703 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 704 rd->sk_rx_ring[i].sk_next = 705 htole32(SK_RX_RING_ADDR(sc_if, 0)); 706 } else { 707 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 708 rd->sk_rx_ring[i].sk_next = 709 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 710 } 711 } 712 713 for (i = 0; i < SK_RX_RING_CNT; i++) { 714 if (sk_newbuf(sc_if, i, NULL, 715 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 716 aprint_error_dev(&sc_if->sk_dev, "failed alloc of %dth mbuf\n", i); 717 return ENOBUFS; 718 } 719 } 720 sc_if->sk_cdata.sk_rx_prod = 0; 721 sc_if->sk_cdata.sk_rx_cons = 0; 722 723 return 0; 724 } 725 726 int 727 sk_init_tx_ring(struct sk_if_softc *sc_if) 728 { 729 struct sk_chain_data *cd = &sc_if->sk_cdata; 730 struct sk_ring_data *rd = sc_if->sk_rdata; 731 int i; 732 733 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 734 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 735 736 for (i = 0; i < SK_TX_RING_CNT; i++) { 737 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 738 if (i == (SK_TX_RING_CNT - 1)) { 739 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 740 rd->sk_tx_ring[i].sk_next = 741 htole32(SK_TX_RING_ADDR(sc_if, 0)); 742 } else { 743 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 744 rd->sk_tx_ring[i].sk_next = 745 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 746 } 747 } 748 749 sc_if->sk_cdata.sk_tx_prod = 0; 750 sc_if->sk_cdata.sk_tx_cons = 0; 751 sc_if->sk_cdata.sk_tx_cnt = 0; 752 753 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 754 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 755 756 return 0; 757 } 758 759 int 760 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 761 bus_dmamap_t dmamap) 762 { 763 struct mbuf *m_new = NULL; 764 struct sk_chain *c; 765 struct sk_rx_desc *r; 766 767 if (m == NULL) { 768 void *buf = NULL; 769 770 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 771 if (m_new == NULL) { 772 aprint_error_dev(&sc_if->sk_dev, "no memory for rx list -- " 773 "packet dropped!\n"); 774 return ENOBUFS; 775 } 776 777 /* Allocate the jumbo buffer */ 778 buf = sk_jalloc(sc_if); 779 if (buf == NULL) { 780 m_freem(m_new); 781 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 782 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 783 return ENOBUFS; 784 } 785 786 /* Attach the buffer to the mbuf */ 787 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 788 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 789 790 } else { 791 /* 792 * We're re-using a previously allocated mbuf; 793 * be sure to re-init pointers and lengths to 794 * default values. 795 */ 796 m_new = m; 797 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 798 m_new->m_data = m_new->m_ext.ext_buf; 799 } 800 m_adj(m_new, ETHER_ALIGN); 801 802 c = &sc_if->sk_cdata.sk_rx_chain[i]; 803 r = c->sk_desc; 804 c->sk_mbuf = m_new; 805 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 806 (((vaddr_t)m_new->m_data 807 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 808 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 809 810 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 811 812 return 0; 813 } 814 815 /* 816 * Memory management for jumbo frames. 817 */ 818 819 int 820 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 821 { 822 struct sk_softc *sc = sc_if->sk_softc; 823 char *ptr, *kva; 824 bus_dma_segment_t seg; 825 int i, rseg, state, error; 826 struct sk_jpool_entry *entry; 827 828 state = error = 0; 829 830 /* Grab a big chunk o' storage. */ 831 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 832 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 833 aprint_error_dev(&sc->sk_dev, "can't alloc rx buffers\n"); 834 return ENOBUFS; 835 } 836 837 state = 1; 838 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 839 BUS_DMA_NOWAIT)) { 840 aprint_error_dev(&sc->sk_dev, "can't map dma buffers (%d bytes)\n", 841 SK_JMEM); 842 error = ENOBUFS; 843 goto out; 844 } 845 846 state = 2; 847 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 848 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 849 aprint_error_dev(&sc->sk_dev, "can't create dma map\n"); 850 error = ENOBUFS; 851 goto out; 852 } 853 854 state = 3; 855 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 856 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 857 aprint_error_dev(&sc->sk_dev, "can't load dma map\n"); 858 error = ENOBUFS; 859 goto out; 860 } 861 862 state = 4; 863 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 864 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 865 866 LIST_INIT(&sc_if->sk_jfree_listhead); 867 LIST_INIT(&sc_if->sk_jinuse_listhead); 868 869 /* 870 * Now divide it up into 9K pieces and save the addresses 871 * in an array. 872 */ 873 ptr = sc_if->sk_cdata.sk_jumbo_buf; 874 for (i = 0; i < SK_JSLOTS; i++) { 875 sc_if->sk_cdata.sk_jslots[i] = ptr; 876 ptr += SK_JLEN; 877 entry = malloc(sizeof(struct sk_jpool_entry), 878 M_DEVBUF, M_NOWAIT); 879 if (entry == NULL) { 880 aprint_error_dev(&sc->sk_dev, "no memory for jumbo buffer queue!\n"); 881 error = ENOBUFS; 882 goto out; 883 } 884 entry->slot = i; 885 if (i) 886 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 887 entry, jpool_entries); 888 else 889 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 890 entry, jpool_entries); 891 } 892 out: 893 if (error != 0) { 894 switch (state) { 895 case 4: 896 bus_dmamap_unload(sc->sc_dmatag, 897 sc_if->sk_cdata.sk_rx_jumbo_map); 898 case 3: 899 bus_dmamap_destroy(sc->sc_dmatag, 900 sc_if->sk_cdata.sk_rx_jumbo_map); 901 case 2: 902 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 903 case 1: 904 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 905 break; 906 default: 907 break; 908 } 909 } 910 911 return error; 912 } 913 914 /* 915 * Allocate a jumbo buffer. 916 */ 917 void * 918 sk_jalloc(struct sk_if_softc *sc_if) 919 { 920 struct sk_jpool_entry *entry; 921 922 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 923 924 if (entry == NULL) 925 return NULL; 926 927 LIST_REMOVE(entry, jpool_entries); 928 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 929 return sc_if->sk_cdata.sk_jslots[entry->slot]; 930 } 931 932 /* 933 * Release a jumbo buffer. 934 */ 935 void 936 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 937 { 938 struct sk_jpool_entry *entry; 939 struct sk_if_softc *sc; 940 int i, s; 941 942 /* Extract the softc struct pointer. */ 943 sc = (struct sk_if_softc *)arg; 944 945 if (sc == NULL) 946 panic("sk_jfree: can't find softc pointer!"); 947 948 /* calculate the slot this buffer belongs to */ 949 950 i = ((vaddr_t)buf 951 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 952 953 if ((i < 0) || (i >= SK_JSLOTS)) 954 panic("sk_jfree: asked to free buffer that we don't manage!"); 955 956 s = splvm(); 957 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 958 if (entry == NULL) 959 panic("sk_jfree: buffer not in use!"); 960 entry->slot = i; 961 LIST_REMOVE(entry, jpool_entries); 962 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 963 964 if (__predict_true(m != NULL)) 965 pool_cache_put(mb_cache, m); 966 splx(s); 967 } 968 969 /* 970 * Set media options. 971 */ 972 int 973 sk_ifmedia_upd(struct ifnet *ifp) 974 { 975 struct sk_if_softc *sc_if = ifp->if_softc; 976 int rc; 977 978 (void) sk_init(ifp); 979 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 980 return 0; 981 return rc; 982 } 983 984 int 985 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 986 { 987 struct sk_if_softc *sc_if = ifp->if_softc; 988 struct sk_softc *sc = sc_if->sk_softc; 989 int s, error = 0; 990 991 /* DPRINTFN(2, ("sk_ioctl\n")); */ 992 993 s = splnet(); 994 995 switch (command) { 996 997 case SIOCSIFFLAGS: 998 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 999 if (ifp->if_flags & IFF_UP) { 1000 if (ifp->if_flags & IFF_RUNNING && 1001 ifp->if_flags & IFF_PROMISC && 1002 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1003 switch (sc->sk_type) { 1004 case SK_GENESIS: 1005 SK_XM_SETBIT_4(sc_if, XM_MODE, 1006 XM_MODE_RX_PROMISC); 1007 break; 1008 case SK_YUKON: 1009 case SK_YUKON_LITE: 1010 case SK_YUKON_LP: 1011 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1012 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1013 break; 1014 } 1015 sk_setmulti(sc_if); 1016 } else if (ifp->if_flags & IFF_RUNNING && 1017 !(ifp->if_flags & IFF_PROMISC) && 1018 sc_if->sk_if_flags & IFF_PROMISC) { 1019 switch (sc->sk_type) { 1020 case SK_GENESIS: 1021 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1022 XM_MODE_RX_PROMISC); 1023 break; 1024 case SK_YUKON: 1025 case SK_YUKON_LITE: 1026 case SK_YUKON_LP: 1027 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1028 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1029 break; 1030 } 1031 1032 sk_setmulti(sc_if); 1033 } else 1034 (void) sk_init(ifp); 1035 } else { 1036 if (ifp->if_flags & IFF_RUNNING) 1037 sk_stop(ifp,0); 1038 } 1039 sc_if->sk_if_flags = ifp->if_flags; 1040 error = 0; 1041 break; 1042 1043 default: 1044 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1045 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1046 break; 1047 1048 error = 0; 1049 1050 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1051 ; 1052 else if (ifp->if_flags & IFF_RUNNING) { 1053 sk_setmulti(sc_if); 1054 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1055 } 1056 break; 1057 } 1058 1059 splx(s); 1060 return error; 1061 } 1062 1063 void 1064 sk_update_int_mod(struct sk_softc *sc) 1065 { 1066 u_int32_t imtimer_ticks; 1067 1068 /* 1069 * Configure interrupt moderation. The moderation timer 1070 * defers interrupts specified in the interrupt moderation 1071 * timer mask based on the timeout specified in the interrupt 1072 * moderation timer init register. Each bit in the timer 1073 * register represents one tick, so to specify a timeout in 1074 * microseconds, we have to multiply by the correct number of 1075 * ticks-per-microsecond. 1076 */ 1077 switch (sc->sk_type) { 1078 case SK_GENESIS: 1079 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1080 break; 1081 case SK_YUKON_EC: 1082 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1083 break; 1084 default: 1085 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1086 } 1087 aprint_verbose_dev(&sc->sk_dev, "interrupt moderation is %d us\n", 1088 sc->sk_int_mod); 1089 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1090 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1091 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1092 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1093 sc->sk_int_mod_pending = 0; 1094 } 1095 1096 /* 1097 * Lookup: Check the PCI vendor and device, and return a pointer to 1098 * The structure if the IDs match against our list. 1099 */ 1100 1101 static const struct sk_product * 1102 sk_lookup(const struct pci_attach_args *pa) 1103 { 1104 const struct sk_product *psk; 1105 1106 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1107 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1108 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1109 return psk; 1110 } 1111 return NULL; 1112 } 1113 1114 /* 1115 * Probe for a SysKonnect GEnesis chip. 1116 */ 1117 1118 int 1119 skc_probe(struct device *parent, struct cfdata *match, 1120 void *aux) 1121 { 1122 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1123 const struct sk_product *psk; 1124 pcireg_t subid; 1125 1126 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1127 1128 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1129 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1130 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1131 subid == SK_LINKSYS_EG1032_SUBID) 1132 return 1; 1133 1134 if ((psk = sk_lookup(pa))) { 1135 return 1; 1136 } 1137 return 0; 1138 } 1139 1140 /* 1141 * Force the GEnesis into reset, then bring it out of reset. 1142 */ 1143 void sk_reset(struct sk_softc *sc) 1144 { 1145 DPRINTFN(2, ("sk_reset\n")); 1146 1147 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1148 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1149 if (SK_YUKON_FAMILY(sc->sk_type)) 1150 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1151 1152 DELAY(1000); 1153 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1154 DELAY(2); 1155 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1156 if (SK_YUKON_FAMILY(sc->sk_type)) 1157 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1158 1159 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1160 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1161 CSR_READ_2(sc, SK_LINK_CTRL))); 1162 1163 if (sc->sk_type == SK_GENESIS) { 1164 /* Configure packet arbiter */ 1165 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1166 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1167 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1168 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1169 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1170 } 1171 1172 /* Enable RAM interface */ 1173 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1174 1175 sk_update_int_mod(sc); 1176 } 1177 1178 int 1179 sk_probe(struct device *parent, struct cfdata *match, 1180 void *aux) 1181 { 1182 struct skc_attach_args *sa = aux; 1183 1184 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1185 return 0; 1186 1187 return 1; 1188 } 1189 1190 /* 1191 * Each XMAC chip is attached as a separate logical IP interface. 1192 * Single port cards will have only one logical interface of course. 1193 */ 1194 void 1195 sk_attach(struct device *parent, struct device *self, void *aux) 1196 { 1197 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1198 struct sk_softc *sc = (struct sk_softc *)parent; 1199 struct skc_attach_args *sa = aux; 1200 struct sk_txmap_entry *entry; 1201 struct ifnet *ifp; 1202 bus_dma_segment_t seg; 1203 bus_dmamap_t dmamap; 1204 void *kva; 1205 int i, rseg; 1206 1207 aprint_naive("\n"); 1208 1209 sc_if->sk_port = sa->skc_port; 1210 sc_if->sk_softc = sc; 1211 sc->sk_if[sa->skc_port] = sc_if; 1212 1213 if (sa->skc_port == SK_PORT_A) 1214 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1215 if (sa->skc_port == SK_PORT_B) 1216 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1217 1218 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1219 1220 /* 1221 * Get station address for this interface. Note that 1222 * dual port cards actually come with three station 1223 * addresses: one for each port, plus an extra. The 1224 * extra one is used by the SysKonnect driver software 1225 * as a 'virtual' station address for when both ports 1226 * are operating in failover mode. Currently we don't 1227 * use this extra address. 1228 */ 1229 for (i = 0; i < ETHER_ADDR_LEN; i++) 1230 sc_if->sk_enaddr[i] = 1231 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1232 1233 1234 aprint_normal(": Ethernet address %s\n", 1235 ether_sprintf(sc_if->sk_enaddr)); 1236 1237 /* 1238 * Set up RAM buffer addresses. The NIC will have a certain 1239 * amount of SRAM on it, somewhere between 512K and 2MB. We 1240 * need to divide this up a) between the transmitter and 1241 * receiver and b) between the two XMACs, if this is a 1242 * dual port NIC. Our algorithm is to divide up the memory 1243 * evenly so that everyone gets a fair share. 1244 */ 1245 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1246 u_int32_t chunk, val; 1247 1248 chunk = sc->sk_ramsize / 2; 1249 val = sc->sk_rboff / sizeof(u_int64_t); 1250 sc_if->sk_rx_ramstart = val; 1251 val += (chunk / sizeof(u_int64_t)); 1252 sc_if->sk_rx_ramend = val - 1; 1253 sc_if->sk_tx_ramstart = val; 1254 val += (chunk / sizeof(u_int64_t)); 1255 sc_if->sk_tx_ramend = val - 1; 1256 } else { 1257 u_int32_t chunk, val; 1258 1259 chunk = sc->sk_ramsize / 4; 1260 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1261 sizeof(u_int64_t); 1262 sc_if->sk_rx_ramstart = val; 1263 val += (chunk / sizeof(u_int64_t)); 1264 sc_if->sk_rx_ramend = val - 1; 1265 sc_if->sk_tx_ramstart = val; 1266 val += (chunk / sizeof(u_int64_t)); 1267 sc_if->sk_tx_ramend = val - 1; 1268 } 1269 1270 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1271 " tx_ramstart=%#x tx_ramend=%#x\n", 1272 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1273 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1274 1275 /* Read and save PHY type and set PHY address */ 1276 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1277 switch (sc_if->sk_phytype) { 1278 case SK_PHYTYPE_XMAC: 1279 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1280 break; 1281 case SK_PHYTYPE_BCOM: 1282 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1283 break; 1284 case SK_PHYTYPE_MARV_COPPER: 1285 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1286 break; 1287 default: 1288 aprint_error_dev(&sc->sk_dev, "unsupported PHY type: %d\n", 1289 sc_if->sk_phytype); 1290 return; 1291 } 1292 1293 /* Allocate the descriptor queues. */ 1294 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1295 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1296 aprint_error_dev(&sc->sk_dev, "can't alloc rx buffers\n"); 1297 goto fail; 1298 } 1299 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1300 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1301 aprint_error_dev(&sc_if->sk_dev, "can't map dma buffers (%lu bytes)\n", 1302 (u_long) sizeof(struct sk_ring_data)); 1303 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1304 goto fail; 1305 } 1306 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1307 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1308 &sc_if->sk_ring_map)) { 1309 aprint_error_dev(&sc_if->sk_dev, "can't create dma map\n"); 1310 bus_dmamem_unmap(sc->sc_dmatag, kva, 1311 sizeof(struct sk_ring_data)); 1312 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1313 goto fail; 1314 } 1315 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1316 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1317 aprint_error_dev(&sc_if->sk_dev, "can't load dma map\n"); 1318 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1319 bus_dmamem_unmap(sc->sc_dmatag, kva, 1320 sizeof(struct sk_ring_data)); 1321 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1322 goto fail; 1323 } 1324 1325 for (i = 0; i < SK_RX_RING_CNT; i++) 1326 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1327 1328 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1329 for (i = 0; i < SK_TX_RING_CNT; i++) { 1330 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1331 1332 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1333 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1334 aprint_error_dev(&sc_if->sk_dev, "Can't create TX dmamap\n"); 1335 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1336 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1337 bus_dmamem_unmap(sc->sc_dmatag, kva, 1338 sizeof(struct sk_ring_data)); 1339 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1340 goto fail; 1341 } 1342 1343 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1344 if (!entry) { 1345 aprint_error_dev(&sc_if->sk_dev, "Can't alloc txmap entry\n"); 1346 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1347 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1348 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1349 bus_dmamem_unmap(sc->sc_dmatag, kva, 1350 sizeof(struct sk_ring_data)); 1351 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1352 goto fail; 1353 } 1354 entry->dmamap = dmamap; 1355 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1356 } 1357 1358 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1359 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1360 1361 ifp = &sc_if->sk_ethercom.ec_if; 1362 /* Try to allocate memory for jumbo buffers. */ 1363 if (sk_alloc_jumbo_mem(sc_if)) { 1364 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1365 goto fail; 1366 } 1367 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1368 | ETHERCAP_JUMBO_MTU; 1369 1370 ifp->if_softc = sc_if; 1371 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1372 ifp->if_ioctl = sk_ioctl; 1373 ifp->if_start = sk_start; 1374 ifp->if_stop = sk_stop; 1375 ifp->if_init = sk_init; 1376 ifp->if_watchdog = sk_watchdog; 1377 ifp->if_capabilities = 0; 1378 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1379 IFQ_SET_READY(&ifp->if_snd); 1380 strlcpy(ifp->if_xname, device_xname(&sc_if->sk_dev), IFNAMSIZ); 1381 1382 /* 1383 * Do miibus setup. 1384 */ 1385 switch (sc->sk_type) { 1386 case SK_GENESIS: 1387 sk_init_xmac(sc_if); 1388 break; 1389 case SK_YUKON: 1390 case SK_YUKON_LITE: 1391 case SK_YUKON_LP: 1392 sk_init_yukon(sc_if); 1393 break; 1394 default: 1395 aprint_error_dev(&sc->sk_dev, "unknown device type %d\n", 1396 sc->sk_type); 1397 goto fail; 1398 } 1399 1400 DPRINTFN(2, ("sk_attach: 1\n")); 1401 1402 sc_if->sk_mii.mii_ifp = ifp; 1403 switch (sc->sk_type) { 1404 case SK_GENESIS: 1405 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1406 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1407 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1408 break; 1409 case SK_YUKON: 1410 case SK_YUKON_LITE: 1411 case SK_YUKON_LP: 1412 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1413 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1414 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1415 break; 1416 } 1417 1418 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1419 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1420 sk_ifmedia_upd, ether_mediastatus); 1421 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1422 MII_OFFSET_ANY, 0); 1423 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1424 aprint_error_dev(&sc_if->sk_dev, "no PHY found!\n"); 1425 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1426 0, NULL); 1427 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1428 } else 1429 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1430 1431 callout_init(&sc_if->sk_tick_ch, 0); 1432 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1433 1434 DPRINTFN(2, ("sk_attach: 1\n")); 1435 1436 /* 1437 * Call MI attach routines. 1438 */ 1439 if_attach(ifp); 1440 1441 ether_ifattach(ifp, sc_if->sk_enaddr); 1442 1443 #if NRND > 0 1444 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sk_dev), 1445 RND_TYPE_NET, 0); 1446 #endif 1447 1448 DPRINTFN(2, ("sk_attach: end\n")); 1449 1450 return; 1451 1452 fail: 1453 sc->sk_if[sa->skc_port] = NULL; 1454 } 1455 1456 int 1457 skcprint(void *aux, const char *pnp) 1458 { 1459 struct skc_attach_args *sa = aux; 1460 1461 if (pnp) 1462 aprint_normal("sk port %c at %s", 1463 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1464 else 1465 aprint_normal(" port %c", 1466 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1467 return UNCONF; 1468 } 1469 1470 /* 1471 * Attach the interface. Allocate softc structures, do ifmedia 1472 * setup and ethernet/BPF attach. 1473 */ 1474 void 1475 skc_attach(struct device *parent, struct device *self, void *aux) 1476 { 1477 struct sk_softc *sc = (struct sk_softc *)self; 1478 struct pci_attach_args *pa = aux; 1479 struct skc_attach_args skca; 1480 pci_chipset_tag_t pc = pa->pa_pc; 1481 #ifndef SK_USEIOSPACE 1482 pcireg_t memtype; 1483 #endif 1484 pci_intr_handle_t ih; 1485 const char *intrstr = NULL; 1486 bus_addr_t iobase; 1487 bus_size_t iosize; 1488 int rc, sk_nodenum; 1489 u_int32_t command; 1490 const char *revstr; 1491 const struct sysctlnode *node; 1492 1493 aprint_naive("\n"); 1494 1495 DPRINTFN(2, ("begin skc_attach\n")); 1496 1497 /* 1498 * Handle power management nonsense. 1499 */ 1500 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1501 1502 if (command == 0x01) { 1503 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1504 if (command & SK_PSTATE_MASK) { 1505 u_int32_t xiobase, membase, irq; 1506 1507 /* Save important PCI config data. */ 1508 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1509 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1510 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1511 1512 /* Reset the power state. */ 1513 aprint_normal_dev(&sc->sk_dev, "chip is in D%d power mode " 1514 "-- setting to D0\n", 1515 command & SK_PSTATE_MASK); 1516 command &= 0xFFFFFFFC; 1517 pci_conf_write(pc, pa->pa_tag, 1518 SK_PCI_PWRMGMTCTRL, command); 1519 1520 /* Restore PCI config data. */ 1521 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1522 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1523 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1524 } 1525 } 1526 1527 /* 1528 * Map control/status registers. 1529 */ 1530 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1531 command |= PCI_COMMAND_IO_ENABLE | 1532 PCI_COMMAND_MEM_ENABLE | 1533 PCI_COMMAND_MASTER_ENABLE; 1534 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1535 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1536 1537 #ifdef SK_USEIOSPACE 1538 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1539 aprint_error(": failed to enable I/O ports!\n"); 1540 return; 1541 } 1542 /* 1543 * Map control/status registers. 1544 */ 1545 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1546 &sc->sk_btag, &sc->sk_bhandle, 1547 &iobase, &iosize)) { 1548 aprint_error(": can't find i/o space\n"); 1549 return; 1550 } 1551 #else 1552 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1553 aprint_error(": failed to enable memory mapping!\n"); 1554 return; 1555 } 1556 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1557 switch (memtype) { 1558 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1559 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1560 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1561 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1562 &iobase, &iosize) == 0) 1563 break; 1564 default: 1565 aprint_error_dev(&sc->sk_dev, "can't find mem space\n"); 1566 return; 1567 } 1568 1569 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1570 #endif 1571 sc->sc_dmatag = pa->pa_dmat; 1572 1573 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1574 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1575 1576 /* bail out here if chip is not recognized */ 1577 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1578 aprint_error_dev(&sc->sk_dev, "unknown chip type\n"); 1579 goto fail; 1580 } 1581 if (SK_IS_YUKON2(sc)) { 1582 aprint_error_dev(&sc->sk_dev, "Does not support Yukon2--try msk(4).\n"); 1583 goto fail; 1584 } 1585 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1586 1587 /* Allocate interrupt */ 1588 if (pci_intr_map(pa, &ih)) { 1589 aprint_error(": couldn't map interrupt\n"); 1590 goto fail; 1591 } 1592 1593 intrstr = pci_intr_string(pc, ih); 1594 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1595 if (sc->sk_intrhand == NULL) { 1596 aprint_error(": couldn't establish interrupt"); 1597 if (intrstr != NULL) 1598 aprint_normal(" at %s", intrstr); 1599 goto fail; 1600 } 1601 aprint_normal(": %s\n", intrstr); 1602 1603 /* Reset the adapter. */ 1604 sk_reset(sc); 1605 1606 /* Read and save vital product data from EEPROM. */ 1607 sk_vpd_read(sc); 1608 1609 if (sc->sk_type == SK_GENESIS) { 1610 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1611 /* Read and save RAM size and RAMbuffer offset */ 1612 switch (val) { 1613 case SK_RAMSIZE_512K_64: 1614 sc->sk_ramsize = 0x80000; 1615 sc->sk_rboff = SK_RBOFF_0; 1616 break; 1617 case SK_RAMSIZE_1024K_64: 1618 sc->sk_ramsize = 0x100000; 1619 sc->sk_rboff = SK_RBOFF_80000; 1620 break; 1621 case SK_RAMSIZE_1024K_128: 1622 sc->sk_ramsize = 0x100000; 1623 sc->sk_rboff = SK_RBOFF_0; 1624 break; 1625 case SK_RAMSIZE_2048K_128: 1626 sc->sk_ramsize = 0x200000; 1627 sc->sk_rboff = SK_RBOFF_0; 1628 break; 1629 default: 1630 aprint_error_dev(&sc->sk_dev, "unknown ram size: %d\n", 1631 val); 1632 goto fail_1; 1633 break; 1634 } 1635 1636 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1637 sc->sk_ramsize, sc->sk_ramsize / 1024, 1638 sc->sk_rboff)); 1639 } else { 1640 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1641 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1642 sc->sk_rboff = SK_RBOFF_0; 1643 1644 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1645 sc->sk_ramsize / 1024, sc->sk_ramsize, 1646 sc->sk_rboff)); 1647 } 1648 1649 /* Read and save physical media type */ 1650 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1651 case SK_PMD_1000BASESX: 1652 sc->sk_pmd = IFM_1000_SX; 1653 break; 1654 case SK_PMD_1000BASELX: 1655 sc->sk_pmd = IFM_1000_LX; 1656 break; 1657 case SK_PMD_1000BASECX: 1658 sc->sk_pmd = IFM_1000_CX; 1659 break; 1660 case SK_PMD_1000BASETX: 1661 case SK_PMD_1000BASETX_ALT: 1662 sc->sk_pmd = IFM_1000_T; 1663 break; 1664 default: 1665 aprint_error_dev(&sc->sk_dev, "unknown media type: 0x%x\n", 1666 sk_win_read_1(sc, SK_PMDTYPE)); 1667 goto fail_1; 1668 } 1669 1670 /* determine whether to name it with vpd or just make it up */ 1671 /* Marvell Yukon VPD's can freqently be bogus */ 1672 1673 switch (pa->pa_id) { 1674 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1675 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1676 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1677 case PCI_PRODUCT_3COM_3C940: 1678 case PCI_PRODUCT_DLINK_DGE530T: 1679 case PCI_PRODUCT_DLINK_DGE560T: 1680 case PCI_PRODUCT_DLINK_DGE560T_2: 1681 case PCI_PRODUCT_LINKSYS_EG1032: 1682 case PCI_PRODUCT_LINKSYS_EG1064: 1683 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1684 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1685 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1686 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1687 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1688 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1689 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1690 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1691 sc->sk_name = sc->sk_vpd_prodname; 1692 break; 1693 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1694 /* whoops yukon vpd prodname bears no resemblance to reality */ 1695 switch (sc->sk_type) { 1696 case SK_GENESIS: 1697 sc->sk_name = sc->sk_vpd_prodname; 1698 break; 1699 case SK_YUKON: 1700 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1701 break; 1702 case SK_YUKON_LITE: 1703 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1704 break; 1705 case SK_YUKON_LP: 1706 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1707 break; 1708 default: 1709 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1710 } 1711 1712 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1713 1714 if ( sc->sk_type == SK_YUKON ) { 1715 uint32_t flashaddr; 1716 uint8_t testbyte; 1717 1718 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1719 1720 /* test Flash-Address Register */ 1721 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1722 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1723 1724 if (testbyte != 0) { 1725 /* this is yukon lite Rev. A0 */ 1726 sc->sk_type = SK_YUKON_LITE; 1727 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1728 /* restore Flash-Address Register */ 1729 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1730 } 1731 } 1732 break; 1733 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1734 sc->sk_name = sc->sk_vpd_prodname; 1735 break; 1736 default: 1737 sc->sk_name = "Unknown Marvell"; 1738 } 1739 1740 1741 if ( sc->sk_type == SK_YUKON_LITE ) { 1742 switch (sc->sk_rev) { 1743 case SK_YUKON_LITE_REV_A0: 1744 revstr = "A0"; 1745 break; 1746 case SK_YUKON_LITE_REV_A1: 1747 revstr = "A1"; 1748 break; 1749 case SK_YUKON_LITE_REV_A3: 1750 revstr = "A3"; 1751 break; 1752 default: 1753 revstr = ""; 1754 } 1755 } else { 1756 revstr = ""; 1757 } 1758 1759 /* Announce the product name. */ 1760 aprint_normal_dev(&sc->sk_dev, "%s rev. %s(0x%x)\n", 1761 sc->sk_name, revstr, sc->sk_rev); 1762 1763 skca.skc_port = SK_PORT_A; 1764 (void)config_found(&sc->sk_dev, &skca, skcprint); 1765 1766 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1767 skca.skc_port = SK_PORT_B; 1768 (void)config_found(&sc->sk_dev, &skca, skcprint); 1769 } 1770 1771 /* Turn on the 'driver is loaded' LED. */ 1772 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1773 1774 /* skc sysctl setup */ 1775 1776 sc->sk_int_mod = SK_IM_DEFAULT; 1777 sc->sk_int_mod_pending = 0; 1778 1779 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1780 0, CTLTYPE_NODE, device_xname(&sc->sk_dev), 1781 SYSCTL_DESCR("skc per-controller controls"), 1782 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1783 CTL_EOL)) != 0) { 1784 aprint_normal_dev(&sc->sk_dev, "couldn't create sysctl node\n"); 1785 goto fail_1; 1786 } 1787 1788 sk_nodenum = node->sysctl_num; 1789 1790 /* interrupt moderation time in usecs */ 1791 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1792 CTLFLAG_READWRITE, 1793 CTLTYPE_INT, "int_mod", 1794 SYSCTL_DESCR("sk interrupt moderation timer"), 1795 sk_sysctl_handler, 0, sc, 1796 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1797 CTL_EOL)) != 0) { 1798 aprint_normal_dev(&sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1799 goto fail_1; 1800 } 1801 1802 return; 1803 1804 fail_1: 1805 pci_intr_disestablish(pc, sc->sk_intrhand); 1806 fail: 1807 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1808 } 1809 1810 int 1811 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1812 { 1813 struct sk_softc *sc = sc_if->sk_softc; 1814 struct sk_tx_desc *f = NULL; 1815 u_int32_t frag, cur, cnt = 0, sk_ctl; 1816 int i; 1817 struct sk_txmap_entry *entry; 1818 bus_dmamap_t txmap; 1819 1820 DPRINTFN(3, ("sk_encap\n")); 1821 1822 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1823 if (entry == NULL) { 1824 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1825 return ENOBUFS; 1826 } 1827 txmap = entry->dmamap; 1828 1829 cur = frag = *txidx; 1830 1831 #ifdef SK_DEBUG 1832 if (skdebug >= 3) 1833 sk_dump_mbuf(m_head); 1834 #endif 1835 1836 /* 1837 * Start packing the mbufs in this chain into 1838 * the fragment pointers. Stop when we run out 1839 * of fragments or hit the end of the mbuf chain. 1840 */ 1841 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1842 BUS_DMA_NOWAIT)) { 1843 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1844 return ENOBUFS; 1845 } 1846 1847 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1848 1849 /* Sync the DMA map. */ 1850 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1851 BUS_DMASYNC_PREWRITE); 1852 1853 for (i = 0; i < txmap->dm_nsegs; i++) { 1854 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1855 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1856 return ENOBUFS; 1857 } 1858 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1859 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1860 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1861 if (cnt == 0) 1862 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1863 else 1864 sk_ctl |= SK_TXCTL_OWN; 1865 f->sk_ctl = htole32(sk_ctl); 1866 cur = frag; 1867 SK_INC(frag, SK_TX_RING_CNT); 1868 cnt++; 1869 } 1870 1871 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1872 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1873 1874 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1875 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1876 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1877 1878 /* Sync descriptors before handing to chip */ 1879 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1880 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1881 1882 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1883 htole32(SK_TXCTL_OWN); 1884 1885 /* Sync first descriptor to hand it off */ 1886 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1887 1888 sc_if->sk_cdata.sk_tx_cnt += cnt; 1889 1890 #ifdef SK_DEBUG 1891 if (skdebug >= 3) { 1892 struct sk_tx_desc *desc; 1893 u_int32_t idx; 1894 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1895 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1896 sk_dump_txdesc(desc, idx); 1897 } 1898 } 1899 #endif 1900 1901 *txidx = frag; 1902 1903 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1904 1905 return 0; 1906 } 1907 1908 void 1909 sk_start(struct ifnet *ifp) 1910 { 1911 struct sk_if_softc *sc_if = ifp->if_softc; 1912 struct sk_softc *sc = sc_if->sk_softc; 1913 struct mbuf *m_head = NULL; 1914 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1915 int pkts = 0; 1916 1917 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1918 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1919 1920 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1921 IFQ_POLL(&ifp->if_snd, m_head); 1922 if (m_head == NULL) 1923 break; 1924 1925 /* 1926 * Pack the data into the transmit ring. If we 1927 * don't have room, set the OACTIVE flag and wait 1928 * for the NIC to drain the ring. 1929 */ 1930 if (sk_encap(sc_if, m_head, &idx)) { 1931 ifp->if_flags |= IFF_OACTIVE; 1932 break; 1933 } 1934 1935 /* now we are committed to transmit the packet */ 1936 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1937 pkts++; 1938 1939 /* 1940 * If there's a BPF listener, bounce a copy of this frame 1941 * to him. 1942 */ 1943 #if NBPFILTER > 0 1944 if (ifp->if_bpf) 1945 bpf_mtap(ifp->if_bpf, m_head); 1946 #endif 1947 } 1948 if (pkts == 0) 1949 return; 1950 1951 /* Transmit */ 1952 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1953 sc_if->sk_cdata.sk_tx_prod = idx; 1954 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1955 1956 /* Set a timeout in case the chip goes out to lunch. */ 1957 ifp->if_timer = 5; 1958 } 1959 } 1960 1961 1962 void 1963 sk_watchdog(struct ifnet *ifp) 1964 { 1965 struct sk_if_softc *sc_if = ifp->if_softc; 1966 1967 /* 1968 * Reclaim first as there is a possibility of losing Tx completion 1969 * interrupts. 1970 */ 1971 sk_txeof(sc_if); 1972 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1973 aprint_error_dev(&sc_if->sk_dev, "watchdog timeout\n"); 1974 1975 ifp->if_oerrors++; 1976 1977 sk_init(ifp); 1978 } 1979 } 1980 1981 void 1982 sk_shutdown(void *v) 1983 { 1984 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1985 struct sk_softc *sc = sc_if->sk_softc; 1986 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1987 1988 DPRINTFN(2, ("sk_shutdown\n")); 1989 sk_stop(ifp,1); 1990 1991 /* Turn off the 'driver is loaded' LED. */ 1992 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1993 1994 /* 1995 * Reset the GEnesis controller. Doing this should also 1996 * assert the resets on the attached XMAC(s). 1997 */ 1998 sk_reset(sc); 1999 } 2000 2001 void 2002 sk_rxeof(struct sk_if_softc *sc_if) 2003 { 2004 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2005 struct mbuf *m; 2006 struct sk_chain *cur_rx; 2007 struct sk_rx_desc *cur_desc; 2008 int i, cur, total_len = 0; 2009 u_int32_t rxstat, sk_ctl; 2010 bus_dmamap_t dmamap; 2011 2012 i = sc_if->sk_cdata.sk_rx_prod; 2013 2014 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2015 2016 for (;;) { 2017 cur = i; 2018 2019 /* Sync the descriptor */ 2020 SK_CDRXSYNC(sc_if, cur, 2021 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2022 2023 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2024 if (sk_ctl & SK_RXCTL_OWN) { 2025 /* Invalidate the descriptor -- it's not ready yet */ 2026 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2027 sc_if->sk_cdata.sk_rx_prod = i; 2028 break; 2029 } 2030 2031 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2032 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2033 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2034 2035 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2036 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2037 2038 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2039 m = cur_rx->sk_mbuf; 2040 cur_rx->sk_mbuf = NULL; 2041 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2042 2043 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2044 2045 SK_INC(i, SK_RX_RING_CNT); 2046 2047 if (rxstat & XM_RXSTAT_ERRFRAME) { 2048 ifp->if_ierrors++; 2049 sk_newbuf(sc_if, cur, m, dmamap); 2050 continue; 2051 } 2052 2053 /* 2054 * Try to allocate a new jumbo buffer. If that 2055 * fails, copy the packet to mbufs and put the 2056 * jumbo buffer back in the ring so it can be 2057 * re-used. If allocating mbufs fails, then we 2058 * have to drop the packet. 2059 */ 2060 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2061 struct mbuf *m0; 2062 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2063 total_len + ETHER_ALIGN, 0, ifp, NULL); 2064 sk_newbuf(sc_if, cur, m, dmamap); 2065 if (m0 == NULL) { 2066 aprint_error_dev(&sc_if->sk_dev, "no receive buffers " 2067 "available -- packet dropped!\n"); 2068 ifp->if_ierrors++; 2069 continue; 2070 } 2071 m_adj(m0, ETHER_ALIGN); 2072 m = m0; 2073 } else { 2074 m->m_pkthdr.rcvif = ifp; 2075 m->m_pkthdr.len = m->m_len = total_len; 2076 } 2077 2078 ifp->if_ipackets++; 2079 2080 #if NBPFILTER > 0 2081 if (ifp->if_bpf) 2082 bpf_mtap(ifp->if_bpf, m); 2083 #endif 2084 /* pass it on. */ 2085 (*ifp->if_input)(ifp, m); 2086 } 2087 } 2088 2089 void 2090 sk_txeof(struct sk_if_softc *sc_if) 2091 { 2092 struct sk_softc *sc = sc_if->sk_softc; 2093 struct sk_tx_desc *cur_tx; 2094 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2095 u_int32_t idx, sk_ctl; 2096 struct sk_txmap_entry *entry; 2097 2098 DPRINTFN(3, ("sk_txeof\n")); 2099 2100 /* 2101 * Go through our tx ring and free mbufs for those 2102 * frames that have been sent. 2103 */ 2104 idx = sc_if->sk_cdata.sk_tx_cons; 2105 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2106 SK_CDTXSYNC(sc_if, idx, 1, 2107 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2108 2109 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2110 sk_ctl = le32toh(cur_tx->sk_ctl); 2111 #ifdef SK_DEBUG 2112 if (skdebug >= 3) 2113 sk_dump_txdesc(cur_tx, idx); 2114 #endif 2115 if (sk_ctl & SK_TXCTL_OWN) { 2116 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2117 break; 2118 } 2119 if (sk_ctl & SK_TXCTL_LASTFRAG) 2120 ifp->if_opackets++; 2121 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2122 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2123 2124 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2125 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2126 2127 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2128 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2129 2130 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2131 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2132 link); 2133 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2134 } 2135 sc_if->sk_cdata.sk_tx_cnt--; 2136 SK_INC(idx, SK_TX_RING_CNT); 2137 } 2138 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2139 ifp->if_timer = 0; 2140 else /* nudge chip to keep tx ring moving */ 2141 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2142 2143 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2144 ifp->if_flags &= ~IFF_OACTIVE; 2145 2146 sc_if->sk_cdata.sk_tx_cons = idx; 2147 } 2148 2149 void 2150 sk_tick(void *xsc_if) 2151 { 2152 struct sk_if_softc *sc_if = xsc_if; 2153 struct mii_data *mii = &sc_if->sk_mii; 2154 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2155 int i; 2156 2157 DPRINTFN(3, ("sk_tick\n")); 2158 2159 if (!(ifp->if_flags & IFF_UP)) 2160 return; 2161 2162 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2163 sk_intr_bcom(sc_if); 2164 return; 2165 } 2166 2167 /* 2168 * According to SysKonnect, the correct way to verify that 2169 * the link has come back up is to poll bit 0 of the GPIO 2170 * register three times. This pin has the signal from the 2171 * link sync pin connected to it; if we read the same link 2172 * state 3 times in a row, we know the link is up. 2173 */ 2174 for (i = 0; i < 3; i++) { 2175 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2176 break; 2177 } 2178 2179 if (i != 3) { 2180 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2181 return; 2182 } 2183 2184 /* Turn the GP0 interrupt back on. */ 2185 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2186 SK_XM_READ_2(sc_if, XM_ISR); 2187 mii_tick(mii); 2188 mii_pollstat(mii); 2189 callout_stop(&sc_if->sk_tick_ch); 2190 } 2191 2192 void 2193 sk_intr_bcom(struct sk_if_softc *sc_if) 2194 { 2195 struct mii_data *mii = &sc_if->sk_mii; 2196 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2197 int status; 2198 2199 2200 DPRINTFN(3, ("sk_intr_bcom\n")); 2201 2202 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2203 2204 /* 2205 * Read the PHY interrupt register to make sure 2206 * we clear any pending interrupts. 2207 */ 2208 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2209 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2210 2211 if (!(ifp->if_flags & IFF_RUNNING)) { 2212 sk_init_xmac(sc_if); 2213 return; 2214 } 2215 2216 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2217 int lstat; 2218 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2219 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2220 2221 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2222 (void)mii_mediachg(mii); 2223 /* Turn off the link LED. */ 2224 SK_IF_WRITE_1(sc_if, 0, 2225 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2226 sc_if->sk_link = 0; 2227 } else if (status & BRGPHY_ISR_LNK_CHG) { 2228 sk_xmac_miibus_writereg((struct device *)sc_if, 2229 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2230 mii_tick(mii); 2231 sc_if->sk_link = 1; 2232 /* Turn on the link LED. */ 2233 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2234 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2235 SK_LINKLED_BLINK_OFF); 2236 mii_pollstat(mii); 2237 } else { 2238 mii_tick(mii); 2239 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2240 } 2241 } 2242 2243 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2244 } 2245 2246 void 2247 sk_intr_xmac(struct sk_if_softc *sc_if) 2248 { 2249 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2250 2251 DPRINTFN(3, ("sk_intr_xmac\n")); 2252 2253 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2254 if (status & XM_ISR_GP0_SET) { 2255 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2256 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2257 } 2258 2259 if (status & XM_ISR_AUTONEG_DONE) { 2260 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2261 } 2262 } 2263 2264 if (status & XM_IMR_TX_UNDERRUN) 2265 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2266 2267 if (status & XM_IMR_RX_OVERRUN) 2268 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2269 } 2270 2271 void 2272 sk_intr_yukon(struct sk_if_softc *sc_if) 2273 { 2274 int status; 2275 2276 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2277 2278 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2279 } 2280 2281 int 2282 sk_intr(void *xsc) 2283 { 2284 struct sk_softc *sc = xsc; 2285 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2286 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2287 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2288 u_int32_t status; 2289 int claimed = 0; 2290 2291 if (sc_if0 != NULL) 2292 ifp0 = &sc_if0->sk_ethercom.ec_if; 2293 if (sc_if1 != NULL) 2294 ifp1 = &sc_if1->sk_ethercom.ec_if; 2295 2296 for (;;) { 2297 status = CSR_READ_4(sc, SK_ISSR); 2298 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2299 2300 if (!(status & sc->sk_intrmask)) 2301 break; 2302 2303 claimed = 1; 2304 2305 /* Handle receive interrupts first. */ 2306 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2307 sk_rxeof(sc_if0); 2308 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2309 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2310 } 2311 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2312 sk_rxeof(sc_if1); 2313 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2314 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2315 } 2316 2317 /* Then transmit interrupts. */ 2318 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2319 sk_txeof(sc_if0); 2320 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2321 SK_TXBMU_CLR_IRQ_EOF); 2322 } 2323 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2324 sk_txeof(sc_if1); 2325 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2326 SK_TXBMU_CLR_IRQ_EOF); 2327 } 2328 2329 /* Then MAC interrupts. */ 2330 if (sc_if0 && (status & SK_ISR_MAC1) && 2331 (ifp0->if_flags & IFF_RUNNING)) { 2332 if (sc->sk_type == SK_GENESIS) 2333 sk_intr_xmac(sc_if0); 2334 else 2335 sk_intr_yukon(sc_if0); 2336 } 2337 2338 if (sc_if1 && (status & SK_ISR_MAC2) && 2339 (ifp1->if_flags & IFF_RUNNING)) { 2340 if (sc->sk_type == SK_GENESIS) 2341 sk_intr_xmac(sc_if1); 2342 else 2343 sk_intr_yukon(sc_if1); 2344 2345 } 2346 2347 if (status & SK_ISR_EXTERNAL_REG) { 2348 if (sc_if0 != NULL && 2349 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2350 sk_intr_bcom(sc_if0); 2351 2352 if (sc_if1 != NULL && 2353 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2354 sk_intr_bcom(sc_if1); 2355 } 2356 } 2357 2358 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2359 2360 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2361 sk_start(ifp0); 2362 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2363 sk_start(ifp1); 2364 2365 #if NRND > 0 2366 if (RND_ENABLED(&sc->rnd_source)) 2367 rnd_add_uint32(&sc->rnd_source, status); 2368 #endif 2369 2370 if (sc->sk_int_mod_pending) 2371 sk_update_int_mod(sc); 2372 2373 return claimed; 2374 } 2375 2376 void 2377 sk_init_xmac(struct sk_if_softc *sc_if) 2378 { 2379 struct sk_softc *sc = sc_if->sk_softc; 2380 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2381 static const struct sk_bcom_hack bhack[] = { 2382 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2383 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2384 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2385 { 0, 0 } }; 2386 2387 DPRINTFN(1, ("sk_init_xmac\n")); 2388 2389 /* Unreset the XMAC. */ 2390 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2391 DELAY(1000); 2392 2393 /* Reset the XMAC's internal state. */ 2394 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2395 2396 /* Save the XMAC II revision */ 2397 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2398 2399 /* 2400 * Perform additional initialization for external PHYs, 2401 * namely for the 1000baseTX cards that use the XMAC's 2402 * GMII mode. 2403 */ 2404 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2405 int i = 0; 2406 u_int32_t val; 2407 2408 /* Take PHY out of reset. */ 2409 val = sk_win_read_4(sc, SK_GPIO); 2410 if (sc_if->sk_port == SK_PORT_A) 2411 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2412 else 2413 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2414 sk_win_write_4(sc, SK_GPIO, val); 2415 2416 /* Enable GMII mode on the XMAC. */ 2417 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2418 2419 sk_xmac_miibus_writereg((struct device *)sc_if, 2420 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2421 DELAY(10000); 2422 sk_xmac_miibus_writereg((struct device *)sc_if, 2423 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2424 2425 /* 2426 * Early versions of the BCM5400 apparently have 2427 * a bug that requires them to have their reserved 2428 * registers initialized to some magic values. I don't 2429 * know what the numbers do, I'm just the messenger. 2430 */ 2431 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2432 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2433 while (bhack[i].reg) { 2434 sk_xmac_miibus_writereg((struct device *)sc_if, 2435 SK_PHYADDR_BCOM, bhack[i].reg, 2436 bhack[i].val); 2437 i++; 2438 } 2439 } 2440 } 2441 2442 /* Set station address */ 2443 SK_XM_WRITE_2(sc_if, XM_PAR0, 2444 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2445 SK_XM_WRITE_2(sc_if, XM_PAR1, 2446 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2447 SK_XM_WRITE_2(sc_if, XM_PAR2, 2448 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2449 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2450 2451 if (ifp->if_flags & IFF_PROMISC) 2452 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2453 else 2454 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2455 2456 if (ifp->if_flags & IFF_BROADCAST) 2457 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2458 else 2459 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2460 2461 /* We don't need the FCS appended to the packet. */ 2462 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2463 2464 /* We want short frames padded to 60 bytes. */ 2465 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2466 2467 /* 2468 * Enable the reception of all error frames. This is is 2469 * a necessary evil due to the design of the XMAC. The 2470 * XMAC's receive FIFO is only 8K in size, however jumbo 2471 * frames can be up to 9000 bytes in length. When bad 2472 * frame filtering is enabled, the XMAC's RX FIFO operates 2473 * in 'store and forward' mode. For this to work, the 2474 * entire frame has to fit into the FIFO, but that means 2475 * that jumbo frames larger than 8192 bytes will be 2476 * truncated. Disabling all bad frame filtering causes 2477 * the RX FIFO to operate in streaming mode, in which 2478 * case the XMAC will start transfering frames out of the 2479 * RX FIFO as soon as the FIFO threshold is reached. 2480 */ 2481 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2482 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2483 XM_MODE_RX_INRANGELEN); 2484 2485 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2486 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2487 else 2488 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2489 2490 /* 2491 * Bump up the transmit threshold. This helps hold off transmit 2492 * underruns when we're blasting traffic from both ports at once. 2493 */ 2494 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2495 2496 /* Set multicast filter */ 2497 sk_setmulti(sc_if); 2498 2499 /* Clear and enable interrupts */ 2500 SK_XM_READ_2(sc_if, XM_ISR); 2501 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2502 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2503 else 2504 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2505 2506 /* Configure MAC arbiter */ 2507 switch (sc_if->sk_xmac_rev) { 2508 case XM_XMAC_REV_B2: 2509 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2510 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2511 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2512 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2513 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2514 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2515 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2516 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2517 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2518 break; 2519 case XM_XMAC_REV_C1: 2520 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2521 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2522 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2523 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2524 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2525 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2526 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2527 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2528 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2529 break; 2530 default: 2531 break; 2532 } 2533 sk_win_write_2(sc, SK_MACARB_CTL, 2534 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2535 2536 sc_if->sk_link = 1; 2537 } 2538 2539 void sk_init_yukon(struct sk_if_softc *sc_if) 2540 { 2541 u_int32_t /*mac, */phy; 2542 u_int16_t reg; 2543 struct sk_softc *sc; 2544 int i; 2545 2546 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2547 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2548 2549 sc = sc_if->sk_softc; 2550 if (sc->sk_type == SK_YUKON_LITE && 2551 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2552 /* Take PHY out of reset. */ 2553 sk_win_write_4(sc, SK_GPIO, 2554 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2555 } 2556 2557 2558 /* GMAC and GPHY Reset */ 2559 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2560 2561 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2562 2563 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2564 DELAY(1000); 2565 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2566 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2567 DELAY(1000); 2568 2569 2570 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2571 2572 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2573 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2574 2575 switch (sc_if->sk_softc->sk_pmd) { 2576 case IFM_1000_SX: 2577 case IFM_1000_LX: 2578 phy |= SK_GPHY_FIBER; 2579 break; 2580 2581 case IFM_1000_CX: 2582 case IFM_1000_T: 2583 phy |= SK_GPHY_COPPER; 2584 break; 2585 } 2586 2587 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2588 2589 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2590 DELAY(1000); 2591 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2592 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2593 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2594 2595 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2596 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2597 2598 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2599 2600 /* unused read of the interrupt source register */ 2601 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2602 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2603 2604 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2605 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2606 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2607 2608 /* MIB Counter Clear Mode set */ 2609 reg |= YU_PAR_MIB_CLR; 2610 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2611 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2612 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2613 2614 /* MIB Counter Clear Mode clear */ 2615 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2616 reg &= ~YU_PAR_MIB_CLR; 2617 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2618 2619 /* receive control reg */ 2620 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2621 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2622 YU_RCR_CRCR); 2623 2624 /* transmit parameter register */ 2625 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2626 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2627 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2628 2629 /* serial mode register */ 2630 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2631 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2632 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2633 YU_SMR_IPG_DATA(0x1e)); 2634 2635 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2636 /* Setup Yukon's address */ 2637 for (i = 0; i < 3; i++) { 2638 /* Write Source Address 1 (unicast filter) */ 2639 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2640 sc_if->sk_enaddr[i * 2] | 2641 sc_if->sk_enaddr[i * 2 + 1] << 8); 2642 } 2643 2644 for (i = 0; i < 3; i++) { 2645 reg = sk_win_read_2(sc_if->sk_softc, 2646 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2647 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2648 } 2649 2650 /* Set multicast filter */ 2651 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2652 sk_setmulti(sc_if); 2653 2654 /* enable interrupt mask for counter overflows */ 2655 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2656 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2657 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2658 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2659 2660 /* Configure RX MAC FIFO */ 2661 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2662 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2663 2664 /* Configure TX MAC FIFO */ 2665 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2666 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2667 2668 DPRINTFN(6, ("sk_init_yukon: end\n")); 2669 } 2670 2671 /* 2672 * Note that to properly initialize any part of the GEnesis chip, 2673 * you first have to take it out of reset mode. 2674 */ 2675 int 2676 sk_init(struct ifnet *ifp) 2677 { 2678 struct sk_if_softc *sc_if = ifp->if_softc; 2679 struct sk_softc *sc = sc_if->sk_softc; 2680 struct mii_data *mii = &sc_if->sk_mii; 2681 int rc = 0, s; 2682 u_int32_t imr, imtimer_ticks; 2683 2684 DPRINTFN(1, ("sk_init\n")); 2685 2686 s = splnet(); 2687 2688 if (ifp->if_flags & IFF_RUNNING) { 2689 splx(s); 2690 return 0; 2691 } 2692 2693 /* Cancel pending I/O and free all RX/TX buffers. */ 2694 sk_stop(ifp,0); 2695 2696 if (sc->sk_type == SK_GENESIS) { 2697 /* Configure LINK_SYNC LED */ 2698 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2699 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2700 SK_LINKLED_LINKSYNC_ON); 2701 2702 /* Configure RX LED */ 2703 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2704 SK_RXLEDCTL_COUNTER_START); 2705 2706 /* Configure TX LED */ 2707 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2708 SK_TXLEDCTL_COUNTER_START); 2709 } 2710 2711 /* Configure I2C registers */ 2712 2713 /* Configure XMAC(s) */ 2714 switch (sc->sk_type) { 2715 case SK_GENESIS: 2716 sk_init_xmac(sc_if); 2717 break; 2718 case SK_YUKON: 2719 case SK_YUKON_LITE: 2720 case SK_YUKON_LP: 2721 sk_init_yukon(sc_if); 2722 break; 2723 } 2724 if ((rc = mii_mediachg(mii)) == ENXIO) 2725 rc = 0; 2726 else if (rc != 0) 2727 goto out; 2728 2729 if (sc->sk_type == SK_GENESIS) { 2730 /* Configure MAC FIFOs */ 2731 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2732 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2733 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2734 2735 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2736 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2737 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2738 } 2739 2740 /* Configure transmit arbiter(s) */ 2741 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2742 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2743 2744 /* Configure RAMbuffers */ 2745 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2746 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2747 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2748 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2749 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2750 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2751 2752 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2753 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2754 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2755 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2756 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2757 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2758 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2759 2760 /* Configure BMUs */ 2761 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2762 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2763 SK_RX_RING_ADDR(sc_if, 0)); 2764 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2765 2766 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2767 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2768 SK_TX_RING_ADDR(sc_if, 0)); 2769 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2770 2771 /* Init descriptors */ 2772 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2773 aprint_error_dev(&sc_if->sk_dev, "initialization failed: no " 2774 "memory for rx buffers\n"); 2775 sk_stop(ifp,0); 2776 splx(s); 2777 return ENOBUFS; 2778 } 2779 2780 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2781 aprint_error_dev(&sc_if->sk_dev, "initialization failed: no " 2782 "memory for tx buffers\n"); 2783 sk_stop(ifp,0); 2784 splx(s); 2785 return ENOBUFS; 2786 } 2787 2788 /* Set interrupt moderation if changed via sysctl. */ 2789 switch (sc->sk_type) { 2790 case SK_GENESIS: 2791 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2792 break; 2793 case SK_YUKON_EC: 2794 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2795 break; 2796 default: 2797 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2798 } 2799 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2800 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2801 sk_win_write_4(sc, SK_IMTIMERINIT, 2802 SK_IM_USECS(sc->sk_int_mod)); 2803 aprint_verbose_dev(&sc->sk_dev, "interrupt moderation is %d us\n", 2804 sc->sk_int_mod); 2805 } 2806 2807 /* Configure interrupt handling */ 2808 CSR_READ_4(sc, SK_ISSR); 2809 if (sc_if->sk_port == SK_PORT_A) 2810 sc->sk_intrmask |= SK_INTRS1; 2811 else 2812 sc->sk_intrmask |= SK_INTRS2; 2813 2814 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2815 2816 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2817 2818 /* Start BMUs. */ 2819 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2820 2821 if (sc->sk_type == SK_GENESIS) { 2822 /* Enable XMACs TX and RX state machines */ 2823 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2824 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2825 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2826 } 2827 2828 if (SK_YUKON_FAMILY(sc->sk_type)) { 2829 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2830 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2831 #if 0 2832 /* XXX disable 100Mbps and full duplex mode? */ 2833 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2834 #endif 2835 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2836 } 2837 2838 2839 ifp->if_flags |= IFF_RUNNING; 2840 ifp->if_flags &= ~IFF_OACTIVE; 2841 2842 out: 2843 splx(s); 2844 return rc; 2845 } 2846 2847 void 2848 sk_stop(struct ifnet *ifp, int disable) 2849 { 2850 struct sk_if_softc *sc_if = ifp->if_softc; 2851 struct sk_softc *sc = sc_if->sk_softc; 2852 int i; 2853 2854 DPRINTFN(1, ("sk_stop\n")); 2855 2856 callout_stop(&sc_if->sk_tick_ch); 2857 2858 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2859 u_int32_t val; 2860 2861 /* Put PHY back into reset. */ 2862 val = sk_win_read_4(sc, SK_GPIO); 2863 if (sc_if->sk_port == SK_PORT_A) { 2864 val |= SK_GPIO_DIR0; 2865 val &= ~SK_GPIO_DAT0; 2866 } else { 2867 val |= SK_GPIO_DIR2; 2868 val &= ~SK_GPIO_DAT2; 2869 } 2870 sk_win_write_4(sc, SK_GPIO, val); 2871 } 2872 2873 /* Turn off various components of this interface. */ 2874 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2875 switch (sc->sk_type) { 2876 case SK_GENESIS: 2877 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2878 SK_TXMACCTL_XMAC_RESET); 2879 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2880 break; 2881 case SK_YUKON: 2882 case SK_YUKON_LITE: 2883 case SK_YUKON_LP: 2884 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2885 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2886 break; 2887 } 2888 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2889 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2890 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2891 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2892 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2893 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2894 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2895 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2896 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2897 2898 /* Disable interrupts */ 2899 if (sc_if->sk_port == SK_PORT_A) 2900 sc->sk_intrmask &= ~SK_INTRS1; 2901 else 2902 sc->sk_intrmask &= ~SK_INTRS2; 2903 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2904 2905 SK_XM_READ_2(sc_if, XM_ISR); 2906 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2907 2908 /* Free RX and TX mbufs still in the queues. */ 2909 for (i = 0; i < SK_RX_RING_CNT; i++) { 2910 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2911 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2912 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2913 } 2914 } 2915 2916 for (i = 0; i < SK_TX_RING_CNT; i++) { 2917 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2918 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2919 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2920 } 2921 } 2922 2923 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2924 } 2925 2926 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2927 2928 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2929 2930 #ifdef SK_DEBUG 2931 void 2932 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2933 { 2934 #define DESC_PRINT(X) \ 2935 if (X) \ 2936 printf("txdesc[%d]." #X "=%#x\n", \ 2937 idx, X); 2938 2939 DESC_PRINT(le32toh(desc->sk_ctl)); 2940 DESC_PRINT(le32toh(desc->sk_next)); 2941 DESC_PRINT(le32toh(desc->sk_data_lo)); 2942 DESC_PRINT(le32toh(desc->sk_data_hi)); 2943 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2944 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2945 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2946 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2947 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2948 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2949 #undef PRINT 2950 } 2951 2952 void 2953 sk_dump_bytes(const char *data, int len) 2954 { 2955 int c, i, j; 2956 2957 for (i = 0; i < len; i += 16) { 2958 printf("%08x ", i); 2959 c = len - i; 2960 if (c > 16) c = 16; 2961 2962 for (j = 0; j < c; j++) { 2963 printf("%02x ", data[i + j] & 0xff); 2964 if ((j & 0xf) == 7 && j > 0) 2965 printf(" "); 2966 } 2967 2968 for (; j < 16; j++) 2969 printf(" "); 2970 printf(" "); 2971 2972 for (j = 0; j < c; j++) { 2973 int ch = data[i + j] & 0xff; 2974 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2975 } 2976 2977 printf("\n"); 2978 2979 if (c < 16) 2980 break; 2981 } 2982 } 2983 2984 void 2985 sk_dump_mbuf(struct mbuf *m) 2986 { 2987 int count = m->m_pkthdr.len; 2988 2989 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2990 2991 while (count > 0 && m) { 2992 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2993 m, m->m_data, m->m_len); 2994 sk_dump_bytes(mtod(m, char *), m->m_len); 2995 2996 count -= m->m_len; 2997 m = m->m_next; 2998 } 2999 } 3000 #endif 3001 3002 static int 3003 sk_sysctl_handler(SYSCTLFN_ARGS) 3004 { 3005 int error, t; 3006 struct sysctlnode node; 3007 struct sk_softc *sc; 3008 3009 node = *rnode; 3010 sc = node.sysctl_data; 3011 t = sc->sk_int_mod; 3012 node.sysctl_data = &t; 3013 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3014 if (error || newp == NULL) 3015 return error; 3016 3017 if (t < SK_IM_MIN || t > SK_IM_MAX) 3018 return EINVAL; 3019 3020 /* update the softc with sysctl-changed value, and mark 3021 for hardware update */ 3022 sc->sk_int_mod = t; 3023 sc->sk_int_mod_pending = 1; 3024 return 0; 3025 } 3026 3027 /* 3028 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3029 * set up in skc_attach() 3030 */ 3031 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3032 { 3033 int rc; 3034 const struct sysctlnode *node; 3035 3036 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3037 0, CTLTYPE_NODE, "hw", NULL, 3038 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3039 goto err; 3040 } 3041 3042 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3043 0, CTLTYPE_NODE, "sk", 3044 SYSCTL_DESCR("sk interface controls"), 3045 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3046 goto err; 3047 } 3048 3049 sk_root_num = node->sysctl_num; 3050 return; 3051 3052 err: 3053 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3054 } 3055
Indexes created Tue Sep 23 07:09:52 GMT 2025