if_sk.c revision 1.48.4.2
1 /* $NetBSD: if_sk.c,v 1.48.4.2 2009/05/04 08:12:57 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.48.4.2 2009/05/04 08:12:57 yamt Exp $"); 119 120 #include "bpfilter.h" 121 #include "rnd.h" 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/sockio.h> 126 #include <sys/mbuf.h> 127 #include <sys/malloc.h> 128 #include <sys/mutex.h> 129 #include <sys/kernel.h> 130 #include <sys/socket.h> 131 #include <sys/device.h> 132 #include <sys/queue.h> 133 #include <sys/callout.h> 134 #include <sys/sysctl.h> 135 #include <sys/endian.h> 136 137 #include <net/if.h> 138 #include <net/if_dl.h> 139 #include <net/if_types.h> 140 141 #include <net/if_media.h> 142 143 #if NBPFILTER > 0 144 #include <net/bpf.h> 145 #endif 146 #if NRND > 0 147 #include <sys/rnd.h> 148 #endif 149 150 #include <dev/mii/mii.h> 151 #include <dev/mii/miivar.h> 152 #include <dev/mii/brgphyreg.h> 153 154 #include <dev/pci/pcireg.h> 155 #include <dev/pci/pcivar.h> 156 #include <dev/pci/pcidevs.h> 157 158 /* #define SK_USEIOSPACE */ 159 160 #include <dev/pci/if_skreg.h> 161 #include <dev/pci/if_skvar.h> 162 163 int skc_probe(device_t, cfdata_t, void *); 164 void skc_attach(device_t, device_t, void *aux); 165 int sk_probe(device_t, cfdata_t, void *); 166 void sk_attach(device_t, device_t, void *aux); 167 int skcprint(void *, const char *); 168 int sk_intr(void *); 169 void sk_intr_bcom(struct sk_if_softc *); 170 void sk_intr_xmac(struct sk_if_softc *); 171 void sk_intr_yukon(struct sk_if_softc *); 172 void sk_rxeof(struct sk_if_softc *); 173 void sk_txeof(struct sk_if_softc *); 174 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 175 void sk_start(struct ifnet *); 176 int sk_ioctl(struct ifnet *, u_long, void *); 177 int sk_init(struct ifnet *); 178 void sk_init_xmac(struct sk_if_softc *); 179 void sk_init_yukon(struct sk_if_softc *); 180 void sk_stop(struct ifnet *, int); 181 void sk_watchdog(struct ifnet *); 182 void sk_shutdown(void *); 183 int sk_ifmedia_upd(struct ifnet *); 184 void sk_reset(struct sk_softc *); 185 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 186 int sk_alloc_jumbo_mem(struct sk_if_softc *); 187 void sk_free_jumbo_mem(struct sk_if_softc *); 188 void *sk_jalloc(struct sk_if_softc *); 189 void sk_jfree(struct mbuf *, void *, size_t, void *); 190 int sk_init_rx_ring(struct sk_if_softc *); 191 int sk_init_tx_ring(struct sk_if_softc *); 192 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 193 void sk_vpd_read_res(struct sk_softc *, 194 struct vpd_res *, int); 195 void sk_vpd_read(struct sk_softc *); 196 197 void sk_update_int_mod(struct sk_softc *); 198 199 int sk_xmac_miibus_readreg(device_t, int, int); 200 void sk_xmac_miibus_writereg(device_t, int, int, int); 201 void sk_xmac_miibus_statchg(device_t); 202 203 int sk_marv_miibus_readreg(device_t, int, int); 204 void sk_marv_miibus_writereg(device_t, int, int, int); 205 void sk_marv_miibus_statchg(device_t); 206 207 u_int32_t sk_xmac_hash(void *); 208 u_int32_t sk_yukon_hash(void *); 209 void sk_setfilt(struct sk_if_softc *, void *, int); 210 void sk_setmulti(struct sk_if_softc *); 211 void sk_tick(void *); 212 213 static bool skc_suspend(device_t dv PMF_FN_ARGS); 214 static bool skc_resume(device_t dv PMF_FN_ARGS); 215 static bool sk_resume(device_t dv PMF_FN_ARGS); 216 217 /* #define SK_DEBUG 2 */ 218 #ifdef SK_DEBUG 219 #define DPRINTF(x) if (skdebug) printf x 220 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 221 int skdebug = SK_DEBUG; 222 223 void sk_dump_txdesc(struct sk_tx_desc *, int); 224 void sk_dump_mbuf(struct mbuf *); 225 void sk_dump_bytes(const char *, int); 226 #else 227 #define DPRINTF(x) 228 #define DPRINTFN(n,x) 229 #endif 230 231 static int sk_sysctl_handler(SYSCTLFN_PROTO); 232 static int sk_root_num; 233 234 /* supported device vendors */ 235 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 236 static const struct sk_product { 237 pci_vendor_id_t sk_vendor; 238 pci_product_id_t sk_product; 239 } sk_products[] = { 240 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 241 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 242 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 243 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 244 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 245 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 246 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 247 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 248 { 0, 0, } 249 }; 250 251 #define SK_LINKSYS_EG1032_SUBID 0x00151737 252 253 static inline u_int32_t 254 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 255 { 256 #ifdef SK_USEIOSPACE 257 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 258 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 259 #else 260 return CSR_READ_4(sc, reg); 261 #endif 262 } 263 264 static inline u_int16_t 265 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 266 { 267 #ifdef SK_USEIOSPACE 268 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 269 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 270 #else 271 return CSR_READ_2(sc, reg); 272 #endif 273 } 274 275 static inline u_int8_t 276 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 277 { 278 #ifdef SK_USEIOSPACE 279 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 280 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 281 #else 282 return CSR_READ_1(sc, reg); 283 #endif 284 } 285 286 static inline void 287 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 288 { 289 #ifdef SK_USEIOSPACE 290 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 291 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 292 #else 293 CSR_WRITE_4(sc, reg, x); 294 #endif 295 } 296 297 static inline void 298 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 299 { 300 #ifdef SK_USEIOSPACE 301 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 302 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 303 #else 304 CSR_WRITE_2(sc, reg, x); 305 #endif 306 } 307 308 static inline void 309 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 310 { 311 #ifdef SK_USEIOSPACE 312 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 313 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 314 #else 315 CSR_WRITE_1(sc, reg, x); 316 #endif 317 } 318 319 /* 320 * The VPD EEPROM contains Vital Product Data, as suggested in 321 * the PCI 2.1 specification. The VPD data is separared into areas 322 * denoted by resource IDs. The SysKonnect VPD contains an ID string 323 * resource (the name of the adapter), a read-only area resource 324 * containing various key/data fields and a read/write area which 325 * can be used to store asset management information or log messages. 326 * We read the ID string and read-only into buffers attached to 327 * the controller softc structure for later use. At the moment, 328 * we only use the ID string during sk_attach(). 329 */ 330 u_int8_t 331 sk_vpd_readbyte(struct sk_softc *sc, int addr) 332 { 333 int i; 334 335 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 336 for (i = 0; i < SK_TIMEOUT; i++) { 337 DELAY(1); 338 if (sk_win_read_2(sc, 339 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 340 break; 341 } 342 343 if (i == SK_TIMEOUT) 344 return 0; 345 346 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 347 } 348 349 void 350 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 351 { 352 int i; 353 u_int8_t *ptr; 354 355 ptr = (u_int8_t *)res; 356 for (i = 0; i < sizeof(struct vpd_res); i++) 357 ptr[i] = sk_vpd_readbyte(sc, i + addr); 358 } 359 360 void 361 sk_vpd_read(struct sk_softc *sc) 362 { 363 int pos = 0, i; 364 struct vpd_res res; 365 366 if (sc->sk_vpd_prodname != NULL) 367 free(sc->sk_vpd_prodname, M_DEVBUF); 368 if (sc->sk_vpd_readonly != NULL) 369 free(sc->sk_vpd_readonly, M_DEVBUF); 370 sc->sk_vpd_prodname = NULL; 371 sc->sk_vpd_readonly = NULL; 372 373 sk_vpd_read_res(sc, &res, pos); 374 375 if (res.vr_id != VPD_RES_ID) { 376 aprint_error_dev(sc->sk_dev, 377 "bad VPD resource id: expected %x got %x\n", 378 VPD_RES_ID, res.vr_id); 379 return; 380 } 381 382 pos += sizeof(res); 383 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 384 if (sc->sk_vpd_prodname == NULL) 385 panic("sk_vpd_read"); 386 for (i = 0; i < res.vr_len; i++) 387 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 388 sc->sk_vpd_prodname[i] = '\0'; 389 pos += i; 390 391 sk_vpd_read_res(sc, &res, pos); 392 393 if (res.vr_id != VPD_RES_READ) { 394 aprint_error_dev(sc->sk_dev, 395 "bad VPD resource id: expected %x got %x\n", 396 VPD_RES_READ, res.vr_id); 397 return; 398 } 399 400 pos += sizeof(res); 401 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 402 if (sc->sk_vpd_readonly == NULL) 403 panic("sk_vpd_read"); 404 for (i = 0; i < res.vr_len ; i++) 405 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 406 } 407 408 int 409 sk_xmac_miibus_readreg(device_t dev, int phy, int reg) 410 { 411 struct sk_if_softc *sc_if = device_private(dev); 412 int i; 413 414 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 415 416 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 417 return 0; 418 419 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 420 SK_XM_READ_2(sc_if, XM_PHY_DATA); 421 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 422 for (i = 0; i < SK_TIMEOUT; i++) { 423 DELAY(1); 424 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 425 XM_MMUCMD_PHYDATARDY) 426 break; 427 } 428 429 if (i == SK_TIMEOUT) { 430 aprint_error_dev(sc_if->sk_dev, 431 "phy failed to come ready\n"); 432 return 0; 433 } 434 } 435 DELAY(1); 436 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 437 } 438 439 void 440 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, int val) 441 { 442 struct sk_if_softc *sc_if = device_private(dev); 443 int i; 444 445 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 446 447 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 448 for (i = 0; i < SK_TIMEOUT; i++) { 449 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 450 break; 451 } 452 453 if (i == SK_TIMEOUT) { 454 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 455 return; 456 } 457 458 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 459 for (i = 0; i < SK_TIMEOUT; i++) { 460 DELAY(1); 461 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 462 break; 463 } 464 465 if (i == SK_TIMEOUT) 466 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 467 } 468 469 void 470 sk_xmac_miibus_statchg(device_t dev) 471 { 472 struct sk_if_softc *sc_if = device_private(dev); 473 struct mii_data *mii = &sc_if->sk_mii; 474 475 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 476 477 /* 478 * If this is a GMII PHY, manually set the XMAC's 479 * duplex mode accordingly. 480 */ 481 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 482 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 483 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 484 else 485 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 486 } 487 } 488 489 int 490 sk_marv_miibus_readreg(device_t dev, int phy, int reg) 491 { 492 struct sk_if_softc *sc_if = device_private(dev); 493 u_int16_t val; 494 int i; 495 496 if (phy != 0 || 497 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 498 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 499 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 500 phy, reg)); 501 return 0; 502 } 503 504 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 505 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 506 507 for (i = 0; i < SK_TIMEOUT; i++) { 508 DELAY(1); 509 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 510 if (val & YU_SMICR_READ_VALID) 511 break; 512 } 513 514 if (i == SK_TIMEOUT) { 515 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 516 return 0; 517 } 518 519 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 520 SK_TIMEOUT)); 521 522 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 523 524 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 525 phy, reg, val)); 526 527 return val; 528 } 529 530 void 531 sk_marv_miibus_writereg(device_t dev, int phy, int reg, int val) 532 { 533 struct sk_if_softc *sc_if = device_private(dev); 534 int i; 535 536 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 537 phy, reg, val)); 538 539 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 540 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 541 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 542 543 for (i = 0; i < SK_TIMEOUT; i++) { 544 DELAY(1); 545 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 546 break; 547 } 548 549 if (i == SK_TIMEOUT) 550 printf("%s: phy write timed out\n", 551 device_xname(sc_if->sk_dev)); 552 } 553 554 void 555 sk_marv_miibus_statchg(device_t dev) 556 { 557 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 558 SK_YU_READ_2(((struct sk_if_softc *)device_private(dev)), 559 YUKON_GPCR))); 560 } 561 562 #define SK_HASH_BITS 6 563 564 u_int32_t 565 sk_xmac_hash(void *addr) 566 { 567 u_int32_t crc; 568 569 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 570 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 571 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 572 return crc; 573 } 574 575 u_int32_t 576 sk_yukon_hash(void *addr) 577 { 578 u_int32_t crc; 579 580 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 581 crc &= ((1 << SK_HASH_BITS) - 1); 582 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 583 return crc; 584 } 585 586 void 587 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 588 { 589 char *addr = addrv; 590 int base = XM_RXFILT_ENTRY(slot); 591 592 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 593 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 594 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 595 } 596 597 void 598 sk_setmulti(struct sk_if_softc *sc_if) 599 { 600 struct sk_softc *sc = sc_if->sk_softc; 601 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 602 u_int32_t hashes[2] = { 0, 0 }; 603 int h = 0, i; 604 struct ethercom *ec = &sc_if->sk_ethercom; 605 struct ether_multi *enm; 606 struct ether_multistep step; 607 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 608 609 /* First, zot all the existing filters. */ 610 switch (sc->sk_type) { 611 case SK_GENESIS: 612 for (i = 1; i < XM_RXFILT_MAX; i++) 613 sk_setfilt(sc_if, (void *)&dummy, i); 614 615 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 616 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 617 break; 618 case SK_YUKON: 619 case SK_YUKON_LITE: 620 case SK_YUKON_LP: 621 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 622 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 623 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 624 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 625 break; 626 } 627 628 /* Now program new ones. */ 629 allmulti: 630 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 631 hashes[0] = 0xFFFFFFFF; 632 hashes[1] = 0xFFFFFFFF; 633 } else { 634 i = 1; 635 /* First find the tail of the list. */ 636 ETHER_FIRST_MULTI(step, ec, enm); 637 while (enm != NULL) { 638 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 639 ETHER_ADDR_LEN)) { 640 ifp->if_flags |= IFF_ALLMULTI; 641 goto allmulti; 642 } 643 DPRINTFN(2,("multicast address %s\n", 644 ether_sprintf(enm->enm_addrlo))); 645 /* 646 * Program the first XM_RXFILT_MAX multicast groups 647 * into the perfect filter. For all others, 648 * use the hash table. 649 */ 650 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 651 sk_setfilt(sc_if, enm->enm_addrlo, i); 652 i++; 653 } 654 else { 655 switch (sc->sk_type) { 656 case SK_GENESIS: 657 h = sk_xmac_hash(enm->enm_addrlo); 658 break; 659 case SK_YUKON: 660 case SK_YUKON_LITE: 661 case SK_YUKON_LP: 662 h = sk_yukon_hash(enm->enm_addrlo); 663 break; 664 } 665 if (h < 32) 666 hashes[0] |= (1 << h); 667 else 668 hashes[1] |= (1 << (h - 32)); 669 } 670 671 ETHER_NEXT_MULTI(step, enm); 672 } 673 } 674 675 switch (sc->sk_type) { 676 case SK_GENESIS: 677 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 678 XM_MODE_RX_USE_PERFECT); 679 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 680 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 681 break; 682 case SK_YUKON: 683 case SK_YUKON_LITE: 684 case SK_YUKON_LP: 685 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 686 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 687 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 688 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 689 break; 690 } 691 } 692 693 int 694 sk_init_rx_ring(struct sk_if_softc *sc_if) 695 { 696 struct sk_chain_data *cd = &sc_if->sk_cdata; 697 struct sk_ring_data *rd = sc_if->sk_rdata; 698 int i; 699 700 memset((char *)rd->sk_rx_ring, 0, 701 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 702 703 for (i = 0; i < SK_RX_RING_CNT; i++) { 704 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 705 if (i == (SK_RX_RING_CNT - 1)) { 706 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 707 rd->sk_rx_ring[i].sk_next = 708 htole32(SK_RX_RING_ADDR(sc_if, 0)); 709 } else { 710 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 711 rd->sk_rx_ring[i].sk_next = 712 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 713 } 714 } 715 716 for (i = 0; i < SK_RX_RING_CNT; i++) { 717 if (sk_newbuf(sc_if, i, NULL, 718 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 719 aprint_error_dev(sc_if->sk_dev, 720 "failed alloc of %dth mbuf\n", i); 721 return ENOBUFS; 722 } 723 } 724 sc_if->sk_cdata.sk_rx_prod = 0; 725 sc_if->sk_cdata.sk_rx_cons = 0; 726 727 return 0; 728 } 729 730 int 731 sk_init_tx_ring(struct sk_if_softc *sc_if) 732 { 733 struct sk_chain_data *cd = &sc_if->sk_cdata; 734 struct sk_ring_data *rd = sc_if->sk_rdata; 735 int i; 736 737 memset(sc_if->sk_rdata->sk_tx_ring, 0, 738 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 739 740 for (i = 0; i < SK_TX_RING_CNT; i++) { 741 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 742 if (i == (SK_TX_RING_CNT - 1)) { 743 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 744 rd->sk_tx_ring[i].sk_next = 745 htole32(SK_TX_RING_ADDR(sc_if, 0)); 746 } else { 747 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 748 rd->sk_tx_ring[i].sk_next = 749 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 750 } 751 } 752 753 sc_if->sk_cdata.sk_tx_prod = 0; 754 sc_if->sk_cdata.sk_tx_cons = 0; 755 sc_if->sk_cdata.sk_tx_cnt = 0; 756 757 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 758 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 759 760 return 0; 761 } 762 763 int 764 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 765 bus_dmamap_t dmamap) 766 { 767 struct mbuf *m_new = NULL; 768 struct sk_chain *c; 769 struct sk_rx_desc *r; 770 771 if (m == NULL) { 772 void *buf = NULL; 773 774 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 775 if (m_new == NULL) { 776 aprint_error_dev(sc_if->sk_dev, 777 "no memory for rx list -- packet dropped!\n"); 778 return ENOBUFS; 779 } 780 781 /* Allocate the jumbo buffer */ 782 buf = sk_jalloc(sc_if); 783 if (buf == NULL) { 784 m_freem(m_new); 785 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 786 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 787 return ENOBUFS; 788 } 789 790 /* Attach the buffer to the mbuf */ 791 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 792 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 793 794 } else { 795 /* 796 * We're re-using a previously allocated mbuf; 797 * be sure to re-init pointers and lengths to 798 * default values. 799 */ 800 m_new = m; 801 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 802 m_new->m_data = m_new->m_ext.ext_buf; 803 } 804 m_adj(m_new, ETHER_ALIGN); 805 806 c = &sc_if->sk_cdata.sk_rx_chain[i]; 807 r = c->sk_desc; 808 c->sk_mbuf = m_new; 809 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 810 (((vaddr_t)m_new->m_data 811 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 812 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 813 814 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 815 816 return 0; 817 } 818 819 /* 820 * Memory management for jumbo frames. 821 */ 822 823 int 824 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 825 { 826 struct sk_softc *sc = sc_if->sk_softc; 827 char *ptr, *kva; 828 bus_dma_segment_t seg; 829 int i, rseg, state, error; 830 struct sk_jpool_entry *entry; 831 832 state = error = 0; 833 834 /* Grab a big chunk o' storage. */ 835 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 836 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 837 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 838 return ENOBUFS; 839 } 840 841 state = 1; 842 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 843 BUS_DMA_NOWAIT)) { 844 aprint_error_dev(sc->sk_dev, 845 "can't map dma buffers (%d bytes)\n", 846 SK_JMEM); 847 error = ENOBUFS; 848 goto out; 849 } 850 851 state = 2; 852 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 853 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 854 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 855 error = ENOBUFS; 856 goto out; 857 } 858 859 state = 3; 860 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 861 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 862 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 863 error = ENOBUFS; 864 goto out; 865 } 866 867 state = 4; 868 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 869 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 870 871 LIST_INIT(&sc_if->sk_jfree_listhead); 872 LIST_INIT(&sc_if->sk_jinuse_listhead); 873 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 874 875 /* 876 * Now divide it up into 9K pieces and save the addresses 877 * in an array. 878 */ 879 ptr = sc_if->sk_cdata.sk_jumbo_buf; 880 for (i = 0; i < SK_JSLOTS; i++) { 881 sc_if->sk_cdata.sk_jslots[i] = ptr; 882 ptr += SK_JLEN; 883 entry = malloc(sizeof(struct sk_jpool_entry), 884 M_DEVBUF, M_NOWAIT); 885 if (entry == NULL) { 886 aprint_error_dev(sc->sk_dev, 887 "no memory for jumbo buffer queue!\n"); 888 error = ENOBUFS; 889 goto out; 890 } 891 entry->slot = i; 892 if (i) 893 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 894 entry, jpool_entries); 895 else 896 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 897 entry, jpool_entries); 898 } 899 out: 900 if (error != 0) { 901 switch (state) { 902 case 4: 903 bus_dmamap_unload(sc->sc_dmatag, 904 sc_if->sk_cdata.sk_rx_jumbo_map); 905 case 3: 906 bus_dmamap_destroy(sc->sc_dmatag, 907 sc_if->sk_cdata.sk_rx_jumbo_map); 908 case 2: 909 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 910 case 1: 911 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 912 break; 913 default: 914 break; 915 } 916 } 917 918 return error; 919 } 920 921 /* 922 * Allocate a jumbo buffer. 923 */ 924 void * 925 sk_jalloc(struct sk_if_softc *sc_if) 926 { 927 struct sk_jpool_entry *entry; 928 929 mutex_enter(&sc_if->sk_jpool_mtx); 930 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 931 932 if (entry == NULL) { 933 mutex_exit(&sc_if->sk_jpool_mtx); 934 return NULL; 935 } 936 937 LIST_REMOVE(entry, jpool_entries); 938 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 939 mutex_exit(&sc_if->sk_jpool_mtx); 940 return sc_if->sk_cdata.sk_jslots[entry->slot]; 941 } 942 943 /* 944 * Release a jumbo buffer. 945 */ 946 void 947 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 948 { 949 struct sk_jpool_entry *entry; 950 struct sk_if_softc *sc; 951 int i; 952 953 /* Extract the softc struct pointer. */ 954 sc = (struct sk_if_softc *)arg; 955 956 if (sc == NULL) 957 panic("sk_jfree: can't find softc pointer!"); 958 959 /* calculate the slot this buffer belongs to */ 960 961 i = ((vaddr_t)buf 962 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 963 964 if ((i < 0) || (i >= SK_JSLOTS)) 965 panic("sk_jfree: asked to free buffer that we don't manage!"); 966 967 mutex_enter(&sc->sk_jpool_mtx); 968 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 969 if (entry == NULL) 970 panic("sk_jfree: buffer not in use!"); 971 entry->slot = i; 972 LIST_REMOVE(entry, jpool_entries); 973 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 974 mutex_exit(&sc->sk_jpool_mtx); 975 976 if (__predict_true(m != NULL)) 977 pool_cache_put(mb_cache, m); 978 } 979 980 /* 981 * Set media options. 982 */ 983 int 984 sk_ifmedia_upd(struct ifnet *ifp) 985 { 986 struct sk_if_softc *sc_if = ifp->if_softc; 987 int rc; 988 989 (void) sk_init(ifp); 990 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 991 return 0; 992 return rc; 993 } 994 995 int 996 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 997 { 998 struct sk_if_softc *sc_if = ifp->if_softc; 999 struct sk_softc *sc = sc_if->sk_softc; 1000 int s, error = 0; 1001 1002 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1003 1004 s = splnet(); 1005 1006 switch (command) { 1007 1008 case SIOCSIFFLAGS: 1009 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1010 if ((error = ifioctl_common(ifp, command, data)) != 0) 1011 break; 1012 if (ifp->if_flags & IFF_UP) { 1013 if (ifp->if_flags & IFF_RUNNING && 1014 ifp->if_flags & IFF_PROMISC && 1015 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1016 switch (sc->sk_type) { 1017 case SK_GENESIS: 1018 SK_XM_SETBIT_4(sc_if, XM_MODE, 1019 XM_MODE_RX_PROMISC); 1020 break; 1021 case SK_YUKON: 1022 case SK_YUKON_LITE: 1023 case SK_YUKON_LP: 1024 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1025 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1026 break; 1027 } 1028 sk_setmulti(sc_if); 1029 } else if (ifp->if_flags & IFF_RUNNING && 1030 !(ifp->if_flags & IFF_PROMISC) && 1031 sc_if->sk_if_flags & IFF_PROMISC) { 1032 switch (sc->sk_type) { 1033 case SK_GENESIS: 1034 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1035 XM_MODE_RX_PROMISC); 1036 break; 1037 case SK_YUKON: 1038 case SK_YUKON_LITE: 1039 case SK_YUKON_LP: 1040 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1041 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1042 break; 1043 } 1044 1045 sk_setmulti(sc_if); 1046 } else 1047 (void) sk_init(ifp); 1048 } else { 1049 if (ifp->if_flags & IFF_RUNNING) 1050 sk_stop(ifp,0); 1051 } 1052 sc_if->sk_if_flags = ifp->if_flags; 1053 error = 0; 1054 break; 1055 1056 default: 1057 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1058 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1059 break; 1060 1061 error = 0; 1062 1063 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1064 ; 1065 else if (ifp->if_flags & IFF_RUNNING) { 1066 sk_setmulti(sc_if); 1067 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1068 } 1069 break; 1070 } 1071 1072 splx(s); 1073 return error; 1074 } 1075 1076 void 1077 sk_update_int_mod(struct sk_softc *sc) 1078 { 1079 u_int32_t imtimer_ticks; 1080 1081 /* 1082 * Configure interrupt moderation. The moderation timer 1083 * defers interrupts specified in the interrupt moderation 1084 * timer mask based on the timeout specified in the interrupt 1085 * moderation timer init register. Each bit in the timer 1086 * register represents one tick, so to specify a timeout in 1087 * microseconds, we have to multiply by the correct number of 1088 * ticks-per-microsecond. 1089 */ 1090 switch (sc->sk_type) { 1091 case SK_GENESIS: 1092 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1093 break; 1094 case SK_YUKON_EC: 1095 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1096 break; 1097 default: 1098 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1099 } 1100 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1101 sc->sk_int_mod); 1102 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1103 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1104 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1105 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1106 sc->sk_int_mod_pending = 0; 1107 } 1108 1109 /* 1110 * Lookup: Check the PCI vendor and device, and return a pointer to 1111 * The structure if the IDs match against our list. 1112 */ 1113 1114 static const struct sk_product * 1115 sk_lookup(const struct pci_attach_args *pa) 1116 { 1117 const struct sk_product *psk; 1118 1119 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1120 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1121 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1122 return psk; 1123 } 1124 return NULL; 1125 } 1126 1127 /* 1128 * Probe for a SysKonnect GEnesis chip. 1129 */ 1130 1131 int 1132 skc_probe(device_t parent, cfdata_t match, void *aux) 1133 { 1134 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1135 const struct sk_product *psk; 1136 pcireg_t subid; 1137 1138 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1139 1140 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1141 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1142 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1143 subid == SK_LINKSYS_EG1032_SUBID) 1144 return 1; 1145 1146 if ((psk = sk_lookup(pa))) { 1147 return 1; 1148 } 1149 return 0; 1150 } 1151 1152 /* 1153 * Force the GEnesis into reset, then bring it out of reset. 1154 */ 1155 void sk_reset(struct sk_softc *sc) 1156 { 1157 DPRINTFN(2, ("sk_reset\n")); 1158 1159 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1160 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1161 if (SK_YUKON_FAMILY(sc->sk_type)) 1162 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1163 1164 DELAY(1000); 1165 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1166 DELAY(2); 1167 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1168 if (SK_YUKON_FAMILY(sc->sk_type)) 1169 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1170 1171 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1172 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1173 CSR_READ_2(sc, SK_LINK_CTRL))); 1174 1175 if (sc->sk_type == SK_GENESIS) { 1176 /* Configure packet arbiter */ 1177 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1178 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1179 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1180 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1181 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1182 } 1183 1184 /* Enable RAM interface */ 1185 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1186 1187 sk_update_int_mod(sc); 1188 } 1189 1190 int 1191 sk_probe(device_t parent, cfdata_t match, void *aux) 1192 { 1193 struct skc_attach_args *sa = aux; 1194 1195 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1196 return 0; 1197 1198 return 1; 1199 } 1200 1201 /* 1202 * Each XMAC chip is attached as a separate logical IP interface. 1203 * Single port cards will have only one logical interface of course. 1204 */ 1205 void 1206 sk_attach(device_t parent, device_t self, void *aux) 1207 { 1208 struct sk_if_softc *sc_if = device_private(self); 1209 struct sk_softc *sc = device_private(parent); 1210 struct skc_attach_args *sa = aux; 1211 struct sk_txmap_entry *entry; 1212 struct ifnet *ifp; 1213 bus_dma_segment_t seg; 1214 bus_dmamap_t dmamap; 1215 void *kva; 1216 int i, rseg; 1217 int mii_flags = 0; 1218 1219 aprint_naive("\n"); 1220 1221 sc_if->sk_dev = self; 1222 sc_if->sk_port = sa->skc_port; 1223 sc_if->sk_softc = sc; 1224 sc->sk_if[sa->skc_port] = sc_if; 1225 1226 if (sa->skc_port == SK_PORT_A) 1227 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1228 if (sa->skc_port == SK_PORT_B) 1229 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1230 1231 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1232 1233 /* 1234 * Get station address for this interface. Note that 1235 * dual port cards actually come with three station 1236 * addresses: one for each port, plus an extra. The 1237 * extra one is used by the SysKonnect driver software 1238 * as a 'virtual' station address for when both ports 1239 * are operating in failover mode. Currently we don't 1240 * use this extra address. 1241 */ 1242 for (i = 0; i < ETHER_ADDR_LEN; i++) 1243 sc_if->sk_enaddr[i] = 1244 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1245 1246 1247 aprint_normal(": Ethernet address %s\n", 1248 ether_sprintf(sc_if->sk_enaddr)); 1249 1250 /* 1251 * Set up RAM buffer addresses. The NIC will have a certain 1252 * amount of SRAM on it, somewhere between 512K and 2MB. We 1253 * need to divide this up a) between the transmitter and 1254 * receiver and b) between the two XMACs, if this is a 1255 * dual port NIC. Our algorithm is to divide up the memory 1256 * evenly so that everyone gets a fair share. 1257 */ 1258 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1259 u_int32_t chunk, val; 1260 1261 chunk = sc->sk_ramsize / 2; 1262 val = sc->sk_rboff / sizeof(u_int64_t); 1263 sc_if->sk_rx_ramstart = val; 1264 val += (chunk / sizeof(u_int64_t)); 1265 sc_if->sk_rx_ramend = val - 1; 1266 sc_if->sk_tx_ramstart = val; 1267 val += (chunk / sizeof(u_int64_t)); 1268 sc_if->sk_tx_ramend = val - 1; 1269 } else { 1270 u_int32_t chunk, val; 1271 1272 chunk = sc->sk_ramsize / 4; 1273 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1274 sizeof(u_int64_t); 1275 sc_if->sk_rx_ramstart = val; 1276 val += (chunk / sizeof(u_int64_t)); 1277 sc_if->sk_rx_ramend = val - 1; 1278 sc_if->sk_tx_ramstart = val; 1279 val += (chunk / sizeof(u_int64_t)); 1280 sc_if->sk_tx_ramend = val - 1; 1281 } 1282 1283 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1284 " tx_ramstart=%#x tx_ramend=%#x\n", 1285 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1286 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1287 1288 /* Read and save PHY type and set PHY address */ 1289 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1290 switch (sc_if->sk_phytype) { 1291 case SK_PHYTYPE_XMAC: 1292 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1293 break; 1294 case SK_PHYTYPE_BCOM: 1295 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1296 break; 1297 case SK_PHYTYPE_MARV_COPPER: 1298 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1299 break; 1300 default: 1301 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1302 sc_if->sk_phytype); 1303 return; 1304 } 1305 1306 /* Allocate the descriptor queues. */ 1307 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1308 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1309 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1310 goto fail; 1311 } 1312 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1313 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1314 aprint_error_dev(sc_if->sk_dev, 1315 "can't map dma buffers (%lu bytes)\n", 1316 (u_long) sizeof(struct sk_ring_data)); 1317 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1318 goto fail; 1319 } 1320 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1321 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1322 &sc_if->sk_ring_map)) { 1323 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1324 bus_dmamem_unmap(sc->sc_dmatag, kva, 1325 sizeof(struct sk_ring_data)); 1326 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1327 goto fail; 1328 } 1329 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1330 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1331 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1332 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1333 bus_dmamem_unmap(sc->sc_dmatag, kva, 1334 sizeof(struct sk_ring_data)); 1335 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1336 goto fail; 1337 } 1338 1339 for (i = 0; i < SK_RX_RING_CNT; i++) 1340 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1341 1342 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1343 for (i = 0; i < SK_TX_RING_CNT; i++) { 1344 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1345 1346 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1347 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1348 aprint_error_dev(sc_if->sk_dev, 1349 "Can't create TX dmamap\n"); 1350 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1351 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1352 bus_dmamem_unmap(sc->sc_dmatag, kva, 1353 sizeof(struct sk_ring_data)); 1354 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1355 goto fail; 1356 } 1357 1358 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1359 if (!entry) { 1360 aprint_error_dev(sc_if->sk_dev, 1361 "Can't alloc txmap entry\n"); 1362 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1363 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1364 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1365 bus_dmamem_unmap(sc->sc_dmatag, kva, 1366 sizeof(struct sk_ring_data)); 1367 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1368 goto fail; 1369 } 1370 entry->dmamap = dmamap; 1371 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1372 } 1373 1374 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1375 memset(sc_if->sk_rdata, 0, sizeof(struct sk_ring_data)); 1376 1377 ifp = &sc_if->sk_ethercom.ec_if; 1378 /* Try to allocate memory for jumbo buffers. */ 1379 if (sk_alloc_jumbo_mem(sc_if)) { 1380 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1381 goto fail; 1382 } 1383 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1384 | ETHERCAP_JUMBO_MTU; 1385 1386 ifp->if_softc = sc_if; 1387 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1388 ifp->if_ioctl = sk_ioctl; 1389 ifp->if_start = sk_start; 1390 ifp->if_stop = sk_stop; 1391 ifp->if_init = sk_init; 1392 ifp->if_watchdog = sk_watchdog; 1393 ifp->if_capabilities = 0; 1394 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1395 IFQ_SET_READY(&ifp->if_snd); 1396 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1397 1398 /* 1399 * Do miibus setup. 1400 */ 1401 switch (sc->sk_type) { 1402 case SK_GENESIS: 1403 sk_init_xmac(sc_if); 1404 break; 1405 case SK_YUKON: 1406 case SK_YUKON_LITE: 1407 case SK_YUKON_LP: 1408 sk_init_yukon(sc_if); 1409 break; 1410 default: 1411 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1412 sc->sk_type); 1413 goto fail; 1414 } 1415 1416 DPRINTFN(2, ("sk_attach: 1\n")); 1417 1418 sc_if->sk_mii.mii_ifp = ifp; 1419 switch (sc->sk_type) { 1420 case SK_GENESIS: 1421 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1422 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1423 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1424 break; 1425 case SK_YUKON: 1426 case SK_YUKON_LITE: 1427 case SK_YUKON_LP: 1428 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1429 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1430 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1431 mii_flags = MIIF_DOPAUSE; 1432 break; 1433 } 1434 1435 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1436 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1437 sk_ifmedia_upd, ether_mediastatus); 1438 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1439 MII_OFFSET_ANY, mii_flags); 1440 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1441 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1442 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1443 0, NULL); 1444 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1445 } else 1446 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1447 1448 callout_init(&sc_if->sk_tick_ch, 0); 1449 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1450 1451 DPRINTFN(2, ("sk_attach: 1\n")); 1452 1453 /* 1454 * Call MI attach routines. 1455 */ 1456 if_attach(ifp); 1457 1458 ether_ifattach(ifp, sc_if->sk_enaddr); 1459 1460 #if NRND > 0 1461 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1462 RND_TYPE_NET, 0); 1463 #endif 1464 1465 if (!pmf_device_register(self, NULL, sk_resume)) 1466 aprint_error_dev(self, "couldn't establish power handler\n"); 1467 else 1468 pmf_class_network_register(self, ifp); 1469 1470 DPRINTFN(2, ("sk_attach: end\n")); 1471 1472 return; 1473 1474 fail: 1475 sc->sk_if[sa->skc_port] = NULL; 1476 } 1477 1478 int 1479 skcprint(void *aux, const char *pnp) 1480 { 1481 struct skc_attach_args *sa = aux; 1482 1483 if (pnp) 1484 aprint_normal("sk port %c at %s", 1485 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1486 else 1487 aprint_normal(" port %c", 1488 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1489 return UNCONF; 1490 } 1491 1492 /* 1493 * Attach the interface. Allocate softc structures, do ifmedia 1494 * setup and ethernet/BPF attach. 1495 */ 1496 void 1497 skc_attach(device_t parent, device_t self, void *aux) 1498 { 1499 struct sk_softc *sc = device_private(self); 1500 struct pci_attach_args *pa = aux; 1501 struct skc_attach_args skca; 1502 pci_chipset_tag_t pc = pa->pa_pc; 1503 #ifndef SK_USEIOSPACE 1504 pcireg_t memtype; 1505 #endif 1506 pci_intr_handle_t ih; 1507 const char *intrstr = NULL; 1508 bus_addr_t iobase; 1509 bus_size_t iosize; 1510 int rc, sk_nodenum; 1511 u_int32_t command; 1512 const char *revstr; 1513 const struct sysctlnode *node; 1514 1515 sc->sk_dev = self; 1516 aprint_naive("\n"); 1517 1518 DPRINTFN(2, ("begin skc_attach\n")); 1519 1520 /* 1521 * Handle power management nonsense. 1522 */ 1523 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1524 1525 if (command == 0x01) { 1526 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1527 if (command & SK_PSTATE_MASK) { 1528 u_int32_t xiobase, membase, irq; 1529 1530 /* Save important PCI config data. */ 1531 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1532 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1533 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1534 1535 /* Reset the power state. */ 1536 aprint_normal_dev(sc->sk_dev, 1537 "chip is in D%d power mode -- setting to D0\n", 1538 command & SK_PSTATE_MASK); 1539 command &= 0xFFFFFFFC; 1540 pci_conf_write(pc, pa->pa_tag, 1541 SK_PCI_PWRMGMTCTRL, command); 1542 1543 /* Restore PCI config data. */ 1544 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1545 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1546 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1547 } 1548 } 1549 1550 /* 1551 * Map control/status registers. 1552 */ 1553 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1554 command |= PCI_COMMAND_IO_ENABLE | 1555 PCI_COMMAND_MEM_ENABLE | 1556 PCI_COMMAND_MASTER_ENABLE; 1557 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1558 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1559 1560 #ifdef SK_USEIOSPACE 1561 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1562 aprint_error(": failed to enable I/O ports!\n"); 1563 return; 1564 } 1565 /* 1566 * Map control/status registers. 1567 */ 1568 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1569 &sc->sk_btag, &sc->sk_bhandle, 1570 &iobase, &iosize)) { 1571 aprint_error(": can't find i/o space\n"); 1572 return; 1573 } 1574 #else 1575 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1576 aprint_error(": failed to enable memory mapping!\n"); 1577 return; 1578 } 1579 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1580 switch (memtype) { 1581 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1582 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1583 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1584 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1585 &iobase, &iosize) == 0) 1586 break; 1587 default: 1588 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1589 return; 1590 } 1591 1592 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, 1593 (u_long)iosize)); 1594 #endif 1595 sc->sc_dmatag = pa->pa_dmat; 1596 1597 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1598 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1599 1600 /* bail out here if chip is not recognized */ 1601 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1602 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1603 goto fail; 1604 } 1605 if (SK_IS_YUKON2(sc)) { 1606 aprint_error_dev(sc->sk_dev, 1607 "Does not support Yukon2--try msk(4).\n"); 1608 goto fail; 1609 } 1610 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1611 1612 /* Allocate interrupt */ 1613 if (pci_intr_map(pa, &ih)) { 1614 aprint_error(": couldn't map interrupt\n"); 1615 goto fail; 1616 } 1617 1618 intrstr = pci_intr_string(pc, ih); 1619 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1620 if (sc->sk_intrhand == NULL) { 1621 aprint_error(": couldn't establish interrupt"); 1622 if (intrstr != NULL) 1623 aprint_normal(" at %s", intrstr); 1624 goto fail; 1625 } 1626 aprint_normal(": %s\n", intrstr); 1627 1628 /* Reset the adapter. */ 1629 sk_reset(sc); 1630 1631 /* Read and save vital product data from EEPROM. */ 1632 sk_vpd_read(sc); 1633 1634 if (sc->sk_type == SK_GENESIS) { 1635 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1636 /* Read and save RAM size and RAMbuffer offset */ 1637 switch (val) { 1638 case SK_RAMSIZE_512K_64: 1639 sc->sk_ramsize = 0x80000; 1640 sc->sk_rboff = SK_RBOFF_0; 1641 break; 1642 case SK_RAMSIZE_1024K_64: 1643 sc->sk_ramsize = 0x100000; 1644 sc->sk_rboff = SK_RBOFF_80000; 1645 break; 1646 case SK_RAMSIZE_1024K_128: 1647 sc->sk_ramsize = 0x100000; 1648 sc->sk_rboff = SK_RBOFF_0; 1649 break; 1650 case SK_RAMSIZE_2048K_128: 1651 sc->sk_ramsize = 0x200000; 1652 sc->sk_rboff = SK_RBOFF_0; 1653 break; 1654 default: 1655 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1656 val); 1657 goto fail_1; 1658 break; 1659 } 1660 1661 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1662 sc->sk_ramsize, sc->sk_ramsize / 1024, 1663 sc->sk_rboff)); 1664 } else { 1665 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1666 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1667 sc->sk_rboff = SK_RBOFF_0; 1668 1669 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1670 sc->sk_ramsize / 1024, sc->sk_ramsize, 1671 sc->sk_rboff)); 1672 } 1673 1674 /* Read and save physical media type */ 1675 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1676 case SK_PMD_1000BASESX: 1677 sc->sk_pmd = IFM_1000_SX; 1678 break; 1679 case SK_PMD_1000BASELX: 1680 sc->sk_pmd = IFM_1000_LX; 1681 break; 1682 case SK_PMD_1000BASECX: 1683 sc->sk_pmd = IFM_1000_CX; 1684 break; 1685 case SK_PMD_1000BASETX: 1686 case SK_PMD_1000BASETX_ALT: 1687 sc->sk_pmd = IFM_1000_T; 1688 break; 1689 default: 1690 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1691 sk_win_read_1(sc, SK_PMDTYPE)); 1692 goto fail_1; 1693 } 1694 1695 /* determine whether to name it with vpd or just make it up */ 1696 /* Marvell Yukon VPD's can freqently be bogus */ 1697 1698 switch (pa->pa_id) { 1699 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1700 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1701 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1702 case PCI_PRODUCT_3COM_3C940: 1703 case PCI_PRODUCT_DLINK_DGE530T: 1704 case PCI_PRODUCT_DLINK_DGE560T: 1705 case PCI_PRODUCT_DLINK_DGE560T_2: 1706 case PCI_PRODUCT_LINKSYS_EG1032: 1707 case PCI_PRODUCT_LINKSYS_EG1064: 1708 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1709 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1710 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1711 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1712 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1713 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1714 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1715 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1716 sc->sk_name = sc->sk_vpd_prodname; 1717 break; 1718 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1719 /* whoops yukon vpd prodname bears no resemblance to reality */ 1720 switch (sc->sk_type) { 1721 case SK_GENESIS: 1722 sc->sk_name = sc->sk_vpd_prodname; 1723 break; 1724 case SK_YUKON: 1725 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1726 break; 1727 case SK_YUKON_LITE: 1728 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1729 break; 1730 case SK_YUKON_LP: 1731 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1732 break; 1733 default: 1734 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1735 } 1736 1737 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1738 1739 if ( sc->sk_type == SK_YUKON ) { 1740 uint32_t flashaddr; 1741 uint8_t testbyte; 1742 1743 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1744 1745 /* test Flash-Address Register */ 1746 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1747 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1748 1749 if (testbyte != 0) { 1750 /* this is yukon lite Rev. A0 */ 1751 sc->sk_type = SK_YUKON_LITE; 1752 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1753 /* restore Flash-Address Register */ 1754 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1755 } 1756 } 1757 break; 1758 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1759 sc->sk_name = sc->sk_vpd_prodname; 1760 break; 1761 default: 1762 sc->sk_name = "Unknown Marvell"; 1763 } 1764 1765 1766 if ( sc->sk_type == SK_YUKON_LITE ) { 1767 switch (sc->sk_rev) { 1768 case SK_YUKON_LITE_REV_A0: 1769 revstr = "A0"; 1770 break; 1771 case SK_YUKON_LITE_REV_A1: 1772 revstr = "A1"; 1773 break; 1774 case SK_YUKON_LITE_REV_A3: 1775 revstr = "A3"; 1776 break; 1777 default: 1778 revstr = ""; 1779 } 1780 } else { 1781 revstr = ""; 1782 } 1783 1784 /* Announce the product name. */ 1785 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1786 sc->sk_name, revstr, sc->sk_rev); 1787 1788 skca.skc_port = SK_PORT_A; 1789 (void)config_found(sc->sk_dev, &skca, skcprint); 1790 1791 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1792 skca.skc_port = SK_PORT_B; 1793 (void)config_found(sc->sk_dev, &skca, skcprint); 1794 } 1795 1796 /* Turn on the 'driver is loaded' LED. */ 1797 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1798 1799 /* skc sysctl setup */ 1800 1801 sc->sk_int_mod = SK_IM_DEFAULT; 1802 sc->sk_int_mod_pending = 0; 1803 1804 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1805 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1806 SYSCTL_DESCR("skc per-controller controls"), 1807 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1808 CTL_EOL)) != 0) { 1809 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1810 goto fail_1; 1811 } 1812 1813 sk_nodenum = node->sysctl_num; 1814 1815 /* interrupt moderation time in usecs */ 1816 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1817 CTLFLAG_READWRITE, 1818 CTLTYPE_INT, "int_mod", 1819 SYSCTL_DESCR("sk interrupt moderation timer"), 1820 sk_sysctl_handler, 0, sc, 1821 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1822 CTL_EOL)) != 0) { 1823 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1824 goto fail_1; 1825 } 1826 1827 if (!pmf_device_register(self, skc_suspend, skc_resume)) 1828 aprint_error_dev(self, "couldn't establish power handler\n"); 1829 1830 return; 1831 1832 fail_1: 1833 pci_intr_disestablish(pc, sc->sk_intrhand); 1834 fail: 1835 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1836 } 1837 1838 int 1839 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1840 { 1841 struct sk_softc *sc = sc_if->sk_softc; 1842 struct sk_tx_desc *f = NULL; 1843 u_int32_t frag, cur, cnt = 0, sk_ctl; 1844 int i; 1845 struct sk_txmap_entry *entry; 1846 bus_dmamap_t txmap; 1847 1848 DPRINTFN(3, ("sk_encap\n")); 1849 1850 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1851 if (entry == NULL) { 1852 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1853 return ENOBUFS; 1854 } 1855 txmap = entry->dmamap; 1856 1857 cur = frag = *txidx; 1858 1859 #ifdef SK_DEBUG 1860 if (skdebug >= 3) 1861 sk_dump_mbuf(m_head); 1862 #endif 1863 1864 /* 1865 * Start packing the mbufs in this chain into 1866 * the fragment pointers. Stop when we run out 1867 * of fragments or hit the end of the mbuf chain. 1868 */ 1869 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1870 BUS_DMA_NOWAIT)) { 1871 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1872 return ENOBUFS; 1873 } 1874 1875 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1876 1877 /* Sync the DMA map. */ 1878 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1879 BUS_DMASYNC_PREWRITE); 1880 1881 for (i = 0; i < txmap->dm_nsegs; i++) { 1882 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1883 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1884 return ENOBUFS; 1885 } 1886 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1887 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1888 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1889 if (cnt == 0) 1890 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1891 else 1892 sk_ctl |= SK_TXCTL_OWN; 1893 f->sk_ctl = htole32(sk_ctl); 1894 cur = frag; 1895 SK_INC(frag, SK_TX_RING_CNT); 1896 cnt++; 1897 } 1898 1899 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1900 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1901 1902 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1903 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1904 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1905 1906 /* Sync descriptors before handing to chip */ 1907 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1908 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1909 1910 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1911 htole32(SK_TXCTL_OWN); 1912 1913 /* Sync first descriptor to hand it off */ 1914 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1915 1916 sc_if->sk_cdata.sk_tx_cnt += cnt; 1917 1918 #ifdef SK_DEBUG 1919 if (skdebug >= 3) { 1920 struct sk_tx_desc *desc; 1921 u_int32_t idx; 1922 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1923 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1924 sk_dump_txdesc(desc, idx); 1925 } 1926 } 1927 #endif 1928 1929 *txidx = frag; 1930 1931 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1932 1933 return 0; 1934 } 1935 1936 void 1937 sk_start(struct ifnet *ifp) 1938 { 1939 struct sk_if_softc *sc_if = ifp->if_softc; 1940 struct sk_softc *sc = sc_if->sk_softc; 1941 struct mbuf *m_head = NULL; 1942 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1943 int pkts = 0; 1944 1945 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1946 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1947 1948 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1949 IFQ_POLL(&ifp->if_snd, m_head); 1950 if (m_head == NULL) 1951 break; 1952 1953 /* 1954 * Pack the data into the transmit ring. If we 1955 * don't have room, set the OACTIVE flag and wait 1956 * for the NIC to drain the ring. 1957 */ 1958 if (sk_encap(sc_if, m_head, &idx)) { 1959 ifp->if_flags |= IFF_OACTIVE; 1960 break; 1961 } 1962 1963 /* now we are committed to transmit the packet */ 1964 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1965 pkts++; 1966 1967 /* 1968 * If there's a BPF listener, bounce a copy of this frame 1969 * to him. 1970 */ 1971 #if NBPFILTER > 0 1972 if (ifp->if_bpf) 1973 bpf_mtap(ifp->if_bpf, m_head); 1974 #endif 1975 } 1976 if (pkts == 0) 1977 return; 1978 1979 /* Transmit */ 1980 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1981 sc_if->sk_cdata.sk_tx_prod = idx; 1982 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1983 1984 /* Set a timeout in case the chip goes out to lunch. */ 1985 ifp->if_timer = 5; 1986 } 1987 } 1988 1989 1990 void 1991 sk_watchdog(struct ifnet *ifp) 1992 { 1993 struct sk_if_softc *sc_if = ifp->if_softc; 1994 1995 /* 1996 * Reclaim first as there is a possibility of losing Tx completion 1997 * interrupts. 1998 */ 1999 sk_txeof(sc_if); 2000 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2001 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 2002 2003 ifp->if_oerrors++; 2004 2005 sk_init(ifp); 2006 } 2007 } 2008 2009 void 2010 sk_shutdown(void *v) 2011 { 2012 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2013 struct sk_softc *sc = sc_if->sk_softc; 2014 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2015 2016 DPRINTFN(2, ("sk_shutdown\n")); 2017 sk_stop(ifp,1); 2018 2019 /* Turn off the 'driver is loaded' LED. */ 2020 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2021 2022 /* 2023 * Reset the GEnesis controller. Doing this should also 2024 * assert the resets on the attached XMAC(s). 2025 */ 2026 sk_reset(sc); 2027 } 2028 2029 void 2030 sk_rxeof(struct sk_if_softc *sc_if) 2031 { 2032 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2033 struct mbuf *m; 2034 struct sk_chain *cur_rx; 2035 struct sk_rx_desc *cur_desc; 2036 int i, cur, total_len = 0; 2037 u_int32_t rxstat, sk_ctl; 2038 bus_dmamap_t dmamap; 2039 2040 i = sc_if->sk_cdata.sk_rx_prod; 2041 2042 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2043 2044 for (;;) { 2045 cur = i; 2046 2047 /* Sync the descriptor */ 2048 SK_CDRXSYNC(sc_if, cur, 2049 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2050 2051 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2052 if (sk_ctl & SK_RXCTL_OWN) { 2053 /* Invalidate the descriptor -- it's not ready yet */ 2054 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2055 sc_if->sk_cdata.sk_rx_prod = i; 2056 break; 2057 } 2058 2059 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2060 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2061 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2062 2063 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2064 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2065 2066 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2067 m = cur_rx->sk_mbuf; 2068 cur_rx->sk_mbuf = NULL; 2069 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2070 2071 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2072 2073 SK_INC(i, SK_RX_RING_CNT); 2074 2075 if (rxstat & XM_RXSTAT_ERRFRAME) { 2076 ifp->if_ierrors++; 2077 sk_newbuf(sc_if, cur, m, dmamap); 2078 continue; 2079 } 2080 2081 /* 2082 * Try to allocate a new jumbo buffer. If that 2083 * fails, copy the packet to mbufs and put the 2084 * jumbo buffer back in the ring so it can be 2085 * re-used. If allocating mbufs fails, then we 2086 * have to drop the packet. 2087 */ 2088 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2089 struct mbuf *m0; 2090 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2091 total_len + ETHER_ALIGN, 0, ifp, NULL); 2092 sk_newbuf(sc_if, cur, m, dmamap); 2093 if (m0 == NULL) { 2094 aprint_error_dev(sc_if->sk_dev, "no receive " 2095 "buffers available -- packet dropped!\n"); 2096 ifp->if_ierrors++; 2097 continue; 2098 } 2099 m_adj(m0, ETHER_ALIGN); 2100 m = m0; 2101 } else { 2102 m->m_pkthdr.rcvif = ifp; 2103 m->m_pkthdr.len = m->m_len = total_len; 2104 } 2105 2106 ifp->if_ipackets++; 2107 2108 #if NBPFILTER > 0 2109 if (ifp->if_bpf) 2110 bpf_mtap(ifp->if_bpf, m); 2111 #endif 2112 /* pass it on. */ 2113 (*ifp->if_input)(ifp, m); 2114 } 2115 } 2116 2117 void 2118 sk_txeof(struct sk_if_softc *sc_if) 2119 { 2120 struct sk_softc *sc = sc_if->sk_softc; 2121 struct sk_tx_desc *cur_tx; 2122 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2123 u_int32_t idx, sk_ctl; 2124 struct sk_txmap_entry *entry; 2125 2126 DPRINTFN(3, ("sk_txeof\n")); 2127 2128 /* 2129 * Go through our tx ring and free mbufs for those 2130 * frames that have been sent. 2131 */ 2132 idx = sc_if->sk_cdata.sk_tx_cons; 2133 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2134 SK_CDTXSYNC(sc_if, idx, 1, 2135 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2136 2137 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2138 sk_ctl = le32toh(cur_tx->sk_ctl); 2139 #ifdef SK_DEBUG 2140 if (skdebug >= 3) 2141 sk_dump_txdesc(cur_tx, idx); 2142 #endif 2143 if (sk_ctl & SK_TXCTL_OWN) { 2144 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2145 break; 2146 } 2147 if (sk_ctl & SK_TXCTL_LASTFRAG) 2148 ifp->if_opackets++; 2149 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2150 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2151 2152 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2153 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2154 2155 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2156 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2157 2158 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2159 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2160 link); 2161 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2162 } 2163 sc_if->sk_cdata.sk_tx_cnt--; 2164 SK_INC(idx, SK_TX_RING_CNT); 2165 } 2166 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2167 ifp->if_timer = 0; 2168 else /* nudge chip to keep tx ring moving */ 2169 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2170 2171 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2172 ifp->if_flags &= ~IFF_OACTIVE; 2173 2174 sc_if->sk_cdata.sk_tx_cons = idx; 2175 } 2176 2177 void 2178 sk_tick(void *xsc_if) 2179 { 2180 struct sk_if_softc *sc_if = xsc_if; 2181 struct mii_data *mii = &sc_if->sk_mii; 2182 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2183 int i; 2184 2185 DPRINTFN(3, ("sk_tick\n")); 2186 2187 if (!(ifp->if_flags & IFF_UP)) 2188 return; 2189 2190 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2191 sk_intr_bcom(sc_if); 2192 return; 2193 } 2194 2195 /* 2196 * According to SysKonnect, the correct way to verify that 2197 * the link has come back up is to poll bit 0 of the GPIO 2198 * register three times. This pin has the signal from the 2199 * link sync pin connected to it; if we read the same link 2200 * state 3 times in a row, we know the link is up. 2201 */ 2202 for (i = 0; i < 3; i++) { 2203 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2204 break; 2205 } 2206 2207 if (i != 3) { 2208 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2209 return; 2210 } 2211 2212 /* Turn the GP0 interrupt back on. */ 2213 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2214 SK_XM_READ_2(sc_if, XM_ISR); 2215 mii_tick(mii); 2216 mii_pollstat(mii); 2217 callout_stop(&sc_if->sk_tick_ch); 2218 } 2219 2220 void 2221 sk_intr_bcom(struct sk_if_softc *sc_if) 2222 { 2223 struct mii_data *mii = &sc_if->sk_mii; 2224 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2225 int status; 2226 2227 2228 DPRINTFN(3, ("sk_intr_bcom\n")); 2229 2230 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2231 2232 /* 2233 * Read the PHY interrupt register to make sure 2234 * we clear any pending interrupts. 2235 */ 2236 status = sk_xmac_miibus_readreg(sc_if->sk_dev, 2237 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2238 2239 if (!(ifp->if_flags & IFF_RUNNING)) { 2240 sk_init_xmac(sc_if); 2241 return; 2242 } 2243 2244 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2245 int lstat; 2246 lstat = sk_xmac_miibus_readreg(sc_if->sk_dev, 2247 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2248 2249 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2250 (void)mii_mediachg(mii); 2251 /* Turn off the link LED. */ 2252 SK_IF_WRITE_1(sc_if, 0, 2253 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2254 sc_if->sk_link = 0; 2255 } else if (status & BRGPHY_ISR_LNK_CHG) { 2256 sk_xmac_miibus_writereg(sc_if->sk_dev, 2257 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2258 mii_tick(mii); 2259 sc_if->sk_link = 1; 2260 /* Turn on the link LED. */ 2261 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2262 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2263 SK_LINKLED_BLINK_OFF); 2264 mii_pollstat(mii); 2265 } else { 2266 mii_tick(mii); 2267 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2268 } 2269 } 2270 2271 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2272 } 2273 2274 void 2275 sk_intr_xmac(struct sk_if_softc *sc_if) 2276 { 2277 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2278 2279 DPRINTFN(3, ("sk_intr_xmac\n")); 2280 2281 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2282 if (status & XM_ISR_GP0_SET) { 2283 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2284 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2285 } 2286 2287 if (status & XM_ISR_AUTONEG_DONE) { 2288 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2289 } 2290 } 2291 2292 if (status & XM_IMR_TX_UNDERRUN) 2293 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2294 2295 if (status & XM_IMR_RX_OVERRUN) 2296 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2297 } 2298 2299 void 2300 sk_intr_yukon(struct sk_if_softc *sc_if) 2301 { 2302 int status; 2303 2304 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2305 2306 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2307 } 2308 2309 int 2310 sk_intr(void *xsc) 2311 { 2312 struct sk_softc *sc = xsc; 2313 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2314 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2315 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2316 u_int32_t status; 2317 int claimed = 0; 2318 2319 if (sc_if0 != NULL) 2320 ifp0 = &sc_if0->sk_ethercom.ec_if; 2321 if (sc_if1 != NULL) 2322 ifp1 = &sc_if1->sk_ethercom.ec_if; 2323 2324 for (;;) { 2325 status = CSR_READ_4(sc, SK_ISSR); 2326 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2327 2328 if (!(status & sc->sk_intrmask)) 2329 break; 2330 2331 claimed = 1; 2332 2333 /* Handle receive interrupts first. */ 2334 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2335 sk_rxeof(sc_if0); 2336 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2337 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2338 } 2339 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2340 sk_rxeof(sc_if1); 2341 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2342 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2343 } 2344 2345 /* Then transmit interrupts. */ 2346 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2347 sk_txeof(sc_if0); 2348 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2349 SK_TXBMU_CLR_IRQ_EOF); 2350 } 2351 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2352 sk_txeof(sc_if1); 2353 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2354 SK_TXBMU_CLR_IRQ_EOF); 2355 } 2356 2357 /* Then MAC interrupts. */ 2358 if (sc_if0 && (status & SK_ISR_MAC1) && 2359 (ifp0->if_flags & IFF_RUNNING)) { 2360 if (sc->sk_type == SK_GENESIS) 2361 sk_intr_xmac(sc_if0); 2362 else 2363 sk_intr_yukon(sc_if0); 2364 } 2365 2366 if (sc_if1 && (status & SK_ISR_MAC2) && 2367 (ifp1->if_flags & IFF_RUNNING)) { 2368 if (sc->sk_type == SK_GENESIS) 2369 sk_intr_xmac(sc_if1); 2370 else 2371 sk_intr_yukon(sc_if1); 2372 2373 } 2374 2375 if (status & SK_ISR_EXTERNAL_REG) { 2376 if (sc_if0 != NULL && 2377 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2378 sk_intr_bcom(sc_if0); 2379 2380 if (sc_if1 != NULL && 2381 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2382 sk_intr_bcom(sc_if1); 2383 } 2384 } 2385 2386 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2387 2388 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2389 sk_start(ifp0); 2390 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2391 sk_start(ifp1); 2392 2393 #if NRND > 0 2394 if (RND_ENABLED(&sc->rnd_source)) 2395 rnd_add_uint32(&sc->rnd_source, status); 2396 #endif 2397 2398 if (sc->sk_int_mod_pending) 2399 sk_update_int_mod(sc); 2400 2401 return claimed; 2402 } 2403 2404 void 2405 sk_init_xmac(struct sk_if_softc *sc_if) 2406 { 2407 struct sk_softc *sc = sc_if->sk_softc; 2408 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2409 static const struct sk_bcom_hack bhack[] = { 2410 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2411 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2412 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2413 { 0, 0 } }; 2414 2415 DPRINTFN(1, ("sk_init_xmac\n")); 2416 2417 /* Unreset the XMAC. */ 2418 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2419 DELAY(1000); 2420 2421 /* Reset the XMAC's internal state. */ 2422 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2423 2424 /* Save the XMAC II revision */ 2425 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2426 2427 /* 2428 * Perform additional initialization for external PHYs, 2429 * namely for the 1000baseTX cards that use the XMAC's 2430 * GMII mode. 2431 */ 2432 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2433 int i = 0; 2434 u_int32_t val; 2435 2436 /* Take PHY out of reset. */ 2437 val = sk_win_read_4(sc, SK_GPIO); 2438 if (sc_if->sk_port == SK_PORT_A) 2439 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2440 else 2441 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2442 sk_win_write_4(sc, SK_GPIO, val); 2443 2444 /* Enable GMII mode on the XMAC. */ 2445 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2446 2447 sk_xmac_miibus_writereg(sc_if->sk_dev, 2448 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2449 DELAY(10000); 2450 sk_xmac_miibus_writereg(sc_if->sk_dev, 2451 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2452 2453 /* 2454 * Early versions of the BCM5400 apparently have 2455 * a bug that requires them to have their reserved 2456 * registers initialized to some magic values. I don't 2457 * know what the numbers do, I'm just the messenger. 2458 */ 2459 if (sk_xmac_miibus_readreg(sc_if->sk_dev, 2460 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2461 while (bhack[i].reg) { 2462 sk_xmac_miibus_writereg(sc_if->sk_dev, 2463 SK_PHYADDR_BCOM, bhack[i].reg, 2464 bhack[i].val); 2465 i++; 2466 } 2467 } 2468 } 2469 2470 /* Set station address */ 2471 SK_XM_WRITE_2(sc_if, XM_PAR0, 2472 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2473 SK_XM_WRITE_2(sc_if, XM_PAR1, 2474 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2475 SK_XM_WRITE_2(sc_if, XM_PAR2, 2476 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2477 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2478 2479 if (ifp->if_flags & IFF_PROMISC) 2480 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2481 else 2482 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2483 2484 if (ifp->if_flags & IFF_BROADCAST) 2485 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2486 else 2487 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2488 2489 /* We don't need the FCS appended to the packet. */ 2490 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2491 2492 /* We want short frames padded to 60 bytes. */ 2493 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2494 2495 /* 2496 * Enable the reception of all error frames. This is is 2497 * a necessary evil due to the design of the XMAC. The 2498 * XMAC's receive FIFO is only 8K in size, however jumbo 2499 * frames can be up to 9000 bytes in length. When bad 2500 * frame filtering is enabled, the XMAC's RX FIFO operates 2501 * in 'store and forward' mode. For this to work, the 2502 * entire frame has to fit into the FIFO, but that means 2503 * that jumbo frames larger than 8192 bytes will be 2504 * truncated. Disabling all bad frame filtering causes 2505 * the RX FIFO to operate in streaming mode, in which 2506 * case the XMAC will start transfering frames out of the 2507 * RX FIFO as soon as the FIFO threshold is reached. 2508 */ 2509 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2510 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2511 XM_MODE_RX_INRANGELEN); 2512 2513 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2514 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2515 else 2516 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2517 2518 /* 2519 * Bump up the transmit threshold. This helps hold off transmit 2520 * underruns when we're blasting traffic from both ports at once. 2521 */ 2522 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2523 2524 /* Set multicast filter */ 2525 sk_setmulti(sc_if); 2526 2527 /* Clear and enable interrupts */ 2528 SK_XM_READ_2(sc_if, XM_ISR); 2529 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2530 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2531 else 2532 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2533 2534 /* Configure MAC arbiter */ 2535 switch (sc_if->sk_xmac_rev) { 2536 case XM_XMAC_REV_B2: 2537 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2538 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2539 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2540 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2541 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2542 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2543 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2544 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2545 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2546 break; 2547 case XM_XMAC_REV_C1: 2548 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2549 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2550 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2551 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2552 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2553 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2554 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2555 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2556 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2557 break; 2558 default: 2559 break; 2560 } 2561 sk_win_write_2(sc, SK_MACARB_CTL, 2562 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2563 2564 sc_if->sk_link = 1; 2565 } 2566 2567 void sk_init_yukon(struct sk_if_softc *sc_if) 2568 { 2569 u_int32_t /*mac, */phy; 2570 u_int16_t reg; 2571 struct sk_softc *sc; 2572 int i; 2573 2574 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2575 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2576 2577 sc = sc_if->sk_softc; 2578 if (sc->sk_type == SK_YUKON_LITE && 2579 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2580 /* Take PHY out of reset. */ 2581 sk_win_write_4(sc, SK_GPIO, 2582 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2583 } 2584 2585 2586 /* GMAC and GPHY Reset */ 2587 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2588 2589 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2590 2591 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2592 DELAY(1000); 2593 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2594 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2595 DELAY(1000); 2596 2597 2598 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2599 2600 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2601 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2602 2603 switch (sc_if->sk_softc->sk_pmd) { 2604 case IFM_1000_SX: 2605 case IFM_1000_LX: 2606 phy |= SK_GPHY_FIBER; 2607 break; 2608 2609 case IFM_1000_CX: 2610 case IFM_1000_T: 2611 phy |= SK_GPHY_COPPER; 2612 break; 2613 } 2614 2615 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2616 2617 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2618 DELAY(1000); 2619 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2620 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2621 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2622 2623 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2624 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2625 2626 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2627 2628 /* unused read of the interrupt source register */ 2629 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2630 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2631 2632 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2633 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2634 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2635 2636 /* MIB Counter Clear Mode set */ 2637 reg |= YU_PAR_MIB_CLR; 2638 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2639 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2640 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2641 2642 /* MIB Counter Clear Mode clear */ 2643 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2644 reg &= ~YU_PAR_MIB_CLR; 2645 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2646 2647 /* receive control reg */ 2648 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2649 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2650 YU_RCR_CRCR); 2651 2652 /* transmit parameter register */ 2653 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2654 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2655 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2656 2657 /* serial mode register */ 2658 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2659 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2660 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2661 YU_SMR_IPG_DATA(0x1e)); 2662 2663 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2664 /* Setup Yukon's address */ 2665 for (i = 0; i < 3; i++) { 2666 /* Write Source Address 1 (unicast filter) */ 2667 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2668 sc_if->sk_enaddr[i * 2] | 2669 sc_if->sk_enaddr[i * 2 + 1] << 8); 2670 } 2671 2672 for (i = 0; i < 3; i++) { 2673 reg = sk_win_read_2(sc_if->sk_softc, 2674 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2675 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2676 } 2677 2678 /* Set multicast filter */ 2679 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2680 sk_setmulti(sc_if); 2681 2682 /* enable interrupt mask for counter overflows */ 2683 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2684 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2685 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2686 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2687 2688 /* Configure RX MAC FIFO */ 2689 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2690 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2691 2692 /* Configure TX MAC FIFO */ 2693 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2694 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2695 2696 DPRINTFN(6, ("sk_init_yukon: end\n")); 2697 } 2698 2699 /* 2700 * Note that to properly initialize any part of the GEnesis chip, 2701 * you first have to take it out of reset mode. 2702 */ 2703 int 2704 sk_init(struct ifnet *ifp) 2705 { 2706 struct sk_if_softc *sc_if = ifp->if_softc; 2707 struct sk_softc *sc = sc_if->sk_softc; 2708 struct mii_data *mii = &sc_if->sk_mii; 2709 int rc = 0, s; 2710 u_int32_t imr, imtimer_ticks; 2711 2712 DPRINTFN(1, ("sk_init\n")); 2713 2714 s = splnet(); 2715 2716 if (ifp->if_flags & IFF_RUNNING) { 2717 splx(s); 2718 return 0; 2719 } 2720 2721 /* Cancel pending I/O and free all RX/TX buffers. */ 2722 sk_stop(ifp,0); 2723 2724 if (sc->sk_type == SK_GENESIS) { 2725 /* Configure LINK_SYNC LED */ 2726 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2727 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2728 SK_LINKLED_LINKSYNC_ON); 2729 2730 /* Configure RX LED */ 2731 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2732 SK_RXLEDCTL_COUNTER_START); 2733 2734 /* Configure TX LED */ 2735 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2736 SK_TXLEDCTL_COUNTER_START); 2737 } 2738 2739 /* Configure I2C registers */ 2740 2741 /* Configure XMAC(s) */ 2742 switch (sc->sk_type) { 2743 case SK_GENESIS: 2744 sk_init_xmac(sc_if); 2745 break; 2746 case SK_YUKON: 2747 case SK_YUKON_LITE: 2748 case SK_YUKON_LP: 2749 sk_init_yukon(sc_if); 2750 break; 2751 } 2752 if ((rc = mii_mediachg(mii)) == ENXIO) 2753 rc = 0; 2754 else if (rc != 0) 2755 goto out; 2756 2757 if (sc->sk_type == SK_GENESIS) { 2758 /* Configure MAC FIFOs */ 2759 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2760 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2761 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2762 2763 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2764 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2765 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2766 } 2767 2768 /* Configure transmit arbiter(s) */ 2769 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2770 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2771 2772 /* Configure RAMbuffers */ 2773 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2774 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2775 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2776 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2777 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2778 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2779 2780 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2781 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2782 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2783 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2784 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2785 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2786 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2787 2788 /* Configure BMUs */ 2789 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2790 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2791 SK_RX_RING_ADDR(sc_if, 0)); 2792 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2793 2794 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2795 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2796 SK_TX_RING_ADDR(sc_if, 0)); 2797 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2798 2799 /* Init descriptors */ 2800 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2801 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2802 "memory for rx buffers\n"); 2803 sk_stop(ifp,0); 2804 splx(s); 2805 return ENOBUFS; 2806 } 2807 2808 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2809 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2810 "memory for tx buffers\n"); 2811 sk_stop(ifp,0); 2812 splx(s); 2813 return ENOBUFS; 2814 } 2815 2816 /* Set interrupt moderation if changed via sysctl. */ 2817 switch (sc->sk_type) { 2818 case SK_GENESIS: 2819 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2820 break; 2821 case SK_YUKON_EC: 2822 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2823 break; 2824 default: 2825 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2826 } 2827 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2828 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2829 sk_win_write_4(sc, SK_IMTIMERINIT, 2830 SK_IM_USECS(sc->sk_int_mod)); 2831 aprint_verbose_dev(sc->sk_dev, 2832 "interrupt moderation is %d us\n", sc->sk_int_mod); 2833 } 2834 2835 /* Configure interrupt handling */ 2836 CSR_READ_4(sc, SK_ISSR); 2837 if (sc_if->sk_port == SK_PORT_A) 2838 sc->sk_intrmask |= SK_INTRS1; 2839 else 2840 sc->sk_intrmask |= SK_INTRS2; 2841 2842 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2843 2844 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2845 2846 /* Start BMUs. */ 2847 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2848 2849 if (sc->sk_type == SK_GENESIS) { 2850 /* Enable XMACs TX and RX state machines */ 2851 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2852 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2853 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2854 } 2855 2856 if (SK_YUKON_FAMILY(sc->sk_type)) { 2857 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2858 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2859 #if 0 2860 /* XXX disable 100Mbps and full duplex mode? */ 2861 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2862 #endif 2863 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2864 } 2865 2866 2867 ifp->if_flags |= IFF_RUNNING; 2868 ifp->if_flags &= ~IFF_OACTIVE; 2869 2870 out: 2871 splx(s); 2872 return rc; 2873 } 2874 2875 void 2876 sk_stop(struct ifnet *ifp, int disable) 2877 { 2878 struct sk_if_softc *sc_if = ifp->if_softc; 2879 struct sk_softc *sc = sc_if->sk_softc; 2880 int i; 2881 2882 DPRINTFN(1, ("sk_stop\n")); 2883 2884 callout_stop(&sc_if->sk_tick_ch); 2885 2886 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2887 u_int32_t val; 2888 2889 /* Put PHY back into reset. */ 2890 val = sk_win_read_4(sc, SK_GPIO); 2891 if (sc_if->sk_port == SK_PORT_A) { 2892 val |= SK_GPIO_DIR0; 2893 val &= ~SK_GPIO_DAT0; 2894 } else { 2895 val |= SK_GPIO_DIR2; 2896 val &= ~SK_GPIO_DAT2; 2897 } 2898 sk_win_write_4(sc, SK_GPIO, val); 2899 } 2900 2901 /* Turn off various components of this interface. */ 2902 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2903 switch (sc->sk_type) { 2904 case SK_GENESIS: 2905 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2906 SK_TXMACCTL_XMAC_RESET); 2907 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2908 break; 2909 case SK_YUKON: 2910 case SK_YUKON_LITE: 2911 case SK_YUKON_LP: 2912 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2913 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2914 break; 2915 } 2916 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2917 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2918 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2919 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2920 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2921 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2922 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2923 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2924 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2925 2926 /* Disable interrupts */ 2927 if (sc_if->sk_port == SK_PORT_A) 2928 sc->sk_intrmask &= ~SK_INTRS1; 2929 else 2930 sc->sk_intrmask &= ~SK_INTRS2; 2931 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2932 2933 SK_XM_READ_2(sc_if, XM_ISR); 2934 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2935 2936 /* Free RX and TX mbufs still in the queues. */ 2937 for (i = 0; i < SK_RX_RING_CNT; i++) { 2938 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2939 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2940 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2941 } 2942 } 2943 2944 for (i = 0; i < SK_TX_RING_CNT; i++) { 2945 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2946 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2947 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2948 } 2949 } 2950 2951 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2952 } 2953 2954 /* Power Management Framework */ 2955 2956 static bool 2957 skc_suspend(device_t dv PMF_FN_ARGS) 2958 { 2959 struct sk_softc *sc = device_private(dv); 2960 2961 DPRINTFN(2, ("skc_suspend\n")); 2962 2963 /* Turn off the driver is loaded LED */ 2964 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2965 2966 return true; 2967 } 2968 2969 static bool 2970 skc_resume(device_t dv PMF_FN_ARGS) 2971 { 2972 struct sk_softc *sc = device_private(dv); 2973 2974 DPRINTFN(2, ("skc_resume\n")); 2975 2976 sk_reset(sc); 2977 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2978 2979 return true; 2980 } 2981 2982 static bool 2983 sk_resume(device_t dv PMF_FN_ARGS) 2984 { 2985 struct sk_if_softc *sc_if = device_private(dv); 2986 2987 sk_init_yukon(sc_if); 2988 return true; 2989 } 2990 2991 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 2992 skc_probe, skc_attach, NULL, NULL); 2993 2994 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 2995 sk_probe, sk_attach, NULL, NULL); 2996 2997 #ifdef SK_DEBUG 2998 void 2999 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 3000 { 3001 #define DESC_PRINT(X) \ 3002 if (X) \ 3003 printf("txdesc[%d]." #X "=%#x\n", \ 3004 idx, X); 3005 3006 DESC_PRINT(le32toh(desc->sk_ctl)); 3007 DESC_PRINT(le32toh(desc->sk_next)); 3008 DESC_PRINT(le32toh(desc->sk_data_lo)); 3009 DESC_PRINT(le32toh(desc->sk_data_hi)); 3010 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 3011 DESC_PRINT(le16toh(desc->sk_rsvd0)); 3012 DESC_PRINT(le16toh(desc->sk_csum_startval)); 3013 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 3014 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 3015 DESC_PRINT(le16toh(desc->sk_rsvd1)); 3016 #undef PRINT 3017 } 3018 3019 void 3020 sk_dump_bytes(const char *data, int len) 3021 { 3022 int c, i, j; 3023 3024 for (i = 0; i < len; i += 16) { 3025 printf("%08x ", i); 3026 c = len - i; 3027 if (c > 16) c = 16; 3028 3029 for (j = 0; j < c; j++) { 3030 printf("%02x ", data[i + j] & 0xff); 3031 if ((j & 0xf) == 7 && j > 0) 3032 printf(" "); 3033 } 3034 3035 for (; j < 16; j++) 3036 printf(" "); 3037 printf(" "); 3038 3039 for (j = 0; j < c; j++) { 3040 int ch = data[i + j] & 0xff; 3041 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3042 } 3043 3044 printf("\n"); 3045 3046 if (c < 16) 3047 break; 3048 } 3049 } 3050 3051 void 3052 sk_dump_mbuf(struct mbuf *m) 3053 { 3054 int count = m->m_pkthdr.len; 3055 3056 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3057 3058 while (count > 0 && m) { 3059 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3060 m, m->m_data, m->m_len); 3061 sk_dump_bytes(mtod(m, char *), m->m_len); 3062 3063 count -= m->m_len; 3064 m = m->m_next; 3065 } 3066 } 3067 #endif 3068 3069 static int 3070 sk_sysctl_handler(SYSCTLFN_ARGS) 3071 { 3072 int error, t; 3073 struct sysctlnode node; 3074 struct sk_softc *sc; 3075 3076 node = *rnode; 3077 sc = node.sysctl_data; 3078 t = sc->sk_int_mod; 3079 node.sysctl_data = &t; 3080 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3081 if (error || newp == NULL) 3082 return error; 3083 3084 if (t < SK_IM_MIN || t > SK_IM_MAX) 3085 return EINVAL; 3086 3087 /* update the softc with sysctl-changed value, and mark 3088 for hardware update */ 3089 sc->sk_int_mod = t; 3090 sc->sk_int_mod_pending = 1; 3091 return 0; 3092 } 3093 3094 /* 3095 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3096 * set up in skc_attach() 3097 */ 3098 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3099 { 3100 int rc; 3101 const struct sysctlnode *node; 3102 3103 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3104 0, CTLTYPE_NODE, "hw", NULL, 3105 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3106 goto err; 3107 } 3108 3109 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3110 0, CTLTYPE_NODE, "sk", 3111 SYSCTL_DESCR("sk interface controls"), 3112 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3113 goto err; 3114 } 3115 3116 sk_root_num = node->sysctl_num; 3117 return; 3118 3119 err: 3120 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3121 } 3122
Indexes created Mon Oct 13 15:10:03 GMT 2025