if_sk.c revision 1.49
1 /* $NetBSD: if_sk.c,v 1.49 2008/04/28 20:23:55 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.49 2008/04/28 20:23:55 martin Exp $"); 119 120 #include "bpfilter.h" 121 #include "rnd.h" 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/sockio.h> 126 #include <sys/mbuf.h> 127 #include <sys/malloc.h> 128 #include <sys/kernel.h> 129 #include <sys/socket.h> 130 #include <sys/device.h> 131 #include <sys/queue.h> 132 #include <sys/callout.h> 133 #include <sys/sysctl.h> 134 #include <sys/endian.h> 135 136 #include <net/if.h> 137 #include <net/if_dl.h> 138 #include <net/if_types.h> 139 140 #include <net/if_media.h> 141 142 #if NBPFILTER > 0 143 #include <net/bpf.h> 144 #endif 145 #if NRND > 0 146 #include <sys/rnd.h> 147 #endif 148 149 #include <dev/mii/mii.h> 150 #include <dev/mii/miivar.h> 151 #include <dev/mii/brgphyreg.h> 152 153 #include <dev/pci/pcireg.h> 154 #include <dev/pci/pcivar.h> 155 #include <dev/pci/pcidevs.h> 156 157 /* #define SK_USEIOSPACE */ 158 159 #include <dev/pci/if_skreg.h> 160 #include <dev/pci/if_skvar.h> 161 162 int skc_probe(struct device *, struct cfdata *, void *); 163 void skc_attach(struct device *, struct device *self, void *aux); 164 int sk_probe(struct device *, struct cfdata *, void *); 165 void sk_attach(struct device *, struct device *self, void *aux); 166 int skcprint(void *, const char *); 167 int sk_intr(void *); 168 void sk_intr_bcom(struct sk_if_softc *); 169 void sk_intr_xmac(struct sk_if_softc *); 170 void sk_intr_yukon(struct sk_if_softc *); 171 void sk_rxeof(struct sk_if_softc *); 172 void sk_txeof(struct sk_if_softc *); 173 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 174 void sk_start(struct ifnet *); 175 int sk_ioctl(struct ifnet *, u_long, void *); 176 int sk_init(struct ifnet *); 177 void sk_init_xmac(struct sk_if_softc *); 178 void sk_init_yukon(struct sk_if_softc *); 179 void sk_stop(struct ifnet *, int); 180 void sk_watchdog(struct ifnet *); 181 void sk_shutdown(void *); 182 int sk_ifmedia_upd(struct ifnet *); 183 void sk_reset(struct sk_softc *); 184 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 185 int sk_alloc_jumbo_mem(struct sk_if_softc *); 186 void sk_free_jumbo_mem(struct sk_if_softc *); 187 void *sk_jalloc(struct sk_if_softc *); 188 void sk_jfree(struct mbuf *, void *, size_t, void *); 189 int sk_init_rx_ring(struct sk_if_softc *); 190 int sk_init_tx_ring(struct sk_if_softc *); 191 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 192 void sk_vpd_read_res(struct sk_softc *, 193 struct vpd_res *, int); 194 void sk_vpd_read(struct sk_softc *); 195 196 void sk_update_int_mod(struct sk_softc *); 197 198 int sk_xmac_miibus_readreg(struct device *, int, int); 199 void sk_xmac_miibus_writereg(struct device *, int, int, int); 200 void sk_xmac_miibus_statchg(struct device *); 201 202 int sk_marv_miibus_readreg(struct device *, int, int); 203 void sk_marv_miibus_writereg(struct device *, int, int, int); 204 void sk_marv_miibus_statchg(struct device *); 205 206 u_int32_t sk_xmac_hash(void *); 207 u_int32_t sk_yukon_hash(void *); 208 void sk_setfilt(struct sk_if_softc *, void *, int); 209 void sk_setmulti(struct sk_if_softc *); 210 void sk_tick(void *); 211 212 /* #define SK_DEBUG 2 */ 213 #ifdef SK_DEBUG 214 #define DPRINTF(x) if (skdebug) printf x 215 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 216 int skdebug = SK_DEBUG; 217 218 void sk_dump_txdesc(struct sk_tx_desc *, int); 219 void sk_dump_mbuf(struct mbuf *); 220 void sk_dump_bytes(const char *, int); 221 #else 222 #define DPRINTF(x) 223 #define DPRINTFN(n,x) 224 #endif 225 226 static int sk_sysctl_handler(SYSCTLFN_PROTO); 227 static int sk_root_num; 228 229 /* supported device vendors */ 230 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 231 static const struct sk_product { 232 pci_vendor_id_t sk_vendor; 233 pci_product_id_t sk_product; 234 } sk_products[] = { 235 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 236 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 237 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 238 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 239 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 240 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 241 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 242 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 243 { 0, 0, } 244 }; 245 246 #define SK_LINKSYS_EG1032_SUBID 0x00151737 247 248 static inline u_int32_t 249 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 250 { 251 #ifdef SK_USEIOSPACE 252 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 253 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 254 #else 255 return CSR_READ_4(sc, reg); 256 #endif 257 } 258 259 static inline u_int16_t 260 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 261 { 262 #ifdef SK_USEIOSPACE 263 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 264 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 265 #else 266 return CSR_READ_2(sc, reg); 267 #endif 268 } 269 270 static inline u_int8_t 271 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 272 { 273 #ifdef SK_USEIOSPACE 274 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 275 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 276 #else 277 return CSR_READ_1(sc, reg); 278 #endif 279 } 280 281 static inline void 282 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 283 { 284 #ifdef SK_USEIOSPACE 285 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 286 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 287 #else 288 CSR_WRITE_4(sc, reg, x); 289 #endif 290 } 291 292 static inline void 293 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 294 { 295 #ifdef SK_USEIOSPACE 296 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 297 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 298 #else 299 CSR_WRITE_2(sc, reg, x); 300 #endif 301 } 302 303 static inline void 304 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 305 { 306 #ifdef SK_USEIOSPACE 307 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 308 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 309 #else 310 CSR_WRITE_1(sc, reg, x); 311 #endif 312 } 313 314 /* 315 * The VPD EEPROM contains Vital Product Data, as suggested in 316 * the PCI 2.1 specification. The VPD data is separared into areas 317 * denoted by resource IDs. The SysKonnect VPD contains an ID string 318 * resource (the name of the adapter), a read-only area resource 319 * containing various key/data fields and a read/write area which 320 * can be used to store asset management information or log messages. 321 * We read the ID string and read-only into buffers attached to 322 * the controller softc structure for later use. At the moment, 323 * we only use the ID string during sk_attach(). 324 */ 325 u_int8_t 326 sk_vpd_readbyte(struct sk_softc *sc, int addr) 327 { 328 int i; 329 330 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 331 for (i = 0; i < SK_TIMEOUT; i++) { 332 DELAY(1); 333 if (sk_win_read_2(sc, 334 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 335 break; 336 } 337 338 if (i == SK_TIMEOUT) 339 return 0; 340 341 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 342 } 343 344 void 345 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 346 { 347 int i; 348 u_int8_t *ptr; 349 350 ptr = (u_int8_t *)res; 351 for (i = 0; i < sizeof(struct vpd_res); i++) 352 ptr[i] = sk_vpd_readbyte(sc, i + addr); 353 } 354 355 void 356 sk_vpd_read(struct sk_softc *sc) 357 { 358 int pos = 0, i; 359 struct vpd_res res; 360 361 if (sc->sk_vpd_prodname != NULL) 362 free(sc->sk_vpd_prodname, M_DEVBUF); 363 if (sc->sk_vpd_readonly != NULL) 364 free(sc->sk_vpd_readonly, M_DEVBUF); 365 sc->sk_vpd_prodname = NULL; 366 sc->sk_vpd_readonly = NULL; 367 368 sk_vpd_read_res(sc, &res, pos); 369 370 if (res.vr_id != VPD_RES_ID) { 371 aprint_error_dev(&sc->sk_dev, "bad VPD resource id: expected %x got %x\n", 372 VPD_RES_ID, res.vr_id); 373 return; 374 } 375 376 pos += sizeof(res); 377 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 378 if (sc->sk_vpd_prodname == NULL) 379 panic("sk_vpd_read"); 380 for (i = 0; i < res.vr_len; i++) 381 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 382 sc->sk_vpd_prodname[i] = '\0'; 383 pos += i; 384 385 sk_vpd_read_res(sc, &res, pos); 386 387 if (res.vr_id != VPD_RES_READ) { 388 aprint_error_dev(&sc->sk_dev, "bad VPD resource id: expected %x got %x\n", 389 VPD_RES_READ, res.vr_id); 390 return; 391 } 392 393 pos += sizeof(res); 394 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 395 if (sc->sk_vpd_readonly == NULL) 396 panic("sk_vpd_read"); 397 for (i = 0; i < res.vr_len ; i++) 398 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 399 } 400 401 int 402 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 403 { 404 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 405 int i; 406 407 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 408 409 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 410 return 0; 411 412 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 413 SK_XM_READ_2(sc_if, XM_PHY_DATA); 414 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 415 for (i = 0; i < SK_TIMEOUT; i++) { 416 DELAY(1); 417 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 418 XM_MMUCMD_PHYDATARDY) 419 break; 420 } 421 422 if (i == SK_TIMEOUT) { 423 aprint_error_dev(&sc_if->sk_dev, "phy failed to come ready\n"); 424 return 0; 425 } 426 } 427 DELAY(1); 428 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 429 } 430 431 void 432 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 433 { 434 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 435 int i; 436 437 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 438 439 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 440 for (i = 0; i < SK_TIMEOUT; i++) { 441 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 442 break; 443 } 444 445 if (i == SK_TIMEOUT) { 446 aprint_error_dev(&sc_if->sk_dev, "phy failed to come ready\n"); 447 return; 448 } 449 450 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 451 for (i = 0; i < SK_TIMEOUT; i++) { 452 DELAY(1); 453 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 454 break; 455 } 456 457 if (i == SK_TIMEOUT) 458 aprint_error_dev(&sc_if->sk_dev, "phy write timed out\n"); 459 } 460 461 void 462 sk_xmac_miibus_statchg(struct device *dev) 463 { 464 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 465 struct mii_data *mii = &sc_if->sk_mii; 466 467 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 468 469 /* 470 * If this is a GMII PHY, manually set the XMAC's 471 * duplex mode accordingly. 472 */ 473 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 474 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 475 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 476 else 477 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 478 } 479 } 480 481 int 482 sk_marv_miibus_readreg(struct device *dev, int phy, int reg) 483 { 484 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 485 u_int16_t val; 486 int i; 487 488 if (phy != 0 || 489 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 490 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 491 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 492 phy, reg)); 493 return 0; 494 } 495 496 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 497 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 498 499 for (i = 0; i < SK_TIMEOUT; i++) { 500 DELAY(1); 501 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 502 if (val & YU_SMICR_READ_VALID) 503 break; 504 } 505 506 if (i == SK_TIMEOUT) { 507 aprint_error_dev(&sc_if->sk_dev, "phy failed to come ready\n"); 508 return 0; 509 } 510 511 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 512 SK_TIMEOUT)); 513 514 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 515 516 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 517 phy, reg, val)); 518 519 return val; 520 } 521 522 void 523 sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 524 { 525 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 526 int i; 527 528 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 529 phy, reg, val)); 530 531 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 532 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 533 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 534 535 for (i = 0; i < SK_TIMEOUT; i++) { 536 DELAY(1); 537 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 538 break; 539 } 540 541 if (i == SK_TIMEOUT) 542 printf("%s: phy write timed out\n", device_xname(&sc_if->sk_dev)); 543 } 544 545 void 546 sk_marv_miibus_statchg(struct device *dev) 547 { 548 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 549 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 550 } 551 552 #define SK_HASH_BITS 6 553 554 u_int32_t 555 sk_xmac_hash(void *addr) 556 { 557 u_int32_t crc; 558 559 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 560 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 561 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 562 return crc; 563 } 564 565 u_int32_t 566 sk_yukon_hash(void *addr) 567 { 568 u_int32_t crc; 569 570 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 571 crc &= ((1 << SK_HASH_BITS) - 1); 572 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 573 return crc; 574 } 575 576 void 577 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 578 { 579 char *addr = addrv; 580 int base = XM_RXFILT_ENTRY(slot); 581 582 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 583 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 584 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 585 } 586 587 void 588 sk_setmulti(struct sk_if_softc *sc_if) 589 { 590 struct sk_softc *sc = sc_if->sk_softc; 591 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 592 u_int32_t hashes[2] = { 0, 0 }; 593 int h = 0, i; 594 struct ethercom *ec = &sc_if->sk_ethercom; 595 struct ether_multi *enm; 596 struct ether_multistep step; 597 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 598 599 /* First, zot all the existing filters. */ 600 switch (sc->sk_type) { 601 case SK_GENESIS: 602 for (i = 1; i < XM_RXFILT_MAX; i++) 603 sk_setfilt(sc_if, (void *)&dummy, i); 604 605 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 606 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 607 break; 608 case SK_YUKON: 609 case SK_YUKON_LITE: 610 case SK_YUKON_LP: 611 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 612 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 613 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 614 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 615 break; 616 } 617 618 /* Now program new ones. */ 619 allmulti: 620 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 621 hashes[0] = 0xFFFFFFFF; 622 hashes[1] = 0xFFFFFFFF; 623 } else { 624 i = 1; 625 /* First find the tail of the list. */ 626 ETHER_FIRST_MULTI(step, ec, enm); 627 while (enm != NULL) { 628 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 629 ETHER_ADDR_LEN)) { 630 ifp->if_flags |= IFF_ALLMULTI; 631 goto allmulti; 632 } 633 DPRINTFN(2,("multicast address %s\n", 634 ether_sprintf(enm->enm_addrlo))); 635 /* 636 * Program the first XM_RXFILT_MAX multicast groups 637 * into the perfect filter. For all others, 638 * use the hash table. 639 */ 640 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 641 sk_setfilt(sc_if, enm->enm_addrlo, i); 642 i++; 643 } 644 else { 645 switch (sc->sk_type) { 646 case SK_GENESIS: 647 h = sk_xmac_hash(enm->enm_addrlo); 648 break; 649 case SK_YUKON: 650 case SK_YUKON_LITE: 651 case SK_YUKON_LP: 652 h = sk_yukon_hash(enm->enm_addrlo); 653 break; 654 } 655 if (h < 32) 656 hashes[0] |= (1 << h); 657 else 658 hashes[1] |= (1 << (h - 32)); 659 } 660 661 ETHER_NEXT_MULTI(step, enm); 662 } 663 } 664 665 switch (sc->sk_type) { 666 case SK_GENESIS: 667 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 668 XM_MODE_RX_USE_PERFECT); 669 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 670 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 671 break; 672 case SK_YUKON: 673 case SK_YUKON_LITE: 674 case SK_YUKON_LP: 675 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 676 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 677 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 678 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 679 break; 680 } 681 } 682 683 int 684 sk_init_rx_ring(struct sk_if_softc *sc_if) 685 { 686 struct sk_chain_data *cd = &sc_if->sk_cdata; 687 struct sk_ring_data *rd = sc_if->sk_rdata; 688 int i; 689 690 bzero((char *)rd->sk_rx_ring, 691 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 692 693 for (i = 0; i < SK_RX_RING_CNT; i++) { 694 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 695 if (i == (SK_RX_RING_CNT - 1)) { 696 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 697 rd->sk_rx_ring[i].sk_next = 698 htole32(SK_RX_RING_ADDR(sc_if, 0)); 699 } else { 700 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 701 rd->sk_rx_ring[i].sk_next = 702 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 703 } 704 } 705 706 for (i = 0; i < SK_RX_RING_CNT; i++) { 707 if (sk_newbuf(sc_if, i, NULL, 708 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 709 aprint_error_dev(&sc_if->sk_dev, "failed alloc of %dth mbuf\n", i); 710 return ENOBUFS; 711 } 712 } 713 sc_if->sk_cdata.sk_rx_prod = 0; 714 sc_if->sk_cdata.sk_rx_cons = 0; 715 716 return 0; 717 } 718 719 int 720 sk_init_tx_ring(struct sk_if_softc *sc_if) 721 { 722 struct sk_chain_data *cd = &sc_if->sk_cdata; 723 struct sk_ring_data *rd = sc_if->sk_rdata; 724 int i; 725 726 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 727 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 728 729 for (i = 0; i < SK_TX_RING_CNT; i++) { 730 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 731 if (i == (SK_TX_RING_CNT - 1)) { 732 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 733 rd->sk_tx_ring[i].sk_next = 734 htole32(SK_TX_RING_ADDR(sc_if, 0)); 735 } else { 736 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 737 rd->sk_tx_ring[i].sk_next = 738 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 739 } 740 } 741 742 sc_if->sk_cdata.sk_tx_prod = 0; 743 sc_if->sk_cdata.sk_tx_cons = 0; 744 sc_if->sk_cdata.sk_tx_cnt = 0; 745 746 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 747 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 748 749 return 0; 750 } 751 752 int 753 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 754 bus_dmamap_t dmamap) 755 { 756 struct mbuf *m_new = NULL; 757 struct sk_chain *c; 758 struct sk_rx_desc *r; 759 760 if (m == NULL) { 761 void *buf = NULL; 762 763 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 764 if (m_new == NULL) { 765 aprint_error_dev(&sc_if->sk_dev, "no memory for rx list -- " 766 "packet dropped!\n"); 767 return ENOBUFS; 768 } 769 770 /* Allocate the jumbo buffer */ 771 buf = sk_jalloc(sc_if); 772 if (buf == NULL) { 773 m_freem(m_new); 774 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 775 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 776 return ENOBUFS; 777 } 778 779 /* Attach the buffer to the mbuf */ 780 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 781 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 782 783 } else { 784 /* 785 * We're re-using a previously allocated mbuf; 786 * be sure to re-init pointers and lengths to 787 * default values. 788 */ 789 m_new = m; 790 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 791 m_new->m_data = m_new->m_ext.ext_buf; 792 } 793 m_adj(m_new, ETHER_ALIGN); 794 795 c = &sc_if->sk_cdata.sk_rx_chain[i]; 796 r = c->sk_desc; 797 c->sk_mbuf = m_new; 798 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 799 (((vaddr_t)m_new->m_data 800 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 801 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 802 803 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 804 805 return 0; 806 } 807 808 /* 809 * Memory management for jumbo frames. 810 */ 811 812 int 813 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 814 { 815 struct sk_softc *sc = sc_if->sk_softc; 816 char *ptr, *kva; 817 bus_dma_segment_t seg; 818 int i, rseg, state, error; 819 struct sk_jpool_entry *entry; 820 821 state = error = 0; 822 823 /* Grab a big chunk o' storage. */ 824 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 825 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 826 aprint_error_dev(&sc->sk_dev, "can't alloc rx buffers\n"); 827 return ENOBUFS; 828 } 829 830 state = 1; 831 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 832 BUS_DMA_NOWAIT)) { 833 aprint_error_dev(&sc->sk_dev, "can't map dma buffers (%d bytes)\n", 834 SK_JMEM); 835 error = ENOBUFS; 836 goto out; 837 } 838 839 state = 2; 840 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 841 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 842 aprint_error_dev(&sc->sk_dev, "can't create dma map\n"); 843 error = ENOBUFS; 844 goto out; 845 } 846 847 state = 3; 848 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 849 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 850 aprint_error_dev(&sc->sk_dev, "can't load dma map\n"); 851 error = ENOBUFS; 852 goto out; 853 } 854 855 state = 4; 856 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 857 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 858 859 LIST_INIT(&sc_if->sk_jfree_listhead); 860 LIST_INIT(&sc_if->sk_jinuse_listhead); 861 862 /* 863 * Now divide it up into 9K pieces and save the addresses 864 * in an array. 865 */ 866 ptr = sc_if->sk_cdata.sk_jumbo_buf; 867 for (i = 0; i < SK_JSLOTS; i++) { 868 sc_if->sk_cdata.sk_jslots[i] = ptr; 869 ptr += SK_JLEN; 870 entry = malloc(sizeof(struct sk_jpool_entry), 871 M_DEVBUF, M_NOWAIT); 872 if (entry == NULL) { 873 aprint_error_dev(&sc->sk_dev, "no memory for jumbo buffer queue!\n"); 874 error = ENOBUFS; 875 goto out; 876 } 877 entry->slot = i; 878 if (i) 879 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 880 entry, jpool_entries); 881 else 882 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 883 entry, jpool_entries); 884 } 885 out: 886 if (error != 0) { 887 switch (state) { 888 case 4: 889 bus_dmamap_unload(sc->sc_dmatag, 890 sc_if->sk_cdata.sk_rx_jumbo_map); 891 case 3: 892 bus_dmamap_destroy(sc->sc_dmatag, 893 sc_if->sk_cdata.sk_rx_jumbo_map); 894 case 2: 895 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 896 case 1: 897 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 898 break; 899 default: 900 break; 901 } 902 } 903 904 return error; 905 } 906 907 /* 908 * Allocate a jumbo buffer. 909 */ 910 void * 911 sk_jalloc(struct sk_if_softc *sc_if) 912 { 913 struct sk_jpool_entry *entry; 914 915 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 916 917 if (entry == NULL) 918 return NULL; 919 920 LIST_REMOVE(entry, jpool_entries); 921 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 922 return sc_if->sk_cdata.sk_jslots[entry->slot]; 923 } 924 925 /* 926 * Release a jumbo buffer. 927 */ 928 void 929 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 930 { 931 struct sk_jpool_entry *entry; 932 struct sk_if_softc *sc; 933 int i, s; 934 935 /* Extract the softc struct pointer. */ 936 sc = (struct sk_if_softc *)arg; 937 938 if (sc == NULL) 939 panic("sk_jfree: can't find softc pointer!"); 940 941 /* calculate the slot this buffer belongs to */ 942 943 i = ((vaddr_t)buf 944 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 945 946 if ((i < 0) || (i >= SK_JSLOTS)) 947 panic("sk_jfree: asked to free buffer that we don't manage!"); 948 949 s = splvm(); 950 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 951 if (entry == NULL) 952 panic("sk_jfree: buffer not in use!"); 953 entry->slot = i; 954 LIST_REMOVE(entry, jpool_entries); 955 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 956 957 if (__predict_true(m != NULL)) 958 pool_cache_put(mb_cache, m); 959 splx(s); 960 } 961 962 /* 963 * Set media options. 964 */ 965 int 966 sk_ifmedia_upd(struct ifnet *ifp) 967 { 968 struct sk_if_softc *sc_if = ifp->if_softc; 969 int rc; 970 971 (void) sk_init(ifp); 972 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 973 return 0; 974 return rc; 975 } 976 977 int 978 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 979 { 980 struct sk_if_softc *sc_if = ifp->if_softc; 981 struct sk_softc *sc = sc_if->sk_softc; 982 int s, error = 0; 983 984 /* DPRINTFN(2, ("sk_ioctl\n")); */ 985 986 s = splnet(); 987 988 switch (command) { 989 990 case SIOCSIFFLAGS: 991 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 992 if (ifp->if_flags & IFF_UP) { 993 if (ifp->if_flags & IFF_RUNNING && 994 ifp->if_flags & IFF_PROMISC && 995 !(sc_if->sk_if_flags & IFF_PROMISC)) { 996 switch (sc->sk_type) { 997 case SK_GENESIS: 998 SK_XM_SETBIT_4(sc_if, XM_MODE, 999 XM_MODE_RX_PROMISC); 1000 break; 1001 case SK_YUKON: 1002 case SK_YUKON_LITE: 1003 case SK_YUKON_LP: 1004 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1005 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1006 break; 1007 } 1008 sk_setmulti(sc_if); 1009 } else if (ifp->if_flags & IFF_RUNNING && 1010 !(ifp->if_flags & IFF_PROMISC) && 1011 sc_if->sk_if_flags & IFF_PROMISC) { 1012 switch (sc->sk_type) { 1013 case SK_GENESIS: 1014 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1015 XM_MODE_RX_PROMISC); 1016 break; 1017 case SK_YUKON: 1018 case SK_YUKON_LITE: 1019 case SK_YUKON_LP: 1020 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1021 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1022 break; 1023 } 1024 1025 sk_setmulti(sc_if); 1026 } else 1027 (void) sk_init(ifp); 1028 } else { 1029 if (ifp->if_flags & IFF_RUNNING) 1030 sk_stop(ifp,0); 1031 } 1032 sc_if->sk_if_flags = ifp->if_flags; 1033 error = 0; 1034 break; 1035 1036 default: 1037 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1038 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1039 break; 1040 1041 error = 0; 1042 1043 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1044 ; 1045 else if (ifp->if_flags & IFF_RUNNING) { 1046 sk_setmulti(sc_if); 1047 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1048 } 1049 break; 1050 } 1051 1052 splx(s); 1053 return error; 1054 } 1055 1056 void 1057 sk_update_int_mod(struct sk_softc *sc) 1058 { 1059 u_int32_t imtimer_ticks; 1060 1061 /* 1062 * Configure interrupt moderation. The moderation timer 1063 * defers interrupts specified in the interrupt moderation 1064 * timer mask based on the timeout specified in the interrupt 1065 * moderation timer init register. Each bit in the timer 1066 * register represents one tick, so to specify a timeout in 1067 * microseconds, we have to multiply by the correct number of 1068 * ticks-per-microsecond. 1069 */ 1070 switch (sc->sk_type) { 1071 case SK_GENESIS: 1072 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1073 break; 1074 case SK_YUKON_EC: 1075 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1076 break; 1077 default: 1078 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1079 } 1080 aprint_verbose_dev(&sc->sk_dev, "interrupt moderation is %d us\n", 1081 sc->sk_int_mod); 1082 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1083 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1084 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1085 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1086 sc->sk_int_mod_pending = 0; 1087 } 1088 1089 /* 1090 * Lookup: Check the PCI vendor and device, and return a pointer to 1091 * The structure if the IDs match against our list. 1092 */ 1093 1094 static const struct sk_product * 1095 sk_lookup(const struct pci_attach_args *pa) 1096 { 1097 const struct sk_product *psk; 1098 1099 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1100 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1101 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1102 return psk; 1103 } 1104 return NULL; 1105 } 1106 1107 /* 1108 * Probe for a SysKonnect GEnesis chip. 1109 */ 1110 1111 int 1112 skc_probe(struct device *parent, struct cfdata *match, 1113 void *aux) 1114 { 1115 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1116 const struct sk_product *psk; 1117 pcireg_t subid; 1118 1119 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1120 1121 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1122 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1123 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1124 subid == SK_LINKSYS_EG1032_SUBID) 1125 return 1; 1126 1127 if ((psk = sk_lookup(pa))) { 1128 return 1; 1129 } 1130 return 0; 1131 } 1132 1133 /* 1134 * Force the GEnesis into reset, then bring it out of reset. 1135 */ 1136 void sk_reset(struct sk_softc *sc) 1137 { 1138 DPRINTFN(2, ("sk_reset\n")); 1139 1140 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1141 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1142 if (SK_YUKON_FAMILY(sc->sk_type)) 1143 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1144 1145 DELAY(1000); 1146 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1147 DELAY(2); 1148 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1149 if (SK_YUKON_FAMILY(sc->sk_type)) 1150 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1151 1152 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1153 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1154 CSR_READ_2(sc, SK_LINK_CTRL))); 1155 1156 if (sc->sk_type == SK_GENESIS) { 1157 /* Configure packet arbiter */ 1158 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1159 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1160 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1161 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1162 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1163 } 1164 1165 /* Enable RAM interface */ 1166 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1167 1168 sk_update_int_mod(sc); 1169 } 1170 1171 int 1172 sk_probe(struct device *parent, struct cfdata *match, 1173 void *aux) 1174 { 1175 struct skc_attach_args *sa = aux; 1176 1177 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1178 return 0; 1179 1180 return 1; 1181 } 1182 1183 /* 1184 * Each XMAC chip is attached as a separate logical IP interface. 1185 * Single port cards will have only one logical interface of course. 1186 */ 1187 void 1188 sk_attach(struct device *parent, struct device *self, void *aux) 1189 { 1190 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1191 struct sk_softc *sc = (struct sk_softc *)parent; 1192 struct skc_attach_args *sa = aux; 1193 struct sk_txmap_entry *entry; 1194 struct ifnet *ifp; 1195 bus_dma_segment_t seg; 1196 bus_dmamap_t dmamap; 1197 void *kva; 1198 int i, rseg; 1199 1200 aprint_naive("\n"); 1201 1202 sc_if->sk_port = sa->skc_port; 1203 sc_if->sk_softc = sc; 1204 sc->sk_if[sa->skc_port] = sc_if; 1205 1206 if (sa->skc_port == SK_PORT_A) 1207 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1208 if (sa->skc_port == SK_PORT_B) 1209 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1210 1211 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1212 1213 /* 1214 * Get station address for this interface. Note that 1215 * dual port cards actually come with three station 1216 * addresses: one for each port, plus an extra. The 1217 * extra one is used by the SysKonnect driver software 1218 * as a 'virtual' station address for when both ports 1219 * are operating in failover mode. Currently we don't 1220 * use this extra address. 1221 */ 1222 for (i = 0; i < ETHER_ADDR_LEN; i++) 1223 sc_if->sk_enaddr[i] = 1224 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1225 1226 1227 aprint_normal(": Ethernet address %s\n", 1228 ether_sprintf(sc_if->sk_enaddr)); 1229 1230 /* 1231 * Set up RAM buffer addresses. The NIC will have a certain 1232 * amount of SRAM on it, somewhere between 512K and 2MB. We 1233 * need to divide this up a) between the transmitter and 1234 * receiver and b) between the two XMACs, if this is a 1235 * dual port NIC. Our algorithm is to divide up the memory 1236 * evenly so that everyone gets a fair share. 1237 */ 1238 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1239 u_int32_t chunk, val; 1240 1241 chunk = sc->sk_ramsize / 2; 1242 val = sc->sk_rboff / sizeof(u_int64_t); 1243 sc_if->sk_rx_ramstart = val; 1244 val += (chunk / sizeof(u_int64_t)); 1245 sc_if->sk_rx_ramend = val - 1; 1246 sc_if->sk_tx_ramstart = val; 1247 val += (chunk / sizeof(u_int64_t)); 1248 sc_if->sk_tx_ramend = val - 1; 1249 } else { 1250 u_int32_t chunk, val; 1251 1252 chunk = sc->sk_ramsize / 4; 1253 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1254 sizeof(u_int64_t); 1255 sc_if->sk_rx_ramstart = val; 1256 val += (chunk / sizeof(u_int64_t)); 1257 sc_if->sk_rx_ramend = val - 1; 1258 sc_if->sk_tx_ramstart = val; 1259 val += (chunk / sizeof(u_int64_t)); 1260 sc_if->sk_tx_ramend = val - 1; 1261 } 1262 1263 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1264 " tx_ramstart=%#x tx_ramend=%#x\n", 1265 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1266 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1267 1268 /* Read and save PHY type and set PHY address */ 1269 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1270 switch (sc_if->sk_phytype) { 1271 case SK_PHYTYPE_XMAC: 1272 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1273 break; 1274 case SK_PHYTYPE_BCOM: 1275 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1276 break; 1277 case SK_PHYTYPE_MARV_COPPER: 1278 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1279 break; 1280 default: 1281 aprint_error_dev(&sc->sk_dev, "unsupported PHY type: %d\n", 1282 sc_if->sk_phytype); 1283 return; 1284 } 1285 1286 /* Allocate the descriptor queues. */ 1287 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1288 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1289 aprint_error_dev(&sc->sk_dev, "can't alloc rx buffers\n"); 1290 goto fail; 1291 } 1292 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1293 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1294 aprint_error_dev(&sc_if->sk_dev, "can't map dma buffers (%lu bytes)\n", 1295 (u_long) sizeof(struct sk_ring_data)); 1296 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1297 goto fail; 1298 } 1299 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1300 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1301 &sc_if->sk_ring_map)) { 1302 aprint_error_dev(&sc_if->sk_dev, "can't create dma map\n"); 1303 bus_dmamem_unmap(sc->sc_dmatag, kva, 1304 sizeof(struct sk_ring_data)); 1305 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1306 goto fail; 1307 } 1308 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1309 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1310 aprint_error_dev(&sc_if->sk_dev, "can't load dma map\n"); 1311 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1312 bus_dmamem_unmap(sc->sc_dmatag, kva, 1313 sizeof(struct sk_ring_data)); 1314 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1315 goto fail; 1316 } 1317 1318 for (i = 0; i < SK_RX_RING_CNT; i++) 1319 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1320 1321 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1322 for (i = 0; i < SK_TX_RING_CNT; i++) { 1323 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1324 1325 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1326 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1327 aprint_error_dev(&sc_if->sk_dev, "Can't create TX dmamap\n"); 1328 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1329 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1330 bus_dmamem_unmap(sc->sc_dmatag, kva, 1331 sizeof(struct sk_ring_data)); 1332 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1333 goto fail; 1334 } 1335 1336 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1337 if (!entry) { 1338 aprint_error_dev(&sc_if->sk_dev, "Can't alloc txmap entry\n"); 1339 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1340 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1341 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1342 bus_dmamem_unmap(sc->sc_dmatag, kva, 1343 sizeof(struct sk_ring_data)); 1344 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1345 goto fail; 1346 } 1347 entry->dmamap = dmamap; 1348 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1349 } 1350 1351 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1352 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1353 1354 ifp = &sc_if->sk_ethercom.ec_if; 1355 /* Try to allocate memory for jumbo buffers. */ 1356 if (sk_alloc_jumbo_mem(sc_if)) { 1357 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1358 goto fail; 1359 } 1360 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1361 | ETHERCAP_JUMBO_MTU; 1362 1363 ifp->if_softc = sc_if; 1364 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1365 ifp->if_ioctl = sk_ioctl; 1366 ifp->if_start = sk_start; 1367 ifp->if_stop = sk_stop; 1368 ifp->if_init = sk_init; 1369 ifp->if_watchdog = sk_watchdog; 1370 ifp->if_capabilities = 0; 1371 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1372 IFQ_SET_READY(&ifp->if_snd); 1373 strlcpy(ifp->if_xname, device_xname(&sc_if->sk_dev), IFNAMSIZ); 1374 1375 /* 1376 * Do miibus setup. 1377 */ 1378 switch (sc->sk_type) { 1379 case SK_GENESIS: 1380 sk_init_xmac(sc_if); 1381 break; 1382 case SK_YUKON: 1383 case SK_YUKON_LITE: 1384 case SK_YUKON_LP: 1385 sk_init_yukon(sc_if); 1386 break; 1387 default: 1388 aprint_error_dev(&sc->sk_dev, "unknown device type %d\n", 1389 sc->sk_type); 1390 goto fail; 1391 } 1392 1393 DPRINTFN(2, ("sk_attach: 1\n")); 1394 1395 sc_if->sk_mii.mii_ifp = ifp; 1396 switch (sc->sk_type) { 1397 case SK_GENESIS: 1398 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1399 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1400 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1401 break; 1402 case SK_YUKON: 1403 case SK_YUKON_LITE: 1404 case SK_YUKON_LP: 1405 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1406 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1407 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1408 break; 1409 } 1410 1411 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1412 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1413 sk_ifmedia_upd, ether_mediastatus); 1414 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1415 MII_OFFSET_ANY, 0); 1416 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1417 aprint_error_dev(&sc_if->sk_dev, "no PHY found!\n"); 1418 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1419 0, NULL); 1420 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1421 } else 1422 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1423 1424 callout_init(&sc_if->sk_tick_ch, 0); 1425 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1426 1427 DPRINTFN(2, ("sk_attach: 1\n")); 1428 1429 /* 1430 * Call MI attach routines. 1431 */ 1432 if_attach(ifp); 1433 1434 ether_ifattach(ifp, sc_if->sk_enaddr); 1435 1436 #if NRND > 0 1437 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sk_dev), 1438 RND_TYPE_NET, 0); 1439 #endif 1440 1441 DPRINTFN(2, ("sk_attach: end\n")); 1442 1443 return; 1444 1445 fail: 1446 sc->sk_if[sa->skc_port] = NULL; 1447 } 1448 1449 int 1450 skcprint(void *aux, const char *pnp) 1451 { 1452 struct skc_attach_args *sa = aux; 1453 1454 if (pnp) 1455 aprint_normal("sk port %c at %s", 1456 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1457 else 1458 aprint_normal(" port %c", 1459 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1460 return UNCONF; 1461 } 1462 1463 /* 1464 * Attach the interface. Allocate softc structures, do ifmedia 1465 * setup and ethernet/BPF attach. 1466 */ 1467 void 1468 skc_attach(struct device *parent, struct device *self, void *aux) 1469 { 1470 struct sk_softc *sc = (struct sk_softc *)self; 1471 struct pci_attach_args *pa = aux; 1472 struct skc_attach_args skca; 1473 pci_chipset_tag_t pc = pa->pa_pc; 1474 #ifndef SK_USEIOSPACE 1475 pcireg_t memtype; 1476 #endif 1477 pci_intr_handle_t ih; 1478 const char *intrstr = NULL; 1479 bus_addr_t iobase; 1480 bus_size_t iosize; 1481 int rc, sk_nodenum; 1482 u_int32_t command; 1483 const char *revstr; 1484 const struct sysctlnode *node; 1485 1486 aprint_naive("\n"); 1487 1488 DPRINTFN(2, ("begin skc_attach\n")); 1489 1490 /* 1491 * Handle power management nonsense. 1492 */ 1493 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1494 1495 if (command == 0x01) { 1496 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1497 if (command & SK_PSTATE_MASK) { 1498 u_int32_t xiobase, membase, irq; 1499 1500 /* Save important PCI config data. */ 1501 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1502 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1503 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1504 1505 /* Reset the power state. */ 1506 aprint_normal_dev(&sc->sk_dev, "chip is in D%d power mode " 1507 "-- setting to D0\n", 1508 command & SK_PSTATE_MASK); 1509 command &= 0xFFFFFFFC; 1510 pci_conf_write(pc, pa->pa_tag, 1511 SK_PCI_PWRMGMTCTRL, command); 1512 1513 /* Restore PCI config data. */ 1514 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1515 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1516 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1517 } 1518 } 1519 1520 /* 1521 * Map control/status registers. 1522 */ 1523 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1524 command |= PCI_COMMAND_IO_ENABLE | 1525 PCI_COMMAND_MEM_ENABLE | 1526 PCI_COMMAND_MASTER_ENABLE; 1527 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1528 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1529 1530 #ifdef SK_USEIOSPACE 1531 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1532 aprint_error(": failed to enable I/O ports!\n"); 1533 return; 1534 } 1535 /* 1536 * Map control/status registers. 1537 */ 1538 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1539 &sc->sk_btag, &sc->sk_bhandle, 1540 &iobase, &iosize)) { 1541 aprint_error(": can't find i/o space\n"); 1542 return; 1543 } 1544 #else 1545 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1546 aprint_error(": failed to enable memory mapping!\n"); 1547 return; 1548 } 1549 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1550 switch (memtype) { 1551 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1552 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1553 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1554 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1555 &iobase, &iosize) == 0) 1556 break; 1557 default: 1558 aprint_error_dev(&sc->sk_dev, "can't find mem space\n"); 1559 return; 1560 } 1561 1562 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1563 #endif 1564 sc->sc_dmatag = pa->pa_dmat; 1565 1566 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1567 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1568 1569 /* bail out here if chip is not recognized */ 1570 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1571 aprint_error_dev(&sc->sk_dev, "unknown chip type\n"); 1572 goto fail; 1573 } 1574 if (SK_IS_YUKON2(sc)) { 1575 aprint_error_dev(&sc->sk_dev, "Does not support Yukon2--try msk(4).\n"); 1576 goto fail; 1577 } 1578 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1579 1580 /* Allocate interrupt */ 1581 if (pci_intr_map(pa, &ih)) { 1582 aprint_error(": couldn't map interrupt\n"); 1583 goto fail; 1584 } 1585 1586 intrstr = pci_intr_string(pc, ih); 1587 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1588 if (sc->sk_intrhand == NULL) { 1589 aprint_error(": couldn't establish interrupt"); 1590 if (intrstr != NULL) 1591 aprint_normal(" at %s", intrstr); 1592 goto fail; 1593 } 1594 aprint_normal(": %s\n", intrstr); 1595 1596 /* Reset the adapter. */ 1597 sk_reset(sc); 1598 1599 /* Read and save vital product data from EEPROM. */ 1600 sk_vpd_read(sc); 1601 1602 if (sc->sk_type == SK_GENESIS) { 1603 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1604 /* Read and save RAM size and RAMbuffer offset */ 1605 switch (val) { 1606 case SK_RAMSIZE_512K_64: 1607 sc->sk_ramsize = 0x80000; 1608 sc->sk_rboff = SK_RBOFF_0; 1609 break; 1610 case SK_RAMSIZE_1024K_64: 1611 sc->sk_ramsize = 0x100000; 1612 sc->sk_rboff = SK_RBOFF_80000; 1613 break; 1614 case SK_RAMSIZE_1024K_128: 1615 sc->sk_ramsize = 0x100000; 1616 sc->sk_rboff = SK_RBOFF_0; 1617 break; 1618 case SK_RAMSIZE_2048K_128: 1619 sc->sk_ramsize = 0x200000; 1620 sc->sk_rboff = SK_RBOFF_0; 1621 break; 1622 default: 1623 aprint_error_dev(&sc->sk_dev, "unknown ram size: %d\n", 1624 val); 1625 goto fail_1; 1626 break; 1627 } 1628 1629 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1630 sc->sk_ramsize, sc->sk_ramsize / 1024, 1631 sc->sk_rboff)); 1632 } else { 1633 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1634 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1635 sc->sk_rboff = SK_RBOFF_0; 1636 1637 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1638 sc->sk_ramsize / 1024, sc->sk_ramsize, 1639 sc->sk_rboff)); 1640 } 1641 1642 /* Read and save physical media type */ 1643 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1644 case SK_PMD_1000BASESX: 1645 sc->sk_pmd = IFM_1000_SX; 1646 break; 1647 case SK_PMD_1000BASELX: 1648 sc->sk_pmd = IFM_1000_LX; 1649 break; 1650 case SK_PMD_1000BASECX: 1651 sc->sk_pmd = IFM_1000_CX; 1652 break; 1653 case SK_PMD_1000BASETX: 1654 case SK_PMD_1000BASETX_ALT: 1655 sc->sk_pmd = IFM_1000_T; 1656 break; 1657 default: 1658 aprint_error_dev(&sc->sk_dev, "unknown media type: 0x%x\n", 1659 sk_win_read_1(sc, SK_PMDTYPE)); 1660 goto fail_1; 1661 } 1662 1663 /* determine whether to name it with vpd or just make it up */ 1664 /* Marvell Yukon VPD's can freqently be bogus */ 1665 1666 switch (pa->pa_id) { 1667 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1668 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1669 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1670 case PCI_PRODUCT_3COM_3C940: 1671 case PCI_PRODUCT_DLINK_DGE530T: 1672 case PCI_PRODUCT_DLINK_DGE560T: 1673 case PCI_PRODUCT_DLINK_DGE560T_2: 1674 case PCI_PRODUCT_LINKSYS_EG1032: 1675 case PCI_PRODUCT_LINKSYS_EG1064: 1676 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1677 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1678 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1679 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1680 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1681 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1682 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1683 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1684 sc->sk_name = sc->sk_vpd_prodname; 1685 break; 1686 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1687 /* whoops yukon vpd prodname bears no resemblance to reality */ 1688 switch (sc->sk_type) { 1689 case SK_GENESIS: 1690 sc->sk_name = sc->sk_vpd_prodname; 1691 break; 1692 case SK_YUKON: 1693 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1694 break; 1695 case SK_YUKON_LITE: 1696 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1697 break; 1698 case SK_YUKON_LP: 1699 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1700 break; 1701 default: 1702 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1703 } 1704 1705 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1706 1707 if ( sc->sk_type == SK_YUKON ) { 1708 uint32_t flashaddr; 1709 uint8_t testbyte; 1710 1711 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1712 1713 /* test Flash-Address Register */ 1714 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1715 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1716 1717 if (testbyte != 0) { 1718 /* this is yukon lite Rev. A0 */ 1719 sc->sk_type = SK_YUKON_LITE; 1720 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1721 /* restore Flash-Address Register */ 1722 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1723 } 1724 } 1725 break; 1726 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1727 sc->sk_name = sc->sk_vpd_prodname; 1728 break; 1729 default: 1730 sc->sk_name = "Unknown Marvell"; 1731 } 1732 1733 1734 if ( sc->sk_type == SK_YUKON_LITE ) { 1735 switch (sc->sk_rev) { 1736 case SK_YUKON_LITE_REV_A0: 1737 revstr = "A0"; 1738 break; 1739 case SK_YUKON_LITE_REV_A1: 1740 revstr = "A1"; 1741 break; 1742 case SK_YUKON_LITE_REV_A3: 1743 revstr = "A3"; 1744 break; 1745 default: 1746 revstr = ""; 1747 } 1748 } else { 1749 revstr = ""; 1750 } 1751 1752 /* Announce the product name. */ 1753 aprint_normal_dev(&sc->sk_dev, "%s rev. %s(0x%x)\n", 1754 sc->sk_name, revstr, sc->sk_rev); 1755 1756 skca.skc_port = SK_PORT_A; 1757 (void)config_found(&sc->sk_dev, &skca, skcprint); 1758 1759 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1760 skca.skc_port = SK_PORT_B; 1761 (void)config_found(&sc->sk_dev, &skca, skcprint); 1762 } 1763 1764 /* Turn on the 'driver is loaded' LED. */ 1765 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1766 1767 /* skc sysctl setup */ 1768 1769 sc->sk_int_mod = SK_IM_DEFAULT; 1770 sc->sk_int_mod_pending = 0; 1771 1772 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1773 0, CTLTYPE_NODE, device_xname(&sc->sk_dev), 1774 SYSCTL_DESCR("skc per-controller controls"), 1775 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1776 CTL_EOL)) != 0) { 1777 aprint_normal_dev(&sc->sk_dev, "couldn't create sysctl node\n"); 1778 goto fail_1; 1779 } 1780 1781 sk_nodenum = node->sysctl_num; 1782 1783 /* interrupt moderation time in usecs */ 1784 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1785 CTLFLAG_READWRITE, 1786 CTLTYPE_INT, "int_mod", 1787 SYSCTL_DESCR("sk interrupt moderation timer"), 1788 sk_sysctl_handler, 0, sc, 1789 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1790 CTL_EOL)) != 0) { 1791 aprint_normal_dev(&sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1792 goto fail_1; 1793 } 1794 1795 return; 1796 1797 fail_1: 1798 pci_intr_disestablish(pc, sc->sk_intrhand); 1799 fail: 1800 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1801 } 1802 1803 int 1804 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1805 { 1806 struct sk_softc *sc = sc_if->sk_softc; 1807 struct sk_tx_desc *f = NULL; 1808 u_int32_t frag, cur, cnt = 0, sk_ctl; 1809 int i; 1810 struct sk_txmap_entry *entry; 1811 bus_dmamap_t txmap; 1812 1813 DPRINTFN(3, ("sk_encap\n")); 1814 1815 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1816 if (entry == NULL) { 1817 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1818 return ENOBUFS; 1819 } 1820 txmap = entry->dmamap; 1821 1822 cur = frag = *txidx; 1823 1824 #ifdef SK_DEBUG 1825 if (skdebug >= 3) 1826 sk_dump_mbuf(m_head); 1827 #endif 1828 1829 /* 1830 * Start packing the mbufs in this chain into 1831 * the fragment pointers. Stop when we run out 1832 * of fragments or hit the end of the mbuf chain. 1833 */ 1834 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1835 BUS_DMA_NOWAIT)) { 1836 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1837 return ENOBUFS; 1838 } 1839 1840 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1841 1842 /* Sync the DMA map. */ 1843 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1844 BUS_DMASYNC_PREWRITE); 1845 1846 for (i = 0; i < txmap->dm_nsegs; i++) { 1847 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1848 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1849 return ENOBUFS; 1850 } 1851 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1852 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1853 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1854 if (cnt == 0) 1855 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1856 else 1857 sk_ctl |= SK_TXCTL_OWN; 1858 f->sk_ctl = htole32(sk_ctl); 1859 cur = frag; 1860 SK_INC(frag, SK_TX_RING_CNT); 1861 cnt++; 1862 } 1863 1864 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1865 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1866 1867 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1868 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1869 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1870 1871 /* Sync descriptors before handing to chip */ 1872 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1873 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1874 1875 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1876 htole32(SK_TXCTL_OWN); 1877 1878 /* Sync first descriptor to hand it off */ 1879 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1880 1881 sc_if->sk_cdata.sk_tx_cnt += cnt; 1882 1883 #ifdef SK_DEBUG 1884 if (skdebug >= 3) { 1885 struct sk_tx_desc *desc; 1886 u_int32_t idx; 1887 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1888 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1889 sk_dump_txdesc(desc, idx); 1890 } 1891 } 1892 #endif 1893 1894 *txidx = frag; 1895 1896 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1897 1898 return 0; 1899 } 1900 1901 void 1902 sk_start(struct ifnet *ifp) 1903 { 1904 struct sk_if_softc *sc_if = ifp->if_softc; 1905 struct sk_softc *sc = sc_if->sk_softc; 1906 struct mbuf *m_head = NULL; 1907 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1908 int pkts = 0; 1909 1910 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1911 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1912 1913 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1914 IFQ_POLL(&ifp->if_snd, m_head); 1915 if (m_head == NULL) 1916 break; 1917 1918 /* 1919 * Pack the data into the transmit ring. If we 1920 * don't have room, set the OACTIVE flag and wait 1921 * for the NIC to drain the ring. 1922 */ 1923 if (sk_encap(sc_if, m_head, &idx)) { 1924 ifp->if_flags |= IFF_OACTIVE; 1925 break; 1926 } 1927 1928 /* now we are committed to transmit the packet */ 1929 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1930 pkts++; 1931 1932 /* 1933 * If there's a BPF listener, bounce a copy of this frame 1934 * to him. 1935 */ 1936 #if NBPFILTER > 0 1937 if (ifp->if_bpf) 1938 bpf_mtap(ifp->if_bpf, m_head); 1939 #endif 1940 } 1941 if (pkts == 0) 1942 return; 1943 1944 /* Transmit */ 1945 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1946 sc_if->sk_cdata.sk_tx_prod = idx; 1947 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1948 1949 /* Set a timeout in case the chip goes out to lunch. */ 1950 ifp->if_timer = 5; 1951 } 1952 } 1953 1954 1955 void 1956 sk_watchdog(struct ifnet *ifp) 1957 { 1958 struct sk_if_softc *sc_if = ifp->if_softc; 1959 1960 /* 1961 * Reclaim first as there is a possibility of losing Tx completion 1962 * interrupts. 1963 */ 1964 sk_txeof(sc_if); 1965 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1966 aprint_error_dev(&sc_if->sk_dev, "watchdog timeout\n"); 1967 1968 ifp->if_oerrors++; 1969 1970 sk_init(ifp); 1971 } 1972 } 1973 1974 void 1975 sk_shutdown(void *v) 1976 { 1977 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1978 struct sk_softc *sc = sc_if->sk_softc; 1979 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1980 1981 DPRINTFN(2, ("sk_shutdown\n")); 1982 sk_stop(ifp,1); 1983 1984 /* Turn off the 'driver is loaded' LED. */ 1985 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1986 1987 /* 1988 * Reset the GEnesis controller. Doing this should also 1989 * assert the resets on the attached XMAC(s). 1990 */ 1991 sk_reset(sc); 1992 } 1993 1994 void 1995 sk_rxeof(struct sk_if_softc *sc_if) 1996 { 1997 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1998 struct mbuf *m; 1999 struct sk_chain *cur_rx; 2000 struct sk_rx_desc *cur_desc; 2001 int i, cur, total_len = 0; 2002 u_int32_t rxstat, sk_ctl; 2003 bus_dmamap_t dmamap; 2004 2005 i = sc_if->sk_cdata.sk_rx_prod; 2006 2007 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2008 2009 for (;;) { 2010 cur = i; 2011 2012 /* Sync the descriptor */ 2013 SK_CDRXSYNC(sc_if, cur, 2014 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2015 2016 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2017 if (sk_ctl & SK_RXCTL_OWN) { 2018 /* Invalidate the descriptor -- it's not ready yet */ 2019 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2020 sc_if->sk_cdata.sk_rx_prod = i; 2021 break; 2022 } 2023 2024 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2025 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2026 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2027 2028 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2029 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2030 2031 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2032 m = cur_rx->sk_mbuf; 2033 cur_rx->sk_mbuf = NULL; 2034 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2035 2036 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2037 2038 SK_INC(i, SK_RX_RING_CNT); 2039 2040 if (rxstat & XM_RXSTAT_ERRFRAME) { 2041 ifp->if_ierrors++; 2042 sk_newbuf(sc_if, cur, m, dmamap); 2043 continue; 2044 } 2045 2046 /* 2047 * Try to allocate a new jumbo buffer. If that 2048 * fails, copy the packet to mbufs and put the 2049 * jumbo buffer back in the ring so it can be 2050 * re-used. If allocating mbufs fails, then we 2051 * have to drop the packet. 2052 */ 2053 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2054 struct mbuf *m0; 2055 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2056 total_len + ETHER_ALIGN, 0, ifp, NULL); 2057 sk_newbuf(sc_if, cur, m, dmamap); 2058 if (m0 == NULL) { 2059 aprint_error_dev(&sc_if->sk_dev, "no receive buffers " 2060 "available -- packet dropped!\n"); 2061 ifp->if_ierrors++; 2062 continue; 2063 } 2064 m_adj(m0, ETHER_ALIGN); 2065 m = m0; 2066 } else { 2067 m->m_pkthdr.rcvif = ifp; 2068 m->m_pkthdr.len = m->m_len = total_len; 2069 } 2070 2071 ifp->if_ipackets++; 2072 2073 #if NBPFILTER > 0 2074 if (ifp->if_bpf) 2075 bpf_mtap(ifp->if_bpf, m); 2076 #endif 2077 /* pass it on. */ 2078 (*ifp->if_input)(ifp, m); 2079 } 2080 } 2081 2082 void 2083 sk_txeof(struct sk_if_softc *sc_if) 2084 { 2085 struct sk_softc *sc = sc_if->sk_softc; 2086 struct sk_tx_desc *cur_tx; 2087 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2088 u_int32_t idx, sk_ctl; 2089 struct sk_txmap_entry *entry; 2090 2091 DPRINTFN(3, ("sk_txeof\n")); 2092 2093 /* 2094 * Go through our tx ring and free mbufs for those 2095 * frames that have been sent. 2096 */ 2097 idx = sc_if->sk_cdata.sk_tx_cons; 2098 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2099 SK_CDTXSYNC(sc_if, idx, 1, 2100 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2101 2102 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2103 sk_ctl = le32toh(cur_tx->sk_ctl); 2104 #ifdef SK_DEBUG 2105 if (skdebug >= 3) 2106 sk_dump_txdesc(cur_tx, idx); 2107 #endif 2108 if (sk_ctl & SK_TXCTL_OWN) { 2109 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2110 break; 2111 } 2112 if (sk_ctl & SK_TXCTL_LASTFRAG) 2113 ifp->if_opackets++; 2114 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2115 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2116 2117 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2118 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2119 2120 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2121 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2122 2123 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2124 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2125 link); 2126 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2127 } 2128 sc_if->sk_cdata.sk_tx_cnt--; 2129 SK_INC(idx, SK_TX_RING_CNT); 2130 } 2131 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2132 ifp->if_timer = 0; 2133 else /* nudge chip to keep tx ring moving */ 2134 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2135 2136 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2137 ifp->if_flags &= ~IFF_OACTIVE; 2138 2139 sc_if->sk_cdata.sk_tx_cons = idx; 2140 } 2141 2142 void 2143 sk_tick(void *xsc_if) 2144 { 2145 struct sk_if_softc *sc_if = xsc_if; 2146 struct mii_data *mii = &sc_if->sk_mii; 2147 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2148 int i; 2149 2150 DPRINTFN(3, ("sk_tick\n")); 2151 2152 if (!(ifp->if_flags & IFF_UP)) 2153 return; 2154 2155 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2156 sk_intr_bcom(sc_if); 2157 return; 2158 } 2159 2160 /* 2161 * According to SysKonnect, the correct way to verify that 2162 * the link has come back up is to poll bit 0 of the GPIO 2163 * register three times. This pin has the signal from the 2164 * link sync pin connected to it; if we read the same link 2165 * state 3 times in a row, we know the link is up. 2166 */ 2167 for (i = 0; i < 3; i++) { 2168 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2169 break; 2170 } 2171 2172 if (i != 3) { 2173 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2174 return; 2175 } 2176 2177 /* Turn the GP0 interrupt back on. */ 2178 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2179 SK_XM_READ_2(sc_if, XM_ISR); 2180 mii_tick(mii); 2181 mii_pollstat(mii); 2182 callout_stop(&sc_if->sk_tick_ch); 2183 } 2184 2185 void 2186 sk_intr_bcom(struct sk_if_softc *sc_if) 2187 { 2188 struct mii_data *mii = &sc_if->sk_mii; 2189 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2190 int status; 2191 2192 2193 DPRINTFN(3, ("sk_intr_bcom\n")); 2194 2195 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2196 2197 /* 2198 * Read the PHY interrupt register to make sure 2199 * we clear any pending interrupts. 2200 */ 2201 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2202 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2203 2204 if (!(ifp->if_flags & IFF_RUNNING)) { 2205 sk_init_xmac(sc_if); 2206 return; 2207 } 2208 2209 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2210 int lstat; 2211 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2212 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2213 2214 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2215 (void)mii_mediachg(mii); 2216 /* Turn off the link LED. */ 2217 SK_IF_WRITE_1(sc_if, 0, 2218 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2219 sc_if->sk_link = 0; 2220 } else if (status & BRGPHY_ISR_LNK_CHG) { 2221 sk_xmac_miibus_writereg((struct device *)sc_if, 2222 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2223 mii_tick(mii); 2224 sc_if->sk_link = 1; 2225 /* Turn on the link LED. */ 2226 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2227 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2228 SK_LINKLED_BLINK_OFF); 2229 mii_pollstat(mii); 2230 } else { 2231 mii_tick(mii); 2232 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2233 } 2234 } 2235 2236 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2237 } 2238 2239 void 2240 sk_intr_xmac(struct sk_if_softc *sc_if) 2241 { 2242 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2243 2244 DPRINTFN(3, ("sk_intr_xmac\n")); 2245 2246 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2247 if (status & XM_ISR_GP0_SET) { 2248 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2249 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2250 } 2251 2252 if (status & XM_ISR_AUTONEG_DONE) { 2253 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2254 } 2255 } 2256 2257 if (status & XM_IMR_TX_UNDERRUN) 2258 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2259 2260 if (status & XM_IMR_RX_OVERRUN) 2261 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2262 } 2263 2264 void 2265 sk_intr_yukon(struct sk_if_softc *sc_if) 2266 { 2267 int status; 2268 2269 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2270 2271 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2272 } 2273 2274 int 2275 sk_intr(void *xsc) 2276 { 2277 struct sk_softc *sc = xsc; 2278 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2279 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2280 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2281 u_int32_t status; 2282 int claimed = 0; 2283 2284 if (sc_if0 != NULL) 2285 ifp0 = &sc_if0->sk_ethercom.ec_if; 2286 if (sc_if1 != NULL) 2287 ifp1 = &sc_if1->sk_ethercom.ec_if; 2288 2289 for (;;) { 2290 status = CSR_READ_4(sc, SK_ISSR); 2291 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2292 2293 if (!(status & sc->sk_intrmask)) 2294 break; 2295 2296 claimed = 1; 2297 2298 /* Handle receive interrupts first. */ 2299 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2300 sk_rxeof(sc_if0); 2301 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2302 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2303 } 2304 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2305 sk_rxeof(sc_if1); 2306 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2307 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2308 } 2309 2310 /* Then transmit interrupts. */ 2311 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2312 sk_txeof(sc_if0); 2313 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2314 SK_TXBMU_CLR_IRQ_EOF); 2315 } 2316 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2317 sk_txeof(sc_if1); 2318 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2319 SK_TXBMU_CLR_IRQ_EOF); 2320 } 2321 2322 /* Then MAC interrupts. */ 2323 if (sc_if0 && (status & SK_ISR_MAC1) && 2324 (ifp0->if_flags & IFF_RUNNING)) { 2325 if (sc->sk_type == SK_GENESIS) 2326 sk_intr_xmac(sc_if0); 2327 else 2328 sk_intr_yukon(sc_if0); 2329 } 2330 2331 if (sc_if1 && (status & SK_ISR_MAC2) && 2332 (ifp1->if_flags & IFF_RUNNING)) { 2333 if (sc->sk_type == SK_GENESIS) 2334 sk_intr_xmac(sc_if1); 2335 else 2336 sk_intr_yukon(sc_if1); 2337 2338 } 2339 2340 if (status & SK_ISR_EXTERNAL_REG) { 2341 if (sc_if0 != NULL && 2342 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2343 sk_intr_bcom(sc_if0); 2344 2345 if (sc_if1 != NULL && 2346 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2347 sk_intr_bcom(sc_if1); 2348 } 2349 } 2350 2351 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2352 2353 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2354 sk_start(ifp0); 2355 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2356 sk_start(ifp1); 2357 2358 #if NRND > 0 2359 if (RND_ENABLED(&sc->rnd_source)) 2360 rnd_add_uint32(&sc->rnd_source, status); 2361 #endif 2362 2363 if (sc->sk_int_mod_pending) 2364 sk_update_int_mod(sc); 2365 2366 return claimed; 2367 } 2368 2369 void 2370 sk_init_xmac(struct sk_if_softc *sc_if) 2371 { 2372 struct sk_softc *sc = sc_if->sk_softc; 2373 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2374 static const struct sk_bcom_hack bhack[] = { 2375 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2376 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2377 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2378 { 0, 0 } }; 2379 2380 DPRINTFN(1, ("sk_init_xmac\n")); 2381 2382 /* Unreset the XMAC. */ 2383 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2384 DELAY(1000); 2385 2386 /* Reset the XMAC's internal state. */ 2387 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2388 2389 /* Save the XMAC II revision */ 2390 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2391 2392 /* 2393 * Perform additional initialization for external PHYs, 2394 * namely for the 1000baseTX cards that use the XMAC's 2395 * GMII mode. 2396 */ 2397 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2398 int i = 0; 2399 u_int32_t val; 2400 2401 /* Take PHY out of reset. */ 2402 val = sk_win_read_4(sc, SK_GPIO); 2403 if (sc_if->sk_port == SK_PORT_A) 2404 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2405 else 2406 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2407 sk_win_write_4(sc, SK_GPIO, val); 2408 2409 /* Enable GMII mode on the XMAC. */ 2410 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2411 2412 sk_xmac_miibus_writereg((struct device *)sc_if, 2413 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2414 DELAY(10000); 2415 sk_xmac_miibus_writereg((struct device *)sc_if, 2416 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2417 2418 /* 2419 * Early versions of the BCM5400 apparently have 2420 * a bug that requires them to have their reserved 2421 * registers initialized to some magic values. I don't 2422 * know what the numbers do, I'm just the messenger. 2423 */ 2424 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2425 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2426 while (bhack[i].reg) { 2427 sk_xmac_miibus_writereg((struct device *)sc_if, 2428 SK_PHYADDR_BCOM, bhack[i].reg, 2429 bhack[i].val); 2430 i++; 2431 } 2432 } 2433 } 2434 2435 /* Set station address */ 2436 SK_XM_WRITE_2(sc_if, XM_PAR0, 2437 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2438 SK_XM_WRITE_2(sc_if, XM_PAR1, 2439 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2440 SK_XM_WRITE_2(sc_if, XM_PAR2, 2441 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2442 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2443 2444 if (ifp->if_flags & IFF_PROMISC) 2445 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2446 else 2447 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2448 2449 if (ifp->if_flags & IFF_BROADCAST) 2450 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2451 else 2452 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2453 2454 /* We don't need the FCS appended to the packet. */ 2455 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2456 2457 /* We want short frames padded to 60 bytes. */ 2458 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2459 2460 /* 2461 * Enable the reception of all error frames. This is is 2462 * a necessary evil due to the design of the XMAC. The 2463 * XMAC's receive FIFO is only 8K in size, however jumbo 2464 * frames can be up to 9000 bytes in length. When bad 2465 * frame filtering is enabled, the XMAC's RX FIFO operates 2466 * in 'store and forward' mode. For this to work, the 2467 * entire frame has to fit into the FIFO, but that means 2468 * that jumbo frames larger than 8192 bytes will be 2469 * truncated. Disabling all bad frame filtering causes 2470 * the RX FIFO to operate in streaming mode, in which 2471 * case the XMAC will start transfering frames out of the 2472 * RX FIFO as soon as the FIFO threshold is reached. 2473 */ 2474 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2475 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2476 XM_MODE_RX_INRANGELEN); 2477 2478 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2479 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2480 else 2481 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2482 2483 /* 2484 * Bump up the transmit threshold. This helps hold off transmit 2485 * underruns when we're blasting traffic from both ports at once. 2486 */ 2487 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2488 2489 /* Set multicast filter */ 2490 sk_setmulti(sc_if); 2491 2492 /* Clear and enable interrupts */ 2493 SK_XM_READ_2(sc_if, XM_ISR); 2494 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2495 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2496 else 2497 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2498 2499 /* Configure MAC arbiter */ 2500 switch (sc_if->sk_xmac_rev) { 2501 case XM_XMAC_REV_B2: 2502 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2503 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2504 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2505 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2506 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2507 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2508 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2509 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2510 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2511 break; 2512 case XM_XMAC_REV_C1: 2513 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2514 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2515 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2516 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2517 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2518 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2519 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2520 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2521 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2522 break; 2523 default: 2524 break; 2525 } 2526 sk_win_write_2(sc, SK_MACARB_CTL, 2527 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2528 2529 sc_if->sk_link = 1; 2530 } 2531 2532 void sk_init_yukon(struct sk_if_softc *sc_if) 2533 { 2534 u_int32_t /*mac, */phy; 2535 u_int16_t reg; 2536 struct sk_softc *sc; 2537 int i; 2538 2539 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2540 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2541 2542 sc = sc_if->sk_softc; 2543 if (sc->sk_type == SK_YUKON_LITE && 2544 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2545 /* Take PHY out of reset. */ 2546 sk_win_write_4(sc, SK_GPIO, 2547 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2548 } 2549 2550 2551 /* GMAC and GPHY Reset */ 2552 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2553 2554 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2555 2556 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2557 DELAY(1000); 2558 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2559 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2560 DELAY(1000); 2561 2562 2563 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2564 2565 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2566 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2567 2568 switch (sc_if->sk_softc->sk_pmd) { 2569 case IFM_1000_SX: 2570 case IFM_1000_LX: 2571 phy |= SK_GPHY_FIBER; 2572 break; 2573 2574 case IFM_1000_CX: 2575 case IFM_1000_T: 2576 phy |= SK_GPHY_COPPER; 2577 break; 2578 } 2579 2580 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2581 2582 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2583 DELAY(1000); 2584 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2585 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2586 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2587 2588 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2589 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2590 2591 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2592 2593 /* unused read of the interrupt source register */ 2594 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2595 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2596 2597 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2598 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2599 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2600 2601 /* MIB Counter Clear Mode set */ 2602 reg |= YU_PAR_MIB_CLR; 2603 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2604 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2605 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2606 2607 /* MIB Counter Clear Mode clear */ 2608 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2609 reg &= ~YU_PAR_MIB_CLR; 2610 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2611 2612 /* receive control reg */ 2613 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2614 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2615 YU_RCR_CRCR); 2616 2617 /* transmit parameter register */ 2618 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2619 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2620 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2621 2622 /* serial mode register */ 2623 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2624 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2625 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2626 YU_SMR_IPG_DATA(0x1e)); 2627 2628 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2629 /* Setup Yukon's address */ 2630 for (i = 0; i < 3; i++) { 2631 /* Write Source Address 1 (unicast filter) */ 2632 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2633 sc_if->sk_enaddr[i * 2] | 2634 sc_if->sk_enaddr[i * 2 + 1] << 8); 2635 } 2636 2637 for (i = 0; i < 3; i++) { 2638 reg = sk_win_read_2(sc_if->sk_softc, 2639 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2640 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2641 } 2642 2643 /* Set multicast filter */ 2644 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2645 sk_setmulti(sc_if); 2646 2647 /* enable interrupt mask for counter overflows */ 2648 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2649 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2650 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2651 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2652 2653 /* Configure RX MAC FIFO */ 2654 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2655 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2656 2657 /* Configure TX MAC FIFO */ 2658 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2659 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2660 2661 DPRINTFN(6, ("sk_init_yukon: end\n")); 2662 } 2663 2664 /* 2665 * Note that to properly initialize any part of the GEnesis chip, 2666 * you first have to take it out of reset mode. 2667 */ 2668 int 2669 sk_init(struct ifnet *ifp) 2670 { 2671 struct sk_if_softc *sc_if = ifp->if_softc; 2672 struct sk_softc *sc = sc_if->sk_softc; 2673 struct mii_data *mii = &sc_if->sk_mii; 2674 int rc = 0, s; 2675 u_int32_t imr, imtimer_ticks; 2676 2677 DPRINTFN(1, ("sk_init\n")); 2678 2679 s = splnet(); 2680 2681 if (ifp->if_flags & IFF_RUNNING) { 2682 splx(s); 2683 return 0; 2684 } 2685 2686 /* Cancel pending I/O and free all RX/TX buffers. */ 2687 sk_stop(ifp,0); 2688 2689 if (sc->sk_type == SK_GENESIS) { 2690 /* Configure LINK_SYNC LED */ 2691 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2692 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2693 SK_LINKLED_LINKSYNC_ON); 2694 2695 /* Configure RX LED */ 2696 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2697 SK_RXLEDCTL_COUNTER_START); 2698 2699 /* Configure TX LED */ 2700 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2701 SK_TXLEDCTL_COUNTER_START); 2702 } 2703 2704 /* Configure I2C registers */ 2705 2706 /* Configure XMAC(s) */ 2707 switch (sc->sk_type) { 2708 case SK_GENESIS: 2709 sk_init_xmac(sc_if); 2710 break; 2711 case SK_YUKON: 2712 case SK_YUKON_LITE: 2713 case SK_YUKON_LP: 2714 sk_init_yukon(sc_if); 2715 break; 2716 } 2717 if ((rc = mii_mediachg(mii)) == ENXIO) 2718 rc = 0; 2719 else if (rc != 0) 2720 goto out; 2721 2722 if (sc->sk_type == SK_GENESIS) { 2723 /* Configure MAC FIFOs */ 2724 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2725 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2726 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2727 2728 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2729 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2730 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2731 } 2732 2733 /* Configure transmit arbiter(s) */ 2734 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2735 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2736 2737 /* Configure RAMbuffers */ 2738 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2739 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2740 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2741 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2742 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2743 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2744 2745 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2746 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2747 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2748 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2749 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2750 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2751 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2752 2753 /* Configure BMUs */ 2754 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2755 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2756 SK_RX_RING_ADDR(sc_if, 0)); 2757 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2758 2759 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2760 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2761 SK_TX_RING_ADDR(sc_if, 0)); 2762 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2763 2764 /* Init descriptors */ 2765 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2766 aprint_error_dev(&sc_if->sk_dev, "initialization failed: no " 2767 "memory for rx buffers\n"); 2768 sk_stop(ifp,0); 2769 splx(s); 2770 return ENOBUFS; 2771 } 2772 2773 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2774 aprint_error_dev(&sc_if->sk_dev, "initialization failed: no " 2775 "memory for tx buffers\n"); 2776 sk_stop(ifp,0); 2777 splx(s); 2778 return ENOBUFS; 2779 } 2780 2781 /* Set interrupt moderation if changed via sysctl. */ 2782 switch (sc->sk_type) { 2783 case SK_GENESIS: 2784 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2785 break; 2786 case SK_YUKON_EC: 2787 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2788 break; 2789 default: 2790 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2791 } 2792 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2793 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2794 sk_win_write_4(sc, SK_IMTIMERINIT, 2795 SK_IM_USECS(sc->sk_int_mod)); 2796 aprint_verbose_dev(&sc->sk_dev, "interrupt moderation is %d us\n", 2797 sc->sk_int_mod); 2798 } 2799 2800 /* Configure interrupt handling */ 2801 CSR_READ_4(sc, SK_ISSR); 2802 if (sc_if->sk_port == SK_PORT_A) 2803 sc->sk_intrmask |= SK_INTRS1; 2804 else 2805 sc->sk_intrmask |= SK_INTRS2; 2806 2807 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2808 2809 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2810 2811 /* Start BMUs. */ 2812 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2813 2814 if (sc->sk_type == SK_GENESIS) { 2815 /* Enable XMACs TX and RX state machines */ 2816 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2817 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2818 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2819 } 2820 2821 if (SK_YUKON_FAMILY(sc->sk_type)) { 2822 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2823 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2824 #if 0 2825 /* XXX disable 100Mbps and full duplex mode? */ 2826 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2827 #endif 2828 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2829 } 2830 2831 2832 ifp->if_flags |= IFF_RUNNING; 2833 ifp->if_flags &= ~IFF_OACTIVE; 2834 2835 out: 2836 splx(s); 2837 return rc; 2838 } 2839 2840 void 2841 sk_stop(struct ifnet *ifp, int disable) 2842 { 2843 struct sk_if_softc *sc_if = ifp->if_softc; 2844 struct sk_softc *sc = sc_if->sk_softc; 2845 int i; 2846 2847 DPRINTFN(1, ("sk_stop\n")); 2848 2849 callout_stop(&sc_if->sk_tick_ch); 2850 2851 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2852 u_int32_t val; 2853 2854 /* Put PHY back into reset. */ 2855 val = sk_win_read_4(sc, SK_GPIO); 2856 if (sc_if->sk_port == SK_PORT_A) { 2857 val |= SK_GPIO_DIR0; 2858 val &= ~SK_GPIO_DAT0; 2859 } else { 2860 val |= SK_GPIO_DIR2; 2861 val &= ~SK_GPIO_DAT2; 2862 } 2863 sk_win_write_4(sc, SK_GPIO, val); 2864 } 2865 2866 /* Turn off various components of this interface. */ 2867 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2868 switch (sc->sk_type) { 2869 case SK_GENESIS: 2870 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2871 SK_TXMACCTL_XMAC_RESET); 2872 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2873 break; 2874 case SK_YUKON: 2875 case SK_YUKON_LITE: 2876 case SK_YUKON_LP: 2877 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2878 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2879 break; 2880 } 2881 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2882 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2883 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2884 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2885 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2886 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2887 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2888 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2889 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2890 2891 /* Disable interrupts */ 2892 if (sc_if->sk_port == SK_PORT_A) 2893 sc->sk_intrmask &= ~SK_INTRS1; 2894 else 2895 sc->sk_intrmask &= ~SK_INTRS2; 2896 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2897 2898 SK_XM_READ_2(sc_if, XM_ISR); 2899 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2900 2901 /* Free RX and TX mbufs still in the queues. */ 2902 for (i = 0; i < SK_RX_RING_CNT; i++) { 2903 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2904 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2905 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2906 } 2907 } 2908 2909 for (i = 0; i < SK_TX_RING_CNT; i++) { 2910 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2911 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2912 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2913 } 2914 } 2915 2916 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2917 } 2918 2919 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2920 2921 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2922 2923 #ifdef SK_DEBUG 2924 void 2925 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2926 { 2927 #define DESC_PRINT(X) \ 2928 if (X) \ 2929 printf("txdesc[%d]." #X "=%#x\n", \ 2930 idx, X); 2931 2932 DESC_PRINT(le32toh(desc->sk_ctl)); 2933 DESC_PRINT(le32toh(desc->sk_next)); 2934 DESC_PRINT(le32toh(desc->sk_data_lo)); 2935 DESC_PRINT(le32toh(desc->sk_data_hi)); 2936 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2937 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2938 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2939 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2940 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2941 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2942 #undef PRINT 2943 } 2944 2945 void 2946 sk_dump_bytes(const char *data, int len) 2947 { 2948 int c, i, j; 2949 2950 for (i = 0; i < len; i += 16) { 2951 printf("%08x ", i); 2952 c = len - i; 2953 if (c > 16) c = 16; 2954 2955 for (j = 0; j < c; j++) { 2956 printf("%02x ", data[i + j] & 0xff); 2957 if ((j & 0xf) == 7 && j > 0) 2958 printf(" "); 2959 } 2960 2961 for (; j < 16; j++) 2962 printf(" "); 2963 printf(" "); 2964 2965 for (j = 0; j < c; j++) { 2966 int ch = data[i + j] & 0xff; 2967 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2968 } 2969 2970 printf("\n"); 2971 2972 if (c < 16) 2973 break; 2974 } 2975 } 2976 2977 void 2978 sk_dump_mbuf(struct mbuf *m) 2979 { 2980 int count = m->m_pkthdr.len; 2981 2982 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2983 2984 while (count > 0 && m) { 2985 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2986 m, m->m_data, m->m_len); 2987 sk_dump_bytes(mtod(m, char *), m->m_len); 2988 2989 count -= m->m_len; 2990 m = m->m_next; 2991 } 2992 } 2993 #endif 2994 2995 static int 2996 sk_sysctl_handler(SYSCTLFN_ARGS) 2997 { 2998 int error, t; 2999 struct sysctlnode node; 3000 struct sk_softc *sc; 3001 3002 node = *rnode; 3003 sc = node.sysctl_data; 3004 t = sc->sk_int_mod; 3005 node.sysctl_data = &t; 3006 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3007 if (error || newp == NULL) 3008 return error; 3009 3010 if (t < SK_IM_MIN || t > SK_IM_MAX) 3011 return EINVAL; 3012 3013 /* update the softc with sysctl-changed value, and mark 3014 for hardware update */ 3015 sc->sk_int_mod = t; 3016 sc->sk_int_mod_pending = 1; 3017 return 0; 3018 } 3019 3020 /* 3021 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3022 * set up in skc_attach() 3023 */ 3024 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3025 { 3026 int rc; 3027 const struct sysctlnode *node; 3028 3029 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3030 0, CTLTYPE_NODE, "hw", NULL, 3031 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3032 goto err; 3033 } 3034 3035 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3036 0, CTLTYPE_NODE, "sk", 3037 SYSCTL_DESCR("sk interface controls"), 3038 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3039 goto err; 3040 } 3041 3042 sk_root_num = node->sysctl_num; 3043 return; 3044 3045 err: 3046 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3047 } 3048
Indexes created Mon Oct 13 16:09:52 GMT 2025