if_sk.c revision 1.49.2.2
1 /* $NetBSD: if_sk.c,v 1.49.2.2 2008/09/24 16:38:53 wrstuden Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.49.2.2 2008/09/24 16:38:53 wrstuden Exp $"); 119 120 #include "bpfilter.h" 121 #include "rnd.h" 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/sockio.h> 126 #include <sys/mbuf.h> 127 #include <sys/malloc.h> 128 #include <sys/mutex.h> 129 #include <sys/kernel.h> 130 #include <sys/socket.h> 131 #include <sys/device.h> 132 #include <sys/queue.h> 133 #include <sys/callout.h> 134 #include <sys/sysctl.h> 135 #include <sys/endian.h> 136 137 #include <net/if.h> 138 #include <net/if_dl.h> 139 #include <net/if_types.h> 140 141 #include <net/if_media.h> 142 143 #if NBPFILTER > 0 144 #include <net/bpf.h> 145 #endif 146 #if NRND > 0 147 #include <sys/rnd.h> 148 #endif 149 150 #include <dev/mii/mii.h> 151 #include <dev/mii/miivar.h> 152 #include <dev/mii/brgphyreg.h> 153 154 #include <dev/pci/pcireg.h> 155 #include <dev/pci/pcivar.h> 156 #include <dev/pci/pcidevs.h> 157 158 /* #define SK_USEIOSPACE */ 159 160 #include <dev/pci/if_skreg.h> 161 #include <dev/pci/if_skvar.h> 162 163 int skc_probe(device_t, cfdata_t, void *); 164 void skc_attach(device_t, device_t, void *aux); 165 int sk_probe(device_t, cfdata_t, void *); 166 void sk_attach(device_t, device_t, void *aux); 167 int skcprint(void *, const char *); 168 int sk_intr(void *); 169 void sk_intr_bcom(struct sk_if_softc *); 170 void sk_intr_xmac(struct sk_if_softc *); 171 void sk_intr_yukon(struct sk_if_softc *); 172 void sk_rxeof(struct sk_if_softc *); 173 void sk_txeof(struct sk_if_softc *); 174 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 175 void sk_start(struct ifnet *); 176 int sk_ioctl(struct ifnet *, u_long, void *); 177 int sk_init(struct ifnet *); 178 void sk_init_xmac(struct sk_if_softc *); 179 void sk_init_yukon(struct sk_if_softc *); 180 void sk_stop(struct ifnet *, int); 181 void sk_watchdog(struct ifnet *); 182 void sk_shutdown(void *); 183 int sk_ifmedia_upd(struct ifnet *); 184 void sk_reset(struct sk_softc *); 185 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 186 int sk_alloc_jumbo_mem(struct sk_if_softc *); 187 void sk_free_jumbo_mem(struct sk_if_softc *); 188 void *sk_jalloc(struct sk_if_softc *); 189 void sk_jfree(struct mbuf *, void *, size_t, void *); 190 int sk_init_rx_ring(struct sk_if_softc *); 191 int sk_init_tx_ring(struct sk_if_softc *); 192 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 193 void sk_vpd_read_res(struct sk_softc *, 194 struct vpd_res *, int); 195 void sk_vpd_read(struct sk_softc *); 196 197 void sk_update_int_mod(struct sk_softc *); 198 199 int sk_xmac_miibus_readreg(device_t, int, int); 200 void sk_xmac_miibus_writereg(device_t, int, int, int); 201 void sk_xmac_miibus_statchg(device_t); 202 203 int sk_marv_miibus_readreg(device_t, int, int); 204 void sk_marv_miibus_writereg(device_t, int, int, int); 205 void sk_marv_miibus_statchg(device_t); 206 207 u_int32_t sk_xmac_hash(void *); 208 u_int32_t sk_yukon_hash(void *); 209 void sk_setfilt(struct sk_if_softc *, void *, int); 210 void sk_setmulti(struct sk_if_softc *); 211 void sk_tick(void *); 212 213 /* #define SK_DEBUG 2 */ 214 #ifdef SK_DEBUG 215 #define DPRINTF(x) if (skdebug) printf x 216 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 217 int skdebug = SK_DEBUG; 218 219 void sk_dump_txdesc(struct sk_tx_desc *, int); 220 void sk_dump_mbuf(struct mbuf *); 221 void sk_dump_bytes(const char *, int); 222 #else 223 #define DPRINTF(x) 224 #define DPRINTFN(n,x) 225 #endif 226 227 static int sk_sysctl_handler(SYSCTLFN_PROTO); 228 static int sk_root_num; 229 230 /* supported device vendors */ 231 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 232 static const struct sk_product { 233 pci_vendor_id_t sk_vendor; 234 pci_product_id_t sk_product; 235 } sk_products[] = { 236 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 237 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 238 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 239 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 240 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 241 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 242 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 243 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 244 { 0, 0, } 245 }; 246 247 #define SK_LINKSYS_EG1032_SUBID 0x00151737 248 249 static inline u_int32_t 250 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 251 { 252 #ifdef SK_USEIOSPACE 253 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 254 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 255 #else 256 return CSR_READ_4(sc, reg); 257 #endif 258 } 259 260 static inline u_int16_t 261 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 262 { 263 #ifdef SK_USEIOSPACE 264 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 265 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 266 #else 267 return CSR_READ_2(sc, reg); 268 #endif 269 } 270 271 static inline u_int8_t 272 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 273 { 274 #ifdef SK_USEIOSPACE 275 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 276 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 277 #else 278 return CSR_READ_1(sc, reg); 279 #endif 280 } 281 282 static inline void 283 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 284 { 285 #ifdef SK_USEIOSPACE 286 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 287 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 288 #else 289 CSR_WRITE_4(sc, reg, x); 290 #endif 291 } 292 293 static inline void 294 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 295 { 296 #ifdef SK_USEIOSPACE 297 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 298 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 299 #else 300 CSR_WRITE_2(sc, reg, x); 301 #endif 302 } 303 304 static inline void 305 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 306 { 307 #ifdef SK_USEIOSPACE 308 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 309 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 310 #else 311 CSR_WRITE_1(sc, reg, x); 312 #endif 313 } 314 315 /* 316 * The VPD EEPROM contains Vital Product Data, as suggested in 317 * the PCI 2.1 specification. The VPD data is separared into areas 318 * denoted by resource IDs. The SysKonnect VPD contains an ID string 319 * resource (the name of the adapter), a read-only area resource 320 * containing various key/data fields and a read/write area which 321 * can be used to store asset management information or log messages. 322 * We read the ID string and read-only into buffers attached to 323 * the controller softc structure for later use. At the moment, 324 * we only use the ID string during sk_attach(). 325 */ 326 u_int8_t 327 sk_vpd_readbyte(struct sk_softc *sc, int addr) 328 { 329 int i; 330 331 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 332 for (i = 0; i < SK_TIMEOUT; i++) { 333 DELAY(1); 334 if (sk_win_read_2(sc, 335 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 336 break; 337 } 338 339 if (i == SK_TIMEOUT) 340 return 0; 341 342 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 343 } 344 345 void 346 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 347 { 348 int i; 349 u_int8_t *ptr; 350 351 ptr = (u_int8_t *)res; 352 for (i = 0; i < sizeof(struct vpd_res); i++) 353 ptr[i] = sk_vpd_readbyte(sc, i + addr); 354 } 355 356 void 357 sk_vpd_read(struct sk_softc *sc) 358 { 359 int pos = 0, i; 360 struct vpd_res res; 361 362 if (sc->sk_vpd_prodname != NULL) 363 free(sc->sk_vpd_prodname, M_DEVBUF); 364 if (sc->sk_vpd_readonly != NULL) 365 free(sc->sk_vpd_readonly, M_DEVBUF); 366 sc->sk_vpd_prodname = NULL; 367 sc->sk_vpd_readonly = NULL; 368 369 sk_vpd_read_res(sc, &res, pos); 370 371 if (res.vr_id != VPD_RES_ID) { 372 aprint_error_dev(sc->sk_dev, 373 "bad VPD resource id: expected %x got %x\n", 374 VPD_RES_ID, res.vr_id); 375 return; 376 } 377 378 pos += sizeof(res); 379 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 380 if (sc->sk_vpd_prodname == NULL) 381 panic("sk_vpd_read"); 382 for (i = 0; i < res.vr_len; i++) 383 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 384 sc->sk_vpd_prodname[i] = '\0'; 385 pos += i; 386 387 sk_vpd_read_res(sc, &res, pos); 388 389 if (res.vr_id != VPD_RES_READ) { 390 aprint_error_dev(sc->sk_dev, 391 "bad VPD resource id: expected %x got %x\n", 392 VPD_RES_READ, res.vr_id); 393 return; 394 } 395 396 pos += sizeof(res); 397 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 398 if (sc->sk_vpd_readonly == NULL) 399 panic("sk_vpd_read"); 400 for (i = 0; i < res.vr_len ; i++) 401 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 402 } 403 404 int 405 sk_xmac_miibus_readreg(device_t dev, int phy, int reg) 406 { 407 struct sk_if_softc *sc_if = device_private(dev); 408 int i; 409 410 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 411 412 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 413 return 0; 414 415 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 416 SK_XM_READ_2(sc_if, XM_PHY_DATA); 417 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 418 for (i = 0; i < SK_TIMEOUT; i++) { 419 DELAY(1); 420 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 421 XM_MMUCMD_PHYDATARDY) 422 break; 423 } 424 425 if (i == SK_TIMEOUT) { 426 aprint_error_dev(sc_if->sk_dev, 427 "phy failed to come ready\n"); 428 return 0; 429 } 430 } 431 DELAY(1); 432 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 433 } 434 435 void 436 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, int val) 437 { 438 struct sk_if_softc *sc_if = device_private(dev); 439 int i; 440 441 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 442 443 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 444 for (i = 0; i < SK_TIMEOUT; i++) { 445 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 446 break; 447 } 448 449 if (i == SK_TIMEOUT) { 450 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 451 return; 452 } 453 454 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 455 for (i = 0; i < SK_TIMEOUT; i++) { 456 DELAY(1); 457 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 458 break; 459 } 460 461 if (i == SK_TIMEOUT) 462 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 463 } 464 465 void 466 sk_xmac_miibus_statchg(device_t dev) 467 { 468 struct sk_if_softc *sc_if = device_private(dev); 469 struct mii_data *mii = &sc_if->sk_mii; 470 471 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 472 473 /* 474 * If this is a GMII PHY, manually set the XMAC's 475 * duplex mode accordingly. 476 */ 477 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 478 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 479 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 480 else 481 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 482 } 483 } 484 485 int 486 sk_marv_miibus_readreg(device_t dev, int phy, int reg) 487 { 488 struct sk_if_softc *sc_if = device_private(dev); 489 u_int16_t val; 490 int i; 491 492 if (phy != 0 || 493 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 494 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 495 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 496 phy, reg)); 497 return 0; 498 } 499 500 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 501 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 502 503 for (i = 0; i < SK_TIMEOUT; i++) { 504 DELAY(1); 505 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 506 if (val & YU_SMICR_READ_VALID) 507 break; 508 } 509 510 if (i == SK_TIMEOUT) { 511 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 512 return 0; 513 } 514 515 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 516 SK_TIMEOUT)); 517 518 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 519 520 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 521 phy, reg, val)); 522 523 return val; 524 } 525 526 void 527 sk_marv_miibus_writereg(device_t dev, int phy, int reg, int val) 528 { 529 struct sk_if_softc *sc_if = device_private(dev); 530 int i; 531 532 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 533 phy, reg, val)); 534 535 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 536 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 537 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 538 539 for (i = 0; i < SK_TIMEOUT; i++) { 540 DELAY(1); 541 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 542 break; 543 } 544 545 if (i == SK_TIMEOUT) 546 printf("%s: phy write timed out\n", 547 device_xname(sc_if->sk_dev)); 548 } 549 550 void 551 sk_marv_miibus_statchg(device_t dev) 552 { 553 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 554 SK_YU_READ_2(((struct sk_if_softc *)device_private(dev)), 555 YUKON_GPCR))); 556 } 557 558 #define SK_HASH_BITS 6 559 560 u_int32_t 561 sk_xmac_hash(void *addr) 562 { 563 u_int32_t crc; 564 565 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 566 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 567 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 568 return crc; 569 } 570 571 u_int32_t 572 sk_yukon_hash(void *addr) 573 { 574 u_int32_t crc; 575 576 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 577 crc &= ((1 << SK_HASH_BITS) - 1); 578 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 579 return crc; 580 } 581 582 void 583 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 584 { 585 char *addr = addrv; 586 int base = XM_RXFILT_ENTRY(slot); 587 588 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 589 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 590 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 591 } 592 593 void 594 sk_setmulti(struct sk_if_softc *sc_if) 595 { 596 struct sk_softc *sc = sc_if->sk_softc; 597 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 598 u_int32_t hashes[2] = { 0, 0 }; 599 int h = 0, i; 600 struct ethercom *ec = &sc_if->sk_ethercom; 601 struct ether_multi *enm; 602 struct ether_multistep step; 603 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 604 605 /* First, zot all the existing filters. */ 606 switch (sc->sk_type) { 607 case SK_GENESIS: 608 for (i = 1; i < XM_RXFILT_MAX; i++) 609 sk_setfilt(sc_if, (void *)&dummy, i); 610 611 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 612 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 613 break; 614 case SK_YUKON: 615 case SK_YUKON_LITE: 616 case SK_YUKON_LP: 617 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 618 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 619 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 620 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 621 break; 622 } 623 624 /* Now program new ones. */ 625 allmulti: 626 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 627 hashes[0] = 0xFFFFFFFF; 628 hashes[1] = 0xFFFFFFFF; 629 } else { 630 i = 1; 631 /* First find the tail of the list. */ 632 ETHER_FIRST_MULTI(step, ec, enm); 633 while (enm != NULL) { 634 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 635 ETHER_ADDR_LEN)) { 636 ifp->if_flags |= IFF_ALLMULTI; 637 goto allmulti; 638 } 639 DPRINTFN(2,("multicast address %s\n", 640 ether_sprintf(enm->enm_addrlo))); 641 /* 642 * Program the first XM_RXFILT_MAX multicast groups 643 * into the perfect filter. For all others, 644 * use the hash table. 645 */ 646 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 647 sk_setfilt(sc_if, enm->enm_addrlo, i); 648 i++; 649 } 650 else { 651 switch (sc->sk_type) { 652 case SK_GENESIS: 653 h = sk_xmac_hash(enm->enm_addrlo); 654 break; 655 case SK_YUKON: 656 case SK_YUKON_LITE: 657 case SK_YUKON_LP: 658 h = sk_yukon_hash(enm->enm_addrlo); 659 break; 660 } 661 if (h < 32) 662 hashes[0] |= (1 << h); 663 else 664 hashes[1] |= (1 << (h - 32)); 665 } 666 667 ETHER_NEXT_MULTI(step, enm); 668 } 669 } 670 671 switch (sc->sk_type) { 672 case SK_GENESIS: 673 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 674 XM_MODE_RX_USE_PERFECT); 675 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 676 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 677 break; 678 case SK_YUKON: 679 case SK_YUKON_LITE: 680 case SK_YUKON_LP: 681 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 682 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 683 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 684 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 685 break; 686 } 687 } 688 689 int 690 sk_init_rx_ring(struct sk_if_softc *sc_if) 691 { 692 struct sk_chain_data *cd = &sc_if->sk_cdata; 693 struct sk_ring_data *rd = sc_if->sk_rdata; 694 int i; 695 696 bzero((char *)rd->sk_rx_ring, 697 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 698 699 for (i = 0; i < SK_RX_RING_CNT; i++) { 700 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 701 if (i == (SK_RX_RING_CNT - 1)) { 702 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 703 rd->sk_rx_ring[i].sk_next = 704 htole32(SK_RX_RING_ADDR(sc_if, 0)); 705 } else { 706 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 707 rd->sk_rx_ring[i].sk_next = 708 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 709 } 710 } 711 712 for (i = 0; i < SK_RX_RING_CNT; i++) { 713 if (sk_newbuf(sc_if, i, NULL, 714 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 715 aprint_error_dev(sc_if->sk_dev, 716 "failed alloc of %dth mbuf\n", i); 717 return ENOBUFS; 718 } 719 } 720 sc_if->sk_cdata.sk_rx_prod = 0; 721 sc_if->sk_cdata.sk_rx_cons = 0; 722 723 return 0; 724 } 725 726 int 727 sk_init_tx_ring(struct sk_if_softc *sc_if) 728 { 729 struct sk_chain_data *cd = &sc_if->sk_cdata; 730 struct sk_ring_data *rd = sc_if->sk_rdata; 731 int i; 732 733 memset(sc_if->sk_rdata->sk_tx_ring, 0, 734 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 735 736 for (i = 0; i < SK_TX_RING_CNT; i++) { 737 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 738 if (i == (SK_TX_RING_CNT - 1)) { 739 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 740 rd->sk_tx_ring[i].sk_next = 741 htole32(SK_TX_RING_ADDR(sc_if, 0)); 742 } else { 743 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 744 rd->sk_tx_ring[i].sk_next = 745 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 746 } 747 } 748 749 sc_if->sk_cdata.sk_tx_prod = 0; 750 sc_if->sk_cdata.sk_tx_cons = 0; 751 sc_if->sk_cdata.sk_tx_cnt = 0; 752 753 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 754 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 755 756 return 0; 757 } 758 759 int 760 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 761 bus_dmamap_t dmamap) 762 { 763 struct mbuf *m_new = NULL; 764 struct sk_chain *c; 765 struct sk_rx_desc *r; 766 767 if (m == NULL) { 768 void *buf = NULL; 769 770 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 771 if (m_new == NULL) { 772 aprint_error_dev(sc_if->sk_dev, 773 "no memory for rx list -- packet dropped!\n"); 774 return ENOBUFS; 775 } 776 777 /* Allocate the jumbo buffer */ 778 buf = sk_jalloc(sc_if); 779 if (buf == NULL) { 780 m_freem(m_new); 781 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 782 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 783 return ENOBUFS; 784 } 785 786 /* Attach the buffer to the mbuf */ 787 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 788 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 789 790 } else { 791 /* 792 * We're re-using a previously allocated mbuf; 793 * be sure to re-init pointers and lengths to 794 * default values. 795 */ 796 m_new = m; 797 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 798 m_new->m_data = m_new->m_ext.ext_buf; 799 } 800 m_adj(m_new, ETHER_ALIGN); 801 802 c = &sc_if->sk_cdata.sk_rx_chain[i]; 803 r = c->sk_desc; 804 c->sk_mbuf = m_new; 805 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 806 (((vaddr_t)m_new->m_data 807 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 808 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 809 810 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 811 812 return 0; 813 } 814 815 /* 816 * Memory management for jumbo frames. 817 */ 818 819 int 820 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 821 { 822 struct sk_softc *sc = sc_if->sk_softc; 823 char *ptr, *kva; 824 bus_dma_segment_t seg; 825 int i, rseg, state, error; 826 struct sk_jpool_entry *entry; 827 828 state = error = 0; 829 830 /* Grab a big chunk o' storage. */ 831 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 832 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 833 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 834 return ENOBUFS; 835 } 836 837 state = 1; 838 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 839 BUS_DMA_NOWAIT)) { 840 aprint_error_dev(sc->sk_dev, 841 "can't map dma buffers (%d bytes)\n", 842 SK_JMEM); 843 error = ENOBUFS; 844 goto out; 845 } 846 847 state = 2; 848 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 849 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 850 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 851 error = ENOBUFS; 852 goto out; 853 } 854 855 state = 3; 856 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 857 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 858 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 859 error = ENOBUFS; 860 goto out; 861 } 862 863 state = 4; 864 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 865 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 866 867 LIST_INIT(&sc_if->sk_jfree_listhead); 868 LIST_INIT(&sc_if->sk_jinuse_listhead); 869 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 870 871 /* 872 * Now divide it up into 9K pieces and save the addresses 873 * in an array. 874 */ 875 ptr = sc_if->sk_cdata.sk_jumbo_buf; 876 for (i = 0; i < SK_JSLOTS; i++) { 877 sc_if->sk_cdata.sk_jslots[i] = ptr; 878 ptr += SK_JLEN; 879 entry = malloc(sizeof(struct sk_jpool_entry), 880 M_DEVBUF, M_NOWAIT); 881 if (entry == NULL) { 882 aprint_error_dev(sc->sk_dev, 883 "no memory for jumbo buffer queue!\n"); 884 error = ENOBUFS; 885 goto out; 886 } 887 entry->slot = i; 888 if (i) 889 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 890 entry, jpool_entries); 891 else 892 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 893 entry, jpool_entries); 894 } 895 out: 896 if (error != 0) { 897 switch (state) { 898 case 4: 899 bus_dmamap_unload(sc->sc_dmatag, 900 sc_if->sk_cdata.sk_rx_jumbo_map); 901 case 3: 902 bus_dmamap_destroy(sc->sc_dmatag, 903 sc_if->sk_cdata.sk_rx_jumbo_map); 904 case 2: 905 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 906 case 1: 907 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 908 break; 909 default: 910 break; 911 } 912 } 913 914 return error; 915 } 916 917 /* 918 * Allocate a jumbo buffer. 919 */ 920 void * 921 sk_jalloc(struct sk_if_softc *sc_if) 922 { 923 struct sk_jpool_entry *entry; 924 925 mutex_enter(&sc_if->sk_jpool_mtx); 926 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 927 928 if (entry == NULL) { 929 mutex_exit(&sc_if->sk_jpool_mtx); 930 return NULL; 931 } 932 933 LIST_REMOVE(entry, jpool_entries); 934 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 935 mutex_exit(&sc_if->sk_jpool_mtx); 936 return sc_if->sk_cdata.sk_jslots[entry->slot]; 937 } 938 939 /* 940 * Release a jumbo buffer. 941 */ 942 void 943 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 944 { 945 struct sk_jpool_entry *entry; 946 struct sk_if_softc *sc; 947 int i; 948 949 /* Extract the softc struct pointer. */ 950 sc = (struct sk_if_softc *)arg; 951 952 if (sc == NULL) 953 panic("sk_jfree: can't find softc pointer!"); 954 955 /* calculate the slot this buffer belongs to */ 956 957 i = ((vaddr_t)buf 958 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 959 960 if ((i < 0) || (i >= SK_JSLOTS)) 961 panic("sk_jfree: asked to free buffer that we don't manage!"); 962 963 mutex_enter(&sc->sk_jpool_mtx); 964 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 965 if (entry == NULL) 966 panic("sk_jfree: buffer not in use!"); 967 entry->slot = i; 968 LIST_REMOVE(entry, jpool_entries); 969 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 970 mutex_exit(&sc->sk_jpool_mtx); 971 972 if (__predict_true(m != NULL)) 973 pool_cache_put(mb_cache, m); 974 } 975 976 /* 977 * Set media options. 978 */ 979 int 980 sk_ifmedia_upd(struct ifnet *ifp) 981 { 982 struct sk_if_softc *sc_if = ifp->if_softc; 983 int rc; 984 985 (void) sk_init(ifp); 986 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 987 return 0; 988 return rc; 989 } 990 991 int 992 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 993 { 994 struct sk_if_softc *sc_if = ifp->if_softc; 995 struct sk_softc *sc = sc_if->sk_softc; 996 int s, error = 0; 997 998 /* DPRINTFN(2, ("sk_ioctl\n")); */ 999 1000 s = splnet(); 1001 1002 switch (command) { 1003 1004 case SIOCSIFFLAGS: 1005 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1006 if (ifp->if_flags & IFF_UP) { 1007 if (ifp->if_flags & IFF_RUNNING && 1008 ifp->if_flags & IFF_PROMISC && 1009 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1010 switch (sc->sk_type) { 1011 case SK_GENESIS: 1012 SK_XM_SETBIT_4(sc_if, XM_MODE, 1013 XM_MODE_RX_PROMISC); 1014 break; 1015 case SK_YUKON: 1016 case SK_YUKON_LITE: 1017 case SK_YUKON_LP: 1018 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1019 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1020 break; 1021 } 1022 sk_setmulti(sc_if); 1023 } else if (ifp->if_flags & IFF_RUNNING && 1024 !(ifp->if_flags & IFF_PROMISC) && 1025 sc_if->sk_if_flags & IFF_PROMISC) { 1026 switch (sc->sk_type) { 1027 case SK_GENESIS: 1028 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1029 XM_MODE_RX_PROMISC); 1030 break; 1031 case SK_YUKON: 1032 case SK_YUKON_LITE: 1033 case SK_YUKON_LP: 1034 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1035 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1036 break; 1037 } 1038 1039 sk_setmulti(sc_if); 1040 } else 1041 (void) sk_init(ifp); 1042 } else { 1043 if (ifp->if_flags & IFF_RUNNING) 1044 sk_stop(ifp,0); 1045 } 1046 sc_if->sk_if_flags = ifp->if_flags; 1047 error = 0; 1048 break; 1049 1050 default: 1051 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1052 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1053 break; 1054 1055 error = 0; 1056 1057 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1058 ; 1059 else if (ifp->if_flags & IFF_RUNNING) { 1060 sk_setmulti(sc_if); 1061 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1062 } 1063 break; 1064 } 1065 1066 splx(s); 1067 return error; 1068 } 1069 1070 void 1071 sk_update_int_mod(struct sk_softc *sc) 1072 { 1073 u_int32_t imtimer_ticks; 1074 1075 /* 1076 * Configure interrupt moderation. The moderation timer 1077 * defers interrupts specified in the interrupt moderation 1078 * timer mask based on the timeout specified in the interrupt 1079 * moderation timer init register. Each bit in the timer 1080 * register represents one tick, so to specify a timeout in 1081 * microseconds, we have to multiply by the correct number of 1082 * ticks-per-microsecond. 1083 */ 1084 switch (sc->sk_type) { 1085 case SK_GENESIS: 1086 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1087 break; 1088 case SK_YUKON_EC: 1089 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1090 break; 1091 default: 1092 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1093 } 1094 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1095 sc->sk_int_mod); 1096 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1097 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1098 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1099 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1100 sc->sk_int_mod_pending = 0; 1101 } 1102 1103 /* 1104 * Lookup: Check the PCI vendor and device, and return a pointer to 1105 * The structure if the IDs match against our list. 1106 */ 1107 1108 static const struct sk_product * 1109 sk_lookup(const struct pci_attach_args *pa) 1110 { 1111 const struct sk_product *psk; 1112 1113 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1114 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1115 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1116 return psk; 1117 } 1118 return NULL; 1119 } 1120 1121 /* 1122 * Probe for a SysKonnect GEnesis chip. 1123 */ 1124 1125 int 1126 skc_probe(device_t parent, cfdata_t match, void *aux) 1127 { 1128 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1129 const struct sk_product *psk; 1130 pcireg_t subid; 1131 1132 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1133 1134 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1135 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1136 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1137 subid == SK_LINKSYS_EG1032_SUBID) 1138 return 1; 1139 1140 if ((psk = sk_lookup(pa))) { 1141 return 1; 1142 } 1143 return 0; 1144 } 1145 1146 /* 1147 * Force the GEnesis into reset, then bring it out of reset. 1148 */ 1149 void sk_reset(struct sk_softc *sc) 1150 { 1151 DPRINTFN(2, ("sk_reset\n")); 1152 1153 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1154 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1155 if (SK_YUKON_FAMILY(sc->sk_type)) 1156 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1157 1158 DELAY(1000); 1159 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1160 DELAY(2); 1161 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1162 if (SK_YUKON_FAMILY(sc->sk_type)) 1163 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1164 1165 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1166 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1167 CSR_READ_2(sc, SK_LINK_CTRL))); 1168 1169 if (sc->sk_type == SK_GENESIS) { 1170 /* Configure packet arbiter */ 1171 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1172 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1173 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1174 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1175 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1176 } 1177 1178 /* Enable RAM interface */ 1179 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1180 1181 sk_update_int_mod(sc); 1182 } 1183 1184 int 1185 sk_probe(device_t parent, cfdata_t match, void *aux) 1186 { 1187 struct skc_attach_args *sa = aux; 1188 1189 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1190 return 0; 1191 1192 return 1; 1193 } 1194 1195 /* 1196 * Each XMAC chip is attached as a separate logical IP interface. 1197 * Single port cards will have only one logical interface of course. 1198 */ 1199 void 1200 sk_attach(device_t parent, device_t self, void *aux) 1201 { 1202 struct sk_if_softc *sc_if = device_private(self); 1203 struct sk_softc *sc = device_private(parent); 1204 struct skc_attach_args *sa = aux; 1205 struct sk_txmap_entry *entry; 1206 struct ifnet *ifp; 1207 bus_dma_segment_t seg; 1208 bus_dmamap_t dmamap; 1209 void *kva; 1210 int i, rseg; 1211 1212 aprint_naive("\n"); 1213 1214 sc_if->sk_dev = self; 1215 sc_if->sk_port = sa->skc_port; 1216 sc_if->sk_softc = sc; 1217 sc->sk_if[sa->skc_port] = sc_if; 1218 1219 if (sa->skc_port == SK_PORT_A) 1220 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1221 if (sa->skc_port == SK_PORT_B) 1222 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1223 1224 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1225 1226 /* 1227 * Get station address for this interface. Note that 1228 * dual port cards actually come with three station 1229 * addresses: one for each port, plus an extra. The 1230 * extra one is used by the SysKonnect driver software 1231 * as a 'virtual' station address for when both ports 1232 * are operating in failover mode. Currently we don't 1233 * use this extra address. 1234 */ 1235 for (i = 0; i < ETHER_ADDR_LEN; i++) 1236 sc_if->sk_enaddr[i] = 1237 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1238 1239 1240 aprint_normal(": Ethernet address %s\n", 1241 ether_sprintf(sc_if->sk_enaddr)); 1242 1243 /* 1244 * Set up RAM buffer addresses. The NIC will have a certain 1245 * amount of SRAM on it, somewhere between 512K and 2MB. We 1246 * need to divide this up a) between the transmitter and 1247 * receiver and b) between the two XMACs, if this is a 1248 * dual port NIC. Our algorithm is to divide up the memory 1249 * evenly so that everyone gets a fair share. 1250 */ 1251 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1252 u_int32_t chunk, val; 1253 1254 chunk = sc->sk_ramsize / 2; 1255 val = sc->sk_rboff / sizeof(u_int64_t); 1256 sc_if->sk_rx_ramstart = val; 1257 val += (chunk / sizeof(u_int64_t)); 1258 sc_if->sk_rx_ramend = val - 1; 1259 sc_if->sk_tx_ramstart = val; 1260 val += (chunk / sizeof(u_int64_t)); 1261 sc_if->sk_tx_ramend = val - 1; 1262 } else { 1263 u_int32_t chunk, val; 1264 1265 chunk = sc->sk_ramsize / 4; 1266 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1267 sizeof(u_int64_t); 1268 sc_if->sk_rx_ramstart = val; 1269 val += (chunk / sizeof(u_int64_t)); 1270 sc_if->sk_rx_ramend = val - 1; 1271 sc_if->sk_tx_ramstart = val; 1272 val += (chunk / sizeof(u_int64_t)); 1273 sc_if->sk_tx_ramend = val - 1; 1274 } 1275 1276 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1277 " tx_ramstart=%#x tx_ramend=%#x\n", 1278 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1279 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1280 1281 /* Read and save PHY type and set PHY address */ 1282 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1283 switch (sc_if->sk_phytype) { 1284 case SK_PHYTYPE_XMAC: 1285 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1286 break; 1287 case SK_PHYTYPE_BCOM: 1288 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1289 break; 1290 case SK_PHYTYPE_MARV_COPPER: 1291 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1292 break; 1293 default: 1294 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1295 sc_if->sk_phytype); 1296 return; 1297 } 1298 1299 /* Allocate the descriptor queues. */ 1300 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1301 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1302 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1303 goto fail; 1304 } 1305 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1306 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1307 aprint_error_dev(sc_if->sk_dev, 1308 "can't map dma buffers (%lu bytes)\n", 1309 (u_long) sizeof(struct sk_ring_data)); 1310 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1311 goto fail; 1312 } 1313 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1314 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1315 &sc_if->sk_ring_map)) { 1316 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1317 bus_dmamem_unmap(sc->sc_dmatag, kva, 1318 sizeof(struct sk_ring_data)); 1319 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1320 goto fail; 1321 } 1322 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1323 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1324 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1325 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1326 bus_dmamem_unmap(sc->sc_dmatag, kva, 1327 sizeof(struct sk_ring_data)); 1328 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1329 goto fail; 1330 } 1331 1332 for (i = 0; i < SK_RX_RING_CNT; i++) 1333 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1334 1335 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1336 for (i = 0; i < SK_TX_RING_CNT; i++) { 1337 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1338 1339 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1340 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1341 aprint_error_dev(sc_if->sk_dev, 1342 "Can't create TX dmamap\n"); 1343 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1344 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1345 bus_dmamem_unmap(sc->sc_dmatag, kva, 1346 sizeof(struct sk_ring_data)); 1347 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1348 goto fail; 1349 } 1350 1351 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1352 if (!entry) { 1353 aprint_error_dev(sc_if->sk_dev, 1354 "Can't alloc txmap entry\n"); 1355 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1356 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1357 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1358 bus_dmamem_unmap(sc->sc_dmatag, kva, 1359 sizeof(struct sk_ring_data)); 1360 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1361 goto fail; 1362 } 1363 entry->dmamap = dmamap; 1364 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1365 } 1366 1367 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1368 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1369 1370 ifp = &sc_if->sk_ethercom.ec_if; 1371 /* Try to allocate memory for jumbo buffers. */ 1372 if (sk_alloc_jumbo_mem(sc_if)) { 1373 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1374 goto fail; 1375 } 1376 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1377 | ETHERCAP_JUMBO_MTU; 1378 1379 ifp->if_softc = sc_if; 1380 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1381 ifp->if_ioctl = sk_ioctl; 1382 ifp->if_start = sk_start; 1383 ifp->if_stop = sk_stop; 1384 ifp->if_init = sk_init; 1385 ifp->if_watchdog = sk_watchdog; 1386 ifp->if_capabilities = 0; 1387 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1388 IFQ_SET_READY(&ifp->if_snd); 1389 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1390 1391 /* 1392 * Do miibus setup. 1393 */ 1394 switch (sc->sk_type) { 1395 case SK_GENESIS: 1396 sk_init_xmac(sc_if); 1397 break; 1398 case SK_YUKON: 1399 case SK_YUKON_LITE: 1400 case SK_YUKON_LP: 1401 sk_init_yukon(sc_if); 1402 break; 1403 default: 1404 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1405 sc->sk_type); 1406 goto fail; 1407 } 1408 1409 DPRINTFN(2, ("sk_attach: 1\n")); 1410 1411 sc_if->sk_mii.mii_ifp = ifp; 1412 switch (sc->sk_type) { 1413 case SK_GENESIS: 1414 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1415 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1416 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1417 break; 1418 case SK_YUKON: 1419 case SK_YUKON_LITE: 1420 case SK_YUKON_LP: 1421 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1422 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1423 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1424 break; 1425 } 1426 1427 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1428 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1429 sk_ifmedia_upd, ether_mediastatus); 1430 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1431 MII_OFFSET_ANY, 0); 1432 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1433 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1434 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1435 0, NULL); 1436 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1437 } else 1438 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1439 1440 callout_init(&sc_if->sk_tick_ch, 0); 1441 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1442 1443 DPRINTFN(2, ("sk_attach: 1\n")); 1444 1445 /* 1446 * Call MI attach routines. 1447 */ 1448 if_attach(ifp); 1449 1450 ether_ifattach(ifp, sc_if->sk_enaddr); 1451 1452 #if NRND > 0 1453 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1454 RND_TYPE_NET, 0); 1455 #endif 1456 1457 DPRINTFN(2, ("sk_attach: end\n")); 1458 1459 return; 1460 1461 fail: 1462 sc->sk_if[sa->skc_port] = NULL; 1463 } 1464 1465 int 1466 skcprint(void *aux, const char *pnp) 1467 { 1468 struct skc_attach_args *sa = aux; 1469 1470 if (pnp) 1471 aprint_normal("sk port %c at %s", 1472 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1473 else 1474 aprint_normal(" port %c", 1475 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1476 return UNCONF; 1477 } 1478 1479 /* 1480 * Attach the interface. Allocate softc structures, do ifmedia 1481 * setup and ethernet/BPF attach. 1482 */ 1483 void 1484 skc_attach(device_t parent, device_t self, void *aux) 1485 { 1486 struct sk_softc *sc = device_private(self); 1487 struct pci_attach_args *pa = aux; 1488 struct skc_attach_args skca; 1489 pci_chipset_tag_t pc = pa->pa_pc; 1490 #ifndef SK_USEIOSPACE 1491 pcireg_t memtype; 1492 #endif 1493 pci_intr_handle_t ih; 1494 const char *intrstr = NULL; 1495 bus_addr_t iobase; 1496 bus_size_t iosize; 1497 int rc, sk_nodenum; 1498 u_int32_t command; 1499 const char *revstr; 1500 const struct sysctlnode *node; 1501 1502 sc->sk_dev = self; 1503 aprint_naive("\n"); 1504 1505 DPRINTFN(2, ("begin skc_attach\n")); 1506 1507 /* 1508 * Handle power management nonsense. 1509 */ 1510 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1511 1512 if (command == 0x01) { 1513 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1514 if (command & SK_PSTATE_MASK) { 1515 u_int32_t xiobase, membase, irq; 1516 1517 /* Save important PCI config data. */ 1518 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1519 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1520 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1521 1522 /* Reset the power state. */ 1523 aprint_normal_dev(sc->sk_dev, 1524 "chip is in D%d power mode -- setting to D0\n", 1525 command & SK_PSTATE_MASK); 1526 command &= 0xFFFFFFFC; 1527 pci_conf_write(pc, pa->pa_tag, 1528 SK_PCI_PWRMGMTCTRL, command); 1529 1530 /* Restore PCI config data. */ 1531 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1532 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1533 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1534 } 1535 } 1536 1537 /* 1538 * Map control/status registers. 1539 */ 1540 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1541 command |= PCI_COMMAND_IO_ENABLE | 1542 PCI_COMMAND_MEM_ENABLE | 1543 PCI_COMMAND_MASTER_ENABLE; 1544 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1545 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1546 1547 #ifdef SK_USEIOSPACE 1548 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1549 aprint_error(": failed to enable I/O ports!\n"); 1550 return; 1551 } 1552 /* 1553 * Map control/status registers. 1554 */ 1555 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1556 &sc->sk_btag, &sc->sk_bhandle, 1557 &iobase, &iosize)) { 1558 aprint_error(": can't find i/o space\n"); 1559 return; 1560 } 1561 #else 1562 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1563 aprint_error(": failed to enable memory mapping!\n"); 1564 return; 1565 } 1566 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1567 switch (memtype) { 1568 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1569 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1570 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1571 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1572 &iobase, &iosize) == 0) 1573 break; 1574 default: 1575 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1576 return; 1577 } 1578 1579 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1580 #endif 1581 sc->sc_dmatag = pa->pa_dmat; 1582 1583 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1584 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1585 1586 /* bail out here if chip is not recognized */ 1587 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1588 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1589 goto fail; 1590 } 1591 if (SK_IS_YUKON2(sc)) { 1592 aprint_error_dev(sc->sk_dev, 1593 "Does not support Yukon2--try msk(4).\n"); 1594 goto fail; 1595 } 1596 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1597 1598 /* Allocate interrupt */ 1599 if (pci_intr_map(pa, &ih)) { 1600 aprint_error(": couldn't map interrupt\n"); 1601 goto fail; 1602 } 1603 1604 intrstr = pci_intr_string(pc, ih); 1605 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1606 if (sc->sk_intrhand == NULL) { 1607 aprint_error(": couldn't establish interrupt"); 1608 if (intrstr != NULL) 1609 aprint_normal(" at %s", intrstr); 1610 goto fail; 1611 } 1612 aprint_normal(": %s\n", intrstr); 1613 1614 /* Reset the adapter. */ 1615 sk_reset(sc); 1616 1617 /* Read and save vital product data from EEPROM. */ 1618 sk_vpd_read(sc); 1619 1620 if (sc->sk_type == SK_GENESIS) { 1621 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1622 /* Read and save RAM size and RAMbuffer offset */ 1623 switch (val) { 1624 case SK_RAMSIZE_512K_64: 1625 sc->sk_ramsize = 0x80000; 1626 sc->sk_rboff = SK_RBOFF_0; 1627 break; 1628 case SK_RAMSIZE_1024K_64: 1629 sc->sk_ramsize = 0x100000; 1630 sc->sk_rboff = SK_RBOFF_80000; 1631 break; 1632 case SK_RAMSIZE_1024K_128: 1633 sc->sk_ramsize = 0x100000; 1634 sc->sk_rboff = SK_RBOFF_0; 1635 break; 1636 case SK_RAMSIZE_2048K_128: 1637 sc->sk_ramsize = 0x200000; 1638 sc->sk_rboff = SK_RBOFF_0; 1639 break; 1640 default: 1641 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1642 val); 1643 goto fail_1; 1644 break; 1645 } 1646 1647 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1648 sc->sk_ramsize, sc->sk_ramsize / 1024, 1649 sc->sk_rboff)); 1650 } else { 1651 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1652 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1653 sc->sk_rboff = SK_RBOFF_0; 1654 1655 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1656 sc->sk_ramsize / 1024, sc->sk_ramsize, 1657 sc->sk_rboff)); 1658 } 1659 1660 /* Read and save physical media type */ 1661 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1662 case SK_PMD_1000BASESX: 1663 sc->sk_pmd = IFM_1000_SX; 1664 break; 1665 case SK_PMD_1000BASELX: 1666 sc->sk_pmd = IFM_1000_LX; 1667 break; 1668 case SK_PMD_1000BASECX: 1669 sc->sk_pmd = IFM_1000_CX; 1670 break; 1671 case SK_PMD_1000BASETX: 1672 case SK_PMD_1000BASETX_ALT: 1673 sc->sk_pmd = IFM_1000_T; 1674 break; 1675 default: 1676 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1677 sk_win_read_1(sc, SK_PMDTYPE)); 1678 goto fail_1; 1679 } 1680 1681 /* determine whether to name it with vpd or just make it up */ 1682 /* Marvell Yukon VPD's can freqently be bogus */ 1683 1684 switch (pa->pa_id) { 1685 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1686 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1687 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1688 case PCI_PRODUCT_3COM_3C940: 1689 case PCI_PRODUCT_DLINK_DGE530T: 1690 case PCI_PRODUCT_DLINK_DGE560T: 1691 case PCI_PRODUCT_DLINK_DGE560T_2: 1692 case PCI_PRODUCT_LINKSYS_EG1032: 1693 case PCI_PRODUCT_LINKSYS_EG1064: 1694 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1695 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1696 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1697 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1698 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1699 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1700 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1701 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1702 sc->sk_name = sc->sk_vpd_prodname; 1703 break; 1704 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1705 /* whoops yukon vpd prodname bears no resemblance to reality */ 1706 switch (sc->sk_type) { 1707 case SK_GENESIS: 1708 sc->sk_name = sc->sk_vpd_prodname; 1709 break; 1710 case SK_YUKON: 1711 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1712 break; 1713 case SK_YUKON_LITE: 1714 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1715 break; 1716 case SK_YUKON_LP: 1717 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1718 break; 1719 default: 1720 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1721 } 1722 1723 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1724 1725 if ( sc->sk_type == SK_YUKON ) { 1726 uint32_t flashaddr; 1727 uint8_t testbyte; 1728 1729 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1730 1731 /* test Flash-Address Register */ 1732 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1733 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1734 1735 if (testbyte != 0) { 1736 /* this is yukon lite Rev. A0 */ 1737 sc->sk_type = SK_YUKON_LITE; 1738 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1739 /* restore Flash-Address Register */ 1740 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1741 } 1742 } 1743 break; 1744 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1745 sc->sk_name = sc->sk_vpd_prodname; 1746 break; 1747 default: 1748 sc->sk_name = "Unknown Marvell"; 1749 } 1750 1751 1752 if ( sc->sk_type == SK_YUKON_LITE ) { 1753 switch (sc->sk_rev) { 1754 case SK_YUKON_LITE_REV_A0: 1755 revstr = "A0"; 1756 break; 1757 case SK_YUKON_LITE_REV_A1: 1758 revstr = "A1"; 1759 break; 1760 case SK_YUKON_LITE_REV_A3: 1761 revstr = "A3"; 1762 break; 1763 default: 1764 revstr = ""; 1765 } 1766 } else { 1767 revstr = ""; 1768 } 1769 1770 /* Announce the product name. */ 1771 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1772 sc->sk_name, revstr, sc->sk_rev); 1773 1774 skca.skc_port = SK_PORT_A; 1775 (void)config_found(sc->sk_dev, &skca, skcprint); 1776 1777 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1778 skca.skc_port = SK_PORT_B; 1779 (void)config_found(sc->sk_dev, &skca, skcprint); 1780 } 1781 1782 /* Turn on the 'driver is loaded' LED. */ 1783 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1784 1785 /* skc sysctl setup */ 1786 1787 sc->sk_int_mod = SK_IM_DEFAULT; 1788 sc->sk_int_mod_pending = 0; 1789 1790 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1791 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1792 SYSCTL_DESCR("skc per-controller controls"), 1793 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1794 CTL_EOL)) != 0) { 1795 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1796 goto fail_1; 1797 } 1798 1799 sk_nodenum = node->sysctl_num; 1800 1801 /* interrupt moderation time in usecs */ 1802 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1803 CTLFLAG_READWRITE, 1804 CTLTYPE_INT, "int_mod", 1805 SYSCTL_DESCR("sk interrupt moderation timer"), 1806 sk_sysctl_handler, 0, sc, 1807 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1808 CTL_EOL)) != 0) { 1809 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1810 goto fail_1; 1811 } 1812 1813 return; 1814 1815 fail_1: 1816 pci_intr_disestablish(pc, sc->sk_intrhand); 1817 fail: 1818 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1819 } 1820 1821 int 1822 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1823 { 1824 struct sk_softc *sc = sc_if->sk_softc; 1825 struct sk_tx_desc *f = NULL; 1826 u_int32_t frag, cur, cnt = 0, sk_ctl; 1827 int i; 1828 struct sk_txmap_entry *entry; 1829 bus_dmamap_t txmap; 1830 1831 DPRINTFN(3, ("sk_encap\n")); 1832 1833 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1834 if (entry == NULL) { 1835 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1836 return ENOBUFS; 1837 } 1838 txmap = entry->dmamap; 1839 1840 cur = frag = *txidx; 1841 1842 #ifdef SK_DEBUG 1843 if (skdebug >= 3) 1844 sk_dump_mbuf(m_head); 1845 #endif 1846 1847 /* 1848 * Start packing the mbufs in this chain into 1849 * the fragment pointers. Stop when we run out 1850 * of fragments or hit the end of the mbuf chain. 1851 */ 1852 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1853 BUS_DMA_NOWAIT)) { 1854 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1855 return ENOBUFS; 1856 } 1857 1858 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1859 1860 /* Sync the DMA map. */ 1861 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1862 BUS_DMASYNC_PREWRITE); 1863 1864 for (i = 0; i < txmap->dm_nsegs; i++) { 1865 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1866 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1867 return ENOBUFS; 1868 } 1869 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1870 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1871 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1872 if (cnt == 0) 1873 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1874 else 1875 sk_ctl |= SK_TXCTL_OWN; 1876 f->sk_ctl = htole32(sk_ctl); 1877 cur = frag; 1878 SK_INC(frag, SK_TX_RING_CNT); 1879 cnt++; 1880 } 1881 1882 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1883 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1884 1885 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1886 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1887 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1888 1889 /* Sync descriptors before handing to chip */ 1890 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1891 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1892 1893 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1894 htole32(SK_TXCTL_OWN); 1895 1896 /* Sync first descriptor to hand it off */ 1897 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1898 1899 sc_if->sk_cdata.sk_tx_cnt += cnt; 1900 1901 #ifdef SK_DEBUG 1902 if (skdebug >= 3) { 1903 struct sk_tx_desc *desc; 1904 u_int32_t idx; 1905 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1906 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1907 sk_dump_txdesc(desc, idx); 1908 } 1909 } 1910 #endif 1911 1912 *txidx = frag; 1913 1914 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1915 1916 return 0; 1917 } 1918 1919 void 1920 sk_start(struct ifnet *ifp) 1921 { 1922 struct sk_if_softc *sc_if = ifp->if_softc; 1923 struct sk_softc *sc = sc_if->sk_softc; 1924 struct mbuf *m_head = NULL; 1925 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1926 int pkts = 0; 1927 1928 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1929 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1930 1931 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1932 IFQ_POLL(&ifp->if_snd, m_head); 1933 if (m_head == NULL) 1934 break; 1935 1936 /* 1937 * Pack the data into the transmit ring. If we 1938 * don't have room, set the OACTIVE flag and wait 1939 * for the NIC to drain the ring. 1940 */ 1941 if (sk_encap(sc_if, m_head, &idx)) { 1942 ifp->if_flags |= IFF_OACTIVE; 1943 break; 1944 } 1945 1946 /* now we are committed to transmit the packet */ 1947 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1948 pkts++; 1949 1950 /* 1951 * If there's a BPF listener, bounce a copy of this frame 1952 * to him. 1953 */ 1954 #if NBPFILTER > 0 1955 if (ifp->if_bpf) 1956 bpf_mtap(ifp->if_bpf, m_head); 1957 #endif 1958 } 1959 if (pkts == 0) 1960 return; 1961 1962 /* Transmit */ 1963 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1964 sc_if->sk_cdata.sk_tx_prod = idx; 1965 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1966 1967 /* Set a timeout in case the chip goes out to lunch. */ 1968 ifp->if_timer = 5; 1969 } 1970 } 1971 1972 1973 void 1974 sk_watchdog(struct ifnet *ifp) 1975 { 1976 struct sk_if_softc *sc_if = ifp->if_softc; 1977 1978 /* 1979 * Reclaim first as there is a possibility of losing Tx completion 1980 * interrupts. 1981 */ 1982 sk_txeof(sc_if); 1983 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1984 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1985 1986 ifp->if_oerrors++; 1987 1988 sk_init(ifp); 1989 } 1990 } 1991 1992 void 1993 sk_shutdown(void *v) 1994 { 1995 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1996 struct sk_softc *sc = sc_if->sk_softc; 1997 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1998 1999 DPRINTFN(2, ("sk_shutdown\n")); 2000 sk_stop(ifp,1); 2001 2002 /* Turn off the 'driver is loaded' LED. */ 2003 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2004 2005 /* 2006 * Reset the GEnesis controller. Doing this should also 2007 * assert the resets on the attached XMAC(s). 2008 */ 2009 sk_reset(sc); 2010 } 2011 2012 void 2013 sk_rxeof(struct sk_if_softc *sc_if) 2014 { 2015 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2016 struct mbuf *m; 2017 struct sk_chain *cur_rx; 2018 struct sk_rx_desc *cur_desc; 2019 int i, cur, total_len = 0; 2020 u_int32_t rxstat, sk_ctl; 2021 bus_dmamap_t dmamap; 2022 2023 i = sc_if->sk_cdata.sk_rx_prod; 2024 2025 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2026 2027 for (;;) { 2028 cur = i; 2029 2030 /* Sync the descriptor */ 2031 SK_CDRXSYNC(sc_if, cur, 2032 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2033 2034 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2035 if (sk_ctl & SK_RXCTL_OWN) { 2036 /* Invalidate the descriptor -- it's not ready yet */ 2037 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2038 sc_if->sk_cdata.sk_rx_prod = i; 2039 break; 2040 } 2041 2042 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2043 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2044 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2045 2046 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2047 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2048 2049 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2050 m = cur_rx->sk_mbuf; 2051 cur_rx->sk_mbuf = NULL; 2052 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2053 2054 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2055 2056 SK_INC(i, SK_RX_RING_CNT); 2057 2058 if (rxstat & XM_RXSTAT_ERRFRAME) { 2059 ifp->if_ierrors++; 2060 sk_newbuf(sc_if, cur, m, dmamap); 2061 continue; 2062 } 2063 2064 /* 2065 * Try to allocate a new jumbo buffer. If that 2066 * fails, copy the packet to mbufs and put the 2067 * jumbo buffer back in the ring so it can be 2068 * re-used. If allocating mbufs fails, then we 2069 * have to drop the packet. 2070 */ 2071 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2072 struct mbuf *m0; 2073 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2074 total_len + ETHER_ALIGN, 0, ifp, NULL); 2075 sk_newbuf(sc_if, cur, m, dmamap); 2076 if (m0 == NULL) { 2077 aprint_error_dev(sc_if->sk_dev, "no receive " 2078 "buffers available -- packet dropped!\n"); 2079 ifp->if_ierrors++; 2080 continue; 2081 } 2082 m_adj(m0, ETHER_ALIGN); 2083 m = m0; 2084 } else { 2085 m->m_pkthdr.rcvif = ifp; 2086 m->m_pkthdr.len = m->m_len = total_len; 2087 } 2088 2089 ifp->if_ipackets++; 2090 2091 #if NBPFILTER > 0 2092 if (ifp->if_bpf) 2093 bpf_mtap(ifp->if_bpf, m); 2094 #endif 2095 /* pass it on. */ 2096 (*ifp->if_input)(ifp, m); 2097 } 2098 } 2099 2100 void 2101 sk_txeof(struct sk_if_softc *sc_if) 2102 { 2103 struct sk_softc *sc = sc_if->sk_softc; 2104 struct sk_tx_desc *cur_tx; 2105 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2106 u_int32_t idx, sk_ctl; 2107 struct sk_txmap_entry *entry; 2108 2109 DPRINTFN(3, ("sk_txeof\n")); 2110 2111 /* 2112 * Go through our tx ring and free mbufs for those 2113 * frames that have been sent. 2114 */ 2115 idx = sc_if->sk_cdata.sk_tx_cons; 2116 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2117 SK_CDTXSYNC(sc_if, idx, 1, 2118 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2119 2120 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2121 sk_ctl = le32toh(cur_tx->sk_ctl); 2122 #ifdef SK_DEBUG 2123 if (skdebug >= 3) 2124 sk_dump_txdesc(cur_tx, idx); 2125 #endif 2126 if (sk_ctl & SK_TXCTL_OWN) { 2127 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2128 break; 2129 } 2130 if (sk_ctl & SK_TXCTL_LASTFRAG) 2131 ifp->if_opackets++; 2132 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2133 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2134 2135 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2136 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2137 2138 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2139 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2140 2141 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2142 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2143 link); 2144 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2145 } 2146 sc_if->sk_cdata.sk_tx_cnt--; 2147 SK_INC(idx, SK_TX_RING_CNT); 2148 } 2149 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2150 ifp->if_timer = 0; 2151 else /* nudge chip to keep tx ring moving */ 2152 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2153 2154 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2155 ifp->if_flags &= ~IFF_OACTIVE; 2156 2157 sc_if->sk_cdata.sk_tx_cons = idx; 2158 } 2159 2160 void 2161 sk_tick(void *xsc_if) 2162 { 2163 struct sk_if_softc *sc_if = xsc_if; 2164 struct mii_data *mii = &sc_if->sk_mii; 2165 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2166 int i; 2167 2168 DPRINTFN(3, ("sk_tick\n")); 2169 2170 if (!(ifp->if_flags & IFF_UP)) 2171 return; 2172 2173 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2174 sk_intr_bcom(sc_if); 2175 return; 2176 } 2177 2178 /* 2179 * According to SysKonnect, the correct way to verify that 2180 * the link has come back up is to poll bit 0 of the GPIO 2181 * register three times. This pin has the signal from the 2182 * link sync pin connected to it; if we read the same link 2183 * state 3 times in a row, we know the link is up. 2184 */ 2185 for (i = 0; i < 3; i++) { 2186 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2187 break; 2188 } 2189 2190 if (i != 3) { 2191 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2192 return; 2193 } 2194 2195 /* Turn the GP0 interrupt back on. */ 2196 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2197 SK_XM_READ_2(sc_if, XM_ISR); 2198 mii_tick(mii); 2199 mii_pollstat(mii); 2200 callout_stop(&sc_if->sk_tick_ch); 2201 } 2202 2203 void 2204 sk_intr_bcom(struct sk_if_softc *sc_if) 2205 { 2206 struct mii_data *mii = &sc_if->sk_mii; 2207 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2208 int status; 2209 2210 2211 DPRINTFN(3, ("sk_intr_bcom\n")); 2212 2213 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2214 2215 /* 2216 * Read the PHY interrupt register to make sure 2217 * we clear any pending interrupts. 2218 */ 2219 status = sk_xmac_miibus_readreg(sc_if->sk_dev, 2220 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2221 2222 if (!(ifp->if_flags & IFF_RUNNING)) { 2223 sk_init_xmac(sc_if); 2224 return; 2225 } 2226 2227 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2228 int lstat; 2229 lstat = sk_xmac_miibus_readreg(sc_if->sk_dev, 2230 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2231 2232 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2233 (void)mii_mediachg(mii); 2234 /* Turn off the link LED. */ 2235 SK_IF_WRITE_1(sc_if, 0, 2236 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2237 sc_if->sk_link = 0; 2238 } else if (status & BRGPHY_ISR_LNK_CHG) { 2239 sk_xmac_miibus_writereg(sc_if->sk_dev, 2240 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2241 mii_tick(mii); 2242 sc_if->sk_link = 1; 2243 /* Turn on the link LED. */ 2244 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2245 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2246 SK_LINKLED_BLINK_OFF); 2247 mii_pollstat(mii); 2248 } else { 2249 mii_tick(mii); 2250 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2251 } 2252 } 2253 2254 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2255 } 2256 2257 void 2258 sk_intr_xmac(struct sk_if_softc *sc_if) 2259 { 2260 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2261 2262 DPRINTFN(3, ("sk_intr_xmac\n")); 2263 2264 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2265 if (status & XM_ISR_GP0_SET) { 2266 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2267 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2268 } 2269 2270 if (status & XM_ISR_AUTONEG_DONE) { 2271 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2272 } 2273 } 2274 2275 if (status & XM_IMR_TX_UNDERRUN) 2276 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2277 2278 if (status & XM_IMR_RX_OVERRUN) 2279 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2280 } 2281 2282 void 2283 sk_intr_yukon(struct sk_if_softc *sc_if) 2284 { 2285 int status; 2286 2287 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2288 2289 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2290 } 2291 2292 int 2293 sk_intr(void *xsc) 2294 { 2295 struct sk_softc *sc = xsc; 2296 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2297 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2298 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2299 u_int32_t status; 2300 int claimed = 0; 2301 2302 if (sc_if0 != NULL) 2303 ifp0 = &sc_if0->sk_ethercom.ec_if; 2304 if (sc_if1 != NULL) 2305 ifp1 = &sc_if1->sk_ethercom.ec_if; 2306 2307 for (;;) { 2308 status = CSR_READ_4(sc, SK_ISSR); 2309 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2310 2311 if (!(status & sc->sk_intrmask)) 2312 break; 2313 2314 claimed = 1; 2315 2316 /* Handle receive interrupts first. */ 2317 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2318 sk_rxeof(sc_if0); 2319 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2320 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2321 } 2322 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2323 sk_rxeof(sc_if1); 2324 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2325 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2326 } 2327 2328 /* Then transmit interrupts. */ 2329 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2330 sk_txeof(sc_if0); 2331 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2332 SK_TXBMU_CLR_IRQ_EOF); 2333 } 2334 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2335 sk_txeof(sc_if1); 2336 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2337 SK_TXBMU_CLR_IRQ_EOF); 2338 } 2339 2340 /* Then MAC interrupts. */ 2341 if (sc_if0 && (status & SK_ISR_MAC1) && 2342 (ifp0->if_flags & IFF_RUNNING)) { 2343 if (sc->sk_type == SK_GENESIS) 2344 sk_intr_xmac(sc_if0); 2345 else 2346 sk_intr_yukon(sc_if0); 2347 } 2348 2349 if (sc_if1 && (status & SK_ISR_MAC2) && 2350 (ifp1->if_flags & IFF_RUNNING)) { 2351 if (sc->sk_type == SK_GENESIS) 2352 sk_intr_xmac(sc_if1); 2353 else 2354 sk_intr_yukon(sc_if1); 2355 2356 } 2357 2358 if (status & SK_ISR_EXTERNAL_REG) { 2359 if (sc_if0 != NULL && 2360 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2361 sk_intr_bcom(sc_if0); 2362 2363 if (sc_if1 != NULL && 2364 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2365 sk_intr_bcom(sc_if1); 2366 } 2367 } 2368 2369 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2370 2371 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2372 sk_start(ifp0); 2373 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2374 sk_start(ifp1); 2375 2376 #if NRND > 0 2377 if (RND_ENABLED(&sc->rnd_source)) 2378 rnd_add_uint32(&sc->rnd_source, status); 2379 #endif 2380 2381 if (sc->sk_int_mod_pending) 2382 sk_update_int_mod(sc); 2383 2384 return claimed; 2385 } 2386 2387 void 2388 sk_init_xmac(struct sk_if_softc *sc_if) 2389 { 2390 struct sk_softc *sc = sc_if->sk_softc; 2391 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2392 static const struct sk_bcom_hack bhack[] = { 2393 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2394 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2395 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2396 { 0, 0 } }; 2397 2398 DPRINTFN(1, ("sk_init_xmac\n")); 2399 2400 /* Unreset the XMAC. */ 2401 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2402 DELAY(1000); 2403 2404 /* Reset the XMAC's internal state. */ 2405 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2406 2407 /* Save the XMAC II revision */ 2408 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2409 2410 /* 2411 * Perform additional initialization for external PHYs, 2412 * namely for the 1000baseTX cards that use the XMAC's 2413 * GMII mode. 2414 */ 2415 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2416 int i = 0; 2417 u_int32_t val; 2418 2419 /* Take PHY out of reset. */ 2420 val = sk_win_read_4(sc, SK_GPIO); 2421 if (sc_if->sk_port == SK_PORT_A) 2422 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2423 else 2424 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2425 sk_win_write_4(sc, SK_GPIO, val); 2426 2427 /* Enable GMII mode on the XMAC. */ 2428 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2429 2430 sk_xmac_miibus_writereg(sc_if->sk_dev, 2431 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2432 DELAY(10000); 2433 sk_xmac_miibus_writereg(sc_if->sk_dev, 2434 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2435 2436 /* 2437 * Early versions of the BCM5400 apparently have 2438 * a bug that requires them to have their reserved 2439 * registers initialized to some magic values. I don't 2440 * know what the numbers do, I'm just the messenger. 2441 */ 2442 if (sk_xmac_miibus_readreg(sc_if->sk_dev, 2443 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2444 while (bhack[i].reg) { 2445 sk_xmac_miibus_writereg(sc_if->sk_dev, 2446 SK_PHYADDR_BCOM, bhack[i].reg, 2447 bhack[i].val); 2448 i++; 2449 } 2450 } 2451 } 2452 2453 /* Set station address */ 2454 SK_XM_WRITE_2(sc_if, XM_PAR0, 2455 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2456 SK_XM_WRITE_2(sc_if, XM_PAR1, 2457 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2458 SK_XM_WRITE_2(sc_if, XM_PAR2, 2459 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2460 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2461 2462 if (ifp->if_flags & IFF_PROMISC) 2463 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2464 else 2465 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2466 2467 if (ifp->if_flags & IFF_BROADCAST) 2468 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2469 else 2470 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2471 2472 /* We don't need the FCS appended to the packet. */ 2473 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2474 2475 /* We want short frames padded to 60 bytes. */ 2476 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2477 2478 /* 2479 * Enable the reception of all error frames. This is is 2480 * a necessary evil due to the design of the XMAC. The 2481 * XMAC's receive FIFO is only 8K in size, however jumbo 2482 * frames can be up to 9000 bytes in length. When bad 2483 * frame filtering is enabled, the XMAC's RX FIFO operates 2484 * in 'store and forward' mode. For this to work, the 2485 * entire frame has to fit into the FIFO, but that means 2486 * that jumbo frames larger than 8192 bytes will be 2487 * truncated. Disabling all bad frame filtering causes 2488 * the RX FIFO to operate in streaming mode, in which 2489 * case the XMAC will start transfering frames out of the 2490 * RX FIFO as soon as the FIFO threshold is reached. 2491 */ 2492 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2493 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2494 XM_MODE_RX_INRANGELEN); 2495 2496 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2497 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2498 else 2499 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2500 2501 /* 2502 * Bump up the transmit threshold. This helps hold off transmit 2503 * underruns when we're blasting traffic from both ports at once. 2504 */ 2505 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2506 2507 /* Set multicast filter */ 2508 sk_setmulti(sc_if); 2509 2510 /* Clear and enable interrupts */ 2511 SK_XM_READ_2(sc_if, XM_ISR); 2512 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2513 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2514 else 2515 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2516 2517 /* Configure MAC arbiter */ 2518 switch (sc_if->sk_xmac_rev) { 2519 case XM_XMAC_REV_B2: 2520 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2521 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2522 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2523 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2524 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2525 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2526 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2527 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2528 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2529 break; 2530 case XM_XMAC_REV_C1: 2531 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2532 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2533 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2534 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2535 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2536 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2537 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2538 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2539 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2540 break; 2541 default: 2542 break; 2543 } 2544 sk_win_write_2(sc, SK_MACARB_CTL, 2545 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2546 2547 sc_if->sk_link = 1; 2548 } 2549 2550 void sk_init_yukon(struct sk_if_softc *sc_if) 2551 { 2552 u_int32_t /*mac, */phy; 2553 u_int16_t reg; 2554 struct sk_softc *sc; 2555 int i; 2556 2557 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2558 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2559 2560 sc = sc_if->sk_softc; 2561 if (sc->sk_type == SK_YUKON_LITE && 2562 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2563 /* Take PHY out of reset. */ 2564 sk_win_write_4(sc, SK_GPIO, 2565 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2566 } 2567 2568 2569 /* GMAC and GPHY Reset */ 2570 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2571 2572 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2573 2574 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2575 DELAY(1000); 2576 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2577 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2578 DELAY(1000); 2579 2580 2581 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2582 2583 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2584 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2585 2586 switch (sc_if->sk_softc->sk_pmd) { 2587 case IFM_1000_SX: 2588 case IFM_1000_LX: 2589 phy |= SK_GPHY_FIBER; 2590 break; 2591 2592 case IFM_1000_CX: 2593 case IFM_1000_T: 2594 phy |= SK_GPHY_COPPER; 2595 break; 2596 } 2597 2598 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2599 2600 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2601 DELAY(1000); 2602 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2603 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2604 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2605 2606 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2607 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2608 2609 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2610 2611 /* unused read of the interrupt source register */ 2612 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2613 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2614 2615 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2616 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2617 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2618 2619 /* MIB Counter Clear Mode set */ 2620 reg |= YU_PAR_MIB_CLR; 2621 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2622 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2623 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2624 2625 /* MIB Counter Clear Mode clear */ 2626 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2627 reg &= ~YU_PAR_MIB_CLR; 2628 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2629 2630 /* receive control reg */ 2631 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2632 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2633 YU_RCR_CRCR); 2634 2635 /* transmit parameter register */ 2636 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2637 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2638 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2639 2640 /* serial mode register */ 2641 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2642 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2643 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2644 YU_SMR_IPG_DATA(0x1e)); 2645 2646 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2647 /* Setup Yukon's address */ 2648 for (i = 0; i < 3; i++) { 2649 /* Write Source Address 1 (unicast filter) */ 2650 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2651 sc_if->sk_enaddr[i * 2] | 2652 sc_if->sk_enaddr[i * 2 + 1] << 8); 2653 } 2654 2655 for (i = 0; i < 3; i++) { 2656 reg = sk_win_read_2(sc_if->sk_softc, 2657 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2658 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2659 } 2660 2661 /* Set multicast filter */ 2662 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2663 sk_setmulti(sc_if); 2664 2665 /* enable interrupt mask for counter overflows */ 2666 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2667 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2668 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2669 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2670 2671 /* Configure RX MAC FIFO */ 2672 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2673 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2674 2675 /* Configure TX MAC FIFO */ 2676 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2677 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2678 2679 DPRINTFN(6, ("sk_init_yukon: end\n")); 2680 } 2681 2682 /* 2683 * Note that to properly initialize any part of the GEnesis chip, 2684 * you first have to take it out of reset mode. 2685 */ 2686 int 2687 sk_init(struct ifnet *ifp) 2688 { 2689 struct sk_if_softc *sc_if = ifp->if_softc; 2690 struct sk_softc *sc = sc_if->sk_softc; 2691 struct mii_data *mii = &sc_if->sk_mii; 2692 int rc = 0, s; 2693 u_int32_t imr, imtimer_ticks; 2694 2695 DPRINTFN(1, ("sk_init\n")); 2696 2697 s = splnet(); 2698 2699 if (ifp->if_flags & IFF_RUNNING) { 2700 splx(s); 2701 return 0; 2702 } 2703 2704 /* Cancel pending I/O and free all RX/TX buffers. */ 2705 sk_stop(ifp,0); 2706 2707 if (sc->sk_type == SK_GENESIS) { 2708 /* Configure LINK_SYNC LED */ 2709 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2710 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2711 SK_LINKLED_LINKSYNC_ON); 2712 2713 /* Configure RX LED */ 2714 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2715 SK_RXLEDCTL_COUNTER_START); 2716 2717 /* Configure TX LED */ 2718 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2719 SK_TXLEDCTL_COUNTER_START); 2720 } 2721 2722 /* Configure I2C registers */ 2723 2724 /* Configure XMAC(s) */ 2725 switch (sc->sk_type) { 2726 case SK_GENESIS: 2727 sk_init_xmac(sc_if); 2728 break; 2729 case SK_YUKON: 2730 case SK_YUKON_LITE: 2731 case SK_YUKON_LP: 2732 sk_init_yukon(sc_if); 2733 break; 2734 } 2735 if ((rc = mii_mediachg(mii)) == ENXIO) 2736 rc = 0; 2737 else if (rc != 0) 2738 goto out; 2739 2740 if (sc->sk_type == SK_GENESIS) { 2741 /* Configure MAC FIFOs */ 2742 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2743 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2744 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2745 2746 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2747 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2748 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2749 } 2750 2751 /* Configure transmit arbiter(s) */ 2752 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2753 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2754 2755 /* Configure RAMbuffers */ 2756 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2757 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2758 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2759 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2760 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2761 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2762 2763 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2764 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2765 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2766 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2767 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2768 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2769 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2770 2771 /* Configure BMUs */ 2772 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2773 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2774 SK_RX_RING_ADDR(sc_if, 0)); 2775 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2776 2777 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2778 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2779 SK_TX_RING_ADDR(sc_if, 0)); 2780 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2781 2782 /* Init descriptors */ 2783 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2784 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2785 "memory for rx buffers\n"); 2786 sk_stop(ifp,0); 2787 splx(s); 2788 return ENOBUFS; 2789 } 2790 2791 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2792 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2793 "memory for tx buffers\n"); 2794 sk_stop(ifp,0); 2795 splx(s); 2796 return ENOBUFS; 2797 } 2798 2799 /* Set interrupt moderation if changed via sysctl. */ 2800 switch (sc->sk_type) { 2801 case SK_GENESIS: 2802 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2803 break; 2804 case SK_YUKON_EC: 2805 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2806 break; 2807 default: 2808 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2809 } 2810 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2811 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2812 sk_win_write_4(sc, SK_IMTIMERINIT, 2813 SK_IM_USECS(sc->sk_int_mod)); 2814 aprint_verbose_dev(sc->sk_dev, 2815 "interrupt moderation is %d us\n", sc->sk_int_mod); 2816 } 2817 2818 /* Configure interrupt handling */ 2819 CSR_READ_4(sc, SK_ISSR); 2820 if (sc_if->sk_port == SK_PORT_A) 2821 sc->sk_intrmask |= SK_INTRS1; 2822 else 2823 sc->sk_intrmask |= SK_INTRS2; 2824 2825 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2826 2827 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2828 2829 /* Start BMUs. */ 2830 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2831 2832 if (sc->sk_type == SK_GENESIS) { 2833 /* Enable XMACs TX and RX state machines */ 2834 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2835 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2836 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2837 } 2838 2839 if (SK_YUKON_FAMILY(sc->sk_type)) { 2840 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2841 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2842 #if 0 2843 /* XXX disable 100Mbps and full duplex mode? */ 2844 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2845 #endif 2846 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2847 } 2848 2849 2850 ifp->if_flags |= IFF_RUNNING; 2851 ifp->if_flags &= ~IFF_OACTIVE; 2852 2853 out: 2854 splx(s); 2855 return rc; 2856 } 2857 2858 void 2859 sk_stop(struct ifnet *ifp, int disable) 2860 { 2861 struct sk_if_softc *sc_if = ifp->if_softc; 2862 struct sk_softc *sc = sc_if->sk_softc; 2863 int i; 2864 2865 DPRINTFN(1, ("sk_stop\n")); 2866 2867 callout_stop(&sc_if->sk_tick_ch); 2868 2869 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2870 u_int32_t val; 2871 2872 /* Put PHY back into reset. */ 2873 val = sk_win_read_4(sc, SK_GPIO); 2874 if (sc_if->sk_port == SK_PORT_A) { 2875 val |= SK_GPIO_DIR0; 2876 val &= ~SK_GPIO_DAT0; 2877 } else { 2878 val |= SK_GPIO_DIR2; 2879 val &= ~SK_GPIO_DAT2; 2880 } 2881 sk_win_write_4(sc, SK_GPIO, val); 2882 } 2883 2884 /* Turn off various components of this interface. */ 2885 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2886 switch (sc->sk_type) { 2887 case SK_GENESIS: 2888 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2889 SK_TXMACCTL_XMAC_RESET); 2890 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2891 break; 2892 case SK_YUKON: 2893 case SK_YUKON_LITE: 2894 case SK_YUKON_LP: 2895 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2896 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2897 break; 2898 } 2899 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2900 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2901 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2902 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2903 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2904 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2905 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2906 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2907 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2908 2909 /* Disable interrupts */ 2910 if (sc_if->sk_port == SK_PORT_A) 2911 sc->sk_intrmask &= ~SK_INTRS1; 2912 else 2913 sc->sk_intrmask &= ~SK_INTRS2; 2914 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2915 2916 SK_XM_READ_2(sc_if, XM_ISR); 2917 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2918 2919 /* Free RX and TX mbufs still in the queues. */ 2920 for (i = 0; i < SK_RX_RING_CNT; i++) { 2921 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2922 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2923 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2924 } 2925 } 2926 2927 for (i = 0; i < SK_TX_RING_CNT; i++) { 2928 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2929 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2930 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2931 } 2932 } 2933 2934 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2935 } 2936 2937 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 2938 skc_probe, skc_attach, NULL, NULL); 2939 2940 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 2941 sk_probe, sk_attach, NULL, NULL); 2942 2943 #ifdef SK_DEBUG 2944 void 2945 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2946 { 2947 #define DESC_PRINT(X) \ 2948 if (X) \ 2949 printf("txdesc[%d]." #X "=%#x\n", \ 2950 idx, X); 2951 2952 DESC_PRINT(le32toh(desc->sk_ctl)); 2953 DESC_PRINT(le32toh(desc->sk_next)); 2954 DESC_PRINT(le32toh(desc->sk_data_lo)); 2955 DESC_PRINT(le32toh(desc->sk_data_hi)); 2956 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2957 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2958 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2959 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2960 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2961 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2962 #undef PRINT 2963 } 2964 2965 void 2966 sk_dump_bytes(const char *data, int len) 2967 { 2968 int c, i, j; 2969 2970 for (i = 0; i < len; i += 16) { 2971 printf("%08x ", i); 2972 c = len - i; 2973 if (c > 16) c = 16; 2974 2975 for (j = 0; j < c; j++) { 2976 printf("%02x ", data[i + j] & 0xff); 2977 if ((j & 0xf) == 7 && j > 0) 2978 printf(" "); 2979 } 2980 2981 for (; j < 16; j++) 2982 printf(" "); 2983 printf(" "); 2984 2985 for (j = 0; j < c; j++) { 2986 int ch = data[i + j] & 0xff; 2987 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2988 } 2989 2990 printf("\n"); 2991 2992 if (c < 16) 2993 break; 2994 } 2995 } 2996 2997 void 2998 sk_dump_mbuf(struct mbuf *m) 2999 { 3000 int count = m->m_pkthdr.len; 3001 3002 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3003 3004 while (count > 0 && m) { 3005 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3006 m, m->m_data, m->m_len); 3007 sk_dump_bytes(mtod(m, char *), m->m_len); 3008 3009 count -= m->m_len; 3010 m = m->m_next; 3011 } 3012 } 3013 #endif 3014 3015 static int 3016 sk_sysctl_handler(SYSCTLFN_ARGS) 3017 { 3018 int error, t; 3019 struct sysctlnode node; 3020 struct sk_softc *sc; 3021 3022 node = *rnode; 3023 sc = node.sysctl_data; 3024 t = sc->sk_int_mod; 3025 node.sysctl_data = &t; 3026 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3027 if (error || newp == NULL) 3028 return error; 3029 3030 if (t < SK_IM_MIN || t > SK_IM_MAX) 3031 return EINVAL; 3032 3033 /* update the softc with sysctl-changed value, and mark 3034 for hardware update */ 3035 sc->sk_int_mod = t; 3036 sc->sk_int_mod_pending = 1; 3037 return 0; 3038 } 3039 3040 /* 3041 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3042 * set up in skc_attach() 3043 */ 3044 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3045 { 3046 int rc; 3047 const struct sysctlnode *node; 3048 3049 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3050 0, CTLTYPE_NODE, "hw", NULL, 3051 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3052 goto err; 3053 } 3054 3055 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3056 0, CTLTYPE_NODE, "sk", 3057 SYSCTL_DESCR("sk interface controls"), 3058 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3059 goto err; 3060 } 3061 3062 sk_root_num = node->sysctl_num; 3063 return; 3064 3065 err: 3066 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3067 } 3068
Indexes created Mon Oct 13 16:09:52 GMT 2025