if_sk.c revision 1.50
1 /* $NetBSD: if_sk.c,v 1.50 2008/06/20 16:28:36 cube Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.50 2008/06/20 16:28:36 cube Exp $"); 119 120 #include "bpfilter.h" 121 #include "rnd.h" 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/sockio.h> 126 #include <sys/mbuf.h> 127 #include <sys/malloc.h> 128 #include <sys/mutex.h> 129 #include <sys/kernel.h> 130 #include <sys/socket.h> 131 #include <sys/device.h> 132 #include <sys/queue.h> 133 #include <sys/callout.h> 134 #include <sys/sysctl.h> 135 #include <sys/endian.h> 136 137 #include <net/if.h> 138 #include <net/if_dl.h> 139 #include <net/if_types.h> 140 141 #include <net/if_media.h> 142 143 #if NBPFILTER > 0 144 #include <net/bpf.h> 145 #endif 146 #if NRND > 0 147 #include <sys/rnd.h> 148 #endif 149 150 #include <dev/mii/mii.h> 151 #include <dev/mii/miivar.h> 152 #include <dev/mii/brgphyreg.h> 153 154 #include <dev/pci/pcireg.h> 155 #include <dev/pci/pcivar.h> 156 #include <dev/pci/pcidevs.h> 157 158 /* #define SK_USEIOSPACE */ 159 160 #include <dev/pci/if_skreg.h> 161 #include <dev/pci/if_skvar.h> 162 163 int skc_probe(struct device *, struct cfdata *, void *); 164 void skc_attach(struct device *, struct device *self, void *aux); 165 int sk_probe(struct device *, struct cfdata *, void *); 166 void sk_attach(struct device *, struct device *self, void *aux); 167 int skcprint(void *, const char *); 168 int sk_intr(void *); 169 void sk_intr_bcom(struct sk_if_softc *); 170 void sk_intr_xmac(struct sk_if_softc *); 171 void sk_intr_yukon(struct sk_if_softc *); 172 void sk_rxeof(struct sk_if_softc *); 173 void sk_txeof(struct sk_if_softc *); 174 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 175 void sk_start(struct ifnet *); 176 int sk_ioctl(struct ifnet *, u_long, void *); 177 int sk_init(struct ifnet *); 178 void sk_init_xmac(struct sk_if_softc *); 179 void sk_init_yukon(struct sk_if_softc *); 180 void sk_stop(struct ifnet *, int); 181 void sk_watchdog(struct ifnet *); 182 void sk_shutdown(void *); 183 int sk_ifmedia_upd(struct ifnet *); 184 void sk_reset(struct sk_softc *); 185 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 186 int sk_alloc_jumbo_mem(struct sk_if_softc *); 187 void sk_free_jumbo_mem(struct sk_if_softc *); 188 void *sk_jalloc(struct sk_if_softc *); 189 void sk_jfree(struct mbuf *, void *, size_t, void *); 190 int sk_init_rx_ring(struct sk_if_softc *); 191 int sk_init_tx_ring(struct sk_if_softc *); 192 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 193 void sk_vpd_read_res(struct sk_softc *, 194 struct vpd_res *, int); 195 void sk_vpd_read(struct sk_softc *); 196 197 void sk_update_int_mod(struct sk_softc *); 198 199 int sk_xmac_miibus_readreg(struct device *, int, int); 200 void sk_xmac_miibus_writereg(struct device *, int, int, int); 201 void sk_xmac_miibus_statchg(struct device *); 202 203 int sk_marv_miibus_readreg(struct device *, int, int); 204 void sk_marv_miibus_writereg(struct device *, int, int, int); 205 void sk_marv_miibus_statchg(struct device *); 206 207 u_int32_t sk_xmac_hash(void *); 208 u_int32_t sk_yukon_hash(void *); 209 void sk_setfilt(struct sk_if_softc *, void *, int); 210 void sk_setmulti(struct sk_if_softc *); 211 void sk_tick(void *); 212 213 /* #define SK_DEBUG 2 */ 214 #ifdef SK_DEBUG 215 #define DPRINTF(x) if (skdebug) printf x 216 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 217 int skdebug = SK_DEBUG; 218 219 void sk_dump_txdesc(struct sk_tx_desc *, int); 220 void sk_dump_mbuf(struct mbuf *); 221 void sk_dump_bytes(const char *, int); 222 #else 223 #define DPRINTF(x) 224 #define DPRINTFN(n,x) 225 #endif 226 227 static int sk_sysctl_handler(SYSCTLFN_PROTO); 228 static int sk_root_num; 229 230 /* supported device vendors */ 231 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 232 static const struct sk_product { 233 pci_vendor_id_t sk_vendor; 234 pci_product_id_t sk_product; 235 } sk_products[] = { 236 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 237 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 238 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 239 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 240 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 241 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 242 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 243 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 244 { 0, 0, } 245 }; 246 247 #define SK_LINKSYS_EG1032_SUBID 0x00151737 248 249 static inline u_int32_t 250 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 251 { 252 #ifdef SK_USEIOSPACE 253 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 254 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 255 #else 256 return CSR_READ_4(sc, reg); 257 #endif 258 } 259 260 static inline u_int16_t 261 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 262 { 263 #ifdef SK_USEIOSPACE 264 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 265 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 266 #else 267 return CSR_READ_2(sc, reg); 268 #endif 269 } 270 271 static inline u_int8_t 272 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 273 { 274 #ifdef SK_USEIOSPACE 275 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 276 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 277 #else 278 return CSR_READ_1(sc, reg); 279 #endif 280 } 281 282 static inline void 283 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 284 { 285 #ifdef SK_USEIOSPACE 286 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 287 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 288 #else 289 CSR_WRITE_4(sc, reg, x); 290 #endif 291 } 292 293 static inline void 294 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 295 { 296 #ifdef SK_USEIOSPACE 297 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 298 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 299 #else 300 CSR_WRITE_2(sc, reg, x); 301 #endif 302 } 303 304 static inline void 305 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 306 { 307 #ifdef SK_USEIOSPACE 308 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 309 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 310 #else 311 CSR_WRITE_1(sc, reg, x); 312 #endif 313 } 314 315 /* 316 * The VPD EEPROM contains Vital Product Data, as suggested in 317 * the PCI 2.1 specification. The VPD data is separared into areas 318 * denoted by resource IDs. The SysKonnect VPD contains an ID string 319 * resource (the name of the adapter), a read-only area resource 320 * containing various key/data fields and a read/write area which 321 * can be used to store asset management information or log messages. 322 * We read the ID string and read-only into buffers attached to 323 * the controller softc structure for later use. At the moment, 324 * we only use the ID string during sk_attach(). 325 */ 326 u_int8_t 327 sk_vpd_readbyte(struct sk_softc *sc, int addr) 328 { 329 int i; 330 331 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 332 for (i = 0; i < SK_TIMEOUT; i++) { 333 DELAY(1); 334 if (sk_win_read_2(sc, 335 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 336 break; 337 } 338 339 if (i == SK_TIMEOUT) 340 return 0; 341 342 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 343 } 344 345 void 346 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 347 { 348 int i; 349 u_int8_t *ptr; 350 351 ptr = (u_int8_t *)res; 352 for (i = 0; i < sizeof(struct vpd_res); i++) 353 ptr[i] = sk_vpd_readbyte(sc, i + addr); 354 } 355 356 void 357 sk_vpd_read(struct sk_softc *sc) 358 { 359 int pos = 0, i; 360 struct vpd_res res; 361 362 if (sc->sk_vpd_prodname != NULL) 363 free(sc->sk_vpd_prodname, M_DEVBUF); 364 if (sc->sk_vpd_readonly != NULL) 365 free(sc->sk_vpd_readonly, M_DEVBUF); 366 sc->sk_vpd_prodname = NULL; 367 sc->sk_vpd_readonly = NULL; 368 369 sk_vpd_read_res(sc, &res, pos); 370 371 if (res.vr_id != VPD_RES_ID) { 372 aprint_error_dev(&sc->sk_dev, "bad VPD resource id: expected %x got %x\n", 373 VPD_RES_ID, res.vr_id); 374 return; 375 } 376 377 pos += sizeof(res); 378 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 379 if (sc->sk_vpd_prodname == NULL) 380 panic("sk_vpd_read"); 381 for (i = 0; i < res.vr_len; i++) 382 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 383 sc->sk_vpd_prodname[i] = '\0'; 384 pos += i; 385 386 sk_vpd_read_res(sc, &res, pos); 387 388 if (res.vr_id != VPD_RES_READ) { 389 aprint_error_dev(&sc->sk_dev, "bad VPD resource id: expected %x got %x\n", 390 VPD_RES_READ, res.vr_id); 391 return; 392 } 393 394 pos += sizeof(res); 395 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 396 if (sc->sk_vpd_readonly == NULL) 397 panic("sk_vpd_read"); 398 for (i = 0; i < res.vr_len ; i++) 399 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 400 } 401 402 int 403 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 404 { 405 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 406 int i; 407 408 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 409 410 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 411 return 0; 412 413 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 414 SK_XM_READ_2(sc_if, XM_PHY_DATA); 415 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 416 for (i = 0; i < SK_TIMEOUT; i++) { 417 DELAY(1); 418 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 419 XM_MMUCMD_PHYDATARDY) 420 break; 421 } 422 423 if (i == SK_TIMEOUT) { 424 aprint_error_dev(&sc_if->sk_dev, "phy failed to come ready\n"); 425 return 0; 426 } 427 } 428 DELAY(1); 429 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 430 } 431 432 void 433 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 434 { 435 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 436 int i; 437 438 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 439 440 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 441 for (i = 0; i < SK_TIMEOUT; i++) { 442 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 443 break; 444 } 445 446 if (i == SK_TIMEOUT) { 447 aprint_error_dev(&sc_if->sk_dev, "phy failed to come ready\n"); 448 return; 449 } 450 451 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 452 for (i = 0; i < SK_TIMEOUT; i++) { 453 DELAY(1); 454 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 455 break; 456 } 457 458 if (i == SK_TIMEOUT) 459 aprint_error_dev(&sc_if->sk_dev, "phy write timed out\n"); 460 } 461 462 void 463 sk_xmac_miibus_statchg(struct device *dev) 464 { 465 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 466 struct mii_data *mii = &sc_if->sk_mii; 467 468 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 469 470 /* 471 * If this is a GMII PHY, manually set the XMAC's 472 * duplex mode accordingly. 473 */ 474 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 475 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 476 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 477 else 478 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 479 } 480 } 481 482 int 483 sk_marv_miibus_readreg(struct device *dev, int phy, int reg) 484 { 485 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 486 u_int16_t val; 487 int i; 488 489 if (phy != 0 || 490 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 491 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 492 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 493 phy, reg)); 494 return 0; 495 } 496 497 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 498 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 499 500 for (i = 0; i < SK_TIMEOUT; i++) { 501 DELAY(1); 502 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 503 if (val & YU_SMICR_READ_VALID) 504 break; 505 } 506 507 if (i == SK_TIMEOUT) { 508 aprint_error_dev(&sc_if->sk_dev, "phy failed to come ready\n"); 509 return 0; 510 } 511 512 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 513 SK_TIMEOUT)); 514 515 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 516 517 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 518 phy, reg, val)); 519 520 return val; 521 } 522 523 void 524 sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val) 525 { 526 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 527 int i; 528 529 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 530 phy, reg, val)); 531 532 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 533 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 534 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 535 536 for (i = 0; i < SK_TIMEOUT; i++) { 537 DELAY(1); 538 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 539 break; 540 } 541 542 if (i == SK_TIMEOUT) 543 printf("%s: phy write timed out\n", device_xname(&sc_if->sk_dev)); 544 } 545 546 void 547 sk_marv_miibus_statchg(struct device *dev) 548 { 549 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 550 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 551 } 552 553 #define SK_HASH_BITS 6 554 555 u_int32_t 556 sk_xmac_hash(void *addr) 557 { 558 u_int32_t crc; 559 560 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 561 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 562 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 563 return crc; 564 } 565 566 u_int32_t 567 sk_yukon_hash(void *addr) 568 { 569 u_int32_t crc; 570 571 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 572 crc &= ((1 << SK_HASH_BITS) - 1); 573 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 574 return crc; 575 } 576 577 void 578 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 579 { 580 char *addr = addrv; 581 int base = XM_RXFILT_ENTRY(slot); 582 583 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 584 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 585 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 586 } 587 588 void 589 sk_setmulti(struct sk_if_softc *sc_if) 590 { 591 struct sk_softc *sc = sc_if->sk_softc; 592 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 593 u_int32_t hashes[2] = { 0, 0 }; 594 int h = 0, i; 595 struct ethercom *ec = &sc_if->sk_ethercom; 596 struct ether_multi *enm; 597 struct ether_multistep step; 598 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 599 600 /* First, zot all the existing filters. */ 601 switch (sc->sk_type) { 602 case SK_GENESIS: 603 for (i = 1; i < XM_RXFILT_MAX; i++) 604 sk_setfilt(sc_if, (void *)&dummy, i); 605 606 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 607 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 608 break; 609 case SK_YUKON: 610 case SK_YUKON_LITE: 611 case SK_YUKON_LP: 612 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 613 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 614 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 615 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 616 break; 617 } 618 619 /* Now program new ones. */ 620 allmulti: 621 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 622 hashes[0] = 0xFFFFFFFF; 623 hashes[1] = 0xFFFFFFFF; 624 } else { 625 i = 1; 626 /* First find the tail of the list. */ 627 ETHER_FIRST_MULTI(step, ec, enm); 628 while (enm != NULL) { 629 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 630 ETHER_ADDR_LEN)) { 631 ifp->if_flags |= IFF_ALLMULTI; 632 goto allmulti; 633 } 634 DPRINTFN(2,("multicast address %s\n", 635 ether_sprintf(enm->enm_addrlo))); 636 /* 637 * Program the first XM_RXFILT_MAX multicast groups 638 * into the perfect filter. For all others, 639 * use the hash table. 640 */ 641 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 642 sk_setfilt(sc_if, enm->enm_addrlo, i); 643 i++; 644 } 645 else { 646 switch (sc->sk_type) { 647 case SK_GENESIS: 648 h = sk_xmac_hash(enm->enm_addrlo); 649 break; 650 case SK_YUKON: 651 case SK_YUKON_LITE: 652 case SK_YUKON_LP: 653 h = sk_yukon_hash(enm->enm_addrlo); 654 break; 655 } 656 if (h < 32) 657 hashes[0] |= (1 << h); 658 else 659 hashes[1] |= (1 << (h - 32)); 660 } 661 662 ETHER_NEXT_MULTI(step, enm); 663 } 664 } 665 666 switch (sc->sk_type) { 667 case SK_GENESIS: 668 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 669 XM_MODE_RX_USE_PERFECT); 670 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 671 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 672 break; 673 case SK_YUKON: 674 case SK_YUKON_LITE: 675 case SK_YUKON_LP: 676 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 677 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 678 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 679 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 680 break; 681 } 682 } 683 684 int 685 sk_init_rx_ring(struct sk_if_softc *sc_if) 686 { 687 struct sk_chain_data *cd = &sc_if->sk_cdata; 688 struct sk_ring_data *rd = sc_if->sk_rdata; 689 int i; 690 691 bzero((char *)rd->sk_rx_ring, 692 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 693 694 for (i = 0; i < SK_RX_RING_CNT; i++) { 695 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 696 if (i == (SK_RX_RING_CNT - 1)) { 697 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 698 rd->sk_rx_ring[i].sk_next = 699 htole32(SK_RX_RING_ADDR(sc_if, 0)); 700 } else { 701 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 702 rd->sk_rx_ring[i].sk_next = 703 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 704 } 705 } 706 707 for (i = 0; i < SK_RX_RING_CNT; i++) { 708 if (sk_newbuf(sc_if, i, NULL, 709 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 710 aprint_error_dev(&sc_if->sk_dev, "failed alloc of %dth mbuf\n", i); 711 return ENOBUFS; 712 } 713 } 714 sc_if->sk_cdata.sk_rx_prod = 0; 715 sc_if->sk_cdata.sk_rx_cons = 0; 716 717 return 0; 718 } 719 720 int 721 sk_init_tx_ring(struct sk_if_softc *sc_if) 722 { 723 struct sk_chain_data *cd = &sc_if->sk_cdata; 724 struct sk_ring_data *rd = sc_if->sk_rdata; 725 int i; 726 727 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 728 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 729 730 for (i = 0; i < SK_TX_RING_CNT; i++) { 731 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 732 if (i == (SK_TX_RING_CNT - 1)) { 733 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 734 rd->sk_tx_ring[i].sk_next = 735 htole32(SK_TX_RING_ADDR(sc_if, 0)); 736 } else { 737 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 738 rd->sk_tx_ring[i].sk_next = 739 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 740 } 741 } 742 743 sc_if->sk_cdata.sk_tx_prod = 0; 744 sc_if->sk_cdata.sk_tx_cons = 0; 745 sc_if->sk_cdata.sk_tx_cnt = 0; 746 747 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 748 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 749 750 return 0; 751 } 752 753 int 754 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 755 bus_dmamap_t dmamap) 756 { 757 struct mbuf *m_new = NULL; 758 struct sk_chain *c; 759 struct sk_rx_desc *r; 760 761 if (m == NULL) { 762 void *buf = NULL; 763 764 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 765 if (m_new == NULL) { 766 aprint_error_dev(&sc_if->sk_dev, "no memory for rx list -- " 767 "packet dropped!\n"); 768 return ENOBUFS; 769 } 770 771 /* Allocate the jumbo buffer */ 772 buf = sk_jalloc(sc_if); 773 if (buf == NULL) { 774 m_freem(m_new); 775 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 776 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 777 return ENOBUFS; 778 } 779 780 /* Attach the buffer to the mbuf */ 781 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 782 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 783 784 } else { 785 /* 786 * We're re-using a previously allocated mbuf; 787 * be sure to re-init pointers and lengths to 788 * default values. 789 */ 790 m_new = m; 791 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 792 m_new->m_data = m_new->m_ext.ext_buf; 793 } 794 m_adj(m_new, ETHER_ALIGN); 795 796 c = &sc_if->sk_cdata.sk_rx_chain[i]; 797 r = c->sk_desc; 798 c->sk_mbuf = m_new; 799 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 800 (((vaddr_t)m_new->m_data 801 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 802 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 803 804 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 805 806 return 0; 807 } 808 809 /* 810 * Memory management for jumbo frames. 811 */ 812 813 int 814 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 815 { 816 struct sk_softc *sc = sc_if->sk_softc; 817 char *ptr, *kva; 818 bus_dma_segment_t seg; 819 int i, rseg, state, error; 820 struct sk_jpool_entry *entry; 821 822 state = error = 0; 823 824 /* Grab a big chunk o' storage. */ 825 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 826 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 827 aprint_error_dev(&sc->sk_dev, "can't alloc rx buffers\n"); 828 return ENOBUFS; 829 } 830 831 state = 1; 832 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 833 BUS_DMA_NOWAIT)) { 834 aprint_error_dev(&sc->sk_dev, "can't map dma buffers (%d bytes)\n", 835 SK_JMEM); 836 error = ENOBUFS; 837 goto out; 838 } 839 840 state = 2; 841 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 842 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 843 aprint_error_dev(&sc->sk_dev, "can't create dma map\n"); 844 error = ENOBUFS; 845 goto out; 846 } 847 848 state = 3; 849 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 850 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 851 aprint_error_dev(&sc->sk_dev, "can't load dma map\n"); 852 error = ENOBUFS; 853 goto out; 854 } 855 856 state = 4; 857 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 858 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 859 860 LIST_INIT(&sc_if->sk_jfree_listhead); 861 LIST_INIT(&sc_if->sk_jinuse_listhead); 862 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 863 864 /* 865 * Now divide it up into 9K pieces and save the addresses 866 * in an array. 867 */ 868 ptr = sc_if->sk_cdata.sk_jumbo_buf; 869 for (i = 0; i < SK_JSLOTS; i++) { 870 sc_if->sk_cdata.sk_jslots[i] = ptr; 871 ptr += SK_JLEN; 872 entry = malloc(sizeof(struct sk_jpool_entry), 873 M_DEVBUF, M_NOWAIT); 874 if (entry == NULL) { 875 aprint_error_dev(&sc->sk_dev, "no memory for jumbo buffer queue!\n"); 876 error = ENOBUFS; 877 goto out; 878 } 879 entry->slot = i; 880 if (i) 881 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 882 entry, jpool_entries); 883 else 884 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 885 entry, jpool_entries); 886 } 887 out: 888 if (error != 0) { 889 switch (state) { 890 case 4: 891 bus_dmamap_unload(sc->sc_dmatag, 892 sc_if->sk_cdata.sk_rx_jumbo_map); 893 case 3: 894 bus_dmamap_destroy(sc->sc_dmatag, 895 sc_if->sk_cdata.sk_rx_jumbo_map); 896 case 2: 897 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 898 case 1: 899 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 900 break; 901 default: 902 break; 903 } 904 } 905 906 return error; 907 } 908 909 /* 910 * Allocate a jumbo buffer. 911 */ 912 void * 913 sk_jalloc(struct sk_if_softc *sc_if) 914 { 915 struct sk_jpool_entry *entry; 916 917 mutex_enter(&sc_if->sk_jpool_mtx); 918 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 919 920 if (entry == NULL) { 921 mutex_exit(&sc_if->sk_jpool_mtx); 922 return NULL; 923 } 924 925 LIST_REMOVE(entry, jpool_entries); 926 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 927 mutex_exit(&sc_if->sk_jpool_mtx); 928 return sc_if->sk_cdata.sk_jslots[entry->slot]; 929 } 930 931 /* 932 * Release a jumbo buffer. 933 */ 934 void 935 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 936 { 937 struct sk_jpool_entry *entry; 938 struct sk_if_softc *sc; 939 int i; 940 941 /* Extract the softc struct pointer. */ 942 sc = (struct sk_if_softc *)arg; 943 944 if (sc == NULL) 945 panic("sk_jfree: can't find softc pointer!"); 946 947 /* calculate the slot this buffer belongs to */ 948 949 i = ((vaddr_t)buf 950 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 951 952 if ((i < 0) || (i >= SK_JSLOTS)) 953 panic("sk_jfree: asked to free buffer that we don't manage!"); 954 955 mutex_enter(&sc->sk_jpool_mtx); 956 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 957 if (entry == NULL) 958 panic("sk_jfree: buffer not in use!"); 959 entry->slot = i; 960 LIST_REMOVE(entry, jpool_entries); 961 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 962 mutex_exit(&sc->sk_jpool_mtx); 963 964 if (__predict_true(m != NULL)) 965 pool_cache_put(mb_cache, m); 966 } 967 968 /* 969 * Set media options. 970 */ 971 int 972 sk_ifmedia_upd(struct ifnet *ifp) 973 { 974 struct sk_if_softc *sc_if = ifp->if_softc; 975 int rc; 976 977 (void) sk_init(ifp); 978 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 979 return 0; 980 return rc; 981 } 982 983 int 984 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 985 { 986 struct sk_if_softc *sc_if = ifp->if_softc; 987 struct sk_softc *sc = sc_if->sk_softc; 988 int s, error = 0; 989 990 /* DPRINTFN(2, ("sk_ioctl\n")); */ 991 992 s = splnet(); 993 994 switch (command) { 995 996 case SIOCSIFFLAGS: 997 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 998 if (ifp->if_flags & IFF_UP) { 999 if (ifp->if_flags & IFF_RUNNING && 1000 ifp->if_flags & IFF_PROMISC && 1001 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1002 switch (sc->sk_type) { 1003 case SK_GENESIS: 1004 SK_XM_SETBIT_4(sc_if, XM_MODE, 1005 XM_MODE_RX_PROMISC); 1006 break; 1007 case SK_YUKON: 1008 case SK_YUKON_LITE: 1009 case SK_YUKON_LP: 1010 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1011 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1012 break; 1013 } 1014 sk_setmulti(sc_if); 1015 } else if (ifp->if_flags & IFF_RUNNING && 1016 !(ifp->if_flags & IFF_PROMISC) && 1017 sc_if->sk_if_flags & IFF_PROMISC) { 1018 switch (sc->sk_type) { 1019 case SK_GENESIS: 1020 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1021 XM_MODE_RX_PROMISC); 1022 break; 1023 case SK_YUKON: 1024 case SK_YUKON_LITE: 1025 case SK_YUKON_LP: 1026 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1027 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1028 break; 1029 } 1030 1031 sk_setmulti(sc_if); 1032 } else 1033 (void) sk_init(ifp); 1034 } else { 1035 if (ifp->if_flags & IFF_RUNNING) 1036 sk_stop(ifp,0); 1037 } 1038 sc_if->sk_if_flags = ifp->if_flags; 1039 error = 0; 1040 break; 1041 1042 default: 1043 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1044 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1045 break; 1046 1047 error = 0; 1048 1049 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1050 ; 1051 else if (ifp->if_flags & IFF_RUNNING) { 1052 sk_setmulti(sc_if); 1053 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1054 } 1055 break; 1056 } 1057 1058 splx(s); 1059 return error; 1060 } 1061 1062 void 1063 sk_update_int_mod(struct sk_softc *sc) 1064 { 1065 u_int32_t imtimer_ticks; 1066 1067 /* 1068 * Configure interrupt moderation. The moderation timer 1069 * defers interrupts specified in the interrupt moderation 1070 * timer mask based on the timeout specified in the interrupt 1071 * moderation timer init register. Each bit in the timer 1072 * register represents one tick, so to specify a timeout in 1073 * microseconds, we have to multiply by the correct number of 1074 * ticks-per-microsecond. 1075 */ 1076 switch (sc->sk_type) { 1077 case SK_GENESIS: 1078 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1079 break; 1080 case SK_YUKON_EC: 1081 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1082 break; 1083 default: 1084 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1085 } 1086 aprint_verbose_dev(&sc->sk_dev, "interrupt moderation is %d us\n", 1087 sc->sk_int_mod); 1088 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1089 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1090 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1091 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1092 sc->sk_int_mod_pending = 0; 1093 } 1094 1095 /* 1096 * Lookup: Check the PCI vendor and device, and return a pointer to 1097 * The structure if the IDs match against our list. 1098 */ 1099 1100 static const struct sk_product * 1101 sk_lookup(const struct pci_attach_args *pa) 1102 { 1103 const struct sk_product *psk; 1104 1105 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1106 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1107 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1108 return psk; 1109 } 1110 return NULL; 1111 } 1112 1113 /* 1114 * Probe for a SysKonnect GEnesis chip. 1115 */ 1116 1117 int 1118 skc_probe(struct device *parent, struct cfdata *match, 1119 void *aux) 1120 { 1121 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1122 const struct sk_product *psk; 1123 pcireg_t subid; 1124 1125 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1126 1127 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1128 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1129 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1130 subid == SK_LINKSYS_EG1032_SUBID) 1131 return 1; 1132 1133 if ((psk = sk_lookup(pa))) { 1134 return 1; 1135 } 1136 return 0; 1137 } 1138 1139 /* 1140 * Force the GEnesis into reset, then bring it out of reset. 1141 */ 1142 void sk_reset(struct sk_softc *sc) 1143 { 1144 DPRINTFN(2, ("sk_reset\n")); 1145 1146 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1147 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1148 if (SK_YUKON_FAMILY(sc->sk_type)) 1149 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1150 1151 DELAY(1000); 1152 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1153 DELAY(2); 1154 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1155 if (SK_YUKON_FAMILY(sc->sk_type)) 1156 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1157 1158 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1159 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1160 CSR_READ_2(sc, SK_LINK_CTRL))); 1161 1162 if (sc->sk_type == SK_GENESIS) { 1163 /* Configure packet arbiter */ 1164 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1165 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1166 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1167 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1168 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1169 } 1170 1171 /* Enable RAM interface */ 1172 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1173 1174 sk_update_int_mod(sc); 1175 } 1176 1177 int 1178 sk_probe(struct device *parent, struct cfdata *match, 1179 void *aux) 1180 { 1181 struct skc_attach_args *sa = aux; 1182 1183 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1184 return 0; 1185 1186 return 1; 1187 } 1188 1189 /* 1190 * Each XMAC chip is attached as a separate logical IP interface. 1191 * Single port cards will have only one logical interface of course. 1192 */ 1193 void 1194 sk_attach(struct device *parent, struct device *self, void *aux) 1195 { 1196 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1197 struct sk_softc *sc = (struct sk_softc *)parent; 1198 struct skc_attach_args *sa = aux; 1199 struct sk_txmap_entry *entry; 1200 struct ifnet *ifp; 1201 bus_dma_segment_t seg; 1202 bus_dmamap_t dmamap; 1203 void *kva; 1204 int i, rseg; 1205 1206 aprint_naive("\n"); 1207 1208 sc_if->sk_port = sa->skc_port; 1209 sc_if->sk_softc = sc; 1210 sc->sk_if[sa->skc_port] = sc_if; 1211 1212 if (sa->skc_port == SK_PORT_A) 1213 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1214 if (sa->skc_port == SK_PORT_B) 1215 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1216 1217 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1218 1219 /* 1220 * Get station address for this interface. Note that 1221 * dual port cards actually come with three station 1222 * addresses: one for each port, plus an extra. The 1223 * extra one is used by the SysKonnect driver software 1224 * as a 'virtual' station address for when both ports 1225 * are operating in failover mode. Currently we don't 1226 * use this extra address. 1227 */ 1228 for (i = 0; i < ETHER_ADDR_LEN; i++) 1229 sc_if->sk_enaddr[i] = 1230 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1231 1232 1233 aprint_normal(": Ethernet address %s\n", 1234 ether_sprintf(sc_if->sk_enaddr)); 1235 1236 /* 1237 * Set up RAM buffer addresses. The NIC will have a certain 1238 * amount of SRAM on it, somewhere between 512K and 2MB. We 1239 * need to divide this up a) between the transmitter and 1240 * receiver and b) between the two XMACs, if this is a 1241 * dual port NIC. Our algorithm is to divide up the memory 1242 * evenly so that everyone gets a fair share. 1243 */ 1244 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1245 u_int32_t chunk, val; 1246 1247 chunk = sc->sk_ramsize / 2; 1248 val = sc->sk_rboff / sizeof(u_int64_t); 1249 sc_if->sk_rx_ramstart = val; 1250 val += (chunk / sizeof(u_int64_t)); 1251 sc_if->sk_rx_ramend = val - 1; 1252 sc_if->sk_tx_ramstart = val; 1253 val += (chunk / sizeof(u_int64_t)); 1254 sc_if->sk_tx_ramend = val - 1; 1255 } else { 1256 u_int32_t chunk, val; 1257 1258 chunk = sc->sk_ramsize / 4; 1259 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1260 sizeof(u_int64_t); 1261 sc_if->sk_rx_ramstart = val; 1262 val += (chunk / sizeof(u_int64_t)); 1263 sc_if->sk_rx_ramend = val - 1; 1264 sc_if->sk_tx_ramstart = val; 1265 val += (chunk / sizeof(u_int64_t)); 1266 sc_if->sk_tx_ramend = val - 1; 1267 } 1268 1269 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1270 " tx_ramstart=%#x tx_ramend=%#x\n", 1271 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1272 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1273 1274 /* Read and save PHY type and set PHY address */ 1275 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1276 switch (sc_if->sk_phytype) { 1277 case SK_PHYTYPE_XMAC: 1278 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1279 break; 1280 case SK_PHYTYPE_BCOM: 1281 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1282 break; 1283 case SK_PHYTYPE_MARV_COPPER: 1284 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1285 break; 1286 default: 1287 aprint_error_dev(&sc->sk_dev, "unsupported PHY type: %d\n", 1288 sc_if->sk_phytype); 1289 return; 1290 } 1291 1292 /* Allocate the descriptor queues. */ 1293 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1294 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1295 aprint_error_dev(&sc->sk_dev, "can't alloc rx buffers\n"); 1296 goto fail; 1297 } 1298 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1299 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1300 aprint_error_dev(&sc_if->sk_dev, "can't map dma buffers (%lu bytes)\n", 1301 (u_long) sizeof(struct sk_ring_data)); 1302 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1303 goto fail; 1304 } 1305 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1306 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1307 &sc_if->sk_ring_map)) { 1308 aprint_error_dev(&sc_if->sk_dev, "can't create dma map\n"); 1309 bus_dmamem_unmap(sc->sc_dmatag, kva, 1310 sizeof(struct sk_ring_data)); 1311 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1312 goto fail; 1313 } 1314 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1315 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1316 aprint_error_dev(&sc_if->sk_dev, "can't load dma map\n"); 1317 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1318 bus_dmamem_unmap(sc->sc_dmatag, kva, 1319 sizeof(struct sk_ring_data)); 1320 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1321 goto fail; 1322 } 1323 1324 for (i = 0; i < SK_RX_RING_CNT; i++) 1325 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1326 1327 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1328 for (i = 0; i < SK_TX_RING_CNT; i++) { 1329 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1330 1331 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1332 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1333 aprint_error_dev(&sc_if->sk_dev, "Can't create TX dmamap\n"); 1334 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1335 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1336 bus_dmamem_unmap(sc->sc_dmatag, kva, 1337 sizeof(struct sk_ring_data)); 1338 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1339 goto fail; 1340 } 1341 1342 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1343 if (!entry) { 1344 aprint_error_dev(&sc_if->sk_dev, "Can't alloc txmap entry\n"); 1345 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1346 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1347 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1348 bus_dmamem_unmap(sc->sc_dmatag, kva, 1349 sizeof(struct sk_ring_data)); 1350 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1351 goto fail; 1352 } 1353 entry->dmamap = dmamap; 1354 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1355 } 1356 1357 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1358 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1359 1360 ifp = &sc_if->sk_ethercom.ec_if; 1361 /* Try to allocate memory for jumbo buffers. */ 1362 if (sk_alloc_jumbo_mem(sc_if)) { 1363 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1364 goto fail; 1365 } 1366 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1367 | ETHERCAP_JUMBO_MTU; 1368 1369 ifp->if_softc = sc_if; 1370 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1371 ifp->if_ioctl = sk_ioctl; 1372 ifp->if_start = sk_start; 1373 ifp->if_stop = sk_stop; 1374 ifp->if_init = sk_init; 1375 ifp->if_watchdog = sk_watchdog; 1376 ifp->if_capabilities = 0; 1377 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1378 IFQ_SET_READY(&ifp->if_snd); 1379 strlcpy(ifp->if_xname, device_xname(&sc_if->sk_dev), IFNAMSIZ); 1380 1381 /* 1382 * Do miibus setup. 1383 */ 1384 switch (sc->sk_type) { 1385 case SK_GENESIS: 1386 sk_init_xmac(sc_if); 1387 break; 1388 case SK_YUKON: 1389 case SK_YUKON_LITE: 1390 case SK_YUKON_LP: 1391 sk_init_yukon(sc_if); 1392 break; 1393 default: 1394 aprint_error_dev(&sc->sk_dev, "unknown device type %d\n", 1395 sc->sk_type); 1396 goto fail; 1397 } 1398 1399 DPRINTFN(2, ("sk_attach: 1\n")); 1400 1401 sc_if->sk_mii.mii_ifp = ifp; 1402 switch (sc->sk_type) { 1403 case SK_GENESIS: 1404 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1405 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1406 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1407 break; 1408 case SK_YUKON: 1409 case SK_YUKON_LITE: 1410 case SK_YUKON_LP: 1411 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1412 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1413 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1414 break; 1415 } 1416 1417 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1418 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1419 sk_ifmedia_upd, ether_mediastatus); 1420 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1421 MII_OFFSET_ANY, 0); 1422 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1423 aprint_error_dev(&sc_if->sk_dev, "no PHY found!\n"); 1424 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1425 0, NULL); 1426 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1427 } else 1428 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1429 1430 callout_init(&sc_if->sk_tick_ch, 0); 1431 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1432 1433 DPRINTFN(2, ("sk_attach: 1\n")); 1434 1435 /* 1436 * Call MI attach routines. 1437 */ 1438 if_attach(ifp); 1439 1440 ether_ifattach(ifp, sc_if->sk_enaddr); 1441 1442 #if NRND > 0 1443 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sk_dev), 1444 RND_TYPE_NET, 0); 1445 #endif 1446 1447 DPRINTFN(2, ("sk_attach: end\n")); 1448 1449 return; 1450 1451 fail: 1452 sc->sk_if[sa->skc_port] = NULL; 1453 } 1454 1455 int 1456 skcprint(void *aux, const char *pnp) 1457 { 1458 struct skc_attach_args *sa = aux; 1459 1460 if (pnp) 1461 aprint_normal("sk port %c at %s", 1462 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1463 else 1464 aprint_normal(" port %c", 1465 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1466 return UNCONF; 1467 } 1468 1469 /* 1470 * Attach the interface. Allocate softc structures, do ifmedia 1471 * setup and ethernet/BPF attach. 1472 */ 1473 void 1474 skc_attach(struct device *parent, struct device *self, void *aux) 1475 { 1476 struct sk_softc *sc = (struct sk_softc *)self; 1477 struct pci_attach_args *pa = aux; 1478 struct skc_attach_args skca; 1479 pci_chipset_tag_t pc = pa->pa_pc; 1480 #ifndef SK_USEIOSPACE 1481 pcireg_t memtype; 1482 #endif 1483 pci_intr_handle_t ih; 1484 const char *intrstr = NULL; 1485 bus_addr_t iobase; 1486 bus_size_t iosize; 1487 int rc, sk_nodenum; 1488 u_int32_t command; 1489 const char *revstr; 1490 const struct sysctlnode *node; 1491 1492 aprint_naive("\n"); 1493 1494 DPRINTFN(2, ("begin skc_attach\n")); 1495 1496 /* 1497 * Handle power management nonsense. 1498 */ 1499 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1500 1501 if (command == 0x01) { 1502 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1503 if (command & SK_PSTATE_MASK) { 1504 u_int32_t xiobase, membase, irq; 1505 1506 /* Save important PCI config data. */ 1507 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1508 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1509 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1510 1511 /* Reset the power state. */ 1512 aprint_normal_dev(&sc->sk_dev, "chip is in D%d power mode " 1513 "-- setting to D0\n", 1514 command & SK_PSTATE_MASK); 1515 command &= 0xFFFFFFFC; 1516 pci_conf_write(pc, pa->pa_tag, 1517 SK_PCI_PWRMGMTCTRL, command); 1518 1519 /* Restore PCI config data. */ 1520 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1521 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1522 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1523 } 1524 } 1525 1526 /* 1527 * Map control/status registers. 1528 */ 1529 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1530 command |= PCI_COMMAND_IO_ENABLE | 1531 PCI_COMMAND_MEM_ENABLE | 1532 PCI_COMMAND_MASTER_ENABLE; 1533 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1534 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1535 1536 #ifdef SK_USEIOSPACE 1537 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1538 aprint_error(": failed to enable I/O ports!\n"); 1539 return; 1540 } 1541 /* 1542 * Map control/status registers. 1543 */ 1544 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1545 &sc->sk_btag, &sc->sk_bhandle, 1546 &iobase, &iosize)) { 1547 aprint_error(": can't find i/o space\n"); 1548 return; 1549 } 1550 #else 1551 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1552 aprint_error(": failed to enable memory mapping!\n"); 1553 return; 1554 } 1555 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1556 switch (memtype) { 1557 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1558 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1559 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1560 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1561 &iobase, &iosize) == 0) 1562 break; 1563 default: 1564 aprint_error_dev(&sc->sk_dev, "can't find mem space\n"); 1565 return; 1566 } 1567 1568 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1569 #endif 1570 sc->sc_dmatag = pa->pa_dmat; 1571 1572 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1573 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1574 1575 /* bail out here if chip is not recognized */ 1576 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1577 aprint_error_dev(&sc->sk_dev, "unknown chip type\n"); 1578 goto fail; 1579 } 1580 if (SK_IS_YUKON2(sc)) { 1581 aprint_error_dev(&sc->sk_dev, "Does not support Yukon2--try msk(4).\n"); 1582 goto fail; 1583 } 1584 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1585 1586 /* Allocate interrupt */ 1587 if (pci_intr_map(pa, &ih)) { 1588 aprint_error(": couldn't map interrupt\n"); 1589 goto fail; 1590 } 1591 1592 intrstr = pci_intr_string(pc, ih); 1593 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1594 if (sc->sk_intrhand == NULL) { 1595 aprint_error(": couldn't establish interrupt"); 1596 if (intrstr != NULL) 1597 aprint_normal(" at %s", intrstr); 1598 goto fail; 1599 } 1600 aprint_normal(": %s\n", intrstr); 1601 1602 /* Reset the adapter. */ 1603 sk_reset(sc); 1604 1605 /* Read and save vital product data from EEPROM. */ 1606 sk_vpd_read(sc); 1607 1608 if (sc->sk_type == SK_GENESIS) { 1609 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1610 /* Read and save RAM size and RAMbuffer offset */ 1611 switch (val) { 1612 case SK_RAMSIZE_512K_64: 1613 sc->sk_ramsize = 0x80000; 1614 sc->sk_rboff = SK_RBOFF_0; 1615 break; 1616 case SK_RAMSIZE_1024K_64: 1617 sc->sk_ramsize = 0x100000; 1618 sc->sk_rboff = SK_RBOFF_80000; 1619 break; 1620 case SK_RAMSIZE_1024K_128: 1621 sc->sk_ramsize = 0x100000; 1622 sc->sk_rboff = SK_RBOFF_0; 1623 break; 1624 case SK_RAMSIZE_2048K_128: 1625 sc->sk_ramsize = 0x200000; 1626 sc->sk_rboff = SK_RBOFF_0; 1627 break; 1628 default: 1629 aprint_error_dev(&sc->sk_dev, "unknown ram size: %d\n", 1630 val); 1631 goto fail_1; 1632 break; 1633 } 1634 1635 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1636 sc->sk_ramsize, sc->sk_ramsize / 1024, 1637 sc->sk_rboff)); 1638 } else { 1639 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1640 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1641 sc->sk_rboff = SK_RBOFF_0; 1642 1643 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1644 sc->sk_ramsize / 1024, sc->sk_ramsize, 1645 sc->sk_rboff)); 1646 } 1647 1648 /* Read and save physical media type */ 1649 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1650 case SK_PMD_1000BASESX: 1651 sc->sk_pmd = IFM_1000_SX; 1652 break; 1653 case SK_PMD_1000BASELX: 1654 sc->sk_pmd = IFM_1000_LX; 1655 break; 1656 case SK_PMD_1000BASECX: 1657 sc->sk_pmd = IFM_1000_CX; 1658 break; 1659 case SK_PMD_1000BASETX: 1660 case SK_PMD_1000BASETX_ALT: 1661 sc->sk_pmd = IFM_1000_T; 1662 break; 1663 default: 1664 aprint_error_dev(&sc->sk_dev, "unknown media type: 0x%x\n", 1665 sk_win_read_1(sc, SK_PMDTYPE)); 1666 goto fail_1; 1667 } 1668 1669 /* determine whether to name it with vpd or just make it up */ 1670 /* Marvell Yukon VPD's can freqently be bogus */ 1671 1672 switch (pa->pa_id) { 1673 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1674 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1675 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1676 case PCI_PRODUCT_3COM_3C940: 1677 case PCI_PRODUCT_DLINK_DGE530T: 1678 case PCI_PRODUCT_DLINK_DGE560T: 1679 case PCI_PRODUCT_DLINK_DGE560T_2: 1680 case PCI_PRODUCT_LINKSYS_EG1032: 1681 case PCI_PRODUCT_LINKSYS_EG1064: 1682 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1683 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1684 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1685 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1686 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1687 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1688 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1689 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1690 sc->sk_name = sc->sk_vpd_prodname; 1691 break; 1692 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1693 /* whoops yukon vpd prodname bears no resemblance to reality */ 1694 switch (sc->sk_type) { 1695 case SK_GENESIS: 1696 sc->sk_name = sc->sk_vpd_prodname; 1697 break; 1698 case SK_YUKON: 1699 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1700 break; 1701 case SK_YUKON_LITE: 1702 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1703 break; 1704 case SK_YUKON_LP: 1705 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1706 break; 1707 default: 1708 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1709 } 1710 1711 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1712 1713 if ( sc->sk_type == SK_YUKON ) { 1714 uint32_t flashaddr; 1715 uint8_t testbyte; 1716 1717 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1718 1719 /* test Flash-Address Register */ 1720 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1721 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1722 1723 if (testbyte != 0) { 1724 /* this is yukon lite Rev. A0 */ 1725 sc->sk_type = SK_YUKON_LITE; 1726 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1727 /* restore Flash-Address Register */ 1728 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1729 } 1730 } 1731 break; 1732 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1733 sc->sk_name = sc->sk_vpd_prodname; 1734 break; 1735 default: 1736 sc->sk_name = "Unknown Marvell"; 1737 } 1738 1739 1740 if ( sc->sk_type == SK_YUKON_LITE ) { 1741 switch (sc->sk_rev) { 1742 case SK_YUKON_LITE_REV_A0: 1743 revstr = "A0"; 1744 break; 1745 case SK_YUKON_LITE_REV_A1: 1746 revstr = "A1"; 1747 break; 1748 case SK_YUKON_LITE_REV_A3: 1749 revstr = "A3"; 1750 break; 1751 default: 1752 revstr = ""; 1753 } 1754 } else { 1755 revstr = ""; 1756 } 1757 1758 /* Announce the product name. */ 1759 aprint_normal_dev(&sc->sk_dev, "%s rev. %s(0x%x)\n", 1760 sc->sk_name, revstr, sc->sk_rev); 1761 1762 skca.skc_port = SK_PORT_A; 1763 (void)config_found(&sc->sk_dev, &skca, skcprint); 1764 1765 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1766 skca.skc_port = SK_PORT_B; 1767 (void)config_found(&sc->sk_dev, &skca, skcprint); 1768 } 1769 1770 /* Turn on the 'driver is loaded' LED. */ 1771 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1772 1773 /* skc sysctl setup */ 1774 1775 sc->sk_int_mod = SK_IM_DEFAULT; 1776 sc->sk_int_mod_pending = 0; 1777 1778 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1779 0, CTLTYPE_NODE, device_xname(&sc->sk_dev), 1780 SYSCTL_DESCR("skc per-controller controls"), 1781 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1782 CTL_EOL)) != 0) { 1783 aprint_normal_dev(&sc->sk_dev, "couldn't create sysctl node\n"); 1784 goto fail_1; 1785 } 1786 1787 sk_nodenum = node->sysctl_num; 1788 1789 /* interrupt moderation time in usecs */ 1790 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1791 CTLFLAG_READWRITE, 1792 CTLTYPE_INT, "int_mod", 1793 SYSCTL_DESCR("sk interrupt moderation timer"), 1794 sk_sysctl_handler, 0, sc, 1795 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1796 CTL_EOL)) != 0) { 1797 aprint_normal_dev(&sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1798 goto fail_1; 1799 } 1800 1801 return; 1802 1803 fail_1: 1804 pci_intr_disestablish(pc, sc->sk_intrhand); 1805 fail: 1806 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1807 } 1808 1809 int 1810 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1811 { 1812 struct sk_softc *sc = sc_if->sk_softc; 1813 struct sk_tx_desc *f = NULL; 1814 u_int32_t frag, cur, cnt = 0, sk_ctl; 1815 int i; 1816 struct sk_txmap_entry *entry; 1817 bus_dmamap_t txmap; 1818 1819 DPRINTFN(3, ("sk_encap\n")); 1820 1821 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1822 if (entry == NULL) { 1823 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1824 return ENOBUFS; 1825 } 1826 txmap = entry->dmamap; 1827 1828 cur = frag = *txidx; 1829 1830 #ifdef SK_DEBUG 1831 if (skdebug >= 3) 1832 sk_dump_mbuf(m_head); 1833 #endif 1834 1835 /* 1836 * Start packing the mbufs in this chain into 1837 * the fragment pointers. Stop when we run out 1838 * of fragments or hit the end of the mbuf chain. 1839 */ 1840 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1841 BUS_DMA_NOWAIT)) { 1842 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1843 return ENOBUFS; 1844 } 1845 1846 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1847 1848 /* Sync the DMA map. */ 1849 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1850 BUS_DMASYNC_PREWRITE); 1851 1852 for (i = 0; i < txmap->dm_nsegs; i++) { 1853 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1854 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1855 return ENOBUFS; 1856 } 1857 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1858 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1859 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1860 if (cnt == 0) 1861 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1862 else 1863 sk_ctl |= SK_TXCTL_OWN; 1864 f->sk_ctl = htole32(sk_ctl); 1865 cur = frag; 1866 SK_INC(frag, SK_TX_RING_CNT); 1867 cnt++; 1868 } 1869 1870 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1871 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1872 1873 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1874 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1875 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1876 1877 /* Sync descriptors before handing to chip */ 1878 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1879 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1880 1881 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1882 htole32(SK_TXCTL_OWN); 1883 1884 /* Sync first descriptor to hand it off */ 1885 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1886 1887 sc_if->sk_cdata.sk_tx_cnt += cnt; 1888 1889 #ifdef SK_DEBUG 1890 if (skdebug >= 3) { 1891 struct sk_tx_desc *desc; 1892 u_int32_t idx; 1893 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1894 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1895 sk_dump_txdesc(desc, idx); 1896 } 1897 } 1898 #endif 1899 1900 *txidx = frag; 1901 1902 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1903 1904 return 0; 1905 } 1906 1907 void 1908 sk_start(struct ifnet *ifp) 1909 { 1910 struct sk_if_softc *sc_if = ifp->if_softc; 1911 struct sk_softc *sc = sc_if->sk_softc; 1912 struct mbuf *m_head = NULL; 1913 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1914 int pkts = 0; 1915 1916 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1917 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1918 1919 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1920 IFQ_POLL(&ifp->if_snd, m_head); 1921 if (m_head == NULL) 1922 break; 1923 1924 /* 1925 * Pack the data into the transmit ring. If we 1926 * don't have room, set the OACTIVE flag and wait 1927 * for the NIC to drain the ring. 1928 */ 1929 if (sk_encap(sc_if, m_head, &idx)) { 1930 ifp->if_flags |= IFF_OACTIVE; 1931 break; 1932 } 1933 1934 /* now we are committed to transmit the packet */ 1935 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1936 pkts++; 1937 1938 /* 1939 * If there's a BPF listener, bounce a copy of this frame 1940 * to him. 1941 */ 1942 #if NBPFILTER > 0 1943 if (ifp->if_bpf) 1944 bpf_mtap(ifp->if_bpf, m_head); 1945 #endif 1946 } 1947 if (pkts == 0) 1948 return; 1949 1950 /* Transmit */ 1951 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1952 sc_if->sk_cdata.sk_tx_prod = idx; 1953 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1954 1955 /* Set a timeout in case the chip goes out to lunch. */ 1956 ifp->if_timer = 5; 1957 } 1958 } 1959 1960 1961 void 1962 sk_watchdog(struct ifnet *ifp) 1963 { 1964 struct sk_if_softc *sc_if = ifp->if_softc; 1965 1966 /* 1967 * Reclaim first as there is a possibility of losing Tx completion 1968 * interrupts. 1969 */ 1970 sk_txeof(sc_if); 1971 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1972 aprint_error_dev(&sc_if->sk_dev, "watchdog timeout\n"); 1973 1974 ifp->if_oerrors++; 1975 1976 sk_init(ifp); 1977 } 1978 } 1979 1980 void 1981 sk_shutdown(void *v) 1982 { 1983 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1984 struct sk_softc *sc = sc_if->sk_softc; 1985 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1986 1987 DPRINTFN(2, ("sk_shutdown\n")); 1988 sk_stop(ifp,1); 1989 1990 /* Turn off the 'driver is loaded' LED. */ 1991 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1992 1993 /* 1994 * Reset the GEnesis controller. Doing this should also 1995 * assert the resets on the attached XMAC(s). 1996 */ 1997 sk_reset(sc); 1998 } 1999 2000 void 2001 sk_rxeof(struct sk_if_softc *sc_if) 2002 { 2003 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2004 struct mbuf *m; 2005 struct sk_chain *cur_rx; 2006 struct sk_rx_desc *cur_desc; 2007 int i, cur, total_len = 0; 2008 u_int32_t rxstat, sk_ctl; 2009 bus_dmamap_t dmamap; 2010 2011 i = sc_if->sk_cdata.sk_rx_prod; 2012 2013 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2014 2015 for (;;) { 2016 cur = i; 2017 2018 /* Sync the descriptor */ 2019 SK_CDRXSYNC(sc_if, cur, 2020 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2021 2022 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2023 if (sk_ctl & SK_RXCTL_OWN) { 2024 /* Invalidate the descriptor -- it's not ready yet */ 2025 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2026 sc_if->sk_cdata.sk_rx_prod = i; 2027 break; 2028 } 2029 2030 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2031 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2032 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2033 2034 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2035 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2036 2037 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2038 m = cur_rx->sk_mbuf; 2039 cur_rx->sk_mbuf = NULL; 2040 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2041 2042 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2043 2044 SK_INC(i, SK_RX_RING_CNT); 2045 2046 if (rxstat & XM_RXSTAT_ERRFRAME) { 2047 ifp->if_ierrors++; 2048 sk_newbuf(sc_if, cur, m, dmamap); 2049 continue; 2050 } 2051 2052 /* 2053 * Try to allocate a new jumbo buffer. If that 2054 * fails, copy the packet to mbufs and put the 2055 * jumbo buffer back in the ring so it can be 2056 * re-used. If allocating mbufs fails, then we 2057 * have to drop the packet. 2058 */ 2059 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2060 struct mbuf *m0; 2061 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2062 total_len + ETHER_ALIGN, 0, ifp, NULL); 2063 sk_newbuf(sc_if, cur, m, dmamap); 2064 if (m0 == NULL) { 2065 aprint_error_dev(&sc_if->sk_dev, "no receive buffers " 2066 "available -- packet dropped!\n"); 2067 ifp->if_ierrors++; 2068 continue; 2069 } 2070 m_adj(m0, ETHER_ALIGN); 2071 m = m0; 2072 } else { 2073 m->m_pkthdr.rcvif = ifp; 2074 m->m_pkthdr.len = m->m_len = total_len; 2075 } 2076 2077 ifp->if_ipackets++; 2078 2079 #if NBPFILTER > 0 2080 if (ifp->if_bpf) 2081 bpf_mtap(ifp->if_bpf, m); 2082 #endif 2083 /* pass it on. */ 2084 (*ifp->if_input)(ifp, m); 2085 } 2086 } 2087 2088 void 2089 sk_txeof(struct sk_if_softc *sc_if) 2090 { 2091 struct sk_softc *sc = sc_if->sk_softc; 2092 struct sk_tx_desc *cur_tx; 2093 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2094 u_int32_t idx, sk_ctl; 2095 struct sk_txmap_entry *entry; 2096 2097 DPRINTFN(3, ("sk_txeof\n")); 2098 2099 /* 2100 * Go through our tx ring and free mbufs for those 2101 * frames that have been sent. 2102 */ 2103 idx = sc_if->sk_cdata.sk_tx_cons; 2104 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2105 SK_CDTXSYNC(sc_if, idx, 1, 2106 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2107 2108 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2109 sk_ctl = le32toh(cur_tx->sk_ctl); 2110 #ifdef SK_DEBUG 2111 if (skdebug >= 3) 2112 sk_dump_txdesc(cur_tx, idx); 2113 #endif 2114 if (sk_ctl & SK_TXCTL_OWN) { 2115 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2116 break; 2117 } 2118 if (sk_ctl & SK_TXCTL_LASTFRAG) 2119 ifp->if_opackets++; 2120 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2121 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2122 2123 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2124 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2125 2126 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2127 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2128 2129 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2130 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2131 link); 2132 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2133 } 2134 sc_if->sk_cdata.sk_tx_cnt--; 2135 SK_INC(idx, SK_TX_RING_CNT); 2136 } 2137 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2138 ifp->if_timer = 0; 2139 else /* nudge chip to keep tx ring moving */ 2140 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2141 2142 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2143 ifp->if_flags &= ~IFF_OACTIVE; 2144 2145 sc_if->sk_cdata.sk_tx_cons = idx; 2146 } 2147 2148 void 2149 sk_tick(void *xsc_if) 2150 { 2151 struct sk_if_softc *sc_if = xsc_if; 2152 struct mii_data *mii = &sc_if->sk_mii; 2153 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2154 int i; 2155 2156 DPRINTFN(3, ("sk_tick\n")); 2157 2158 if (!(ifp->if_flags & IFF_UP)) 2159 return; 2160 2161 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2162 sk_intr_bcom(sc_if); 2163 return; 2164 } 2165 2166 /* 2167 * According to SysKonnect, the correct way to verify that 2168 * the link has come back up is to poll bit 0 of the GPIO 2169 * register three times. This pin has the signal from the 2170 * link sync pin connected to it; if we read the same link 2171 * state 3 times in a row, we know the link is up. 2172 */ 2173 for (i = 0; i < 3; i++) { 2174 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2175 break; 2176 } 2177 2178 if (i != 3) { 2179 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2180 return; 2181 } 2182 2183 /* Turn the GP0 interrupt back on. */ 2184 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2185 SK_XM_READ_2(sc_if, XM_ISR); 2186 mii_tick(mii); 2187 mii_pollstat(mii); 2188 callout_stop(&sc_if->sk_tick_ch); 2189 } 2190 2191 void 2192 sk_intr_bcom(struct sk_if_softc *sc_if) 2193 { 2194 struct mii_data *mii = &sc_if->sk_mii; 2195 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2196 int status; 2197 2198 2199 DPRINTFN(3, ("sk_intr_bcom\n")); 2200 2201 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2202 2203 /* 2204 * Read the PHY interrupt register to make sure 2205 * we clear any pending interrupts. 2206 */ 2207 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2208 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2209 2210 if (!(ifp->if_flags & IFF_RUNNING)) { 2211 sk_init_xmac(sc_if); 2212 return; 2213 } 2214 2215 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2216 int lstat; 2217 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2218 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2219 2220 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2221 (void)mii_mediachg(mii); 2222 /* Turn off the link LED. */ 2223 SK_IF_WRITE_1(sc_if, 0, 2224 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2225 sc_if->sk_link = 0; 2226 } else if (status & BRGPHY_ISR_LNK_CHG) { 2227 sk_xmac_miibus_writereg((struct device *)sc_if, 2228 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2229 mii_tick(mii); 2230 sc_if->sk_link = 1; 2231 /* Turn on the link LED. */ 2232 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2233 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2234 SK_LINKLED_BLINK_OFF); 2235 mii_pollstat(mii); 2236 } else { 2237 mii_tick(mii); 2238 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2239 } 2240 } 2241 2242 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2243 } 2244 2245 void 2246 sk_intr_xmac(struct sk_if_softc *sc_if) 2247 { 2248 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2249 2250 DPRINTFN(3, ("sk_intr_xmac\n")); 2251 2252 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2253 if (status & XM_ISR_GP0_SET) { 2254 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2255 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2256 } 2257 2258 if (status & XM_ISR_AUTONEG_DONE) { 2259 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2260 } 2261 } 2262 2263 if (status & XM_IMR_TX_UNDERRUN) 2264 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2265 2266 if (status & XM_IMR_RX_OVERRUN) 2267 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2268 } 2269 2270 void 2271 sk_intr_yukon(struct sk_if_softc *sc_if) 2272 { 2273 int status; 2274 2275 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2276 2277 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2278 } 2279 2280 int 2281 sk_intr(void *xsc) 2282 { 2283 struct sk_softc *sc = xsc; 2284 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2285 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2286 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2287 u_int32_t status; 2288 int claimed = 0; 2289 2290 if (sc_if0 != NULL) 2291 ifp0 = &sc_if0->sk_ethercom.ec_if; 2292 if (sc_if1 != NULL) 2293 ifp1 = &sc_if1->sk_ethercom.ec_if; 2294 2295 for (;;) { 2296 status = CSR_READ_4(sc, SK_ISSR); 2297 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2298 2299 if (!(status & sc->sk_intrmask)) 2300 break; 2301 2302 claimed = 1; 2303 2304 /* Handle receive interrupts first. */ 2305 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2306 sk_rxeof(sc_if0); 2307 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2308 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2309 } 2310 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2311 sk_rxeof(sc_if1); 2312 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2313 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2314 } 2315 2316 /* Then transmit interrupts. */ 2317 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2318 sk_txeof(sc_if0); 2319 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2320 SK_TXBMU_CLR_IRQ_EOF); 2321 } 2322 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2323 sk_txeof(sc_if1); 2324 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2325 SK_TXBMU_CLR_IRQ_EOF); 2326 } 2327 2328 /* Then MAC interrupts. */ 2329 if (sc_if0 && (status & SK_ISR_MAC1) && 2330 (ifp0->if_flags & IFF_RUNNING)) { 2331 if (sc->sk_type == SK_GENESIS) 2332 sk_intr_xmac(sc_if0); 2333 else 2334 sk_intr_yukon(sc_if0); 2335 } 2336 2337 if (sc_if1 && (status & SK_ISR_MAC2) && 2338 (ifp1->if_flags & IFF_RUNNING)) { 2339 if (sc->sk_type == SK_GENESIS) 2340 sk_intr_xmac(sc_if1); 2341 else 2342 sk_intr_yukon(sc_if1); 2343 2344 } 2345 2346 if (status & SK_ISR_EXTERNAL_REG) { 2347 if (sc_if0 != NULL && 2348 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2349 sk_intr_bcom(sc_if0); 2350 2351 if (sc_if1 != NULL && 2352 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2353 sk_intr_bcom(sc_if1); 2354 } 2355 } 2356 2357 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2358 2359 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2360 sk_start(ifp0); 2361 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2362 sk_start(ifp1); 2363 2364 #if NRND > 0 2365 if (RND_ENABLED(&sc->rnd_source)) 2366 rnd_add_uint32(&sc->rnd_source, status); 2367 #endif 2368 2369 if (sc->sk_int_mod_pending) 2370 sk_update_int_mod(sc); 2371 2372 return claimed; 2373 } 2374 2375 void 2376 sk_init_xmac(struct sk_if_softc *sc_if) 2377 { 2378 struct sk_softc *sc = sc_if->sk_softc; 2379 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2380 static const struct sk_bcom_hack bhack[] = { 2381 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2382 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2383 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2384 { 0, 0 } }; 2385 2386 DPRINTFN(1, ("sk_init_xmac\n")); 2387 2388 /* Unreset the XMAC. */ 2389 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2390 DELAY(1000); 2391 2392 /* Reset the XMAC's internal state. */ 2393 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2394 2395 /* Save the XMAC II revision */ 2396 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2397 2398 /* 2399 * Perform additional initialization for external PHYs, 2400 * namely for the 1000baseTX cards that use the XMAC's 2401 * GMII mode. 2402 */ 2403 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2404 int i = 0; 2405 u_int32_t val; 2406 2407 /* Take PHY out of reset. */ 2408 val = sk_win_read_4(sc, SK_GPIO); 2409 if (sc_if->sk_port == SK_PORT_A) 2410 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2411 else 2412 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2413 sk_win_write_4(sc, SK_GPIO, val); 2414 2415 /* Enable GMII mode on the XMAC. */ 2416 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2417 2418 sk_xmac_miibus_writereg((struct device *)sc_if, 2419 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2420 DELAY(10000); 2421 sk_xmac_miibus_writereg((struct device *)sc_if, 2422 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2423 2424 /* 2425 * Early versions of the BCM5400 apparently have 2426 * a bug that requires them to have their reserved 2427 * registers initialized to some magic values. I don't 2428 * know what the numbers do, I'm just the messenger. 2429 */ 2430 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2431 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2432 while (bhack[i].reg) { 2433 sk_xmac_miibus_writereg((struct device *)sc_if, 2434 SK_PHYADDR_BCOM, bhack[i].reg, 2435 bhack[i].val); 2436 i++; 2437 } 2438 } 2439 } 2440 2441 /* Set station address */ 2442 SK_XM_WRITE_2(sc_if, XM_PAR0, 2443 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2444 SK_XM_WRITE_2(sc_if, XM_PAR1, 2445 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2446 SK_XM_WRITE_2(sc_if, XM_PAR2, 2447 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2448 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2449 2450 if (ifp->if_flags & IFF_PROMISC) 2451 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2452 else 2453 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2454 2455 if (ifp->if_flags & IFF_BROADCAST) 2456 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2457 else 2458 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2459 2460 /* We don't need the FCS appended to the packet. */ 2461 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2462 2463 /* We want short frames padded to 60 bytes. */ 2464 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2465 2466 /* 2467 * Enable the reception of all error frames. This is is 2468 * a necessary evil due to the design of the XMAC. The 2469 * XMAC's receive FIFO is only 8K in size, however jumbo 2470 * frames can be up to 9000 bytes in length. When bad 2471 * frame filtering is enabled, the XMAC's RX FIFO operates 2472 * in 'store and forward' mode. For this to work, the 2473 * entire frame has to fit into the FIFO, but that means 2474 * that jumbo frames larger than 8192 bytes will be 2475 * truncated. Disabling all bad frame filtering causes 2476 * the RX FIFO to operate in streaming mode, in which 2477 * case the XMAC will start transfering frames out of the 2478 * RX FIFO as soon as the FIFO threshold is reached. 2479 */ 2480 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2481 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2482 XM_MODE_RX_INRANGELEN); 2483 2484 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2485 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2486 else 2487 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2488 2489 /* 2490 * Bump up the transmit threshold. This helps hold off transmit 2491 * underruns when we're blasting traffic from both ports at once. 2492 */ 2493 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2494 2495 /* Set multicast filter */ 2496 sk_setmulti(sc_if); 2497 2498 /* Clear and enable interrupts */ 2499 SK_XM_READ_2(sc_if, XM_ISR); 2500 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2501 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2502 else 2503 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2504 2505 /* Configure MAC arbiter */ 2506 switch (sc_if->sk_xmac_rev) { 2507 case XM_XMAC_REV_B2: 2508 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2509 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2510 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2511 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2512 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2513 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2514 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2515 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2516 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2517 break; 2518 case XM_XMAC_REV_C1: 2519 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2520 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2521 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2522 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2523 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2524 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2525 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2526 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2527 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2528 break; 2529 default: 2530 break; 2531 } 2532 sk_win_write_2(sc, SK_MACARB_CTL, 2533 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2534 2535 sc_if->sk_link = 1; 2536 } 2537 2538 void sk_init_yukon(struct sk_if_softc *sc_if) 2539 { 2540 u_int32_t /*mac, */phy; 2541 u_int16_t reg; 2542 struct sk_softc *sc; 2543 int i; 2544 2545 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2546 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2547 2548 sc = sc_if->sk_softc; 2549 if (sc->sk_type == SK_YUKON_LITE && 2550 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2551 /* Take PHY out of reset. */ 2552 sk_win_write_4(sc, SK_GPIO, 2553 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2554 } 2555 2556 2557 /* GMAC and GPHY Reset */ 2558 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2559 2560 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2561 2562 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2563 DELAY(1000); 2564 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2565 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2566 DELAY(1000); 2567 2568 2569 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2570 2571 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2572 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2573 2574 switch (sc_if->sk_softc->sk_pmd) { 2575 case IFM_1000_SX: 2576 case IFM_1000_LX: 2577 phy |= SK_GPHY_FIBER; 2578 break; 2579 2580 case IFM_1000_CX: 2581 case IFM_1000_T: 2582 phy |= SK_GPHY_COPPER; 2583 break; 2584 } 2585 2586 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2587 2588 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2589 DELAY(1000); 2590 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2591 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2592 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2593 2594 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2595 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2596 2597 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2598 2599 /* unused read of the interrupt source register */ 2600 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2601 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2602 2603 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2604 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2605 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2606 2607 /* MIB Counter Clear Mode set */ 2608 reg |= YU_PAR_MIB_CLR; 2609 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2610 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2611 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2612 2613 /* MIB Counter Clear Mode clear */ 2614 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2615 reg &= ~YU_PAR_MIB_CLR; 2616 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2617 2618 /* receive control reg */ 2619 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2620 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2621 YU_RCR_CRCR); 2622 2623 /* transmit parameter register */ 2624 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2625 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2626 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2627 2628 /* serial mode register */ 2629 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2630 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2631 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2632 YU_SMR_IPG_DATA(0x1e)); 2633 2634 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2635 /* Setup Yukon's address */ 2636 for (i = 0; i < 3; i++) { 2637 /* Write Source Address 1 (unicast filter) */ 2638 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2639 sc_if->sk_enaddr[i * 2] | 2640 sc_if->sk_enaddr[i * 2 + 1] << 8); 2641 } 2642 2643 for (i = 0; i < 3; i++) { 2644 reg = sk_win_read_2(sc_if->sk_softc, 2645 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2646 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2647 } 2648 2649 /* Set multicast filter */ 2650 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2651 sk_setmulti(sc_if); 2652 2653 /* enable interrupt mask for counter overflows */ 2654 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2655 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2656 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2657 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2658 2659 /* Configure RX MAC FIFO */ 2660 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2661 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2662 2663 /* Configure TX MAC FIFO */ 2664 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2665 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2666 2667 DPRINTFN(6, ("sk_init_yukon: end\n")); 2668 } 2669 2670 /* 2671 * Note that to properly initialize any part of the GEnesis chip, 2672 * you first have to take it out of reset mode. 2673 */ 2674 int 2675 sk_init(struct ifnet *ifp) 2676 { 2677 struct sk_if_softc *sc_if = ifp->if_softc; 2678 struct sk_softc *sc = sc_if->sk_softc; 2679 struct mii_data *mii = &sc_if->sk_mii; 2680 int rc = 0, s; 2681 u_int32_t imr, imtimer_ticks; 2682 2683 DPRINTFN(1, ("sk_init\n")); 2684 2685 s = splnet(); 2686 2687 if (ifp->if_flags & IFF_RUNNING) { 2688 splx(s); 2689 return 0; 2690 } 2691 2692 /* Cancel pending I/O and free all RX/TX buffers. */ 2693 sk_stop(ifp,0); 2694 2695 if (sc->sk_type == SK_GENESIS) { 2696 /* Configure LINK_SYNC LED */ 2697 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2698 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2699 SK_LINKLED_LINKSYNC_ON); 2700 2701 /* Configure RX LED */ 2702 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2703 SK_RXLEDCTL_COUNTER_START); 2704 2705 /* Configure TX LED */ 2706 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2707 SK_TXLEDCTL_COUNTER_START); 2708 } 2709 2710 /* Configure I2C registers */ 2711 2712 /* Configure XMAC(s) */ 2713 switch (sc->sk_type) { 2714 case SK_GENESIS: 2715 sk_init_xmac(sc_if); 2716 break; 2717 case SK_YUKON: 2718 case SK_YUKON_LITE: 2719 case SK_YUKON_LP: 2720 sk_init_yukon(sc_if); 2721 break; 2722 } 2723 if ((rc = mii_mediachg(mii)) == ENXIO) 2724 rc = 0; 2725 else if (rc != 0) 2726 goto out; 2727 2728 if (sc->sk_type == SK_GENESIS) { 2729 /* Configure MAC FIFOs */ 2730 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2731 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2732 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2733 2734 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2735 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2736 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2737 } 2738 2739 /* Configure transmit arbiter(s) */ 2740 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2741 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2742 2743 /* Configure RAMbuffers */ 2744 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2745 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2746 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2747 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2748 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2749 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2750 2751 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2752 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2753 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2754 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2755 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2756 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2757 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2758 2759 /* Configure BMUs */ 2760 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2761 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2762 SK_RX_RING_ADDR(sc_if, 0)); 2763 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2764 2765 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2766 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2767 SK_TX_RING_ADDR(sc_if, 0)); 2768 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2769 2770 /* Init descriptors */ 2771 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2772 aprint_error_dev(&sc_if->sk_dev, "initialization failed: no " 2773 "memory for rx buffers\n"); 2774 sk_stop(ifp,0); 2775 splx(s); 2776 return ENOBUFS; 2777 } 2778 2779 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2780 aprint_error_dev(&sc_if->sk_dev, "initialization failed: no " 2781 "memory for tx buffers\n"); 2782 sk_stop(ifp,0); 2783 splx(s); 2784 return ENOBUFS; 2785 } 2786 2787 /* Set interrupt moderation if changed via sysctl. */ 2788 switch (sc->sk_type) { 2789 case SK_GENESIS: 2790 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2791 break; 2792 case SK_YUKON_EC: 2793 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2794 break; 2795 default: 2796 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2797 } 2798 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2799 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2800 sk_win_write_4(sc, SK_IMTIMERINIT, 2801 SK_IM_USECS(sc->sk_int_mod)); 2802 aprint_verbose_dev(&sc->sk_dev, "interrupt moderation is %d us\n", 2803 sc->sk_int_mod); 2804 } 2805 2806 /* Configure interrupt handling */ 2807 CSR_READ_4(sc, SK_ISSR); 2808 if (sc_if->sk_port == SK_PORT_A) 2809 sc->sk_intrmask |= SK_INTRS1; 2810 else 2811 sc->sk_intrmask |= SK_INTRS2; 2812 2813 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2814 2815 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2816 2817 /* Start BMUs. */ 2818 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2819 2820 if (sc->sk_type == SK_GENESIS) { 2821 /* Enable XMACs TX and RX state machines */ 2822 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2823 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2824 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2825 } 2826 2827 if (SK_YUKON_FAMILY(sc->sk_type)) { 2828 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2829 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2830 #if 0 2831 /* XXX disable 100Mbps and full duplex mode? */ 2832 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2833 #endif 2834 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2835 } 2836 2837 2838 ifp->if_flags |= IFF_RUNNING; 2839 ifp->if_flags &= ~IFF_OACTIVE; 2840 2841 out: 2842 splx(s); 2843 return rc; 2844 } 2845 2846 void 2847 sk_stop(struct ifnet *ifp, int disable) 2848 { 2849 struct sk_if_softc *sc_if = ifp->if_softc; 2850 struct sk_softc *sc = sc_if->sk_softc; 2851 int i; 2852 2853 DPRINTFN(1, ("sk_stop\n")); 2854 2855 callout_stop(&sc_if->sk_tick_ch); 2856 2857 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2858 u_int32_t val; 2859 2860 /* Put PHY back into reset. */ 2861 val = sk_win_read_4(sc, SK_GPIO); 2862 if (sc_if->sk_port == SK_PORT_A) { 2863 val |= SK_GPIO_DIR0; 2864 val &= ~SK_GPIO_DAT0; 2865 } else { 2866 val |= SK_GPIO_DIR2; 2867 val &= ~SK_GPIO_DAT2; 2868 } 2869 sk_win_write_4(sc, SK_GPIO, val); 2870 } 2871 2872 /* Turn off various components of this interface. */ 2873 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2874 switch (sc->sk_type) { 2875 case SK_GENESIS: 2876 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2877 SK_TXMACCTL_XMAC_RESET); 2878 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2879 break; 2880 case SK_YUKON: 2881 case SK_YUKON_LITE: 2882 case SK_YUKON_LP: 2883 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2884 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2885 break; 2886 } 2887 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2888 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2889 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2890 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2891 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2892 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2893 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2894 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2895 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2896 2897 /* Disable interrupts */ 2898 if (sc_if->sk_port == SK_PORT_A) 2899 sc->sk_intrmask &= ~SK_INTRS1; 2900 else 2901 sc->sk_intrmask &= ~SK_INTRS2; 2902 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2903 2904 SK_XM_READ_2(sc_if, XM_ISR); 2905 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2906 2907 /* Free RX and TX mbufs still in the queues. */ 2908 for (i = 0; i < SK_RX_RING_CNT; i++) { 2909 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2910 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2911 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2912 } 2913 } 2914 2915 for (i = 0; i < SK_TX_RING_CNT; i++) { 2916 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2917 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2918 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2919 } 2920 } 2921 2922 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2923 } 2924 2925 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2926 2927 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2928 2929 #ifdef SK_DEBUG 2930 void 2931 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2932 { 2933 #define DESC_PRINT(X) \ 2934 if (X) \ 2935 printf("txdesc[%d]." #X "=%#x\n", \ 2936 idx, X); 2937 2938 DESC_PRINT(le32toh(desc->sk_ctl)); 2939 DESC_PRINT(le32toh(desc->sk_next)); 2940 DESC_PRINT(le32toh(desc->sk_data_lo)); 2941 DESC_PRINT(le32toh(desc->sk_data_hi)); 2942 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2943 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2944 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2945 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2946 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2947 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2948 #undef PRINT 2949 } 2950 2951 void 2952 sk_dump_bytes(const char *data, int len) 2953 { 2954 int c, i, j; 2955 2956 for (i = 0; i < len; i += 16) { 2957 printf("%08x ", i); 2958 c = len - i; 2959 if (c > 16) c = 16; 2960 2961 for (j = 0; j < c; j++) { 2962 printf("%02x ", data[i + j] & 0xff); 2963 if ((j & 0xf) == 7 && j > 0) 2964 printf(" "); 2965 } 2966 2967 for (; j < 16; j++) 2968 printf(" "); 2969 printf(" "); 2970 2971 for (j = 0; j < c; j++) { 2972 int ch = data[i + j] & 0xff; 2973 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2974 } 2975 2976 printf("\n"); 2977 2978 if (c < 16) 2979 break; 2980 } 2981 } 2982 2983 void 2984 sk_dump_mbuf(struct mbuf *m) 2985 { 2986 int count = m->m_pkthdr.len; 2987 2988 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2989 2990 while (count > 0 && m) { 2991 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2992 m, m->m_data, m->m_len); 2993 sk_dump_bytes(mtod(m, char *), m->m_len); 2994 2995 count -= m->m_len; 2996 m = m->m_next; 2997 } 2998 } 2999 #endif 3000 3001 static int 3002 sk_sysctl_handler(SYSCTLFN_ARGS) 3003 { 3004 int error, t; 3005 struct sysctlnode node; 3006 struct sk_softc *sc; 3007 3008 node = *rnode; 3009 sc = node.sysctl_data; 3010 t = sc->sk_int_mod; 3011 node.sysctl_data = &t; 3012 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3013 if (error || newp == NULL) 3014 return error; 3015 3016 if (t < SK_IM_MIN || t > SK_IM_MAX) 3017 return EINVAL; 3018 3019 /* update the softc with sysctl-changed value, and mark 3020 for hardware update */ 3021 sc->sk_int_mod = t; 3022 sc->sk_int_mod_pending = 1; 3023 return 0; 3024 } 3025 3026 /* 3027 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3028 * set up in skc_attach() 3029 */ 3030 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3031 { 3032 int rc; 3033 const struct sysctlnode *node; 3034 3035 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3036 0, CTLTYPE_NODE, "hw", NULL, 3037 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3038 goto err; 3039 } 3040 3041 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3042 0, CTLTYPE_NODE, "sk", 3043 SYSCTL_DESCR("sk interface controls"), 3044 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3045 goto err; 3046 } 3047 3048 sk_root_num = node->sysctl_num; 3049 return; 3050 3051 err: 3052 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3053 } 3054
Indexes created Tue Sep 23 14:10:03 GMT 2025