if_sk.c revision 1.52
1 /* $NetBSD: if_sk.c,v 1.52 2008/09/08 21:44:22 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.52 2008/09/08 21:44:22 christos Exp $"); 119 120 #include "bpfilter.h" 121 #include "rnd.h" 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/sockio.h> 126 #include <sys/mbuf.h> 127 #include <sys/malloc.h> 128 #include <sys/mutex.h> 129 #include <sys/kernel.h> 130 #include <sys/socket.h> 131 #include <sys/device.h> 132 #include <sys/queue.h> 133 #include <sys/callout.h> 134 #include <sys/sysctl.h> 135 #include <sys/endian.h> 136 137 #include <net/if.h> 138 #include <net/if_dl.h> 139 #include <net/if_types.h> 140 141 #include <net/if_media.h> 142 143 #if NBPFILTER > 0 144 #include <net/bpf.h> 145 #endif 146 #if NRND > 0 147 #include <sys/rnd.h> 148 #endif 149 150 #include <dev/mii/mii.h> 151 #include <dev/mii/miivar.h> 152 #include <dev/mii/brgphyreg.h> 153 154 #include <dev/pci/pcireg.h> 155 #include <dev/pci/pcivar.h> 156 #include <dev/pci/pcidevs.h> 157 158 /* #define SK_USEIOSPACE */ 159 160 #include <dev/pci/if_skreg.h> 161 #include <dev/pci/if_skvar.h> 162 163 int skc_probe(device_t, cfdata_t, void *); 164 void skc_attach(device_t, device_t, void *aux); 165 int sk_probe(device_t, cfdata_t, void *); 166 void sk_attach(device_t, device_t, void *aux); 167 int skcprint(void *, const char *); 168 int sk_intr(void *); 169 void sk_intr_bcom(struct sk_if_softc *); 170 void sk_intr_xmac(struct sk_if_softc *); 171 void sk_intr_yukon(struct sk_if_softc *); 172 void sk_rxeof(struct sk_if_softc *); 173 void sk_txeof(struct sk_if_softc *); 174 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 175 void sk_start(struct ifnet *); 176 int sk_ioctl(struct ifnet *, u_long, void *); 177 int sk_init(struct ifnet *); 178 void sk_init_xmac(struct sk_if_softc *); 179 void sk_init_yukon(struct sk_if_softc *); 180 void sk_stop(struct ifnet *, int); 181 void sk_watchdog(struct ifnet *); 182 void sk_shutdown(void *); 183 int sk_ifmedia_upd(struct ifnet *); 184 void sk_reset(struct sk_softc *); 185 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 186 int sk_alloc_jumbo_mem(struct sk_if_softc *); 187 void sk_free_jumbo_mem(struct sk_if_softc *); 188 void *sk_jalloc(struct sk_if_softc *); 189 void sk_jfree(struct mbuf *, void *, size_t, void *); 190 int sk_init_rx_ring(struct sk_if_softc *); 191 int sk_init_tx_ring(struct sk_if_softc *); 192 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 193 void sk_vpd_read_res(struct sk_softc *, 194 struct vpd_res *, int); 195 void sk_vpd_read(struct sk_softc *); 196 197 void sk_update_int_mod(struct sk_softc *); 198 199 int sk_xmac_miibus_readreg(device_t, int, int); 200 void sk_xmac_miibus_writereg(device_t, int, int, int); 201 void sk_xmac_miibus_statchg(device_t); 202 203 int sk_marv_miibus_readreg(device_t, int, int); 204 void sk_marv_miibus_writereg(device_t, int, int, int); 205 void sk_marv_miibus_statchg(device_t); 206 207 u_int32_t sk_xmac_hash(void *); 208 u_int32_t sk_yukon_hash(void *); 209 void sk_setfilt(struct sk_if_softc *, void *, int); 210 void sk_setmulti(struct sk_if_softc *); 211 void sk_tick(void *); 212 213 /* #define SK_DEBUG 2 */ 214 #ifdef SK_DEBUG 215 #define DPRINTF(x) if (skdebug) printf x 216 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 217 int skdebug = SK_DEBUG; 218 219 void sk_dump_txdesc(struct sk_tx_desc *, int); 220 void sk_dump_mbuf(struct mbuf *); 221 void sk_dump_bytes(const char *, int); 222 #else 223 #define DPRINTF(x) 224 #define DPRINTFN(n,x) 225 #endif 226 227 static int sk_sysctl_handler(SYSCTLFN_PROTO); 228 static int sk_root_num; 229 230 /* supported device vendors */ 231 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 232 static const struct sk_product { 233 pci_vendor_id_t sk_vendor; 234 pci_product_id_t sk_product; 235 } sk_products[] = { 236 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 237 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 238 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 239 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 240 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 241 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 242 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 243 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 244 { 0, 0, } 245 }; 246 247 #define SK_LINKSYS_EG1032_SUBID 0x00151737 248 249 static inline u_int32_t 250 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 251 { 252 #ifdef SK_USEIOSPACE 253 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 254 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 255 #else 256 return CSR_READ_4(sc, reg); 257 #endif 258 } 259 260 static inline u_int16_t 261 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 262 { 263 #ifdef SK_USEIOSPACE 264 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 265 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 266 #else 267 return CSR_READ_2(sc, reg); 268 #endif 269 } 270 271 static inline u_int8_t 272 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 273 { 274 #ifdef SK_USEIOSPACE 275 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 276 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 277 #else 278 return CSR_READ_1(sc, reg); 279 #endif 280 } 281 282 static inline void 283 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 284 { 285 #ifdef SK_USEIOSPACE 286 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 287 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 288 #else 289 CSR_WRITE_4(sc, reg, x); 290 #endif 291 } 292 293 static inline void 294 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 295 { 296 #ifdef SK_USEIOSPACE 297 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 298 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 299 #else 300 CSR_WRITE_2(sc, reg, x); 301 #endif 302 } 303 304 static inline void 305 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 306 { 307 #ifdef SK_USEIOSPACE 308 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 309 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 310 #else 311 CSR_WRITE_1(sc, reg, x); 312 #endif 313 } 314 315 /* 316 * The VPD EEPROM contains Vital Product Data, as suggested in 317 * the PCI 2.1 specification. The VPD data is separared into areas 318 * denoted by resource IDs. The SysKonnect VPD contains an ID string 319 * resource (the name of the adapter), a read-only area resource 320 * containing various key/data fields and a read/write area which 321 * can be used to store asset management information or log messages. 322 * We read the ID string and read-only into buffers attached to 323 * the controller softc structure for later use. At the moment, 324 * we only use the ID string during sk_attach(). 325 */ 326 u_int8_t 327 sk_vpd_readbyte(struct sk_softc *sc, int addr) 328 { 329 int i; 330 331 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 332 for (i = 0; i < SK_TIMEOUT; i++) { 333 DELAY(1); 334 if (sk_win_read_2(sc, 335 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 336 break; 337 } 338 339 if (i == SK_TIMEOUT) 340 return 0; 341 342 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 343 } 344 345 void 346 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 347 { 348 int i; 349 u_int8_t *ptr; 350 351 ptr = (u_int8_t *)res; 352 for (i = 0; i < sizeof(struct vpd_res); i++) 353 ptr[i] = sk_vpd_readbyte(sc, i + addr); 354 } 355 356 void 357 sk_vpd_read(struct sk_softc *sc) 358 { 359 int pos = 0, i; 360 struct vpd_res res; 361 362 if (sc->sk_vpd_prodname != NULL) 363 free(sc->sk_vpd_prodname, M_DEVBUF); 364 if (sc->sk_vpd_readonly != NULL) 365 free(sc->sk_vpd_readonly, M_DEVBUF); 366 sc->sk_vpd_prodname = NULL; 367 sc->sk_vpd_readonly = NULL; 368 369 sk_vpd_read_res(sc, &res, pos); 370 371 if (res.vr_id != VPD_RES_ID) { 372 aprint_error_dev(sc->sk_dev, 373 "bad VPD resource id: expected %x got %x\n", 374 VPD_RES_ID, res.vr_id); 375 return; 376 } 377 378 pos += sizeof(res); 379 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 380 if (sc->sk_vpd_prodname == NULL) 381 panic("sk_vpd_read"); 382 for (i = 0; i < res.vr_len; i++) 383 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 384 sc->sk_vpd_prodname[i] = '\0'; 385 pos += i; 386 387 sk_vpd_read_res(sc, &res, pos); 388 389 if (res.vr_id != VPD_RES_READ) { 390 aprint_error_dev(sc->sk_dev, 391 "bad VPD resource id: expected %x got %x\n", 392 VPD_RES_READ, res.vr_id); 393 return; 394 } 395 396 pos += sizeof(res); 397 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 398 if (sc->sk_vpd_readonly == NULL) 399 panic("sk_vpd_read"); 400 for (i = 0; i < res.vr_len ; i++) 401 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 402 } 403 404 int 405 sk_xmac_miibus_readreg(device_t dev, int phy, int reg) 406 { 407 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 408 int i; 409 410 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 411 412 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 413 return 0; 414 415 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 416 SK_XM_READ_2(sc_if, XM_PHY_DATA); 417 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 418 for (i = 0; i < SK_TIMEOUT; i++) { 419 DELAY(1); 420 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 421 XM_MMUCMD_PHYDATARDY) 422 break; 423 } 424 425 if (i == SK_TIMEOUT) { 426 aprint_error_dev(sc_if->sk_dev, 427 "phy failed to come ready\n"); 428 return 0; 429 } 430 } 431 DELAY(1); 432 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 433 } 434 435 void 436 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, int val) 437 { 438 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 439 int i; 440 441 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 442 443 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 444 for (i = 0; i < SK_TIMEOUT; i++) { 445 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 446 break; 447 } 448 449 if (i == SK_TIMEOUT) { 450 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 451 return; 452 } 453 454 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 455 for (i = 0; i < SK_TIMEOUT; i++) { 456 DELAY(1); 457 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 458 break; 459 } 460 461 if (i == SK_TIMEOUT) 462 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 463 } 464 465 void 466 sk_xmac_miibus_statchg(device_t dev) 467 { 468 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 469 struct mii_data *mii = &sc_if->sk_mii; 470 471 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 472 473 /* 474 * If this is a GMII PHY, manually set the XMAC's 475 * duplex mode accordingly. 476 */ 477 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 478 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 479 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 480 else 481 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 482 } 483 } 484 485 int 486 sk_marv_miibus_readreg(device_t dev, int phy, int reg) 487 { 488 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 489 u_int16_t val; 490 int i; 491 492 if (phy != 0 || 493 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 494 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 495 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 496 phy, reg)); 497 return 0; 498 } 499 500 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 501 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 502 503 for (i = 0; i < SK_TIMEOUT; i++) { 504 DELAY(1); 505 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 506 if (val & YU_SMICR_READ_VALID) 507 break; 508 } 509 510 if (i == SK_TIMEOUT) { 511 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 512 return 0; 513 } 514 515 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 516 SK_TIMEOUT)); 517 518 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 519 520 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 521 phy, reg, val)); 522 523 return val; 524 } 525 526 void 527 sk_marv_miibus_writereg(device_t dev, int phy, int reg, int val) 528 { 529 struct sk_if_softc *sc_if = device_private(dev); 530 int i; 531 532 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 533 phy, reg, val)); 534 535 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 536 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 537 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 538 539 for (i = 0; i < SK_TIMEOUT; i++) { 540 DELAY(1); 541 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 542 break; 543 } 544 545 if (i == SK_TIMEOUT) 546 printf("%s: phy write timed out\n", 547 device_xname(sc_if->sk_dev)); 548 } 549 550 void 551 sk_marv_miibus_statchg(device_t dev) 552 { 553 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 554 SK_YU_READ_2((device_private(dev)), YUKON_GPCR))); 555 } 556 557 #define SK_HASH_BITS 6 558 559 u_int32_t 560 sk_xmac_hash(void *addr) 561 { 562 u_int32_t crc; 563 564 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 565 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 566 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 567 return crc; 568 } 569 570 u_int32_t 571 sk_yukon_hash(void *addr) 572 { 573 u_int32_t crc; 574 575 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 576 crc &= ((1 << SK_HASH_BITS) - 1); 577 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 578 return crc; 579 } 580 581 void 582 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 583 { 584 char *addr = addrv; 585 int base = XM_RXFILT_ENTRY(slot); 586 587 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 588 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 589 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 590 } 591 592 void 593 sk_setmulti(struct sk_if_softc *sc_if) 594 { 595 struct sk_softc *sc = sc_if->sk_softc; 596 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 597 u_int32_t hashes[2] = { 0, 0 }; 598 int h = 0, i; 599 struct ethercom *ec = &sc_if->sk_ethercom; 600 struct ether_multi *enm; 601 struct ether_multistep step; 602 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 603 604 /* First, zot all the existing filters. */ 605 switch (sc->sk_type) { 606 case SK_GENESIS: 607 for (i = 1; i < XM_RXFILT_MAX; i++) 608 sk_setfilt(sc_if, (void *)&dummy, i); 609 610 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 611 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 612 break; 613 case SK_YUKON: 614 case SK_YUKON_LITE: 615 case SK_YUKON_LP: 616 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 617 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 618 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 619 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 620 break; 621 } 622 623 /* Now program new ones. */ 624 allmulti: 625 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 626 hashes[0] = 0xFFFFFFFF; 627 hashes[1] = 0xFFFFFFFF; 628 } else { 629 i = 1; 630 /* First find the tail of the list. */ 631 ETHER_FIRST_MULTI(step, ec, enm); 632 while (enm != NULL) { 633 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 634 ETHER_ADDR_LEN)) { 635 ifp->if_flags |= IFF_ALLMULTI; 636 goto allmulti; 637 } 638 DPRINTFN(2,("multicast address %s\n", 639 ether_sprintf(enm->enm_addrlo))); 640 /* 641 * Program the first XM_RXFILT_MAX multicast groups 642 * into the perfect filter. For all others, 643 * use the hash table. 644 */ 645 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 646 sk_setfilt(sc_if, enm->enm_addrlo, i); 647 i++; 648 } 649 else { 650 switch (sc->sk_type) { 651 case SK_GENESIS: 652 h = sk_xmac_hash(enm->enm_addrlo); 653 break; 654 case SK_YUKON: 655 case SK_YUKON_LITE: 656 case SK_YUKON_LP: 657 h = sk_yukon_hash(enm->enm_addrlo); 658 break; 659 } 660 if (h < 32) 661 hashes[0] |= (1 << h); 662 else 663 hashes[1] |= (1 << (h - 32)); 664 } 665 666 ETHER_NEXT_MULTI(step, enm); 667 } 668 } 669 670 switch (sc->sk_type) { 671 case SK_GENESIS: 672 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 673 XM_MODE_RX_USE_PERFECT); 674 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 675 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 676 break; 677 case SK_YUKON: 678 case SK_YUKON_LITE: 679 case SK_YUKON_LP: 680 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 681 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 682 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 683 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 684 break; 685 } 686 } 687 688 int 689 sk_init_rx_ring(struct sk_if_softc *sc_if) 690 { 691 struct sk_chain_data *cd = &sc_if->sk_cdata; 692 struct sk_ring_data *rd = sc_if->sk_rdata; 693 int i; 694 695 bzero((char *)rd->sk_rx_ring, 696 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 697 698 for (i = 0; i < SK_RX_RING_CNT; i++) { 699 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 700 if (i == (SK_RX_RING_CNT - 1)) { 701 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 702 rd->sk_rx_ring[i].sk_next = 703 htole32(SK_RX_RING_ADDR(sc_if, 0)); 704 } else { 705 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 706 rd->sk_rx_ring[i].sk_next = 707 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 708 } 709 } 710 711 for (i = 0; i < SK_RX_RING_CNT; i++) { 712 if (sk_newbuf(sc_if, i, NULL, 713 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 714 aprint_error_dev(sc_if->sk_dev, 715 "failed alloc of %dth mbuf\n", i); 716 return ENOBUFS; 717 } 718 } 719 sc_if->sk_cdata.sk_rx_prod = 0; 720 sc_if->sk_cdata.sk_rx_cons = 0; 721 722 return 0; 723 } 724 725 int 726 sk_init_tx_ring(struct sk_if_softc *sc_if) 727 { 728 struct sk_chain_data *cd = &sc_if->sk_cdata; 729 struct sk_ring_data *rd = sc_if->sk_rdata; 730 int i; 731 732 memset(sc_if->sk_rdata->sk_tx_ring, 0, 733 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 734 735 for (i = 0; i < SK_TX_RING_CNT; i++) { 736 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 737 if (i == (SK_TX_RING_CNT - 1)) { 738 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 739 rd->sk_tx_ring[i].sk_next = 740 htole32(SK_TX_RING_ADDR(sc_if, 0)); 741 } else { 742 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 743 rd->sk_tx_ring[i].sk_next = 744 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 745 } 746 } 747 748 sc_if->sk_cdata.sk_tx_prod = 0; 749 sc_if->sk_cdata.sk_tx_cons = 0; 750 sc_if->sk_cdata.sk_tx_cnt = 0; 751 752 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 753 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 754 755 return 0; 756 } 757 758 int 759 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 760 bus_dmamap_t dmamap) 761 { 762 struct mbuf *m_new = NULL; 763 struct sk_chain *c; 764 struct sk_rx_desc *r; 765 766 if (m == NULL) { 767 void *buf = NULL; 768 769 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 770 if (m_new == NULL) { 771 aprint_error_dev(sc_if->sk_dev, 772 "no memory for rx list -- packet dropped!\n"); 773 return ENOBUFS; 774 } 775 776 /* Allocate the jumbo buffer */ 777 buf = sk_jalloc(sc_if); 778 if (buf == NULL) { 779 m_freem(m_new); 780 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 781 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 782 return ENOBUFS; 783 } 784 785 /* Attach the buffer to the mbuf */ 786 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 787 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 788 789 } else { 790 /* 791 * We're re-using a previously allocated mbuf; 792 * be sure to re-init pointers and lengths to 793 * default values. 794 */ 795 m_new = m; 796 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 797 m_new->m_data = m_new->m_ext.ext_buf; 798 } 799 m_adj(m_new, ETHER_ALIGN); 800 801 c = &sc_if->sk_cdata.sk_rx_chain[i]; 802 r = c->sk_desc; 803 c->sk_mbuf = m_new; 804 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 805 (((vaddr_t)m_new->m_data 806 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 807 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 808 809 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 810 811 return 0; 812 } 813 814 /* 815 * Memory management for jumbo frames. 816 */ 817 818 int 819 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 820 { 821 struct sk_softc *sc = sc_if->sk_softc; 822 char *ptr, *kva; 823 bus_dma_segment_t seg; 824 int i, rseg, state, error; 825 struct sk_jpool_entry *entry; 826 827 state = error = 0; 828 829 /* Grab a big chunk o' storage. */ 830 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 831 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 832 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 833 return ENOBUFS; 834 } 835 836 state = 1; 837 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 838 BUS_DMA_NOWAIT)) { 839 aprint_error_dev(sc->sk_dev, 840 "can't map dma buffers (%d bytes)\n", 841 SK_JMEM); 842 error = ENOBUFS; 843 goto out; 844 } 845 846 state = 2; 847 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 848 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 849 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 850 error = ENOBUFS; 851 goto out; 852 } 853 854 state = 3; 855 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 856 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 857 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 858 error = ENOBUFS; 859 goto out; 860 } 861 862 state = 4; 863 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 864 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 865 866 LIST_INIT(&sc_if->sk_jfree_listhead); 867 LIST_INIT(&sc_if->sk_jinuse_listhead); 868 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 869 870 /* 871 * Now divide it up into 9K pieces and save the addresses 872 * in an array. 873 */ 874 ptr = sc_if->sk_cdata.sk_jumbo_buf; 875 for (i = 0; i < SK_JSLOTS; i++) { 876 sc_if->sk_cdata.sk_jslots[i] = ptr; 877 ptr += SK_JLEN; 878 entry = malloc(sizeof(struct sk_jpool_entry), 879 M_DEVBUF, M_NOWAIT); 880 if (entry == NULL) { 881 aprint_error_dev(sc->sk_dev, 882 "no memory for jumbo buffer queue!\n"); 883 error = ENOBUFS; 884 goto out; 885 } 886 entry->slot = i; 887 if (i) 888 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 889 entry, jpool_entries); 890 else 891 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 892 entry, jpool_entries); 893 } 894 out: 895 if (error != 0) { 896 switch (state) { 897 case 4: 898 bus_dmamap_unload(sc->sc_dmatag, 899 sc_if->sk_cdata.sk_rx_jumbo_map); 900 case 3: 901 bus_dmamap_destroy(sc->sc_dmatag, 902 sc_if->sk_cdata.sk_rx_jumbo_map); 903 case 2: 904 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 905 case 1: 906 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 907 break; 908 default: 909 break; 910 } 911 } 912 913 return error; 914 } 915 916 /* 917 * Allocate a jumbo buffer. 918 */ 919 void * 920 sk_jalloc(struct sk_if_softc *sc_if) 921 { 922 struct sk_jpool_entry *entry; 923 924 mutex_enter(&sc_if->sk_jpool_mtx); 925 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 926 927 if (entry == NULL) { 928 mutex_exit(&sc_if->sk_jpool_mtx); 929 return NULL; 930 } 931 932 LIST_REMOVE(entry, jpool_entries); 933 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 934 mutex_exit(&sc_if->sk_jpool_mtx); 935 return sc_if->sk_cdata.sk_jslots[entry->slot]; 936 } 937 938 /* 939 * Release a jumbo buffer. 940 */ 941 void 942 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 943 { 944 struct sk_jpool_entry *entry; 945 struct sk_if_softc *sc; 946 int i; 947 948 /* Extract the softc struct pointer. */ 949 sc = (struct sk_if_softc *)arg; 950 951 if (sc == NULL) 952 panic("sk_jfree: can't find softc pointer!"); 953 954 /* calculate the slot this buffer belongs to */ 955 956 i = ((vaddr_t)buf 957 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 958 959 if ((i < 0) || (i >= SK_JSLOTS)) 960 panic("sk_jfree: asked to free buffer that we don't manage!"); 961 962 mutex_enter(&sc->sk_jpool_mtx); 963 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 964 if (entry == NULL) 965 panic("sk_jfree: buffer not in use!"); 966 entry->slot = i; 967 LIST_REMOVE(entry, jpool_entries); 968 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 969 mutex_exit(&sc->sk_jpool_mtx); 970 971 if (__predict_true(m != NULL)) 972 pool_cache_put(mb_cache, m); 973 } 974 975 /* 976 * Set media options. 977 */ 978 int 979 sk_ifmedia_upd(struct ifnet *ifp) 980 { 981 struct sk_if_softc *sc_if = ifp->if_softc; 982 int rc; 983 984 (void) sk_init(ifp); 985 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 986 return 0; 987 return rc; 988 } 989 990 int 991 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 992 { 993 struct sk_if_softc *sc_if = ifp->if_softc; 994 struct sk_softc *sc = sc_if->sk_softc; 995 int s, error = 0; 996 997 /* DPRINTFN(2, ("sk_ioctl\n")); */ 998 999 s = splnet(); 1000 1001 switch (command) { 1002 1003 case SIOCSIFFLAGS: 1004 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1005 if (ifp->if_flags & IFF_UP) { 1006 if (ifp->if_flags & IFF_RUNNING && 1007 ifp->if_flags & IFF_PROMISC && 1008 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1009 switch (sc->sk_type) { 1010 case SK_GENESIS: 1011 SK_XM_SETBIT_4(sc_if, XM_MODE, 1012 XM_MODE_RX_PROMISC); 1013 break; 1014 case SK_YUKON: 1015 case SK_YUKON_LITE: 1016 case SK_YUKON_LP: 1017 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1018 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1019 break; 1020 } 1021 sk_setmulti(sc_if); 1022 } else if (ifp->if_flags & IFF_RUNNING && 1023 !(ifp->if_flags & IFF_PROMISC) && 1024 sc_if->sk_if_flags & IFF_PROMISC) { 1025 switch (sc->sk_type) { 1026 case SK_GENESIS: 1027 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1028 XM_MODE_RX_PROMISC); 1029 break; 1030 case SK_YUKON: 1031 case SK_YUKON_LITE: 1032 case SK_YUKON_LP: 1033 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1034 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1035 break; 1036 } 1037 1038 sk_setmulti(sc_if); 1039 } else 1040 (void) sk_init(ifp); 1041 } else { 1042 if (ifp->if_flags & IFF_RUNNING) 1043 sk_stop(ifp,0); 1044 } 1045 sc_if->sk_if_flags = ifp->if_flags; 1046 error = 0; 1047 break; 1048 1049 default: 1050 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1051 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1052 break; 1053 1054 error = 0; 1055 1056 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1057 ; 1058 else if (ifp->if_flags & IFF_RUNNING) { 1059 sk_setmulti(sc_if); 1060 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1061 } 1062 break; 1063 } 1064 1065 splx(s); 1066 return error; 1067 } 1068 1069 void 1070 sk_update_int_mod(struct sk_softc *sc) 1071 { 1072 u_int32_t imtimer_ticks; 1073 1074 /* 1075 * Configure interrupt moderation. The moderation timer 1076 * defers interrupts specified in the interrupt moderation 1077 * timer mask based on the timeout specified in the interrupt 1078 * moderation timer init register. Each bit in the timer 1079 * register represents one tick, so to specify a timeout in 1080 * microseconds, we have to multiply by the correct number of 1081 * ticks-per-microsecond. 1082 */ 1083 switch (sc->sk_type) { 1084 case SK_GENESIS: 1085 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1086 break; 1087 case SK_YUKON_EC: 1088 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1089 break; 1090 default: 1091 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1092 } 1093 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1094 sc->sk_int_mod); 1095 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1096 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1097 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1098 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1099 sc->sk_int_mod_pending = 0; 1100 } 1101 1102 /* 1103 * Lookup: Check the PCI vendor and device, and return a pointer to 1104 * The structure if the IDs match against our list. 1105 */ 1106 1107 static const struct sk_product * 1108 sk_lookup(const struct pci_attach_args *pa) 1109 { 1110 const struct sk_product *psk; 1111 1112 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1113 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1114 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1115 return psk; 1116 } 1117 return NULL; 1118 } 1119 1120 /* 1121 * Probe for a SysKonnect GEnesis chip. 1122 */ 1123 1124 int 1125 skc_probe(device_t parent, cfdata_t match, void *aux) 1126 { 1127 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1128 const struct sk_product *psk; 1129 pcireg_t subid; 1130 1131 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1132 1133 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1134 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1135 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1136 subid == SK_LINKSYS_EG1032_SUBID) 1137 return 1; 1138 1139 if ((psk = sk_lookup(pa))) { 1140 return 1; 1141 } 1142 return 0; 1143 } 1144 1145 /* 1146 * Force the GEnesis into reset, then bring it out of reset. 1147 */ 1148 void sk_reset(struct sk_softc *sc) 1149 { 1150 DPRINTFN(2, ("sk_reset\n")); 1151 1152 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1153 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1154 if (SK_YUKON_FAMILY(sc->sk_type)) 1155 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1156 1157 DELAY(1000); 1158 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1159 DELAY(2); 1160 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1161 if (SK_YUKON_FAMILY(sc->sk_type)) 1162 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1163 1164 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1165 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1166 CSR_READ_2(sc, SK_LINK_CTRL))); 1167 1168 if (sc->sk_type == SK_GENESIS) { 1169 /* Configure packet arbiter */ 1170 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1171 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1172 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1173 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1174 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1175 } 1176 1177 /* Enable RAM interface */ 1178 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1179 1180 sk_update_int_mod(sc); 1181 } 1182 1183 int 1184 sk_probe(device_t parent, cfdata_t match, void *aux) 1185 { 1186 struct skc_attach_args *sa = aux; 1187 1188 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1189 return 0; 1190 1191 return 1; 1192 } 1193 1194 /* 1195 * Each XMAC chip is attached as a separate logical IP interface. 1196 * Single port cards will have only one logical interface of course. 1197 */ 1198 void 1199 sk_attach(device_t parent, device_t self, void *aux) 1200 { 1201 struct sk_if_softc *sc_if = device_private(self); 1202 struct sk_softc *sc = device_private(parent); 1203 struct skc_attach_args *sa = aux; 1204 struct sk_txmap_entry *entry; 1205 struct ifnet *ifp; 1206 bus_dma_segment_t seg; 1207 bus_dmamap_t dmamap; 1208 void *kva; 1209 int i, rseg; 1210 1211 aprint_naive("\n"); 1212 1213 sc_if->sk_dev = self; 1214 sc_if->sk_port = sa->skc_port; 1215 sc_if->sk_softc = sc; 1216 sc->sk_if[sa->skc_port] = sc_if; 1217 1218 if (sa->skc_port == SK_PORT_A) 1219 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1220 if (sa->skc_port == SK_PORT_B) 1221 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1222 1223 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1224 1225 /* 1226 * Get station address for this interface. Note that 1227 * dual port cards actually come with three station 1228 * addresses: one for each port, plus an extra. The 1229 * extra one is used by the SysKonnect driver software 1230 * as a 'virtual' station address for when both ports 1231 * are operating in failover mode. Currently we don't 1232 * use this extra address. 1233 */ 1234 for (i = 0; i < ETHER_ADDR_LEN; i++) 1235 sc_if->sk_enaddr[i] = 1236 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1237 1238 1239 aprint_normal(": Ethernet address %s\n", 1240 ether_sprintf(sc_if->sk_enaddr)); 1241 1242 /* 1243 * Set up RAM buffer addresses. The NIC will have a certain 1244 * amount of SRAM on it, somewhere between 512K and 2MB. We 1245 * need to divide this up a) between the transmitter and 1246 * receiver and b) between the two XMACs, if this is a 1247 * dual port NIC. Our algorithm is to divide up the memory 1248 * evenly so that everyone gets a fair share. 1249 */ 1250 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1251 u_int32_t chunk, val; 1252 1253 chunk = sc->sk_ramsize / 2; 1254 val = sc->sk_rboff / sizeof(u_int64_t); 1255 sc_if->sk_rx_ramstart = val; 1256 val += (chunk / sizeof(u_int64_t)); 1257 sc_if->sk_rx_ramend = val - 1; 1258 sc_if->sk_tx_ramstart = val; 1259 val += (chunk / sizeof(u_int64_t)); 1260 sc_if->sk_tx_ramend = val - 1; 1261 } else { 1262 u_int32_t chunk, val; 1263 1264 chunk = sc->sk_ramsize / 4; 1265 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1266 sizeof(u_int64_t); 1267 sc_if->sk_rx_ramstart = val; 1268 val += (chunk / sizeof(u_int64_t)); 1269 sc_if->sk_rx_ramend = val - 1; 1270 sc_if->sk_tx_ramstart = val; 1271 val += (chunk / sizeof(u_int64_t)); 1272 sc_if->sk_tx_ramend = val - 1; 1273 } 1274 1275 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1276 " tx_ramstart=%#x tx_ramend=%#x\n", 1277 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1278 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1279 1280 /* Read and save PHY type and set PHY address */ 1281 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1282 switch (sc_if->sk_phytype) { 1283 case SK_PHYTYPE_XMAC: 1284 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1285 break; 1286 case SK_PHYTYPE_BCOM: 1287 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1288 break; 1289 case SK_PHYTYPE_MARV_COPPER: 1290 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1291 break; 1292 default: 1293 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1294 sc_if->sk_phytype); 1295 return; 1296 } 1297 1298 /* Allocate the descriptor queues. */ 1299 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1300 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1301 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1302 goto fail; 1303 } 1304 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1305 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1306 aprint_error_dev(sc_if->sk_dev, 1307 "can't map dma buffers (%lu bytes)\n", 1308 (u_long) sizeof(struct sk_ring_data)); 1309 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1310 goto fail; 1311 } 1312 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1313 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1314 &sc_if->sk_ring_map)) { 1315 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1316 bus_dmamem_unmap(sc->sc_dmatag, kva, 1317 sizeof(struct sk_ring_data)); 1318 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1319 goto fail; 1320 } 1321 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1322 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1323 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1324 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1325 bus_dmamem_unmap(sc->sc_dmatag, kva, 1326 sizeof(struct sk_ring_data)); 1327 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1328 goto fail; 1329 } 1330 1331 for (i = 0; i < SK_RX_RING_CNT; i++) 1332 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1333 1334 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1335 for (i = 0; i < SK_TX_RING_CNT; i++) { 1336 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1337 1338 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1339 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1340 aprint_error_dev(sc_if->sk_dev, 1341 "Can't create TX dmamap\n"); 1342 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1343 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1344 bus_dmamem_unmap(sc->sc_dmatag, kva, 1345 sizeof(struct sk_ring_data)); 1346 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1347 goto fail; 1348 } 1349 1350 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1351 if (!entry) { 1352 aprint_error_dev(sc_if->sk_dev, 1353 "Can't alloc txmap entry\n"); 1354 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1355 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1356 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1357 bus_dmamem_unmap(sc->sc_dmatag, kva, 1358 sizeof(struct sk_ring_data)); 1359 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1360 goto fail; 1361 } 1362 entry->dmamap = dmamap; 1363 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1364 } 1365 1366 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1367 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1368 1369 ifp = &sc_if->sk_ethercom.ec_if; 1370 /* Try to allocate memory for jumbo buffers. */ 1371 if (sk_alloc_jumbo_mem(sc_if)) { 1372 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1373 goto fail; 1374 } 1375 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1376 | ETHERCAP_JUMBO_MTU; 1377 1378 ifp->if_softc = sc_if; 1379 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1380 ifp->if_ioctl = sk_ioctl; 1381 ifp->if_start = sk_start; 1382 ifp->if_stop = sk_stop; 1383 ifp->if_init = sk_init; 1384 ifp->if_watchdog = sk_watchdog; 1385 ifp->if_capabilities = 0; 1386 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1387 IFQ_SET_READY(&ifp->if_snd); 1388 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1389 1390 /* 1391 * Do miibus setup. 1392 */ 1393 switch (sc->sk_type) { 1394 case SK_GENESIS: 1395 sk_init_xmac(sc_if); 1396 break; 1397 case SK_YUKON: 1398 case SK_YUKON_LITE: 1399 case SK_YUKON_LP: 1400 sk_init_yukon(sc_if); 1401 break; 1402 default: 1403 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1404 sc->sk_type); 1405 goto fail; 1406 } 1407 1408 DPRINTFN(2, ("sk_attach: 1\n")); 1409 1410 sc_if->sk_mii.mii_ifp = ifp; 1411 switch (sc->sk_type) { 1412 case SK_GENESIS: 1413 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1414 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1415 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1416 break; 1417 case SK_YUKON: 1418 case SK_YUKON_LITE: 1419 case SK_YUKON_LP: 1420 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1421 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1422 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1423 break; 1424 } 1425 1426 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1427 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1428 sk_ifmedia_upd, ether_mediastatus); 1429 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1430 MII_OFFSET_ANY, 0); 1431 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1432 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1433 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1434 0, NULL); 1435 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1436 } else 1437 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1438 1439 callout_init(&sc_if->sk_tick_ch, 0); 1440 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1441 1442 DPRINTFN(2, ("sk_attach: 1\n")); 1443 1444 /* 1445 * Call MI attach routines. 1446 */ 1447 if_attach(ifp); 1448 1449 ether_ifattach(ifp, sc_if->sk_enaddr); 1450 1451 #if NRND > 0 1452 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1453 RND_TYPE_NET, 0); 1454 #endif 1455 1456 DPRINTFN(2, ("sk_attach: end\n")); 1457 1458 return; 1459 1460 fail: 1461 sc->sk_if[sa->skc_port] = NULL; 1462 } 1463 1464 int 1465 skcprint(void *aux, const char *pnp) 1466 { 1467 struct skc_attach_args *sa = aux; 1468 1469 if (pnp) 1470 aprint_normal("sk port %c at %s", 1471 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1472 else 1473 aprint_normal(" port %c", 1474 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1475 return UNCONF; 1476 } 1477 1478 /* 1479 * Attach the interface. Allocate softc structures, do ifmedia 1480 * setup and ethernet/BPF attach. 1481 */ 1482 void 1483 skc_attach(device_t parent, device_t self, void *aux) 1484 { 1485 struct sk_softc *sc = device_private(self); 1486 struct pci_attach_args *pa = aux; 1487 struct skc_attach_args skca; 1488 pci_chipset_tag_t pc = pa->pa_pc; 1489 #ifndef SK_USEIOSPACE 1490 pcireg_t memtype; 1491 #endif 1492 pci_intr_handle_t ih; 1493 const char *intrstr = NULL; 1494 bus_addr_t iobase; 1495 bus_size_t iosize; 1496 int rc, sk_nodenum; 1497 u_int32_t command; 1498 const char *revstr; 1499 const struct sysctlnode *node; 1500 1501 sc->sk_dev = self; 1502 aprint_naive("\n"); 1503 1504 DPRINTFN(2, ("begin skc_attach\n")); 1505 1506 /* 1507 * Handle power management nonsense. 1508 */ 1509 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1510 1511 if (command == 0x01) { 1512 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1513 if (command & SK_PSTATE_MASK) { 1514 u_int32_t xiobase, membase, irq; 1515 1516 /* Save important PCI config data. */ 1517 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1518 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1519 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1520 1521 /* Reset the power state. */ 1522 aprint_normal_dev(sc->sk_dev, 1523 "chip is in D%d power mode -- setting to D0\n", 1524 command & SK_PSTATE_MASK); 1525 command &= 0xFFFFFFFC; 1526 pci_conf_write(pc, pa->pa_tag, 1527 SK_PCI_PWRMGMTCTRL, command); 1528 1529 /* Restore PCI config data. */ 1530 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1531 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1532 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1533 } 1534 } 1535 1536 /* 1537 * Map control/status registers. 1538 */ 1539 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1540 command |= PCI_COMMAND_IO_ENABLE | 1541 PCI_COMMAND_MEM_ENABLE | 1542 PCI_COMMAND_MASTER_ENABLE; 1543 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1544 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1545 1546 #ifdef SK_USEIOSPACE 1547 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1548 aprint_error(": failed to enable I/O ports!\n"); 1549 return; 1550 } 1551 /* 1552 * Map control/status registers. 1553 */ 1554 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1555 &sc->sk_btag, &sc->sk_bhandle, 1556 &iobase, &iosize)) { 1557 aprint_error(": can't find i/o space\n"); 1558 return; 1559 } 1560 #else 1561 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1562 aprint_error(": failed to enable memory mapping!\n"); 1563 return; 1564 } 1565 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1566 switch (memtype) { 1567 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1568 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1569 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1570 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1571 &iobase, &iosize) == 0) 1572 break; 1573 default: 1574 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1575 return; 1576 } 1577 1578 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1579 #endif 1580 sc->sc_dmatag = pa->pa_dmat; 1581 1582 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1583 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1584 1585 /* bail out here if chip is not recognized */ 1586 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1587 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1588 goto fail; 1589 } 1590 if (SK_IS_YUKON2(sc)) { 1591 aprint_error_dev(sc->sk_dev, 1592 "Does not support Yukon2--try msk(4).\n"); 1593 goto fail; 1594 } 1595 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1596 1597 /* Allocate interrupt */ 1598 if (pci_intr_map(pa, &ih)) { 1599 aprint_error(": couldn't map interrupt\n"); 1600 goto fail; 1601 } 1602 1603 intrstr = pci_intr_string(pc, ih); 1604 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1605 if (sc->sk_intrhand == NULL) { 1606 aprint_error(": couldn't establish interrupt"); 1607 if (intrstr != NULL) 1608 aprint_normal(" at %s", intrstr); 1609 goto fail; 1610 } 1611 aprint_normal(": %s\n", intrstr); 1612 1613 /* Reset the adapter. */ 1614 sk_reset(sc); 1615 1616 /* Read and save vital product data from EEPROM. */ 1617 sk_vpd_read(sc); 1618 1619 if (sc->sk_type == SK_GENESIS) { 1620 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1621 /* Read and save RAM size and RAMbuffer offset */ 1622 switch (val) { 1623 case SK_RAMSIZE_512K_64: 1624 sc->sk_ramsize = 0x80000; 1625 sc->sk_rboff = SK_RBOFF_0; 1626 break; 1627 case SK_RAMSIZE_1024K_64: 1628 sc->sk_ramsize = 0x100000; 1629 sc->sk_rboff = SK_RBOFF_80000; 1630 break; 1631 case SK_RAMSIZE_1024K_128: 1632 sc->sk_ramsize = 0x100000; 1633 sc->sk_rboff = SK_RBOFF_0; 1634 break; 1635 case SK_RAMSIZE_2048K_128: 1636 sc->sk_ramsize = 0x200000; 1637 sc->sk_rboff = SK_RBOFF_0; 1638 break; 1639 default: 1640 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1641 val); 1642 goto fail_1; 1643 break; 1644 } 1645 1646 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1647 sc->sk_ramsize, sc->sk_ramsize / 1024, 1648 sc->sk_rboff)); 1649 } else { 1650 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1651 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1652 sc->sk_rboff = SK_RBOFF_0; 1653 1654 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1655 sc->sk_ramsize / 1024, sc->sk_ramsize, 1656 sc->sk_rboff)); 1657 } 1658 1659 /* Read and save physical media type */ 1660 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1661 case SK_PMD_1000BASESX: 1662 sc->sk_pmd = IFM_1000_SX; 1663 break; 1664 case SK_PMD_1000BASELX: 1665 sc->sk_pmd = IFM_1000_LX; 1666 break; 1667 case SK_PMD_1000BASECX: 1668 sc->sk_pmd = IFM_1000_CX; 1669 break; 1670 case SK_PMD_1000BASETX: 1671 case SK_PMD_1000BASETX_ALT: 1672 sc->sk_pmd = IFM_1000_T; 1673 break; 1674 default: 1675 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1676 sk_win_read_1(sc, SK_PMDTYPE)); 1677 goto fail_1; 1678 } 1679 1680 /* determine whether to name it with vpd or just make it up */ 1681 /* Marvell Yukon VPD's can freqently be bogus */ 1682 1683 switch (pa->pa_id) { 1684 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1685 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1686 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1687 case PCI_PRODUCT_3COM_3C940: 1688 case PCI_PRODUCT_DLINK_DGE530T: 1689 case PCI_PRODUCT_DLINK_DGE560T: 1690 case PCI_PRODUCT_DLINK_DGE560T_2: 1691 case PCI_PRODUCT_LINKSYS_EG1032: 1692 case PCI_PRODUCT_LINKSYS_EG1064: 1693 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1694 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1695 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1696 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1697 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1698 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1699 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1700 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1701 sc->sk_name = sc->sk_vpd_prodname; 1702 break; 1703 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1704 /* whoops yukon vpd prodname bears no resemblance to reality */ 1705 switch (sc->sk_type) { 1706 case SK_GENESIS: 1707 sc->sk_name = sc->sk_vpd_prodname; 1708 break; 1709 case SK_YUKON: 1710 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1711 break; 1712 case SK_YUKON_LITE: 1713 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1714 break; 1715 case SK_YUKON_LP: 1716 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1717 break; 1718 default: 1719 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1720 } 1721 1722 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1723 1724 if ( sc->sk_type == SK_YUKON ) { 1725 uint32_t flashaddr; 1726 uint8_t testbyte; 1727 1728 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1729 1730 /* test Flash-Address Register */ 1731 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1732 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1733 1734 if (testbyte != 0) { 1735 /* this is yukon lite Rev. A0 */ 1736 sc->sk_type = SK_YUKON_LITE; 1737 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1738 /* restore Flash-Address Register */ 1739 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1740 } 1741 } 1742 break; 1743 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1744 sc->sk_name = sc->sk_vpd_prodname; 1745 break; 1746 default: 1747 sc->sk_name = "Unknown Marvell"; 1748 } 1749 1750 1751 if ( sc->sk_type == SK_YUKON_LITE ) { 1752 switch (sc->sk_rev) { 1753 case SK_YUKON_LITE_REV_A0: 1754 revstr = "A0"; 1755 break; 1756 case SK_YUKON_LITE_REV_A1: 1757 revstr = "A1"; 1758 break; 1759 case SK_YUKON_LITE_REV_A3: 1760 revstr = "A3"; 1761 break; 1762 default: 1763 revstr = ""; 1764 } 1765 } else { 1766 revstr = ""; 1767 } 1768 1769 /* Announce the product name. */ 1770 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1771 sc->sk_name, revstr, sc->sk_rev); 1772 1773 skca.skc_port = SK_PORT_A; 1774 (void)config_found(sc->sk_dev, &skca, skcprint); 1775 1776 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1777 skca.skc_port = SK_PORT_B; 1778 (void)config_found(sc->sk_dev, &skca, skcprint); 1779 } 1780 1781 /* Turn on the 'driver is loaded' LED. */ 1782 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1783 1784 /* skc sysctl setup */ 1785 1786 sc->sk_int_mod = SK_IM_DEFAULT; 1787 sc->sk_int_mod_pending = 0; 1788 1789 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1790 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1791 SYSCTL_DESCR("skc per-controller controls"), 1792 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1793 CTL_EOL)) != 0) { 1794 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1795 goto fail_1; 1796 } 1797 1798 sk_nodenum = node->sysctl_num; 1799 1800 /* interrupt moderation time in usecs */ 1801 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1802 CTLFLAG_READWRITE, 1803 CTLTYPE_INT, "int_mod", 1804 SYSCTL_DESCR("sk interrupt moderation timer"), 1805 sk_sysctl_handler, 0, sc, 1806 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1807 CTL_EOL)) != 0) { 1808 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1809 goto fail_1; 1810 } 1811 1812 return; 1813 1814 fail_1: 1815 pci_intr_disestablish(pc, sc->sk_intrhand); 1816 fail: 1817 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1818 } 1819 1820 int 1821 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1822 { 1823 struct sk_softc *sc = sc_if->sk_softc; 1824 struct sk_tx_desc *f = NULL; 1825 u_int32_t frag, cur, cnt = 0, sk_ctl; 1826 int i; 1827 struct sk_txmap_entry *entry; 1828 bus_dmamap_t txmap; 1829 1830 DPRINTFN(3, ("sk_encap\n")); 1831 1832 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1833 if (entry == NULL) { 1834 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1835 return ENOBUFS; 1836 } 1837 txmap = entry->dmamap; 1838 1839 cur = frag = *txidx; 1840 1841 #ifdef SK_DEBUG 1842 if (skdebug >= 3) 1843 sk_dump_mbuf(m_head); 1844 #endif 1845 1846 /* 1847 * Start packing the mbufs in this chain into 1848 * the fragment pointers. Stop when we run out 1849 * of fragments or hit the end of the mbuf chain. 1850 */ 1851 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1852 BUS_DMA_NOWAIT)) { 1853 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1854 return ENOBUFS; 1855 } 1856 1857 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1858 1859 /* Sync the DMA map. */ 1860 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1861 BUS_DMASYNC_PREWRITE); 1862 1863 for (i = 0; i < txmap->dm_nsegs; i++) { 1864 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1865 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1866 return ENOBUFS; 1867 } 1868 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1869 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1870 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1871 if (cnt == 0) 1872 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1873 else 1874 sk_ctl |= SK_TXCTL_OWN; 1875 f->sk_ctl = htole32(sk_ctl); 1876 cur = frag; 1877 SK_INC(frag, SK_TX_RING_CNT); 1878 cnt++; 1879 } 1880 1881 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1882 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1883 1884 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1885 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1886 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1887 1888 /* Sync descriptors before handing to chip */ 1889 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1890 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1891 1892 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1893 htole32(SK_TXCTL_OWN); 1894 1895 /* Sync first descriptor to hand it off */ 1896 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1897 1898 sc_if->sk_cdata.sk_tx_cnt += cnt; 1899 1900 #ifdef SK_DEBUG 1901 if (skdebug >= 3) { 1902 struct sk_tx_desc *desc; 1903 u_int32_t idx; 1904 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1905 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1906 sk_dump_txdesc(desc, idx); 1907 } 1908 } 1909 #endif 1910 1911 *txidx = frag; 1912 1913 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1914 1915 return 0; 1916 } 1917 1918 void 1919 sk_start(struct ifnet *ifp) 1920 { 1921 struct sk_if_softc *sc_if = ifp->if_softc; 1922 struct sk_softc *sc = sc_if->sk_softc; 1923 struct mbuf *m_head = NULL; 1924 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1925 int pkts = 0; 1926 1927 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1928 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1929 1930 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1931 IFQ_POLL(&ifp->if_snd, m_head); 1932 if (m_head == NULL) 1933 break; 1934 1935 /* 1936 * Pack the data into the transmit ring. If we 1937 * don't have room, set the OACTIVE flag and wait 1938 * for the NIC to drain the ring. 1939 */ 1940 if (sk_encap(sc_if, m_head, &idx)) { 1941 ifp->if_flags |= IFF_OACTIVE; 1942 break; 1943 } 1944 1945 /* now we are committed to transmit the packet */ 1946 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1947 pkts++; 1948 1949 /* 1950 * If there's a BPF listener, bounce a copy of this frame 1951 * to him. 1952 */ 1953 #if NBPFILTER > 0 1954 if (ifp->if_bpf) 1955 bpf_mtap(ifp->if_bpf, m_head); 1956 #endif 1957 } 1958 if (pkts == 0) 1959 return; 1960 1961 /* Transmit */ 1962 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1963 sc_if->sk_cdata.sk_tx_prod = idx; 1964 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1965 1966 /* Set a timeout in case the chip goes out to lunch. */ 1967 ifp->if_timer = 5; 1968 } 1969 } 1970 1971 1972 void 1973 sk_watchdog(struct ifnet *ifp) 1974 { 1975 struct sk_if_softc *sc_if = ifp->if_softc; 1976 1977 /* 1978 * Reclaim first as there is a possibility of losing Tx completion 1979 * interrupts. 1980 */ 1981 sk_txeof(sc_if); 1982 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1983 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1984 1985 ifp->if_oerrors++; 1986 1987 sk_init(ifp); 1988 } 1989 } 1990 1991 void 1992 sk_shutdown(void *v) 1993 { 1994 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1995 struct sk_softc *sc = sc_if->sk_softc; 1996 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1997 1998 DPRINTFN(2, ("sk_shutdown\n")); 1999 sk_stop(ifp,1); 2000 2001 /* Turn off the 'driver is loaded' LED. */ 2002 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2003 2004 /* 2005 * Reset the GEnesis controller. Doing this should also 2006 * assert the resets on the attached XMAC(s). 2007 */ 2008 sk_reset(sc); 2009 } 2010 2011 void 2012 sk_rxeof(struct sk_if_softc *sc_if) 2013 { 2014 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2015 struct mbuf *m; 2016 struct sk_chain *cur_rx; 2017 struct sk_rx_desc *cur_desc; 2018 int i, cur, total_len = 0; 2019 u_int32_t rxstat, sk_ctl; 2020 bus_dmamap_t dmamap; 2021 2022 i = sc_if->sk_cdata.sk_rx_prod; 2023 2024 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2025 2026 for (;;) { 2027 cur = i; 2028 2029 /* Sync the descriptor */ 2030 SK_CDRXSYNC(sc_if, cur, 2031 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2032 2033 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2034 if (sk_ctl & SK_RXCTL_OWN) { 2035 /* Invalidate the descriptor -- it's not ready yet */ 2036 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2037 sc_if->sk_cdata.sk_rx_prod = i; 2038 break; 2039 } 2040 2041 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2042 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2043 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2044 2045 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2046 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2047 2048 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2049 m = cur_rx->sk_mbuf; 2050 cur_rx->sk_mbuf = NULL; 2051 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2052 2053 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2054 2055 SK_INC(i, SK_RX_RING_CNT); 2056 2057 if (rxstat & XM_RXSTAT_ERRFRAME) { 2058 ifp->if_ierrors++; 2059 sk_newbuf(sc_if, cur, m, dmamap); 2060 continue; 2061 } 2062 2063 /* 2064 * Try to allocate a new jumbo buffer. If that 2065 * fails, copy the packet to mbufs and put the 2066 * jumbo buffer back in the ring so it can be 2067 * re-used. If allocating mbufs fails, then we 2068 * have to drop the packet. 2069 */ 2070 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2071 struct mbuf *m0; 2072 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2073 total_len + ETHER_ALIGN, 0, ifp, NULL); 2074 sk_newbuf(sc_if, cur, m, dmamap); 2075 if (m0 == NULL) { 2076 aprint_error_dev(sc_if->sk_dev, "no receive " 2077 "buffers available -- packet dropped!\n"); 2078 ifp->if_ierrors++; 2079 continue; 2080 } 2081 m_adj(m0, ETHER_ALIGN); 2082 m = m0; 2083 } else { 2084 m->m_pkthdr.rcvif = ifp; 2085 m->m_pkthdr.len = m->m_len = total_len; 2086 } 2087 2088 ifp->if_ipackets++; 2089 2090 #if NBPFILTER > 0 2091 if (ifp->if_bpf) 2092 bpf_mtap(ifp->if_bpf, m); 2093 #endif 2094 /* pass it on. */ 2095 (*ifp->if_input)(ifp, m); 2096 } 2097 } 2098 2099 void 2100 sk_txeof(struct sk_if_softc *sc_if) 2101 { 2102 struct sk_softc *sc = sc_if->sk_softc; 2103 struct sk_tx_desc *cur_tx; 2104 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2105 u_int32_t idx, sk_ctl; 2106 struct sk_txmap_entry *entry; 2107 2108 DPRINTFN(3, ("sk_txeof\n")); 2109 2110 /* 2111 * Go through our tx ring and free mbufs for those 2112 * frames that have been sent. 2113 */ 2114 idx = sc_if->sk_cdata.sk_tx_cons; 2115 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2116 SK_CDTXSYNC(sc_if, idx, 1, 2117 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2118 2119 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2120 sk_ctl = le32toh(cur_tx->sk_ctl); 2121 #ifdef SK_DEBUG 2122 if (skdebug >= 3) 2123 sk_dump_txdesc(cur_tx, idx); 2124 #endif 2125 if (sk_ctl & SK_TXCTL_OWN) { 2126 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2127 break; 2128 } 2129 if (sk_ctl & SK_TXCTL_LASTFRAG) 2130 ifp->if_opackets++; 2131 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2132 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2133 2134 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2135 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2136 2137 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2138 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2139 2140 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2141 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2142 link); 2143 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2144 } 2145 sc_if->sk_cdata.sk_tx_cnt--; 2146 SK_INC(idx, SK_TX_RING_CNT); 2147 } 2148 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2149 ifp->if_timer = 0; 2150 else /* nudge chip to keep tx ring moving */ 2151 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2152 2153 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2154 ifp->if_flags &= ~IFF_OACTIVE; 2155 2156 sc_if->sk_cdata.sk_tx_cons = idx; 2157 } 2158 2159 void 2160 sk_tick(void *xsc_if) 2161 { 2162 struct sk_if_softc *sc_if = xsc_if; 2163 struct mii_data *mii = &sc_if->sk_mii; 2164 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2165 int i; 2166 2167 DPRINTFN(3, ("sk_tick\n")); 2168 2169 if (!(ifp->if_flags & IFF_UP)) 2170 return; 2171 2172 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2173 sk_intr_bcom(sc_if); 2174 return; 2175 } 2176 2177 /* 2178 * According to SysKonnect, the correct way to verify that 2179 * the link has come back up is to poll bit 0 of the GPIO 2180 * register three times. This pin has the signal from the 2181 * link sync pin connected to it; if we read the same link 2182 * state 3 times in a row, we know the link is up. 2183 */ 2184 for (i = 0; i < 3; i++) { 2185 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2186 break; 2187 } 2188 2189 if (i != 3) { 2190 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2191 return; 2192 } 2193 2194 /* Turn the GP0 interrupt back on. */ 2195 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2196 SK_XM_READ_2(sc_if, XM_ISR); 2197 mii_tick(mii); 2198 mii_pollstat(mii); 2199 callout_stop(&sc_if->sk_tick_ch); 2200 } 2201 2202 void 2203 sk_intr_bcom(struct sk_if_softc *sc_if) 2204 { 2205 struct mii_data *mii = &sc_if->sk_mii; 2206 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2207 int status; 2208 2209 2210 DPRINTFN(3, ("sk_intr_bcom\n")); 2211 2212 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2213 2214 /* 2215 * Read the PHY interrupt register to make sure 2216 * we clear any pending interrupts. 2217 */ 2218 status = sk_xmac_miibus_readreg(sc_if->sk_dev, 2219 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2220 2221 if (!(ifp->if_flags & IFF_RUNNING)) { 2222 sk_init_xmac(sc_if); 2223 return; 2224 } 2225 2226 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2227 int lstat; 2228 lstat = sk_xmac_miibus_readreg(sc_if->sk_dev, 2229 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2230 2231 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2232 (void)mii_mediachg(mii); 2233 /* Turn off the link LED. */ 2234 SK_IF_WRITE_1(sc_if, 0, 2235 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2236 sc_if->sk_link = 0; 2237 } else if (status & BRGPHY_ISR_LNK_CHG) { 2238 sk_xmac_miibus_writereg(sc_if->sk_dev, 2239 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2240 mii_tick(mii); 2241 sc_if->sk_link = 1; 2242 /* Turn on the link LED. */ 2243 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2244 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2245 SK_LINKLED_BLINK_OFF); 2246 mii_pollstat(mii); 2247 } else { 2248 mii_tick(mii); 2249 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2250 } 2251 } 2252 2253 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2254 } 2255 2256 void 2257 sk_intr_xmac(struct sk_if_softc *sc_if) 2258 { 2259 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2260 2261 DPRINTFN(3, ("sk_intr_xmac\n")); 2262 2263 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2264 if (status & XM_ISR_GP0_SET) { 2265 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2266 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2267 } 2268 2269 if (status & XM_ISR_AUTONEG_DONE) { 2270 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2271 } 2272 } 2273 2274 if (status & XM_IMR_TX_UNDERRUN) 2275 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2276 2277 if (status & XM_IMR_RX_OVERRUN) 2278 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2279 } 2280 2281 void 2282 sk_intr_yukon(struct sk_if_softc *sc_if) 2283 { 2284 int status; 2285 2286 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2287 2288 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2289 } 2290 2291 int 2292 sk_intr(void *xsc) 2293 { 2294 struct sk_softc *sc = xsc; 2295 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2296 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2297 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2298 u_int32_t status; 2299 int claimed = 0; 2300 2301 if (sc_if0 != NULL) 2302 ifp0 = &sc_if0->sk_ethercom.ec_if; 2303 if (sc_if1 != NULL) 2304 ifp1 = &sc_if1->sk_ethercom.ec_if; 2305 2306 for (;;) { 2307 status = CSR_READ_4(sc, SK_ISSR); 2308 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2309 2310 if (!(status & sc->sk_intrmask)) 2311 break; 2312 2313 claimed = 1; 2314 2315 /* Handle receive interrupts first. */ 2316 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2317 sk_rxeof(sc_if0); 2318 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2319 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2320 } 2321 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2322 sk_rxeof(sc_if1); 2323 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2324 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2325 } 2326 2327 /* Then transmit interrupts. */ 2328 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2329 sk_txeof(sc_if0); 2330 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2331 SK_TXBMU_CLR_IRQ_EOF); 2332 } 2333 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2334 sk_txeof(sc_if1); 2335 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2336 SK_TXBMU_CLR_IRQ_EOF); 2337 } 2338 2339 /* Then MAC interrupts. */ 2340 if (sc_if0 && (status & SK_ISR_MAC1) && 2341 (ifp0->if_flags & IFF_RUNNING)) { 2342 if (sc->sk_type == SK_GENESIS) 2343 sk_intr_xmac(sc_if0); 2344 else 2345 sk_intr_yukon(sc_if0); 2346 } 2347 2348 if (sc_if1 && (status & SK_ISR_MAC2) && 2349 (ifp1->if_flags & IFF_RUNNING)) { 2350 if (sc->sk_type == SK_GENESIS) 2351 sk_intr_xmac(sc_if1); 2352 else 2353 sk_intr_yukon(sc_if1); 2354 2355 } 2356 2357 if (status & SK_ISR_EXTERNAL_REG) { 2358 if (sc_if0 != NULL && 2359 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2360 sk_intr_bcom(sc_if0); 2361 2362 if (sc_if1 != NULL && 2363 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2364 sk_intr_bcom(sc_if1); 2365 } 2366 } 2367 2368 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2369 2370 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2371 sk_start(ifp0); 2372 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2373 sk_start(ifp1); 2374 2375 #if NRND > 0 2376 if (RND_ENABLED(&sc->rnd_source)) 2377 rnd_add_uint32(&sc->rnd_source, status); 2378 #endif 2379 2380 if (sc->sk_int_mod_pending) 2381 sk_update_int_mod(sc); 2382 2383 return claimed; 2384 } 2385 2386 void 2387 sk_init_xmac(struct sk_if_softc *sc_if) 2388 { 2389 struct sk_softc *sc = sc_if->sk_softc; 2390 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2391 static const struct sk_bcom_hack bhack[] = { 2392 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2393 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2394 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2395 { 0, 0 } }; 2396 2397 DPRINTFN(1, ("sk_init_xmac\n")); 2398 2399 /* Unreset the XMAC. */ 2400 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2401 DELAY(1000); 2402 2403 /* Reset the XMAC's internal state. */ 2404 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2405 2406 /* Save the XMAC II revision */ 2407 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2408 2409 /* 2410 * Perform additional initialization for external PHYs, 2411 * namely for the 1000baseTX cards that use the XMAC's 2412 * GMII mode. 2413 */ 2414 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2415 int i = 0; 2416 u_int32_t val; 2417 2418 /* Take PHY out of reset. */ 2419 val = sk_win_read_4(sc, SK_GPIO); 2420 if (sc_if->sk_port == SK_PORT_A) 2421 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2422 else 2423 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2424 sk_win_write_4(sc, SK_GPIO, val); 2425 2426 /* Enable GMII mode on the XMAC. */ 2427 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2428 2429 sk_xmac_miibus_writereg(sc_if->sk_dev, 2430 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2431 DELAY(10000); 2432 sk_xmac_miibus_writereg(sc_if->sk_dev, 2433 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2434 2435 /* 2436 * Early versions of the BCM5400 apparently have 2437 * a bug that requires them to have their reserved 2438 * registers initialized to some magic values. I don't 2439 * know what the numbers do, I'm just the messenger. 2440 */ 2441 if (sk_xmac_miibus_readreg(sc_if->sk_dev, 2442 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2443 while (bhack[i].reg) { 2444 sk_xmac_miibus_writereg(sc_if->sk_dev, 2445 SK_PHYADDR_BCOM, bhack[i].reg, 2446 bhack[i].val); 2447 i++; 2448 } 2449 } 2450 } 2451 2452 /* Set station address */ 2453 SK_XM_WRITE_2(sc_if, XM_PAR0, 2454 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2455 SK_XM_WRITE_2(sc_if, XM_PAR1, 2456 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2457 SK_XM_WRITE_2(sc_if, XM_PAR2, 2458 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2459 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2460 2461 if (ifp->if_flags & IFF_PROMISC) 2462 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2463 else 2464 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2465 2466 if (ifp->if_flags & IFF_BROADCAST) 2467 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2468 else 2469 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2470 2471 /* We don't need the FCS appended to the packet. */ 2472 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2473 2474 /* We want short frames padded to 60 bytes. */ 2475 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2476 2477 /* 2478 * Enable the reception of all error frames. This is is 2479 * a necessary evil due to the design of the XMAC. The 2480 * XMAC's receive FIFO is only 8K in size, however jumbo 2481 * frames can be up to 9000 bytes in length. When bad 2482 * frame filtering is enabled, the XMAC's RX FIFO operates 2483 * in 'store and forward' mode. For this to work, the 2484 * entire frame has to fit into the FIFO, but that means 2485 * that jumbo frames larger than 8192 bytes will be 2486 * truncated. Disabling all bad frame filtering causes 2487 * the RX FIFO to operate in streaming mode, in which 2488 * case the XMAC will start transfering frames out of the 2489 * RX FIFO as soon as the FIFO threshold is reached. 2490 */ 2491 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2492 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2493 XM_MODE_RX_INRANGELEN); 2494 2495 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2496 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2497 else 2498 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2499 2500 /* 2501 * Bump up the transmit threshold. This helps hold off transmit 2502 * underruns when we're blasting traffic from both ports at once. 2503 */ 2504 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2505 2506 /* Set multicast filter */ 2507 sk_setmulti(sc_if); 2508 2509 /* Clear and enable interrupts */ 2510 SK_XM_READ_2(sc_if, XM_ISR); 2511 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2512 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2513 else 2514 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2515 2516 /* Configure MAC arbiter */ 2517 switch (sc_if->sk_xmac_rev) { 2518 case XM_XMAC_REV_B2: 2519 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2520 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2521 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2522 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2523 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2524 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2525 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2526 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2527 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2528 break; 2529 case XM_XMAC_REV_C1: 2530 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2531 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2532 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2533 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2534 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2535 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2536 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2537 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2538 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2539 break; 2540 default: 2541 break; 2542 } 2543 sk_win_write_2(sc, SK_MACARB_CTL, 2544 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2545 2546 sc_if->sk_link = 1; 2547 } 2548 2549 void sk_init_yukon(struct sk_if_softc *sc_if) 2550 { 2551 u_int32_t /*mac, */phy; 2552 u_int16_t reg; 2553 struct sk_softc *sc; 2554 int i; 2555 2556 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2557 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2558 2559 sc = sc_if->sk_softc; 2560 if (sc->sk_type == SK_YUKON_LITE && 2561 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2562 /* Take PHY out of reset. */ 2563 sk_win_write_4(sc, SK_GPIO, 2564 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2565 } 2566 2567 2568 /* GMAC and GPHY Reset */ 2569 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2570 2571 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2572 2573 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2574 DELAY(1000); 2575 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2576 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2577 DELAY(1000); 2578 2579 2580 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2581 2582 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2583 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2584 2585 switch (sc_if->sk_softc->sk_pmd) { 2586 case IFM_1000_SX: 2587 case IFM_1000_LX: 2588 phy |= SK_GPHY_FIBER; 2589 break; 2590 2591 case IFM_1000_CX: 2592 case IFM_1000_T: 2593 phy |= SK_GPHY_COPPER; 2594 break; 2595 } 2596 2597 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2598 2599 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2600 DELAY(1000); 2601 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2602 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2603 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2604 2605 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2606 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2607 2608 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2609 2610 /* unused read of the interrupt source register */ 2611 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2612 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2613 2614 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2615 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2616 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2617 2618 /* MIB Counter Clear Mode set */ 2619 reg |= YU_PAR_MIB_CLR; 2620 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2621 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2622 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2623 2624 /* MIB Counter Clear Mode clear */ 2625 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2626 reg &= ~YU_PAR_MIB_CLR; 2627 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2628 2629 /* receive control reg */ 2630 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2631 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2632 YU_RCR_CRCR); 2633 2634 /* transmit parameter register */ 2635 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2636 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2637 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2638 2639 /* serial mode register */ 2640 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2641 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2642 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2643 YU_SMR_IPG_DATA(0x1e)); 2644 2645 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2646 /* Setup Yukon's address */ 2647 for (i = 0; i < 3; i++) { 2648 /* Write Source Address 1 (unicast filter) */ 2649 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2650 sc_if->sk_enaddr[i * 2] | 2651 sc_if->sk_enaddr[i * 2 + 1] << 8); 2652 } 2653 2654 for (i = 0; i < 3; i++) { 2655 reg = sk_win_read_2(sc_if->sk_softc, 2656 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2657 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2658 } 2659 2660 /* Set multicast filter */ 2661 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2662 sk_setmulti(sc_if); 2663 2664 /* enable interrupt mask for counter overflows */ 2665 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2666 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2667 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2668 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2669 2670 /* Configure RX MAC FIFO */ 2671 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2672 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2673 2674 /* Configure TX MAC FIFO */ 2675 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2676 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2677 2678 DPRINTFN(6, ("sk_init_yukon: end\n")); 2679 } 2680 2681 /* 2682 * Note that to properly initialize any part of the GEnesis chip, 2683 * you first have to take it out of reset mode. 2684 */ 2685 int 2686 sk_init(struct ifnet *ifp) 2687 { 2688 struct sk_if_softc *sc_if = ifp->if_softc; 2689 struct sk_softc *sc = sc_if->sk_softc; 2690 struct mii_data *mii = &sc_if->sk_mii; 2691 int rc = 0, s; 2692 u_int32_t imr, imtimer_ticks; 2693 2694 DPRINTFN(1, ("sk_init\n")); 2695 2696 s = splnet(); 2697 2698 if (ifp->if_flags & IFF_RUNNING) { 2699 splx(s); 2700 return 0; 2701 } 2702 2703 /* Cancel pending I/O and free all RX/TX buffers. */ 2704 sk_stop(ifp,0); 2705 2706 if (sc->sk_type == SK_GENESIS) { 2707 /* Configure LINK_SYNC LED */ 2708 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2709 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2710 SK_LINKLED_LINKSYNC_ON); 2711 2712 /* Configure RX LED */ 2713 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2714 SK_RXLEDCTL_COUNTER_START); 2715 2716 /* Configure TX LED */ 2717 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2718 SK_TXLEDCTL_COUNTER_START); 2719 } 2720 2721 /* Configure I2C registers */ 2722 2723 /* Configure XMAC(s) */ 2724 switch (sc->sk_type) { 2725 case SK_GENESIS: 2726 sk_init_xmac(sc_if); 2727 break; 2728 case SK_YUKON: 2729 case SK_YUKON_LITE: 2730 case SK_YUKON_LP: 2731 sk_init_yukon(sc_if); 2732 break; 2733 } 2734 if ((rc = mii_mediachg(mii)) == ENXIO) 2735 rc = 0; 2736 else if (rc != 0) 2737 goto out; 2738 2739 if (sc->sk_type == SK_GENESIS) { 2740 /* Configure MAC FIFOs */ 2741 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2742 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2743 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2744 2745 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2746 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2747 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2748 } 2749 2750 /* Configure transmit arbiter(s) */ 2751 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2752 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2753 2754 /* Configure RAMbuffers */ 2755 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2756 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2757 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2758 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2759 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2760 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2761 2762 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2763 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2764 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2765 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2766 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2767 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2768 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2769 2770 /* Configure BMUs */ 2771 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2772 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2773 SK_RX_RING_ADDR(sc_if, 0)); 2774 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2775 2776 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2777 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2778 SK_TX_RING_ADDR(sc_if, 0)); 2779 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2780 2781 /* Init descriptors */ 2782 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2783 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2784 "memory for rx buffers\n"); 2785 sk_stop(ifp,0); 2786 splx(s); 2787 return ENOBUFS; 2788 } 2789 2790 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2791 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2792 "memory for tx buffers\n"); 2793 sk_stop(ifp,0); 2794 splx(s); 2795 return ENOBUFS; 2796 } 2797 2798 /* Set interrupt moderation if changed via sysctl. */ 2799 switch (sc->sk_type) { 2800 case SK_GENESIS: 2801 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2802 break; 2803 case SK_YUKON_EC: 2804 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2805 break; 2806 default: 2807 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2808 } 2809 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2810 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2811 sk_win_write_4(sc, SK_IMTIMERINIT, 2812 SK_IM_USECS(sc->sk_int_mod)); 2813 aprint_verbose_dev(sc->sk_dev, 2814 "interrupt moderation is %d us\n", sc->sk_int_mod); 2815 } 2816 2817 /* Configure interrupt handling */ 2818 CSR_READ_4(sc, SK_ISSR); 2819 if (sc_if->sk_port == SK_PORT_A) 2820 sc->sk_intrmask |= SK_INTRS1; 2821 else 2822 sc->sk_intrmask |= SK_INTRS2; 2823 2824 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2825 2826 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2827 2828 /* Start BMUs. */ 2829 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2830 2831 if (sc->sk_type == SK_GENESIS) { 2832 /* Enable XMACs TX and RX state machines */ 2833 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2834 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2835 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2836 } 2837 2838 if (SK_YUKON_FAMILY(sc->sk_type)) { 2839 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2840 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2841 #if 0 2842 /* XXX disable 100Mbps and full duplex mode? */ 2843 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2844 #endif 2845 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2846 } 2847 2848 2849 ifp->if_flags |= IFF_RUNNING; 2850 ifp->if_flags &= ~IFF_OACTIVE; 2851 2852 out: 2853 splx(s); 2854 return rc; 2855 } 2856 2857 void 2858 sk_stop(struct ifnet *ifp, int disable) 2859 { 2860 struct sk_if_softc *sc_if = ifp->if_softc; 2861 struct sk_softc *sc = sc_if->sk_softc; 2862 int i; 2863 2864 DPRINTFN(1, ("sk_stop\n")); 2865 2866 callout_stop(&sc_if->sk_tick_ch); 2867 2868 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2869 u_int32_t val; 2870 2871 /* Put PHY back into reset. */ 2872 val = sk_win_read_4(sc, SK_GPIO); 2873 if (sc_if->sk_port == SK_PORT_A) { 2874 val |= SK_GPIO_DIR0; 2875 val &= ~SK_GPIO_DAT0; 2876 } else { 2877 val |= SK_GPIO_DIR2; 2878 val &= ~SK_GPIO_DAT2; 2879 } 2880 sk_win_write_4(sc, SK_GPIO, val); 2881 } 2882 2883 /* Turn off various components of this interface. */ 2884 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2885 switch (sc->sk_type) { 2886 case SK_GENESIS: 2887 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2888 SK_TXMACCTL_XMAC_RESET); 2889 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2890 break; 2891 case SK_YUKON: 2892 case SK_YUKON_LITE: 2893 case SK_YUKON_LP: 2894 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2895 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2896 break; 2897 } 2898 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2899 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2900 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2901 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2902 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2903 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2904 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2905 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2906 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2907 2908 /* Disable interrupts */ 2909 if (sc_if->sk_port == SK_PORT_A) 2910 sc->sk_intrmask &= ~SK_INTRS1; 2911 else 2912 sc->sk_intrmask &= ~SK_INTRS2; 2913 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2914 2915 SK_XM_READ_2(sc_if, XM_ISR); 2916 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2917 2918 /* Free RX and TX mbufs still in the queues. */ 2919 for (i = 0; i < SK_RX_RING_CNT; i++) { 2920 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2921 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2922 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2923 } 2924 } 2925 2926 for (i = 0; i < SK_TX_RING_CNT; i++) { 2927 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2928 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2929 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2930 } 2931 } 2932 2933 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2934 } 2935 2936 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 2937 skc_probe, skc_attach, NULL, NULL); 2938 2939 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 2940 sk_probe, sk_attach, NULL, NULL); 2941 2942 #ifdef SK_DEBUG 2943 void 2944 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2945 { 2946 #define DESC_PRINT(X) \ 2947 if (X) \ 2948 printf("txdesc[%d]." #X "=%#x\n", \ 2949 idx, X); 2950 2951 DESC_PRINT(le32toh(desc->sk_ctl)); 2952 DESC_PRINT(le32toh(desc->sk_next)); 2953 DESC_PRINT(le32toh(desc->sk_data_lo)); 2954 DESC_PRINT(le32toh(desc->sk_data_hi)); 2955 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2956 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2957 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2958 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2959 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2960 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2961 #undef PRINT 2962 } 2963 2964 void 2965 sk_dump_bytes(const char *data, int len) 2966 { 2967 int c, i, j; 2968 2969 for (i = 0; i < len; i += 16) { 2970 printf("%08x ", i); 2971 c = len - i; 2972 if (c > 16) c = 16; 2973 2974 for (j = 0; j < c; j++) { 2975 printf("%02x ", data[i + j] & 0xff); 2976 if ((j & 0xf) == 7 && j > 0) 2977 printf(" "); 2978 } 2979 2980 for (; j < 16; j++) 2981 printf(" "); 2982 printf(" "); 2983 2984 for (j = 0; j < c; j++) { 2985 int ch = data[i + j] & 0xff; 2986 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2987 } 2988 2989 printf("\n"); 2990 2991 if (c < 16) 2992 break; 2993 } 2994 } 2995 2996 void 2997 sk_dump_mbuf(struct mbuf *m) 2998 { 2999 int count = m->m_pkthdr.len; 3000 3001 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3002 3003 while (count > 0 && m) { 3004 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3005 m, m->m_data, m->m_len); 3006 sk_dump_bytes(mtod(m, char *), m->m_len); 3007 3008 count -= m->m_len; 3009 m = m->m_next; 3010 } 3011 } 3012 #endif 3013 3014 static int 3015 sk_sysctl_handler(SYSCTLFN_ARGS) 3016 { 3017 int error, t; 3018 struct sysctlnode node; 3019 struct sk_softc *sc; 3020 3021 node = *rnode; 3022 sc = node.sysctl_data; 3023 t = sc->sk_int_mod; 3024 node.sysctl_data = &t; 3025 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3026 if (error || newp == NULL) 3027 return error; 3028 3029 if (t < SK_IM_MIN || t > SK_IM_MAX) 3030 return EINVAL; 3031 3032 /* update the softc with sysctl-changed value, and mark 3033 for hardware update */ 3034 sc->sk_int_mod = t; 3035 sc->sk_int_mod_pending = 1; 3036 return 0; 3037 } 3038 3039 /* 3040 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3041 * set up in skc_attach() 3042 */ 3043 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3044 { 3045 int rc; 3046 const struct sysctlnode *node; 3047 3048 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3049 0, CTLTYPE_NODE, "hw", NULL, 3050 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3051 goto err; 3052 } 3053 3054 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3055 0, CTLTYPE_NODE, "sk", 3056 SYSCTL_DESCR("sk interface controls"), 3057 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3058 goto err; 3059 } 3060 3061 sk_root_num = node->sysctl_num; 3062 return; 3063 3064 err: 3065 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3066 } 3067
Indexes created Mon Sep 22 21:09:42 GMT 2025