if_sk.c revision 1.55
1 /* $NetBSD: if_sk.c,v 1.55 2008/11/07 00:20:07 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.55 2008/11/07 00:20:07 dyoung Exp $"); 119 120 #include "bpfilter.h" 121 #include "rnd.h" 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/sockio.h> 126 #include <sys/mbuf.h> 127 #include <sys/malloc.h> 128 #include <sys/mutex.h> 129 #include <sys/kernel.h> 130 #include <sys/socket.h> 131 #include <sys/device.h> 132 #include <sys/queue.h> 133 #include <sys/callout.h> 134 #include <sys/sysctl.h> 135 #include <sys/endian.h> 136 137 #include <net/if.h> 138 #include <net/if_dl.h> 139 #include <net/if_types.h> 140 141 #include <net/if_media.h> 142 143 #if NBPFILTER > 0 144 #include <net/bpf.h> 145 #endif 146 #if NRND > 0 147 #include <sys/rnd.h> 148 #endif 149 150 #include <dev/mii/mii.h> 151 #include <dev/mii/miivar.h> 152 #include <dev/mii/brgphyreg.h> 153 154 #include <dev/pci/pcireg.h> 155 #include <dev/pci/pcivar.h> 156 #include <dev/pci/pcidevs.h> 157 158 /* #define SK_USEIOSPACE */ 159 160 #include <dev/pci/if_skreg.h> 161 #include <dev/pci/if_skvar.h> 162 163 int skc_probe(device_t, cfdata_t, void *); 164 void skc_attach(device_t, device_t, void *aux); 165 int sk_probe(device_t, cfdata_t, void *); 166 void sk_attach(device_t, device_t, void *aux); 167 int skcprint(void *, const char *); 168 int sk_intr(void *); 169 void sk_intr_bcom(struct sk_if_softc *); 170 void sk_intr_xmac(struct sk_if_softc *); 171 void sk_intr_yukon(struct sk_if_softc *); 172 void sk_rxeof(struct sk_if_softc *); 173 void sk_txeof(struct sk_if_softc *); 174 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 175 void sk_start(struct ifnet *); 176 int sk_ioctl(struct ifnet *, u_long, void *); 177 int sk_init(struct ifnet *); 178 void sk_init_xmac(struct sk_if_softc *); 179 void sk_init_yukon(struct sk_if_softc *); 180 void sk_stop(struct ifnet *, int); 181 void sk_watchdog(struct ifnet *); 182 void sk_shutdown(void *); 183 int sk_ifmedia_upd(struct ifnet *); 184 void sk_reset(struct sk_softc *); 185 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 186 int sk_alloc_jumbo_mem(struct sk_if_softc *); 187 void sk_free_jumbo_mem(struct sk_if_softc *); 188 void *sk_jalloc(struct sk_if_softc *); 189 void sk_jfree(struct mbuf *, void *, size_t, void *); 190 int sk_init_rx_ring(struct sk_if_softc *); 191 int sk_init_tx_ring(struct sk_if_softc *); 192 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 193 void sk_vpd_read_res(struct sk_softc *, 194 struct vpd_res *, int); 195 void sk_vpd_read(struct sk_softc *); 196 197 void sk_update_int_mod(struct sk_softc *); 198 199 int sk_xmac_miibus_readreg(device_t, int, int); 200 void sk_xmac_miibus_writereg(device_t, int, int, int); 201 void sk_xmac_miibus_statchg(device_t); 202 203 int sk_marv_miibus_readreg(device_t, int, int); 204 void sk_marv_miibus_writereg(device_t, int, int, int); 205 void sk_marv_miibus_statchg(device_t); 206 207 u_int32_t sk_xmac_hash(void *); 208 u_int32_t sk_yukon_hash(void *); 209 void sk_setfilt(struct sk_if_softc *, void *, int); 210 void sk_setmulti(struct sk_if_softc *); 211 void sk_tick(void *); 212 213 /* #define SK_DEBUG 2 */ 214 #ifdef SK_DEBUG 215 #define DPRINTF(x) if (skdebug) printf x 216 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 217 int skdebug = SK_DEBUG; 218 219 void sk_dump_txdesc(struct sk_tx_desc *, int); 220 void sk_dump_mbuf(struct mbuf *); 221 void sk_dump_bytes(const char *, int); 222 #else 223 #define DPRINTF(x) 224 #define DPRINTFN(n,x) 225 #endif 226 227 static int sk_sysctl_handler(SYSCTLFN_PROTO); 228 static int sk_root_num; 229 230 /* supported device vendors */ 231 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 232 static const struct sk_product { 233 pci_vendor_id_t sk_vendor; 234 pci_product_id_t sk_product; 235 } sk_products[] = { 236 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 237 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 238 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 239 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 240 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 241 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 242 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 243 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 244 { 0, 0, } 245 }; 246 247 #define SK_LINKSYS_EG1032_SUBID 0x00151737 248 249 static inline u_int32_t 250 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 251 { 252 #ifdef SK_USEIOSPACE 253 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 254 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 255 #else 256 return CSR_READ_4(sc, reg); 257 #endif 258 } 259 260 static inline u_int16_t 261 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 262 { 263 #ifdef SK_USEIOSPACE 264 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 265 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 266 #else 267 return CSR_READ_2(sc, reg); 268 #endif 269 } 270 271 static inline u_int8_t 272 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 273 { 274 #ifdef SK_USEIOSPACE 275 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 276 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 277 #else 278 return CSR_READ_1(sc, reg); 279 #endif 280 } 281 282 static inline void 283 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 284 { 285 #ifdef SK_USEIOSPACE 286 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 287 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 288 #else 289 CSR_WRITE_4(sc, reg, x); 290 #endif 291 } 292 293 static inline void 294 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 295 { 296 #ifdef SK_USEIOSPACE 297 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 298 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 299 #else 300 CSR_WRITE_2(sc, reg, x); 301 #endif 302 } 303 304 static inline void 305 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 306 { 307 #ifdef SK_USEIOSPACE 308 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 309 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 310 #else 311 CSR_WRITE_1(sc, reg, x); 312 #endif 313 } 314 315 /* 316 * The VPD EEPROM contains Vital Product Data, as suggested in 317 * the PCI 2.1 specification. The VPD data is separared into areas 318 * denoted by resource IDs. The SysKonnect VPD contains an ID string 319 * resource (the name of the adapter), a read-only area resource 320 * containing various key/data fields and a read/write area which 321 * can be used to store asset management information or log messages. 322 * We read the ID string and read-only into buffers attached to 323 * the controller softc structure for later use. At the moment, 324 * we only use the ID string during sk_attach(). 325 */ 326 u_int8_t 327 sk_vpd_readbyte(struct sk_softc *sc, int addr) 328 { 329 int i; 330 331 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 332 for (i = 0; i < SK_TIMEOUT; i++) { 333 DELAY(1); 334 if (sk_win_read_2(sc, 335 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 336 break; 337 } 338 339 if (i == SK_TIMEOUT) 340 return 0; 341 342 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 343 } 344 345 void 346 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 347 { 348 int i; 349 u_int8_t *ptr; 350 351 ptr = (u_int8_t *)res; 352 for (i = 0; i < sizeof(struct vpd_res); i++) 353 ptr[i] = sk_vpd_readbyte(sc, i + addr); 354 } 355 356 void 357 sk_vpd_read(struct sk_softc *sc) 358 { 359 int pos = 0, i; 360 struct vpd_res res; 361 362 if (sc->sk_vpd_prodname != NULL) 363 free(sc->sk_vpd_prodname, M_DEVBUF); 364 if (sc->sk_vpd_readonly != NULL) 365 free(sc->sk_vpd_readonly, M_DEVBUF); 366 sc->sk_vpd_prodname = NULL; 367 sc->sk_vpd_readonly = NULL; 368 369 sk_vpd_read_res(sc, &res, pos); 370 371 if (res.vr_id != VPD_RES_ID) { 372 aprint_error_dev(sc->sk_dev, 373 "bad VPD resource id: expected %x got %x\n", 374 VPD_RES_ID, res.vr_id); 375 return; 376 } 377 378 pos += sizeof(res); 379 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 380 if (sc->sk_vpd_prodname == NULL) 381 panic("sk_vpd_read"); 382 for (i = 0; i < res.vr_len; i++) 383 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 384 sc->sk_vpd_prodname[i] = '\0'; 385 pos += i; 386 387 sk_vpd_read_res(sc, &res, pos); 388 389 if (res.vr_id != VPD_RES_READ) { 390 aprint_error_dev(sc->sk_dev, 391 "bad VPD resource id: expected %x got %x\n", 392 VPD_RES_READ, res.vr_id); 393 return; 394 } 395 396 pos += sizeof(res); 397 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 398 if (sc->sk_vpd_readonly == NULL) 399 panic("sk_vpd_read"); 400 for (i = 0; i < res.vr_len ; i++) 401 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 402 } 403 404 int 405 sk_xmac_miibus_readreg(device_t dev, int phy, int reg) 406 { 407 struct sk_if_softc *sc_if = device_private(dev); 408 int i; 409 410 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 411 412 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 413 return 0; 414 415 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 416 SK_XM_READ_2(sc_if, XM_PHY_DATA); 417 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 418 for (i = 0; i < SK_TIMEOUT; i++) { 419 DELAY(1); 420 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 421 XM_MMUCMD_PHYDATARDY) 422 break; 423 } 424 425 if (i == SK_TIMEOUT) { 426 aprint_error_dev(sc_if->sk_dev, 427 "phy failed to come ready\n"); 428 return 0; 429 } 430 } 431 DELAY(1); 432 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 433 } 434 435 void 436 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, int val) 437 { 438 struct sk_if_softc *sc_if = device_private(dev); 439 int i; 440 441 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 442 443 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 444 for (i = 0; i < SK_TIMEOUT; i++) { 445 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 446 break; 447 } 448 449 if (i == SK_TIMEOUT) { 450 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 451 return; 452 } 453 454 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 455 for (i = 0; i < SK_TIMEOUT; i++) { 456 DELAY(1); 457 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 458 break; 459 } 460 461 if (i == SK_TIMEOUT) 462 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 463 } 464 465 void 466 sk_xmac_miibus_statchg(device_t dev) 467 { 468 struct sk_if_softc *sc_if = device_private(dev); 469 struct mii_data *mii = &sc_if->sk_mii; 470 471 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 472 473 /* 474 * If this is a GMII PHY, manually set the XMAC's 475 * duplex mode accordingly. 476 */ 477 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 478 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 479 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 480 else 481 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 482 } 483 } 484 485 int 486 sk_marv_miibus_readreg(device_t dev, int phy, int reg) 487 { 488 struct sk_if_softc *sc_if = device_private(dev); 489 u_int16_t val; 490 int i; 491 492 if (phy != 0 || 493 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 494 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 495 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 496 phy, reg)); 497 return 0; 498 } 499 500 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 501 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 502 503 for (i = 0; i < SK_TIMEOUT; i++) { 504 DELAY(1); 505 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 506 if (val & YU_SMICR_READ_VALID) 507 break; 508 } 509 510 if (i == SK_TIMEOUT) { 511 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 512 return 0; 513 } 514 515 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 516 SK_TIMEOUT)); 517 518 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 519 520 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 521 phy, reg, val)); 522 523 return val; 524 } 525 526 void 527 sk_marv_miibus_writereg(device_t dev, int phy, int reg, int val) 528 { 529 struct sk_if_softc *sc_if = device_private(dev); 530 int i; 531 532 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 533 phy, reg, val)); 534 535 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 536 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 537 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 538 539 for (i = 0; i < SK_TIMEOUT; i++) { 540 DELAY(1); 541 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 542 break; 543 } 544 545 if (i == SK_TIMEOUT) 546 printf("%s: phy write timed out\n", 547 device_xname(sc_if->sk_dev)); 548 } 549 550 void 551 sk_marv_miibus_statchg(device_t dev) 552 { 553 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 554 SK_YU_READ_2(((struct sk_if_softc *)device_private(dev)), 555 YUKON_GPCR))); 556 } 557 558 #define SK_HASH_BITS 6 559 560 u_int32_t 561 sk_xmac_hash(void *addr) 562 { 563 u_int32_t crc; 564 565 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 566 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 567 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 568 return crc; 569 } 570 571 u_int32_t 572 sk_yukon_hash(void *addr) 573 { 574 u_int32_t crc; 575 576 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 577 crc &= ((1 << SK_HASH_BITS) - 1); 578 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 579 return crc; 580 } 581 582 void 583 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 584 { 585 char *addr = addrv; 586 int base = XM_RXFILT_ENTRY(slot); 587 588 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 589 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 590 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 591 } 592 593 void 594 sk_setmulti(struct sk_if_softc *sc_if) 595 { 596 struct sk_softc *sc = sc_if->sk_softc; 597 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 598 u_int32_t hashes[2] = { 0, 0 }; 599 int h = 0, i; 600 struct ethercom *ec = &sc_if->sk_ethercom; 601 struct ether_multi *enm; 602 struct ether_multistep step; 603 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 604 605 /* First, zot all the existing filters. */ 606 switch (sc->sk_type) { 607 case SK_GENESIS: 608 for (i = 1; i < XM_RXFILT_MAX; i++) 609 sk_setfilt(sc_if, (void *)&dummy, i); 610 611 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 612 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 613 break; 614 case SK_YUKON: 615 case SK_YUKON_LITE: 616 case SK_YUKON_LP: 617 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 618 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 619 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 620 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 621 break; 622 } 623 624 /* Now program new ones. */ 625 allmulti: 626 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 627 hashes[0] = 0xFFFFFFFF; 628 hashes[1] = 0xFFFFFFFF; 629 } else { 630 i = 1; 631 /* First find the tail of the list. */ 632 ETHER_FIRST_MULTI(step, ec, enm); 633 while (enm != NULL) { 634 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 635 ETHER_ADDR_LEN)) { 636 ifp->if_flags |= IFF_ALLMULTI; 637 goto allmulti; 638 } 639 DPRINTFN(2,("multicast address %s\n", 640 ether_sprintf(enm->enm_addrlo))); 641 /* 642 * Program the first XM_RXFILT_MAX multicast groups 643 * into the perfect filter. For all others, 644 * use the hash table. 645 */ 646 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 647 sk_setfilt(sc_if, enm->enm_addrlo, i); 648 i++; 649 } 650 else { 651 switch (sc->sk_type) { 652 case SK_GENESIS: 653 h = sk_xmac_hash(enm->enm_addrlo); 654 break; 655 case SK_YUKON: 656 case SK_YUKON_LITE: 657 case SK_YUKON_LP: 658 h = sk_yukon_hash(enm->enm_addrlo); 659 break; 660 } 661 if (h < 32) 662 hashes[0] |= (1 << h); 663 else 664 hashes[1] |= (1 << (h - 32)); 665 } 666 667 ETHER_NEXT_MULTI(step, enm); 668 } 669 } 670 671 switch (sc->sk_type) { 672 case SK_GENESIS: 673 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 674 XM_MODE_RX_USE_PERFECT); 675 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 676 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 677 break; 678 case SK_YUKON: 679 case SK_YUKON_LITE: 680 case SK_YUKON_LP: 681 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 682 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 683 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 684 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 685 break; 686 } 687 } 688 689 int 690 sk_init_rx_ring(struct sk_if_softc *sc_if) 691 { 692 struct sk_chain_data *cd = &sc_if->sk_cdata; 693 struct sk_ring_data *rd = sc_if->sk_rdata; 694 int i; 695 696 bzero((char *)rd->sk_rx_ring, 697 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 698 699 for (i = 0; i < SK_RX_RING_CNT; i++) { 700 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 701 if (i == (SK_RX_RING_CNT - 1)) { 702 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 703 rd->sk_rx_ring[i].sk_next = 704 htole32(SK_RX_RING_ADDR(sc_if, 0)); 705 } else { 706 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 707 rd->sk_rx_ring[i].sk_next = 708 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 709 } 710 } 711 712 for (i = 0; i < SK_RX_RING_CNT; i++) { 713 if (sk_newbuf(sc_if, i, NULL, 714 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 715 aprint_error_dev(sc_if->sk_dev, 716 "failed alloc of %dth mbuf\n", i); 717 return ENOBUFS; 718 } 719 } 720 sc_if->sk_cdata.sk_rx_prod = 0; 721 sc_if->sk_cdata.sk_rx_cons = 0; 722 723 return 0; 724 } 725 726 int 727 sk_init_tx_ring(struct sk_if_softc *sc_if) 728 { 729 struct sk_chain_data *cd = &sc_if->sk_cdata; 730 struct sk_ring_data *rd = sc_if->sk_rdata; 731 int i; 732 733 memset(sc_if->sk_rdata->sk_tx_ring, 0, 734 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 735 736 for (i = 0; i < SK_TX_RING_CNT; i++) { 737 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 738 if (i == (SK_TX_RING_CNT - 1)) { 739 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 740 rd->sk_tx_ring[i].sk_next = 741 htole32(SK_TX_RING_ADDR(sc_if, 0)); 742 } else { 743 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 744 rd->sk_tx_ring[i].sk_next = 745 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 746 } 747 } 748 749 sc_if->sk_cdata.sk_tx_prod = 0; 750 sc_if->sk_cdata.sk_tx_cons = 0; 751 sc_if->sk_cdata.sk_tx_cnt = 0; 752 753 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 754 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 755 756 return 0; 757 } 758 759 int 760 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 761 bus_dmamap_t dmamap) 762 { 763 struct mbuf *m_new = NULL; 764 struct sk_chain *c; 765 struct sk_rx_desc *r; 766 767 if (m == NULL) { 768 void *buf = NULL; 769 770 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 771 if (m_new == NULL) { 772 aprint_error_dev(sc_if->sk_dev, 773 "no memory for rx list -- packet dropped!\n"); 774 return ENOBUFS; 775 } 776 777 /* Allocate the jumbo buffer */ 778 buf = sk_jalloc(sc_if); 779 if (buf == NULL) { 780 m_freem(m_new); 781 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 782 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 783 return ENOBUFS; 784 } 785 786 /* Attach the buffer to the mbuf */ 787 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 788 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 789 790 } else { 791 /* 792 * We're re-using a previously allocated mbuf; 793 * be sure to re-init pointers and lengths to 794 * default values. 795 */ 796 m_new = m; 797 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 798 m_new->m_data = m_new->m_ext.ext_buf; 799 } 800 m_adj(m_new, ETHER_ALIGN); 801 802 c = &sc_if->sk_cdata.sk_rx_chain[i]; 803 r = c->sk_desc; 804 c->sk_mbuf = m_new; 805 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 806 (((vaddr_t)m_new->m_data 807 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 808 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 809 810 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 811 812 return 0; 813 } 814 815 /* 816 * Memory management for jumbo frames. 817 */ 818 819 int 820 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 821 { 822 struct sk_softc *sc = sc_if->sk_softc; 823 char *ptr, *kva; 824 bus_dma_segment_t seg; 825 int i, rseg, state, error; 826 struct sk_jpool_entry *entry; 827 828 state = error = 0; 829 830 /* Grab a big chunk o' storage. */ 831 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 832 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 833 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 834 return ENOBUFS; 835 } 836 837 state = 1; 838 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 839 BUS_DMA_NOWAIT)) { 840 aprint_error_dev(sc->sk_dev, 841 "can't map dma buffers (%d bytes)\n", 842 SK_JMEM); 843 error = ENOBUFS; 844 goto out; 845 } 846 847 state = 2; 848 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 849 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 850 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 851 error = ENOBUFS; 852 goto out; 853 } 854 855 state = 3; 856 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 857 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 858 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 859 error = ENOBUFS; 860 goto out; 861 } 862 863 state = 4; 864 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 865 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 866 867 LIST_INIT(&sc_if->sk_jfree_listhead); 868 LIST_INIT(&sc_if->sk_jinuse_listhead); 869 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 870 871 /* 872 * Now divide it up into 9K pieces and save the addresses 873 * in an array. 874 */ 875 ptr = sc_if->sk_cdata.sk_jumbo_buf; 876 for (i = 0; i < SK_JSLOTS; i++) { 877 sc_if->sk_cdata.sk_jslots[i] = ptr; 878 ptr += SK_JLEN; 879 entry = malloc(sizeof(struct sk_jpool_entry), 880 M_DEVBUF, M_NOWAIT); 881 if (entry == NULL) { 882 aprint_error_dev(sc->sk_dev, 883 "no memory for jumbo buffer queue!\n"); 884 error = ENOBUFS; 885 goto out; 886 } 887 entry->slot = i; 888 if (i) 889 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 890 entry, jpool_entries); 891 else 892 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 893 entry, jpool_entries); 894 } 895 out: 896 if (error != 0) { 897 switch (state) { 898 case 4: 899 bus_dmamap_unload(sc->sc_dmatag, 900 sc_if->sk_cdata.sk_rx_jumbo_map); 901 case 3: 902 bus_dmamap_destroy(sc->sc_dmatag, 903 sc_if->sk_cdata.sk_rx_jumbo_map); 904 case 2: 905 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 906 case 1: 907 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 908 break; 909 default: 910 break; 911 } 912 } 913 914 return error; 915 } 916 917 /* 918 * Allocate a jumbo buffer. 919 */ 920 void * 921 sk_jalloc(struct sk_if_softc *sc_if) 922 { 923 struct sk_jpool_entry *entry; 924 925 mutex_enter(&sc_if->sk_jpool_mtx); 926 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 927 928 if (entry == NULL) { 929 mutex_exit(&sc_if->sk_jpool_mtx); 930 return NULL; 931 } 932 933 LIST_REMOVE(entry, jpool_entries); 934 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 935 mutex_exit(&sc_if->sk_jpool_mtx); 936 return sc_if->sk_cdata.sk_jslots[entry->slot]; 937 } 938 939 /* 940 * Release a jumbo buffer. 941 */ 942 void 943 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 944 { 945 struct sk_jpool_entry *entry; 946 struct sk_if_softc *sc; 947 int i; 948 949 /* Extract the softc struct pointer. */ 950 sc = (struct sk_if_softc *)arg; 951 952 if (sc == NULL) 953 panic("sk_jfree: can't find softc pointer!"); 954 955 /* calculate the slot this buffer belongs to */ 956 957 i = ((vaddr_t)buf 958 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 959 960 if ((i < 0) || (i >= SK_JSLOTS)) 961 panic("sk_jfree: asked to free buffer that we don't manage!"); 962 963 mutex_enter(&sc->sk_jpool_mtx); 964 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 965 if (entry == NULL) 966 panic("sk_jfree: buffer not in use!"); 967 entry->slot = i; 968 LIST_REMOVE(entry, jpool_entries); 969 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 970 mutex_exit(&sc->sk_jpool_mtx); 971 972 if (__predict_true(m != NULL)) 973 pool_cache_put(mb_cache, m); 974 } 975 976 /* 977 * Set media options. 978 */ 979 int 980 sk_ifmedia_upd(struct ifnet *ifp) 981 { 982 struct sk_if_softc *sc_if = ifp->if_softc; 983 int rc; 984 985 (void) sk_init(ifp); 986 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 987 return 0; 988 return rc; 989 } 990 991 int 992 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 993 { 994 struct sk_if_softc *sc_if = ifp->if_softc; 995 struct sk_softc *sc = sc_if->sk_softc; 996 int s, error = 0; 997 998 /* DPRINTFN(2, ("sk_ioctl\n")); */ 999 1000 s = splnet(); 1001 1002 switch (command) { 1003 1004 case SIOCSIFFLAGS: 1005 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1006 if ((error = ifioctl_common(ifp, command, data)) != 0) 1007 break; 1008 if (ifp->if_flags & IFF_UP) { 1009 if (ifp->if_flags & IFF_RUNNING && 1010 ifp->if_flags & IFF_PROMISC && 1011 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1012 switch (sc->sk_type) { 1013 case SK_GENESIS: 1014 SK_XM_SETBIT_4(sc_if, XM_MODE, 1015 XM_MODE_RX_PROMISC); 1016 break; 1017 case SK_YUKON: 1018 case SK_YUKON_LITE: 1019 case SK_YUKON_LP: 1020 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1021 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1022 break; 1023 } 1024 sk_setmulti(sc_if); 1025 } else if (ifp->if_flags & IFF_RUNNING && 1026 !(ifp->if_flags & IFF_PROMISC) && 1027 sc_if->sk_if_flags & IFF_PROMISC) { 1028 switch (sc->sk_type) { 1029 case SK_GENESIS: 1030 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1031 XM_MODE_RX_PROMISC); 1032 break; 1033 case SK_YUKON: 1034 case SK_YUKON_LITE: 1035 case SK_YUKON_LP: 1036 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1037 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1038 break; 1039 } 1040 1041 sk_setmulti(sc_if); 1042 } else 1043 (void) sk_init(ifp); 1044 } else { 1045 if (ifp->if_flags & IFF_RUNNING) 1046 sk_stop(ifp,0); 1047 } 1048 sc_if->sk_if_flags = ifp->if_flags; 1049 error = 0; 1050 break; 1051 1052 default: 1053 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1054 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1055 break; 1056 1057 error = 0; 1058 1059 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1060 ; 1061 else if (ifp->if_flags & IFF_RUNNING) { 1062 sk_setmulti(sc_if); 1063 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1064 } 1065 break; 1066 } 1067 1068 splx(s); 1069 return error; 1070 } 1071 1072 void 1073 sk_update_int_mod(struct sk_softc *sc) 1074 { 1075 u_int32_t imtimer_ticks; 1076 1077 /* 1078 * Configure interrupt moderation. The moderation timer 1079 * defers interrupts specified in the interrupt moderation 1080 * timer mask based on the timeout specified in the interrupt 1081 * moderation timer init register. Each bit in the timer 1082 * register represents one tick, so to specify a timeout in 1083 * microseconds, we have to multiply by the correct number of 1084 * ticks-per-microsecond. 1085 */ 1086 switch (sc->sk_type) { 1087 case SK_GENESIS: 1088 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1089 break; 1090 case SK_YUKON_EC: 1091 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1092 break; 1093 default: 1094 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1095 } 1096 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1097 sc->sk_int_mod); 1098 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1099 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1100 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1101 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1102 sc->sk_int_mod_pending = 0; 1103 } 1104 1105 /* 1106 * Lookup: Check the PCI vendor and device, and return a pointer to 1107 * The structure if the IDs match against our list. 1108 */ 1109 1110 static const struct sk_product * 1111 sk_lookup(const struct pci_attach_args *pa) 1112 { 1113 const struct sk_product *psk; 1114 1115 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1116 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1117 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1118 return psk; 1119 } 1120 return NULL; 1121 } 1122 1123 /* 1124 * Probe for a SysKonnect GEnesis chip. 1125 */ 1126 1127 int 1128 skc_probe(device_t parent, cfdata_t match, void *aux) 1129 { 1130 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1131 const struct sk_product *psk; 1132 pcireg_t subid; 1133 1134 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1135 1136 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1137 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1138 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1139 subid == SK_LINKSYS_EG1032_SUBID) 1140 return 1; 1141 1142 if ((psk = sk_lookup(pa))) { 1143 return 1; 1144 } 1145 return 0; 1146 } 1147 1148 /* 1149 * Force the GEnesis into reset, then bring it out of reset. 1150 */ 1151 void sk_reset(struct sk_softc *sc) 1152 { 1153 DPRINTFN(2, ("sk_reset\n")); 1154 1155 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1156 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1157 if (SK_YUKON_FAMILY(sc->sk_type)) 1158 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1159 1160 DELAY(1000); 1161 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1162 DELAY(2); 1163 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1164 if (SK_YUKON_FAMILY(sc->sk_type)) 1165 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1166 1167 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1168 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1169 CSR_READ_2(sc, SK_LINK_CTRL))); 1170 1171 if (sc->sk_type == SK_GENESIS) { 1172 /* Configure packet arbiter */ 1173 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1174 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1175 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1176 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1177 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1178 } 1179 1180 /* Enable RAM interface */ 1181 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1182 1183 sk_update_int_mod(sc); 1184 } 1185 1186 int 1187 sk_probe(device_t parent, cfdata_t match, void *aux) 1188 { 1189 struct skc_attach_args *sa = aux; 1190 1191 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1192 return 0; 1193 1194 return 1; 1195 } 1196 1197 /* 1198 * Each XMAC chip is attached as a separate logical IP interface. 1199 * Single port cards will have only one logical interface of course. 1200 */ 1201 void 1202 sk_attach(device_t parent, device_t self, void *aux) 1203 { 1204 struct sk_if_softc *sc_if = device_private(self); 1205 struct sk_softc *sc = device_private(parent); 1206 struct skc_attach_args *sa = aux; 1207 struct sk_txmap_entry *entry; 1208 struct ifnet *ifp; 1209 bus_dma_segment_t seg; 1210 bus_dmamap_t dmamap; 1211 void *kva; 1212 int i, rseg; 1213 1214 aprint_naive("\n"); 1215 1216 sc_if->sk_dev = self; 1217 sc_if->sk_port = sa->skc_port; 1218 sc_if->sk_softc = sc; 1219 sc->sk_if[sa->skc_port] = sc_if; 1220 1221 if (sa->skc_port == SK_PORT_A) 1222 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1223 if (sa->skc_port == SK_PORT_B) 1224 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1225 1226 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1227 1228 /* 1229 * Get station address for this interface. Note that 1230 * dual port cards actually come with three station 1231 * addresses: one for each port, plus an extra. The 1232 * extra one is used by the SysKonnect driver software 1233 * as a 'virtual' station address for when both ports 1234 * are operating in failover mode. Currently we don't 1235 * use this extra address. 1236 */ 1237 for (i = 0; i < ETHER_ADDR_LEN; i++) 1238 sc_if->sk_enaddr[i] = 1239 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1240 1241 1242 aprint_normal(": Ethernet address %s\n", 1243 ether_sprintf(sc_if->sk_enaddr)); 1244 1245 /* 1246 * Set up RAM buffer addresses. The NIC will have a certain 1247 * amount of SRAM on it, somewhere between 512K and 2MB. We 1248 * need to divide this up a) between the transmitter and 1249 * receiver and b) between the two XMACs, if this is a 1250 * dual port NIC. Our algorithm is to divide up the memory 1251 * evenly so that everyone gets a fair share. 1252 */ 1253 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1254 u_int32_t chunk, val; 1255 1256 chunk = sc->sk_ramsize / 2; 1257 val = sc->sk_rboff / sizeof(u_int64_t); 1258 sc_if->sk_rx_ramstart = val; 1259 val += (chunk / sizeof(u_int64_t)); 1260 sc_if->sk_rx_ramend = val - 1; 1261 sc_if->sk_tx_ramstart = val; 1262 val += (chunk / sizeof(u_int64_t)); 1263 sc_if->sk_tx_ramend = val - 1; 1264 } else { 1265 u_int32_t chunk, val; 1266 1267 chunk = sc->sk_ramsize / 4; 1268 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1269 sizeof(u_int64_t); 1270 sc_if->sk_rx_ramstart = val; 1271 val += (chunk / sizeof(u_int64_t)); 1272 sc_if->sk_rx_ramend = val - 1; 1273 sc_if->sk_tx_ramstart = val; 1274 val += (chunk / sizeof(u_int64_t)); 1275 sc_if->sk_tx_ramend = val - 1; 1276 } 1277 1278 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1279 " tx_ramstart=%#x tx_ramend=%#x\n", 1280 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1281 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1282 1283 /* Read and save PHY type and set PHY address */ 1284 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1285 switch (sc_if->sk_phytype) { 1286 case SK_PHYTYPE_XMAC: 1287 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1288 break; 1289 case SK_PHYTYPE_BCOM: 1290 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1291 break; 1292 case SK_PHYTYPE_MARV_COPPER: 1293 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1294 break; 1295 default: 1296 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1297 sc_if->sk_phytype); 1298 return; 1299 } 1300 1301 /* Allocate the descriptor queues. */ 1302 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1303 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1304 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1305 goto fail; 1306 } 1307 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1308 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1309 aprint_error_dev(sc_if->sk_dev, 1310 "can't map dma buffers (%lu bytes)\n", 1311 (u_long) sizeof(struct sk_ring_data)); 1312 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1313 goto fail; 1314 } 1315 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1316 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1317 &sc_if->sk_ring_map)) { 1318 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1319 bus_dmamem_unmap(sc->sc_dmatag, kva, 1320 sizeof(struct sk_ring_data)); 1321 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1322 goto fail; 1323 } 1324 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1325 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1326 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1327 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1328 bus_dmamem_unmap(sc->sc_dmatag, kva, 1329 sizeof(struct sk_ring_data)); 1330 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1331 goto fail; 1332 } 1333 1334 for (i = 0; i < SK_RX_RING_CNT; i++) 1335 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1336 1337 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1338 for (i = 0; i < SK_TX_RING_CNT; i++) { 1339 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1340 1341 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1342 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1343 aprint_error_dev(sc_if->sk_dev, 1344 "Can't create TX dmamap\n"); 1345 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1346 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1347 bus_dmamem_unmap(sc->sc_dmatag, kva, 1348 sizeof(struct sk_ring_data)); 1349 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1350 goto fail; 1351 } 1352 1353 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1354 if (!entry) { 1355 aprint_error_dev(sc_if->sk_dev, 1356 "Can't alloc txmap entry\n"); 1357 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1358 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1359 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1360 bus_dmamem_unmap(sc->sc_dmatag, kva, 1361 sizeof(struct sk_ring_data)); 1362 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1363 goto fail; 1364 } 1365 entry->dmamap = dmamap; 1366 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1367 } 1368 1369 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1370 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1371 1372 ifp = &sc_if->sk_ethercom.ec_if; 1373 /* Try to allocate memory for jumbo buffers. */ 1374 if (sk_alloc_jumbo_mem(sc_if)) { 1375 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1376 goto fail; 1377 } 1378 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1379 | ETHERCAP_JUMBO_MTU; 1380 1381 ifp->if_softc = sc_if; 1382 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1383 ifp->if_ioctl = sk_ioctl; 1384 ifp->if_start = sk_start; 1385 ifp->if_stop = sk_stop; 1386 ifp->if_init = sk_init; 1387 ifp->if_watchdog = sk_watchdog; 1388 ifp->if_capabilities = 0; 1389 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1390 IFQ_SET_READY(&ifp->if_snd); 1391 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1392 1393 /* 1394 * Do miibus setup. 1395 */ 1396 switch (sc->sk_type) { 1397 case SK_GENESIS: 1398 sk_init_xmac(sc_if); 1399 break; 1400 case SK_YUKON: 1401 case SK_YUKON_LITE: 1402 case SK_YUKON_LP: 1403 sk_init_yukon(sc_if); 1404 break; 1405 default: 1406 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1407 sc->sk_type); 1408 goto fail; 1409 } 1410 1411 DPRINTFN(2, ("sk_attach: 1\n")); 1412 1413 sc_if->sk_mii.mii_ifp = ifp; 1414 switch (sc->sk_type) { 1415 case SK_GENESIS: 1416 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1417 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1418 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1419 break; 1420 case SK_YUKON: 1421 case SK_YUKON_LITE: 1422 case SK_YUKON_LP: 1423 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1424 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1425 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1426 break; 1427 } 1428 1429 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1430 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1431 sk_ifmedia_upd, ether_mediastatus); 1432 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1433 MII_OFFSET_ANY, 0); 1434 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1435 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1436 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1437 0, NULL); 1438 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1439 } else 1440 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1441 1442 callout_init(&sc_if->sk_tick_ch, 0); 1443 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1444 1445 DPRINTFN(2, ("sk_attach: 1\n")); 1446 1447 /* 1448 * Call MI attach routines. 1449 */ 1450 if_attach(ifp); 1451 1452 ether_ifattach(ifp, sc_if->sk_enaddr); 1453 1454 #if NRND > 0 1455 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1456 RND_TYPE_NET, 0); 1457 #endif 1458 1459 DPRINTFN(2, ("sk_attach: end\n")); 1460 1461 return; 1462 1463 fail: 1464 sc->sk_if[sa->skc_port] = NULL; 1465 } 1466 1467 int 1468 skcprint(void *aux, const char *pnp) 1469 { 1470 struct skc_attach_args *sa = aux; 1471 1472 if (pnp) 1473 aprint_normal("sk port %c at %s", 1474 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1475 else 1476 aprint_normal(" port %c", 1477 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1478 return UNCONF; 1479 } 1480 1481 /* 1482 * Attach the interface. Allocate softc structures, do ifmedia 1483 * setup and ethernet/BPF attach. 1484 */ 1485 void 1486 skc_attach(device_t parent, device_t self, void *aux) 1487 { 1488 struct sk_softc *sc = device_private(self); 1489 struct pci_attach_args *pa = aux; 1490 struct skc_attach_args skca; 1491 pci_chipset_tag_t pc = pa->pa_pc; 1492 #ifndef SK_USEIOSPACE 1493 pcireg_t memtype; 1494 #endif 1495 pci_intr_handle_t ih; 1496 const char *intrstr = NULL; 1497 bus_addr_t iobase; 1498 bus_size_t iosize; 1499 int rc, sk_nodenum; 1500 u_int32_t command; 1501 const char *revstr; 1502 const struct sysctlnode *node; 1503 1504 sc->sk_dev = self; 1505 aprint_naive("\n"); 1506 1507 DPRINTFN(2, ("begin skc_attach\n")); 1508 1509 /* 1510 * Handle power management nonsense. 1511 */ 1512 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1513 1514 if (command == 0x01) { 1515 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1516 if (command & SK_PSTATE_MASK) { 1517 u_int32_t xiobase, membase, irq; 1518 1519 /* Save important PCI config data. */ 1520 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1521 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1522 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1523 1524 /* Reset the power state. */ 1525 aprint_normal_dev(sc->sk_dev, 1526 "chip is in D%d power mode -- setting to D0\n", 1527 command & SK_PSTATE_MASK); 1528 command &= 0xFFFFFFFC; 1529 pci_conf_write(pc, pa->pa_tag, 1530 SK_PCI_PWRMGMTCTRL, command); 1531 1532 /* Restore PCI config data. */ 1533 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1534 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1535 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1536 } 1537 } 1538 1539 /* 1540 * Map control/status registers. 1541 */ 1542 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1543 command |= PCI_COMMAND_IO_ENABLE | 1544 PCI_COMMAND_MEM_ENABLE | 1545 PCI_COMMAND_MASTER_ENABLE; 1546 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1547 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1548 1549 #ifdef SK_USEIOSPACE 1550 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1551 aprint_error(": failed to enable I/O ports!\n"); 1552 return; 1553 } 1554 /* 1555 * Map control/status registers. 1556 */ 1557 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1558 &sc->sk_btag, &sc->sk_bhandle, 1559 &iobase, &iosize)) { 1560 aprint_error(": can't find i/o space\n"); 1561 return; 1562 } 1563 #else 1564 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1565 aprint_error(": failed to enable memory mapping!\n"); 1566 return; 1567 } 1568 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1569 switch (memtype) { 1570 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1571 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1572 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1573 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1574 &iobase, &iosize) == 0) 1575 break; 1576 default: 1577 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1578 return; 1579 } 1580 1581 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1582 #endif 1583 sc->sc_dmatag = pa->pa_dmat; 1584 1585 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1586 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1587 1588 /* bail out here if chip is not recognized */ 1589 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1590 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1591 goto fail; 1592 } 1593 if (SK_IS_YUKON2(sc)) { 1594 aprint_error_dev(sc->sk_dev, 1595 "Does not support Yukon2--try msk(4).\n"); 1596 goto fail; 1597 } 1598 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1599 1600 /* Allocate interrupt */ 1601 if (pci_intr_map(pa, &ih)) { 1602 aprint_error(": couldn't map interrupt\n"); 1603 goto fail; 1604 } 1605 1606 intrstr = pci_intr_string(pc, ih); 1607 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1608 if (sc->sk_intrhand == NULL) { 1609 aprint_error(": couldn't establish interrupt"); 1610 if (intrstr != NULL) 1611 aprint_normal(" at %s", intrstr); 1612 goto fail; 1613 } 1614 aprint_normal(": %s\n", intrstr); 1615 1616 /* Reset the adapter. */ 1617 sk_reset(sc); 1618 1619 /* Read and save vital product data from EEPROM. */ 1620 sk_vpd_read(sc); 1621 1622 if (sc->sk_type == SK_GENESIS) { 1623 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1624 /* Read and save RAM size and RAMbuffer offset */ 1625 switch (val) { 1626 case SK_RAMSIZE_512K_64: 1627 sc->sk_ramsize = 0x80000; 1628 sc->sk_rboff = SK_RBOFF_0; 1629 break; 1630 case SK_RAMSIZE_1024K_64: 1631 sc->sk_ramsize = 0x100000; 1632 sc->sk_rboff = SK_RBOFF_80000; 1633 break; 1634 case SK_RAMSIZE_1024K_128: 1635 sc->sk_ramsize = 0x100000; 1636 sc->sk_rboff = SK_RBOFF_0; 1637 break; 1638 case SK_RAMSIZE_2048K_128: 1639 sc->sk_ramsize = 0x200000; 1640 sc->sk_rboff = SK_RBOFF_0; 1641 break; 1642 default: 1643 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1644 val); 1645 goto fail_1; 1646 break; 1647 } 1648 1649 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1650 sc->sk_ramsize, sc->sk_ramsize / 1024, 1651 sc->sk_rboff)); 1652 } else { 1653 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1654 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1655 sc->sk_rboff = SK_RBOFF_0; 1656 1657 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1658 sc->sk_ramsize / 1024, sc->sk_ramsize, 1659 sc->sk_rboff)); 1660 } 1661 1662 /* Read and save physical media type */ 1663 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1664 case SK_PMD_1000BASESX: 1665 sc->sk_pmd = IFM_1000_SX; 1666 break; 1667 case SK_PMD_1000BASELX: 1668 sc->sk_pmd = IFM_1000_LX; 1669 break; 1670 case SK_PMD_1000BASECX: 1671 sc->sk_pmd = IFM_1000_CX; 1672 break; 1673 case SK_PMD_1000BASETX: 1674 case SK_PMD_1000BASETX_ALT: 1675 sc->sk_pmd = IFM_1000_T; 1676 break; 1677 default: 1678 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1679 sk_win_read_1(sc, SK_PMDTYPE)); 1680 goto fail_1; 1681 } 1682 1683 /* determine whether to name it with vpd or just make it up */ 1684 /* Marvell Yukon VPD's can freqently be bogus */ 1685 1686 switch (pa->pa_id) { 1687 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1688 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1689 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1690 case PCI_PRODUCT_3COM_3C940: 1691 case PCI_PRODUCT_DLINK_DGE530T: 1692 case PCI_PRODUCT_DLINK_DGE560T: 1693 case PCI_PRODUCT_DLINK_DGE560T_2: 1694 case PCI_PRODUCT_LINKSYS_EG1032: 1695 case PCI_PRODUCT_LINKSYS_EG1064: 1696 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1697 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1698 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1699 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1700 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1701 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1702 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1703 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1704 sc->sk_name = sc->sk_vpd_prodname; 1705 break; 1706 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1707 /* whoops yukon vpd prodname bears no resemblance to reality */ 1708 switch (sc->sk_type) { 1709 case SK_GENESIS: 1710 sc->sk_name = sc->sk_vpd_prodname; 1711 break; 1712 case SK_YUKON: 1713 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1714 break; 1715 case SK_YUKON_LITE: 1716 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1717 break; 1718 case SK_YUKON_LP: 1719 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1720 break; 1721 default: 1722 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1723 } 1724 1725 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1726 1727 if ( sc->sk_type == SK_YUKON ) { 1728 uint32_t flashaddr; 1729 uint8_t testbyte; 1730 1731 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1732 1733 /* test Flash-Address Register */ 1734 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1735 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1736 1737 if (testbyte != 0) { 1738 /* this is yukon lite Rev. A0 */ 1739 sc->sk_type = SK_YUKON_LITE; 1740 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1741 /* restore Flash-Address Register */ 1742 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1743 } 1744 } 1745 break; 1746 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1747 sc->sk_name = sc->sk_vpd_prodname; 1748 break; 1749 default: 1750 sc->sk_name = "Unknown Marvell"; 1751 } 1752 1753 1754 if ( sc->sk_type == SK_YUKON_LITE ) { 1755 switch (sc->sk_rev) { 1756 case SK_YUKON_LITE_REV_A0: 1757 revstr = "A0"; 1758 break; 1759 case SK_YUKON_LITE_REV_A1: 1760 revstr = "A1"; 1761 break; 1762 case SK_YUKON_LITE_REV_A3: 1763 revstr = "A3"; 1764 break; 1765 default: 1766 revstr = ""; 1767 } 1768 } else { 1769 revstr = ""; 1770 } 1771 1772 /* Announce the product name. */ 1773 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1774 sc->sk_name, revstr, sc->sk_rev); 1775 1776 skca.skc_port = SK_PORT_A; 1777 (void)config_found(sc->sk_dev, &skca, skcprint); 1778 1779 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1780 skca.skc_port = SK_PORT_B; 1781 (void)config_found(sc->sk_dev, &skca, skcprint); 1782 } 1783 1784 /* Turn on the 'driver is loaded' LED. */ 1785 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1786 1787 /* skc sysctl setup */ 1788 1789 sc->sk_int_mod = SK_IM_DEFAULT; 1790 sc->sk_int_mod_pending = 0; 1791 1792 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1793 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1794 SYSCTL_DESCR("skc per-controller controls"), 1795 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1796 CTL_EOL)) != 0) { 1797 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1798 goto fail_1; 1799 } 1800 1801 sk_nodenum = node->sysctl_num; 1802 1803 /* interrupt moderation time in usecs */ 1804 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1805 CTLFLAG_READWRITE, 1806 CTLTYPE_INT, "int_mod", 1807 SYSCTL_DESCR("sk interrupt moderation timer"), 1808 sk_sysctl_handler, 0, sc, 1809 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1810 CTL_EOL)) != 0) { 1811 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1812 goto fail_1; 1813 } 1814 1815 return; 1816 1817 fail_1: 1818 pci_intr_disestablish(pc, sc->sk_intrhand); 1819 fail: 1820 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1821 } 1822 1823 int 1824 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1825 { 1826 struct sk_softc *sc = sc_if->sk_softc; 1827 struct sk_tx_desc *f = NULL; 1828 u_int32_t frag, cur, cnt = 0, sk_ctl; 1829 int i; 1830 struct sk_txmap_entry *entry; 1831 bus_dmamap_t txmap; 1832 1833 DPRINTFN(3, ("sk_encap\n")); 1834 1835 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1836 if (entry == NULL) { 1837 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1838 return ENOBUFS; 1839 } 1840 txmap = entry->dmamap; 1841 1842 cur = frag = *txidx; 1843 1844 #ifdef SK_DEBUG 1845 if (skdebug >= 3) 1846 sk_dump_mbuf(m_head); 1847 #endif 1848 1849 /* 1850 * Start packing the mbufs in this chain into 1851 * the fragment pointers. Stop when we run out 1852 * of fragments or hit the end of the mbuf chain. 1853 */ 1854 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1855 BUS_DMA_NOWAIT)) { 1856 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1857 return ENOBUFS; 1858 } 1859 1860 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1861 1862 /* Sync the DMA map. */ 1863 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1864 BUS_DMASYNC_PREWRITE); 1865 1866 for (i = 0; i < txmap->dm_nsegs; i++) { 1867 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1868 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1869 return ENOBUFS; 1870 } 1871 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1872 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1873 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1874 if (cnt == 0) 1875 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1876 else 1877 sk_ctl |= SK_TXCTL_OWN; 1878 f->sk_ctl = htole32(sk_ctl); 1879 cur = frag; 1880 SK_INC(frag, SK_TX_RING_CNT); 1881 cnt++; 1882 } 1883 1884 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1885 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1886 1887 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1888 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1889 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1890 1891 /* Sync descriptors before handing to chip */ 1892 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1893 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1894 1895 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1896 htole32(SK_TXCTL_OWN); 1897 1898 /* Sync first descriptor to hand it off */ 1899 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1900 1901 sc_if->sk_cdata.sk_tx_cnt += cnt; 1902 1903 #ifdef SK_DEBUG 1904 if (skdebug >= 3) { 1905 struct sk_tx_desc *desc; 1906 u_int32_t idx; 1907 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1908 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1909 sk_dump_txdesc(desc, idx); 1910 } 1911 } 1912 #endif 1913 1914 *txidx = frag; 1915 1916 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1917 1918 return 0; 1919 } 1920 1921 void 1922 sk_start(struct ifnet *ifp) 1923 { 1924 struct sk_if_softc *sc_if = ifp->if_softc; 1925 struct sk_softc *sc = sc_if->sk_softc; 1926 struct mbuf *m_head = NULL; 1927 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1928 int pkts = 0; 1929 1930 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1931 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1932 1933 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1934 IFQ_POLL(&ifp->if_snd, m_head); 1935 if (m_head == NULL) 1936 break; 1937 1938 /* 1939 * Pack the data into the transmit ring. If we 1940 * don't have room, set the OACTIVE flag and wait 1941 * for the NIC to drain the ring. 1942 */ 1943 if (sk_encap(sc_if, m_head, &idx)) { 1944 ifp->if_flags |= IFF_OACTIVE; 1945 break; 1946 } 1947 1948 /* now we are committed to transmit the packet */ 1949 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1950 pkts++; 1951 1952 /* 1953 * If there's a BPF listener, bounce a copy of this frame 1954 * to him. 1955 */ 1956 #if NBPFILTER > 0 1957 if (ifp->if_bpf) 1958 bpf_mtap(ifp->if_bpf, m_head); 1959 #endif 1960 } 1961 if (pkts == 0) 1962 return; 1963 1964 /* Transmit */ 1965 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1966 sc_if->sk_cdata.sk_tx_prod = idx; 1967 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1968 1969 /* Set a timeout in case the chip goes out to lunch. */ 1970 ifp->if_timer = 5; 1971 } 1972 } 1973 1974 1975 void 1976 sk_watchdog(struct ifnet *ifp) 1977 { 1978 struct sk_if_softc *sc_if = ifp->if_softc; 1979 1980 /* 1981 * Reclaim first as there is a possibility of losing Tx completion 1982 * interrupts. 1983 */ 1984 sk_txeof(sc_if); 1985 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1986 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1987 1988 ifp->if_oerrors++; 1989 1990 sk_init(ifp); 1991 } 1992 } 1993 1994 void 1995 sk_shutdown(void *v) 1996 { 1997 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1998 struct sk_softc *sc = sc_if->sk_softc; 1999 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2000 2001 DPRINTFN(2, ("sk_shutdown\n")); 2002 sk_stop(ifp,1); 2003 2004 /* Turn off the 'driver is loaded' LED. */ 2005 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2006 2007 /* 2008 * Reset the GEnesis controller. Doing this should also 2009 * assert the resets on the attached XMAC(s). 2010 */ 2011 sk_reset(sc); 2012 } 2013 2014 void 2015 sk_rxeof(struct sk_if_softc *sc_if) 2016 { 2017 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2018 struct mbuf *m; 2019 struct sk_chain *cur_rx; 2020 struct sk_rx_desc *cur_desc; 2021 int i, cur, total_len = 0; 2022 u_int32_t rxstat, sk_ctl; 2023 bus_dmamap_t dmamap; 2024 2025 i = sc_if->sk_cdata.sk_rx_prod; 2026 2027 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2028 2029 for (;;) { 2030 cur = i; 2031 2032 /* Sync the descriptor */ 2033 SK_CDRXSYNC(sc_if, cur, 2034 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2035 2036 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2037 if (sk_ctl & SK_RXCTL_OWN) { 2038 /* Invalidate the descriptor -- it's not ready yet */ 2039 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2040 sc_if->sk_cdata.sk_rx_prod = i; 2041 break; 2042 } 2043 2044 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2045 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2046 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2047 2048 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2049 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2050 2051 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2052 m = cur_rx->sk_mbuf; 2053 cur_rx->sk_mbuf = NULL; 2054 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2055 2056 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2057 2058 SK_INC(i, SK_RX_RING_CNT); 2059 2060 if (rxstat & XM_RXSTAT_ERRFRAME) { 2061 ifp->if_ierrors++; 2062 sk_newbuf(sc_if, cur, m, dmamap); 2063 continue; 2064 } 2065 2066 /* 2067 * Try to allocate a new jumbo buffer. If that 2068 * fails, copy the packet to mbufs and put the 2069 * jumbo buffer back in the ring so it can be 2070 * re-used. If allocating mbufs fails, then we 2071 * have to drop the packet. 2072 */ 2073 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2074 struct mbuf *m0; 2075 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2076 total_len + ETHER_ALIGN, 0, ifp, NULL); 2077 sk_newbuf(sc_if, cur, m, dmamap); 2078 if (m0 == NULL) { 2079 aprint_error_dev(sc_if->sk_dev, "no receive " 2080 "buffers available -- packet dropped!\n"); 2081 ifp->if_ierrors++; 2082 continue; 2083 } 2084 m_adj(m0, ETHER_ALIGN); 2085 m = m0; 2086 } else { 2087 m->m_pkthdr.rcvif = ifp; 2088 m->m_pkthdr.len = m->m_len = total_len; 2089 } 2090 2091 ifp->if_ipackets++; 2092 2093 #if NBPFILTER > 0 2094 if (ifp->if_bpf) 2095 bpf_mtap(ifp->if_bpf, m); 2096 #endif 2097 /* pass it on. */ 2098 (*ifp->if_input)(ifp, m); 2099 } 2100 } 2101 2102 void 2103 sk_txeof(struct sk_if_softc *sc_if) 2104 { 2105 struct sk_softc *sc = sc_if->sk_softc; 2106 struct sk_tx_desc *cur_tx; 2107 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2108 u_int32_t idx, sk_ctl; 2109 struct sk_txmap_entry *entry; 2110 2111 DPRINTFN(3, ("sk_txeof\n")); 2112 2113 /* 2114 * Go through our tx ring and free mbufs for those 2115 * frames that have been sent. 2116 */ 2117 idx = sc_if->sk_cdata.sk_tx_cons; 2118 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2119 SK_CDTXSYNC(sc_if, idx, 1, 2120 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2121 2122 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2123 sk_ctl = le32toh(cur_tx->sk_ctl); 2124 #ifdef SK_DEBUG 2125 if (skdebug >= 3) 2126 sk_dump_txdesc(cur_tx, idx); 2127 #endif 2128 if (sk_ctl & SK_TXCTL_OWN) { 2129 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2130 break; 2131 } 2132 if (sk_ctl & SK_TXCTL_LASTFRAG) 2133 ifp->if_opackets++; 2134 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2135 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2136 2137 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2138 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2139 2140 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2141 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2142 2143 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2144 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2145 link); 2146 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2147 } 2148 sc_if->sk_cdata.sk_tx_cnt--; 2149 SK_INC(idx, SK_TX_RING_CNT); 2150 } 2151 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2152 ifp->if_timer = 0; 2153 else /* nudge chip to keep tx ring moving */ 2154 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2155 2156 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2157 ifp->if_flags &= ~IFF_OACTIVE; 2158 2159 sc_if->sk_cdata.sk_tx_cons = idx; 2160 } 2161 2162 void 2163 sk_tick(void *xsc_if) 2164 { 2165 struct sk_if_softc *sc_if = xsc_if; 2166 struct mii_data *mii = &sc_if->sk_mii; 2167 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2168 int i; 2169 2170 DPRINTFN(3, ("sk_tick\n")); 2171 2172 if (!(ifp->if_flags & IFF_UP)) 2173 return; 2174 2175 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2176 sk_intr_bcom(sc_if); 2177 return; 2178 } 2179 2180 /* 2181 * According to SysKonnect, the correct way to verify that 2182 * the link has come back up is to poll bit 0 of the GPIO 2183 * register three times. This pin has the signal from the 2184 * link sync pin connected to it; if we read the same link 2185 * state 3 times in a row, we know the link is up. 2186 */ 2187 for (i = 0; i < 3; i++) { 2188 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2189 break; 2190 } 2191 2192 if (i != 3) { 2193 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2194 return; 2195 } 2196 2197 /* Turn the GP0 interrupt back on. */ 2198 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2199 SK_XM_READ_2(sc_if, XM_ISR); 2200 mii_tick(mii); 2201 mii_pollstat(mii); 2202 callout_stop(&sc_if->sk_tick_ch); 2203 } 2204 2205 void 2206 sk_intr_bcom(struct sk_if_softc *sc_if) 2207 { 2208 struct mii_data *mii = &sc_if->sk_mii; 2209 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2210 int status; 2211 2212 2213 DPRINTFN(3, ("sk_intr_bcom\n")); 2214 2215 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2216 2217 /* 2218 * Read the PHY interrupt register to make sure 2219 * we clear any pending interrupts. 2220 */ 2221 status = sk_xmac_miibus_readreg(sc_if->sk_dev, 2222 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2223 2224 if (!(ifp->if_flags & IFF_RUNNING)) { 2225 sk_init_xmac(sc_if); 2226 return; 2227 } 2228 2229 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2230 int lstat; 2231 lstat = sk_xmac_miibus_readreg(sc_if->sk_dev, 2232 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2233 2234 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2235 (void)mii_mediachg(mii); 2236 /* Turn off the link LED. */ 2237 SK_IF_WRITE_1(sc_if, 0, 2238 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2239 sc_if->sk_link = 0; 2240 } else if (status & BRGPHY_ISR_LNK_CHG) { 2241 sk_xmac_miibus_writereg(sc_if->sk_dev, 2242 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2243 mii_tick(mii); 2244 sc_if->sk_link = 1; 2245 /* Turn on the link LED. */ 2246 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2247 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2248 SK_LINKLED_BLINK_OFF); 2249 mii_pollstat(mii); 2250 } else { 2251 mii_tick(mii); 2252 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2253 } 2254 } 2255 2256 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2257 } 2258 2259 void 2260 sk_intr_xmac(struct sk_if_softc *sc_if) 2261 { 2262 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2263 2264 DPRINTFN(3, ("sk_intr_xmac\n")); 2265 2266 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2267 if (status & XM_ISR_GP0_SET) { 2268 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2269 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2270 } 2271 2272 if (status & XM_ISR_AUTONEG_DONE) { 2273 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2274 } 2275 } 2276 2277 if (status & XM_IMR_TX_UNDERRUN) 2278 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2279 2280 if (status & XM_IMR_RX_OVERRUN) 2281 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2282 } 2283 2284 void 2285 sk_intr_yukon(struct sk_if_softc *sc_if) 2286 { 2287 int status; 2288 2289 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2290 2291 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2292 } 2293 2294 int 2295 sk_intr(void *xsc) 2296 { 2297 struct sk_softc *sc = xsc; 2298 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2299 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2300 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2301 u_int32_t status; 2302 int claimed = 0; 2303 2304 if (sc_if0 != NULL) 2305 ifp0 = &sc_if0->sk_ethercom.ec_if; 2306 if (sc_if1 != NULL) 2307 ifp1 = &sc_if1->sk_ethercom.ec_if; 2308 2309 for (;;) { 2310 status = CSR_READ_4(sc, SK_ISSR); 2311 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2312 2313 if (!(status & sc->sk_intrmask)) 2314 break; 2315 2316 claimed = 1; 2317 2318 /* Handle receive interrupts first. */ 2319 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2320 sk_rxeof(sc_if0); 2321 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2322 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2323 } 2324 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2325 sk_rxeof(sc_if1); 2326 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2327 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2328 } 2329 2330 /* Then transmit interrupts. */ 2331 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2332 sk_txeof(sc_if0); 2333 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2334 SK_TXBMU_CLR_IRQ_EOF); 2335 } 2336 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2337 sk_txeof(sc_if1); 2338 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2339 SK_TXBMU_CLR_IRQ_EOF); 2340 } 2341 2342 /* Then MAC interrupts. */ 2343 if (sc_if0 && (status & SK_ISR_MAC1) && 2344 (ifp0->if_flags & IFF_RUNNING)) { 2345 if (sc->sk_type == SK_GENESIS) 2346 sk_intr_xmac(sc_if0); 2347 else 2348 sk_intr_yukon(sc_if0); 2349 } 2350 2351 if (sc_if1 && (status & SK_ISR_MAC2) && 2352 (ifp1->if_flags & IFF_RUNNING)) { 2353 if (sc->sk_type == SK_GENESIS) 2354 sk_intr_xmac(sc_if1); 2355 else 2356 sk_intr_yukon(sc_if1); 2357 2358 } 2359 2360 if (status & SK_ISR_EXTERNAL_REG) { 2361 if (sc_if0 != NULL && 2362 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2363 sk_intr_bcom(sc_if0); 2364 2365 if (sc_if1 != NULL && 2366 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2367 sk_intr_bcom(sc_if1); 2368 } 2369 } 2370 2371 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2372 2373 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2374 sk_start(ifp0); 2375 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2376 sk_start(ifp1); 2377 2378 #if NRND > 0 2379 if (RND_ENABLED(&sc->rnd_source)) 2380 rnd_add_uint32(&sc->rnd_source, status); 2381 #endif 2382 2383 if (sc->sk_int_mod_pending) 2384 sk_update_int_mod(sc); 2385 2386 return claimed; 2387 } 2388 2389 void 2390 sk_init_xmac(struct sk_if_softc *sc_if) 2391 { 2392 struct sk_softc *sc = sc_if->sk_softc; 2393 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2394 static const struct sk_bcom_hack bhack[] = { 2395 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2396 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2397 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2398 { 0, 0 } }; 2399 2400 DPRINTFN(1, ("sk_init_xmac\n")); 2401 2402 /* Unreset the XMAC. */ 2403 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2404 DELAY(1000); 2405 2406 /* Reset the XMAC's internal state. */ 2407 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2408 2409 /* Save the XMAC II revision */ 2410 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2411 2412 /* 2413 * Perform additional initialization for external PHYs, 2414 * namely for the 1000baseTX cards that use the XMAC's 2415 * GMII mode. 2416 */ 2417 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2418 int i = 0; 2419 u_int32_t val; 2420 2421 /* Take PHY out of reset. */ 2422 val = sk_win_read_4(sc, SK_GPIO); 2423 if (sc_if->sk_port == SK_PORT_A) 2424 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2425 else 2426 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2427 sk_win_write_4(sc, SK_GPIO, val); 2428 2429 /* Enable GMII mode on the XMAC. */ 2430 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2431 2432 sk_xmac_miibus_writereg(sc_if->sk_dev, 2433 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2434 DELAY(10000); 2435 sk_xmac_miibus_writereg(sc_if->sk_dev, 2436 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2437 2438 /* 2439 * Early versions of the BCM5400 apparently have 2440 * a bug that requires them to have their reserved 2441 * registers initialized to some magic values. I don't 2442 * know what the numbers do, I'm just the messenger. 2443 */ 2444 if (sk_xmac_miibus_readreg(sc_if->sk_dev, 2445 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2446 while (bhack[i].reg) { 2447 sk_xmac_miibus_writereg(sc_if->sk_dev, 2448 SK_PHYADDR_BCOM, bhack[i].reg, 2449 bhack[i].val); 2450 i++; 2451 } 2452 } 2453 } 2454 2455 /* Set station address */ 2456 SK_XM_WRITE_2(sc_if, XM_PAR0, 2457 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2458 SK_XM_WRITE_2(sc_if, XM_PAR1, 2459 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2460 SK_XM_WRITE_2(sc_if, XM_PAR2, 2461 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2462 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2463 2464 if (ifp->if_flags & IFF_PROMISC) 2465 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2466 else 2467 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2468 2469 if (ifp->if_flags & IFF_BROADCAST) 2470 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2471 else 2472 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2473 2474 /* We don't need the FCS appended to the packet. */ 2475 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2476 2477 /* We want short frames padded to 60 bytes. */ 2478 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2479 2480 /* 2481 * Enable the reception of all error frames. This is is 2482 * a necessary evil due to the design of the XMAC. The 2483 * XMAC's receive FIFO is only 8K in size, however jumbo 2484 * frames can be up to 9000 bytes in length. When bad 2485 * frame filtering is enabled, the XMAC's RX FIFO operates 2486 * in 'store and forward' mode. For this to work, the 2487 * entire frame has to fit into the FIFO, but that means 2488 * that jumbo frames larger than 8192 bytes will be 2489 * truncated. Disabling all bad frame filtering causes 2490 * the RX FIFO to operate in streaming mode, in which 2491 * case the XMAC will start transfering frames out of the 2492 * RX FIFO as soon as the FIFO threshold is reached. 2493 */ 2494 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2495 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2496 XM_MODE_RX_INRANGELEN); 2497 2498 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2499 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2500 else 2501 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2502 2503 /* 2504 * Bump up the transmit threshold. This helps hold off transmit 2505 * underruns when we're blasting traffic from both ports at once. 2506 */ 2507 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2508 2509 /* Set multicast filter */ 2510 sk_setmulti(sc_if); 2511 2512 /* Clear and enable interrupts */ 2513 SK_XM_READ_2(sc_if, XM_ISR); 2514 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2515 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2516 else 2517 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2518 2519 /* Configure MAC arbiter */ 2520 switch (sc_if->sk_xmac_rev) { 2521 case XM_XMAC_REV_B2: 2522 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2523 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2524 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2525 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2526 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2527 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2528 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2529 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2530 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2531 break; 2532 case XM_XMAC_REV_C1: 2533 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2534 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2535 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2536 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2537 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2538 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2539 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2540 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2541 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2542 break; 2543 default: 2544 break; 2545 } 2546 sk_win_write_2(sc, SK_MACARB_CTL, 2547 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2548 2549 sc_if->sk_link = 1; 2550 } 2551 2552 void sk_init_yukon(struct sk_if_softc *sc_if) 2553 { 2554 u_int32_t /*mac, */phy; 2555 u_int16_t reg; 2556 struct sk_softc *sc; 2557 int i; 2558 2559 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2560 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2561 2562 sc = sc_if->sk_softc; 2563 if (sc->sk_type == SK_YUKON_LITE && 2564 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2565 /* Take PHY out of reset. */ 2566 sk_win_write_4(sc, SK_GPIO, 2567 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2568 } 2569 2570 2571 /* GMAC and GPHY Reset */ 2572 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2573 2574 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2575 2576 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2577 DELAY(1000); 2578 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2579 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2580 DELAY(1000); 2581 2582 2583 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2584 2585 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2586 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2587 2588 switch (sc_if->sk_softc->sk_pmd) { 2589 case IFM_1000_SX: 2590 case IFM_1000_LX: 2591 phy |= SK_GPHY_FIBER; 2592 break; 2593 2594 case IFM_1000_CX: 2595 case IFM_1000_T: 2596 phy |= SK_GPHY_COPPER; 2597 break; 2598 } 2599 2600 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2601 2602 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2603 DELAY(1000); 2604 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2605 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2606 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2607 2608 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2609 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2610 2611 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2612 2613 /* unused read of the interrupt source register */ 2614 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2615 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2616 2617 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2618 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2619 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2620 2621 /* MIB Counter Clear Mode set */ 2622 reg |= YU_PAR_MIB_CLR; 2623 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2624 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2625 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2626 2627 /* MIB Counter Clear Mode clear */ 2628 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2629 reg &= ~YU_PAR_MIB_CLR; 2630 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2631 2632 /* receive control reg */ 2633 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2634 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2635 YU_RCR_CRCR); 2636 2637 /* transmit parameter register */ 2638 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2639 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2640 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2641 2642 /* serial mode register */ 2643 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2644 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2645 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2646 YU_SMR_IPG_DATA(0x1e)); 2647 2648 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2649 /* Setup Yukon's address */ 2650 for (i = 0; i < 3; i++) { 2651 /* Write Source Address 1 (unicast filter) */ 2652 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2653 sc_if->sk_enaddr[i * 2] | 2654 sc_if->sk_enaddr[i * 2 + 1] << 8); 2655 } 2656 2657 for (i = 0; i < 3; i++) { 2658 reg = sk_win_read_2(sc_if->sk_softc, 2659 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2660 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2661 } 2662 2663 /* Set multicast filter */ 2664 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2665 sk_setmulti(sc_if); 2666 2667 /* enable interrupt mask for counter overflows */ 2668 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2669 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2670 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2671 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2672 2673 /* Configure RX MAC FIFO */ 2674 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2675 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2676 2677 /* Configure TX MAC FIFO */ 2678 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2679 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2680 2681 DPRINTFN(6, ("sk_init_yukon: end\n")); 2682 } 2683 2684 /* 2685 * Note that to properly initialize any part of the GEnesis chip, 2686 * you first have to take it out of reset mode. 2687 */ 2688 int 2689 sk_init(struct ifnet *ifp) 2690 { 2691 struct sk_if_softc *sc_if = ifp->if_softc; 2692 struct sk_softc *sc = sc_if->sk_softc; 2693 struct mii_data *mii = &sc_if->sk_mii; 2694 int rc = 0, s; 2695 u_int32_t imr, imtimer_ticks; 2696 2697 DPRINTFN(1, ("sk_init\n")); 2698 2699 s = splnet(); 2700 2701 if (ifp->if_flags & IFF_RUNNING) { 2702 splx(s); 2703 return 0; 2704 } 2705 2706 /* Cancel pending I/O and free all RX/TX buffers. */ 2707 sk_stop(ifp,0); 2708 2709 if (sc->sk_type == SK_GENESIS) { 2710 /* Configure LINK_SYNC LED */ 2711 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2712 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2713 SK_LINKLED_LINKSYNC_ON); 2714 2715 /* Configure RX LED */ 2716 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2717 SK_RXLEDCTL_COUNTER_START); 2718 2719 /* Configure TX LED */ 2720 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2721 SK_TXLEDCTL_COUNTER_START); 2722 } 2723 2724 /* Configure I2C registers */ 2725 2726 /* Configure XMAC(s) */ 2727 switch (sc->sk_type) { 2728 case SK_GENESIS: 2729 sk_init_xmac(sc_if); 2730 break; 2731 case SK_YUKON: 2732 case SK_YUKON_LITE: 2733 case SK_YUKON_LP: 2734 sk_init_yukon(sc_if); 2735 break; 2736 } 2737 if ((rc = mii_mediachg(mii)) == ENXIO) 2738 rc = 0; 2739 else if (rc != 0) 2740 goto out; 2741 2742 if (sc->sk_type == SK_GENESIS) { 2743 /* Configure MAC FIFOs */ 2744 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2745 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2746 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2747 2748 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2749 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2750 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2751 } 2752 2753 /* Configure transmit arbiter(s) */ 2754 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2755 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2756 2757 /* Configure RAMbuffers */ 2758 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2759 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2760 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2761 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2762 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2763 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2764 2765 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2766 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2767 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2768 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2769 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2770 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2771 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2772 2773 /* Configure BMUs */ 2774 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2775 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2776 SK_RX_RING_ADDR(sc_if, 0)); 2777 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2778 2779 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2780 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2781 SK_TX_RING_ADDR(sc_if, 0)); 2782 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2783 2784 /* Init descriptors */ 2785 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2786 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2787 "memory for rx buffers\n"); 2788 sk_stop(ifp,0); 2789 splx(s); 2790 return ENOBUFS; 2791 } 2792 2793 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2794 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2795 "memory for tx buffers\n"); 2796 sk_stop(ifp,0); 2797 splx(s); 2798 return ENOBUFS; 2799 } 2800 2801 /* Set interrupt moderation if changed via sysctl. */ 2802 switch (sc->sk_type) { 2803 case SK_GENESIS: 2804 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2805 break; 2806 case SK_YUKON_EC: 2807 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2808 break; 2809 default: 2810 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2811 } 2812 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2813 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2814 sk_win_write_4(sc, SK_IMTIMERINIT, 2815 SK_IM_USECS(sc->sk_int_mod)); 2816 aprint_verbose_dev(sc->sk_dev, 2817 "interrupt moderation is %d us\n", sc->sk_int_mod); 2818 } 2819 2820 /* Configure interrupt handling */ 2821 CSR_READ_4(sc, SK_ISSR); 2822 if (sc_if->sk_port == SK_PORT_A) 2823 sc->sk_intrmask |= SK_INTRS1; 2824 else 2825 sc->sk_intrmask |= SK_INTRS2; 2826 2827 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2828 2829 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2830 2831 /* Start BMUs. */ 2832 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2833 2834 if (sc->sk_type == SK_GENESIS) { 2835 /* Enable XMACs TX and RX state machines */ 2836 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2837 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2838 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2839 } 2840 2841 if (SK_YUKON_FAMILY(sc->sk_type)) { 2842 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2843 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2844 #if 0 2845 /* XXX disable 100Mbps and full duplex mode? */ 2846 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2847 #endif 2848 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2849 } 2850 2851 2852 ifp->if_flags |= IFF_RUNNING; 2853 ifp->if_flags &= ~IFF_OACTIVE; 2854 2855 out: 2856 splx(s); 2857 return rc; 2858 } 2859 2860 void 2861 sk_stop(struct ifnet *ifp, int disable) 2862 { 2863 struct sk_if_softc *sc_if = ifp->if_softc; 2864 struct sk_softc *sc = sc_if->sk_softc; 2865 int i; 2866 2867 DPRINTFN(1, ("sk_stop\n")); 2868 2869 callout_stop(&sc_if->sk_tick_ch); 2870 2871 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2872 u_int32_t val; 2873 2874 /* Put PHY back into reset. */ 2875 val = sk_win_read_4(sc, SK_GPIO); 2876 if (sc_if->sk_port == SK_PORT_A) { 2877 val |= SK_GPIO_DIR0; 2878 val &= ~SK_GPIO_DAT0; 2879 } else { 2880 val |= SK_GPIO_DIR2; 2881 val &= ~SK_GPIO_DAT2; 2882 } 2883 sk_win_write_4(sc, SK_GPIO, val); 2884 } 2885 2886 /* Turn off various components of this interface. */ 2887 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2888 switch (sc->sk_type) { 2889 case SK_GENESIS: 2890 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2891 SK_TXMACCTL_XMAC_RESET); 2892 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2893 break; 2894 case SK_YUKON: 2895 case SK_YUKON_LITE: 2896 case SK_YUKON_LP: 2897 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2898 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2899 break; 2900 } 2901 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2902 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2903 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2904 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2905 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2906 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2907 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2908 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2909 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2910 2911 /* Disable interrupts */ 2912 if (sc_if->sk_port == SK_PORT_A) 2913 sc->sk_intrmask &= ~SK_INTRS1; 2914 else 2915 sc->sk_intrmask &= ~SK_INTRS2; 2916 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2917 2918 SK_XM_READ_2(sc_if, XM_ISR); 2919 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2920 2921 /* Free RX and TX mbufs still in the queues. */ 2922 for (i = 0; i < SK_RX_RING_CNT; i++) { 2923 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2924 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2925 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2926 } 2927 } 2928 2929 for (i = 0; i < SK_TX_RING_CNT; i++) { 2930 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2931 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2932 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2933 } 2934 } 2935 2936 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2937 } 2938 2939 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 2940 skc_probe, skc_attach, NULL, NULL); 2941 2942 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 2943 sk_probe, sk_attach, NULL, NULL); 2944 2945 #ifdef SK_DEBUG 2946 void 2947 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2948 { 2949 #define DESC_PRINT(X) \ 2950 if (X) \ 2951 printf("txdesc[%d]." #X "=%#x\n", \ 2952 idx, X); 2953 2954 DESC_PRINT(le32toh(desc->sk_ctl)); 2955 DESC_PRINT(le32toh(desc->sk_next)); 2956 DESC_PRINT(le32toh(desc->sk_data_lo)); 2957 DESC_PRINT(le32toh(desc->sk_data_hi)); 2958 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2959 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2960 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2961 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2962 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2963 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2964 #undef PRINT 2965 } 2966 2967 void 2968 sk_dump_bytes(const char *data, int len) 2969 { 2970 int c, i, j; 2971 2972 for (i = 0; i < len; i += 16) { 2973 printf("%08x ", i); 2974 c = len - i; 2975 if (c > 16) c = 16; 2976 2977 for (j = 0; j < c; j++) { 2978 printf("%02x ", data[i + j] & 0xff); 2979 if ((j & 0xf) == 7 && j > 0) 2980 printf(" "); 2981 } 2982 2983 for (; j < 16; j++) 2984 printf(" "); 2985 printf(" "); 2986 2987 for (j = 0; j < c; j++) { 2988 int ch = data[i + j] & 0xff; 2989 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2990 } 2991 2992 printf("\n"); 2993 2994 if (c < 16) 2995 break; 2996 } 2997 } 2998 2999 void 3000 sk_dump_mbuf(struct mbuf *m) 3001 { 3002 int count = m->m_pkthdr.len; 3003 3004 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3005 3006 while (count > 0 && m) { 3007 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3008 m, m->m_data, m->m_len); 3009 sk_dump_bytes(mtod(m, char *), m->m_len); 3010 3011 count -= m->m_len; 3012 m = m->m_next; 3013 } 3014 } 3015 #endif 3016 3017 static int 3018 sk_sysctl_handler(SYSCTLFN_ARGS) 3019 { 3020 int error, t; 3021 struct sysctlnode node; 3022 struct sk_softc *sc; 3023 3024 node = *rnode; 3025 sc = node.sysctl_data; 3026 t = sc->sk_int_mod; 3027 node.sysctl_data = &t; 3028 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3029 if (error || newp == NULL) 3030 return error; 3031 3032 if (t < SK_IM_MIN || t > SK_IM_MAX) 3033 return EINVAL; 3034 3035 /* update the softc with sysctl-changed value, and mark 3036 for hardware update */ 3037 sc->sk_int_mod = t; 3038 sc->sk_int_mod_pending = 1; 3039 return 0; 3040 } 3041 3042 /* 3043 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3044 * set up in skc_attach() 3045 */ 3046 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3047 { 3048 int rc; 3049 const struct sysctlnode *node; 3050 3051 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3052 0, CTLTYPE_NODE, "hw", NULL, 3053 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3054 goto err; 3055 } 3056 3057 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3058 0, CTLTYPE_NODE, "sk", 3059 SYSCTL_DESCR("sk interface controls"), 3060 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3061 goto err; 3062 } 3063 3064 sk_root_num = node->sysctl_num; 3065 return; 3066 3067 err: 3068 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3069 } 3070
Indexes created Tue Sep 23 07:09:52 GMT 2025