if_sk.c revision 1.56
1 /* $NetBSD: if_sk.c,v 1.56 2009/02/12 10:22:30 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.56 2009/02/12 10:22:30 cegger Exp $"); 119 120 #include "bpfilter.h" 121 #include "rnd.h" 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/sockio.h> 126 #include <sys/mbuf.h> 127 #include <sys/malloc.h> 128 #include <sys/mutex.h> 129 #include <sys/kernel.h> 130 #include <sys/socket.h> 131 #include <sys/device.h> 132 #include <sys/queue.h> 133 #include <sys/callout.h> 134 #include <sys/sysctl.h> 135 #include <sys/endian.h> 136 137 #include <net/if.h> 138 #include <net/if_dl.h> 139 #include <net/if_types.h> 140 141 #include <net/if_media.h> 142 143 #if NBPFILTER > 0 144 #include <net/bpf.h> 145 #endif 146 #if NRND > 0 147 #include <sys/rnd.h> 148 #endif 149 150 #include <dev/mii/mii.h> 151 #include <dev/mii/miivar.h> 152 #include <dev/mii/brgphyreg.h> 153 154 #include <dev/pci/pcireg.h> 155 #include <dev/pci/pcivar.h> 156 #include <dev/pci/pcidevs.h> 157 158 /* #define SK_USEIOSPACE */ 159 160 #include <dev/pci/if_skreg.h> 161 #include <dev/pci/if_skvar.h> 162 163 int skc_probe(device_t, cfdata_t, void *); 164 void skc_attach(device_t, device_t, void *aux); 165 int sk_probe(device_t, cfdata_t, void *); 166 void sk_attach(device_t, device_t, void *aux); 167 int skcprint(void *, const char *); 168 int sk_intr(void *); 169 void sk_intr_bcom(struct sk_if_softc *); 170 void sk_intr_xmac(struct sk_if_softc *); 171 void sk_intr_yukon(struct sk_if_softc *); 172 void sk_rxeof(struct sk_if_softc *); 173 void sk_txeof(struct sk_if_softc *); 174 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 175 void sk_start(struct ifnet *); 176 int sk_ioctl(struct ifnet *, u_long, void *); 177 int sk_init(struct ifnet *); 178 void sk_init_xmac(struct sk_if_softc *); 179 void sk_init_yukon(struct sk_if_softc *); 180 void sk_stop(struct ifnet *, int); 181 void sk_watchdog(struct ifnet *); 182 void sk_shutdown(void *); 183 int sk_ifmedia_upd(struct ifnet *); 184 void sk_reset(struct sk_softc *); 185 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 186 int sk_alloc_jumbo_mem(struct sk_if_softc *); 187 void sk_free_jumbo_mem(struct sk_if_softc *); 188 void *sk_jalloc(struct sk_if_softc *); 189 void sk_jfree(struct mbuf *, void *, size_t, void *); 190 int sk_init_rx_ring(struct sk_if_softc *); 191 int sk_init_tx_ring(struct sk_if_softc *); 192 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 193 void sk_vpd_read_res(struct sk_softc *, 194 struct vpd_res *, int); 195 void sk_vpd_read(struct sk_softc *); 196 197 void sk_update_int_mod(struct sk_softc *); 198 199 int sk_xmac_miibus_readreg(device_t, int, int); 200 void sk_xmac_miibus_writereg(device_t, int, int, int); 201 void sk_xmac_miibus_statchg(device_t); 202 203 int sk_marv_miibus_readreg(device_t, int, int); 204 void sk_marv_miibus_writereg(device_t, int, int, int); 205 void sk_marv_miibus_statchg(device_t); 206 207 u_int32_t sk_xmac_hash(void *); 208 u_int32_t sk_yukon_hash(void *); 209 void sk_setfilt(struct sk_if_softc *, void *, int); 210 void sk_setmulti(struct sk_if_softc *); 211 void sk_tick(void *); 212 213 /* #define SK_DEBUG 2 */ 214 #ifdef SK_DEBUG 215 #define DPRINTF(x) if (skdebug) printf x 216 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 217 int skdebug = SK_DEBUG; 218 219 void sk_dump_txdesc(struct sk_tx_desc *, int); 220 void sk_dump_mbuf(struct mbuf *); 221 void sk_dump_bytes(const char *, int); 222 #else 223 #define DPRINTF(x) 224 #define DPRINTFN(n,x) 225 #endif 226 227 static int sk_sysctl_handler(SYSCTLFN_PROTO); 228 static int sk_root_num; 229 230 /* supported device vendors */ 231 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 232 static const struct sk_product { 233 pci_vendor_id_t sk_vendor; 234 pci_product_id_t sk_product; 235 } sk_products[] = { 236 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 237 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 238 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 239 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 240 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 241 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 242 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 243 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 244 { 0, 0, } 245 }; 246 247 #define SK_LINKSYS_EG1032_SUBID 0x00151737 248 249 static inline u_int32_t 250 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 251 { 252 #ifdef SK_USEIOSPACE 253 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 254 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 255 #else 256 return CSR_READ_4(sc, reg); 257 #endif 258 } 259 260 static inline u_int16_t 261 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 262 { 263 #ifdef SK_USEIOSPACE 264 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 265 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 266 #else 267 return CSR_READ_2(sc, reg); 268 #endif 269 } 270 271 static inline u_int8_t 272 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 273 { 274 #ifdef SK_USEIOSPACE 275 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 276 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 277 #else 278 return CSR_READ_1(sc, reg); 279 #endif 280 } 281 282 static inline void 283 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 284 { 285 #ifdef SK_USEIOSPACE 286 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 287 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 288 #else 289 CSR_WRITE_4(sc, reg, x); 290 #endif 291 } 292 293 static inline void 294 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 295 { 296 #ifdef SK_USEIOSPACE 297 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 298 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 299 #else 300 CSR_WRITE_2(sc, reg, x); 301 #endif 302 } 303 304 static inline void 305 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 306 { 307 #ifdef SK_USEIOSPACE 308 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 309 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 310 #else 311 CSR_WRITE_1(sc, reg, x); 312 #endif 313 } 314 315 /* 316 * The VPD EEPROM contains Vital Product Data, as suggested in 317 * the PCI 2.1 specification. The VPD data is separared into areas 318 * denoted by resource IDs. The SysKonnect VPD contains an ID string 319 * resource (the name of the adapter), a read-only area resource 320 * containing various key/data fields and a read/write area which 321 * can be used to store asset management information or log messages. 322 * We read the ID string and read-only into buffers attached to 323 * the controller softc structure for later use. At the moment, 324 * we only use the ID string during sk_attach(). 325 */ 326 u_int8_t 327 sk_vpd_readbyte(struct sk_softc *sc, int addr) 328 { 329 int i; 330 331 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 332 for (i = 0; i < SK_TIMEOUT; i++) { 333 DELAY(1); 334 if (sk_win_read_2(sc, 335 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 336 break; 337 } 338 339 if (i == SK_TIMEOUT) 340 return 0; 341 342 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 343 } 344 345 void 346 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 347 { 348 int i; 349 u_int8_t *ptr; 350 351 ptr = (u_int8_t *)res; 352 for (i = 0; i < sizeof(struct vpd_res); i++) 353 ptr[i] = sk_vpd_readbyte(sc, i + addr); 354 } 355 356 void 357 sk_vpd_read(struct sk_softc *sc) 358 { 359 int pos = 0, i; 360 struct vpd_res res; 361 362 if (sc->sk_vpd_prodname != NULL) 363 free(sc->sk_vpd_prodname, M_DEVBUF); 364 if (sc->sk_vpd_readonly != NULL) 365 free(sc->sk_vpd_readonly, M_DEVBUF); 366 sc->sk_vpd_prodname = NULL; 367 sc->sk_vpd_readonly = NULL; 368 369 sk_vpd_read_res(sc, &res, pos); 370 371 if (res.vr_id != VPD_RES_ID) { 372 aprint_error_dev(sc->sk_dev, 373 "bad VPD resource id: expected %x got %x\n", 374 VPD_RES_ID, res.vr_id); 375 return; 376 } 377 378 pos += sizeof(res); 379 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 380 if (sc->sk_vpd_prodname == NULL) 381 panic("sk_vpd_read"); 382 for (i = 0; i < res.vr_len; i++) 383 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 384 sc->sk_vpd_prodname[i] = '\0'; 385 pos += i; 386 387 sk_vpd_read_res(sc, &res, pos); 388 389 if (res.vr_id != VPD_RES_READ) { 390 aprint_error_dev(sc->sk_dev, 391 "bad VPD resource id: expected %x got %x\n", 392 VPD_RES_READ, res.vr_id); 393 return; 394 } 395 396 pos += sizeof(res); 397 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 398 if (sc->sk_vpd_readonly == NULL) 399 panic("sk_vpd_read"); 400 for (i = 0; i < res.vr_len ; i++) 401 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 402 } 403 404 int 405 sk_xmac_miibus_readreg(device_t dev, int phy, int reg) 406 { 407 struct sk_if_softc *sc_if = device_private(dev); 408 int i; 409 410 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 411 412 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 413 return 0; 414 415 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 416 SK_XM_READ_2(sc_if, XM_PHY_DATA); 417 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 418 for (i = 0; i < SK_TIMEOUT; i++) { 419 DELAY(1); 420 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 421 XM_MMUCMD_PHYDATARDY) 422 break; 423 } 424 425 if (i == SK_TIMEOUT) { 426 aprint_error_dev(sc_if->sk_dev, 427 "phy failed to come ready\n"); 428 return 0; 429 } 430 } 431 DELAY(1); 432 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 433 } 434 435 void 436 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, int val) 437 { 438 struct sk_if_softc *sc_if = device_private(dev); 439 int i; 440 441 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 442 443 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 444 for (i = 0; i < SK_TIMEOUT; i++) { 445 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 446 break; 447 } 448 449 if (i == SK_TIMEOUT) { 450 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 451 return; 452 } 453 454 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 455 for (i = 0; i < SK_TIMEOUT; i++) { 456 DELAY(1); 457 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 458 break; 459 } 460 461 if (i == SK_TIMEOUT) 462 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 463 } 464 465 void 466 sk_xmac_miibus_statchg(device_t dev) 467 { 468 struct sk_if_softc *sc_if = device_private(dev); 469 struct mii_data *mii = &sc_if->sk_mii; 470 471 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 472 473 /* 474 * If this is a GMII PHY, manually set the XMAC's 475 * duplex mode accordingly. 476 */ 477 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 478 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 479 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 480 else 481 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 482 } 483 } 484 485 int 486 sk_marv_miibus_readreg(device_t dev, int phy, int reg) 487 { 488 struct sk_if_softc *sc_if = device_private(dev); 489 u_int16_t val; 490 int i; 491 492 if (phy != 0 || 493 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 494 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 495 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 496 phy, reg)); 497 return 0; 498 } 499 500 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 501 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 502 503 for (i = 0; i < SK_TIMEOUT; i++) { 504 DELAY(1); 505 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 506 if (val & YU_SMICR_READ_VALID) 507 break; 508 } 509 510 if (i == SK_TIMEOUT) { 511 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 512 return 0; 513 } 514 515 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 516 SK_TIMEOUT)); 517 518 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 519 520 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 521 phy, reg, val)); 522 523 return val; 524 } 525 526 void 527 sk_marv_miibus_writereg(device_t dev, int phy, int reg, int val) 528 { 529 struct sk_if_softc *sc_if = device_private(dev); 530 int i; 531 532 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 533 phy, reg, val)); 534 535 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 536 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 537 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 538 539 for (i = 0; i < SK_TIMEOUT; i++) { 540 DELAY(1); 541 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 542 break; 543 } 544 545 if (i == SK_TIMEOUT) 546 printf("%s: phy write timed out\n", 547 device_xname(sc_if->sk_dev)); 548 } 549 550 void 551 sk_marv_miibus_statchg(device_t dev) 552 { 553 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 554 SK_YU_READ_2(((struct sk_if_softc *)device_private(dev)), 555 YUKON_GPCR))); 556 } 557 558 #define SK_HASH_BITS 6 559 560 u_int32_t 561 sk_xmac_hash(void *addr) 562 { 563 u_int32_t crc; 564 565 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 566 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 567 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 568 return crc; 569 } 570 571 u_int32_t 572 sk_yukon_hash(void *addr) 573 { 574 u_int32_t crc; 575 576 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 577 crc &= ((1 << SK_HASH_BITS) - 1); 578 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 579 return crc; 580 } 581 582 void 583 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 584 { 585 char *addr = addrv; 586 int base = XM_RXFILT_ENTRY(slot); 587 588 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 589 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 590 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 591 } 592 593 void 594 sk_setmulti(struct sk_if_softc *sc_if) 595 { 596 struct sk_softc *sc = sc_if->sk_softc; 597 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 598 u_int32_t hashes[2] = { 0, 0 }; 599 int h = 0, i; 600 struct ethercom *ec = &sc_if->sk_ethercom; 601 struct ether_multi *enm; 602 struct ether_multistep step; 603 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 604 605 /* First, zot all the existing filters. */ 606 switch (sc->sk_type) { 607 case SK_GENESIS: 608 for (i = 1; i < XM_RXFILT_MAX; i++) 609 sk_setfilt(sc_if, (void *)&dummy, i); 610 611 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 612 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 613 break; 614 case SK_YUKON: 615 case SK_YUKON_LITE: 616 case SK_YUKON_LP: 617 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 618 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 619 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 620 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 621 break; 622 } 623 624 /* Now program new ones. */ 625 allmulti: 626 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 627 hashes[0] = 0xFFFFFFFF; 628 hashes[1] = 0xFFFFFFFF; 629 } else { 630 i = 1; 631 /* First find the tail of the list. */ 632 ETHER_FIRST_MULTI(step, ec, enm); 633 while (enm != NULL) { 634 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 635 ETHER_ADDR_LEN)) { 636 ifp->if_flags |= IFF_ALLMULTI; 637 goto allmulti; 638 } 639 DPRINTFN(2,("multicast address %s\n", 640 ether_sprintf(enm->enm_addrlo))); 641 /* 642 * Program the first XM_RXFILT_MAX multicast groups 643 * into the perfect filter. For all others, 644 * use the hash table. 645 */ 646 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 647 sk_setfilt(sc_if, enm->enm_addrlo, i); 648 i++; 649 } 650 else { 651 switch (sc->sk_type) { 652 case SK_GENESIS: 653 h = sk_xmac_hash(enm->enm_addrlo); 654 break; 655 case SK_YUKON: 656 case SK_YUKON_LITE: 657 case SK_YUKON_LP: 658 h = sk_yukon_hash(enm->enm_addrlo); 659 break; 660 } 661 if (h < 32) 662 hashes[0] |= (1 << h); 663 else 664 hashes[1] |= (1 << (h - 32)); 665 } 666 667 ETHER_NEXT_MULTI(step, enm); 668 } 669 } 670 671 switch (sc->sk_type) { 672 case SK_GENESIS: 673 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 674 XM_MODE_RX_USE_PERFECT); 675 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 676 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 677 break; 678 case SK_YUKON: 679 case SK_YUKON_LITE: 680 case SK_YUKON_LP: 681 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 682 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 683 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 684 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 685 break; 686 } 687 } 688 689 int 690 sk_init_rx_ring(struct sk_if_softc *sc_if) 691 { 692 struct sk_chain_data *cd = &sc_if->sk_cdata; 693 struct sk_ring_data *rd = sc_if->sk_rdata; 694 int i; 695 696 bzero((char *)rd->sk_rx_ring, 697 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 698 699 for (i = 0; i < SK_RX_RING_CNT; i++) { 700 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 701 if (i == (SK_RX_RING_CNT - 1)) { 702 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 703 rd->sk_rx_ring[i].sk_next = 704 htole32(SK_RX_RING_ADDR(sc_if, 0)); 705 } else { 706 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 707 rd->sk_rx_ring[i].sk_next = 708 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 709 } 710 } 711 712 for (i = 0; i < SK_RX_RING_CNT; i++) { 713 if (sk_newbuf(sc_if, i, NULL, 714 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 715 aprint_error_dev(sc_if->sk_dev, 716 "failed alloc of %dth mbuf\n", i); 717 return ENOBUFS; 718 } 719 } 720 sc_if->sk_cdata.sk_rx_prod = 0; 721 sc_if->sk_cdata.sk_rx_cons = 0; 722 723 return 0; 724 } 725 726 int 727 sk_init_tx_ring(struct sk_if_softc *sc_if) 728 { 729 struct sk_chain_data *cd = &sc_if->sk_cdata; 730 struct sk_ring_data *rd = sc_if->sk_rdata; 731 int i; 732 733 memset(sc_if->sk_rdata->sk_tx_ring, 0, 734 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 735 736 for (i = 0; i < SK_TX_RING_CNT; i++) { 737 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 738 if (i == (SK_TX_RING_CNT - 1)) { 739 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 740 rd->sk_tx_ring[i].sk_next = 741 htole32(SK_TX_RING_ADDR(sc_if, 0)); 742 } else { 743 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 744 rd->sk_tx_ring[i].sk_next = 745 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 746 } 747 } 748 749 sc_if->sk_cdata.sk_tx_prod = 0; 750 sc_if->sk_cdata.sk_tx_cons = 0; 751 sc_if->sk_cdata.sk_tx_cnt = 0; 752 753 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 754 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 755 756 return 0; 757 } 758 759 int 760 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 761 bus_dmamap_t dmamap) 762 { 763 struct mbuf *m_new = NULL; 764 struct sk_chain *c; 765 struct sk_rx_desc *r; 766 767 if (m == NULL) { 768 void *buf = NULL; 769 770 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 771 if (m_new == NULL) { 772 aprint_error_dev(sc_if->sk_dev, 773 "no memory for rx list -- packet dropped!\n"); 774 return ENOBUFS; 775 } 776 777 /* Allocate the jumbo buffer */ 778 buf = sk_jalloc(sc_if); 779 if (buf == NULL) { 780 m_freem(m_new); 781 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 782 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 783 return ENOBUFS; 784 } 785 786 /* Attach the buffer to the mbuf */ 787 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 788 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 789 790 } else { 791 /* 792 * We're re-using a previously allocated mbuf; 793 * be sure to re-init pointers and lengths to 794 * default values. 795 */ 796 m_new = m; 797 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 798 m_new->m_data = m_new->m_ext.ext_buf; 799 } 800 m_adj(m_new, ETHER_ALIGN); 801 802 c = &sc_if->sk_cdata.sk_rx_chain[i]; 803 r = c->sk_desc; 804 c->sk_mbuf = m_new; 805 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 806 (((vaddr_t)m_new->m_data 807 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 808 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 809 810 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 811 812 return 0; 813 } 814 815 /* 816 * Memory management for jumbo frames. 817 */ 818 819 int 820 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 821 { 822 struct sk_softc *sc = sc_if->sk_softc; 823 char *ptr, *kva; 824 bus_dma_segment_t seg; 825 int i, rseg, state, error; 826 struct sk_jpool_entry *entry; 827 828 state = error = 0; 829 830 /* Grab a big chunk o' storage. */ 831 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 832 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 833 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 834 return ENOBUFS; 835 } 836 837 state = 1; 838 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 839 BUS_DMA_NOWAIT)) { 840 aprint_error_dev(sc->sk_dev, 841 "can't map dma buffers (%d bytes)\n", 842 SK_JMEM); 843 error = ENOBUFS; 844 goto out; 845 } 846 847 state = 2; 848 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 849 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 850 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 851 error = ENOBUFS; 852 goto out; 853 } 854 855 state = 3; 856 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 857 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 858 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 859 error = ENOBUFS; 860 goto out; 861 } 862 863 state = 4; 864 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 865 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 866 867 LIST_INIT(&sc_if->sk_jfree_listhead); 868 LIST_INIT(&sc_if->sk_jinuse_listhead); 869 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 870 871 /* 872 * Now divide it up into 9K pieces and save the addresses 873 * in an array. 874 */ 875 ptr = sc_if->sk_cdata.sk_jumbo_buf; 876 for (i = 0; i < SK_JSLOTS; i++) { 877 sc_if->sk_cdata.sk_jslots[i] = ptr; 878 ptr += SK_JLEN; 879 entry = malloc(sizeof(struct sk_jpool_entry), 880 M_DEVBUF, M_NOWAIT); 881 if (entry == NULL) { 882 aprint_error_dev(sc->sk_dev, 883 "no memory for jumbo buffer queue!\n"); 884 error = ENOBUFS; 885 goto out; 886 } 887 entry->slot = i; 888 if (i) 889 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 890 entry, jpool_entries); 891 else 892 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 893 entry, jpool_entries); 894 } 895 out: 896 if (error != 0) { 897 switch (state) { 898 case 4: 899 bus_dmamap_unload(sc->sc_dmatag, 900 sc_if->sk_cdata.sk_rx_jumbo_map); 901 case 3: 902 bus_dmamap_destroy(sc->sc_dmatag, 903 sc_if->sk_cdata.sk_rx_jumbo_map); 904 case 2: 905 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 906 case 1: 907 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 908 break; 909 default: 910 break; 911 } 912 } 913 914 return error; 915 } 916 917 /* 918 * Allocate a jumbo buffer. 919 */ 920 void * 921 sk_jalloc(struct sk_if_softc *sc_if) 922 { 923 struct sk_jpool_entry *entry; 924 925 mutex_enter(&sc_if->sk_jpool_mtx); 926 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 927 928 if (entry == NULL) { 929 mutex_exit(&sc_if->sk_jpool_mtx); 930 return NULL; 931 } 932 933 LIST_REMOVE(entry, jpool_entries); 934 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 935 mutex_exit(&sc_if->sk_jpool_mtx); 936 return sc_if->sk_cdata.sk_jslots[entry->slot]; 937 } 938 939 /* 940 * Release a jumbo buffer. 941 */ 942 void 943 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 944 { 945 struct sk_jpool_entry *entry; 946 struct sk_if_softc *sc; 947 int i; 948 949 /* Extract the softc struct pointer. */ 950 sc = (struct sk_if_softc *)arg; 951 952 if (sc == NULL) 953 panic("sk_jfree: can't find softc pointer!"); 954 955 /* calculate the slot this buffer belongs to */ 956 957 i = ((vaddr_t)buf 958 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 959 960 if ((i < 0) || (i >= SK_JSLOTS)) 961 panic("sk_jfree: asked to free buffer that we don't manage!"); 962 963 mutex_enter(&sc->sk_jpool_mtx); 964 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 965 if (entry == NULL) 966 panic("sk_jfree: buffer not in use!"); 967 entry->slot = i; 968 LIST_REMOVE(entry, jpool_entries); 969 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 970 mutex_exit(&sc->sk_jpool_mtx); 971 972 if (__predict_true(m != NULL)) 973 pool_cache_put(mb_cache, m); 974 } 975 976 /* 977 * Set media options. 978 */ 979 int 980 sk_ifmedia_upd(struct ifnet *ifp) 981 { 982 struct sk_if_softc *sc_if = ifp->if_softc; 983 int rc; 984 985 (void) sk_init(ifp); 986 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 987 return 0; 988 return rc; 989 } 990 991 int 992 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 993 { 994 struct sk_if_softc *sc_if = ifp->if_softc; 995 struct sk_softc *sc = sc_if->sk_softc; 996 int s, error = 0; 997 998 /* DPRINTFN(2, ("sk_ioctl\n")); */ 999 1000 s = splnet(); 1001 1002 switch (command) { 1003 1004 case SIOCSIFFLAGS: 1005 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1006 if ((error = ifioctl_common(ifp, command, data)) != 0) 1007 break; 1008 if (ifp->if_flags & IFF_UP) { 1009 if (ifp->if_flags & IFF_RUNNING && 1010 ifp->if_flags & IFF_PROMISC && 1011 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1012 switch (sc->sk_type) { 1013 case SK_GENESIS: 1014 SK_XM_SETBIT_4(sc_if, XM_MODE, 1015 XM_MODE_RX_PROMISC); 1016 break; 1017 case SK_YUKON: 1018 case SK_YUKON_LITE: 1019 case SK_YUKON_LP: 1020 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1021 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1022 break; 1023 } 1024 sk_setmulti(sc_if); 1025 } else if (ifp->if_flags & IFF_RUNNING && 1026 !(ifp->if_flags & IFF_PROMISC) && 1027 sc_if->sk_if_flags & IFF_PROMISC) { 1028 switch (sc->sk_type) { 1029 case SK_GENESIS: 1030 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1031 XM_MODE_RX_PROMISC); 1032 break; 1033 case SK_YUKON: 1034 case SK_YUKON_LITE: 1035 case SK_YUKON_LP: 1036 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1037 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1038 break; 1039 } 1040 1041 sk_setmulti(sc_if); 1042 } else 1043 (void) sk_init(ifp); 1044 } else { 1045 if (ifp->if_flags & IFF_RUNNING) 1046 sk_stop(ifp,0); 1047 } 1048 sc_if->sk_if_flags = ifp->if_flags; 1049 error = 0; 1050 break; 1051 1052 default: 1053 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1054 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1055 break; 1056 1057 error = 0; 1058 1059 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1060 ; 1061 else if (ifp->if_flags & IFF_RUNNING) { 1062 sk_setmulti(sc_if); 1063 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1064 } 1065 break; 1066 } 1067 1068 splx(s); 1069 return error; 1070 } 1071 1072 void 1073 sk_update_int_mod(struct sk_softc *sc) 1074 { 1075 u_int32_t imtimer_ticks; 1076 1077 /* 1078 * Configure interrupt moderation. The moderation timer 1079 * defers interrupts specified in the interrupt moderation 1080 * timer mask based on the timeout specified in the interrupt 1081 * moderation timer init register. Each bit in the timer 1082 * register represents one tick, so to specify a timeout in 1083 * microseconds, we have to multiply by the correct number of 1084 * ticks-per-microsecond. 1085 */ 1086 switch (sc->sk_type) { 1087 case SK_GENESIS: 1088 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1089 break; 1090 case SK_YUKON_EC: 1091 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1092 break; 1093 default: 1094 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1095 } 1096 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1097 sc->sk_int_mod); 1098 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1099 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1100 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1101 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1102 sc->sk_int_mod_pending = 0; 1103 } 1104 1105 /* 1106 * Lookup: Check the PCI vendor and device, and return a pointer to 1107 * The structure if the IDs match against our list. 1108 */ 1109 1110 static const struct sk_product * 1111 sk_lookup(const struct pci_attach_args *pa) 1112 { 1113 const struct sk_product *psk; 1114 1115 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1116 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1117 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1118 return psk; 1119 } 1120 return NULL; 1121 } 1122 1123 /* 1124 * Probe for a SysKonnect GEnesis chip. 1125 */ 1126 1127 int 1128 skc_probe(device_t parent, cfdata_t match, void *aux) 1129 { 1130 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1131 const struct sk_product *psk; 1132 pcireg_t subid; 1133 1134 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1135 1136 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1137 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1138 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1139 subid == SK_LINKSYS_EG1032_SUBID) 1140 return 1; 1141 1142 if ((psk = sk_lookup(pa))) { 1143 return 1; 1144 } 1145 return 0; 1146 } 1147 1148 /* 1149 * Force the GEnesis into reset, then bring it out of reset. 1150 */ 1151 void sk_reset(struct sk_softc *sc) 1152 { 1153 DPRINTFN(2, ("sk_reset\n")); 1154 1155 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1156 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1157 if (SK_YUKON_FAMILY(sc->sk_type)) 1158 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1159 1160 DELAY(1000); 1161 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1162 DELAY(2); 1163 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1164 if (SK_YUKON_FAMILY(sc->sk_type)) 1165 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1166 1167 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1168 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1169 CSR_READ_2(sc, SK_LINK_CTRL))); 1170 1171 if (sc->sk_type == SK_GENESIS) { 1172 /* Configure packet arbiter */ 1173 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1174 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1175 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1176 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1177 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1178 } 1179 1180 /* Enable RAM interface */ 1181 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1182 1183 sk_update_int_mod(sc); 1184 } 1185 1186 int 1187 sk_probe(device_t parent, cfdata_t match, void *aux) 1188 { 1189 struct skc_attach_args *sa = aux; 1190 1191 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1192 return 0; 1193 1194 return 1; 1195 } 1196 1197 /* 1198 * Each XMAC chip is attached as a separate logical IP interface. 1199 * Single port cards will have only one logical interface of course. 1200 */ 1201 void 1202 sk_attach(device_t parent, device_t self, void *aux) 1203 { 1204 struct sk_if_softc *sc_if = device_private(self); 1205 struct sk_softc *sc = device_private(parent); 1206 struct skc_attach_args *sa = aux; 1207 struct sk_txmap_entry *entry; 1208 struct ifnet *ifp; 1209 bus_dma_segment_t seg; 1210 bus_dmamap_t dmamap; 1211 void *kva; 1212 int i, rseg; 1213 int mii_flags = 0; 1214 1215 aprint_naive("\n"); 1216 1217 sc_if->sk_dev = self; 1218 sc_if->sk_port = sa->skc_port; 1219 sc_if->sk_softc = sc; 1220 sc->sk_if[sa->skc_port] = sc_if; 1221 1222 if (sa->skc_port == SK_PORT_A) 1223 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1224 if (sa->skc_port == SK_PORT_B) 1225 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1226 1227 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1228 1229 /* 1230 * Get station address for this interface. Note that 1231 * dual port cards actually come with three station 1232 * addresses: one for each port, plus an extra. The 1233 * extra one is used by the SysKonnect driver software 1234 * as a 'virtual' station address for when both ports 1235 * are operating in failover mode. Currently we don't 1236 * use this extra address. 1237 */ 1238 for (i = 0; i < ETHER_ADDR_LEN; i++) 1239 sc_if->sk_enaddr[i] = 1240 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1241 1242 1243 aprint_normal(": Ethernet address %s\n", 1244 ether_sprintf(sc_if->sk_enaddr)); 1245 1246 /* 1247 * Set up RAM buffer addresses. The NIC will have a certain 1248 * amount of SRAM on it, somewhere between 512K and 2MB. We 1249 * need to divide this up a) between the transmitter and 1250 * receiver and b) between the two XMACs, if this is a 1251 * dual port NIC. Our algorithm is to divide up the memory 1252 * evenly so that everyone gets a fair share. 1253 */ 1254 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1255 u_int32_t chunk, val; 1256 1257 chunk = sc->sk_ramsize / 2; 1258 val = sc->sk_rboff / sizeof(u_int64_t); 1259 sc_if->sk_rx_ramstart = val; 1260 val += (chunk / sizeof(u_int64_t)); 1261 sc_if->sk_rx_ramend = val - 1; 1262 sc_if->sk_tx_ramstart = val; 1263 val += (chunk / sizeof(u_int64_t)); 1264 sc_if->sk_tx_ramend = val - 1; 1265 } else { 1266 u_int32_t chunk, val; 1267 1268 chunk = sc->sk_ramsize / 4; 1269 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1270 sizeof(u_int64_t); 1271 sc_if->sk_rx_ramstart = val; 1272 val += (chunk / sizeof(u_int64_t)); 1273 sc_if->sk_rx_ramend = val - 1; 1274 sc_if->sk_tx_ramstart = val; 1275 val += (chunk / sizeof(u_int64_t)); 1276 sc_if->sk_tx_ramend = val - 1; 1277 } 1278 1279 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1280 " tx_ramstart=%#x tx_ramend=%#x\n", 1281 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1282 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1283 1284 /* Read and save PHY type and set PHY address */ 1285 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1286 switch (sc_if->sk_phytype) { 1287 case SK_PHYTYPE_XMAC: 1288 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1289 break; 1290 case SK_PHYTYPE_BCOM: 1291 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1292 break; 1293 case SK_PHYTYPE_MARV_COPPER: 1294 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1295 break; 1296 default: 1297 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1298 sc_if->sk_phytype); 1299 return; 1300 } 1301 1302 /* Allocate the descriptor queues. */ 1303 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1304 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1305 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1306 goto fail; 1307 } 1308 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1309 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1310 aprint_error_dev(sc_if->sk_dev, 1311 "can't map dma buffers (%lu bytes)\n", 1312 (u_long) sizeof(struct sk_ring_data)); 1313 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1314 goto fail; 1315 } 1316 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1317 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1318 &sc_if->sk_ring_map)) { 1319 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1320 bus_dmamem_unmap(sc->sc_dmatag, kva, 1321 sizeof(struct sk_ring_data)); 1322 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1323 goto fail; 1324 } 1325 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1326 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1327 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1328 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1329 bus_dmamem_unmap(sc->sc_dmatag, kva, 1330 sizeof(struct sk_ring_data)); 1331 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1332 goto fail; 1333 } 1334 1335 for (i = 0; i < SK_RX_RING_CNT; i++) 1336 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1337 1338 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1339 for (i = 0; i < SK_TX_RING_CNT; i++) { 1340 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1341 1342 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1343 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1344 aprint_error_dev(sc_if->sk_dev, 1345 "Can't create TX dmamap\n"); 1346 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1347 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1348 bus_dmamem_unmap(sc->sc_dmatag, kva, 1349 sizeof(struct sk_ring_data)); 1350 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1351 goto fail; 1352 } 1353 1354 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1355 if (!entry) { 1356 aprint_error_dev(sc_if->sk_dev, 1357 "Can't alloc txmap entry\n"); 1358 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1359 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1360 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1361 bus_dmamem_unmap(sc->sc_dmatag, kva, 1362 sizeof(struct sk_ring_data)); 1363 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1364 goto fail; 1365 } 1366 entry->dmamap = dmamap; 1367 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1368 } 1369 1370 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1371 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1372 1373 ifp = &sc_if->sk_ethercom.ec_if; 1374 /* Try to allocate memory for jumbo buffers. */ 1375 if (sk_alloc_jumbo_mem(sc_if)) { 1376 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1377 goto fail; 1378 } 1379 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1380 | ETHERCAP_JUMBO_MTU; 1381 1382 ifp->if_softc = sc_if; 1383 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1384 ifp->if_ioctl = sk_ioctl; 1385 ifp->if_start = sk_start; 1386 ifp->if_stop = sk_stop; 1387 ifp->if_init = sk_init; 1388 ifp->if_watchdog = sk_watchdog; 1389 ifp->if_capabilities = 0; 1390 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1391 IFQ_SET_READY(&ifp->if_snd); 1392 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1393 1394 /* 1395 * Do miibus setup. 1396 */ 1397 switch (sc->sk_type) { 1398 case SK_GENESIS: 1399 sk_init_xmac(sc_if); 1400 break; 1401 case SK_YUKON: 1402 case SK_YUKON_LITE: 1403 case SK_YUKON_LP: 1404 sk_init_yukon(sc_if); 1405 break; 1406 default: 1407 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1408 sc->sk_type); 1409 goto fail; 1410 } 1411 1412 DPRINTFN(2, ("sk_attach: 1\n")); 1413 1414 sc_if->sk_mii.mii_ifp = ifp; 1415 switch (sc->sk_type) { 1416 case SK_GENESIS: 1417 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1418 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1419 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1420 break; 1421 case SK_YUKON: 1422 case SK_YUKON_LITE: 1423 case SK_YUKON_LP: 1424 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1425 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1426 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1427 mii_flags = MIIF_DOPAUSE; 1428 break; 1429 } 1430 1431 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1432 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1433 sk_ifmedia_upd, ether_mediastatus); 1434 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1435 MII_OFFSET_ANY, mii_flags); 1436 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1437 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1438 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1439 0, NULL); 1440 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1441 } else 1442 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1443 1444 callout_init(&sc_if->sk_tick_ch, 0); 1445 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1446 1447 DPRINTFN(2, ("sk_attach: 1\n")); 1448 1449 /* 1450 * Call MI attach routines. 1451 */ 1452 if_attach(ifp); 1453 1454 ether_ifattach(ifp, sc_if->sk_enaddr); 1455 1456 #if NRND > 0 1457 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1458 RND_TYPE_NET, 0); 1459 #endif 1460 1461 DPRINTFN(2, ("sk_attach: end\n")); 1462 1463 return; 1464 1465 fail: 1466 sc->sk_if[sa->skc_port] = NULL; 1467 } 1468 1469 int 1470 skcprint(void *aux, const char *pnp) 1471 { 1472 struct skc_attach_args *sa = aux; 1473 1474 if (pnp) 1475 aprint_normal("sk port %c at %s", 1476 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1477 else 1478 aprint_normal(" port %c", 1479 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1480 return UNCONF; 1481 } 1482 1483 /* 1484 * Attach the interface. Allocate softc structures, do ifmedia 1485 * setup and ethernet/BPF attach. 1486 */ 1487 void 1488 skc_attach(device_t parent, device_t self, void *aux) 1489 { 1490 struct sk_softc *sc = device_private(self); 1491 struct pci_attach_args *pa = aux; 1492 struct skc_attach_args skca; 1493 pci_chipset_tag_t pc = pa->pa_pc; 1494 #ifndef SK_USEIOSPACE 1495 pcireg_t memtype; 1496 #endif 1497 pci_intr_handle_t ih; 1498 const char *intrstr = NULL; 1499 bus_addr_t iobase; 1500 bus_size_t iosize; 1501 int rc, sk_nodenum; 1502 u_int32_t command; 1503 const char *revstr; 1504 const struct sysctlnode *node; 1505 1506 sc->sk_dev = self; 1507 aprint_naive("\n"); 1508 1509 DPRINTFN(2, ("begin skc_attach\n")); 1510 1511 /* 1512 * Handle power management nonsense. 1513 */ 1514 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1515 1516 if (command == 0x01) { 1517 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1518 if (command & SK_PSTATE_MASK) { 1519 u_int32_t xiobase, membase, irq; 1520 1521 /* Save important PCI config data. */ 1522 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1523 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1524 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1525 1526 /* Reset the power state. */ 1527 aprint_normal_dev(sc->sk_dev, 1528 "chip is in D%d power mode -- setting to D0\n", 1529 command & SK_PSTATE_MASK); 1530 command &= 0xFFFFFFFC; 1531 pci_conf_write(pc, pa->pa_tag, 1532 SK_PCI_PWRMGMTCTRL, command); 1533 1534 /* Restore PCI config data. */ 1535 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1536 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1537 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1538 } 1539 } 1540 1541 /* 1542 * Map control/status registers. 1543 */ 1544 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1545 command |= PCI_COMMAND_IO_ENABLE | 1546 PCI_COMMAND_MEM_ENABLE | 1547 PCI_COMMAND_MASTER_ENABLE; 1548 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1549 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1550 1551 #ifdef SK_USEIOSPACE 1552 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1553 aprint_error(": failed to enable I/O ports!\n"); 1554 return; 1555 } 1556 /* 1557 * Map control/status registers. 1558 */ 1559 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1560 &sc->sk_btag, &sc->sk_bhandle, 1561 &iobase, &iosize)) { 1562 aprint_error(": can't find i/o space\n"); 1563 return; 1564 } 1565 #else 1566 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1567 aprint_error(": failed to enable memory mapping!\n"); 1568 return; 1569 } 1570 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1571 switch (memtype) { 1572 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1573 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1574 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1575 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1576 &iobase, &iosize) == 0) 1577 break; 1578 default: 1579 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1580 return; 1581 } 1582 1583 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1584 #endif 1585 sc->sc_dmatag = pa->pa_dmat; 1586 1587 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1588 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1589 1590 /* bail out here if chip is not recognized */ 1591 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1592 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1593 goto fail; 1594 } 1595 if (SK_IS_YUKON2(sc)) { 1596 aprint_error_dev(sc->sk_dev, 1597 "Does not support Yukon2--try msk(4).\n"); 1598 goto fail; 1599 } 1600 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1601 1602 /* Allocate interrupt */ 1603 if (pci_intr_map(pa, &ih)) { 1604 aprint_error(": couldn't map interrupt\n"); 1605 goto fail; 1606 } 1607 1608 intrstr = pci_intr_string(pc, ih); 1609 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1610 if (sc->sk_intrhand == NULL) { 1611 aprint_error(": couldn't establish interrupt"); 1612 if (intrstr != NULL) 1613 aprint_normal(" at %s", intrstr); 1614 goto fail; 1615 } 1616 aprint_normal(": %s\n", intrstr); 1617 1618 /* Reset the adapter. */ 1619 sk_reset(sc); 1620 1621 /* Read and save vital product data from EEPROM. */ 1622 sk_vpd_read(sc); 1623 1624 if (sc->sk_type == SK_GENESIS) { 1625 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1626 /* Read and save RAM size and RAMbuffer offset */ 1627 switch (val) { 1628 case SK_RAMSIZE_512K_64: 1629 sc->sk_ramsize = 0x80000; 1630 sc->sk_rboff = SK_RBOFF_0; 1631 break; 1632 case SK_RAMSIZE_1024K_64: 1633 sc->sk_ramsize = 0x100000; 1634 sc->sk_rboff = SK_RBOFF_80000; 1635 break; 1636 case SK_RAMSIZE_1024K_128: 1637 sc->sk_ramsize = 0x100000; 1638 sc->sk_rboff = SK_RBOFF_0; 1639 break; 1640 case SK_RAMSIZE_2048K_128: 1641 sc->sk_ramsize = 0x200000; 1642 sc->sk_rboff = SK_RBOFF_0; 1643 break; 1644 default: 1645 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1646 val); 1647 goto fail_1; 1648 break; 1649 } 1650 1651 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1652 sc->sk_ramsize, sc->sk_ramsize / 1024, 1653 sc->sk_rboff)); 1654 } else { 1655 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1656 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1657 sc->sk_rboff = SK_RBOFF_0; 1658 1659 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1660 sc->sk_ramsize / 1024, sc->sk_ramsize, 1661 sc->sk_rboff)); 1662 } 1663 1664 /* Read and save physical media type */ 1665 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1666 case SK_PMD_1000BASESX: 1667 sc->sk_pmd = IFM_1000_SX; 1668 break; 1669 case SK_PMD_1000BASELX: 1670 sc->sk_pmd = IFM_1000_LX; 1671 break; 1672 case SK_PMD_1000BASECX: 1673 sc->sk_pmd = IFM_1000_CX; 1674 break; 1675 case SK_PMD_1000BASETX: 1676 case SK_PMD_1000BASETX_ALT: 1677 sc->sk_pmd = IFM_1000_T; 1678 break; 1679 default: 1680 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1681 sk_win_read_1(sc, SK_PMDTYPE)); 1682 goto fail_1; 1683 } 1684 1685 /* determine whether to name it with vpd or just make it up */ 1686 /* Marvell Yukon VPD's can freqently be bogus */ 1687 1688 switch (pa->pa_id) { 1689 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1690 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1691 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1692 case PCI_PRODUCT_3COM_3C940: 1693 case PCI_PRODUCT_DLINK_DGE530T: 1694 case PCI_PRODUCT_DLINK_DGE560T: 1695 case PCI_PRODUCT_DLINK_DGE560T_2: 1696 case PCI_PRODUCT_LINKSYS_EG1032: 1697 case PCI_PRODUCT_LINKSYS_EG1064: 1698 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1699 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1700 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1701 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1702 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1703 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1704 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1705 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1706 sc->sk_name = sc->sk_vpd_prodname; 1707 break; 1708 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1709 /* whoops yukon vpd prodname bears no resemblance to reality */ 1710 switch (sc->sk_type) { 1711 case SK_GENESIS: 1712 sc->sk_name = sc->sk_vpd_prodname; 1713 break; 1714 case SK_YUKON: 1715 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1716 break; 1717 case SK_YUKON_LITE: 1718 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1719 break; 1720 case SK_YUKON_LP: 1721 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1722 break; 1723 default: 1724 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1725 } 1726 1727 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1728 1729 if ( sc->sk_type == SK_YUKON ) { 1730 uint32_t flashaddr; 1731 uint8_t testbyte; 1732 1733 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1734 1735 /* test Flash-Address Register */ 1736 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1737 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1738 1739 if (testbyte != 0) { 1740 /* this is yukon lite Rev. A0 */ 1741 sc->sk_type = SK_YUKON_LITE; 1742 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1743 /* restore Flash-Address Register */ 1744 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1745 } 1746 } 1747 break; 1748 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1749 sc->sk_name = sc->sk_vpd_prodname; 1750 break; 1751 default: 1752 sc->sk_name = "Unknown Marvell"; 1753 } 1754 1755 1756 if ( sc->sk_type == SK_YUKON_LITE ) { 1757 switch (sc->sk_rev) { 1758 case SK_YUKON_LITE_REV_A0: 1759 revstr = "A0"; 1760 break; 1761 case SK_YUKON_LITE_REV_A1: 1762 revstr = "A1"; 1763 break; 1764 case SK_YUKON_LITE_REV_A3: 1765 revstr = "A3"; 1766 break; 1767 default: 1768 revstr = ""; 1769 } 1770 } else { 1771 revstr = ""; 1772 } 1773 1774 /* Announce the product name. */ 1775 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1776 sc->sk_name, revstr, sc->sk_rev); 1777 1778 skca.skc_port = SK_PORT_A; 1779 (void)config_found(sc->sk_dev, &skca, skcprint); 1780 1781 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1782 skca.skc_port = SK_PORT_B; 1783 (void)config_found(sc->sk_dev, &skca, skcprint); 1784 } 1785 1786 /* Turn on the 'driver is loaded' LED. */ 1787 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1788 1789 /* skc sysctl setup */ 1790 1791 sc->sk_int_mod = SK_IM_DEFAULT; 1792 sc->sk_int_mod_pending = 0; 1793 1794 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1795 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1796 SYSCTL_DESCR("skc per-controller controls"), 1797 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1798 CTL_EOL)) != 0) { 1799 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1800 goto fail_1; 1801 } 1802 1803 sk_nodenum = node->sysctl_num; 1804 1805 /* interrupt moderation time in usecs */ 1806 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1807 CTLFLAG_READWRITE, 1808 CTLTYPE_INT, "int_mod", 1809 SYSCTL_DESCR("sk interrupt moderation timer"), 1810 sk_sysctl_handler, 0, sc, 1811 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1812 CTL_EOL)) != 0) { 1813 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1814 goto fail_1; 1815 } 1816 1817 return; 1818 1819 fail_1: 1820 pci_intr_disestablish(pc, sc->sk_intrhand); 1821 fail: 1822 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1823 } 1824 1825 int 1826 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1827 { 1828 struct sk_softc *sc = sc_if->sk_softc; 1829 struct sk_tx_desc *f = NULL; 1830 u_int32_t frag, cur, cnt = 0, sk_ctl; 1831 int i; 1832 struct sk_txmap_entry *entry; 1833 bus_dmamap_t txmap; 1834 1835 DPRINTFN(3, ("sk_encap\n")); 1836 1837 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1838 if (entry == NULL) { 1839 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1840 return ENOBUFS; 1841 } 1842 txmap = entry->dmamap; 1843 1844 cur = frag = *txidx; 1845 1846 #ifdef SK_DEBUG 1847 if (skdebug >= 3) 1848 sk_dump_mbuf(m_head); 1849 #endif 1850 1851 /* 1852 * Start packing the mbufs in this chain into 1853 * the fragment pointers. Stop when we run out 1854 * of fragments or hit the end of the mbuf chain. 1855 */ 1856 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1857 BUS_DMA_NOWAIT)) { 1858 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1859 return ENOBUFS; 1860 } 1861 1862 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1863 1864 /* Sync the DMA map. */ 1865 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1866 BUS_DMASYNC_PREWRITE); 1867 1868 for (i = 0; i < txmap->dm_nsegs; i++) { 1869 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1870 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1871 return ENOBUFS; 1872 } 1873 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1874 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1875 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1876 if (cnt == 0) 1877 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1878 else 1879 sk_ctl |= SK_TXCTL_OWN; 1880 f->sk_ctl = htole32(sk_ctl); 1881 cur = frag; 1882 SK_INC(frag, SK_TX_RING_CNT); 1883 cnt++; 1884 } 1885 1886 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1887 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1888 1889 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1890 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1891 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1892 1893 /* Sync descriptors before handing to chip */ 1894 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1895 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1896 1897 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1898 htole32(SK_TXCTL_OWN); 1899 1900 /* Sync first descriptor to hand it off */ 1901 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1902 1903 sc_if->sk_cdata.sk_tx_cnt += cnt; 1904 1905 #ifdef SK_DEBUG 1906 if (skdebug >= 3) { 1907 struct sk_tx_desc *desc; 1908 u_int32_t idx; 1909 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1910 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1911 sk_dump_txdesc(desc, idx); 1912 } 1913 } 1914 #endif 1915 1916 *txidx = frag; 1917 1918 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1919 1920 return 0; 1921 } 1922 1923 void 1924 sk_start(struct ifnet *ifp) 1925 { 1926 struct sk_if_softc *sc_if = ifp->if_softc; 1927 struct sk_softc *sc = sc_if->sk_softc; 1928 struct mbuf *m_head = NULL; 1929 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1930 int pkts = 0; 1931 1932 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1933 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1934 1935 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1936 IFQ_POLL(&ifp->if_snd, m_head); 1937 if (m_head == NULL) 1938 break; 1939 1940 /* 1941 * Pack the data into the transmit ring. If we 1942 * don't have room, set the OACTIVE flag and wait 1943 * for the NIC to drain the ring. 1944 */ 1945 if (sk_encap(sc_if, m_head, &idx)) { 1946 ifp->if_flags |= IFF_OACTIVE; 1947 break; 1948 } 1949 1950 /* now we are committed to transmit the packet */ 1951 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1952 pkts++; 1953 1954 /* 1955 * If there's a BPF listener, bounce a copy of this frame 1956 * to him. 1957 */ 1958 #if NBPFILTER > 0 1959 if (ifp->if_bpf) 1960 bpf_mtap(ifp->if_bpf, m_head); 1961 #endif 1962 } 1963 if (pkts == 0) 1964 return; 1965 1966 /* Transmit */ 1967 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1968 sc_if->sk_cdata.sk_tx_prod = idx; 1969 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1970 1971 /* Set a timeout in case the chip goes out to lunch. */ 1972 ifp->if_timer = 5; 1973 } 1974 } 1975 1976 1977 void 1978 sk_watchdog(struct ifnet *ifp) 1979 { 1980 struct sk_if_softc *sc_if = ifp->if_softc; 1981 1982 /* 1983 * Reclaim first as there is a possibility of losing Tx completion 1984 * interrupts. 1985 */ 1986 sk_txeof(sc_if); 1987 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1988 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1989 1990 ifp->if_oerrors++; 1991 1992 sk_init(ifp); 1993 } 1994 } 1995 1996 void 1997 sk_shutdown(void *v) 1998 { 1999 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2000 struct sk_softc *sc = sc_if->sk_softc; 2001 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2002 2003 DPRINTFN(2, ("sk_shutdown\n")); 2004 sk_stop(ifp,1); 2005 2006 /* Turn off the 'driver is loaded' LED. */ 2007 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2008 2009 /* 2010 * Reset the GEnesis controller. Doing this should also 2011 * assert the resets on the attached XMAC(s). 2012 */ 2013 sk_reset(sc); 2014 } 2015 2016 void 2017 sk_rxeof(struct sk_if_softc *sc_if) 2018 { 2019 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2020 struct mbuf *m; 2021 struct sk_chain *cur_rx; 2022 struct sk_rx_desc *cur_desc; 2023 int i, cur, total_len = 0; 2024 u_int32_t rxstat, sk_ctl; 2025 bus_dmamap_t dmamap; 2026 2027 i = sc_if->sk_cdata.sk_rx_prod; 2028 2029 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2030 2031 for (;;) { 2032 cur = i; 2033 2034 /* Sync the descriptor */ 2035 SK_CDRXSYNC(sc_if, cur, 2036 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2037 2038 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2039 if (sk_ctl & SK_RXCTL_OWN) { 2040 /* Invalidate the descriptor -- it's not ready yet */ 2041 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2042 sc_if->sk_cdata.sk_rx_prod = i; 2043 break; 2044 } 2045 2046 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2047 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2048 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2049 2050 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2051 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2052 2053 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2054 m = cur_rx->sk_mbuf; 2055 cur_rx->sk_mbuf = NULL; 2056 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2057 2058 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2059 2060 SK_INC(i, SK_RX_RING_CNT); 2061 2062 if (rxstat & XM_RXSTAT_ERRFRAME) { 2063 ifp->if_ierrors++; 2064 sk_newbuf(sc_if, cur, m, dmamap); 2065 continue; 2066 } 2067 2068 /* 2069 * Try to allocate a new jumbo buffer. If that 2070 * fails, copy the packet to mbufs and put the 2071 * jumbo buffer back in the ring so it can be 2072 * re-used. If allocating mbufs fails, then we 2073 * have to drop the packet. 2074 */ 2075 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2076 struct mbuf *m0; 2077 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2078 total_len + ETHER_ALIGN, 0, ifp, NULL); 2079 sk_newbuf(sc_if, cur, m, dmamap); 2080 if (m0 == NULL) { 2081 aprint_error_dev(sc_if->sk_dev, "no receive " 2082 "buffers available -- packet dropped!\n"); 2083 ifp->if_ierrors++; 2084 continue; 2085 } 2086 m_adj(m0, ETHER_ALIGN); 2087 m = m0; 2088 } else { 2089 m->m_pkthdr.rcvif = ifp; 2090 m->m_pkthdr.len = m->m_len = total_len; 2091 } 2092 2093 ifp->if_ipackets++; 2094 2095 #if NBPFILTER > 0 2096 if (ifp->if_bpf) 2097 bpf_mtap(ifp->if_bpf, m); 2098 #endif 2099 /* pass it on. */ 2100 (*ifp->if_input)(ifp, m); 2101 } 2102 } 2103 2104 void 2105 sk_txeof(struct sk_if_softc *sc_if) 2106 { 2107 struct sk_softc *sc = sc_if->sk_softc; 2108 struct sk_tx_desc *cur_tx; 2109 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2110 u_int32_t idx, sk_ctl; 2111 struct sk_txmap_entry *entry; 2112 2113 DPRINTFN(3, ("sk_txeof\n")); 2114 2115 /* 2116 * Go through our tx ring and free mbufs for those 2117 * frames that have been sent. 2118 */ 2119 idx = sc_if->sk_cdata.sk_tx_cons; 2120 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2121 SK_CDTXSYNC(sc_if, idx, 1, 2122 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2123 2124 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2125 sk_ctl = le32toh(cur_tx->sk_ctl); 2126 #ifdef SK_DEBUG 2127 if (skdebug >= 3) 2128 sk_dump_txdesc(cur_tx, idx); 2129 #endif 2130 if (sk_ctl & SK_TXCTL_OWN) { 2131 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2132 break; 2133 } 2134 if (sk_ctl & SK_TXCTL_LASTFRAG) 2135 ifp->if_opackets++; 2136 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2137 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2138 2139 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2140 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2141 2142 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2143 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2144 2145 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2146 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2147 link); 2148 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2149 } 2150 sc_if->sk_cdata.sk_tx_cnt--; 2151 SK_INC(idx, SK_TX_RING_CNT); 2152 } 2153 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2154 ifp->if_timer = 0; 2155 else /* nudge chip to keep tx ring moving */ 2156 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2157 2158 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2159 ifp->if_flags &= ~IFF_OACTIVE; 2160 2161 sc_if->sk_cdata.sk_tx_cons = idx; 2162 } 2163 2164 void 2165 sk_tick(void *xsc_if) 2166 { 2167 struct sk_if_softc *sc_if = xsc_if; 2168 struct mii_data *mii = &sc_if->sk_mii; 2169 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2170 int i; 2171 2172 DPRINTFN(3, ("sk_tick\n")); 2173 2174 if (!(ifp->if_flags & IFF_UP)) 2175 return; 2176 2177 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2178 sk_intr_bcom(sc_if); 2179 return; 2180 } 2181 2182 /* 2183 * According to SysKonnect, the correct way to verify that 2184 * the link has come back up is to poll bit 0 of the GPIO 2185 * register three times. This pin has the signal from the 2186 * link sync pin connected to it; if we read the same link 2187 * state 3 times in a row, we know the link is up. 2188 */ 2189 for (i = 0; i < 3; i++) { 2190 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2191 break; 2192 } 2193 2194 if (i != 3) { 2195 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2196 return; 2197 } 2198 2199 /* Turn the GP0 interrupt back on. */ 2200 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2201 SK_XM_READ_2(sc_if, XM_ISR); 2202 mii_tick(mii); 2203 mii_pollstat(mii); 2204 callout_stop(&sc_if->sk_tick_ch); 2205 } 2206 2207 void 2208 sk_intr_bcom(struct sk_if_softc *sc_if) 2209 { 2210 struct mii_data *mii = &sc_if->sk_mii; 2211 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2212 int status; 2213 2214 2215 DPRINTFN(3, ("sk_intr_bcom\n")); 2216 2217 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2218 2219 /* 2220 * Read the PHY interrupt register to make sure 2221 * we clear any pending interrupts. 2222 */ 2223 status = sk_xmac_miibus_readreg(sc_if->sk_dev, 2224 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2225 2226 if (!(ifp->if_flags & IFF_RUNNING)) { 2227 sk_init_xmac(sc_if); 2228 return; 2229 } 2230 2231 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2232 int lstat; 2233 lstat = sk_xmac_miibus_readreg(sc_if->sk_dev, 2234 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2235 2236 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2237 (void)mii_mediachg(mii); 2238 /* Turn off the link LED. */ 2239 SK_IF_WRITE_1(sc_if, 0, 2240 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2241 sc_if->sk_link = 0; 2242 } else if (status & BRGPHY_ISR_LNK_CHG) { 2243 sk_xmac_miibus_writereg(sc_if->sk_dev, 2244 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2245 mii_tick(mii); 2246 sc_if->sk_link = 1; 2247 /* Turn on the link LED. */ 2248 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2249 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2250 SK_LINKLED_BLINK_OFF); 2251 mii_pollstat(mii); 2252 } else { 2253 mii_tick(mii); 2254 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2255 } 2256 } 2257 2258 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2259 } 2260 2261 void 2262 sk_intr_xmac(struct sk_if_softc *sc_if) 2263 { 2264 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2265 2266 DPRINTFN(3, ("sk_intr_xmac\n")); 2267 2268 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2269 if (status & XM_ISR_GP0_SET) { 2270 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2271 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2272 } 2273 2274 if (status & XM_ISR_AUTONEG_DONE) { 2275 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2276 } 2277 } 2278 2279 if (status & XM_IMR_TX_UNDERRUN) 2280 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2281 2282 if (status & XM_IMR_RX_OVERRUN) 2283 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2284 } 2285 2286 void 2287 sk_intr_yukon(struct sk_if_softc *sc_if) 2288 { 2289 int status; 2290 2291 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2292 2293 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2294 } 2295 2296 int 2297 sk_intr(void *xsc) 2298 { 2299 struct sk_softc *sc = xsc; 2300 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2301 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2302 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2303 u_int32_t status; 2304 int claimed = 0; 2305 2306 if (sc_if0 != NULL) 2307 ifp0 = &sc_if0->sk_ethercom.ec_if; 2308 if (sc_if1 != NULL) 2309 ifp1 = &sc_if1->sk_ethercom.ec_if; 2310 2311 for (;;) { 2312 status = CSR_READ_4(sc, SK_ISSR); 2313 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2314 2315 if (!(status & sc->sk_intrmask)) 2316 break; 2317 2318 claimed = 1; 2319 2320 /* Handle receive interrupts first. */ 2321 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2322 sk_rxeof(sc_if0); 2323 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2324 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2325 } 2326 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2327 sk_rxeof(sc_if1); 2328 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2329 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2330 } 2331 2332 /* Then transmit interrupts. */ 2333 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2334 sk_txeof(sc_if0); 2335 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2336 SK_TXBMU_CLR_IRQ_EOF); 2337 } 2338 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2339 sk_txeof(sc_if1); 2340 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2341 SK_TXBMU_CLR_IRQ_EOF); 2342 } 2343 2344 /* Then MAC interrupts. */ 2345 if (sc_if0 && (status & SK_ISR_MAC1) && 2346 (ifp0->if_flags & IFF_RUNNING)) { 2347 if (sc->sk_type == SK_GENESIS) 2348 sk_intr_xmac(sc_if0); 2349 else 2350 sk_intr_yukon(sc_if0); 2351 } 2352 2353 if (sc_if1 && (status & SK_ISR_MAC2) && 2354 (ifp1->if_flags & IFF_RUNNING)) { 2355 if (sc->sk_type == SK_GENESIS) 2356 sk_intr_xmac(sc_if1); 2357 else 2358 sk_intr_yukon(sc_if1); 2359 2360 } 2361 2362 if (status & SK_ISR_EXTERNAL_REG) { 2363 if (sc_if0 != NULL && 2364 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2365 sk_intr_bcom(sc_if0); 2366 2367 if (sc_if1 != NULL && 2368 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2369 sk_intr_bcom(sc_if1); 2370 } 2371 } 2372 2373 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2374 2375 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2376 sk_start(ifp0); 2377 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2378 sk_start(ifp1); 2379 2380 #if NRND > 0 2381 if (RND_ENABLED(&sc->rnd_source)) 2382 rnd_add_uint32(&sc->rnd_source, status); 2383 #endif 2384 2385 if (sc->sk_int_mod_pending) 2386 sk_update_int_mod(sc); 2387 2388 return claimed; 2389 } 2390 2391 void 2392 sk_init_xmac(struct sk_if_softc *sc_if) 2393 { 2394 struct sk_softc *sc = sc_if->sk_softc; 2395 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2396 static const struct sk_bcom_hack bhack[] = { 2397 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2398 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2399 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2400 { 0, 0 } }; 2401 2402 DPRINTFN(1, ("sk_init_xmac\n")); 2403 2404 /* Unreset the XMAC. */ 2405 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2406 DELAY(1000); 2407 2408 /* Reset the XMAC's internal state. */ 2409 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2410 2411 /* Save the XMAC II revision */ 2412 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2413 2414 /* 2415 * Perform additional initialization for external PHYs, 2416 * namely for the 1000baseTX cards that use the XMAC's 2417 * GMII mode. 2418 */ 2419 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2420 int i = 0; 2421 u_int32_t val; 2422 2423 /* Take PHY out of reset. */ 2424 val = sk_win_read_4(sc, SK_GPIO); 2425 if (sc_if->sk_port == SK_PORT_A) 2426 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2427 else 2428 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2429 sk_win_write_4(sc, SK_GPIO, val); 2430 2431 /* Enable GMII mode on the XMAC. */ 2432 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2433 2434 sk_xmac_miibus_writereg(sc_if->sk_dev, 2435 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2436 DELAY(10000); 2437 sk_xmac_miibus_writereg(sc_if->sk_dev, 2438 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2439 2440 /* 2441 * Early versions of the BCM5400 apparently have 2442 * a bug that requires them to have their reserved 2443 * registers initialized to some magic values. I don't 2444 * know what the numbers do, I'm just the messenger. 2445 */ 2446 if (sk_xmac_miibus_readreg(sc_if->sk_dev, 2447 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2448 while (bhack[i].reg) { 2449 sk_xmac_miibus_writereg(sc_if->sk_dev, 2450 SK_PHYADDR_BCOM, bhack[i].reg, 2451 bhack[i].val); 2452 i++; 2453 } 2454 } 2455 } 2456 2457 /* Set station address */ 2458 SK_XM_WRITE_2(sc_if, XM_PAR0, 2459 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2460 SK_XM_WRITE_2(sc_if, XM_PAR1, 2461 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2462 SK_XM_WRITE_2(sc_if, XM_PAR2, 2463 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2464 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2465 2466 if (ifp->if_flags & IFF_PROMISC) 2467 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2468 else 2469 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2470 2471 if (ifp->if_flags & IFF_BROADCAST) 2472 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2473 else 2474 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2475 2476 /* We don't need the FCS appended to the packet. */ 2477 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2478 2479 /* We want short frames padded to 60 bytes. */ 2480 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2481 2482 /* 2483 * Enable the reception of all error frames. This is is 2484 * a necessary evil due to the design of the XMAC. The 2485 * XMAC's receive FIFO is only 8K in size, however jumbo 2486 * frames can be up to 9000 bytes in length. When bad 2487 * frame filtering is enabled, the XMAC's RX FIFO operates 2488 * in 'store and forward' mode. For this to work, the 2489 * entire frame has to fit into the FIFO, but that means 2490 * that jumbo frames larger than 8192 bytes will be 2491 * truncated. Disabling all bad frame filtering causes 2492 * the RX FIFO to operate in streaming mode, in which 2493 * case the XMAC will start transfering frames out of the 2494 * RX FIFO as soon as the FIFO threshold is reached. 2495 */ 2496 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2497 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2498 XM_MODE_RX_INRANGELEN); 2499 2500 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2501 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2502 else 2503 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2504 2505 /* 2506 * Bump up the transmit threshold. This helps hold off transmit 2507 * underruns when we're blasting traffic from both ports at once. 2508 */ 2509 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2510 2511 /* Set multicast filter */ 2512 sk_setmulti(sc_if); 2513 2514 /* Clear and enable interrupts */ 2515 SK_XM_READ_2(sc_if, XM_ISR); 2516 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2517 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2518 else 2519 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2520 2521 /* Configure MAC arbiter */ 2522 switch (sc_if->sk_xmac_rev) { 2523 case XM_XMAC_REV_B2: 2524 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2525 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2526 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2527 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2528 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2529 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2530 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2531 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2532 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2533 break; 2534 case XM_XMAC_REV_C1: 2535 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2536 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2537 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2538 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2539 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2540 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2541 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2542 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2543 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2544 break; 2545 default: 2546 break; 2547 } 2548 sk_win_write_2(sc, SK_MACARB_CTL, 2549 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2550 2551 sc_if->sk_link = 1; 2552 } 2553 2554 void sk_init_yukon(struct sk_if_softc *sc_if) 2555 { 2556 u_int32_t /*mac, */phy; 2557 u_int16_t reg; 2558 struct sk_softc *sc; 2559 int i; 2560 2561 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2562 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2563 2564 sc = sc_if->sk_softc; 2565 if (sc->sk_type == SK_YUKON_LITE && 2566 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2567 /* Take PHY out of reset. */ 2568 sk_win_write_4(sc, SK_GPIO, 2569 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2570 } 2571 2572 2573 /* GMAC and GPHY Reset */ 2574 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2575 2576 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2577 2578 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2579 DELAY(1000); 2580 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2581 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2582 DELAY(1000); 2583 2584 2585 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2586 2587 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2588 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2589 2590 switch (sc_if->sk_softc->sk_pmd) { 2591 case IFM_1000_SX: 2592 case IFM_1000_LX: 2593 phy |= SK_GPHY_FIBER; 2594 break; 2595 2596 case IFM_1000_CX: 2597 case IFM_1000_T: 2598 phy |= SK_GPHY_COPPER; 2599 break; 2600 } 2601 2602 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2603 2604 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2605 DELAY(1000); 2606 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2607 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2608 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2609 2610 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2611 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2612 2613 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2614 2615 /* unused read of the interrupt source register */ 2616 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2617 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2618 2619 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2620 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2621 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2622 2623 /* MIB Counter Clear Mode set */ 2624 reg |= YU_PAR_MIB_CLR; 2625 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2626 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2627 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2628 2629 /* MIB Counter Clear Mode clear */ 2630 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2631 reg &= ~YU_PAR_MIB_CLR; 2632 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2633 2634 /* receive control reg */ 2635 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2636 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2637 YU_RCR_CRCR); 2638 2639 /* transmit parameter register */ 2640 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2641 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2642 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2643 2644 /* serial mode register */ 2645 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2646 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2647 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2648 YU_SMR_IPG_DATA(0x1e)); 2649 2650 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2651 /* Setup Yukon's address */ 2652 for (i = 0; i < 3; i++) { 2653 /* Write Source Address 1 (unicast filter) */ 2654 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2655 sc_if->sk_enaddr[i * 2] | 2656 sc_if->sk_enaddr[i * 2 + 1] << 8); 2657 } 2658 2659 for (i = 0; i < 3; i++) { 2660 reg = sk_win_read_2(sc_if->sk_softc, 2661 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2662 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2663 } 2664 2665 /* Set multicast filter */ 2666 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2667 sk_setmulti(sc_if); 2668 2669 /* enable interrupt mask for counter overflows */ 2670 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2671 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2672 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2673 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2674 2675 /* Configure RX MAC FIFO */ 2676 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2677 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2678 2679 /* Configure TX MAC FIFO */ 2680 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2681 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2682 2683 DPRINTFN(6, ("sk_init_yukon: end\n")); 2684 } 2685 2686 /* 2687 * Note that to properly initialize any part of the GEnesis chip, 2688 * you first have to take it out of reset mode. 2689 */ 2690 int 2691 sk_init(struct ifnet *ifp) 2692 { 2693 struct sk_if_softc *sc_if = ifp->if_softc; 2694 struct sk_softc *sc = sc_if->sk_softc; 2695 struct mii_data *mii = &sc_if->sk_mii; 2696 int rc = 0, s; 2697 u_int32_t imr, imtimer_ticks; 2698 2699 DPRINTFN(1, ("sk_init\n")); 2700 2701 s = splnet(); 2702 2703 if (ifp->if_flags & IFF_RUNNING) { 2704 splx(s); 2705 return 0; 2706 } 2707 2708 /* Cancel pending I/O and free all RX/TX buffers. */ 2709 sk_stop(ifp,0); 2710 2711 if (sc->sk_type == SK_GENESIS) { 2712 /* Configure LINK_SYNC LED */ 2713 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2714 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2715 SK_LINKLED_LINKSYNC_ON); 2716 2717 /* Configure RX LED */ 2718 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2719 SK_RXLEDCTL_COUNTER_START); 2720 2721 /* Configure TX LED */ 2722 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2723 SK_TXLEDCTL_COUNTER_START); 2724 } 2725 2726 /* Configure I2C registers */ 2727 2728 /* Configure XMAC(s) */ 2729 switch (sc->sk_type) { 2730 case SK_GENESIS: 2731 sk_init_xmac(sc_if); 2732 break; 2733 case SK_YUKON: 2734 case SK_YUKON_LITE: 2735 case SK_YUKON_LP: 2736 sk_init_yukon(sc_if); 2737 break; 2738 } 2739 if ((rc = mii_mediachg(mii)) == ENXIO) 2740 rc = 0; 2741 else if (rc != 0) 2742 goto out; 2743 2744 if (sc->sk_type == SK_GENESIS) { 2745 /* Configure MAC FIFOs */ 2746 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2747 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2748 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2749 2750 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2751 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2752 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2753 } 2754 2755 /* Configure transmit arbiter(s) */ 2756 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2757 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2758 2759 /* Configure RAMbuffers */ 2760 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2761 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2762 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2763 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2764 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2765 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2766 2767 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2768 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2769 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2770 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2771 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2772 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2773 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2774 2775 /* Configure BMUs */ 2776 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2777 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2778 SK_RX_RING_ADDR(sc_if, 0)); 2779 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2780 2781 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2782 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2783 SK_TX_RING_ADDR(sc_if, 0)); 2784 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2785 2786 /* Init descriptors */ 2787 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2788 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2789 "memory for rx buffers\n"); 2790 sk_stop(ifp,0); 2791 splx(s); 2792 return ENOBUFS; 2793 } 2794 2795 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2796 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2797 "memory for tx buffers\n"); 2798 sk_stop(ifp,0); 2799 splx(s); 2800 return ENOBUFS; 2801 } 2802 2803 /* Set interrupt moderation if changed via sysctl. */ 2804 switch (sc->sk_type) { 2805 case SK_GENESIS: 2806 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2807 break; 2808 case SK_YUKON_EC: 2809 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2810 break; 2811 default: 2812 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2813 } 2814 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2815 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2816 sk_win_write_4(sc, SK_IMTIMERINIT, 2817 SK_IM_USECS(sc->sk_int_mod)); 2818 aprint_verbose_dev(sc->sk_dev, 2819 "interrupt moderation is %d us\n", sc->sk_int_mod); 2820 } 2821 2822 /* Configure interrupt handling */ 2823 CSR_READ_4(sc, SK_ISSR); 2824 if (sc_if->sk_port == SK_PORT_A) 2825 sc->sk_intrmask |= SK_INTRS1; 2826 else 2827 sc->sk_intrmask |= SK_INTRS2; 2828 2829 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2830 2831 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2832 2833 /* Start BMUs. */ 2834 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2835 2836 if (sc->sk_type == SK_GENESIS) { 2837 /* Enable XMACs TX and RX state machines */ 2838 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2839 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2840 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2841 } 2842 2843 if (SK_YUKON_FAMILY(sc->sk_type)) { 2844 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2845 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2846 #if 0 2847 /* XXX disable 100Mbps and full duplex mode? */ 2848 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2849 #endif 2850 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2851 } 2852 2853 2854 ifp->if_flags |= IFF_RUNNING; 2855 ifp->if_flags &= ~IFF_OACTIVE; 2856 2857 out: 2858 splx(s); 2859 return rc; 2860 } 2861 2862 void 2863 sk_stop(struct ifnet *ifp, int disable) 2864 { 2865 struct sk_if_softc *sc_if = ifp->if_softc; 2866 struct sk_softc *sc = sc_if->sk_softc; 2867 int i; 2868 2869 DPRINTFN(1, ("sk_stop\n")); 2870 2871 callout_stop(&sc_if->sk_tick_ch); 2872 2873 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2874 u_int32_t val; 2875 2876 /* Put PHY back into reset. */ 2877 val = sk_win_read_4(sc, SK_GPIO); 2878 if (sc_if->sk_port == SK_PORT_A) { 2879 val |= SK_GPIO_DIR0; 2880 val &= ~SK_GPIO_DAT0; 2881 } else { 2882 val |= SK_GPIO_DIR2; 2883 val &= ~SK_GPIO_DAT2; 2884 } 2885 sk_win_write_4(sc, SK_GPIO, val); 2886 } 2887 2888 /* Turn off various components of this interface. */ 2889 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2890 switch (sc->sk_type) { 2891 case SK_GENESIS: 2892 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2893 SK_TXMACCTL_XMAC_RESET); 2894 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2895 break; 2896 case SK_YUKON: 2897 case SK_YUKON_LITE: 2898 case SK_YUKON_LP: 2899 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2900 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2901 break; 2902 } 2903 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2904 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2905 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2906 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2907 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2908 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2909 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2910 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2911 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2912 2913 /* Disable interrupts */ 2914 if (sc_if->sk_port == SK_PORT_A) 2915 sc->sk_intrmask &= ~SK_INTRS1; 2916 else 2917 sc->sk_intrmask &= ~SK_INTRS2; 2918 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2919 2920 SK_XM_READ_2(sc_if, XM_ISR); 2921 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2922 2923 /* Free RX and TX mbufs still in the queues. */ 2924 for (i = 0; i < SK_RX_RING_CNT; i++) { 2925 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2926 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2927 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2928 } 2929 } 2930 2931 for (i = 0; i < SK_TX_RING_CNT; i++) { 2932 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2933 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2934 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2935 } 2936 } 2937 2938 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2939 } 2940 2941 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 2942 skc_probe, skc_attach, NULL, NULL); 2943 2944 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 2945 sk_probe, sk_attach, NULL, NULL); 2946 2947 #ifdef SK_DEBUG 2948 void 2949 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2950 { 2951 #define DESC_PRINT(X) \ 2952 if (X) \ 2953 printf("txdesc[%d]." #X "=%#x\n", \ 2954 idx, X); 2955 2956 DESC_PRINT(le32toh(desc->sk_ctl)); 2957 DESC_PRINT(le32toh(desc->sk_next)); 2958 DESC_PRINT(le32toh(desc->sk_data_lo)); 2959 DESC_PRINT(le32toh(desc->sk_data_hi)); 2960 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 2961 DESC_PRINT(le16toh(desc->sk_rsvd0)); 2962 DESC_PRINT(le16toh(desc->sk_csum_startval)); 2963 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 2964 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 2965 DESC_PRINT(le16toh(desc->sk_rsvd1)); 2966 #undef PRINT 2967 } 2968 2969 void 2970 sk_dump_bytes(const char *data, int len) 2971 { 2972 int c, i, j; 2973 2974 for (i = 0; i < len; i += 16) { 2975 printf("%08x ", i); 2976 c = len - i; 2977 if (c > 16) c = 16; 2978 2979 for (j = 0; j < c; j++) { 2980 printf("%02x ", data[i + j] & 0xff); 2981 if ((j & 0xf) == 7 && j > 0) 2982 printf(" "); 2983 } 2984 2985 for (; j < 16; j++) 2986 printf(" "); 2987 printf(" "); 2988 2989 for (j = 0; j < c; j++) { 2990 int ch = data[i + j] & 0xff; 2991 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2992 } 2993 2994 printf("\n"); 2995 2996 if (c < 16) 2997 break; 2998 } 2999 } 3000 3001 void 3002 sk_dump_mbuf(struct mbuf *m) 3003 { 3004 int count = m->m_pkthdr.len; 3005 3006 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3007 3008 while (count > 0 && m) { 3009 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3010 m, m->m_data, m->m_len); 3011 sk_dump_bytes(mtod(m, char *), m->m_len); 3012 3013 count -= m->m_len; 3014 m = m->m_next; 3015 } 3016 } 3017 #endif 3018 3019 static int 3020 sk_sysctl_handler(SYSCTLFN_ARGS) 3021 { 3022 int error, t; 3023 struct sysctlnode node; 3024 struct sk_softc *sc; 3025 3026 node = *rnode; 3027 sc = node.sysctl_data; 3028 t = sc->sk_int_mod; 3029 node.sysctl_data = &t; 3030 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3031 if (error || newp == NULL) 3032 return error; 3033 3034 if (t < SK_IM_MIN || t > SK_IM_MAX) 3035 return EINVAL; 3036 3037 /* update the softc with sysctl-changed value, and mark 3038 for hardware update */ 3039 sc->sk_int_mod = t; 3040 sc->sk_int_mod_pending = 1; 3041 return 0; 3042 } 3043 3044 /* 3045 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3046 * set up in skc_attach() 3047 */ 3048 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3049 { 3050 int rc; 3051 const struct sysctlnode *node; 3052 3053 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3054 0, CTLTYPE_NODE, "hw", NULL, 3055 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3056 goto err; 3057 } 3058 3059 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3060 0, CTLTYPE_NODE, "sk", 3061 SYSCTL_DESCR("sk interface controls"), 3062 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3063 goto err; 3064 } 3065 3066 sk_root_num = node->sysctl_num; 3067 return; 3068 3069 err: 3070 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3071 } 3072
Indexes created Tue Sep 23 07:09:52 GMT 2025