if_sk.c revision 1.66
1 /* $NetBSD: if_sk.c,v 1.66 2010/04/05 07:20:27 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.66 2010/04/05 07:20:27 joerg Exp $"); 119 120 #include "rnd.h" 121 122 #include <sys/param.h> 123 #include <sys/systm.h> 124 #include <sys/sockio.h> 125 #include <sys/mbuf.h> 126 #include <sys/malloc.h> 127 #include <sys/mutex.h> 128 #include <sys/kernel.h> 129 #include <sys/socket.h> 130 #include <sys/device.h> 131 #include <sys/queue.h> 132 #include <sys/callout.h> 133 #include <sys/sysctl.h> 134 #include <sys/endian.h> 135 136 #include <net/if.h> 137 #include <net/if_dl.h> 138 #include <net/if_types.h> 139 140 #include <net/if_media.h> 141 142 #include <net/bpf.h> 143 #if NRND > 0 144 #include <sys/rnd.h> 145 #endif 146 147 #include <dev/mii/mii.h> 148 #include <dev/mii/miivar.h> 149 #include <dev/mii/brgphyreg.h> 150 151 #include <dev/pci/pcireg.h> 152 #include <dev/pci/pcivar.h> 153 #include <dev/pci/pcidevs.h> 154 155 /* #define SK_USEIOSPACE */ 156 157 #include <dev/pci/if_skreg.h> 158 #include <dev/pci/if_skvar.h> 159 160 int skc_probe(device_t, cfdata_t, void *); 161 void skc_attach(device_t, device_t, void *aux); 162 int sk_probe(device_t, cfdata_t, void *); 163 void sk_attach(device_t, device_t, void *aux); 164 int skcprint(void *, const char *); 165 int sk_intr(void *); 166 void sk_intr_bcom(struct sk_if_softc *); 167 void sk_intr_xmac(struct sk_if_softc *); 168 void sk_intr_yukon(struct sk_if_softc *); 169 void sk_rxeof(struct sk_if_softc *); 170 void sk_txeof(struct sk_if_softc *); 171 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 172 void sk_start(struct ifnet *); 173 int sk_ioctl(struct ifnet *, u_long, void *); 174 int sk_init(struct ifnet *); 175 void sk_init_xmac(struct sk_if_softc *); 176 void sk_init_yukon(struct sk_if_softc *); 177 void sk_stop(struct ifnet *, int); 178 void sk_watchdog(struct ifnet *); 179 void sk_shutdown(void *); 180 int sk_ifmedia_upd(struct ifnet *); 181 void sk_reset(struct sk_softc *); 182 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 183 int sk_alloc_jumbo_mem(struct sk_if_softc *); 184 void sk_free_jumbo_mem(struct sk_if_softc *); 185 void *sk_jalloc(struct sk_if_softc *); 186 void sk_jfree(struct mbuf *, void *, size_t, void *); 187 int sk_init_rx_ring(struct sk_if_softc *); 188 int sk_init_tx_ring(struct sk_if_softc *); 189 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 190 void sk_vpd_read_res(struct sk_softc *, 191 struct vpd_res *, int); 192 void sk_vpd_read(struct sk_softc *); 193 194 void sk_update_int_mod(struct sk_softc *); 195 196 int sk_xmac_miibus_readreg(device_t, int, int); 197 void sk_xmac_miibus_writereg(device_t, int, int, int); 198 void sk_xmac_miibus_statchg(device_t); 199 200 int sk_marv_miibus_readreg(device_t, int, int); 201 void sk_marv_miibus_writereg(device_t, int, int, int); 202 void sk_marv_miibus_statchg(device_t); 203 204 u_int32_t sk_xmac_hash(void *); 205 u_int32_t sk_yukon_hash(void *); 206 void sk_setfilt(struct sk_if_softc *, void *, int); 207 void sk_setmulti(struct sk_if_softc *); 208 void sk_tick(void *); 209 210 static bool skc_suspend(device_t, const pmf_qual_t *); 211 static bool skc_resume(device_t, const pmf_qual_t *); 212 static bool sk_resume(device_t dv, const pmf_qual_t *); 213 214 /* #define SK_DEBUG 2 */ 215 #ifdef SK_DEBUG 216 #define DPRINTF(x) if (skdebug) printf x 217 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 218 int skdebug = SK_DEBUG; 219 220 void sk_dump_txdesc(struct sk_tx_desc *, int); 221 void sk_dump_mbuf(struct mbuf *); 222 void sk_dump_bytes(const char *, int); 223 #else 224 #define DPRINTF(x) 225 #define DPRINTFN(n,x) 226 #endif 227 228 static int sk_sysctl_handler(SYSCTLFN_PROTO); 229 static int sk_root_num; 230 231 /* supported device vendors */ 232 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 233 static const struct sk_product { 234 pci_vendor_id_t sk_vendor; 235 pci_product_id_t sk_product; 236 } sk_products[] = { 237 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 238 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 239 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 240 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 241 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 242 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 243 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 244 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 245 { 0, 0, } 246 }; 247 248 #define SK_LINKSYS_EG1032_SUBID 0x00151737 249 250 static inline u_int32_t 251 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 252 { 253 #ifdef SK_USEIOSPACE 254 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 255 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 256 #else 257 return CSR_READ_4(sc, reg); 258 #endif 259 } 260 261 static inline u_int16_t 262 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 263 { 264 #ifdef SK_USEIOSPACE 265 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 266 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 267 #else 268 return CSR_READ_2(sc, reg); 269 #endif 270 } 271 272 static inline u_int8_t 273 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 274 { 275 #ifdef SK_USEIOSPACE 276 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 277 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 278 #else 279 return CSR_READ_1(sc, reg); 280 #endif 281 } 282 283 static inline void 284 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 285 { 286 #ifdef SK_USEIOSPACE 287 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 288 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 289 #else 290 CSR_WRITE_4(sc, reg, x); 291 #endif 292 } 293 294 static inline void 295 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 296 { 297 #ifdef SK_USEIOSPACE 298 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 299 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 300 #else 301 CSR_WRITE_2(sc, reg, x); 302 #endif 303 } 304 305 static inline void 306 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 307 { 308 #ifdef SK_USEIOSPACE 309 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 310 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 311 #else 312 CSR_WRITE_1(sc, reg, x); 313 #endif 314 } 315 316 /* 317 * The VPD EEPROM contains Vital Product Data, as suggested in 318 * the PCI 2.1 specification. The VPD data is separared into areas 319 * denoted by resource IDs. The SysKonnect VPD contains an ID string 320 * resource (the name of the adapter), a read-only area resource 321 * containing various key/data fields and a read/write area which 322 * can be used to store asset management information or log messages. 323 * We read the ID string and read-only into buffers attached to 324 * the controller softc structure for later use. At the moment, 325 * we only use the ID string during sk_attach(). 326 */ 327 u_int8_t 328 sk_vpd_readbyte(struct sk_softc *sc, int addr) 329 { 330 int i; 331 332 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 333 for (i = 0; i < SK_TIMEOUT; i++) { 334 DELAY(1); 335 if (sk_win_read_2(sc, 336 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 337 break; 338 } 339 340 if (i == SK_TIMEOUT) 341 return 0; 342 343 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 344 } 345 346 void 347 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 348 { 349 int i; 350 u_int8_t *ptr; 351 352 ptr = (u_int8_t *)res; 353 for (i = 0; i < sizeof(struct vpd_res); i++) 354 ptr[i] = sk_vpd_readbyte(sc, i + addr); 355 } 356 357 void 358 sk_vpd_read(struct sk_softc *sc) 359 { 360 int pos = 0, i; 361 struct vpd_res res; 362 363 if (sc->sk_vpd_prodname != NULL) 364 free(sc->sk_vpd_prodname, M_DEVBUF); 365 if (sc->sk_vpd_readonly != NULL) 366 free(sc->sk_vpd_readonly, M_DEVBUF); 367 sc->sk_vpd_prodname = NULL; 368 sc->sk_vpd_readonly = NULL; 369 370 sk_vpd_read_res(sc, &res, pos); 371 372 if (res.vr_id != VPD_RES_ID) { 373 aprint_error_dev(sc->sk_dev, 374 "bad VPD resource id: expected %x got %x\n", 375 VPD_RES_ID, res.vr_id); 376 return; 377 } 378 379 pos += sizeof(res); 380 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 381 if (sc->sk_vpd_prodname == NULL) 382 panic("sk_vpd_read"); 383 for (i = 0; i < res.vr_len; i++) 384 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 385 sc->sk_vpd_prodname[i] = '\0'; 386 pos += i; 387 388 sk_vpd_read_res(sc, &res, pos); 389 390 if (res.vr_id != VPD_RES_READ) { 391 aprint_error_dev(sc->sk_dev, 392 "bad VPD resource id: expected %x got %x\n", 393 VPD_RES_READ, res.vr_id); 394 return; 395 } 396 397 pos += sizeof(res); 398 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 399 if (sc->sk_vpd_readonly == NULL) 400 panic("sk_vpd_read"); 401 for (i = 0; i < res.vr_len ; i++) 402 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 403 } 404 405 int 406 sk_xmac_miibus_readreg(device_t dev, int phy, int reg) 407 { 408 struct sk_if_softc *sc_if = device_private(dev); 409 int i; 410 411 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 412 413 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 414 return 0; 415 416 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 417 SK_XM_READ_2(sc_if, XM_PHY_DATA); 418 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 419 for (i = 0; i < SK_TIMEOUT; i++) { 420 DELAY(1); 421 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 422 XM_MMUCMD_PHYDATARDY) 423 break; 424 } 425 426 if (i == SK_TIMEOUT) { 427 aprint_error_dev(sc_if->sk_dev, 428 "phy failed to come ready\n"); 429 return 0; 430 } 431 } 432 DELAY(1); 433 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 434 } 435 436 void 437 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, int val) 438 { 439 struct sk_if_softc *sc_if = device_private(dev); 440 int i; 441 442 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 443 444 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 445 for (i = 0; i < SK_TIMEOUT; i++) { 446 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 447 break; 448 } 449 450 if (i == SK_TIMEOUT) { 451 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 452 return; 453 } 454 455 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 456 for (i = 0; i < SK_TIMEOUT; i++) { 457 DELAY(1); 458 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 459 break; 460 } 461 462 if (i == SK_TIMEOUT) 463 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 464 } 465 466 void 467 sk_xmac_miibus_statchg(device_t dev) 468 { 469 struct sk_if_softc *sc_if = device_private(dev); 470 struct mii_data *mii = &sc_if->sk_mii; 471 472 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 473 474 /* 475 * If this is a GMII PHY, manually set the XMAC's 476 * duplex mode accordingly. 477 */ 478 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 479 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 480 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 481 else 482 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 483 } 484 } 485 486 int 487 sk_marv_miibus_readreg(device_t dev, int phy, int reg) 488 { 489 struct sk_if_softc *sc_if = device_private(dev); 490 u_int16_t val; 491 int i; 492 493 if (phy != 0 || 494 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 495 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 496 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 497 phy, reg)); 498 return 0; 499 } 500 501 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 502 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 503 504 for (i = 0; i < SK_TIMEOUT; i++) { 505 DELAY(1); 506 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 507 if (val & YU_SMICR_READ_VALID) 508 break; 509 } 510 511 if (i == SK_TIMEOUT) { 512 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 513 return 0; 514 } 515 516 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 517 SK_TIMEOUT)); 518 519 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 520 521 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 522 phy, reg, val)); 523 524 return val; 525 } 526 527 void 528 sk_marv_miibus_writereg(device_t dev, int phy, int reg, int val) 529 { 530 struct sk_if_softc *sc_if = device_private(dev); 531 int i; 532 533 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 534 phy, reg, val)); 535 536 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 537 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 538 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 539 540 for (i = 0; i < SK_TIMEOUT; i++) { 541 DELAY(1); 542 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 543 break; 544 } 545 546 if (i == SK_TIMEOUT) 547 printf("%s: phy write timed out\n", 548 device_xname(sc_if->sk_dev)); 549 } 550 551 void 552 sk_marv_miibus_statchg(device_t dev) 553 { 554 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 555 SK_YU_READ_2(((struct sk_if_softc *)device_private(dev)), 556 YUKON_GPCR))); 557 } 558 559 #define SK_HASH_BITS 6 560 561 u_int32_t 562 sk_xmac_hash(void *addr) 563 { 564 u_int32_t crc; 565 566 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 567 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 568 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 569 return crc; 570 } 571 572 u_int32_t 573 sk_yukon_hash(void *addr) 574 { 575 u_int32_t crc; 576 577 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 578 crc &= ((1 << SK_HASH_BITS) - 1); 579 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 580 return crc; 581 } 582 583 void 584 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 585 { 586 char *addr = addrv; 587 int base = XM_RXFILT_ENTRY(slot); 588 589 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 590 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 591 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 592 } 593 594 void 595 sk_setmulti(struct sk_if_softc *sc_if) 596 { 597 struct sk_softc *sc = sc_if->sk_softc; 598 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 599 u_int32_t hashes[2] = { 0, 0 }; 600 int h = 0, i; 601 struct ethercom *ec = &sc_if->sk_ethercom; 602 struct ether_multi *enm; 603 struct ether_multistep step; 604 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 605 606 /* First, zot all the existing filters. */ 607 switch (sc->sk_type) { 608 case SK_GENESIS: 609 for (i = 1; i < XM_RXFILT_MAX; i++) 610 sk_setfilt(sc_if, (void *)&dummy, i); 611 612 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 613 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 614 break; 615 case SK_YUKON: 616 case SK_YUKON_LITE: 617 case SK_YUKON_LP: 618 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 619 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 620 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 621 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 622 break; 623 } 624 625 /* Now program new ones. */ 626 allmulti: 627 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 628 hashes[0] = 0xFFFFFFFF; 629 hashes[1] = 0xFFFFFFFF; 630 } else { 631 i = 1; 632 /* First find the tail of the list. */ 633 ETHER_FIRST_MULTI(step, ec, enm); 634 while (enm != NULL) { 635 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 636 ETHER_ADDR_LEN)) { 637 ifp->if_flags |= IFF_ALLMULTI; 638 goto allmulti; 639 } 640 DPRINTFN(2,("multicast address %s\n", 641 ether_sprintf(enm->enm_addrlo))); 642 /* 643 * Program the first XM_RXFILT_MAX multicast groups 644 * into the perfect filter. For all others, 645 * use the hash table. 646 */ 647 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 648 sk_setfilt(sc_if, enm->enm_addrlo, i); 649 i++; 650 } 651 else { 652 switch (sc->sk_type) { 653 case SK_GENESIS: 654 h = sk_xmac_hash(enm->enm_addrlo); 655 break; 656 case SK_YUKON: 657 case SK_YUKON_LITE: 658 case SK_YUKON_LP: 659 h = sk_yukon_hash(enm->enm_addrlo); 660 break; 661 } 662 if (h < 32) 663 hashes[0] |= (1 << h); 664 else 665 hashes[1] |= (1 << (h - 32)); 666 } 667 668 ETHER_NEXT_MULTI(step, enm); 669 } 670 } 671 672 switch (sc->sk_type) { 673 case SK_GENESIS: 674 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 675 XM_MODE_RX_USE_PERFECT); 676 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 677 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 678 break; 679 case SK_YUKON: 680 case SK_YUKON_LITE: 681 case SK_YUKON_LP: 682 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 683 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 684 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 685 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 686 break; 687 } 688 } 689 690 int 691 sk_init_rx_ring(struct sk_if_softc *sc_if) 692 { 693 struct sk_chain_data *cd = &sc_if->sk_cdata; 694 struct sk_ring_data *rd = sc_if->sk_rdata; 695 int i; 696 697 memset((char *)rd->sk_rx_ring, 0, 698 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 699 700 for (i = 0; i < SK_RX_RING_CNT; i++) { 701 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 702 if (i == (SK_RX_RING_CNT - 1)) { 703 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 704 rd->sk_rx_ring[i].sk_next = 705 htole32(SK_RX_RING_ADDR(sc_if, 0)); 706 } else { 707 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 708 rd->sk_rx_ring[i].sk_next = 709 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 710 } 711 } 712 713 for (i = 0; i < SK_RX_RING_CNT; i++) { 714 if (sk_newbuf(sc_if, i, NULL, 715 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 716 aprint_error_dev(sc_if->sk_dev, 717 "failed alloc of %dth mbuf\n", i); 718 return ENOBUFS; 719 } 720 } 721 sc_if->sk_cdata.sk_rx_prod = 0; 722 sc_if->sk_cdata.sk_rx_cons = 0; 723 724 return 0; 725 } 726 727 int 728 sk_init_tx_ring(struct sk_if_softc *sc_if) 729 { 730 struct sk_chain_data *cd = &sc_if->sk_cdata; 731 struct sk_ring_data *rd = sc_if->sk_rdata; 732 int i; 733 734 memset(sc_if->sk_rdata->sk_tx_ring, 0, 735 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 736 737 for (i = 0; i < SK_TX_RING_CNT; i++) { 738 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 739 if (i == (SK_TX_RING_CNT - 1)) { 740 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 741 rd->sk_tx_ring[i].sk_next = 742 htole32(SK_TX_RING_ADDR(sc_if, 0)); 743 } else { 744 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 745 rd->sk_tx_ring[i].sk_next = 746 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 747 } 748 } 749 750 sc_if->sk_cdata.sk_tx_prod = 0; 751 sc_if->sk_cdata.sk_tx_cons = 0; 752 sc_if->sk_cdata.sk_tx_cnt = 0; 753 754 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 755 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 756 757 return 0; 758 } 759 760 int 761 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 762 bus_dmamap_t dmamap) 763 { 764 struct mbuf *m_new = NULL; 765 struct sk_chain *c; 766 struct sk_rx_desc *r; 767 768 if (m == NULL) { 769 void *buf = NULL; 770 771 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 772 if (m_new == NULL) { 773 aprint_error_dev(sc_if->sk_dev, 774 "no memory for rx list -- packet dropped!\n"); 775 return ENOBUFS; 776 } 777 778 /* Allocate the jumbo buffer */ 779 buf = sk_jalloc(sc_if); 780 if (buf == NULL) { 781 m_freem(m_new); 782 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 783 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 784 return ENOBUFS; 785 } 786 787 /* Attach the buffer to the mbuf */ 788 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 789 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 790 791 } else { 792 /* 793 * We're re-using a previously allocated mbuf; 794 * be sure to re-init pointers and lengths to 795 * default values. 796 */ 797 m_new = m; 798 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 799 m_new->m_data = m_new->m_ext.ext_buf; 800 } 801 m_adj(m_new, ETHER_ALIGN); 802 803 c = &sc_if->sk_cdata.sk_rx_chain[i]; 804 r = c->sk_desc; 805 c->sk_mbuf = m_new; 806 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 807 (((vaddr_t)m_new->m_data 808 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 809 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 810 811 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 812 813 return 0; 814 } 815 816 /* 817 * Memory management for jumbo frames. 818 */ 819 820 int 821 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 822 { 823 struct sk_softc *sc = sc_if->sk_softc; 824 char *ptr, *kva; 825 bus_dma_segment_t seg; 826 int i, rseg, state, error; 827 struct sk_jpool_entry *entry; 828 829 state = error = 0; 830 831 /* Grab a big chunk o' storage. */ 832 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 833 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 834 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 835 return ENOBUFS; 836 } 837 838 state = 1; 839 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 840 BUS_DMA_NOWAIT)) { 841 aprint_error_dev(sc->sk_dev, 842 "can't map dma buffers (%d bytes)\n", 843 SK_JMEM); 844 error = ENOBUFS; 845 goto out; 846 } 847 848 state = 2; 849 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 850 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 851 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 852 error = ENOBUFS; 853 goto out; 854 } 855 856 state = 3; 857 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 858 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 859 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 860 error = ENOBUFS; 861 goto out; 862 } 863 864 state = 4; 865 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 866 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 867 868 LIST_INIT(&sc_if->sk_jfree_listhead); 869 LIST_INIT(&sc_if->sk_jinuse_listhead); 870 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 871 872 /* 873 * Now divide it up into 9K pieces and save the addresses 874 * in an array. 875 */ 876 ptr = sc_if->sk_cdata.sk_jumbo_buf; 877 for (i = 0; i < SK_JSLOTS; i++) { 878 sc_if->sk_cdata.sk_jslots[i] = ptr; 879 ptr += SK_JLEN; 880 entry = malloc(sizeof(struct sk_jpool_entry), 881 M_DEVBUF, M_NOWAIT); 882 if (entry == NULL) { 883 aprint_error_dev(sc->sk_dev, 884 "no memory for jumbo buffer queue!\n"); 885 error = ENOBUFS; 886 goto out; 887 } 888 entry->slot = i; 889 if (i) 890 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 891 entry, jpool_entries); 892 else 893 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 894 entry, jpool_entries); 895 } 896 out: 897 if (error != 0) { 898 switch (state) { 899 case 4: 900 bus_dmamap_unload(sc->sc_dmatag, 901 sc_if->sk_cdata.sk_rx_jumbo_map); 902 case 3: 903 bus_dmamap_destroy(sc->sc_dmatag, 904 sc_if->sk_cdata.sk_rx_jumbo_map); 905 case 2: 906 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 907 case 1: 908 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 909 break; 910 default: 911 break; 912 } 913 } 914 915 return error; 916 } 917 918 /* 919 * Allocate a jumbo buffer. 920 */ 921 void * 922 sk_jalloc(struct sk_if_softc *sc_if) 923 { 924 struct sk_jpool_entry *entry; 925 926 mutex_enter(&sc_if->sk_jpool_mtx); 927 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 928 929 if (entry == NULL) { 930 mutex_exit(&sc_if->sk_jpool_mtx); 931 return NULL; 932 } 933 934 LIST_REMOVE(entry, jpool_entries); 935 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 936 mutex_exit(&sc_if->sk_jpool_mtx); 937 return sc_if->sk_cdata.sk_jslots[entry->slot]; 938 } 939 940 /* 941 * Release a jumbo buffer. 942 */ 943 void 944 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 945 { 946 struct sk_jpool_entry *entry; 947 struct sk_if_softc *sc; 948 int i; 949 950 /* Extract the softc struct pointer. */ 951 sc = (struct sk_if_softc *)arg; 952 953 if (sc == NULL) 954 panic("sk_jfree: can't find softc pointer!"); 955 956 /* calculate the slot this buffer belongs to */ 957 958 i = ((vaddr_t)buf 959 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 960 961 if ((i < 0) || (i >= SK_JSLOTS)) 962 panic("sk_jfree: asked to free buffer that we don't manage!"); 963 964 mutex_enter(&sc->sk_jpool_mtx); 965 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 966 if (entry == NULL) 967 panic("sk_jfree: buffer not in use!"); 968 entry->slot = i; 969 LIST_REMOVE(entry, jpool_entries); 970 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 971 mutex_exit(&sc->sk_jpool_mtx); 972 973 if (__predict_true(m != NULL)) 974 pool_cache_put(mb_cache, m); 975 } 976 977 /* 978 * Set media options. 979 */ 980 int 981 sk_ifmedia_upd(struct ifnet *ifp) 982 { 983 struct sk_if_softc *sc_if = ifp->if_softc; 984 int rc; 985 986 (void) sk_init(ifp); 987 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 988 return 0; 989 return rc; 990 } 991 992 int 993 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 994 { 995 struct sk_if_softc *sc_if = ifp->if_softc; 996 struct sk_softc *sc = sc_if->sk_softc; 997 int s, error = 0; 998 999 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1000 1001 s = splnet(); 1002 1003 switch (command) { 1004 1005 case SIOCSIFFLAGS: 1006 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1007 if ((error = ifioctl_common(ifp, command, data)) != 0) 1008 break; 1009 if (ifp->if_flags & IFF_UP) { 1010 if (ifp->if_flags & IFF_RUNNING && 1011 ifp->if_flags & IFF_PROMISC && 1012 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1013 switch (sc->sk_type) { 1014 case SK_GENESIS: 1015 SK_XM_SETBIT_4(sc_if, XM_MODE, 1016 XM_MODE_RX_PROMISC); 1017 break; 1018 case SK_YUKON: 1019 case SK_YUKON_LITE: 1020 case SK_YUKON_LP: 1021 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1022 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1023 break; 1024 } 1025 sk_setmulti(sc_if); 1026 } else if (ifp->if_flags & IFF_RUNNING && 1027 !(ifp->if_flags & IFF_PROMISC) && 1028 sc_if->sk_if_flags & IFF_PROMISC) { 1029 switch (sc->sk_type) { 1030 case SK_GENESIS: 1031 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1032 XM_MODE_RX_PROMISC); 1033 break; 1034 case SK_YUKON: 1035 case SK_YUKON_LITE: 1036 case SK_YUKON_LP: 1037 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1038 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1039 break; 1040 } 1041 1042 sk_setmulti(sc_if); 1043 } else 1044 (void) sk_init(ifp); 1045 } else { 1046 if (ifp->if_flags & IFF_RUNNING) 1047 sk_stop(ifp,0); 1048 } 1049 sc_if->sk_if_flags = ifp->if_flags; 1050 error = 0; 1051 break; 1052 1053 default: 1054 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1055 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1056 break; 1057 1058 error = 0; 1059 1060 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1061 ; 1062 else if (ifp->if_flags & IFF_RUNNING) { 1063 sk_setmulti(sc_if); 1064 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1065 } 1066 break; 1067 } 1068 1069 splx(s); 1070 return error; 1071 } 1072 1073 void 1074 sk_update_int_mod(struct sk_softc *sc) 1075 { 1076 u_int32_t imtimer_ticks; 1077 1078 /* 1079 * Configure interrupt moderation. The moderation timer 1080 * defers interrupts specified in the interrupt moderation 1081 * timer mask based on the timeout specified in the interrupt 1082 * moderation timer init register. Each bit in the timer 1083 * register represents one tick, so to specify a timeout in 1084 * microseconds, we have to multiply by the correct number of 1085 * ticks-per-microsecond. 1086 */ 1087 switch (sc->sk_type) { 1088 case SK_GENESIS: 1089 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1090 break; 1091 case SK_YUKON_EC: 1092 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1093 break; 1094 default: 1095 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1096 } 1097 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1098 sc->sk_int_mod); 1099 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1100 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1101 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1102 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1103 sc->sk_int_mod_pending = 0; 1104 } 1105 1106 /* 1107 * Lookup: Check the PCI vendor and device, and return a pointer to 1108 * The structure if the IDs match against our list. 1109 */ 1110 1111 static const struct sk_product * 1112 sk_lookup(const struct pci_attach_args *pa) 1113 { 1114 const struct sk_product *psk; 1115 1116 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1117 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1118 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1119 return psk; 1120 } 1121 return NULL; 1122 } 1123 1124 /* 1125 * Probe for a SysKonnect GEnesis chip. 1126 */ 1127 1128 int 1129 skc_probe(device_t parent, cfdata_t match, void *aux) 1130 { 1131 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1132 const struct sk_product *psk; 1133 pcireg_t subid; 1134 1135 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1136 1137 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1138 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1139 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1140 subid == SK_LINKSYS_EG1032_SUBID) 1141 return 1; 1142 1143 if ((psk = sk_lookup(pa))) { 1144 return 1; 1145 } 1146 return 0; 1147 } 1148 1149 /* 1150 * Force the GEnesis into reset, then bring it out of reset. 1151 */ 1152 void sk_reset(struct sk_softc *sc) 1153 { 1154 DPRINTFN(2, ("sk_reset\n")); 1155 1156 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1157 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1158 if (SK_YUKON_FAMILY(sc->sk_type)) 1159 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1160 1161 DELAY(1000); 1162 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1163 DELAY(2); 1164 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1165 if (SK_YUKON_FAMILY(sc->sk_type)) 1166 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1167 1168 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1169 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1170 CSR_READ_2(sc, SK_LINK_CTRL))); 1171 1172 if (sc->sk_type == SK_GENESIS) { 1173 /* Configure packet arbiter */ 1174 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1175 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1176 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1177 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1178 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1179 } 1180 1181 /* Enable RAM interface */ 1182 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1183 1184 sk_update_int_mod(sc); 1185 } 1186 1187 int 1188 sk_probe(device_t parent, cfdata_t match, void *aux) 1189 { 1190 struct skc_attach_args *sa = aux; 1191 1192 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1193 return 0; 1194 1195 return 1; 1196 } 1197 1198 /* 1199 * Each XMAC chip is attached as a separate logical IP interface. 1200 * Single port cards will have only one logical interface of course. 1201 */ 1202 void 1203 sk_attach(device_t parent, device_t self, void *aux) 1204 { 1205 struct sk_if_softc *sc_if = device_private(self); 1206 struct sk_softc *sc = device_private(parent); 1207 struct skc_attach_args *sa = aux; 1208 struct sk_txmap_entry *entry; 1209 struct ifnet *ifp; 1210 bus_dma_segment_t seg; 1211 bus_dmamap_t dmamap; 1212 void *kva; 1213 int i, rseg; 1214 int mii_flags = 0; 1215 1216 aprint_naive("\n"); 1217 1218 sc_if->sk_dev = self; 1219 sc_if->sk_port = sa->skc_port; 1220 sc_if->sk_softc = sc; 1221 sc->sk_if[sa->skc_port] = sc_if; 1222 1223 if (sa->skc_port == SK_PORT_A) 1224 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1225 if (sa->skc_port == SK_PORT_B) 1226 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1227 1228 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1229 1230 /* 1231 * Get station address for this interface. Note that 1232 * dual port cards actually come with three station 1233 * addresses: one for each port, plus an extra. The 1234 * extra one is used by the SysKonnect driver software 1235 * as a 'virtual' station address for when both ports 1236 * are operating in failover mode. Currently we don't 1237 * use this extra address. 1238 */ 1239 for (i = 0; i < ETHER_ADDR_LEN; i++) 1240 sc_if->sk_enaddr[i] = 1241 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1242 1243 1244 aprint_normal(": Ethernet address %s\n", 1245 ether_sprintf(sc_if->sk_enaddr)); 1246 1247 /* 1248 * Set up RAM buffer addresses. The NIC will have a certain 1249 * amount of SRAM on it, somewhere between 512K and 2MB. We 1250 * need to divide this up a) between the transmitter and 1251 * receiver and b) between the two XMACs, if this is a 1252 * dual port NIC. Our algorithm is to divide up the memory 1253 * evenly so that everyone gets a fair share. 1254 */ 1255 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1256 u_int32_t chunk, val; 1257 1258 chunk = sc->sk_ramsize / 2; 1259 val = sc->sk_rboff / sizeof(u_int64_t); 1260 sc_if->sk_rx_ramstart = val; 1261 val += (chunk / sizeof(u_int64_t)); 1262 sc_if->sk_rx_ramend = val - 1; 1263 sc_if->sk_tx_ramstart = val; 1264 val += (chunk / sizeof(u_int64_t)); 1265 sc_if->sk_tx_ramend = val - 1; 1266 } else { 1267 u_int32_t chunk, val; 1268 1269 chunk = sc->sk_ramsize / 4; 1270 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1271 sizeof(u_int64_t); 1272 sc_if->sk_rx_ramstart = val; 1273 val += (chunk / sizeof(u_int64_t)); 1274 sc_if->sk_rx_ramend = val - 1; 1275 sc_if->sk_tx_ramstart = val; 1276 val += (chunk / sizeof(u_int64_t)); 1277 sc_if->sk_tx_ramend = val - 1; 1278 } 1279 1280 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1281 " tx_ramstart=%#x tx_ramend=%#x\n", 1282 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1283 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1284 1285 /* Read and save PHY type and set PHY address */ 1286 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1287 switch (sc_if->sk_phytype) { 1288 case SK_PHYTYPE_XMAC: 1289 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1290 break; 1291 case SK_PHYTYPE_BCOM: 1292 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1293 break; 1294 case SK_PHYTYPE_MARV_COPPER: 1295 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1296 break; 1297 default: 1298 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1299 sc_if->sk_phytype); 1300 return; 1301 } 1302 1303 /* Allocate the descriptor queues. */ 1304 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1305 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1306 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1307 goto fail; 1308 } 1309 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1310 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1311 aprint_error_dev(sc_if->sk_dev, 1312 "can't map dma buffers (%lu bytes)\n", 1313 (u_long) sizeof(struct sk_ring_data)); 1314 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1315 goto fail; 1316 } 1317 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1318 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1319 &sc_if->sk_ring_map)) { 1320 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1321 bus_dmamem_unmap(sc->sc_dmatag, kva, 1322 sizeof(struct sk_ring_data)); 1323 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1324 goto fail; 1325 } 1326 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1327 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1328 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1329 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1330 bus_dmamem_unmap(sc->sc_dmatag, kva, 1331 sizeof(struct sk_ring_data)); 1332 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1333 goto fail; 1334 } 1335 1336 for (i = 0; i < SK_RX_RING_CNT; i++) 1337 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1338 1339 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1340 for (i = 0; i < SK_TX_RING_CNT; i++) { 1341 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1342 1343 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1344 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1345 aprint_error_dev(sc_if->sk_dev, 1346 "Can't create TX dmamap\n"); 1347 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1348 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1349 bus_dmamem_unmap(sc->sc_dmatag, kva, 1350 sizeof(struct sk_ring_data)); 1351 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1352 goto fail; 1353 } 1354 1355 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1356 if (!entry) { 1357 aprint_error_dev(sc_if->sk_dev, 1358 "Can't alloc txmap entry\n"); 1359 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1360 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1361 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1362 bus_dmamem_unmap(sc->sc_dmatag, kva, 1363 sizeof(struct sk_ring_data)); 1364 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1365 goto fail; 1366 } 1367 entry->dmamap = dmamap; 1368 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1369 } 1370 1371 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1372 memset(sc_if->sk_rdata, 0, sizeof(struct sk_ring_data)); 1373 1374 ifp = &sc_if->sk_ethercom.ec_if; 1375 /* Try to allocate memory for jumbo buffers. */ 1376 if (sk_alloc_jumbo_mem(sc_if)) { 1377 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1378 goto fail; 1379 } 1380 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1381 | ETHERCAP_JUMBO_MTU; 1382 1383 ifp->if_softc = sc_if; 1384 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1385 ifp->if_ioctl = sk_ioctl; 1386 ifp->if_start = sk_start; 1387 ifp->if_stop = sk_stop; 1388 ifp->if_init = sk_init; 1389 ifp->if_watchdog = sk_watchdog; 1390 ifp->if_capabilities = 0; 1391 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1392 IFQ_SET_READY(&ifp->if_snd); 1393 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1394 1395 /* 1396 * Do miibus setup. 1397 */ 1398 switch (sc->sk_type) { 1399 case SK_GENESIS: 1400 sk_init_xmac(sc_if); 1401 break; 1402 case SK_YUKON: 1403 case SK_YUKON_LITE: 1404 case SK_YUKON_LP: 1405 sk_init_yukon(sc_if); 1406 break; 1407 default: 1408 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1409 sc->sk_type); 1410 goto fail; 1411 } 1412 1413 DPRINTFN(2, ("sk_attach: 1\n")); 1414 1415 sc_if->sk_mii.mii_ifp = ifp; 1416 switch (sc->sk_type) { 1417 case SK_GENESIS: 1418 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1419 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1420 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1421 break; 1422 case SK_YUKON: 1423 case SK_YUKON_LITE: 1424 case SK_YUKON_LP: 1425 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1426 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1427 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1428 mii_flags = MIIF_DOPAUSE; 1429 break; 1430 } 1431 1432 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1433 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1434 sk_ifmedia_upd, ether_mediastatus); 1435 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1436 MII_OFFSET_ANY, mii_flags); 1437 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1438 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1439 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1440 0, NULL); 1441 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1442 } else 1443 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1444 1445 callout_init(&sc_if->sk_tick_ch, 0); 1446 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1447 1448 DPRINTFN(2, ("sk_attach: 1\n")); 1449 1450 /* 1451 * Call MI attach routines. 1452 */ 1453 if_attach(ifp); 1454 1455 ether_ifattach(ifp, sc_if->sk_enaddr); 1456 1457 #if NRND > 0 1458 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1459 RND_TYPE_NET, 0); 1460 #endif 1461 1462 if (pmf_device_register(self, NULL, sk_resume)) 1463 pmf_class_network_register(self, ifp); 1464 else 1465 aprint_error_dev(self, "couldn't establish power handler\n"); 1466 1467 DPRINTFN(2, ("sk_attach: end\n")); 1468 1469 return; 1470 1471 fail: 1472 sc->sk_if[sa->skc_port] = NULL; 1473 } 1474 1475 int 1476 skcprint(void *aux, const char *pnp) 1477 { 1478 struct skc_attach_args *sa = aux; 1479 1480 if (pnp) 1481 aprint_normal("sk port %c at %s", 1482 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1483 else 1484 aprint_normal(" port %c", 1485 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1486 return UNCONF; 1487 } 1488 1489 /* 1490 * Attach the interface. Allocate softc structures, do ifmedia 1491 * setup and ethernet/BPF attach. 1492 */ 1493 void 1494 skc_attach(device_t parent, device_t self, void *aux) 1495 { 1496 struct sk_softc *sc = device_private(self); 1497 struct pci_attach_args *pa = aux; 1498 struct skc_attach_args skca; 1499 pci_chipset_tag_t pc = pa->pa_pc; 1500 #ifndef SK_USEIOSPACE 1501 pcireg_t memtype; 1502 #endif 1503 pci_intr_handle_t ih; 1504 const char *intrstr = NULL; 1505 bus_addr_t iobase; 1506 bus_size_t iosize; 1507 int rc, sk_nodenum; 1508 u_int32_t command; 1509 const char *revstr; 1510 const struct sysctlnode *node; 1511 1512 sc->sk_dev = self; 1513 aprint_naive("\n"); 1514 1515 DPRINTFN(2, ("begin skc_attach\n")); 1516 1517 /* 1518 * Handle power management nonsense. 1519 */ 1520 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1521 1522 if (command == 0x01) { 1523 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1524 if (command & SK_PSTATE_MASK) { 1525 u_int32_t xiobase, membase, irq; 1526 1527 /* Save important PCI config data. */ 1528 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1529 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1530 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1531 1532 /* Reset the power state. */ 1533 aprint_normal_dev(sc->sk_dev, 1534 "chip is in D%d power mode -- setting to D0\n", 1535 command & SK_PSTATE_MASK); 1536 command &= 0xFFFFFFFC; 1537 pci_conf_write(pc, pa->pa_tag, 1538 SK_PCI_PWRMGMTCTRL, command); 1539 1540 /* Restore PCI config data. */ 1541 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1542 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1543 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1544 } 1545 } 1546 1547 /* 1548 * Map control/status registers. 1549 */ 1550 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1551 command |= PCI_COMMAND_IO_ENABLE | 1552 PCI_COMMAND_MEM_ENABLE | 1553 PCI_COMMAND_MASTER_ENABLE; 1554 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1555 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1556 1557 #ifdef SK_USEIOSPACE 1558 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1559 aprint_error(": failed to enable I/O ports!\n"); 1560 return; 1561 } 1562 /* 1563 * Map control/status registers. 1564 */ 1565 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1566 &sc->sk_btag, &sc->sk_bhandle, 1567 &iobase, &iosize)) { 1568 aprint_error(": can't find i/o space\n"); 1569 return; 1570 } 1571 #else 1572 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1573 aprint_error(": failed to enable memory mapping!\n"); 1574 return; 1575 } 1576 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1577 switch (memtype) { 1578 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1579 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1580 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1581 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1582 &iobase, &iosize) == 0) 1583 break; 1584 default: 1585 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1586 return; 1587 } 1588 1589 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, 1590 (u_long)iosize)); 1591 #endif 1592 sc->sc_dmatag = pa->pa_dmat; 1593 1594 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1595 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1596 1597 /* bail out here if chip is not recognized */ 1598 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1599 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1600 goto fail; 1601 } 1602 if (SK_IS_YUKON2(sc)) { 1603 aprint_error_dev(sc->sk_dev, 1604 "Does not support Yukon2--try msk(4).\n"); 1605 goto fail; 1606 } 1607 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1608 1609 /* Allocate interrupt */ 1610 if (pci_intr_map(pa, &ih)) { 1611 aprint_error(": couldn't map interrupt\n"); 1612 goto fail; 1613 } 1614 1615 intrstr = pci_intr_string(pc, ih); 1616 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1617 if (sc->sk_intrhand == NULL) { 1618 aprint_error(": couldn't establish interrupt"); 1619 if (intrstr != NULL) 1620 aprint_error(" at %s", intrstr); 1621 aprint_error("\n"); 1622 goto fail; 1623 } 1624 aprint_normal(": %s\n", intrstr); 1625 1626 /* Reset the adapter. */ 1627 sk_reset(sc); 1628 1629 /* Read and save vital product data from EEPROM. */ 1630 sk_vpd_read(sc); 1631 1632 if (sc->sk_type == SK_GENESIS) { 1633 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1634 /* Read and save RAM size and RAMbuffer offset */ 1635 switch (val) { 1636 case SK_RAMSIZE_512K_64: 1637 sc->sk_ramsize = 0x80000; 1638 sc->sk_rboff = SK_RBOFF_0; 1639 break; 1640 case SK_RAMSIZE_1024K_64: 1641 sc->sk_ramsize = 0x100000; 1642 sc->sk_rboff = SK_RBOFF_80000; 1643 break; 1644 case SK_RAMSIZE_1024K_128: 1645 sc->sk_ramsize = 0x100000; 1646 sc->sk_rboff = SK_RBOFF_0; 1647 break; 1648 case SK_RAMSIZE_2048K_128: 1649 sc->sk_ramsize = 0x200000; 1650 sc->sk_rboff = SK_RBOFF_0; 1651 break; 1652 default: 1653 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1654 val); 1655 goto fail_1; 1656 break; 1657 } 1658 1659 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1660 sc->sk_ramsize, sc->sk_ramsize / 1024, 1661 sc->sk_rboff)); 1662 } else { 1663 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1664 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1665 sc->sk_rboff = SK_RBOFF_0; 1666 1667 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1668 sc->sk_ramsize / 1024, sc->sk_ramsize, 1669 sc->sk_rboff)); 1670 } 1671 1672 /* Read and save physical media type */ 1673 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1674 case SK_PMD_1000BASESX: 1675 sc->sk_pmd = IFM_1000_SX; 1676 break; 1677 case SK_PMD_1000BASELX: 1678 sc->sk_pmd = IFM_1000_LX; 1679 break; 1680 case SK_PMD_1000BASECX: 1681 sc->sk_pmd = IFM_1000_CX; 1682 break; 1683 case SK_PMD_1000BASETX: 1684 case SK_PMD_1000BASETX_ALT: 1685 sc->sk_pmd = IFM_1000_T; 1686 break; 1687 default: 1688 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1689 sk_win_read_1(sc, SK_PMDTYPE)); 1690 goto fail_1; 1691 } 1692 1693 /* determine whether to name it with vpd or just make it up */ 1694 /* Marvell Yukon VPD's can freqently be bogus */ 1695 1696 switch (pa->pa_id) { 1697 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1698 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1699 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1700 case PCI_PRODUCT_3COM_3C940: 1701 case PCI_PRODUCT_DLINK_DGE530T: 1702 case PCI_PRODUCT_DLINK_DGE560T: 1703 case PCI_PRODUCT_DLINK_DGE560T_2: 1704 case PCI_PRODUCT_LINKSYS_EG1032: 1705 case PCI_PRODUCT_LINKSYS_EG1064: 1706 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1707 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1708 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1709 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1710 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1711 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1712 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1713 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1714 sc->sk_name = sc->sk_vpd_prodname; 1715 break; 1716 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1717 /* whoops yukon vpd prodname bears no resemblance to reality */ 1718 switch (sc->sk_type) { 1719 case SK_GENESIS: 1720 sc->sk_name = sc->sk_vpd_prodname; 1721 break; 1722 case SK_YUKON: 1723 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1724 break; 1725 case SK_YUKON_LITE: 1726 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1727 break; 1728 case SK_YUKON_LP: 1729 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1730 break; 1731 default: 1732 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1733 } 1734 1735 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1736 1737 if ( sc->sk_type == SK_YUKON ) { 1738 uint32_t flashaddr; 1739 uint8_t testbyte; 1740 1741 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1742 1743 /* test Flash-Address Register */ 1744 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1745 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1746 1747 if (testbyte != 0) { 1748 /* this is yukon lite Rev. A0 */ 1749 sc->sk_type = SK_YUKON_LITE; 1750 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1751 /* restore Flash-Address Register */ 1752 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1753 } 1754 } 1755 break; 1756 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1757 sc->sk_name = sc->sk_vpd_prodname; 1758 break; 1759 default: 1760 sc->sk_name = "Unknown Marvell"; 1761 } 1762 1763 1764 if ( sc->sk_type == SK_YUKON_LITE ) { 1765 switch (sc->sk_rev) { 1766 case SK_YUKON_LITE_REV_A0: 1767 revstr = "A0"; 1768 break; 1769 case SK_YUKON_LITE_REV_A1: 1770 revstr = "A1"; 1771 break; 1772 case SK_YUKON_LITE_REV_A3: 1773 revstr = "A3"; 1774 break; 1775 default: 1776 revstr = ""; 1777 } 1778 } else { 1779 revstr = ""; 1780 } 1781 1782 /* Announce the product name. */ 1783 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1784 sc->sk_name, revstr, sc->sk_rev); 1785 1786 skca.skc_port = SK_PORT_A; 1787 (void)config_found(sc->sk_dev, &skca, skcprint); 1788 1789 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1790 skca.skc_port = SK_PORT_B; 1791 (void)config_found(sc->sk_dev, &skca, skcprint); 1792 } 1793 1794 /* Turn on the 'driver is loaded' LED. */ 1795 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1796 1797 /* skc sysctl setup */ 1798 1799 sc->sk_int_mod = SK_IM_DEFAULT; 1800 sc->sk_int_mod_pending = 0; 1801 1802 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1803 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1804 SYSCTL_DESCR("skc per-controller controls"), 1805 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1806 CTL_EOL)) != 0) { 1807 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1808 goto fail_1; 1809 } 1810 1811 sk_nodenum = node->sysctl_num; 1812 1813 /* interrupt moderation time in usecs */ 1814 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1815 CTLFLAG_READWRITE, 1816 CTLTYPE_INT, "int_mod", 1817 SYSCTL_DESCR("sk interrupt moderation timer"), 1818 sk_sysctl_handler, 0, sc, 1819 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1820 CTL_EOL)) != 0) { 1821 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1822 goto fail_1; 1823 } 1824 1825 if (!pmf_device_register(self, skc_suspend, skc_resume)) 1826 aprint_error_dev(self, "couldn't establish power handler\n"); 1827 1828 return; 1829 1830 fail_1: 1831 pci_intr_disestablish(pc, sc->sk_intrhand); 1832 fail: 1833 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1834 } 1835 1836 int 1837 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1838 { 1839 struct sk_softc *sc = sc_if->sk_softc; 1840 struct sk_tx_desc *f = NULL; 1841 u_int32_t frag, cur, cnt = 0, sk_ctl; 1842 int i; 1843 struct sk_txmap_entry *entry; 1844 bus_dmamap_t txmap; 1845 1846 DPRINTFN(3, ("sk_encap\n")); 1847 1848 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1849 if (entry == NULL) { 1850 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1851 return ENOBUFS; 1852 } 1853 txmap = entry->dmamap; 1854 1855 cur = frag = *txidx; 1856 1857 #ifdef SK_DEBUG 1858 if (skdebug >= 3) 1859 sk_dump_mbuf(m_head); 1860 #endif 1861 1862 /* 1863 * Start packing the mbufs in this chain into 1864 * the fragment pointers. Stop when we run out 1865 * of fragments or hit the end of the mbuf chain. 1866 */ 1867 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1868 BUS_DMA_NOWAIT)) { 1869 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1870 return ENOBUFS; 1871 } 1872 1873 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1874 1875 /* Sync the DMA map. */ 1876 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1877 BUS_DMASYNC_PREWRITE); 1878 1879 for (i = 0; i < txmap->dm_nsegs; i++) { 1880 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1881 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1882 return ENOBUFS; 1883 } 1884 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1885 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1886 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1887 if (cnt == 0) 1888 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1889 else 1890 sk_ctl |= SK_TXCTL_OWN; 1891 f->sk_ctl = htole32(sk_ctl); 1892 cur = frag; 1893 SK_INC(frag, SK_TX_RING_CNT); 1894 cnt++; 1895 } 1896 1897 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1898 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1899 1900 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1901 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1902 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1903 1904 /* Sync descriptors before handing to chip */ 1905 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1906 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1907 1908 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1909 htole32(SK_TXCTL_OWN); 1910 1911 /* Sync first descriptor to hand it off */ 1912 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1913 1914 sc_if->sk_cdata.sk_tx_cnt += cnt; 1915 1916 #ifdef SK_DEBUG 1917 if (skdebug >= 3) { 1918 struct sk_tx_desc *desc; 1919 u_int32_t idx; 1920 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1921 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1922 sk_dump_txdesc(desc, idx); 1923 } 1924 } 1925 #endif 1926 1927 *txidx = frag; 1928 1929 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1930 1931 return 0; 1932 } 1933 1934 void 1935 sk_start(struct ifnet *ifp) 1936 { 1937 struct sk_if_softc *sc_if = ifp->if_softc; 1938 struct sk_softc *sc = sc_if->sk_softc; 1939 struct mbuf *m_head = NULL; 1940 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1941 int pkts = 0; 1942 1943 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1944 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1945 1946 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1947 IFQ_POLL(&ifp->if_snd, m_head); 1948 if (m_head == NULL) 1949 break; 1950 1951 /* 1952 * Pack the data into the transmit ring. If we 1953 * don't have room, set the OACTIVE flag and wait 1954 * for the NIC to drain the ring. 1955 */ 1956 if (sk_encap(sc_if, m_head, &idx)) { 1957 ifp->if_flags |= IFF_OACTIVE; 1958 break; 1959 } 1960 1961 /* now we are committed to transmit the packet */ 1962 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1963 pkts++; 1964 1965 /* 1966 * If there's a BPF listener, bounce a copy of this frame 1967 * to him. 1968 */ 1969 bpf_mtap(ifp, m_head); 1970 } 1971 if (pkts == 0) 1972 return; 1973 1974 /* Transmit */ 1975 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1976 sc_if->sk_cdata.sk_tx_prod = idx; 1977 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1978 1979 /* Set a timeout in case the chip goes out to lunch. */ 1980 ifp->if_timer = 5; 1981 } 1982 } 1983 1984 1985 void 1986 sk_watchdog(struct ifnet *ifp) 1987 { 1988 struct sk_if_softc *sc_if = ifp->if_softc; 1989 1990 /* 1991 * Reclaim first as there is a possibility of losing Tx completion 1992 * interrupts. 1993 */ 1994 sk_txeof(sc_if); 1995 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 1996 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 1997 1998 ifp->if_oerrors++; 1999 2000 sk_init(ifp); 2001 } 2002 } 2003 2004 void 2005 sk_shutdown(void *v) 2006 { 2007 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2008 struct sk_softc *sc = sc_if->sk_softc; 2009 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2010 2011 DPRINTFN(2, ("sk_shutdown\n")); 2012 sk_stop(ifp,1); 2013 2014 /* Turn off the 'driver is loaded' LED. */ 2015 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2016 2017 /* 2018 * Reset the GEnesis controller. Doing this should also 2019 * assert the resets on the attached XMAC(s). 2020 */ 2021 sk_reset(sc); 2022 } 2023 2024 void 2025 sk_rxeof(struct sk_if_softc *sc_if) 2026 { 2027 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2028 struct mbuf *m; 2029 struct sk_chain *cur_rx; 2030 struct sk_rx_desc *cur_desc; 2031 int i, cur, total_len = 0; 2032 u_int32_t rxstat, sk_ctl; 2033 bus_dmamap_t dmamap; 2034 2035 i = sc_if->sk_cdata.sk_rx_prod; 2036 2037 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2038 2039 for (;;) { 2040 cur = i; 2041 2042 /* Sync the descriptor */ 2043 SK_CDRXSYNC(sc_if, cur, 2044 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2045 2046 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2047 if (sk_ctl & SK_RXCTL_OWN) { 2048 /* Invalidate the descriptor -- it's not ready yet */ 2049 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2050 sc_if->sk_cdata.sk_rx_prod = i; 2051 break; 2052 } 2053 2054 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2055 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2056 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2057 2058 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2059 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2060 2061 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2062 m = cur_rx->sk_mbuf; 2063 cur_rx->sk_mbuf = NULL; 2064 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2065 2066 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2067 2068 SK_INC(i, SK_RX_RING_CNT); 2069 2070 if (rxstat & XM_RXSTAT_ERRFRAME) { 2071 ifp->if_ierrors++; 2072 sk_newbuf(sc_if, cur, m, dmamap); 2073 continue; 2074 } 2075 2076 /* 2077 * Try to allocate a new jumbo buffer. If that 2078 * fails, copy the packet to mbufs and put the 2079 * jumbo buffer back in the ring so it can be 2080 * re-used. If allocating mbufs fails, then we 2081 * have to drop the packet. 2082 */ 2083 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2084 struct mbuf *m0; 2085 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2086 total_len + ETHER_ALIGN, 0, ifp, NULL); 2087 sk_newbuf(sc_if, cur, m, dmamap); 2088 if (m0 == NULL) { 2089 aprint_error_dev(sc_if->sk_dev, "no receive " 2090 "buffers available -- packet dropped!\n"); 2091 ifp->if_ierrors++; 2092 continue; 2093 } 2094 m_adj(m0, ETHER_ALIGN); 2095 m = m0; 2096 } else { 2097 m->m_pkthdr.rcvif = ifp; 2098 m->m_pkthdr.len = m->m_len = total_len; 2099 } 2100 2101 ifp->if_ipackets++; 2102 2103 bpf_mtap(ifp, m); 2104 /* pass it on. */ 2105 (*ifp->if_input)(ifp, m); 2106 } 2107 } 2108 2109 void 2110 sk_txeof(struct sk_if_softc *sc_if) 2111 { 2112 struct sk_softc *sc = sc_if->sk_softc; 2113 struct sk_tx_desc *cur_tx; 2114 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2115 u_int32_t idx, sk_ctl; 2116 struct sk_txmap_entry *entry; 2117 2118 DPRINTFN(3, ("sk_txeof\n")); 2119 2120 /* 2121 * Go through our tx ring and free mbufs for those 2122 * frames that have been sent. 2123 */ 2124 idx = sc_if->sk_cdata.sk_tx_cons; 2125 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2126 SK_CDTXSYNC(sc_if, idx, 1, 2127 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2128 2129 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2130 sk_ctl = le32toh(cur_tx->sk_ctl); 2131 #ifdef SK_DEBUG 2132 if (skdebug >= 3) 2133 sk_dump_txdesc(cur_tx, idx); 2134 #endif 2135 if (sk_ctl & SK_TXCTL_OWN) { 2136 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2137 break; 2138 } 2139 if (sk_ctl & SK_TXCTL_LASTFRAG) 2140 ifp->if_opackets++; 2141 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2142 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2143 2144 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2145 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2146 2147 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2148 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2149 2150 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2151 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2152 link); 2153 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2154 } 2155 sc_if->sk_cdata.sk_tx_cnt--; 2156 SK_INC(idx, SK_TX_RING_CNT); 2157 } 2158 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2159 ifp->if_timer = 0; 2160 else /* nudge chip to keep tx ring moving */ 2161 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2162 2163 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2164 ifp->if_flags &= ~IFF_OACTIVE; 2165 2166 sc_if->sk_cdata.sk_tx_cons = idx; 2167 } 2168 2169 void 2170 sk_tick(void *xsc_if) 2171 { 2172 struct sk_if_softc *sc_if = xsc_if; 2173 struct mii_data *mii = &sc_if->sk_mii; 2174 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2175 int i; 2176 2177 DPRINTFN(3, ("sk_tick\n")); 2178 2179 if (!(ifp->if_flags & IFF_UP)) 2180 return; 2181 2182 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2183 sk_intr_bcom(sc_if); 2184 return; 2185 } 2186 2187 /* 2188 * According to SysKonnect, the correct way to verify that 2189 * the link has come back up is to poll bit 0 of the GPIO 2190 * register three times. This pin has the signal from the 2191 * link sync pin connected to it; if we read the same link 2192 * state 3 times in a row, we know the link is up. 2193 */ 2194 for (i = 0; i < 3; i++) { 2195 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2196 break; 2197 } 2198 2199 if (i != 3) { 2200 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2201 return; 2202 } 2203 2204 /* Turn the GP0 interrupt back on. */ 2205 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2206 SK_XM_READ_2(sc_if, XM_ISR); 2207 mii_tick(mii); 2208 mii_pollstat(mii); 2209 callout_stop(&sc_if->sk_tick_ch); 2210 } 2211 2212 void 2213 sk_intr_bcom(struct sk_if_softc *sc_if) 2214 { 2215 struct mii_data *mii = &sc_if->sk_mii; 2216 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2217 int status; 2218 2219 2220 DPRINTFN(3, ("sk_intr_bcom\n")); 2221 2222 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2223 2224 /* 2225 * Read the PHY interrupt register to make sure 2226 * we clear any pending interrupts. 2227 */ 2228 status = sk_xmac_miibus_readreg(sc_if->sk_dev, 2229 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2230 2231 if (!(ifp->if_flags & IFF_RUNNING)) { 2232 sk_init_xmac(sc_if); 2233 return; 2234 } 2235 2236 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2237 int lstat; 2238 lstat = sk_xmac_miibus_readreg(sc_if->sk_dev, 2239 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2240 2241 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2242 (void)mii_mediachg(mii); 2243 /* Turn off the link LED. */ 2244 SK_IF_WRITE_1(sc_if, 0, 2245 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2246 sc_if->sk_link = 0; 2247 } else if (status & BRGPHY_ISR_LNK_CHG) { 2248 sk_xmac_miibus_writereg(sc_if->sk_dev, 2249 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2250 mii_tick(mii); 2251 sc_if->sk_link = 1; 2252 /* Turn on the link LED. */ 2253 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2254 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2255 SK_LINKLED_BLINK_OFF); 2256 mii_pollstat(mii); 2257 } else { 2258 mii_tick(mii); 2259 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2260 } 2261 } 2262 2263 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2264 } 2265 2266 void 2267 sk_intr_xmac(struct sk_if_softc *sc_if) 2268 { 2269 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2270 2271 DPRINTFN(3, ("sk_intr_xmac\n")); 2272 2273 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2274 if (status & XM_ISR_GP0_SET) { 2275 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2276 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2277 } 2278 2279 if (status & XM_ISR_AUTONEG_DONE) { 2280 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2281 } 2282 } 2283 2284 if (status & XM_IMR_TX_UNDERRUN) 2285 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2286 2287 if (status & XM_IMR_RX_OVERRUN) 2288 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2289 } 2290 2291 void 2292 sk_intr_yukon(struct sk_if_softc *sc_if) 2293 { 2294 int status; 2295 2296 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2297 2298 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2299 } 2300 2301 int 2302 sk_intr(void *xsc) 2303 { 2304 struct sk_softc *sc = xsc; 2305 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2306 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2307 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2308 u_int32_t status; 2309 int claimed = 0; 2310 2311 if (sc_if0 != NULL) 2312 ifp0 = &sc_if0->sk_ethercom.ec_if; 2313 if (sc_if1 != NULL) 2314 ifp1 = &sc_if1->sk_ethercom.ec_if; 2315 2316 for (;;) { 2317 status = CSR_READ_4(sc, SK_ISSR); 2318 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2319 2320 if (!(status & sc->sk_intrmask)) 2321 break; 2322 2323 claimed = 1; 2324 2325 /* Handle receive interrupts first. */ 2326 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2327 sk_rxeof(sc_if0); 2328 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2329 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2330 } 2331 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2332 sk_rxeof(sc_if1); 2333 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2334 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2335 } 2336 2337 /* Then transmit interrupts. */ 2338 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2339 sk_txeof(sc_if0); 2340 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2341 SK_TXBMU_CLR_IRQ_EOF); 2342 } 2343 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2344 sk_txeof(sc_if1); 2345 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2346 SK_TXBMU_CLR_IRQ_EOF); 2347 } 2348 2349 /* Then MAC interrupts. */ 2350 if (sc_if0 && (status & SK_ISR_MAC1) && 2351 (ifp0->if_flags & IFF_RUNNING)) { 2352 if (sc->sk_type == SK_GENESIS) 2353 sk_intr_xmac(sc_if0); 2354 else 2355 sk_intr_yukon(sc_if0); 2356 } 2357 2358 if (sc_if1 && (status & SK_ISR_MAC2) && 2359 (ifp1->if_flags & IFF_RUNNING)) { 2360 if (sc->sk_type == SK_GENESIS) 2361 sk_intr_xmac(sc_if1); 2362 else 2363 sk_intr_yukon(sc_if1); 2364 2365 } 2366 2367 if (status & SK_ISR_EXTERNAL_REG) { 2368 if (sc_if0 != NULL && 2369 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2370 sk_intr_bcom(sc_if0); 2371 2372 if (sc_if1 != NULL && 2373 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2374 sk_intr_bcom(sc_if1); 2375 } 2376 } 2377 2378 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2379 2380 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2381 sk_start(ifp0); 2382 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2383 sk_start(ifp1); 2384 2385 #if NRND > 0 2386 if (RND_ENABLED(&sc->rnd_source)) 2387 rnd_add_uint32(&sc->rnd_source, status); 2388 #endif 2389 2390 if (sc->sk_int_mod_pending) 2391 sk_update_int_mod(sc); 2392 2393 return claimed; 2394 } 2395 2396 void 2397 sk_init_xmac(struct sk_if_softc *sc_if) 2398 { 2399 struct sk_softc *sc = sc_if->sk_softc; 2400 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2401 static const struct sk_bcom_hack bhack[] = { 2402 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2403 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2404 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2405 { 0, 0 } }; 2406 2407 DPRINTFN(1, ("sk_init_xmac\n")); 2408 2409 /* Unreset the XMAC. */ 2410 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2411 DELAY(1000); 2412 2413 /* Reset the XMAC's internal state. */ 2414 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2415 2416 /* Save the XMAC II revision */ 2417 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2418 2419 /* 2420 * Perform additional initialization for external PHYs, 2421 * namely for the 1000baseTX cards that use the XMAC's 2422 * GMII mode. 2423 */ 2424 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2425 int i = 0; 2426 u_int32_t val; 2427 2428 /* Take PHY out of reset. */ 2429 val = sk_win_read_4(sc, SK_GPIO); 2430 if (sc_if->sk_port == SK_PORT_A) 2431 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2432 else 2433 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2434 sk_win_write_4(sc, SK_GPIO, val); 2435 2436 /* Enable GMII mode on the XMAC. */ 2437 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2438 2439 sk_xmac_miibus_writereg(sc_if->sk_dev, 2440 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2441 DELAY(10000); 2442 sk_xmac_miibus_writereg(sc_if->sk_dev, 2443 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2444 2445 /* 2446 * Early versions of the BCM5400 apparently have 2447 * a bug that requires them to have their reserved 2448 * registers initialized to some magic values. I don't 2449 * know what the numbers do, I'm just the messenger. 2450 */ 2451 if (sk_xmac_miibus_readreg(sc_if->sk_dev, 2452 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2453 while (bhack[i].reg) { 2454 sk_xmac_miibus_writereg(sc_if->sk_dev, 2455 SK_PHYADDR_BCOM, bhack[i].reg, 2456 bhack[i].val); 2457 i++; 2458 } 2459 } 2460 } 2461 2462 /* Set station address */ 2463 SK_XM_WRITE_2(sc_if, XM_PAR0, 2464 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2465 SK_XM_WRITE_2(sc_if, XM_PAR1, 2466 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2467 SK_XM_WRITE_2(sc_if, XM_PAR2, 2468 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2469 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2470 2471 if (ifp->if_flags & IFF_PROMISC) 2472 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2473 else 2474 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2475 2476 if (ifp->if_flags & IFF_BROADCAST) 2477 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2478 else 2479 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2480 2481 /* We don't need the FCS appended to the packet. */ 2482 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2483 2484 /* We want short frames padded to 60 bytes. */ 2485 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2486 2487 /* 2488 * Enable the reception of all error frames. This is is 2489 * a necessary evil due to the design of the XMAC. The 2490 * XMAC's receive FIFO is only 8K in size, however jumbo 2491 * frames can be up to 9000 bytes in length. When bad 2492 * frame filtering is enabled, the XMAC's RX FIFO operates 2493 * in 'store and forward' mode. For this to work, the 2494 * entire frame has to fit into the FIFO, but that means 2495 * that jumbo frames larger than 8192 bytes will be 2496 * truncated. Disabling all bad frame filtering causes 2497 * the RX FIFO to operate in streaming mode, in which 2498 * case the XMAC will start transfering frames out of the 2499 * RX FIFO as soon as the FIFO threshold is reached. 2500 */ 2501 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2502 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2503 XM_MODE_RX_INRANGELEN); 2504 2505 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2506 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2507 else 2508 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2509 2510 /* 2511 * Bump up the transmit threshold. This helps hold off transmit 2512 * underruns when we're blasting traffic from both ports at once. 2513 */ 2514 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2515 2516 /* Set multicast filter */ 2517 sk_setmulti(sc_if); 2518 2519 /* Clear and enable interrupts */ 2520 SK_XM_READ_2(sc_if, XM_ISR); 2521 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2522 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2523 else 2524 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2525 2526 /* Configure MAC arbiter */ 2527 switch (sc_if->sk_xmac_rev) { 2528 case XM_XMAC_REV_B2: 2529 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2530 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2531 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2532 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2533 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2534 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2535 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2536 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2537 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2538 break; 2539 case XM_XMAC_REV_C1: 2540 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2541 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2542 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2543 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2544 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2545 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2546 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2547 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2548 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2549 break; 2550 default: 2551 break; 2552 } 2553 sk_win_write_2(sc, SK_MACARB_CTL, 2554 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2555 2556 sc_if->sk_link = 1; 2557 } 2558 2559 void sk_init_yukon(struct sk_if_softc *sc_if) 2560 { 2561 u_int32_t /*mac, */phy; 2562 u_int16_t reg; 2563 struct sk_softc *sc; 2564 int i; 2565 2566 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2567 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2568 2569 sc = sc_if->sk_softc; 2570 if (sc->sk_type == SK_YUKON_LITE && 2571 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2572 /* Take PHY out of reset. */ 2573 sk_win_write_4(sc, SK_GPIO, 2574 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2575 } 2576 2577 2578 /* GMAC and GPHY Reset */ 2579 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2580 2581 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2582 2583 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2584 DELAY(1000); 2585 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2586 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2587 DELAY(1000); 2588 2589 2590 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2591 2592 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2593 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2594 2595 switch (sc_if->sk_softc->sk_pmd) { 2596 case IFM_1000_SX: 2597 case IFM_1000_LX: 2598 phy |= SK_GPHY_FIBER; 2599 break; 2600 2601 case IFM_1000_CX: 2602 case IFM_1000_T: 2603 phy |= SK_GPHY_COPPER; 2604 break; 2605 } 2606 2607 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2608 2609 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2610 DELAY(1000); 2611 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2612 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2613 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2614 2615 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2616 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2617 2618 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2619 2620 /* unused read of the interrupt source register */ 2621 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2622 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2623 2624 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2625 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2626 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2627 2628 /* MIB Counter Clear Mode set */ 2629 reg |= YU_PAR_MIB_CLR; 2630 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2631 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2632 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2633 2634 /* MIB Counter Clear Mode clear */ 2635 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2636 reg &= ~YU_PAR_MIB_CLR; 2637 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2638 2639 /* receive control reg */ 2640 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2641 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2642 YU_RCR_CRCR); 2643 2644 /* transmit parameter register */ 2645 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2646 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2647 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2648 2649 /* serial mode register */ 2650 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2651 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2652 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2653 YU_SMR_IPG_DATA(0x1e)); 2654 2655 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2656 /* Setup Yukon's address */ 2657 for (i = 0; i < 3; i++) { 2658 /* Write Source Address 1 (unicast filter) */ 2659 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2660 sc_if->sk_enaddr[i * 2] | 2661 sc_if->sk_enaddr[i * 2 + 1] << 8); 2662 } 2663 2664 for (i = 0; i < 3; i++) { 2665 reg = sk_win_read_2(sc_if->sk_softc, 2666 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2667 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2668 } 2669 2670 /* Set multicast filter */ 2671 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2672 sk_setmulti(sc_if); 2673 2674 /* enable interrupt mask for counter overflows */ 2675 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2676 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2677 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2678 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2679 2680 /* Configure RX MAC FIFO */ 2681 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2682 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2683 2684 /* Configure TX MAC FIFO */ 2685 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2686 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2687 2688 DPRINTFN(6, ("sk_init_yukon: end\n")); 2689 } 2690 2691 /* 2692 * Note that to properly initialize any part of the GEnesis chip, 2693 * you first have to take it out of reset mode. 2694 */ 2695 int 2696 sk_init(struct ifnet *ifp) 2697 { 2698 struct sk_if_softc *sc_if = ifp->if_softc; 2699 struct sk_softc *sc = sc_if->sk_softc; 2700 struct mii_data *mii = &sc_if->sk_mii; 2701 int rc = 0, s; 2702 u_int32_t imr, imtimer_ticks; 2703 2704 DPRINTFN(1, ("sk_init\n")); 2705 2706 s = splnet(); 2707 2708 if (ifp->if_flags & IFF_RUNNING) { 2709 splx(s); 2710 return 0; 2711 } 2712 2713 /* Cancel pending I/O and free all RX/TX buffers. */ 2714 sk_stop(ifp,0); 2715 2716 if (sc->sk_type == SK_GENESIS) { 2717 /* Configure LINK_SYNC LED */ 2718 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2719 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2720 SK_LINKLED_LINKSYNC_ON); 2721 2722 /* Configure RX LED */ 2723 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2724 SK_RXLEDCTL_COUNTER_START); 2725 2726 /* Configure TX LED */ 2727 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2728 SK_TXLEDCTL_COUNTER_START); 2729 } 2730 2731 /* Configure I2C registers */ 2732 2733 /* Configure XMAC(s) */ 2734 switch (sc->sk_type) { 2735 case SK_GENESIS: 2736 sk_init_xmac(sc_if); 2737 break; 2738 case SK_YUKON: 2739 case SK_YUKON_LITE: 2740 case SK_YUKON_LP: 2741 sk_init_yukon(sc_if); 2742 break; 2743 } 2744 if ((rc = mii_mediachg(mii)) == ENXIO) 2745 rc = 0; 2746 else if (rc != 0) 2747 goto out; 2748 2749 if (sc->sk_type == SK_GENESIS) { 2750 /* Configure MAC FIFOs */ 2751 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2752 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2753 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2754 2755 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2756 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2757 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2758 } 2759 2760 /* Configure transmit arbiter(s) */ 2761 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2762 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2763 2764 /* Configure RAMbuffers */ 2765 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2766 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2767 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2768 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2769 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2770 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2771 2772 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2773 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2774 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2775 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2776 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2777 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2778 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2779 2780 /* Configure BMUs */ 2781 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2782 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2783 SK_RX_RING_ADDR(sc_if, 0)); 2784 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2785 2786 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2787 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2788 SK_TX_RING_ADDR(sc_if, 0)); 2789 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2790 2791 /* Init descriptors */ 2792 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2793 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2794 "memory for rx buffers\n"); 2795 sk_stop(ifp,0); 2796 splx(s); 2797 return ENOBUFS; 2798 } 2799 2800 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2801 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2802 "memory for tx buffers\n"); 2803 sk_stop(ifp,0); 2804 splx(s); 2805 return ENOBUFS; 2806 } 2807 2808 /* Set interrupt moderation if changed via sysctl. */ 2809 switch (sc->sk_type) { 2810 case SK_GENESIS: 2811 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2812 break; 2813 case SK_YUKON_EC: 2814 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2815 break; 2816 default: 2817 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2818 } 2819 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2820 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2821 sk_win_write_4(sc, SK_IMTIMERINIT, 2822 SK_IM_USECS(sc->sk_int_mod)); 2823 aprint_verbose_dev(sc->sk_dev, 2824 "interrupt moderation is %d us\n", sc->sk_int_mod); 2825 } 2826 2827 /* Configure interrupt handling */ 2828 CSR_READ_4(sc, SK_ISSR); 2829 if (sc_if->sk_port == SK_PORT_A) 2830 sc->sk_intrmask |= SK_INTRS1; 2831 else 2832 sc->sk_intrmask |= SK_INTRS2; 2833 2834 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2835 2836 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2837 2838 /* Start BMUs. */ 2839 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2840 2841 if (sc->sk_type == SK_GENESIS) { 2842 /* Enable XMACs TX and RX state machines */ 2843 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2844 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2845 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2846 } 2847 2848 if (SK_YUKON_FAMILY(sc->sk_type)) { 2849 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2850 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2851 #if 0 2852 /* XXX disable 100Mbps and full duplex mode? */ 2853 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2854 #endif 2855 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2856 } 2857 2858 2859 ifp->if_flags |= IFF_RUNNING; 2860 ifp->if_flags &= ~IFF_OACTIVE; 2861 2862 out: 2863 splx(s); 2864 return rc; 2865 } 2866 2867 void 2868 sk_stop(struct ifnet *ifp, int disable) 2869 { 2870 struct sk_if_softc *sc_if = ifp->if_softc; 2871 struct sk_softc *sc = sc_if->sk_softc; 2872 int i; 2873 2874 DPRINTFN(1, ("sk_stop\n")); 2875 2876 callout_stop(&sc_if->sk_tick_ch); 2877 2878 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2879 u_int32_t val; 2880 2881 /* Put PHY back into reset. */ 2882 val = sk_win_read_4(sc, SK_GPIO); 2883 if (sc_if->sk_port == SK_PORT_A) { 2884 val |= SK_GPIO_DIR0; 2885 val &= ~SK_GPIO_DAT0; 2886 } else { 2887 val |= SK_GPIO_DIR2; 2888 val &= ~SK_GPIO_DAT2; 2889 } 2890 sk_win_write_4(sc, SK_GPIO, val); 2891 } 2892 2893 /* Turn off various components of this interface. */ 2894 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2895 switch (sc->sk_type) { 2896 case SK_GENESIS: 2897 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2898 SK_TXMACCTL_XMAC_RESET); 2899 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2900 break; 2901 case SK_YUKON: 2902 case SK_YUKON_LITE: 2903 case SK_YUKON_LP: 2904 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2905 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2906 break; 2907 } 2908 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2909 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2910 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2911 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2912 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2913 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2914 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2915 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2916 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2917 2918 /* Disable interrupts */ 2919 if (sc_if->sk_port == SK_PORT_A) 2920 sc->sk_intrmask &= ~SK_INTRS1; 2921 else 2922 sc->sk_intrmask &= ~SK_INTRS2; 2923 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2924 2925 SK_XM_READ_2(sc_if, XM_ISR); 2926 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2927 2928 /* Free RX and TX mbufs still in the queues. */ 2929 for (i = 0; i < SK_RX_RING_CNT; i++) { 2930 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2931 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2932 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2933 } 2934 } 2935 2936 for (i = 0; i < SK_TX_RING_CNT; i++) { 2937 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2938 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2939 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2940 } 2941 } 2942 2943 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2944 } 2945 2946 /* Power Management Framework */ 2947 2948 static bool 2949 skc_suspend(device_t dv, const pmf_qual_t *qual) 2950 { 2951 struct sk_softc *sc = device_private(dv); 2952 2953 DPRINTFN(2, ("skc_suspend\n")); 2954 2955 /* Turn off the driver is loaded LED */ 2956 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2957 2958 return true; 2959 } 2960 2961 static bool 2962 skc_resume(device_t dv, const pmf_qual_t *qual) 2963 { 2964 struct sk_softc *sc = device_private(dv); 2965 2966 DPRINTFN(2, ("skc_resume\n")); 2967 2968 sk_reset(sc); 2969 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2970 2971 return true; 2972 } 2973 2974 static bool 2975 sk_resume(device_t dv, const pmf_qual_t *qual) 2976 { 2977 struct sk_if_softc *sc_if = device_private(dv); 2978 2979 sk_init_yukon(sc_if); 2980 return true; 2981 } 2982 2983 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 2984 skc_probe, skc_attach, NULL, NULL); 2985 2986 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 2987 sk_probe, sk_attach, NULL, NULL); 2988 2989 #ifdef SK_DEBUG 2990 void 2991 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2992 { 2993 #define DESC_PRINT(X) \ 2994 if (X) \ 2995 printf("txdesc[%d]." #X "=%#x\n", \ 2996 idx, X); 2997 2998 DESC_PRINT(le32toh(desc->sk_ctl)); 2999 DESC_PRINT(le32toh(desc->sk_next)); 3000 DESC_PRINT(le32toh(desc->sk_data_lo)); 3001 DESC_PRINT(le32toh(desc->sk_data_hi)); 3002 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 3003 DESC_PRINT(le16toh(desc->sk_rsvd0)); 3004 DESC_PRINT(le16toh(desc->sk_csum_startval)); 3005 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 3006 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 3007 DESC_PRINT(le16toh(desc->sk_rsvd1)); 3008 #undef PRINT 3009 } 3010 3011 void 3012 sk_dump_bytes(const char *data, int len) 3013 { 3014 int c, i, j; 3015 3016 for (i = 0; i < len; i += 16) { 3017 printf("%08x ", i); 3018 c = len - i; 3019 if (c > 16) c = 16; 3020 3021 for (j = 0; j < c; j++) { 3022 printf("%02x ", data[i + j] & 0xff); 3023 if ((j & 0xf) == 7 && j > 0) 3024 printf(" "); 3025 } 3026 3027 for (; j < 16; j++) 3028 printf(" "); 3029 printf(" "); 3030 3031 for (j = 0; j < c; j++) { 3032 int ch = data[i + j] & 0xff; 3033 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3034 } 3035 3036 printf("\n"); 3037 3038 if (c < 16) 3039 break; 3040 } 3041 } 3042 3043 void 3044 sk_dump_mbuf(struct mbuf *m) 3045 { 3046 int count = m->m_pkthdr.len; 3047 3048 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3049 3050 while (count > 0 && m) { 3051 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3052 m, m->m_data, m->m_len); 3053 sk_dump_bytes(mtod(m, char *), m->m_len); 3054 3055 count -= m->m_len; 3056 m = m->m_next; 3057 } 3058 } 3059 #endif 3060 3061 static int 3062 sk_sysctl_handler(SYSCTLFN_ARGS) 3063 { 3064 int error, t; 3065 struct sysctlnode node; 3066 struct sk_softc *sc; 3067 3068 node = *rnode; 3069 sc = node.sysctl_data; 3070 t = sc->sk_int_mod; 3071 node.sysctl_data = &t; 3072 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3073 if (error || newp == NULL) 3074 return error; 3075 3076 if (t < SK_IM_MIN || t > SK_IM_MAX) 3077 return EINVAL; 3078 3079 /* update the softc with sysctl-changed value, and mark 3080 for hardware update */ 3081 sc->sk_int_mod = t; 3082 sc->sk_int_mod_pending = 1; 3083 return 0; 3084 } 3085 3086 /* 3087 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3088 * set up in skc_attach() 3089 */ 3090 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3091 { 3092 int rc; 3093 const struct sysctlnode *node; 3094 3095 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3096 0, CTLTYPE_NODE, "hw", NULL, 3097 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3098 goto err; 3099 } 3100 3101 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3102 0, CTLTYPE_NODE, "sk", 3103 SYSCTL_DESCR("sk interface controls"), 3104 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3105 goto err; 3106 } 3107 3108 sk_root_num = node->sysctl_num; 3109 return; 3110 3111 err: 3112 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3113 } 3114
Indexes created Fri Sep 26 20:09:58 GMT 2025