if_sk.c revision 1.68
1 /* $NetBSD: if_sk.c,v 1.68 2010/07/26 22:33:24 jym Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.68 2010/07/26 22:33:24 jym Exp $"); 119 120 #include "rnd.h" 121 122 #include <sys/param.h> 123 #include <sys/systm.h> 124 #include <sys/sockio.h> 125 #include <sys/mbuf.h> 126 #include <sys/malloc.h> 127 #include <sys/mutex.h> 128 #include <sys/kernel.h> 129 #include <sys/socket.h> 130 #include <sys/device.h> 131 #include <sys/queue.h> 132 #include <sys/callout.h> 133 #include <sys/sysctl.h> 134 #include <sys/endian.h> 135 136 #include <net/if.h> 137 #include <net/if_dl.h> 138 #include <net/if_types.h> 139 140 #include <net/if_media.h> 141 142 #include <net/bpf.h> 143 #if NRND > 0 144 #include <sys/rnd.h> 145 #endif 146 147 #include <dev/mii/mii.h> 148 #include <dev/mii/miivar.h> 149 #include <dev/mii/brgphyreg.h> 150 151 #include <dev/pci/pcireg.h> 152 #include <dev/pci/pcivar.h> 153 #include <dev/pci/pcidevs.h> 154 155 /* #define SK_USEIOSPACE */ 156 157 #include <dev/pci/if_skreg.h> 158 #include <dev/pci/if_skvar.h> 159 160 int skc_probe(device_t, cfdata_t, void *); 161 void skc_attach(device_t, device_t, void *aux); 162 int sk_probe(device_t, cfdata_t, void *); 163 void sk_attach(device_t, device_t, void *aux); 164 int skcprint(void *, const char *); 165 int sk_intr(void *); 166 void sk_intr_bcom(struct sk_if_softc *); 167 void sk_intr_xmac(struct sk_if_softc *); 168 void sk_intr_yukon(struct sk_if_softc *); 169 void sk_rxeof(struct sk_if_softc *); 170 void sk_txeof(struct sk_if_softc *); 171 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 172 void sk_start(struct ifnet *); 173 int sk_ioctl(struct ifnet *, u_long, void *); 174 int sk_init(struct ifnet *); 175 void sk_init_xmac(struct sk_if_softc *); 176 void sk_init_yukon(struct sk_if_softc *); 177 void sk_stop(struct ifnet *, int); 178 void sk_watchdog(struct ifnet *); 179 void sk_shutdown(void *); 180 int sk_ifmedia_upd(struct ifnet *); 181 void sk_reset(struct sk_softc *); 182 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 183 int sk_alloc_jumbo_mem(struct sk_if_softc *); 184 void sk_free_jumbo_mem(struct sk_if_softc *); 185 void *sk_jalloc(struct sk_if_softc *); 186 void sk_jfree(struct mbuf *, void *, size_t, void *); 187 int sk_init_rx_ring(struct sk_if_softc *); 188 int sk_init_tx_ring(struct sk_if_softc *); 189 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 190 void sk_vpd_read_res(struct sk_softc *, 191 struct vpd_res *, int); 192 void sk_vpd_read(struct sk_softc *); 193 194 void sk_update_int_mod(struct sk_softc *); 195 196 int sk_xmac_miibus_readreg(device_t, int, int); 197 void sk_xmac_miibus_writereg(device_t, int, int, int); 198 void sk_xmac_miibus_statchg(device_t); 199 200 int sk_marv_miibus_readreg(device_t, int, int); 201 void sk_marv_miibus_writereg(device_t, int, int, int); 202 void sk_marv_miibus_statchg(device_t); 203 204 u_int32_t sk_xmac_hash(void *); 205 u_int32_t sk_yukon_hash(void *); 206 void sk_setfilt(struct sk_if_softc *, void *, int); 207 void sk_setmulti(struct sk_if_softc *); 208 void sk_tick(void *); 209 210 static bool skc_suspend(device_t, const pmf_qual_t *); 211 static bool skc_resume(device_t, const pmf_qual_t *); 212 static bool sk_resume(device_t dv, const pmf_qual_t *); 213 214 /* #define SK_DEBUG 2 */ 215 #ifdef SK_DEBUG 216 #define DPRINTF(x) if (skdebug) printf x 217 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 218 int skdebug = SK_DEBUG; 219 220 void sk_dump_txdesc(struct sk_tx_desc *, int); 221 void sk_dump_mbuf(struct mbuf *); 222 void sk_dump_bytes(const char *, int); 223 #else 224 #define DPRINTF(x) 225 #define DPRINTFN(n,x) 226 #endif 227 228 static int sk_sysctl_handler(SYSCTLFN_PROTO); 229 static int sk_root_num; 230 231 /* supported device vendors */ 232 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 233 static const struct sk_product { 234 pci_vendor_id_t sk_vendor; 235 pci_product_id_t sk_product; 236 } sk_products[] = { 237 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 238 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 239 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 240 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 241 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 242 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 243 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 244 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 245 { 0, 0, } 246 }; 247 248 #define SK_LINKSYS_EG1032_SUBID 0x00151737 249 250 static inline u_int32_t 251 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 252 { 253 #ifdef SK_USEIOSPACE 254 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 255 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 256 #else 257 return CSR_READ_4(sc, reg); 258 #endif 259 } 260 261 static inline u_int16_t 262 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 263 { 264 #ifdef SK_USEIOSPACE 265 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 266 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 267 #else 268 return CSR_READ_2(sc, reg); 269 #endif 270 } 271 272 static inline u_int8_t 273 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 274 { 275 #ifdef SK_USEIOSPACE 276 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 277 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 278 #else 279 return CSR_READ_1(sc, reg); 280 #endif 281 } 282 283 static inline void 284 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 285 { 286 #ifdef SK_USEIOSPACE 287 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 288 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 289 #else 290 CSR_WRITE_4(sc, reg, x); 291 #endif 292 } 293 294 static inline void 295 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 296 { 297 #ifdef SK_USEIOSPACE 298 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 299 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 300 #else 301 CSR_WRITE_2(sc, reg, x); 302 #endif 303 } 304 305 static inline void 306 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 307 { 308 #ifdef SK_USEIOSPACE 309 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 310 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 311 #else 312 CSR_WRITE_1(sc, reg, x); 313 #endif 314 } 315 316 /* 317 * The VPD EEPROM contains Vital Product Data, as suggested in 318 * the PCI 2.1 specification. The VPD data is separared into areas 319 * denoted by resource IDs. The SysKonnect VPD contains an ID string 320 * resource (the name of the adapter), a read-only area resource 321 * containing various key/data fields and a read/write area which 322 * can be used to store asset management information or log messages. 323 * We read the ID string and read-only into buffers attached to 324 * the controller softc structure for later use. At the moment, 325 * we only use the ID string during sk_attach(). 326 */ 327 u_int8_t 328 sk_vpd_readbyte(struct sk_softc *sc, int addr) 329 { 330 int i; 331 332 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 333 for (i = 0; i < SK_TIMEOUT; i++) { 334 DELAY(1); 335 if (sk_win_read_2(sc, 336 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 337 break; 338 } 339 340 if (i == SK_TIMEOUT) 341 return 0; 342 343 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 344 } 345 346 void 347 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 348 { 349 int i; 350 u_int8_t *ptr; 351 352 ptr = (u_int8_t *)res; 353 for (i = 0; i < sizeof(struct vpd_res); i++) 354 ptr[i] = sk_vpd_readbyte(sc, i + addr); 355 } 356 357 void 358 sk_vpd_read(struct sk_softc *sc) 359 { 360 int pos = 0, i; 361 struct vpd_res res; 362 363 if (sc->sk_vpd_prodname != NULL) 364 free(sc->sk_vpd_prodname, M_DEVBUF); 365 if (sc->sk_vpd_readonly != NULL) 366 free(sc->sk_vpd_readonly, M_DEVBUF); 367 sc->sk_vpd_prodname = NULL; 368 sc->sk_vpd_readonly = NULL; 369 370 sk_vpd_read_res(sc, &res, pos); 371 372 if (res.vr_id != VPD_RES_ID) { 373 aprint_error_dev(sc->sk_dev, 374 "bad VPD resource id: expected %x got %x\n", 375 VPD_RES_ID, res.vr_id); 376 return; 377 } 378 379 pos += sizeof(res); 380 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 381 if (sc->sk_vpd_prodname == NULL) 382 panic("sk_vpd_read"); 383 for (i = 0; i < res.vr_len; i++) 384 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 385 sc->sk_vpd_prodname[i] = '\0'; 386 pos += i; 387 388 sk_vpd_read_res(sc, &res, pos); 389 390 if (res.vr_id != VPD_RES_READ) { 391 aprint_error_dev(sc->sk_dev, 392 "bad VPD resource id: expected %x got %x\n", 393 VPD_RES_READ, res.vr_id); 394 return; 395 } 396 397 pos += sizeof(res); 398 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 399 if (sc->sk_vpd_readonly == NULL) 400 panic("sk_vpd_read"); 401 for (i = 0; i < res.vr_len ; i++) 402 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 403 } 404 405 int 406 sk_xmac_miibus_readreg(device_t dev, int phy, int reg) 407 { 408 struct sk_if_softc *sc_if = device_private(dev); 409 int i; 410 411 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 412 413 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 414 return 0; 415 416 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 417 SK_XM_READ_2(sc_if, XM_PHY_DATA); 418 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 419 for (i = 0; i < SK_TIMEOUT; i++) { 420 DELAY(1); 421 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 422 XM_MMUCMD_PHYDATARDY) 423 break; 424 } 425 426 if (i == SK_TIMEOUT) { 427 aprint_error_dev(sc_if->sk_dev, 428 "phy failed to come ready\n"); 429 return 0; 430 } 431 } 432 DELAY(1); 433 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 434 } 435 436 void 437 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, int val) 438 { 439 struct sk_if_softc *sc_if = device_private(dev); 440 int i; 441 442 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 443 444 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 445 for (i = 0; i < SK_TIMEOUT; i++) { 446 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 447 break; 448 } 449 450 if (i == SK_TIMEOUT) { 451 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 452 return; 453 } 454 455 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 456 for (i = 0; i < SK_TIMEOUT; i++) { 457 DELAY(1); 458 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 459 break; 460 } 461 462 if (i == SK_TIMEOUT) 463 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 464 } 465 466 void 467 sk_xmac_miibus_statchg(device_t dev) 468 { 469 struct sk_if_softc *sc_if = device_private(dev); 470 struct mii_data *mii = &sc_if->sk_mii; 471 472 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 473 474 /* 475 * If this is a GMII PHY, manually set the XMAC's 476 * duplex mode accordingly. 477 */ 478 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 479 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 480 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 481 else 482 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 483 } 484 } 485 486 int 487 sk_marv_miibus_readreg(device_t dev, int phy, int reg) 488 { 489 struct sk_if_softc *sc_if = device_private(dev); 490 u_int16_t val; 491 int i; 492 493 if (phy != 0 || 494 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 495 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 496 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 497 phy, reg)); 498 return 0; 499 } 500 501 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 502 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 503 504 for (i = 0; i < SK_TIMEOUT; i++) { 505 DELAY(1); 506 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 507 if (val & YU_SMICR_READ_VALID) 508 break; 509 } 510 511 if (i == SK_TIMEOUT) { 512 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 513 return 0; 514 } 515 516 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 517 SK_TIMEOUT)); 518 519 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 520 521 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 522 phy, reg, val)); 523 524 return val; 525 } 526 527 void 528 sk_marv_miibus_writereg(device_t dev, int phy, int reg, int val) 529 { 530 struct sk_if_softc *sc_if = device_private(dev); 531 int i; 532 533 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 534 phy, reg, val)); 535 536 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 537 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 538 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 539 540 for (i = 0; i < SK_TIMEOUT; i++) { 541 DELAY(1); 542 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 543 break; 544 } 545 546 if (i == SK_TIMEOUT) 547 printf("%s: phy write timed out\n", 548 device_xname(sc_if->sk_dev)); 549 } 550 551 void 552 sk_marv_miibus_statchg(device_t dev) 553 { 554 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 555 SK_YU_READ_2(((struct sk_if_softc *)device_private(dev)), 556 YUKON_GPCR))); 557 } 558 559 #define SK_HASH_BITS 6 560 561 u_int32_t 562 sk_xmac_hash(void *addr) 563 { 564 u_int32_t crc; 565 566 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 567 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 568 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 569 return crc; 570 } 571 572 u_int32_t 573 sk_yukon_hash(void *addr) 574 { 575 u_int32_t crc; 576 577 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 578 crc &= ((1 << SK_HASH_BITS) - 1); 579 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 580 return crc; 581 } 582 583 void 584 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 585 { 586 char *addr = addrv; 587 int base = XM_RXFILT_ENTRY(slot); 588 589 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 590 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 591 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 592 } 593 594 void 595 sk_setmulti(struct sk_if_softc *sc_if) 596 { 597 struct sk_softc *sc = sc_if->sk_softc; 598 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 599 u_int32_t hashes[2] = { 0, 0 }; 600 int h = 0, i; 601 struct ethercom *ec = &sc_if->sk_ethercom; 602 struct ether_multi *enm; 603 struct ether_multistep step; 604 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 605 606 /* First, zot all the existing filters. */ 607 switch (sc->sk_type) { 608 case SK_GENESIS: 609 for (i = 1; i < XM_RXFILT_MAX; i++) 610 sk_setfilt(sc_if, (void *)&dummy, i); 611 612 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 613 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 614 break; 615 case SK_YUKON: 616 case SK_YUKON_LITE: 617 case SK_YUKON_LP: 618 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 619 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 620 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 621 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 622 break; 623 } 624 625 /* Now program new ones. */ 626 allmulti: 627 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 628 hashes[0] = 0xFFFFFFFF; 629 hashes[1] = 0xFFFFFFFF; 630 } else { 631 i = 1; 632 /* First find the tail of the list. */ 633 ETHER_FIRST_MULTI(step, ec, enm); 634 while (enm != NULL) { 635 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 636 ETHER_ADDR_LEN)) { 637 ifp->if_flags |= IFF_ALLMULTI; 638 goto allmulti; 639 } 640 DPRINTFN(2,("multicast address %s\n", 641 ether_sprintf(enm->enm_addrlo))); 642 /* 643 * Program the first XM_RXFILT_MAX multicast groups 644 * into the perfect filter. For all others, 645 * use the hash table. 646 */ 647 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 648 sk_setfilt(sc_if, enm->enm_addrlo, i); 649 i++; 650 } 651 else { 652 switch (sc->sk_type) { 653 case SK_GENESIS: 654 h = sk_xmac_hash(enm->enm_addrlo); 655 break; 656 case SK_YUKON: 657 case SK_YUKON_LITE: 658 case SK_YUKON_LP: 659 h = sk_yukon_hash(enm->enm_addrlo); 660 break; 661 } 662 if (h < 32) 663 hashes[0] |= (1 << h); 664 else 665 hashes[1] |= (1 << (h - 32)); 666 } 667 668 ETHER_NEXT_MULTI(step, enm); 669 } 670 } 671 672 switch (sc->sk_type) { 673 case SK_GENESIS: 674 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 675 XM_MODE_RX_USE_PERFECT); 676 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 677 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 678 break; 679 case SK_YUKON: 680 case SK_YUKON_LITE: 681 case SK_YUKON_LP: 682 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 683 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 684 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 685 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 686 break; 687 } 688 } 689 690 int 691 sk_init_rx_ring(struct sk_if_softc *sc_if) 692 { 693 struct sk_chain_data *cd = &sc_if->sk_cdata; 694 struct sk_ring_data *rd = sc_if->sk_rdata; 695 int i; 696 697 memset((char *)rd->sk_rx_ring, 0, 698 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 699 700 for (i = 0; i < SK_RX_RING_CNT; i++) { 701 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 702 if (i == (SK_RX_RING_CNT - 1)) { 703 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 704 rd->sk_rx_ring[i].sk_next = 705 htole32(SK_RX_RING_ADDR(sc_if, 0)); 706 } else { 707 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 708 rd->sk_rx_ring[i].sk_next = 709 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 710 } 711 } 712 713 for (i = 0; i < SK_RX_RING_CNT; i++) { 714 if (sk_newbuf(sc_if, i, NULL, 715 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 716 aprint_error_dev(sc_if->sk_dev, 717 "failed alloc of %dth mbuf\n", i); 718 return ENOBUFS; 719 } 720 } 721 sc_if->sk_cdata.sk_rx_prod = 0; 722 sc_if->sk_cdata.sk_rx_cons = 0; 723 724 return 0; 725 } 726 727 int 728 sk_init_tx_ring(struct sk_if_softc *sc_if) 729 { 730 struct sk_chain_data *cd = &sc_if->sk_cdata; 731 struct sk_ring_data *rd = sc_if->sk_rdata; 732 int i; 733 734 memset(sc_if->sk_rdata->sk_tx_ring, 0, 735 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 736 737 for (i = 0; i < SK_TX_RING_CNT; i++) { 738 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 739 if (i == (SK_TX_RING_CNT - 1)) { 740 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 741 rd->sk_tx_ring[i].sk_next = 742 htole32(SK_TX_RING_ADDR(sc_if, 0)); 743 } else { 744 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 745 rd->sk_tx_ring[i].sk_next = 746 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 747 } 748 } 749 750 sc_if->sk_cdata.sk_tx_prod = 0; 751 sc_if->sk_cdata.sk_tx_cons = 0; 752 sc_if->sk_cdata.sk_tx_cnt = 0; 753 754 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 755 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 756 757 return 0; 758 } 759 760 int 761 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 762 bus_dmamap_t dmamap) 763 { 764 struct mbuf *m_new = NULL; 765 struct sk_chain *c; 766 struct sk_rx_desc *r; 767 768 if (m == NULL) { 769 void *buf = NULL; 770 771 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 772 if (m_new == NULL) { 773 aprint_error_dev(sc_if->sk_dev, 774 "no memory for rx list -- packet dropped!\n"); 775 return ENOBUFS; 776 } 777 778 /* Allocate the jumbo buffer */ 779 buf = sk_jalloc(sc_if); 780 if (buf == NULL) { 781 m_freem(m_new); 782 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 783 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 784 return ENOBUFS; 785 } 786 787 /* Attach the buffer to the mbuf */ 788 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 789 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 790 791 } else { 792 /* 793 * We're re-using a previously allocated mbuf; 794 * be sure to re-init pointers and lengths to 795 * default values. 796 */ 797 m_new = m; 798 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 799 m_new->m_data = m_new->m_ext.ext_buf; 800 } 801 m_adj(m_new, ETHER_ALIGN); 802 803 c = &sc_if->sk_cdata.sk_rx_chain[i]; 804 r = c->sk_desc; 805 c->sk_mbuf = m_new; 806 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 807 (((vaddr_t)m_new->m_data 808 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 809 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 810 811 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 812 813 return 0; 814 } 815 816 /* 817 * Memory management for jumbo frames. 818 */ 819 820 int 821 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 822 { 823 struct sk_softc *sc = sc_if->sk_softc; 824 char *ptr, *kva; 825 bus_dma_segment_t seg; 826 int i, rseg, state, error; 827 struct sk_jpool_entry *entry; 828 829 state = error = 0; 830 831 /* Grab a big chunk o' storage. */ 832 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 833 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 834 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 835 return ENOBUFS; 836 } 837 838 state = 1; 839 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 840 BUS_DMA_NOWAIT)) { 841 aprint_error_dev(sc->sk_dev, 842 "can't map dma buffers (%d bytes)\n", 843 SK_JMEM); 844 error = ENOBUFS; 845 goto out; 846 } 847 848 state = 2; 849 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 850 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 851 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 852 error = ENOBUFS; 853 goto out; 854 } 855 856 state = 3; 857 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 858 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 859 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 860 error = ENOBUFS; 861 goto out; 862 } 863 864 state = 4; 865 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 866 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 867 868 LIST_INIT(&sc_if->sk_jfree_listhead); 869 LIST_INIT(&sc_if->sk_jinuse_listhead); 870 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 871 872 /* 873 * Now divide it up into 9K pieces and save the addresses 874 * in an array. 875 */ 876 ptr = sc_if->sk_cdata.sk_jumbo_buf; 877 for (i = 0; i < SK_JSLOTS; i++) { 878 sc_if->sk_cdata.sk_jslots[i] = ptr; 879 ptr += SK_JLEN; 880 entry = malloc(sizeof(struct sk_jpool_entry), 881 M_DEVBUF, M_NOWAIT); 882 if (entry == NULL) { 883 aprint_error_dev(sc->sk_dev, 884 "no memory for jumbo buffer queue!\n"); 885 error = ENOBUFS; 886 goto out; 887 } 888 entry->slot = i; 889 if (i) 890 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 891 entry, jpool_entries); 892 else 893 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 894 entry, jpool_entries); 895 } 896 out: 897 if (error != 0) { 898 switch (state) { 899 case 4: 900 bus_dmamap_unload(sc->sc_dmatag, 901 sc_if->sk_cdata.sk_rx_jumbo_map); 902 case 3: 903 bus_dmamap_destroy(sc->sc_dmatag, 904 sc_if->sk_cdata.sk_rx_jumbo_map); 905 case 2: 906 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 907 case 1: 908 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 909 break; 910 default: 911 break; 912 } 913 } 914 915 return error; 916 } 917 918 /* 919 * Allocate a jumbo buffer. 920 */ 921 void * 922 sk_jalloc(struct sk_if_softc *sc_if) 923 { 924 struct sk_jpool_entry *entry; 925 926 mutex_enter(&sc_if->sk_jpool_mtx); 927 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 928 929 if (entry == NULL) { 930 mutex_exit(&sc_if->sk_jpool_mtx); 931 return NULL; 932 } 933 934 LIST_REMOVE(entry, jpool_entries); 935 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 936 mutex_exit(&sc_if->sk_jpool_mtx); 937 return sc_if->sk_cdata.sk_jslots[entry->slot]; 938 } 939 940 /* 941 * Release a jumbo buffer. 942 */ 943 void 944 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 945 { 946 struct sk_jpool_entry *entry; 947 struct sk_if_softc *sc; 948 int i; 949 950 /* Extract the softc struct pointer. */ 951 sc = (struct sk_if_softc *)arg; 952 953 if (sc == NULL) 954 panic("sk_jfree: can't find softc pointer!"); 955 956 /* calculate the slot this buffer belongs to */ 957 958 i = ((vaddr_t)buf 959 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 960 961 if ((i < 0) || (i >= SK_JSLOTS)) 962 panic("sk_jfree: asked to free buffer that we don't manage!"); 963 964 mutex_enter(&sc->sk_jpool_mtx); 965 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 966 if (entry == NULL) 967 panic("sk_jfree: buffer not in use!"); 968 entry->slot = i; 969 LIST_REMOVE(entry, jpool_entries); 970 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 971 mutex_exit(&sc->sk_jpool_mtx); 972 973 if (__predict_true(m != NULL)) 974 pool_cache_put(mb_cache, m); 975 } 976 977 /* 978 * Set media options. 979 */ 980 int 981 sk_ifmedia_upd(struct ifnet *ifp) 982 { 983 struct sk_if_softc *sc_if = ifp->if_softc; 984 int rc; 985 986 (void) sk_init(ifp); 987 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 988 return 0; 989 return rc; 990 } 991 992 int 993 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 994 { 995 struct sk_if_softc *sc_if = ifp->if_softc; 996 struct sk_softc *sc = sc_if->sk_softc; 997 int s, error = 0; 998 999 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1000 1001 s = splnet(); 1002 1003 switch (command) { 1004 1005 case SIOCSIFFLAGS: 1006 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1007 if ((error = ifioctl_common(ifp, command, data)) != 0) 1008 break; 1009 if (ifp->if_flags & IFF_UP) { 1010 if (ifp->if_flags & IFF_RUNNING && 1011 ifp->if_flags & IFF_PROMISC && 1012 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1013 switch (sc->sk_type) { 1014 case SK_GENESIS: 1015 SK_XM_SETBIT_4(sc_if, XM_MODE, 1016 XM_MODE_RX_PROMISC); 1017 break; 1018 case SK_YUKON: 1019 case SK_YUKON_LITE: 1020 case SK_YUKON_LP: 1021 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1022 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1023 break; 1024 } 1025 sk_setmulti(sc_if); 1026 } else if (ifp->if_flags & IFF_RUNNING && 1027 !(ifp->if_flags & IFF_PROMISC) && 1028 sc_if->sk_if_flags & IFF_PROMISC) { 1029 switch (sc->sk_type) { 1030 case SK_GENESIS: 1031 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1032 XM_MODE_RX_PROMISC); 1033 break; 1034 case SK_YUKON: 1035 case SK_YUKON_LITE: 1036 case SK_YUKON_LP: 1037 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1038 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1039 break; 1040 } 1041 1042 sk_setmulti(sc_if); 1043 } else 1044 (void) sk_init(ifp); 1045 } else { 1046 if (ifp->if_flags & IFF_RUNNING) 1047 sk_stop(ifp,0); 1048 } 1049 sc_if->sk_if_flags = ifp->if_flags; 1050 error = 0; 1051 break; 1052 1053 default: 1054 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1055 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1056 break; 1057 1058 error = 0; 1059 1060 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1061 ; 1062 else if (ifp->if_flags & IFF_RUNNING) { 1063 sk_setmulti(sc_if); 1064 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1065 } 1066 break; 1067 } 1068 1069 splx(s); 1070 return error; 1071 } 1072 1073 void 1074 sk_update_int_mod(struct sk_softc *sc) 1075 { 1076 u_int32_t imtimer_ticks; 1077 1078 /* 1079 * Configure interrupt moderation. The moderation timer 1080 * defers interrupts specified in the interrupt moderation 1081 * timer mask based on the timeout specified in the interrupt 1082 * moderation timer init register. Each bit in the timer 1083 * register represents one tick, so to specify a timeout in 1084 * microseconds, we have to multiply by the correct number of 1085 * ticks-per-microsecond. 1086 */ 1087 switch (sc->sk_type) { 1088 case SK_GENESIS: 1089 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1090 break; 1091 case SK_YUKON_EC: 1092 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1093 break; 1094 default: 1095 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1096 } 1097 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1098 sc->sk_int_mod); 1099 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1100 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1101 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1102 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1103 sc->sk_int_mod_pending = 0; 1104 } 1105 1106 /* 1107 * Lookup: Check the PCI vendor and device, and return a pointer to 1108 * The structure if the IDs match against our list. 1109 */ 1110 1111 static const struct sk_product * 1112 sk_lookup(const struct pci_attach_args *pa) 1113 { 1114 const struct sk_product *psk; 1115 1116 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1117 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1118 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1119 return psk; 1120 } 1121 return NULL; 1122 } 1123 1124 /* 1125 * Probe for a SysKonnect GEnesis chip. 1126 */ 1127 1128 int 1129 skc_probe(device_t parent, cfdata_t match, void *aux) 1130 { 1131 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1132 const struct sk_product *psk; 1133 pcireg_t subid; 1134 1135 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1136 1137 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1138 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1139 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1140 subid == SK_LINKSYS_EG1032_SUBID) 1141 return 1; 1142 1143 if ((psk = sk_lookup(pa))) { 1144 return 1; 1145 } 1146 return 0; 1147 } 1148 1149 /* 1150 * Force the GEnesis into reset, then bring it out of reset. 1151 */ 1152 void sk_reset(struct sk_softc *sc) 1153 { 1154 DPRINTFN(2, ("sk_reset\n")); 1155 1156 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1157 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1158 if (SK_YUKON_FAMILY(sc->sk_type)) 1159 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1160 1161 DELAY(1000); 1162 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1163 DELAY(2); 1164 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1165 if (SK_YUKON_FAMILY(sc->sk_type)) 1166 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1167 1168 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1169 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1170 CSR_READ_2(sc, SK_LINK_CTRL))); 1171 1172 if (sc->sk_type == SK_GENESIS) { 1173 /* Configure packet arbiter */ 1174 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1175 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1176 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1177 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1178 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1179 } 1180 1181 /* Enable RAM interface */ 1182 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1183 1184 sk_update_int_mod(sc); 1185 } 1186 1187 int 1188 sk_probe(device_t parent, cfdata_t match, void *aux) 1189 { 1190 struct skc_attach_args *sa = aux; 1191 1192 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1193 return 0; 1194 1195 return 1; 1196 } 1197 1198 /* 1199 * Each XMAC chip is attached as a separate logical IP interface. 1200 * Single port cards will have only one logical interface of course. 1201 */ 1202 void 1203 sk_attach(device_t parent, device_t self, void *aux) 1204 { 1205 struct sk_if_softc *sc_if = device_private(self); 1206 struct sk_softc *sc = device_private(parent); 1207 struct skc_attach_args *sa = aux; 1208 struct sk_txmap_entry *entry; 1209 struct ifnet *ifp; 1210 bus_dma_segment_t seg; 1211 bus_dmamap_t dmamap; 1212 prop_data_t data; 1213 void *kva; 1214 int i, rseg; 1215 int mii_flags = 0; 1216 1217 aprint_naive("\n"); 1218 1219 sc_if->sk_dev = self; 1220 sc_if->sk_port = sa->skc_port; 1221 sc_if->sk_softc = sc; 1222 sc->sk_if[sa->skc_port] = sc_if; 1223 1224 if (sa->skc_port == SK_PORT_A) 1225 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1226 if (sa->skc_port == SK_PORT_B) 1227 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1228 1229 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1230 1231 /* 1232 * Get station address for this interface. Note that 1233 * dual port cards actually come with three station 1234 * addresses: one for each port, plus an extra. The 1235 * extra one is used by the SysKonnect driver software 1236 * as a 'virtual' station address for when both ports 1237 * are operating in failover mode. Currently we don't 1238 * use this extra address. 1239 */ 1240 data = prop_dictionary_get(device_properties(self), "mac-address"); 1241 if (data != NULL) { 1242 /* 1243 * Try to get the station address from device properties 1244 * first, in case the ROM is missing. 1245 */ 1246 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 1247 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 1248 memcpy(sc_if->sk_enaddr, prop_data_data_nocopy(data), 1249 ETHER_ADDR_LEN); 1250 } else 1251 for (i = 0; i < ETHER_ADDR_LEN; i++) 1252 sc_if->sk_enaddr[i] = sk_win_read_1(sc, 1253 SK_MAC0_0 + (sa->skc_port * 8) + i); 1254 1255 aprint_normal(": Ethernet address %s\n", 1256 ether_sprintf(sc_if->sk_enaddr)); 1257 1258 /* 1259 * Set up RAM buffer addresses. The NIC will have a certain 1260 * amount of SRAM on it, somewhere between 512K and 2MB. We 1261 * need to divide this up a) between the transmitter and 1262 * receiver and b) between the two XMACs, if this is a 1263 * dual port NIC. Our algorithm is to divide up the memory 1264 * evenly so that everyone gets a fair share. 1265 */ 1266 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1267 u_int32_t chunk, val; 1268 1269 chunk = sc->sk_ramsize / 2; 1270 val = sc->sk_rboff / sizeof(u_int64_t); 1271 sc_if->sk_rx_ramstart = val; 1272 val += (chunk / sizeof(u_int64_t)); 1273 sc_if->sk_rx_ramend = val - 1; 1274 sc_if->sk_tx_ramstart = val; 1275 val += (chunk / sizeof(u_int64_t)); 1276 sc_if->sk_tx_ramend = val - 1; 1277 } else { 1278 u_int32_t chunk, val; 1279 1280 chunk = sc->sk_ramsize / 4; 1281 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1282 sizeof(u_int64_t); 1283 sc_if->sk_rx_ramstart = val; 1284 val += (chunk / sizeof(u_int64_t)); 1285 sc_if->sk_rx_ramend = val - 1; 1286 sc_if->sk_tx_ramstart = val; 1287 val += (chunk / sizeof(u_int64_t)); 1288 sc_if->sk_tx_ramend = val - 1; 1289 } 1290 1291 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1292 " tx_ramstart=%#x tx_ramend=%#x\n", 1293 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1294 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1295 1296 /* Read and save PHY type and set PHY address */ 1297 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1298 switch (sc_if->sk_phytype) { 1299 case SK_PHYTYPE_XMAC: 1300 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1301 break; 1302 case SK_PHYTYPE_BCOM: 1303 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1304 break; 1305 case SK_PHYTYPE_MARV_COPPER: 1306 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1307 break; 1308 default: 1309 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1310 sc_if->sk_phytype); 1311 return; 1312 } 1313 1314 /* Allocate the descriptor queues. */ 1315 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1316 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1317 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1318 goto fail; 1319 } 1320 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1321 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1322 aprint_error_dev(sc_if->sk_dev, 1323 "can't map dma buffers (%lu bytes)\n", 1324 (u_long) sizeof(struct sk_ring_data)); 1325 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1326 goto fail; 1327 } 1328 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1329 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1330 &sc_if->sk_ring_map)) { 1331 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1332 bus_dmamem_unmap(sc->sc_dmatag, kva, 1333 sizeof(struct sk_ring_data)); 1334 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1335 goto fail; 1336 } 1337 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1338 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1339 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1340 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1341 bus_dmamem_unmap(sc->sc_dmatag, kva, 1342 sizeof(struct sk_ring_data)); 1343 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1344 goto fail; 1345 } 1346 1347 for (i = 0; i < SK_RX_RING_CNT; i++) 1348 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1349 1350 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1351 for (i = 0; i < SK_TX_RING_CNT; i++) { 1352 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1353 1354 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1355 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1356 aprint_error_dev(sc_if->sk_dev, 1357 "Can't create TX dmamap\n"); 1358 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1359 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1360 bus_dmamem_unmap(sc->sc_dmatag, kva, 1361 sizeof(struct sk_ring_data)); 1362 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1363 goto fail; 1364 } 1365 1366 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1367 if (!entry) { 1368 aprint_error_dev(sc_if->sk_dev, 1369 "Can't alloc txmap entry\n"); 1370 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1371 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1372 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1373 bus_dmamem_unmap(sc->sc_dmatag, kva, 1374 sizeof(struct sk_ring_data)); 1375 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1376 goto fail; 1377 } 1378 entry->dmamap = dmamap; 1379 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1380 } 1381 1382 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1383 memset(sc_if->sk_rdata, 0, sizeof(struct sk_ring_data)); 1384 1385 ifp = &sc_if->sk_ethercom.ec_if; 1386 /* Try to allocate memory for jumbo buffers. */ 1387 if (sk_alloc_jumbo_mem(sc_if)) { 1388 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1389 goto fail; 1390 } 1391 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1392 | ETHERCAP_JUMBO_MTU; 1393 1394 ifp->if_softc = sc_if; 1395 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1396 ifp->if_ioctl = sk_ioctl; 1397 ifp->if_start = sk_start; 1398 ifp->if_stop = sk_stop; 1399 ifp->if_init = sk_init; 1400 ifp->if_watchdog = sk_watchdog; 1401 ifp->if_capabilities = 0; 1402 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1403 IFQ_SET_READY(&ifp->if_snd); 1404 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1405 1406 /* 1407 * Do miibus setup. 1408 */ 1409 switch (sc->sk_type) { 1410 case SK_GENESIS: 1411 sk_init_xmac(sc_if); 1412 break; 1413 case SK_YUKON: 1414 case SK_YUKON_LITE: 1415 case SK_YUKON_LP: 1416 sk_init_yukon(sc_if); 1417 break; 1418 default: 1419 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1420 sc->sk_type); 1421 goto fail; 1422 } 1423 1424 DPRINTFN(2, ("sk_attach: 1\n")); 1425 1426 sc_if->sk_mii.mii_ifp = ifp; 1427 switch (sc->sk_type) { 1428 case SK_GENESIS: 1429 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1430 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1431 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1432 break; 1433 case SK_YUKON: 1434 case SK_YUKON_LITE: 1435 case SK_YUKON_LP: 1436 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1437 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1438 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1439 mii_flags = MIIF_DOPAUSE; 1440 break; 1441 } 1442 1443 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1444 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1445 sk_ifmedia_upd, ether_mediastatus); 1446 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1447 MII_OFFSET_ANY, mii_flags); 1448 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1449 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1450 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1451 0, NULL); 1452 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1453 } else 1454 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1455 1456 callout_init(&sc_if->sk_tick_ch, 0); 1457 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1458 1459 DPRINTFN(2, ("sk_attach: 1\n")); 1460 1461 /* 1462 * Call MI attach routines. 1463 */ 1464 if_attach(ifp); 1465 1466 ether_ifattach(ifp, sc_if->sk_enaddr); 1467 1468 #if NRND > 0 1469 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1470 RND_TYPE_NET, 0); 1471 #endif 1472 1473 if (pmf_device_register(self, NULL, sk_resume)) 1474 pmf_class_network_register(self, ifp); 1475 else 1476 aprint_error_dev(self, "couldn't establish power handler\n"); 1477 1478 DPRINTFN(2, ("sk_attach: end\n")); 1479 1480 return; 1481 1482 fail: 1483 sc->sk_if[sa->skc_port] = NULL; 1484 } 1485 1486 int 1487 skcprint(void *aux, const char *pnp) 1488 { 1489 struct skc_attach_args *sa = aux; 1490 1491 if (pnp) 1492 aprint_normal("sk port %c at %s", 1493 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1494 else 1495 aprint_normal(" port %c", 1496 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1497 return UNCONF; 1498 } 1499 1500 /* 1501 * Attach the interface. Allocate softc structures, do ifmedia 1502 * setup and ethernet/BPF attach. 1503 */ 1504 void 1505 skc_attach(device_t parent, device_t self, void *aux) 1506 { 1507 struct sk_softc *sc = device_private(self); 1508 struct pci_attach_args *pa = aux; 1509 struct skc_attach_args skca; 1510 pci_chipset_tag_t pc = pa->pa_pc; 1511 #ifndef SK_USEIOSPACE 1512 pcireg_t memtype; 1513 #endif 1514 pci_intr_handle_t ih; 1515 const char *intrstr = NULL; 1516 bus_addr_t iobase; 1517 bus_size_t iosize; 1518 int rc, sk_nodenum; 1519 u_int32_t command; 1520 const char *revstr; 1521 const struct sysctlnode *node; 1522 1523 sc->sk_dev = self; 1524 aprint_naive("\n"); 1525 1526 DPRINTFN(2, ("begin skc_attach\n")); 1527 1528 /* 1529 * Handle power management nonsense. 1530 */ 1531 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1532 1533 if (command == 0x01) { 1534 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1535 if (command & SK_PSTATE_MASK) { 1536 u_int32_t xiobase, membase, irq; 1537 1538 /* Save important PCI config data. */ 1539 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1540 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1541 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1542 1543 /* Reset the power state. */ 1544 aprint_normal_dev(sc->sk_dev, 1545 "chip is in D%d power mode -- setting to D0\n", 1546 command & SK_PSTATE_MASK); 1547 command &= 0xFFFFFFFC; 1548 pci_conf_write(pc, pa->pa_tag, 1549 SK_PCI_PWRMGMTCTRL, command); 1550 1551 /* Restore PCI config data. */ 1552 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1553 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1554 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1555 } 1556 } 1557 1558 /* 1559 * Map control/status registers. 1560 */ 1561 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1562 command |= PCI_COMMAND_IO_ENABLE | 1563 PCI_COMMAND_MEM_ENABLE | 1564 PCI_COMMAND_MASTER_ENABLE; 1565 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1566 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1567 1568 #ifdef SK_USEIOSPACE 1569 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1570 aprint_error(": failed to enable I/O ports!\n"); 1571 return; 1572 } 1573 /* 1574 * Map control/status registers. 1575 */ 1576 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1577 &sc->sk_btag, &sc->sk_bhandle, 1578 &iobase, &iosize)) { 1579 aprint_error(": can't find i/o space\n"); 1580 return; 1581 } 1582 #else 1583 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1584 aprint_error(": failed to enable memory mapping!\n"); 1585 return; 1586 } 1587 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1588 switch (memtype) { 1589 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1590 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1591 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1592 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1593 &iobase, &iosize) == 0) 1594 break; 1595 default: 1596 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1597 return; 1598 } 1599 1600 DPRINTFN(2, ("skc_attach: iobase=%#" PRIxPADDR ", iosize=%zx\n", 1601 iobase, iosize)); 1602 #endif 1603 sc->sc_dmatag = pa->pa_dmat; 1604 1605 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1606 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1607 1608 /* bail out here if chip is not recognized */ 1609 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1610 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1611 goto fail; 1612 } 1613 if (SK_IS_YUKON2(sc)) { 1614 aprint_error_dev(sc->sk_dev, 1615 "Does not support Yukon2--try msk(4).\n"); 1616 goto fail; 1617 } 1618 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1619 1620 /* Allocate interrupt */ 1621 if (pci_intr_map(pa, &ih)) { 1622 aprint_error(": couldn't map interrupt\n"); 1623 goto fail; 1624 } 1625 1626 intrstr = pci_intr_string(pc, ih); 1627 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1628 if (sc->sk_intrhand == NULL) { 1629 aprint_error(": couldn't establish interrupt"); 1630 if (intrstr != NULL) 1631 aprint_error(" at %s", intrstr); 1632 aprint_error("\n"); 1633 goto fail; 1634 } 1635 aprint_normal(": %s\n", intrstr); 1636 1637 /* Reset the adapter. */ 1638 sk_reset(sc); 1639 1640 /* Read and save vital product data from EEPROM. */ 1641 sk_vpd_read(sc); 1642 1643 if (sc->sk_type == SK_GENESIS) { 1644 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1645 /* Read and save RAM size and RAMbuffer offset */ 1646 switch (val) { 1647 case SK_RAMSIZE_512K_64: 1648 sc->sk_ramsize = 0x80000; 1649 sc->sk_rboff = SK_RBOFF_0; 1650 break; 1651 case SK_RAMSIZE_1024K_64: 1652 sc->sk_ramsize = 0x100000; 1653 sc->sk_rboff = SK_RBOFF_80000; 1654 break; 1655 case SK_RAMSIZE_1024K_128: 1656 sc->sk_ramsize = 0x100000; 1657 sc->sk_rboff = SK_RBOFF_0; 1658 break; 1659 case SK_RAMSIZE_2048K_128: 1660 sc->sk_ramsize = 0x200000; 1661 sc->sk_rboff = SK_RBOFF_0; 1662 break; 1663 default: 1664 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1665 val); 1666 goto fail_1; 1667 break; 1668 } 1669 1670 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1671 sc->sk_ramsize, sc->sk_ramsize / 1024, 1672 sc->sk_rboff)); 1673 } else { 1674 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1675 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1676 sc->sk_rboff = SK_RBOFF_0; 1677 1678 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1679 sc->sk_ramsize / 1024, sc->sk_ramsize, 1680 sc->sk_rboff)); 1681 } 1682 1683 /* Read and save physical media type */ 1684 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1685 case SK_PMD_1000BASESX: 1686 sc->sk_pmd = IFM_1000_SX; 1687 break; 1688 case SK_PMD_1000BASELX: 1689 sc->sk_pmd = IFM_1000_LX; 1690 break; 1691 case SK_PMD_1000BASECX: 1692 sc->sk_pmd = IFM_1000_CX; 1693 break; 1694 case SK_PMD_1000BASETX: 1695 case SK_PMD_1000BASETX_ALT: 1696 sc->sk_pmd = IFM_1000_T; 1697 break; 1698 default: 1699 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1700 sk_win_read_1(sc, SK_PMDTYPE)); 1701 goto fail_1; 1702 } 1703 1704 /* determine whether to name it with vpd or just make it up */ 1705 /* Marvell Yukon VPD's can freqently be bogus */ 1706 1707 switch (pa->pa_id) { 1708 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1709 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1710 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1711 case PCI_PRODUCT_3COM_3C940: 1712 case PCI_PRODUCT_DLINK_DGE530T: 1713 case PCI_PRODUCT_DLINK_DGE560T: 1714 case PCI_PRODUCT_DLINK_DGE560T_2: 1715 case PCI_PRODUCT_LINKSYS_EG1032: 1716 case PCI_PRODUCT_LINKSYS_EG1064: 1717 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1718 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1719 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1720 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1721 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1722 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1723 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1724 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1725 sc->sk_name = sc->sk_vpd_prodname; 1726 break; 1727 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1728 /* whoops yukon vpd prodname bears no resemblance to reality */ 1729 switch (sc->sk_type) { 1730 case SK_GENESIS: 1731 sc->sk_name = sc->sk_vpd_prodname; 1732 break; 1733 case SK_YUKON: 1734 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1735 break; 1736 case SK_YUKON_LITE: 1737 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1738 break; 1739 case SK_YUKON_LP: 1740 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1741 break; 1742 default: 1743 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1744 } 1745 1746 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1747 1748 if ( sc->sk_type == SK_YUKON ) { 1749 uint32_t flashaddr; 1750 uint8_t testbyte; 1751 1752 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1753 1754 /* test Flash-Address Register */ 1755 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1756 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1757 1758 if (testbyte != 0) { 1759 /* this is yukon lite Rev. A0 */ 1760 sc->sk_type = SK_YUKON_LITE; 1761 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1762 /* restore Flash-Address Register */ 1763 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1764 } 1765 } 1766 break; 1767 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1768 sc->sk_name = sc->sk_vpd_prodname; 1769 break; 1770 default: 1771 sc->sk_name = "Unknown Marvell"; 1772 } 1773 1774 1775 if ( sc->sk_type == SK_YUKON_LITE ) { 1776 switch (sc->sk_rev) { 1777 case SK_YUKON_LITE_REV_A0: 1778 revstr = "A0"; 1779 break; 1780 case SK_YUKON_LITE_REV_A1: 1781 revstr = "A1"; 1782 break; 1783 case SK_YUKON_LITE_REV_A3: 1784 revstr = "A3"; 1785 break; 1786 default: 1787 revstr = ""; 1788 } 1789 } else { 1790 revstr = ""; 1791 } 1792 1793 /* Announce the product name. */ 1794 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1795 sc->sk_name, revstr, sc->sk_rev); 1796 1797 skca.skc_port = SK_PORT_A; 1798 (void)config_found(sc->sk_dev, &skca, skcprint); 1799 1800 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1801 skca.skc_port = SK_PORT_B; 1802 (void)config_found(sc->sk_dev, &skca, skcprint); 1803 } 1804 1805 /* Turn on the 'driver is loaded' LED. */ 1806 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1807 1808 /* skc sysctl setup */ 1809 1810 sc->sk_int_mod = SK_IM_DEFAULT; 1811 sc->sk_int_mod_pending = 0; 1812 1813 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1814 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1815 SYSCTL_DESCR("skc per-controller controls"), 1816 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1817 CTL_EOL)) != 0) { 1818 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1819 goto fail_1; 1820 } 1821 1822 sk_nodenum = node->sysctl_num; 1823 1824 /* interrupt moderation time in usecs */ 1825 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1826 CTLFLAG_READWRITE, 1827 CTLTYPE_INT, "int_mod", 1828 SYSCTL_DESCR("sk interrupt moderation timer"), 1829 sk_sysctl_handler, 0, sc, 1830 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1831 CTL_EOL)) != 0) { 1832 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1833 goto fail_1; 1834 } 1835 1836 if (!pmf_device_register(self, skc_suspend, skc_resume)) 1837 aprint_error_dev(self, "couldn't establish power handler\n"); 1838 1839 return; 1840 1841 fail_1: 1842 pci_intr_disestablish(pc, sc->sk_intrhand); 1843 fail: 1844 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1845 } 1846 1847 int 1848 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1849 { 1850 struct sk_softc *sc = sc_if->sk_softc; 1851 struct sk_tx_desc *f = NULL; 1852 u_int32_t frag, cur, cnt = 0, sk_ctl; 1853 int i; 1854 struct sk_txmap_entry *entry; 1855 bus_dmamap_t txmap; 1856 1857 DPRINTFN(3, ("sk_encap\n")); 1858 1859 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1860 if (entry == NULL) { 1861 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1862 return ENOBUFS; 1863 } 1864 txmap = entry->dmamap; 1865 1866 cur = frag = *txidx; 1867 1868 #ifdef SK_DEBUG 1869 if (skdebug >= 3) 1870 sk_dump_mbuf(m_head); 1871 #endif 1872 1873 /* 1874 * Start packing the mbufs in this chain into 1875 * the fragment pointers. Stop when we run out 1876 * of fragments or hit the end of the mbuf chain. 1877 */ 1878 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1879 BUS_DMA_NOWAIT)) { 1880 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1881 return ENOBUFS; 1882 } 1883 1884 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1885 1886 /* Sync the DMA map. */ 1887 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1888 BUS_DMASYNC_PREWRITE); 1889 1890 for (i = 0; i < txmap->dm_nsegs; i++) { 1891 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1892 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1893 return ENOBUFS; 1894 } 1895 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1896 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1897 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1898 if (cnt == 0) 1899 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1900 else 1901 sk_ctl |= SK_TXCTL_OWN; 1902 f->sk_ctl = htole32(sk_ctl); 1903 cur = frag; 1904 SK_INC(frag, SK_TX_RING_CNT); 1905 cnt++; 1906 } 1907 1908 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1909 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1910 1911 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1912 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1913 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1914 1915 /* Sync descriptors before handing to chip */ 1916 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1917 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1918 1919 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1920 htole32(SK_TXCTL_OWN); 1921 1922 /* Sync first descriptor to hand it off */ 1923 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1924 1925 sc_if->sk_cdata.sk_tx_cnt += cnt; 1926 1927 #ifdef SK_DEBUG 1928 if (skdebug >= 3) { 1929 struct sk_tx_desc *desc; 1930 u_int32_t idx; 1931 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1932 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1933 sk_dump_txdesc(desc, idx); 1934 } 1935 } 1936 #endif 1937 1938 *txidx = frag; 1939 1940 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1941 1942 return 0; 1943 } 1944 1945 void 1946 sk_start(struct ifnet *ifp) 1947 { 1948 struct sk_if_softc *sc_if = ifp->if_softc; 1949 struct sk_softc *sc = sc_if->sk_softc; 1950 struct mbuf *m_head = NULL; 1951 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1952 int pkts = 0; 1953 1954 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1955 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1956 1957 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1958 IFQ_POLL(&ifp->if_snd, m_head); 1959 if (m_head == NULL) 1960 break; 1961 1962 /* 1963 * Pack the data into the transmit ring. If we 1964 * don't have room, set the OACTIVE flag and wait 1965 * for the NIC to drain the ring. 1966 */ 1967 if (sk_encap(sc_if, m_head, &idx)) { 1968 ifp->if_flags |= IFF_OACTIVE; 1969 break; 1970 } 1971 1972 /* now we are committed to transmit the packet */ 1973 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1974 pkts++; 1975 1976 /* 1977 * If there's a BPF listener, bounce a copy of this frame 1978 * to him. 1979 */ 1980 bpf_mtap(ifp, m_head); 1981 } 1982 if (pkts == 0) 1983 return; 1984 1985 /* Transmit */ 1986 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1987 sc_if->sk_cdata.sk_tx_prod = idx; 1988 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1989 1990 /* Set a timeout in case the chip goes out to lunch. */ 1991 ifp->if_timer = 5; 1992 } 1993 } 1994 1995 1996 void 1997 sk_watchdog(struct ifnet *ifp) 1998 { 1999 struct sk_if_softc *sc_if = ifp->if_softc; 2000 2001 /* 2002 * Reclaim first as there is a possibility of losing Tx completion 2003 * interrupts. 2004 */ 2005 sk_txeof(sc_if); 2006 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2007 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 2008 2009 ifp->if_oerrors++; 2010 2011 sk_init(ifp); 2012 } 2013 } 2014 2015 void 2016 sk_shutdown(void *v) 2017 { 2018 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2019 struct sk_softc *sc = sc_if->sk_softc; 2020 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2021 2022 DPRINTFN(2, ("sk_shutdown\n")); 2023 sk_stop(ifp,1); 2024 2025 /* Turn off the 'driver is loaded' LED. */ 2026 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2027 2028 /* 2029 * Reset the GEnesis controller. Doing this should also 2030 * assert the resets on the attached XMAC(s). 2031 */ 2032 sk_reset(sc); 2033 } 2034 2035 void 2036 sk_rxeof(struct sk_if_softc *sc_if) 2037 { 2038 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2039 struct mbuf *m; 2040 struct sk_chain *cur_rx; 2041 struct sk_rx_desc *cur_desc; 2042 int i, cur, total_len = 0; 2043 u_int32_t rxstat, sk_ctl; 2044 bus_dmamap_t dmamap; 2045 2046 i = sc_if->sk_cdata.sk_rx_prod; 2047 2048 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2049 2050 for (;;) { 2051 cur = i; 2052 2053 /* Sync the descriptor */ 2054 SK_CDRXSYNC(sc_if, cur, 2055 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2056 2057 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2058 if (sk_ctl & SK_RXCTL_OWN) { 2059 /* Invalidate the descriptor -- it's not ready yet */ 2060 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2061 sc_if->sk_cdata.sk_rx_prod = i; 2062 break; 2063 } 2064 2065 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2066 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2067 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2068 2069 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2070 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2071 2072 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2073 m = cur_rx->sk_mbuf; 2074 cur_rx->sk_mbuf = NULL; 2075 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2076 2077 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2078 2079 SK_INC(i, SK_RX_RING_CNT); 2080 2081 if (rxstat & XM_RXSTAT_ERRFRAME) { 2082 ifp->if_ierrors++; 2083 sk_newbuf(sc_if, cur, m, dmamap); 2084 continue; 2085 } 2086 2087 /* 2088 * Try to allocate a new jumbo buffer. If that 2089 * fails, copy the packet to mbufs and put the 2090 * jumbo buffer back in the ring so it can be 2091 * re-used. If allocating mbufs fails, then we 2092 * have to drop the packet. 2093 */ 2094 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2095 struct mbuf *m0; 2096 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2097 total_len + ETHER_ALIGN, 0, ifp, NULL); 2098 sk_newbuf(sc_if, cur, m, dmamap); 2099 if (m0 == NULL) { 2100 aprint_error_dev(sc_if->sk_dev, "no receive " 2101 "buffers available -- packet dropped!\n"); 2102 ifp->if_ierrors++; 2103 continue; 2104 } 2105 m_adj(m0, ETHER_ALIGN); 2106 m = m0; 2107 } else { 2108 m->m_pkthdr.rcvif = ifp; 2109 m->m_pkthdr.len = m->m_len = total_len; 2110 } 2111 2112 ifp->if_ipackets++; 2113 2114 bpf_mtap(ifp, m); 2115 /* pass it on. */ 2116 (*ifp->if_input)(ifp, m); 2117 } 2118 } 2119 2120 void 2121 sk_txeof(struct sk_if_softc *sc_if) 2122 { 2123 struct sk_softc *sc = sc_if->sk_softc; 2124 struct sk_tx_desc *cur_tx; 2125 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2126 u_int32_t idx, sk_ctl; 2127 struct sk_txmap_entry *entry; 2128 2129 DPRINTFN(3, ("sk_txeof\n")); 2130 2131 /* 2132 * Go through our tx ring and free mbufs for those 2133 * frames that have been sent. 2134 */ 2135 idx = sc_if->sk_cdata.sk_tx_cons; 2136 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2137 SK_CDTXSYNC(sc_if, idx, 1, 2138 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2139 2140 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2141 sk_ctl = le32toh(cur_tx->sk_ctl); 2142 #ifdef SK_DEBUG 2143 if (skdebug >= 3) 2144 sk_dump_txdesc(cur_tx, idx); 2145 #endif 2146 if (sk_ctl & SK_TXCTL_OWN) { 2147 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2148 break; 2149 } 2150 if (sk_ctl & SK_TXCTL_LASTFRAG) 2151 ifp->if_opackets++; 2152 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2153 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2154 2155 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2156 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2157 2158 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2159 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2160 2161 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2162 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2163 link); 2164 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2165 } 2166 sc_if->sk_cdata.sk_tx_cnt--; 2167 SK_INC(idx, SK_TX_RING_CNT); 2168 } 2169 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2170 ifp->if_timer = 0; 2171 else /* nudge chip to keep tx ring moving */ 2172 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2173 2174 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2175 ifp->if_flags &= ~IFF_OACTIVE; 2176 2177 sc_if->sk_cdata.sk_tx_cons = idx; 2178 } 2179 2180 void 2181 sk_tick(void *xsc_if) 2182 { 2183 struct sk_if_softc *sc_if = xsc_if; 2184 struct mii_data *mii = &sc_if->sk_mii; 2185 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2186 int i; 2187 2188 DPRINTFN(3, ("sk_tick\n")); 2189 2190 if (!(ifp->if_flags & IFF_UP)) 2191 return; 2192 2193 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2194 sk_intr_bcom(sc_if); 2195 return; 2196 } 2197 2198 /* 2199 * According to SysKonnect, the correct way to verify that 2200 * the link has come back up is to poll bit 0 of the GPIO 2201 * register three times. This pin has the signal from the 2202 * link sync pin connected to it; if we read the same link 2203 * state 3 times in a row, we know the link is up. 2204 */ 2205 for (i = 0; i < 3; i++) { 2206 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2207 break; 2208 } 2209 2210 if (i != 3) { 2211 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2212 return; 2213 } 2214 2215 /* Turn the GP0 interrupt back on. */ 2216 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2217 SK_XM_READ_2(sc_if, XM_ISR); 2218 mii_tick(mii); 2219 mii_pollstat(mii); 2220 callout_stop(&sc_if->sk_tick_ch); 2221 } 2222 2223 void 2224 sk_intr_bcom(struct sk_if_softc *sc_if) 2225 { 2226 struct mii_data *mii = &sc_if->sk_mii; 2227 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2228 int status; 2229 2230 2231 DPRINTFN(3, ("sk_intr_bcom\n")); 2232 2233 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2234 2235 /* 2236 * Read the PHY interrupt register to make sure 2237 * we clear any pending interrupts. 2238 */ 2239 status = sk_xmac_miibus_readreg(sc_if->sk_dev, 2240 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2241 2242 if (!(ifp->if_flags & IFF_RUNNING)) { 2243 sk_init_xmac(sc_if); 2244 return; 2245 } 2246 2247 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2248 int lstat; 2249 lstat = sk_xmac_miibus_readreg(sc_if->sk_dev, 2250 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2251 2252 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2253 (void)mii_mediachg(mii); 2254 /* Turn off the link LED. */ 2255 SK_IF_WRITE_1(sc_if, 0, 2256 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2257 sc_if->sk_link = 0; 2258 } else if (status & BRGPHY_ISR_LNK_CHG) { 2259 sk_xmac_miibus_writereg(sc_if->sk_dev, 2260 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2261 mii_tick(mii); 2262 sc_if->sk_link = 1; 2263 /* Turn on the link LED. */ 2264 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2265 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2266 SK_LINKLED_BLINK_OFF); 2267 mii_pollstat(mii); 2268 } else { 2269 mii_tick(mii); 2270 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2271 } 2272 } 2273 2274 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2275 } 2276 2277 void 2278 sk_intr_xmac(struct sk_if_softc *sc_if) 2279 { 2280 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2281 2282 DPRINTFN(3, ("sk_intr_xmac\n")); 2283 2284 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2285 if (status & XM_ISR_GP0_SET) { 2286 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2287 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2288 } 2289 2290 if (status & XM_ISR_AUTONEG_DONE) { 2291 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2292 } 2293 } 2294 2295 if (status & XM_IMR_TX_UNDERRUN) 2296 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2297 2298 if (status & XM_IMR_RX_OVERRUN) 2299 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2300 } 2301 2302 void 2303 sk_intr_yukon(struct sk_if_softc *sc_if) 2304 { 2305 int status; 2306 2307 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2308 2309 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2310 } 2311 2312 int 2313 sk_intr(void *xsc) 2314 { 2315 struct sk_softc *sc = xsc; 2316 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2317 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2318 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2319 u_int32_t status; 2320 int claimed = 0; 2321 2322 if (sc_if0 != NULL) 2323 ifp0 = &sc_if0->sk_ethercom.ec_if; 2324 if (sc_if1 != NULL) 2325 ifp1 = &sc_if1->sk_ethercom.ec_if; 2326 2327 for (;;) { 2328 status = CSR_READ_4(sc, SK_ISSR); 2329 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2330 2331 if (!(status & sc->sk_intrmask)) 2332 break; 2333 2334 claimed = 1; 2335 2336 /* Handle receive interrupts first. */ 2337 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2338 sk_rxeof(sc_if0); 2339 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2340 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2341 } 2342 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2343 sk_rxeof(sc_if1); 2344 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2345 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2346 } 2347 2348 /* Then transmit interrupts. */ 2349 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2350 sk_txeof(sc_if0); 2351 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2352 SK_TXBMU_CLR_IRQ_EOF); 2353 } 2354 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2355 sk_txeof(sc_if1); 2356 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2357 SK_TXBMU_CLR_IRQ_EOF); 2358 } 2359 2360 /* Then MAC interrupts. */ 2361 if (sc_if0 && (status & SK_ISR_MAC1) && 2362 (ifp0->if_flags & IFF_RUNNING)) { 2363 if (sc->sk_type == SK_GENESIS) 2364 sk_intr_xmac(sc_if0); 2365 else 2366 sk_intr_yukon(sc_if0); 2367 } 2368 2369 if (sc_if1 && (status & SK_ISR_MAC2) && 2370 (ifp1->if_flags & IFF_RUNNING)) { 2371 if (sc->sk_type == SK_GENESIS) 2372 sk_intr_xmac(sc_if1); 2373 else 2374 sk_intr_yukon(sc_if1); 2375 2376 } 2377 2378 if (status & SK_ISR_EXTERNAL_REG) { 2379 if (sc_if0 != NULL && 2380 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2381 sk_intr_bcom(sc_if0); 2382 2383 if (sc_if1 != NULL && 2384 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2385 sk_intr_bcom(sc_if1); 2386 } 2387 } 2388 2389 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2390 2391 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2392 sk_start(ifp0); 2393 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2394 sk_start(ifp1); 2395 2396 #if NRND > 0 2397 if (RND_ENABLED(&sc->rnd_source)) 2398 rnd_add_uint32(&sc->rnd_source, status); 2399 #endif 2400 2401 if (sc->sk_int_mod_pending) 2402 sk_update_int_mod(sc); 2403 2404 return claimed; 2405 } 2406 2407 void 2408 sk_init_xmac(struct sk_if_softc *sc_if) 2409 { 2410 struct sk_softc *sc = sc_if->sk_softc; 2411 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2412 static const struct sk_bcom_hack bhack[] = { 2413 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2414 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2415 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2416 { 0, 0 } }; 2417 2418 DPRINTFN(1, ("sk_init_xmac\n")); 2419 2420 /* Unreset the XMAC. */ 2421 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2422 DELAY(1000); 2423 2424 /* Reset the XMAC's internal state. */ 2425 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2426 2427 /* Save the XMAC II revision */ 2428 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2429 2430 /* 2431 * Perform additional initialization for external PHYs, 2432 * namely for the 1000baseTX cards that use the XMAC's 2433 * GMII mode. 2434 */ 2435 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2436 int i = 0; 2437 u_int32_t val; 2438 2439 /* Take PHY out of reset. */ 2440 val = sk_win_read_4(sc, SK_GPIO); 2441 if (sc_if->sk_port == SK_PORT_A) 2442 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2443 else 2444 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2445 sk_win_write_4(sc, SK_GPIO, val); 2446 2447 /* Enable GMII mode on the XMAC. */ 2448 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2449 2450 sk_xmac_miibus_writereg(sc_if->sk_dev, 2451 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2452 DELAY(10000); 2453 sk_xmac_miibus_writereg(sc_if->sk_dev, 2454 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2455 2456 /* 2457 * Early versions of the BCM5400 apparently have 2458 * a bug that requires them to have their reserved 2459 * registers initialized to some magic values. I don't 2460 * know what the numbers do, I'm just the messenger. 2461 */ 2462 if (sk_xmac_miibus_readreg(sc_if->sk_dev, 2463 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2464 while (bhack[i].reg) { 2465 sk_xmac_miibus_writereg(sc_if->sk_dev, 2466 SK_PHYADDR_BCOM, bhack[i].reg, 2467 bhack[i].val); 2468 i++; 2469 } 2470 } 2471 } 2472 2473 /* Set station address */ 2474 SK_XM_WRITE_2(sc_if, XM_PAR0, 2475 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2476 SK_XM_WRITE_2(sc_if, XM_PAR1, 2477 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2478 SK_XM_WRITE_2(sc_if, XM_PAR2, 2479 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2480 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2481 2482 if (ifp->if_flags & IFF_PROMISC) 2483 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2484 else 2485 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2486 2487 if (ifp->if_flags & IFF_BROADCAST) 2488 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2489 else 2490 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2491 2492 /* We don't need the FCS appended to the packet. */ 2493 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2494 2495 /* We want short frames padded to 60 bytes. */ 2496 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2497 2498 /* 2499 * Enable the reception of all error frames. This is is 2500 * a necessary evil due to the design of the XMAC. The 2501 * XMAC's receive FIFO is only 8K in size, however jumbo 2502 * frames can be up to 9000 bytes in length. When bad 2503 * frame filtering is enabled, the XMAC's RX FIFO operates 2504 * in 'store and forward' mode. For this to work, the 2505 * entire frame has to fit into the FIFO, but that means 2506 * that jumbo frames larger than 8192 bytes will be 2507 * truncated. Disabling all bad frame filtering causes 2508 * the RX FIFO to operate in streaming mode, in which 2509 * case the XMAC will start transfering frames out of the 2510 * RX FIFO as soon as the FIFO threshold is reached. 2511 */ 2512 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2513 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2514 XM_MODE_RX_INRANGELEN); 2515 2516 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2517 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2518 else 2519 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2520 2521 /* 2522 * Bump up the transmit threshold. This helps hold off transmit 2523 * underruns when we're blasting traffic from both ports at once. 2524 */ 2525 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2526 2527 /* Set multicast filter */ 2528 sk_setmulti(sc_if); 2529 2530 /* Clear and enable interrupts */ 2531 SK_XM_READ_2(sc_if, XM_ISR); 2532 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2533 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2534 else 2535 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2536 2537 /* Configure MAC arbiter */ 2538 switch (sc_if->sk_xmac_rev) { 2539 case XM_XMAC_REV_B2: 2540 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2541 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2542 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2543 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2544 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2545 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2546 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2547 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2548 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2549 break; 2550 case XM_XMAC_REV_C1: 2551 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2552 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2553 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2554 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2555 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2556 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2557 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2558 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2559 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2560 break; 2561 default: 2562 break; 2563 } 2564 sk_win_write_2(sc, SK_MACARB_CTL, 2565 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2566 2567 sc_if->sk_link = 1; 2568 } 2569 2570 void sk_init_yukon(struct sk_if_softc *sc_if) 2571 { 2572 u_int32_t /*mac, */phy; 2573 u_int16_t reg; 2574 struct sk_softc *sc; 2575 int i; 2576 2577 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2578 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2579 2580 sc = sc_if->sk_softc; 2581 if (sc->sk_type == SK_YUKON_LITE && 2582 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2583 /* Take PHY out of reset. */ 2584 sk_win_write_4(sc, SK_GPIO, 2585 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2586 } 2587 2588 2589 /* GMAC and GPHY Reset */ 2590 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2591 2592 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2593 2594 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2595 DELAY(1000); 2596 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2597 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2598 DELAY(1000); 2599 2600 2601 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2602 2603 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2604 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2605 2606 switch (sc_if->sk_softc->sk_pmd) { 2607 case IFM_1000_SX: 2608 case IFM_1000_LX: 2609 phy |= SK_GPHY_FIBER; 2610 break; 2611 2612 case IFM_1000_CX: 2613 case IFM_1000_T: 2614 phy |= SK_GPHY_COPPER; 2615 break; 2616 } 2617 2618 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2619 2620 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2621 DELAY(1000); 2622 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2623 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2624 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2625 2626 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2627 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2628 2629 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2630 2631 /* unused read of the interrupt source register */ 2632 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2633 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2634 2635 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2636 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2637 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2638 2639 /* MIB Counter Clear Mode set */ 2640 reg |= YU_PAR_MIB_CLR; 2641 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2642 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2643 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2644 2645 /* MIB Counter Clear Mode clear */ 2646 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2647 reg &= ~YU_PAR_MIB_CLR; 2648 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2649 2650 /* receive control reg */ 2651 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2652 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2653 YU_RCR_CRCR); 2654 2655 /* transmit parameter register */ 2656 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2657 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2658 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2659 2660 /* serial mode register */ 2661 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2662 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2663 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2664 YU_SMR_IPG_DATA(0x1e)); 2665 2666 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2667 /* Setup Yukon's address */ 2668 for (i = 0; i < 3; i++) { 2669 /* Write Source Address 1 (unicast filter) */ 2670 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2671 sc_if->sk_enaddr[i * 2] | 2672 sc_if->sk_enaddr[i * 2 + 1] << 8); 2673 } 2674 2675 for (i = 0; i < 3; i++) { 2676 reg = sk_win_read_2(sc_if->sk_softc, 2677 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2678 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2679 } 2680 2681 /* Set multicast filter */ 2682 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2683 sk_setmulti(sc_if); 2684 2685 /* enable interrupt mask for counter overflows */ 2686 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2687 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2688 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2689 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2690 2691 /* Configure RX MAC FIFO */ 2692 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2693 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2694 2695 /* Configure TX MAC FIFO */ 2696 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2697 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2698 2699 DPRINTFN(6, ("sk_init_yukon: end\n")); 2700 } 2701 2702 /* 2703 * Note that to properly initialize any part of the GEnesis chip, 2704 * you first have to take it out of reset mode. 2705 */ 2706 int 2707 sk_init(struct ifnet *ifp) 2708 { 2709 struct sk_if_softc *sc_if = ifp->if_softc; 2710 struct sk_softc *sc = sc_if->sk_softc; 2711 struct mii_data *mii = &sc_if->sk_mii; 2712 int rc = 0, s; 2713 u_int32_t imr, imtimer_ticks; 2714 2715 DPRINTFN(1, ("sk_init\n")); 2716 2717 s = splnet(); 2718 2719 if (ifp->if_flags & IFF_RUNNING) { 2720 splx(s); 2721 return 0; 2722 } 2723 2724 /* Cancel pending I/O and free all RX/TX buffers. */ 2725 sk_stop(ifp,0); 2726 2727 if (sc->sk_type == SK_GENESIS) { 2728 /* Configure LINK_SYNC LED */ 2729 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2730 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2731 SK_LINKLED_LINKSYNC_ON); 2732 2733 /* Configure RX LED */ 2734 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2735 SK_RXLEDCTL_COUNTER_START); 2736 2737 /* Configure TX LED */ 2738 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2739 SK_TXLEDCTL_COUNTER_START); 2740 } 2741 2742 /* Configure I2C registers */ 2743 2744 /* Configure XMAC(s) */ 2745 switch (sc->sk_type) { 2746 case SK_GENESIS: 2747 sk_init_xmac(sc_if); 2748 break; 2749 case SK_YUKON: 2750 case SK_YUKON_LITE: 2751 case SK_YUKON_LP: 2752 sk_init_yukon(sc_if); 2753 break; 2754 } 2755 if ((rc = mii_mediachg(mii)) == ENXIO) 2756 rc = 0; 2757 else if (rc != 0) 2758 goto out; 2759 2760 if (sc->sk_type == SK_GENESIS) { 2761 /* Configure MAC FIFOs */ 2762 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2763 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2764 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2765 2766 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2767 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2768 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2769 } 2770 2771 /* Configure transmit arbiter(s) */ 2772 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2773 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2774 2775 /* Configure RAMbuffers */ 2776 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2777 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2778 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2779 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2780 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2781 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2782 2783 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2784 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2785 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2786 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2787 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2788 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2789 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2790 2791 /* Configure BMUs */ 2792 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2793 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2794 SK_RX_RING_ADDR(sc_if, 0)); 2795 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2796 2797 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2798 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2799 SK_TX_RING_ADDR(sc_if, 0)); 2800 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2801 2802 /* Init descriptors */ 2803 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2804 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2805 "memory for rx buffers\n"); 2806 sk_stop(ifp,0); 2807 splx(s); 2808 return ENOBUFS; 2809 } 2810 2811 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2812 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2813 "memory for tx buffers\n"); 2814 sk_stop(ifp,0); 2815 splx(s); 2816 return ENOBUFS; 2817 } 2818 2819 /* Set interrupt moderation if changed via sysctl. */ 2820 switch (sc->sk_type) { 2821 case SK_GENESIS: 2822 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2823 break; 2824 case SK_YUKON_EC: 2825 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2826 break; 2827 default: 2828 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2829 } 2830 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2831 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2832 sk_win_write_4(sc, SK_IMTIMERINIT, 2833 SK_IM_USECS(sc->sk_int_mod)); 2834 aprint_verbose_dev(sc->sk_dev, 2835 "interrupt moderation is %d us\n", sc->sk_int_mod); 2836 } 2837 2838 /* Configure interrupt handling */ 2839 CSR_READ_4(sc, SK_ISSR); 2840 if (sc_if->sk_port == SK_PORT_A) 2841 sc->sk_intrmask |= SK_INTRS1; 2842 else 2843 sc->sk_intrmask |= SK_INTRS2; 2844 2845 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2846 2847 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2848 2849 /* Start BMUs. */ 2850 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2851 2852 if (sc->sk_type == SK_GENESIS) { 2853 /* Enable XMACs TX and RX state machines */ 2854 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2855 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2856 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2857 } 2858 2859 if (SK_YUKON_FAMILY(sc->sk_type)) { 2860 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2861 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2862 #if 0 2863 /* XXX disable 100Mbps and full duplex mode? */ 2864 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2865 #endif 2866 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2867 } 2868 2869 2870 ifp->if_flags |= IFF_RUNNING; 2871 ifp->if_flags &= ~IFF_OACTIVE; 2872 2873 out: 2874 splx(s); 2875 return rc; 2876 } 2877 2878 void 2879 sk_stop(struct ifnet *ifp, int disable) 2880 { 2881 struct sk_if_softc *sc_if = ifp->if_softc; 2882 struct sk_softc *sc = sc_if->sk_softc; 2883 int i; 2884 2885 DPRINTFN(1, ("sk_stop\n")); 2886 2887 callout_stop(&sc_if->sk_tick_ch); 2888 2889 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2890 u_int32_t val; 2891 2892 /* Put PHY back into reset. */ 2893 val = sk_win_read_4(sc, SK_GPIO); 2894 if (sc_if->sk_port == SK_PORT_A) { 2895 val |= SK_GPIO_DIR0; 2896 val &= ~SK_GPIO_DAT0; 2897 } else { 2898 val |= SK_GPIO_DIR2; 2899 val &= ~SK_GPIO_DAT2; 2900 } 2901 sk_win_write_4(sc, SK_GPIO, val); 2902 } 2903 2904 /* Turn off various components of this interface. */ 2905 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2906 switch (sc->sk_type) { 2907 case SK_GENESIS: 2908 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2909 SK_TXMACCTL_XMAC_RESET); 2910 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2911 break; 2912 case SK_YUKON: 2913 case SK_YUKON_LITE: 2914 case SK_YUKON_LP: 2915 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2916 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2917 break; 2918 } 2919 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2920 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2921 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2922 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2923 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2924 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2925 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2926 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2927 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2928 2929 /* Disable interrupts */ 2930 if (sc_if->sk_port == SK_PORT_A) 2931 sc->sk_intrmask &= ~SK_INTRS1; 2932 else 2933 sc->sk_intrmask &= ~SK_INTRS2; 2934 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2935 2936 SK_XM_READ_2(sc_if, XM_ISR); 2937 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2938 2939 /* Free RX and TX mbufs still in the queues. */ 2940 for (i = 0; i < SK_RX_RING_CNT; i++) { 2941 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2942 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2943 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2944 } 2945 } 2946 2947 for (i = 0; i < SK_TX_RING_CNT; i++) { 2948 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2949 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2950 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2951 } 2952 } 2953 2954 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2955 } 2956 2957 /* Power Management Framework */ 2958 2959 static bool 2960 skc_suspend(device_t dv, const pmf_qual_t *qual) 2961 { 2962 struct sk_softc *sc = device_private(dv); 2963 2964 DPRINTFN(2, ("skc_suspend\n")); 2965 2966 /* Turn off the driver is loaded LED */ 2967 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2968 2969 return true; 2970 } 2971 2972 static bool 2973 skc_resume(device_t dv, const pmf_qual_t *qual) 2974 { 2975 struct sk_softc *sc = device_private(dv); 2976 2977 DPRINTFN(2, ("skc_resume\n")); 2978 2979 sk_reset(sc); 2980 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2981 2982 return true; 2983 } 2984 2985 static bool 2986 sk_resume(device_t dv, const pmf_qual_t *qual) 2987 { 2988 struct sk_if_softc *sc_if = device_private(dv); 2989 2990 sk_init_yukon(sc_if); 2991 return true; 2992 } 2993 2994 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 2995 skc_probe, skc_attach, NULL, NULL); 2996 2997 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 2998 sk_probe, sk_attach, NULL, NULL); 2999 3000 #ifdef SK_DEBUG 3001 void 3002 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 3003 { 3004 #define DESC_PRINT(X) \ 3005 if (X) \ 3006 printf("txdesc[%d]." #X "=%#x\n", \ 3007 idx, X); 3008 3009 DESC_PRINT(le32toh(desc->sk_ctl)); 3010 DESC_PRINT(le32toh(desc->sk_next)); 3011 DESC_PRINT(le32toh(desc->sk_data_lo)); 3012 DESC_PRINT(le32toh(desc->sk_data_hi)); 3013 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 3014 DESC_PRINT(le16toh(desc->sk_rsvd0)); 3015 DESC_PRINT(le16toh(desc->sk_csum_startval)); 3016 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 3017 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 3018 DESC_PRINT(le16toh(desc->sk_rsvd1)); 3019 #undef PRINT 3020 } 3021 3022 void 3023 sk_dump_bytes(const char *data, int len) 3024 { 3025 int c, i, j; 3026 3027 for (i = 0; i < len; i += 16) { 3028 printf("%08x ", i); 3029 c = len - i; 3030 if (c > 16) c = 16; 3031 3032 for (j = 0; j < c; j++) { 3033 printf("%02x ", data[i + j] & 0xff); 3034 if ((j & 0xf) == 7 && j > 0) 3035 printf(" "); 3036 } 3037 3038 for (; j < 16; j++) 3039 printf(" "); 3040 printf(" "); 3041 3042 for (j = 0; j < c; j++) { 3043 int ch = data[i + j] & 0xff; 3044 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3045 } 3046 3047 printf("\n"); 3048 3049 if (c < 16) 3050 break; 3051 } 3052 } 3053 3054 void 3055 sk_dump_mbuf(struct mbuf *m) 3056 { 3057 int count = m->m_pkthdr.len; 3058 3059 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3060 3061 while (count > 0 && m) { 3062 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3063 m, m->m_data, m->m_len); 3064 sk_dump_bytes(mtod(m, char *), m->m_len); 3065 3066 count -= m->m_len; 3067 m = m->m_next; 3068 } 3069 } 3070 #endif 3071 3072 static int 3073 sk_sysctl_handler(SYSCTLFN_ARGS) 3074 { 3075 int error, t; 3076 struct sysctlnode node; 3077 struct sk_softc *sc; 3078 3079 node = *rnode; 3080 sc = node.sysctl_data; 3081 t = sc->sk_int_mod; 3082 node.sysctl_data = &t; 3083 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3084 if (error || newp == NULL) 3085 return error; 3086 3087 if (t < SK_IM_MIN || t > SK_IM_MAX) 3088 return EINVAL; 3089 3090 /* update the softc with sysctl-changed value, and mark 3091 for hardware update */ 3092 sc->sk_int_mod = t; 3093 sc->sk_int_mod_pending = 1; 3094 return 0; 3095 } 3096 3097 /* 3098 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3099 * set up in skc_attach() 3100 */ 3101 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3102 { 3103 int rc; 3104 const struct sysctlnode *node; 3105 3106 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3107 0, CTLTYPE_NODE, "hw", NULL, 3108 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3109 goto err; 3110 } 3111 3112 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3113 0, CTLTYPE_NODE, "sk", 3114 SYSCTL_DESCR("sk interface controls"), 3115 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3116 goto err; 3117 } 3118 3119 sk_root_num = node->sysctl_num; 3120 return; 3121 3122 err: 3123 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3124 } 3125
Indexes created Tue Sep 23 07:09:52 GMT 2025