if_sk.c revision 1.7.2.3.2.2
1 /* $NetBSD: if_sk.c,v 1.7.2.3.2.2 2005/01/24 21:42:31 he Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 126 #include <sys/param.h> 127 #include <sys/systm.h> 128 #include <sys/sockio.h> 129 #include <sys/mbuf.h> 130 #include <sys/malloc.h> 131 #include <sys/kernel.h> 132 #include <sys/socket.h> 133 #include <sys/device.h> 134 #include <sys/queue.h> 135 #include <sys/callout.h> 136 137 #include <net/if.h> 138 #include <net/if_dl.h> 139 #include <net/if_types.h> 140 141 #ifdef INET 142 #include <netinet/in.h> 143 #include <netinet/in_systm.h> 144 #include <netinet/in_var.h> 145 #include <netinet/ip.h> 146 #include <netinet/if_ether.h> 147 #endif 148 149 #include <net/if_media.h> 150 151 #if NBPFILTER > 0 152 #include <net/bpf.h> 153 #endif 154 155 #include <dev/mii/mii.h> 156 #include <dev/mii/miivar.h> 157 #include <dev/mii/brgphyreg.h> 158 159 #include <dev/pci/pcireg.h> 160 #include <dev/pci/pcivar.h> 161 #include <dev/pci/pcidevs.h> 162 163 #define SK_VERBOSE 164 /* #define SK_USEIOSPACE */ 165 166 #include <dev/pci/if_skreg.h> 167 #include <dev/pci/if_skvar.h> 168 169 int skc_probe(struct device *, struct cfdata *, void *); 170 void skc_attach(struct device *, struct device *self, void *aux); 171 int sk_probe(struct device *, struct cfdata *, void *); 172 void sk_attach(struct device *, struct device *self, void *aux); 173 int skcprint(void *, const char *); 174 int sk_intr(void *); 175 void sk_intr_bcom(struct sk_if_softc *); 176 void sk_intr_xmac(struct sk_if_softc *); 177 void sk_intr_yukon(struct sk_if_softc *); 178 void sk_rxeof(struct sk_if_softc *); 179 void sk_txeof(struct sk_if_softc *); 180 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 181 void sk_start(struct ifnet *); 182 int sk_ioctl(struct ifnet *, u_long, caddr_t); 183 int sk_init(struct ifnet *); 184 void sk_init_xmac(struct sk_if_softc *); 185 void sk_init_yukon(struct sk_if_softc *); 186 void sk_stop(struct ifnet *, int); 187 void sk_watchdog(struct ifnet *); 188 void sk_shutdown(void *); 189 int sk_ifmedia_upd(struct ifnet *); 190 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 191 void sk_reset(struct sk_softc *); 192 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 193 int sk_init_rx_ring(struct sk_if_softc *); 194 int sk_init_tx_ring(struct sk_if_softc *); 195 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 196 void sk_vpd_read_res(struct sk_softc *, 197 struct vpd_res *, int); 198 void sk_vpd_read(struct sk_softc *); 199 200 int sk_xmac_miibus_readreg(struct device *, int, int); 201 void sk_xmac_miibus_writereg(struct device *, int, int, int); 202 void sk_xmac_miibus_statchg(struct device *); 203 204 int sk_marv_miibus_readreg(struct device *, int, int); 205 void sk_marv_miibus_writereg(struct device *, int, int, int); 206 void sk_marv_miibus_statchg(struct device *); 207 208 u_int32_t sk_xmac_hash(caddr_t); 209 u_int32_t sk_yukon_hash(caddr_t); 210 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 211 void sk_setmulti(struct sk_if_softc *); 212 void sk_tick(void *); 213 214 /* #define SK_DEBUG 2 */ 215 #ifdef SK_DEBUG 216 #define DPRINTF(x) if (skdebug) printf x 217 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 218 int skdebug = SK_DEBUG; 219 220 void sk_dump_txdesc(struct sk_tx_desc *, int); 221 void sk_dump_mbuf(struct mbuf *); 222 void sk_dump_bytes(const char *, int); 223 #else 224 #define DPRINTF(x) 225 #define DPRINTFN(n,x) 226 #endif 227 228 #define SK_SETBIT(sc, reg, x) \ 229 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 230 231 #define SK_CLRBIT(sc, reg, x) \ 232 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 233 234 #define SK_WIN_SETBIT_4(sc, reg, x) \ 235 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 236 237 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 238 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 239 240 #define SK_WIN_SETBIT_2(sc, reg, x) \ 241 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 242 243 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 244 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 245 246 /* supported device vendors */ 247 static const struct sk_product { 248 pci_vendor_id_t sk_vendor; 249 pci_product_id_t sk_product; 250 } sk_products[] = { 251 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 252 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 253 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, }, 254 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 255 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 256 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 257 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_SKNET, }, 258 { 0, 0, } 259 }; 260 261 static inline u_int32_t 262 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 263 { 264 #ifdef SK_USEIOSPACE 265 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 266 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 267 #else 268 return CSR_READ_4(sc, reg); 269 #endif 270 } 271 272 static inline u_int16_t 273 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 274 { 275 #ifdef SK_USEIOSPACE 276 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 277 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 278 #else 279 return CSR_READ_2(sc, reg); 280 #endif 281 } 282 283 static inline u_int8_t 284 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 285 { 286 #ifdef SK_USEIOSPACE 287 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 288 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 289 #else 290 return CSR_READ_1(sc, reg); 291 #endif 292 } 293 294 static inline void 295 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 296 { 297 #ifdef SK_USEIOSPACE 298 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 299 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 300 #else 301 CSR_WRITE_4(sc, reg, x); 302 #endif 303 } 304 305 static inline void 306 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 307 { 308 #ifdef SK_USEIOSPACE 309 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 310 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 311 #else 312 CSR_WRITE_2(sc, reg, x); 313 #endif 314 } 315 316 static inline void 317 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 318 { 319 #ifdef SK_USEIOSPACE 320 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 321 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 322 #else 323 CSR_WRITE_1(sc, reg, x); 324 #endif 325 } 326 327 /* 328 * The VPD EEPROM contains Vital Product Data, as suggested in 329 * the PCI 2.1 specification. The VPD data is separared into areas 330 * denoted by resource IDs. The SysKonnect VPD contains an ID string 331 * resource (the name of the adapter), a read-only area resource 332 * containing various key/data fields and a read/write area which 333 * can be used to store asset management information or log messages. 334 * We read the ID string and read-only into buffers attached to 335 * the controller softc structure for later use. At the moment, 336 * we only use the ID string during sk_attach(). 337 */ 338 u_int8_t 339 sk_vpd_readbyte(struct sk_softc *sc, int addr) 340 { 341 int i; 342 343 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 344 for (i = 0; i < SK_TIMEOUT; i++) { 345 DELAY(1); 346 if (sk_win_read_2(sc, 347 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 348 break; 349 } 350 351 if (i == SK_TIMEOUT) 352 return(0); 353 354 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 355 } 356 357 void 358 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 359 { 360 int i; 361 u_int8_t *ptr; 362 363 ptr = (u_int8_t *)res; 364 for (i = 0; i < sizeof(struct vpd_res); i++) 365 ptr[i] = sk_vpd_readbyte(sc, i + addr); 366 } 367 368 void 369 sk_vpd_read(struct sk_softc *sc) 370 { 371 int pos = 0, i; 372 struct vpd_res res; 373 374 if (sc->sk_vpd_prodname != NULL) 375 free(sc->sk_vpd_prodname, M_DEVBUF); 376 if (sc->sk_vpd_readonly != NULL) 377 free(sc->sk_vpd_readonly, M_DEVBUF); 378 sc->sk_vpd_prodname = NULL; 379 sc->sk_vpd_readonly = NULL; 380 381 sk_vpd_read_res(sc, &res, pos); 382 383 if (res.vr_id != VPD_RES_ID) { 384 printf("%s: bad VPD resource id: expected %x got %x\n", 385 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 386 return; 387 } 388 389 pos += sizeof(res); 390 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 391 if (sc->sk_vpd_prodname == NULL) 392 panic("sk_vpd_read"); 393 for (i = 0; i < res.vr_len; i++) 394 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 395 sc->sk_vpd_prodname[i] = '\0'; 396 pos += i; 397 398 sk_vpd_read_res(sc, &res, pos); 399 400 if (res.vr_id != VPD_RES_READ) { 401 printf("%s: bad VPD resource id: expected %x got %x\n", 402 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 403 return; 404 } 405 406 pos += sizeof(res); 407 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 408 if (sc->sk_vpd_readonly == NULL) 409 panic("sk_vpd_read"); 410 for (i = 0; i < res.vr_len ; i++) 411 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 412 } 413 414 int 415 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 416 { 417 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 418 int i; 419 420 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 421 422 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 423 return(0); 424 425 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 426 SK_XM_READ_2(sc_if, XM_PHY_DATA); 427 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 428 for (i = 0; i < SK_TIMEOUT; i++) { 429 DELAY(1); 430 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 431 XM_MMUCMD_PHYDATARDY) 432 break; 433 } 434 435 if (i == SK_TIMEOUT) { 436 printf("%s: phy failed to come ready\n", 437 sc_if->sk_dev.dv_xname); 438 return(0); 439 } 440 } 441 DELAY(1); 442 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 443 } 444 445 void 446 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 447 { 448 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 449 int i; 450 451 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 452 453 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 454 for (i = 0; i < SK_TIMEOUT; i++) { 455 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 456 break; 457 } 458 459 if (i == SK_TIMEOUT) { 460 printf("%s: phy failed to come ready\n", 461 sc_if->sk_dev.dv_xname); 462 return; 463 } 464 465 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 466 for (i = 0; i < SK_TIMEOUT; i++) { 467 DELAY(1); 468 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 469 break; 470 } 471 472 if (i == SK_TIMEOUT) 473 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 474 } 475 476 void 477 sk_xmac_miibus_statchg(struct device *dev) 478 { 479 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 480 struct mii_data *mii = &sc_if->sk_mii; 481 482 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 483 484 /* 485 * If this is a GMII PHY, manually set the XMAC's 486 * duplex mode accordingly. 487 */ 488 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 489 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 490 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 491 } else { 492 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 493 } 494 } 495 } 496 497 int 498 sk_marv_miibus_readreg(dev, phy, reg) 499 struct device *dev; 500 int phy, reg; 501 { 502 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 503 u_int16_t val; 504 int i; 505 506 if (phy != 0 || 507 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 508 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 509 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 510 phy, reg)); 511 return(0); 512 } 513 514 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 515 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 516 517 for (i = 0; i < SK_TIMEOUT; i++) { 518 DELAY(1); 519 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 520 if (val & YU_SMICR_READ_VALID) 521 break; 522 } 523 524 if (i == SK_TIMEOUT) { 525 printf("%s: phy failed to come ready\n", 526 sc_if->sk_dev.dv_xname); 527 return 0; 528 } 529 530 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 531 SK_TIMEOUT)); 532 533 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 534 535 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 536 phy, reg, val)); 537 538 return val; 539 } 540 541 void 542 sk_marv_miibus_writereg(dev, phy, reg, val) 543 struct device *dev; 544 int phy, reg, val; 545 { 546 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 547 int i; 548 549 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 550 phy, reg, val)); 551 552 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 553 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 554 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 555 556 for (i = 0; i < SK_TIMEOUT; i++) { 557 DELAY(1); 558 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 559 break; 560 } 561 } 562 563 void 564 sk_marv_miibus_statchg(dev) 565 struct device *dev; 566 { 567 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 568 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 569 } 570 571 #define SK_HASH_BITS 6 572 573 u_int32_t 574 sk_xmac_hash(caddr_t addr) 575 { 576 u_int32_t crc; 577 578 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 579 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 580 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 581 return (crc); 582 } 583 584 u_int32_t 585 sk_yukon_hash(caddr_t addr) 586 { 587 u_int32_t crc; 588 589 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 590 crc &= ((1 << SK_HASH_BITS) - 1); 591 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 592 return (crc); 593 } 594 595 void 596 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 597 { 598 int base = XM_RXFILT_ENTRY(slot); 599 600 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 601 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 602 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 603 } 604 605 void 606 sk_setmulti(struct sk_if_softc *sc_if) 607 { 608 struct sk_softc *sc = sc_if->sk_softc; 609 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 610 u_int32_t hashes[2] = { 0, 0 }; 611 int h = 0, i; 612 struct ethercom *ec = &sc_if->sk_ethercom; 613 struct ether_multi *enm; 614 struct ether_multistep step; 615 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 616 617 /* First, zot all the existing filters. */ 618 switch(sc->sk_type) { 619 case SK_GENESIS: 620 for (i = 1; i < XM_RXFILT_MAX; i++) 621 sk_setfilt(sc_if, (caddr_t)&dummy, i); 622 623 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 624 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 625 break; 626 case SK_YUKON: 627 case SK_YUKON_LITE: 628 case SK_YUKON_LP: 629 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 630 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 631 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 632 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 633 break; 634 } 635 636 /* Now program new ones. */ 637 allmulti: 638 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 639 hashes[0] = 0xFFFFFFFF; 640 hashes[1] = 0xFFFFFFFF; 641 } else { 642 i = 1; 643 /* First find the tail of the list. */ 644 ETHER_FIRST_MULTI(step, ec, enm); 645 while (enm != NULL) { 646 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 647 ETHER_ADDR_LEN)) { 648 ifp->if_flags |= IFF_ALLMULTI; 649 goto allmulti; 650 } 651 DPRINTFN(2,("multicast address %s\n", 652 ether_sprintf(enm->enm_addrlo))); 653 /* 654 * Program the first XM_RXFILT_MAX multicast groups 655 * into the perfect filter. For all others, 656 * use the hash table. 657 */ 658 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 659 sk_setfilt(sc_if, enm->enm_addrlo, i); 660 i++; 661 } 662 else { 663 switch (sc->sk_type) { 664 case SK_GENESIS: 665 h = sk_xmac_hash(enm->enm_addrlo); 666 break; 667 case SK_YUKON: 668 case SK_YUKON_LITE: 669 case SK_YUKON_LP: 670 h = sk_yukon_hash(enm->enm_addrlo); 671 break; 672 } 673 if (h < 32) 674 hashes[0] |= (1 << h); 675 else 676 hashes[1] |= (1 << (h - 32)); 677 } 678 679 ETHER_NEXT_MULTI(step, enm); 680 } 681 } 682 683 switch(sc->sk_type) { 684 case SK_GENESIS: 685 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 686 XM_MODE_RX_USE_PERFECT); 687 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 688 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 689 break; 690 case SK_YUKON: 691 case SK_YUKON_LITE: 692 case SK_YUKON_LP: 693 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 694 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 695 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 696 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 697 break; 698 } 699 } 700 701 int 702 sk_init_rx_ring(struct sk_if_softc *sc_if) 703 { 704 struct sk_chain_data *cd = &sc_if->sk_cdata; 705 struct sk_ring_data *rd = sc_if->sk_rdata; 706 int i; 707 708 bzero((char *)rd->sk_rx_ring, 709 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 710 711 for (i = 0; i < SK_RX_RING_CNT; i++) { 712 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 713 if (i == (SK_RX_RING_CNT - 1)) { 714 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 715 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 716 } else { 717 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 718 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 719 } 720 } 721 722 for (i = 0; i < SK_RX_RING_CNT; i++) { 723 if (sk_newbuf(sc_if, i, NULL, NULL) == ENOBUFS) { 724 printf("%s: failed alloc of %dth mbuf\n", 725 sc_if->sk_dev.dv_xname, i); 726 return(ENOBUFS); 727 } 728 } 729 sc_if->sk_cdata.sk_rx_prod = 0; 730 sc_if->sk_cdata.sk_rx_cons = 0; 731 732 return(0); 733 } 734 735 int 736 sk_init_tx_ring(struct sk_if_softc *sc_if) 737 { 738 struct sk_chain_data *cd = &sc_if->sk_cdata; 739 struct sk_ring_data *rd = sc_if->sk_rdata; 740 int i; 741 742 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 743 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 744 745 for (i = 0; i < SK_TX_RING_CNT; i++) { 746 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 747 if (i == (SK_TX_RING_CNT - 1)) { 748 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 749 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 750 } else { 751 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 752 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 753 } 754 } 755 756 sc_if->sk_cdata.sk_tx_prod = 0; 757 sc_if->sk_cdata.sk_tx_cons = 0; 758 sc_if->sk_cdata.sk_tx_cnt = 0; 759 760 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 761 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 762 763 return (0); 764 } 765 766 int 767 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 768 bus_dmamap_t dmamap) 769 { 770 struct sk_softc *sc = sc_if->sk_softc; 771 struct mbuf *m_new = NULL; 772 struct sk_chain *c; 773 struct sk_rx_desc *r; 774 775 if (dmamap == NULL) { 776 /* if (m) panic() */ 777 778 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES, 779 0, BUS_DMA_NOWAIT, &dmamap)) { 780 printf("%s: can't create recv map\n", 781 sc_if->sk_dev.dv_xname); 782 return(ENOMEM); 783 } 784 } else if (m == NULL) 785 bus_dmamap_unload(sc->sc_dmatag, dmamap); 786 787 sc_if->sk_cdata.sk_rx_map[i] = dmamap; 788 789 if (m == NULL) { 790 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 791 if (m_new == NULL) { 792 printf("%s: no memory for rx list -- " 793 "packet dropped!\n", sc_if->sk_dev.dv_xname); 794 return(ENOBUFS); 795 } 796 797 /* Allocate the jumbo buffer */ 798 MCLGET(m_new, M_DONTWAIT); 799 if (!(m_new->m_flags & M_EXT)) { 800 m_freem(m_new); 801 return (ENOBUFS); 802 } 803 804 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 805 806 m_adj(m_new, ETHER_ALIGN); 807 808 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new, 809 BUS_DMA_NOWAIT)) 810 return(ENOBUFS); 811 } else { 812 /* 813 * We're re-using a previously allocated mbuf; 814 * be sure to re-init pointers and lengths to 815 * default values. 816 */ 817 m_new = m; 818 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 819 m_adj(m_new, ETHER_ALIGN); 820 m_new->m_data = m_new->m_ext.ext_buf; 821 } 822 823 c = &sc_if->sk_cdata.sk_rx_chain[i]; 824 r = c->sk_desc; 825 c->sk_mbuf = m_new; 826 r->sk_data_lo = dmamap->dm_segs[0].ds_addr; 827 r->sk_ctl = dmamap->dm_segs[0].ds_len | SK_RXSTAT; 828 829 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 830 831 return(0); 832 } 833 834 /* 835 * Set media options. 836 */ 837 int 838 sk_ifmedia_upd(struct ifnet *ifp) 839 { 840 struct sk_if_softc *sc_if = ifp->if_softc; 841 842 (void) sk_init(ifp); 843 mii_mediachg(&sc_if->sk_mii); 844 return(0); 845 } 846 847 /* 848 * Report current media status. 849 */ 850 void 851 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 852 { 853 struct sk_if_softc *sc_if = ifp->if_softc; 854 855 mii_pollstat(&sc_if->sk_mii); 856 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 857 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 858 } 859 860 int 861 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 862 { 863 struct sk_if_softc *sc_if = ifp->if_softc; 864 struct sk_softc *sc = sc_if->sk_softc; 865 struct ifreq *ifr = (struct ifreq *) data; 866 /* struct ifaddr *ifa = (struct ifaddr *) data; */ 867 struct mii_data *mii; 868 int s, error = 0; 869 870 /* DPRINTFN(2, ("sk_ioctl\n")); */ 871 872 s = splnet(); 873 874 switch(command) { 875 876 case SIOCSIFFLAGS: 877 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 878 if (ifp->if_flags & IFF_UP) { 879 if (ifp->if_flags & IFF_RUNNING && 880 ifp->if_flags & IFF_PROMISC && 881 !(sc_if->sk_if_flags & IFF_PROMISC)) { 882 switch(sc->sk_type) { 883 case SK_GENESIS: 884 SK_XM_SETBIT_4(sc_if, XM_MODE, 885 XM_MODE_RX_PROMISC); 886 break; 887 case SK_YUKON: 888 case SK_YUKON_LITE: 889 case SK_YUKON_LP: 890 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 891 YU_RCR_UFLEN | YU_RCR_MUFLEN); 892 break; 893 } 894 sk_setmulti(sc_if); 895 } else if (ifp->if_flags & IFF_RUNNING && 896 !(ifp->if_flags & IFF_PROMISC) && 897 sc_if->sk_if_flags & IFF_PROMISC) { 898 switch(sc->sk_type) { 899 case SK_GENESIS: 900 SK_XM_CLRBIT_4(sc_if, XM_MODE, 901 XM_MODE_RX_PROMISC); 902 break; 903 case SK_YUKON: 904 case SK_YUKON_LITE: 905 case SK_YUKON_LP: 906 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 907 YU_RCR_UFLEN | YU_RCR_MUFLEN); 908 break; 909 } 910 911 sk_setmulti(sc_if); 912 } else 913 (void) sk_init(ifp); 914 } else { 915 if (ifp->if_flags & IFF_RUNNING) 916 sk_stop(ifp,0); 917 } 918 sc_if->sk_if_flags = ifp->if_flags; 919 error = 0; 920 break; 921 922 case SIOCGIFMEDIA: 923 case SIOCSIFMEDIA: 924 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 925 mii = &sc_if->sk_mii; 926 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 927 break; 928 default: 929 DPRINTFN(2, ("sk_ioctl ETHER\n")); 930 error = ether_ioctl(ifp, command, data); 931 932 if ( error == ENETRESET) { 933 if (ifp->if_flags & IFF_RUNNING) { 934 sk_setmulti(sc_if); 935 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 936 } 937 error = 0; 938 } else if ( error ) { 939 splx(s); 940 return error; 941 } 942 break; 943 } 944 945 splx(s); 946 return(error); 947 } 948 949 /* 950 * Lookup: Check the PCI vendor and device, and return a pointer to 951 * The structure if the IDs match against our list. 952 */ 953 954 static const struct sk_product * 955 sk_lookup(const struct pci_attach_args *pa) 956 { 957 const struct sk_product *psk; 958 959 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 960 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 961 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 962 return (psk); 963 } 964 return (NULL); 965 } 966 967 /* 968 * Probe for a SysKonnect GEnesis chip. 969 */ 970 971 int 972 skc_probe(struct device *parent, struct cfdata *match, void *aux) 973 { 974 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 975 const struct sk_product *psk; 976 977 if ((psk = sk_lookup(pa))) { 978 return(1); 979 } 980 return(0); 981 } 982 983 /* 984 * Force the GEnesis into reset, then bring it out of reset. 985 */ 986 void sk_reset(struct sk_softc *sc) 987 { 988 DPRINTFN(2, ("sk_reset\n")); 989 990 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 991 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 992 if (SK_YUKON_FAMILY(sc->sk_type)) 993 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 994 995 DELAY(1000); 996 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 997 DELAY(2); 998 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 999 if (SK_YUKON_FAMILY(sc->sk_type)) 1000 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1001 1002 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1003 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1004 CSR_READ_2(sc, SK_LINK_CTRL))); 1005 1006 if (sc->sk_type == SK_GENESIS) { 1007 /* Configure packet arbiter */ 1008 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1009 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1010 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1011 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1012 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1013 } 1014 1015 /* Enable RAM interface */ 1016 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1017 1018 /* 1019 * Configure interrupt moderation. The moderation timer 1020 * defers interrupts specified in the interrupt moderation 1021 * timer mask based on the timeout specified in the interrupt 1022 * moderation timer init register. Each bit in the timer 1023 * register represents 18.825ns, so to specify a timeout in 1024 * microseconds, we have to multiply by 54. 1025 */ 1026 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(100)); 1027 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1028 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1029 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1030 } 1031 1032 int 1033 sk_probe(struct device *parent, struct cfdata *match, void *aux) 1034 { 1035 struct skc_attach_args *sa = aux; 1036 1037 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1038 return(0); 1039 1040 return (1); 1041 } 1042 1043 /* 1044 * Each XMAC chip is attached as a separate logical IP interface. 1045 * Single port cards will have only one logical interface of course. 1046 */ 1047 void 1048 sk_attach(struct device *parent, struct device *self, void *aux) 1049 { 1050 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1051 struct sk_softc *sc = (struct sk_softc *)parent; 1052 struct skc_attach_args *sa = aux; 1053 struct sk_txmap_entry *entry; 1054 struct ifnet *ifp; 1055 bus_dma_segment_t seg; 1056 bus_dmamap_t dmamap; 1057 caddr_t kva; 1058 int i, rseg; 1059 1060 sc_if->sk_port = sa->skc_port; 1061 sc_if->sk_softc = sc; 1062 sc->sk_if[sa->skc_port] = sc_if; 1063 1064 if (sa->skc_port == SK_PORT_A) 1065 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1066 if (sa->skc_port == SK_PORT_B) 1067 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1068 1069 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1070 1071 /* 1072 * Get station address for this interface. Note that 1073 * dual port cards actually come with three station 1074 * addresses: one for each port, plus an extra. The 1075 * extra one is used by the SysKonnect driver software 1076 * as a 'virtual' station address for when both ports 1077 * are operating in failover mode. Currently we don't 1078 * use this extra address. 1079 */ 1080 for (i = 0; i < ETHER_ADDR_LEN; i++) 1081 sc_if->sk_enaddr[i] = 1082 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1083 1084 1085 aprint_normal(": Ethernet address %s\n", 1086 ether_sprintf(sc_if->sk_enaddr)); 1087 1088 /* 1089 * Set up RAM buffer addresses. The NIC will have a certain 1090 * amount of SRAM on it, somewhere between 512K and 2MB. We 1091 * need to divide this up a) between the transmitter and 1092 * receiver and b) between the two XMACs, if this is a 1093 * dual port NIC. Our algotithm is to divide up the memory 1094 * evenly so that everyone gets a fair share. 1095 */ 1096 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1097 u_int32_t chunk, val; 1098 1099 chunk = sc->sk_ramsize / 2; 1100 val = sc->sk_rboff / sizeof(u_int64_t); 1101 sc_if->sk_rx_ramstart = val; 1102 val += (chunk / sizeof(u_int64_t)); 1103 sc_if->sk_rx_ramend = val - 1; 1104 sc_if->sk_tx_ramstart = val; 1105 val += (chunk / sizeof(u_int64_t)); 1106 sc_if->sk_tx_ramend = val - 1; 1107 } else { 1108 u_int32_t chunk, val; 1109 1110 chunk = sc->sk_ramsize / 4; 1111 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1112 sizeof(u_int64_t); 1113 sc_if->sk_rx_ramstart = val; 1114 val += (chunk / sizeof(u_int64_t)); 1115 sc_if->sk_rx_ramend = val - 1; 1116 sc_if->sk_tx_ramstart = val; 1117 val += (chunk / sizeof(u_int64_t)); 1118 sc_if->sk_tx_ramend = val - 1; 1119 } 1120 1121 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1122 " tx_ramstart=%#x tx_ramend=%#x\n", 1123 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1124 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1125 1126 /* Read and save PHY type and set PHY address */ 1127 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1128 switch (sc_if->sk_phytype) { 1129 case SK_PHYTYPE_XMAC: 1130 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1131 break; 1132 case SK_PHYTYPE_BCOM: 1133 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1134 break; 1135 case SK_PHYTYPE_MARV_COPPER: 1136 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1137 break; 1138 default: 1139 aprint_error("%s: unsupported PHY type: %d\n", 1140 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1141 return; 1142 } 1143 1144 /* Allocate the descriptor queues. */ 1145 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1146 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1147 aprint_error("%s: can't alloc rx buffers\n", 1148 sc->sk_dev.dv_xname); 1149 goto fail; 1150 } 1151 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1152 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1153 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1154 sc_if->sk_dev.dv_xname, 1155 (u_long) sizeof(struct sk_ring_data)); 1156 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1157 goto fail; 1158 } 1159 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1160 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1161 &sc_if->sk_ring_map)) { 1162 aprint_error("%s: can't create dma map\n", 1163 sc_if->sk_dev.dv_xname); 1164 bus_dmamem_unmap(sc->sc_dmatag, kva, 1165 sizeof(struct sk_ring_data)); 1166 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1167 goto fail; 1168 } 1169 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1170 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1171 aprint_error("%s: can't load dma map\n", 1172 sc_if->sk_dev.dv_xname); 1173 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1174 bus_dmamem_unmap(sc->sc_dmatag, kva, 1175 sizeof(struct sk_ring_data)); 1176 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1177 goto fail; 1178 } 1179 1180 for (i = 0; i < SK_RX_RING_CNT; i++) 1181 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1182 1183 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1184 for (i = 0; i < SK_TX_RING_CNT; i++) { 1185 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1186 1187 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, SK_NTXSEG, 1188 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap)) { 1189 aprint_error("%s: Can't create TX dmamap\n", 1190 sc_if->sk_dev.dv_xname); 1191 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1192 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1193 bus_dmamem_unmap(sc->sc_dmatag, kva, 1194 sizeof(struct sk_ring_data)); 1195 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1196 goto fail; 1197 } 1198 1199 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1200 if (!entry) { 1201 aprint_error("%s: Can't alloc txmap entry\n", 1202 sc_if->sk_dev.dv_xname); 1203 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1204 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1205 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1206 bus_dmamem_unmap(sc->sc_dmatag, kva, 1207 sizeof(struct sk_ring_data)); 1208 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1209 goto fail; 1210 } 1211 entry->dmamap = dmamap; 1212 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1213 } 1214 1215 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1216 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1217 1218 /* XXX TLS It's not clear what's wrong with the Jumbo MTU 1219 XXX TLS support in this driver, so we don't enable it. */ 1220 1221 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1222 1223 ifp = &sc_if->sk_ethercom.ec_if; 1224 ifp->if_softc = sc_if; 1225 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1226 ifp->if_ioctl = sk_ioctl; 1227 ifp->if_start = sk_start; 1228 ifp->if_stop = sk_stop; 1229 ifp->if_init = sk_init; 1230 ifp->if_watchdog = sk_watchdog; 1231 ifp->if_capabilities = 0; 1232 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1233 IFQ_SET_READY(&ifp->if_snd); 1234 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1235 1236 /* 1237 * Do miibus setup. 1238 */ 1239 switch (sc->sk_type) { 1240 case SK_GENESIS: 1241 sk_init_xmac(sc_if); 1242 break; 1243 case SK_YUKON: 1244 case SK_YUKON_LITE: 1245 case SK_YUKON_LP: 1246 sk_init_yukon(sc_if); 1247 break; 1248 default: 1249 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1250 sc->sk_type); 1251 } 1252 1253 DPRINTFN(2, ("sk_attach: 1\n")); 1254 1255 sc_if->sk_mii.mii_ifp = ifp; 1256 switch (sc->sk_type) { 1257 case SK_GENESIS: 1258 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1259 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1260 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1261 break; 1262 case SK_YUKON: 1263 case SK_YUKON_LITE: 1264 case SK_YUKON_LP: 1265 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1266 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1267 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1268 break; 1269 } 1270 1271 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1272 sk_ifmedia_upd, sk_ifmedia_sts); 1273 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1274 MII_OFFSET_ANY, 0); 1275 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1276 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1277 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1278 0, NULL); 1279 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1280 } 1281 else 1282 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1283 1284 callout_init(&sc_if->sk_tick_ch); 1285 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1286 1287 DPRINTFN(2, ("sk_attach: 1\n")); 1288 1289 /* 1290 * Call MI attach routines. 1291 */ 1292 if_attach(ifp); 1293 1294 ether_ifattach(ifp, sc_if->sk_enaddr); 1295 1296 #if NRND > 0 1297 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1298 RND_TYPE_NET, 0); 1299 #endif 1300 1301 DPRINTFN(2, ("sk_attach: end\n")); 1302 1303 return; 1304 1305 fail: 1306 sc->sk_if[sa->skc_port] = NULL; 1307 } 1308 1309 int 1310 skcprint(void *aux, const char *pnp) 1311 { 1312 struct skc_attach_args *sa = aux; 1313 1314 if (pnp) 1315 aprint_normal("sk port %c at %s", 1316 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1317 else 1318 aprint_normal(" port %c", 1319 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1320 return (UNCONF); 1321 } 1322 1323 /* 1324 * Attach the interface. Allocate softc structures, do ifmedia 1325 * setup and ethernet/BPF attach. 1326 */ 1327 void 1328 skc_attach(struct device *parent, struct device *self, void *aux) 1329 { 1330 struct sk_softc *sc = (struct sk_softc *)self; 1331 struct pci_attach_args *pa = aux; 1332 struct skc_attach_args skca; 1333 pci_chipset_tag_t pc = pa->pa_pc; 1334 pcireg_t memtype; 1335 pci_intr_handle_t ih; 1336 const char *intrstr = NULL; 1337 bus_addr_t iobase; 1338 bus_size_t iosize; 1339 int s; 1340 u_int32_t command; 1341 char *revstr; 1342 1343 DPRINTFN(2, ("begin skc_attach\n")); 1344 1345 s = splnet(); 1346 1347 /* 1348 * Handle power management nonsense. 1349 */ 1350 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1351 1352 if (command == 0x01) { 1353 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1354 if (command & SK_PSTATE_MASK) { 1355 u_int32_t iobase, membase, irq; 1356 1357 /* Save important PCI config data. */ 1358 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1359 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1360 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1361 1362 /* Reset the power state. */ 1363 aprint_normal("%s chip is in D%d power mode " 1364 "-- setting to D0\n", sc->sk_dev.dv_xname, 1365 command & SK_PSTATE_MASK); 1366 command &= 0xFFFFFFFC; 1367 pci_conf_write(pc, pa->pa_tag, 1368 SK_PCI_PWRMGMTCTRL, command); 1369 1370 /* Restore PCI config data. */ 1371 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1372 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1373 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1374 } 1375 } 1376 1377 /* 1378 * Map control/status registers. 1379 */ 1380 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1381 command |= PCI_COMMAND_IO_ENABLE | 1382 PCI_COMMAND_MEM_ENABLE | 1383 PCI_COMMAND_MASTER_ENABLE; 1384 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1385 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1386 1387 #ifdef SK_USEIOSPACE 1388 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1389 aprint_error(": failed to enable I/O ports!\n"); 1390 goto fail; 1391 } 1392 /* 1393 * Map control/status registers. 1394 */ 1395 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1396 &iobase, &iosize)) { 1397 aprint_error(": can't find i/o space\n"); 1398 goto fail; 1399 } 1400 #else 1401 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1402 aprint_error(": failed to enable memory mapping!\n"); 1403 goto fail; 1404 } 1405 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1406 switch (memtype) { 1407 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1408 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1409 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1410 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1411 &iobase, &iosize) == 0) 1412 break; 1413 default: 1414 aprint_error("%s: can't find mem space\n", 1415 sc->sk_dev.dv_xname); 1416 return; 1417 } 1418 1419 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1420 #endif 1421 sc->sc_dmatag = pa->pa_dmat; 1422 1423 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1424 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1425 1426 /* bail out here if chip is not recognized */ 1427 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1428 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1429 goto fail; 1430 } 1431 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1432 1433 /* Allocate interrupt */ 1434 if (pci_intr_map(pa, &ih)) { 1435 aprint_error(": couldn't map interrupt\n"); 1436 goto fail; 1437 } 1438 1439 intrstr = pci_intr_string(pc, ih); 1440 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1441 if (sc->sk_intrhand == NULL) { 1442 aprint_error(": couldn't establish interrupt"); 1443 if (intrstr != NULL) 1444 aprint_normal(" at %s", intrstr); 1445 goto fail; 1446 } 1447 aprint_normal(": %s\n", intrstr); 1448 1449 /* Reset the adapter. */ 1450 sk_reset(sc); 1451 1452 /* Read and save vital product data from EEPROM. */ 1453 sk_vpd_read(sc); 1454 1455 if (sc->sk_type == SK_GENESIS) { 1456 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1457 /* Read and save RAM size and RAMbuffer offset */ 1458 switch(val) { 1459 case SK_RAMSIZE_512K_64: 1460 sc->sk_ramsize = 0x80000; 1461 sc->sk_rboff = SK_RBOFF_0; 1462 break; 1463 case SK_RAMSIZE_1024K_64: 1464 sc->sk_ramsize = 0x100000; 1465 sc->sk_rboff = SK_RBOFF_80000; 1466 break; 1467 case SK_RAMSIZE_1024K_128: 1468 sc->sk_ramsize = 0x100000; 1469 sc->sk_rboff = SK_RBOFF_0; 1470 break; 1471 case SK_RAMSIZE_2048K_128: 1472 sc->sk_ramsize = 0x200000; 1473 sc->sk_rboff = SK_RBOFF_0; 1474 break; 1475 default: 1476 aprint_error("%s: unknown ram size: %d\n", 1477 sc->sk_dev.dv_xname, val); 1478 goto fail; 1479 break; 1480 } 1481 1482 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1483 sc->sk_ramsize, sc->sk_ramsize / 1024, 1484 sc->sk_rboff)); 1485 } else { 1486 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1487 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1488 sc->sk_rboff = SK_RBOFF_0; 1489 1490 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1491 sc->sk_ramsize / 1024, sc->sk_ramsize, 1492 sc->sk_rboff)); 1493 } 1494 1495 /* Read and save physical media type */ 1496 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1497 case SK_PMD_1000BASESX: 1498 sc->sk_pmd = IFM_1000_SX; 1499 break; 1500 case SK_PMD_1000BASELX: 1501 sc->sk_pmd = IFM_1000_LX; 1502 break; 1503 case SK_PMD_1000BASECX: 1504 sc->sk_pmd = IFM_1000_CX; 1505 break; 1506 case SK_PMD_1000BASETX: 1507 sc->sk_pmd = IFM_1000_T; 1508 break; 1509 default: 1510 aprint_error("%s: unknown media type: 0x%x\n", 1511 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1512 goto fail; 1513 } 1514 1515 /* determine whether to name it with vpd or just make it up */ 1516 /* Marvell Yukon VPD's can freqently be bogus */ 1517 1518 switch (pa->pa_id) { 1519 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1520 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1521 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1522 case PCI_PRODUCT_3COM_3C940: 1523 case PCI_PRODUCT_DLINK_DGE530T: 1524 case PCI_PRODUCT_LINKSYS_EG1032: 1525 case PCI_PRODUCT_LINKSYS_EG1064: 1526 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1527 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1528 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1529 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1530 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1531 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1532 sc->sk_name = sc->sk_vpd_prodname; 1533 break; 1534 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_SKNET): 1535 /* whoops yukon vpd prodname bears no resemblance to reality */ 1536 switch (sc->sk_type) { 1537 case SK_GENESIS: 1538 sc->sk_name = sc->sk_vpd_prodname; 1539 break; 1540 case SK_YUKON: 1541 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1542 break; 1543 case SK_YUKON_LITE: 1544 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1545 break; 1546 case SK_YUKON_LP: 1547 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1548 break; 1549 default: 1550 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1551 } 1552 1553 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1554 1555 if ( sc->sk_type == SK_YUKON ) { 1556 uint32_t flashaddr; 1557 uint8_t testbyte; 1558 1559 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1560 1561 /* test Flash-Address Register */ 1562 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1563 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1564 1565 if (testbyte != 0) { 1566 /* this is yukon lite Rev. A0 */ 1567 sc->sk_type = SK_YUKON_LITE; 1568 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1569 /* restore Flash-Address Register */ 1570 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1571 } 1572 } 1573 break; 1574 default: 1575 sc->sk_name = "Unkown Marvell"; 1576 } 1577 1578 1579 if ( sc->sk_type == SK_YUKON_LITE ) { 1580 switch (sc->sk_rev) { 1581 case SK_YUKON_LITE_REV_A0: 1582 revstr = "A0"; 1583 break; 1584 case SK_YUKON_LITE_REV_A1: 1585 revstr = "A1"; 1586 break; 1587 case SK_YUKON_LITE_REV_A3: 1588 revstr = "A3"; 1589 break; 1590 default: 1591 revstr = ""; 1592 } 1593 } else { 1594 revstr = ""; 1595 } 1596 1597 /* Announce the product name. */ 1598 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1599 sc->sk_name, revstr, sc->sk_rev); 1600 1601 skca.skc_port = SK_PORT_A; 1602 (void)config_found(&sc->sk_dev, &skca, skcprint); 1603 1604 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1605 skca.skc_port = SK_PORT_B; 1606 (void)config_found(&sc->sk_dev, &skca, skcprint); 1607 } 1608 1609 /* Turn on the 'driver is loaded' LED. */ 1610 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1611 1612 fail: 1613 splx(s); 1614 } 1615 1616 int 1617 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1618 { 1619 struct sk_softc *sc = sc_if->sk_softc; 1620 struct sk_tx_desc *f = NULL; 1621 u_int32_t frag, cur, cnt = 0; 1622 int i; 1623 struct sk_txmap_entry *entry; 1624 bus_dmamap_t txmap; 1625 1626 DPRINTFN(3, ("sk_encap\n")); 1627 1628 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1629 if (entry == NULL) { 1630 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1631 return ENOBUFS; 1632 } 1633 txmap = entry->dmamap; 1634 1635 cur = frag = *txidx; 1636 1637 #ifdef SK_DEBUG 1638 if (skdebug >= 3) 1639 sk_dump_mbuf(m_head); 1640 #endif 1641 1642 /* 1643 * Start packing the mbufs in this chain into 1644 * the fragment pointers. Stop when we run out 1645 * of fragments or hit the end of the mbuf chain. 1646 */ 1647 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1648 BUS_DMA_NOWAIT)) { 1649 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1650 return(ENOBUFS); 1651 } 1652 1653 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1654 1655 /* Sync the DMA map. */ 1656 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1657 BUS_DMASYNC_PREWRITE); 1658 1659 for (i = 0; i < txmap->dm_nsegs; i++) { 1660 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1661 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1662 return(ENOBUFS); 1663 } 1664 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1665 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1666 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1667 if (cnt == 0) 1668 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1669 else 1670 f->sk_ctl |= SK_TXCTL_OWN; 1671 1672 cur = frag; 1673 SK_INC(frag, SK_TX_RING_CNT); 1674 cnt++; 1675 } 1676 1677 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1678 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1679 1680 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1681 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1682 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1683 1684 /* Sync descriptors before handing to chip */ 1685 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1686 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1687 1688 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1689 1690 /* Sync first descriptor to hand it off */ 1691 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1692 1693 sc_if->sk_cdata.sk_tx_cnt += cnt; 1694 1695 #ifdef SK_DEBUG 1696 if (skdebug >= 3) { 1697 struct sk_tx_desc *desc; 1698 u_int32_t idx; 1699 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1700 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1701 sk_dump_txdesc(desc, idx); 1702 } 1703 } 1704 #endif 1705 1706 *txidx = frag; 1707 1708 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1709 1710 return(0); 1711 } 1712 1713 void 1714 sk_start(struct ifnet *ifp) 1715 { 1716 struct sk_if_softc *sc_if = ifp->if_softc; 1717 struct sk_softc *sc = sc_if->sk_softc; 1718 struct mbuf *m_head = NULL; 1719 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1720 int pkts = 0; 1721 1722 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1723 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1724 1725 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1726 1727 IFQ_POLL(&ifp->if_snd, m_head); 1728 if (m_head == NULL) 1729 break; 1730 1731 /* 1732 * Pack the data into the transmit ring. If we 1733 * don't have room, set the OACTIVE flag and wait 1734 * for the NIC to drain the ring. 1735 */ 1736 if (sk_encap(sc_if, m_head, &idx)) { 1737 ifp->if_flags |= IFF_OACTIVE; 1738 break; 1739 } 1740 1741 /* now we are committed to transmit the packet */ 1742 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1743 pkts++; 1744 1745 /* 1746 * If there's a BPF listener, bounce a copy of this frame 1747 * to him. 1748 */ 1749 #if NBPFILTER > 0 1750 if (ifp->if_bpf) 1751 bpf_mtap(ifp->if_bpf, m_head); 1752 #endif 1753 } 1754 if (pkts == 0) 1755 return; 1756 1757 /* Transmit */ 1758 sc_if->sk_cdata.sk_tx_prod = idx; 1759 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1760 1761 /* Set a timeout in case the chip goes out to lunch. */ 1762 ifp->if_timer = 5; 1763 } 1764 1765 1766 void 1767 sk_watchdog(struct ifnet *ifp) 1768 { 1769 struct sk_if_softc *sc_if = ifp->if_softc; 1770 1771 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1772 (void) sk_init(ifp); 1773 } 1774 1775 void 1776 sk_shutdown(void * v) 1777 { 1778 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1779 struct sk_softc *sc = sc_if->sk_softc; 1780 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1781 1782 DPRINTFN(2, ("sk_shutdown\n")); 1783 sk_stop(ifp,1); 1784 1785 /* Turn off the 'driver is loaded' LED. */ 1786 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1787 1788 /* 1789 * Reset the GEnesis controller. Doing this should also 1790 * assert the resets on the attached XMAC(s). 1791 */ 1792 sk_reset(sc); 1793 } 1794 1795 void 1796 sk_rxeof(struct sk_if_softc *sc_if) 1797 { 1798 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1799 struct mbuf *m; 1800 struct sk_chain *cur_rx; 1801 struct sk_rx_desc *cur_desc; 1802 int i, cur, total_len = 0; 1803 u_int32_t rxstat; 1804 bus_dmamap_t dmamap; 1805 1806 i = sc_if->sk_cdata.sk_rx_prod; 1807 1808 DPRINTFN(3, ("sk_rxeof %d\n", i)); 1809 1810 for (;;) { 1811 cur = i; 1812 1813 /* Sync the descriptor */ 1814 SK_CDRXSYNC(sc_if, cur, 1815 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1816 1817 if (sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl & SK_RXCTL_OWN) { 1818 /* Invalidate the descriptor -- it's not ready yet */ 1819 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 1820 sc_if->sk_cdata.sk_rx_prod = i; 1821 break; 1822 } 1823 1824 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1825 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1826 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1827 1828 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1829 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1830 1831 rxstat = cur_desc->sk_xmac_rxstat; 1832 m = cur_rx->sk_mbuf; 1833 cur_rx->sk_mbuf = NULL; 1834 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1835 1836 sc_if->sk_cdata.sk_rx_map[cur] = 0; 1837 1838 SK_INC(i, SK_RX_RING_CNT); 1839 1840 if (rxstat & XM_RXSTAT_ERRFRAME) { 1841 ifp->if_ierrors++; 1842 sk_newbuf(sc_if, cur, m, dmamap); 1843 continue; 1844 } 1845 1846 /* 1847 * Try to allocate a new jumbo buffer. If that 1848 * fails, copy the packet to mbufs and put the 1849 * jumbo buffer back in the ring so it can be 1850 * re-used. If allocating mbufs fails, then we 1851 * have to drop the packet. 1852 */ 1853 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1854 struct mbuf *m0; 1855 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1856 total_len + ETHER_ALIGN, 0, ifp, NULL); 1857 sk_newbuf(sc_if, cur, m, dmamap); 1858 if (m0 == NULL) { 1859 printf("%s: no receive buffers " 1860 "available -- packet dropped!\n", 1861 sc_if->sk_dev.dv_xname); 1862 ifp->if_ierrors++; 1863 continue; 1864 } 1865 m_adj(m0, ETHER_ALIGN); 1866 m = m0; 1867 } else { 1868 m->m_pkthdr.rcvif = ifp; 1869 m->m_pkthdr.len = m->m_len = total_len; 1870 } 1871 1872 ifp->if_ipackets++; 1873 1874 #if NBPFILTER > 0 1875 if (ifp->if_bpf) 1876 bpf_mtap(ifp->if_bpf, m); 1877 #endif 1878 /* pass it on. */ 1879 (*ifp->if_input)(ifp, m); 1880 } 1881 } 1882 1883 void 1884 sk_txeof(struct sk_if_softc *sc_if) 1885 { 1886 struct sk_softc *sc = sc_if->sk_softc; 1887 struct sk_tx_desc *cur_tx = NULL; 1888 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1889 u_int32_t idx; 1890 struct sk_txmap_entry *entry; 1891 1892 DPRINTFN(3, ("sk_txeof\n")); 1893 1894 /* 1895 * Go through our tx ring and free mbufs for those 1896 * frames that have been sent. 1897 */ 1898 idx = sc_if->sk_cdata.sk_tx_cons; 1899 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1900 SK_CDTXSYNC(sc_if, idx, 1, 1901 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1902 1903 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1904 #ifdef SK_DEBUG 1905 if (skdebug >= 3) 1906 sk_dump_txdesc(cur_tx, idx); 1907 #endif 1908 if (cur_tx->sk_ctl & SK_TXCTL_OWN) { 1909 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 1910 break; 1911 } 1912 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1913 ifp->if_opackets++; 1914 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1915 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1916 1917 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1918 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1919 1920 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1921 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1922 1923 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1924 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1925 link); 1926 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1927 } 1928 sc_if->sk_cdata.sk_tx_cnt--; 1929 SK_INC(idx, SK_TX_RING_CNT); 1930 } 1931 if (sc_if->sk_cdata.sk_tx_cnt == 0) 1932 ifp->if_timer = 0; 1933 else /* nudge chip to keep tx ring moving */ 1934 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1935 1936 sc_if->sk_cdata.sk_tx_cons = idx; 1937 1938 if (cur_tx != NULL) 1939 ifp->if_flags &= ~IFF_OACTIVE; 1940 } 1941 1942 void 1943 sk_tick(void *xsc_if) 1944 { 1945 struct sk_if_softc *sc_if = xsc_if; 1946 struct mii_data *mii = &sc_if->sk_mii; 1947 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1948 int i; 1949 1950 DPRINTFN(3, ("sk_tick\n")); 1951 1952 if (!(ifp->if_flags & IFF_UP)) 1953 return; 1954 1955 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1956 sk_intr_bcom(sc_if); 1957 return; 1958 } 1959 1960 /* 1961 * According to SysKonnect, the correct way to verify that 1962 * the link has come back up is to poll bit 0 of the GPIO 1963 * register three times. This pin has the signal from the 1964 * link sync pin connected to it; if we read the same link 1965 * state 3 times in a row, we know the link is up. 1966 */ 1967 for (i = 0; i < 3; i++) { 1968 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1969 break; 1970 } 1971 1972 if (i != 3) { 1973 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1974 return; 1975 } 1976 1977 /* Turn the GP0 interrupt back on. */ 1978 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1979 SK_XM_READ_2(sc_if, XM_ISR); 1980 mii_tick(mii); 1981 mii_pollstat(mii); 1982 callout_stop(&sc_if->sk_tick_ch); 1983 } 1984 1985 void 1986 sk_intr_bcom(struct sk_if_softc *sc_if) 1987 { 1988 struct mii_data *mii = &sc_if->sk_mii; 1989 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1990 int status; 1991 1992 1993 DPRINTFN(3, ("sk_intr_bcom\n")); 1994 1995 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1996 1997 /* 1998 * Read the PHY interrupt register to make sure 1999 * we clear any pending interrupts. 2000 */ 2001 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2002 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2003 2004 if (!(ifp->if_flags & IFF_RUNNING)) { 2005 sk_init_xmac(sc_if); 2006 return; 2007 } 2008 2009 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2010 int lstat; 2011 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2012 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2013 2014 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2015 mii_mediachg(mii); 2016 /* Turn off the link LED. */ 2017 SK_IF_WRITE_1(sc_if, 0, 2018 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2019 sc_if->sk_link = 0; 2020 } else if (status & BRGPHY_ISR_LNK_CHG) { 2021 sk_xmac_miibus_writereg((struct device *)sc_if, 2022 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2023 mii_tick(mii); 2024 sc_if->sk_link = 1; 2025 /* Turn on the link LED. */ 2026 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2027 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2028 SK_LINKLED_BLINK_OFF); 2029 mii_pollstat(mii); 2030 } else { 2031 mii_tick(mii); 2032 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2033 } 2034 } 2035 2036 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2037 } 2038 2039 void 2040 sk_intr_xmac(struct sk_if_softc *sc_if) 2041 { 2042 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2043 2044 DPRINTFN(3, ("sk_intr_xmac\n")); 2045 2046 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2047 if (status & XM_ISR_GP0_SET) { 2048 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2049 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2050 } 2051 2052 if (status & XM_ISR_AUTONEG_DONE) { 2053 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2054 } 2055 } 2056 2057 if (status & XM_IMR_TX_UNDERRUN) 2058 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2059 2060 if (status & XM_IMR_RX_OVERRUN) 2061 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2062 } 2063 2064 void 2065 sk_intr_yukon(sc_if) 2066 struct sk_if_softc *sc_if; 2067 { 2068 int status; 2069 2070 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2071 2072 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2073 } 2074 2075 int 2076 sk_intr(void *xsc) 2077 { 2078 struct sk_softc *sc = xsc; 2079 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2080 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2081 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2082 u_int32_t status; 2083 int claimed = 0; 2084 2085 if (sc_if0 != NULL) 2086 ifp0 = &sc_if0->sk_ethercom.ec_if; 2087 if (sc_if1 != NULL) 2088 ifp1 = &sc_if1->sk_ethercom.ec_if; 2089 2090 for (;;) { 2091 status = CSR_READ_4(sc, SK_ISSR); 2092 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2093 2094 if (!(status & sc->sk_intrmask)) 2095 break; 2096 2097 claimed = 1; 2098 2099 /* Handle receive interrupts first. */ 2100 if (status & SK_ISR_RX1_EOF) { 2101 sk_rxeof(sc_if0); 2102 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2103 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2104 } 2105 if (status & SK_ISR_RX2_EOF) { 2106 sk_rxeof(sc_if1); 2107 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2108 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2109 } 2110 2111 /* Then transmit interrupts. */ 2112 if (status & SK_ISR_TX1_S_EOF) { 2113 sk_txeof(sc_if0); 2114 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2115 SK_TXBMU_CLR_IRQ_EOF); 2116 } 2117 if (status & SK_ISR_TX2_S_EOF) { 2118 sk_txeof(sc_if1); 2119 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2120 SK_TXBMU_CLR_IRQ_EOF); 2121 } 2122 2123 /* Then MAC interrupts. */ 2124 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 2125 if (sc->sk_type == SK_GENESIS) 2126 sk_intr_xmac(sc_if0); 2127 else 2128 sk_intr_yukon(sc_if0); 2129 } 2130 2131 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 2132 if (sc->sk_type == SK_GENESIS) 2133 sk_intr_xmac(sc_if1); 2134 else 2135 sk_intr_yukon(sc_if1); 2136 2137 } 2138 2139 if (status & SK_ISR_EXTERNAL_REG) { 2140 if (ifp0 != NULL && 2141 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2142 sk_intr_bcom(sc_if0); 2143 2144 if (ifp1 != NULL && 2145 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2146 sk_intr_bcom(sc_if1); 2147 } 2148 } 2149 2150 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2151 2152 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2153 sk_start(ifp0); 2154 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2155 sk_start(ifp1); 2156 2157 return (claimed); 2158 } 2159 2160 void 2161 sk_init_xmac(struct sk_if_softc *sc_if) 2162 { 2163 struct sk_softc *sc = sc_if->sk_softc; 2164 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2165 static const struct sk_bcom_hack bhack[] = { 2166 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2167 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2168 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2169 { 0, 0 } }; 2170 2171 DPRINTFN(1, ("sk_init_xmac\n")); 2172 2173 /* Unreset the XMAC. */ 2174 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2175 DELAY(1000); 2176 2177 /* Reset the XMAC's internal state. */ 2178 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2179 2180 /* Save the XMAC II revision */ 2181 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2182 2183 /* 2184 * Perform additional initialization for external PHYs, 2185 * namely for the 1000baseTX cards that use the XMAC's 2186 * GMII mode. 2187 */ 2188 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2189 int i = 0; 2190 u_int32_t val; 2191 2192 /* Take PHY out of reset. */ 2193 val = sk_win_read_4(sc, SK_GPIO); 2194 if (sc_if->sk_port == SK_PORT_A) 2195 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2196 else 2197 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2198 sk_win_write_4(sc, SK_GPIO, val); 2199 2200 /* Enable GMII mode on the XMAC. */ 2201 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2202 2203 sk_xmac_miibus_writereg((struct device *)sc_if, 2204 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2205 DELAY(10000); 2206 sk_xmac_miibus_writereg((struct device *)sc_if, 2207 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2208 2209 /* 2210 * Early versions of the BCM5400 apparently have 2211 * a bug that requires them to have their reserved 2212 * registers initialized to some magic values. I don't 2213 * know what the numbers do, I'm just the messenger. 2214 */ 2215 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2216 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2217 while(bhack[i].reg) { 2218 sk_xmac_miibus_writereg((struct device *)sc_if, 2219 SK_PHYADDR_BCOM, bhack[i].reg, 2220 bhack[i].val); 2221 i++; 2222 } 2223 } 2224 } 2225 2226 /* Set station address */ 2227 SK_XM_WRITE_2(sc_if, XM_PAR0, 2228 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2229 SK_XM_WRITE_2(sc_if, XM_PAR1, 2230 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2231 SK_XM_WRITE_2(sc_if, XM_PAR2, 2232 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2233 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2234 2235 if (ifp->if_flags & IFF_PROMISC) { 2236 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2237 } else { 2238 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2239 } 2240 2241 if (ifp->if_flags & IFF_BROADCAST) { 2242 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2243 } else { 2244 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2245 } 2246 2247 /* We don't need the FCS appended to the packet. */ 2248 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2249 2250 /* We want short frames padded to 60 bytes. */ 2251 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2252 2253 /* 2254 * Enable the reception of all error frames. This is is 2255 * a necessary evil due to the design of the XMAC. The 2256 * XMAC's receive FIFO is only 8K in size, however jumbo 2257 * frames can be up to 9000 bytes in length. When bad 2258 * frame filtering is enabled, the XMAC's RX FIFO operates 2259 * in 'store and forward' mode. For this to work, the 2260 * entire frame has to fit into the FIFO, but that means 2261 * that jumbo frames larger than 8192 bytes will be 2262 * truncated. Disabling all bad frame filtering causes 2263 * the RX FIFO to operate in streaming mode, in which 2264 * case the XMAC will start transfering frames out of the 2265 * RX FIFO as soon as the FIFO threshold is reached. 2266 */ 2267 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2268 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2269 XM_MODE_RX_INRANGELEN); 2270 2271 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2272 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2273 else 2274 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2275 2276 /* 2277 * Bump up the transmit threshold. This helps hold off transmit 2278 * underruns when we're blasting traffic from both ports at once. 2279 */ 2280 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2281 2282 /* Set multicast filter */ 2283 sk_setmulti(sc_if); 2284 2285 /* Clear and enable interrupts */ 2286 SK_XM_READ_2(sc_if, XM_ISR); 2287 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2288 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2289 else 2290 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2291 2292 /* Configure MAC arbiter */ 2293 switch(sc_if->sk_xmac_rev) { 2294 case XM_XMAC_REV_B2: 2295 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2296 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2297 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2298 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2299 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2300 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2301 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2302 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2303 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2304 break; 2305 case XM_XMAC_REV_C1: 2306 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2307 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2308 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2309 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2310 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2311 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2312 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2313 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2314 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2315 break; 2316 default: 2317 break; 2318 } 2319 sk_win_write_2(sc, SK_MACARB_CTL, 2320 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2321 2322 sc_if->sk_link = 1; 2323 } 2324 2325 void sk_init_yukon(sc_if) 2326 struct sk_if_softc *sc_if; 2327 { 2328 u_int32_t /*mac, */phy; 2329 u_int16_t reg; 2330 int i; 2331 2332 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2333 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2334 2335 /* GMAC and GPHY Reset */ 2336 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2337 2338 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2339 2340 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2341 DELAY(1000); 2342 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2343 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2344 DELAY(1000); 2345 2346 2347 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2348 2349 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2350 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2351 2352 switch(sc_if->sk_softc->sk_pmd) { 2353 case IFM_1000_SX: 2354 case IFM_1000_LX: 2355 phy |= SK_GPHY_FIBER; 2356 break; 2357 2358 case IFM_1000_CX: 2359 case IFM_1000_T: 2360 phy |= SK_GPHY_COPPER; 2361 break; 2362 } 2363 2364 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2365 2366 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2367 DELAY(1000); 2368 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2369 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2370 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2371 2372 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2373 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2374 2375 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2376 2377 /* unused read of the interrupt source register */ 2378 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2379 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2380 2381 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2382 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2383 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2384 2385 /* MIB Counter Clear Mode set */ 2386 reg |= YU_PAR_MIB_CLR; 2387 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2388 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2389 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2390 2391 /* MIB Counter Clear Mode clear */ 2392 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2393 reg &= ~YU_PAR_MIB_CLR; 2394 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2395 2396 /* receive control reg */ 2397 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2398 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2399 YU_RCR_CRCR); 2400 2401 /* transmit parameter register */ 2402 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2403 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2404 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2405 2406 /* serial mode register */ 2407 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2408 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2409 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2410 2411 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2412 /* Setup Yukon's address */ 2413 for (i = 0; i < 3; i++) { 2414 /* Write Source Address 1 (unicast filter) */ 2415 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2416 sc_if->sk_enaddr[i * 2] | 2417 sc_if->sk_enaddr[i * 2 + 1] << 8); 2418 } 2419 2420 for (i = 0; i < 3; i++) { 2421 reg = sk_win_read_2(sc_if->sk_softc, 2422 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2423 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2424 } 2425 2426 /* Set multicast filter */ 2427 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2428 sk_setmulti(sc_if); 2429 2430 /* enable interrupt mask for counter overflows */ 2431 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2432 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2433 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2434 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2435 2436 /* Configure RX MAC FIFO */ 2437 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2438 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2439 2440 /* Configure TX MAC FIFO */ 2441 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2442 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2443 2444 DPRINTFN(6, ("sk_init_yukon: end\n")); 2445 } 2446 2447 /* 2448 * Note that to properly initialize any part of the GEnesis chip, 2449 * you first have to take it out of reset mode. 2450 */ 2451 int 2452 sk_init(struct ifnet *ifp) 2453 { 2454 struct sk_if_softc *sc_if = ifp->if_softc; 2455 struct sk_softc *sc = sc_if->sk_softc; 2456 struct mii_data *mii = &sc_if->sk_mii; 2457 int s; 2458 2459 DPRINTFN(1, ("sk_init\n")); 2460 2461 s = splnet(); 2462 2463 /* Cancel pending I/O and free all RX/TX buffers. */ 2464 sk_stop(ifp,0); 2465 2466 if (sc->sk_type == SK_GENESIS) { 2467 /* Configure LINK_SYNC LED */ 2468 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2469 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2470 SK_LINKLED_LINKSYNC_ON); 2471 2472 /* Configure RX LED */ 2473 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2474 SK_RXLEDCTL_COUNTER_START); 2475 2476 /* Configure TX LED */ 2477 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2478 SK_TXLEDCTL_COUNTER_START); 2479 } 2480 2481 /* Configure I2C registers */ 2482 2483 /* Configure XMAC(s) */ 2484 switch (sc->sk_type) { 2485 case SK_GENESIS: 2486 sk_init_xmac(sc_if); 2487 break; 2488 case SK_YUKON: 2489 case SK_YUKON_LITE: 2490 case SK_YUKON_LP: 2491 sk_init_yukon(sc_if); 2492 break; 2493 } 2494 mii_mediachg(mii); 2495 2496 if (sc->sk_type == SK_GENESIS) { 2497 /* Configure MAC FIFOs */ 2498 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2499 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2500 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2501 2502 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2503 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2504 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2505 } 2506 2507 /* Configure transmit arbiter(s) */ 2508 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2509 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2510 2511 /* Configure RAMbuffers */ 2512 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2513 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2514 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2515 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2516 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2517 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2518 2519 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2520 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2521 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2522 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2523 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2524 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2525 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2526 2527 /* Configure BMUs */ 2528 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2529 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2530 SK_RX_RING_ADDR(sc_if, 0)); 2531 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2532 2533 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2534 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2535 SK_TX_RING_ADDR(sc_if, 0)); 2536 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2537 2538 /* Init descriptors */ 2539 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2540 printf("%s: initialization failed: no " 2541 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2542 sk_stop(ifp,0); 2543 splx(s); 2544 return(ENOBUFS); 2545 } 2546 2547 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2548 printf("%s: initialization failed: no " 2549 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2550 sk_stop(ifp,0); 2551 splx(s); 2552 return(ENOBUFS); 2553 } 2554 2555 /* Configure interrupt handling */ 2556 CSR_READ_4(sc, SK_ISSR); 2557 if (sc_if->sk_port == SK_PORT_A) 2558 sc->sk_intrmask |= SK_INTRS1; 2559 else 2560 sc->sk_intrmask |= SK_INTRS2; 2561 2562 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2563 2564 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2565 2566 /* Start BMUs. */ 2567 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2568 2569 if (sc->sk_type == SK_GENESIS) { 2570 /* Enable XMACs TX and RX state machines */ 2571 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2572 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2573 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2574 } 2575 2576 if (SK_YUKON_FAMILY(sc->sk_type)) { 2577 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2578 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2579 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2580 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2581 } 2582 2583 2584 ifp->if_flags |= IFF_RUNNING; 2585 ifp->if_flags &= ~IFF_OACTIVE; 2586 2587 splx(s); 2588 return(0); 2589 } 2590 2591 void 2592 sk_stop(struct ifnet *ifp, int disable) 2593 { 2594 struct sk_if_softc *sc_if = ifp->if_softc; 2595 struct sk_softc *sc = sc_if->sk_softc; 2596 int i; 2597 2598 DPRINTFN(1, ("sk_stop\n")); 2599 2600 callout_stop(&sc_if->sk_tick_ch); 2601 2602 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2603 u_int32_t val; 2604 2605 /* Put PHY back into reset. */ 2606 val = sk_win_read_4(sc, SK_GPIO); 2607 if (sc_if->sk_port == SK_PORT_A) { 2608 val |= SK_GPIO_DIR0; 2609 val &= ~SK_GPIO_DAT0; 2610 } else { 2611 val |= SK_GPIO_DIR2; 2612 val &= ~SK_GPIO_DAT2; 2613 } 2614 sk_win_write_4(sc, SK_GPIO, val); 2615 } 2616 2617 /* Turn off various components of this interface. */ 2618 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2619 switch (sc->sk_type) { 2620 case SK_GENESIS: 2621 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2622 SK_TXMACCTL_XMAC_RESET); 2623 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2624 break; 2625 case SK_YUKON: 2626 case SK_YUKON_LITE: 2627 case SK_YUKON_LP: 2628 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2629 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2630 break; 2631 } 2632 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2633 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2634 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2635 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2636 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2637 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2638 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2639 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2640 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2641 2642 /* Disable interrupts */ 2643 if (sc_if->sk_port == SK_PORT_A) 2644 sc->sk_intrmask &= ~SK_INTRS1; 2645 else 2646 sc->sk_intrmask &= ~SK_INTRS2; 2647 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2648 2649 SK_XM_READ_2(sc_if, XM_ISR); 2650 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2651 2652 /* Free RX and TX mbufs still in the queues. */ 2653 for (i = 0; i < SK_RX_RING_CNT; i++) { 2654 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2655 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2656 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2657 } 2658 } 2659 2660 for (i = 0; i < SK_TX_RING_CNT; i++) { 2661 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2662 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2663 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2664 } 2665 } 2666 2667 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2668 } 2669 2670 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2671 2672 /* 2673 struct cfdriver skc_cd = { 2674 0, "skc", DV_DULL 2675 }; 2676 */ 2677 2678 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2679 2680 /* 2681 struct cfdriver sk_cd = { 2682 0, "sk", DV_IFNET 2683 }; 2684 */ 2685 2686 #ifdef SK_DEBUG 2687 void 2688 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2689 { 2690 #define DESC_PRINT(X) \ 2691 if (desc->X) \ 2692 printf("txdesc[%d]." #X "=%#x\n", \ 2693 idx, desc->X); 2694 2695 DESC_PRINT(sk_ctl); 2696 DESC_PRINT(sk_next); 2697 DESC_PRINT(sk_data_lo); 2698 DESC_PRINT(sk_data_hi); 2699 DESC_PRINT(sk_xmac_txstat); 2700 DESC_PRINT(sk_rsvd0); 2701 DESC_PRINT(sk_csum_startval); 2702 DESC_PRINT(sk_csum_startpos); 2703 DESC_PRINT(sk_csum_writepos); 2704 DESC_PRINT(sk_rsvd1); 2705 #undef PRINT 2706 } 2707 2708 void 2709 sk_dump_bytes(const char *data, int len) 2710 { 2711 int c, i, j; 2712 2713 for (i = 0; i < len; i += 16) { 2714 printf("%08x ", i); 2715 c = len - i; 2716 if (c > 16) c = 16; 2717 2718 for (j = 0; j < c; j++) { 2719 printf("%02x ", data[i + j] & 0xff); 2720 if ((j & 0xf) == 7 && j > 0) 2721 printf(" "); 2722 } 2723 2724 for (; j < 16; j++) 2725 printf(" "); 2726 printf(" "); 2727 2728 for (j = 0; j < c; j++) { 2729 int ch = data[i + j] & 0xff; 2730 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2731 } 2732 2733 printf("\n"); 2734 2735 if (c < 16) 2736 break; 2737 } 2738 } 2739 2740 void 2741 sk_dump_mbuf(struct mbuf *m) 2742 { 2743 int count = m->m_pkthdr.len; 2744 2745 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2746 2747 while (count > 0 && m) { 2748 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2749 m, m->m_data, m->m_len); 2750 sk_dump_bytes(mtod(m, char *), m->m_len); 2751 2752 count -= m->m_len; 2753 m = m->m_next; 2754 } 2755 } 2756 #endif 2757
Indexes created Mon Oct 13 15:10:03 GMT 2025