if_sk.c revision 1.72
1 /* $NetBSD: if_sk.c,v 1.72 2012/07/22 14:33:03 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.72 2012/07/22 14:33:03 matt Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/sockio.h> 123 #include <sys/mbuf.h> 124 #include <sys/malloc.h> 125 #include <sys/mutex.h> 126 #include <sys/kernel.h> 127 #include <sys/socket.h> 128 #include <sys/device.h> 129 #include <sys/queue.h> 130 #include <sys/callout.h> 131 #include <sys/sysctl.h> 132 #include <sys/endian.h> 133 134 #include <net/if.h> 135 #include <net/if_dl.h> 136 #include <net/if_types.h> 137 138 #include <net/if_media.h> 139 140 #include <net/bpf.h> 141 #include <sys/rnd.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 #include <dev/mii/brgphyreg.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 #include <dev/pci/pcidevs.h> 150 151 /* #define SK_USEIOSPACE */ 152 153 #include <dev/pci/if_skreg.h> 154 #include <dev/pci/if_skvar.h> 155 156 int skc_probe(device_t, cfdata_t, void *); 157 void skc_attach(device_t, device_t, void *aux); 158 int sk_probe(device_t, cfdata_t, void *); 159 void sk_attach(device_t, device_t, void *aux); 160 int skcprint(void *, const char *); 161 int sk_intr(void *); 162 void sk_intr_bcom(struct sk_if_softc *); 163 void sk_intr_xmac(struct sk_if_softc *); 164 void sk_intr_yukon(struct sk_if_softc *); 165 void sk_rxeof(struct sk_if_softc *); 166 void sk_txeof(struct sk_if_softc *); 167 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 168 void sk_start(struct ifnet *); 169 int sk_ioctl(struct ifnet *, u_long, void *); 170 int sk_init(struct ifnet *); 171 void sk_init_xmac(struct sk_if_softc *); 172 void sk_init_yukon(struct sk_if_softc *); 173 void sk_stop(struct ifnet *, int); 174 void sk_watchdog(struct ifnet *); 175 void sk_shutdown(void *); 176 int sk_ifmedia_upd(struct ifnet *); 177 void sk_reset(struct sk_softc *); 178 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 179 int sk_alloc_jumbo_mem(struct sk_if_softc *); 180 void sk_free_jumbo_mem(struct sk_if_softc *); 181 void *sk_jalloc(struct sk_if_softc *); 182 void sk_jfree(struct mbuf *, void *, size_t, void *); 183 int sk_init_rx_ring(struct sk_if_softc *); 184 int sk_init_tx_ring(struct sk_if_softc *); 185 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 186 void sk_vpd_read_res(struct sk_softc *, 187 struct vpd_res *, int); 188 void sk_vpd_read(struct sk_softc *); 189 190 void sk_update_int_mod(struct sk_softc *); 191 192 int sk_xmac_miibus_readreg(device_t, int, int); 193 void sk_xmac_miibus_writereg(device_t, int, int, int); 194 void sk_xmac_miibus_statchg(struct ifnet *); 195 196 int sk_marv_miibus_readreg(device_t, int, int); 197 void sk_marv_miibus_writereg(device_t, int, int, int); 198 void sk_marv_miibus_statchg(struct ifnet *); 199 200 u_int32_t sk_xmac_hash(void *); 201 u_int32_t sk_yukon_hash(void *); 202 void sk_setfilt(struct sk_if_softc *, void *, int); 203 void sk_setmulti(struct sk_if_softc *); 204 void sk_tick(void *); 205 206 static bool skc_suspend(device_t, const pmf_qual_t *); 207 static bool skc_resume(device_t, const pmf_qual_t *); 208 static bool sk_resume(device_t dv, const pmf_qual_t *); 209 210 /* #define SK_DEBUG 2 */ 211 #ifdef SK_DEBUG 212 #define DPRINTF(x) if (skdebug) printf x 213 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 214 int skdebug = SK_DEBUG; 215 216 void sk_dump_txdesc(struct sk_tx_desc *, int); 217 void sk_dump_mbuf(struct mbuf *); 218 void sk_dump_bytes(const char *, int); 219 #else 220 #define DPRINTF(x) 221 #define DPRINTFN(n,x) 222 #endif 223 224 static int sk_sysctl_handler(SYSCTLFN_PROTO); 225 static int sk_root_num; 226 227 /* supported device vendors */ 228 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 229 static const struct sk_product { 230 pci_vendor_id_t sk_vendor; 231 pci_product_id_t sk_product; 232 } sk_products[] = { 233 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 234 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 235 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 236 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 237 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 238 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 239 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 240 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 241 { 0, 0, } 242 }; 243 244 #define SK_LINKSYS_EG1032_SUBID 0x00151737 245 246 static inline u_int32_t 247 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 248 { 249 #ifdef SK_USEIOSPACE 250 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 251 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 252 #else 253 return CSR_READ_4(sc, reg); 254 #endif 255 } 256 257 static inline u_int16_t 258 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 259 { 260 #ifdef SK_USEIOSPACE 261 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 262 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 263 #else 264 return CSR_READ_2(sc, reg); 265 #endif 266 } 267 268 static inline u_int8_t 269 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 270 { 271 #ifdef SK_USEIOSPACE 272 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 273 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 274 #else 275 return CSR_READ_1(sc, reg); 276 #endif 277 } 278 279 static inline void 280 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 281 { 282 #ifdef SK_USEIOSPACE 283 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 284 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 285 #else 286 CSR_WRITE_4(sc, reg, x); 287 #endif 288 } 289 290 static inline void 291 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 292 { 293 #ifdef SK_USEIOSPACE 294 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 295 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 296 #else 297 CSR_WRITE_2(sc, reg, x); 298 #endif 299 } 300 301 static inline void 302 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 303 { 304 #ifdef SK_USEIOSPACE 305 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 306 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 307 #else 308 CSR_WRITE_1(sc, reg, x); 309 #endif 310 } 311 312 /* 313 * The VPD EEPROM contains Vital Product Data, as suggested in 314 * the PCI 2.1 specification. The VPD data is separared into areas 315 * denoted by resource IDs. The SysKonnect VPD contains an ID string 316 * resource (the name of the adapter), a read-only area resource 317 * containing various key/data fields and a read/write area which 318 * can be used to store asset management information or log messages. 319 * We read the ID string and read-only into buffers attached to 320 * the controller softc structure for later use. At the moment, 321 * we only use the ID string during sk_attach(). 322 */ 323 u_int8_t 324 sk_vpd_readbyte(struct sk_softc *sc, int addr) 325 { 326 int i; 327 328 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 329 for (i = 0; i < SK_TIMEOUT; i++) { 330 DELAY(1); 331 if (sk_win_read_2(sc, 332 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 333 break; 334 } 335 336 if (i == SK_TIMEOUT) 337 return 0; 338 339 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 340 } 341 342 void 343 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 344 { 345 int i; 346 u_int8_t *ptr; 347 348 ptr = (u_int8_t *)res; 349 for (i = 0; i < sizeof(struct vpd_res); i++) 350 ptr[i] = sk_vpd_readbyte(sc, i + addr); 351 } 352 353 void 354 sk_vpd_read(struct sk_softc *sc) 355 { 356 int pos = 0, i; 357 struct vpd_res res; 358 359 if (sc->sk_vpd_prodname != NULL) 360 free(sc->sk_vpd_prodname, M_DEVBUF); 361 if (sc->sk_vpd_readonly != NULL) 362 free(sc->sk_vpd_readonly, M_DEVBUF); 363 sc->sk_vpd_prodname = NULL; 364 sc->sk_vpd_readonly = NULL; 365 366 sk_vpd_read_res(sc, &res, pos); 367 368 if (res.vr_id != VPD_RES_ID) { 369 aprint_error_dev(sc->sk_dev, 370 "bad VPD resource id: expected %x got %x\n", 371 VPD_RES_ID, res.vr_id); 372 return; 373 } 374 375 pos += sizeof(res); 376 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 377 if (sc->sk_vpd_prodname == NULL) 378 panic("sk_vpd_read"); 379 for (i = 0; i < res.vr_len; i++) 380 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 381 sc->sk_vpd_prodname[i] = '\0'; 382 pos += i; 383 384 sk_vpd_read_res(sc, &res, pos); 385 386 if (res.vr_id != VPD_RES_READ) { 387 aprint_error_dev(sc->sk_dev, 388 "bad VPD resource id: expected %x got %x\n", 389 VPD_RES_READ, res.vr_id); 390 return; 391 } 392 393 pos += sizeof(res); 394 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 395 if (sc->sk_vpd_readonly == NULL) 396 panic("sk_vpd_read"); 397 for (i = 0; i < res.vr_len ; i++) 398 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 399 } 400 401 int 402 sk_xmac_miibus_readreg(device_t dev, int phy, int reg) 403 { 404 struct sk_if_softc *sc_if = device_private(dev); 405 int i; 406 407 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 408 409 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 410 return 0; 411 412 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 413 SK_XM_READ_2(sc_if, XM_PHY_DATA); 414 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 415 for (i = 0; i < SK_TIMEOUT; i++) { 416 DELAY(1); 417 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 418 XM_MMUCMD_PHYDATARDY) 419 break; 420 } 421 422 if (i == SK_TIMEOUT) { 423 aprint_error_dev(sc_if->sk_dev, 424 "phy failed to come ready\n"); 425 return 0; 426 } 427 } 428 DELAY(1); 429 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 430 } 431 432 void 433 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, int val) 434 { 435 struct sk_if_softc *sc_if = device_private(dev); 436 int i; 437 438 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 439 440 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 441 for (i = 0; i < SK_TIMEOUT; i++) { 442 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 443 break; 444 } 445 446 if (i == SK_TIMEOUT) { 447 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 448 return; 449 } 450 451 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 452 for (i = 0; i < SK_TIMEOUT; i++) { 453 DELAY(1); 454 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 455 break; 456 } 457 458 if (i == SK_TIMEOUT) 459 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 460 } 461 462 void 463 sk_xmac_miibus_statchg(struct ifnet *ifp) 464 { 465 struct sk_if_softc *sc_if = ifp->if_softc; 466 struct mii_data *mii = &sc_if->sk_mii; 467 468 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 469 470 /* 471 * If this is a GMII PHY, manually set the XMAC's 472 * duplex mode accordingly. 473 */ 474 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 475 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 476 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 477 else 478 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 479 } 480 } 481 482 int 483 sk_marv_miibus_readreg(device_t dev, int phy, int reg) 484 { 485 struct sk_if_softc *sc_if = device_private(dev); 486 u_int16_t val; 487 int i; 488 489 if (phy != 0 || 490 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 491 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 492 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 493 phy, reg)); 494 return 0; 495 } 496 497 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 498 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 499 500 for (i = 0; i < SK_TIMEOUT; i++) { 501 DELAY(1); 502 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 503 if (val & YU_SMICR_READ_VALID) 504 break; 505 } 506 507 if (i == SK_TIMEOUT) { 508 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 509 return 0; 510 } 511 512 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 513 SK_TIMEOUT)); 514 515 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 516 517 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 518 phy, reg, val)); 519 520 return val; 521 } 522 523 void 524 sk_marv_miibus_writereg(device_t dev, int phy, int reg, int val) 525 { 526 struct sk_if_softc *sc_if = device_private(dev); 527 int i; 528 529 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 530 phy, reg, val)); 531 532 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 533 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 534 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 535 536 for (i = 0; i < SK_TIMEOUT; i++) { 537 DELAY(1); 538 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 539 break; 540 } 541 542 if (i == SK_TIMEOUT) 543 printf("%s: phy write timed out\n", 544 device_xname(sc_if->sk_dev)); 545 } 546 547 void 548 sk_marv_miibus_statchg(struct ifnet *ifp) 549 { 550 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 551 SK_YU_READ_2(((struct sk_if_softc *)ifp->if_softc), 552 YUKON_GPCR))); 553 } 554 555 #define SK_HASH_BITS 6 556 557 u_int32_t 558 sk_xmac_hash(void *addr) 559 { 560 u_int32_t crc; 561 562 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 563 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 564 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 565 return crc; 566 } 567 568 u_int32_t 569 sk_yukon_hash(void *addr) 570 { 571 u_int32_t crc; 572 573 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 574 crc &= ((1 << SK_HASH_BITS) - 1); 575 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 576 return crc; 577 } 578 579 void 580 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 581 { 582 char *addr = addrv; 583 int base = XM_RXFILT_ENTRY(slot); 584 585 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 586 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 587 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 588 } 589 590 void 591 sk_setmulti(struct sk_if_softc *sc_if) 592 { 593 struct sk_softc *sc = sc_if->sk_softc; 594 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 595 u_int32_t hashes[2] = { 0, 0 }; 596 int h = 0, i; 597 struct ethercom *ec = &sc_if->sk_ethercom; 598 struct ether_multi *enm; 599 struct ether_multistep step; 600 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 601 602 /* First, zot all the existing filters. */ 603 switch (sc->sk_type) { 604 case SK_GENESIS: 605 for (i = 1; i < XM_RXFILT_MAX; i++) 606 sk_setfilt(sc_if, (void *)&dummy, i); 607 608 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 609 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 610 break; 611 case SK_YUKON: 612 case SK_YUKON_LITE: 613 case SK_YUKON_LP: 614 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 615 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 616 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 617 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 618 break; 619 } 620 621 /* Now program new ones. */ 622 allmulti: 623 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 624 hashes[0] = 0xFFFFFFFF; 625 hashes[1] = 0xFFFFFFFF; 626 } else { 627 i = 1; 628 /* First find the tail of the list. */ 629 ETHER_FIRST_MULTI(step, ec, enm); 630 while (enm != NULL) { 631 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 632 ETHER_ADDR_LEN)) { 633 ifp->if_flags |= IFF_ALLMULTI; 634 goto allmulti; 635 } 636 DPRINTFN(2,("multicast address %s\n", 637 ether_sprintf(enm->enm_addrlo))); 638 /* 639 * Program the first XM_RXFILT_MAX multicast groups 640 * into the perfect filter. For all others, 641 * use the hash table. 642 */ 643 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 644 sk_setfilt(sc_if, enm->enm_addrlo, i); 645 i++; 646 } 647 else { 648 switch (sc->sk_type) { 649 case SK_GENESIS: 650 h = sk_xmac_hash(enm->enm_addrlo); 651 break; 652 case SK_YUKON: 653 case SK_YUKON_LITE: 654 case SK_YUKON_LP: 655 h = sk_yukon_hash(enm->enm_addrlo); 656 break; 657 } 658 if (h < 32) 659 hashes[0] |= (1 << h); 660 else 661 hashes[1] |= (1 << (h - 32)); 662 } 663 664 ETHER_NEXT_MULTI(step, enm); 665 } 666 } 667 668 switch (sc->sk_type) { 669 case SK_GENESIS: 670 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 671 XM_MODE_RX_USE_PERFECT); 672 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 673 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 674 break; 675 case SK_YUKON: 676 case SK_YUKON_LITE: 677 case SK_YUKON_LP: 678 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 679 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 680 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 681 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 682 break; 683 } 684 } 685 686 int 687 sk_init_rx_ring(struct sk_if_softc *sc_if) 688 { 689 struct sk_chain_data *cd = &sc_if->sk_cdata; 690 struct sk_ring_data *rd = sc_if->sk_rdata; 691 int i; 692 693 memset((char *)rd->sk_rx_ring, 0, 694 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 695 696 for (i = 0; i < SK_RX_RING_CNT; i++) { 697 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 698 if (i == (SK_RX_RING_CNT - 1)) { 699 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 700 rd->sk_rx_ring[i].sk_next = 701 htole32(SK_RX_RING_ADDR(sc_if, 0)); 702 } else { 703 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 704 rd->sk_rx_ring[i].sk_next = 705 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 706 } 707 } 708 709 for (i = 0; i < SK_RX_RING_CNT; i++) { 710 if (sk_newbuf(sc_if, i, NULL, 711 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 712 aprint_error_dev(sc_if->sk_dev, 713 "failed alloc of %dth mbuf\n", i); 714 return ENOBUFS; 715 } 716 } 717 sc_if->sk_cdata.sk_rx_prod = 0; 718 sc_if->sk_cdata.sk_rx_cons = 0; 719 720 return 0; 721 } 722 723 int 724 sk_init_tx_ring(struct sk_if_softc *sc_if) 725 { 726 struct sk_chain_data *cd = &sc_if->sk_cdata; 727 struct sk_ring_data *rd = sc_if->sk_rdata; 728 int i; 729 730 memset(sc_if->sk_rdata->sk_tx_ring, 0, 731 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 732 733 for (i = 0; i < SK_TX_RING_CNT; i++) { 734 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 735 if (i == (SK_TX_RING_CNT - 1)) { 736 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 737 rd->sk_tx_ring[i].sk_next = 738 htole32(SK_TX_RING_ADDR(sc_if, 0)); 739 } else { 740 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 741 rd->sk_tx_ring[i].sk_next = 742 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 743 } 744 } 745 746 sc_if->sk_cdata.sk_tx_prod = 0; 747 sc_if->sk_cdata.sk_tx_cons = 0; 748 sc_if->sk_cdata.sk_tx_cnt = 0; 749 750 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 751 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 752 753 return 0; 754 } 755 756 int 757 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 758 bus_dmamap_t dmamap) 759 { 760 struct mbuf *m_new = NULL; 761 struct sk_chain *c; 762 struct sk_rx_desc *r; 763 764 if (m == NULL) { 765 void *buf = NULL; 766 767 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 768 if (m_new == NULL) { 769 aprint_error_dev(sc_if->sk_dev, 770 "no memory for rx list -- packet dropped!\n"); 771 return ENOBUFS; 772 } 773 774 /* Allocate the jumbo buffer */ 775 buf = sk_jalloc(sc_if); 776 if (buf == NULL) { 777 m_freem(m_new); 778 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 779 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 780 return ENOBUFS; 781 } 782 783 /* Attach the buffer to the mbuf */ 784 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 785 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 786 787 } else { 788 /* 789 * We're re-using a previously allocated mbuf; 790 * be sure to re-init pointers and lengths to 791 * default values. 792 */ 793 m_new = m; 794 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 795 m_new->m_data = m_new->m_ext.ext_buf; 796 } 797 m_adj(m_new, ETHER_ALIGN); 798 799 c = &sc_if->sk_cdata.sk_rx_chain[i]; 800 r = c->sk_desc; 801 c->sk_mbuf = m_new; 802 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 803 (((vaddr_t)m_new->m_data 804 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 805 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 806 807 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 808 809 return 0; 810 } 811 812 /* 813 * Memory management for jumbo frames. 814 */ 815 816 int 817 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 818 { 819 struct sk_softc *sc = sc_if->sk_softc; 820 char *ptr, *kva; 821 bus_dma_segment_t seg; 822 int i, rseg, state, error; 823 struct sk_jpool_entry *entry; 824 825 state = error = 0; 826 827 /* Grab a big chunk o' storage. */ 828 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 829 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 830 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 831 return ENOBUFS; 832 } 833 834 state = 1; 835 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 836 BUS_DMA_NOWAIT)) { 837 aprint_error_dev(sc->sk_dev, 838 "can't map dma buffers (%d bytes)\n", 839 SK_JMEM); 840 error = ENOBUFS; 841 goto out; 842 } 843 844 state = 2; 845 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 846 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 847 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 848 error = ENOBUFS; 849 goto out; 850 } 851 852 state = 3; 853 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 854 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 855 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 856 error = ENOBUFS; 857 goto out; 858 } 859 860 state = 4; 861 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 862 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 863 864 LIST_INIT(&sc_if->sk_jfree_listhead); 865 LIST_INIT(&sc_if->sk_jinuse_listhead); 866 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 867 868 /* 869 * Now divide it up into 9K pieces and save the addresses 870 * in an array. 871 */ 872 ptr = sc_if->sk_cdata.sk_jumbo_buf; 873 for (i = 0; i < SK_JSLOTS; i++) { 874 sc_if->sk_cdata.sk_jslots[i] = ptr; 875 ptr += SK_JLEN; 876 entry = malloc(sizeof(struct sk_jpool_entry), 877 M_DEVBUF, M_NOWAIT); 878 if (entry == NULL) { 879 aprint_error_dev(sc->sk_dev, 880 "no memory for jumbo buffer queue!\n"); 881 error = ENOBUFS; 882 goto out; 883 } 884 entry->slot = i; 885 if (i) 886 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 887 entry, jpool_entries); 888 else 889 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 890 entry, jpool_entries); 891 } 892 out: 893 if (error != 0) { 894 switch (state) { 895 case 4: 896 bus_dmamap_unload(sc->sc_dmatag, 897 sc_if->sk_cdata.sk_rx_jumbo_map); 898 case 3: 899 bus_dmamap_destroy(sc->sc_dmatag, 900 sc_if->sk_cdata.sk_rx_jumbo_map); 901 case 2: 902 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 903 case 1: 904 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 905 break; 906 default: 907 break; 908 } 909 } 910 911 return error; 912 } 913 914 /* 915 * Allocate a jumbo buffer. 916 */ 917 void * 918 sk_jalloc(struct sk_if_softc *sc_if) 919 { 920 struct sk_jpool_entry *entry; 921 922 mutex_enter(&sc_if->sk_jpool_mtx); 923 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 924 925 if (entry == NULL) { 926 mutex_exit(&sc_if->sk_jpool_mtx); 927 return NULL; 928 } 929 930 LIST_REMOVE(entry, jpool_entries); 931 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 932 mutex_exit(&sc_if->sk_jpool_mtx); 933 return sc_if->sk_cdata.sk_jslots[entry->slot]; 934 } 935 936 /* 937 * Release a jumbo buffer. 938 */ 939 void 940 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 941 { 942 struct sk_jpool_entry *entry; 943 struct sk_if_softc *sc; 944 int i; 945 946 /* Extract the softc struct pointer. */ 947 sc = (struct sk_if_softc *)arg; 948 949 if (sc == NULL) 950 panic("sk_jfree: can't find softc pointer!"); 951 952 /* calculate the slot this buffer belongs to */ 953 954 i = ((vaddr_t)buf 955 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 956 957 if ((i < 0) || (i >= SK_JSLOTS)) 958 panic("sk_jfree: asked to free buffer that we don't manage!"); 959 960 mutex_enter(&sc->sk_jpool_mtx); 961 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 962 if (entry == NULL) 963 panic("sk_jfree: buffer not in use!"); 964 entry->slot = i; 965 LIST_REMOVE(entry, jpool_entries); 966 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 967 mutex_exit(&sc->sk_jpool_mtx); 968 969 if (__predict_true(m != NULL)) 970 pool_cache_put(mb_cache, m); 971 } 972 973 /* 974 * Set media options. 975 */ 976 int 977 sk_ifmedia_upd(struct ifnet *ifp) 978 { 979 struct sk_if_softc *sc_if = ifp->if_softc; 980 int rc; 981 982 (void) sk_init(ifp); 983 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 984 return 0; 985 return rc; 986 } 987 988 int 989 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 990 { 991 struct sk_if_softc *sc_if = ifp->if_softc; 992 struct sk_softc *sc = sc_if->sk_softc; 993 int s, error = 0; 994 995 /* DPRINTFN(2, ("sk_ioctl\n")); */ 996 997 s = splnet(); 998 999 switch (command) { 1000 1001 case SIOCSIFFLAGS: 1002 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1003 if ((error = ifioctl_common(ifp, command, data)) != 0) 1004 break; 1005 if (ifp->if_flags & IFF_UP) { 1006 if (ifp->if_flags & IFF_RUNNING && 1007 ifp->if_flags & IFF_PROMISC && 1008 !(sc_if->sk_if_flags & IFF_PROMISC)) { 1009 switch (sc->sk_type) { 1010 case SK_GENESIS: 1011 SK_XM_SETBIT_4(sc_if, XM_MODE, 1012 XM_MODE_RX_PROMISC); 1013 break; 1014 case SK_YUKON: 1015 case SK_YUKON_LITE: 1016 case SK_YUKON_LP: 1017 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1018 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1019 break; 1020 } 1021 sk_setmulti(sc_if); 1022 } else if (ifp->if_flags & IFF_RUNNING && 1023 !(ifp->if_flags & IFF_PROMISC) && 1024 sc_if->sk_if_flags & IFF_PROMISC) { 1025 switch (sc->sk_type) { 1026 case SK_GENESIS: 1027 SK_XM_CLRBIT_4(sc_if, XM_MODE, 1028 XM_MODE_RX_PROMISC); 1029 break; 1030 case SK_YUKON: 1031 case SK_YUKON_LITE: 1032 case SK_YUKON_LP: 1033 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1034 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1035 break; 1036 } 1037 1038 sk_setmulti(sc_if); 1039 } else 1040 (void) sk_init(ifp); 1041 } else { 1042 if (ifp->if_flags & IFF_RUNNING) 1043 sk_stop(ifp,0); 1044 } 1045 sc_if->sk_if_flags = ifp->if_flags; 1046 error = 0; 1047 break; 1048 1049 default: 1050 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1051 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1052 break; 1053 1054 error = 0; 1055 1056 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1057 ; 1058 else if (ifp->if_flags & IFF_RUNNING) { 1059 sk_setmulti(sc_if); 1060 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1061 } 1062 break; 1063 } 1064 1065 splx(s); 1066 return error; 1067 } 1068 1069 void 1070 sk_update_int_mod(struct sk_softc *sc) 1071 { 1072 u_int32_t imtimer_ticks; 1073 1074 /* 1075 * Configure interrupt moderation. The moderation timer 1076 * defers interrupts specified in the interrupt moderation 1077 * timer mask based on the timeout specified in the interrupt 1078 * moderation timer init register. Each bit in the timer 1079 * register represents one tick, so to specify a timeout in 1080 * microseconds, we have to multiply by the correct number of 1081 * ticks-per-microsecond. 1082 */ 1083 switch (sc->sk_type) { 1084 case SK_GENESIS: 1085 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1086 break; 1087 case SK_YUKON_EC: 1088 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1089 break; 1090 default: 1091 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1092 } 1093 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1094 sc->sk_int_mod); 1095 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1096 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1097 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1098 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1099 sc->sk_int_mod_pending = 0; 1100 } 1101 1102 /* 1103 * Lookup: Check the PCI vendor and device, and return a pointer to 1104 * The structure if the IDs match against our list. 1105 */ 1106 1107 static const struct sk_product * 1108 sk_lookup(const struct pci_attach_args *pa) 1109 { 1110 const struct sk_product *psk; 1111 1112 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1113 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1114 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1115 return psk; 1116 } 1117 return NULL; 1118 } 1119 1120 /* 1121 * Probe for a SysKonnect GEnesis chip. 1122 */ 1123 1124 int 1125 skc_probe(device_t parent, cfdata_t match, void *aux) 1126 { 1127 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1128 const struct sk_product *psk; 1129 pcireg_t subid; 1130 1131 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1132 1133 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1134 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1135 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1136 subid == SK_LINKSYS_EG1032_SUBID) 1137 return 1; 1138 1139 if ((psk = sk_lookup(pa))) { 1140 return 1; 1141 } 1142 return 0; 1143 } 1144 1145 /* 1146 * Force the GEnesis into reset, then bring it out of reset. 1147 */ 1148 void sk_reset(struct sk_softc *sc) 1149 { 1150 DPRINTFN(2, ("sk_reset\n")); 1151 1152 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1153 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1154 if (SK_YUKON_FAMILY(sc->sk_type)) 1155 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1156 1157 DELAY(1000); 1158 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1159 DELAY(2); 1160 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1161 if (SK_YUKON_FAMILY(sc->sk_type)) 1162 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1163 1164 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1165 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1166 CSR_READ_2(sc, SK_LINK_CTRL))); 1167 1168 if (sc->sk_type == SK_GENESIS) { 1169 /* Configure packet arbiter */ 1170 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1171 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1172 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1173 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1174 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1175 } 1176 1177 /* Enable RAM interface */ 1178 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1179 1180 sk_update_int_mod(sc); 1181 } 1182 1183 int 1184 sk_probe(device_t parent, cfdata_t match, void *aux) 1185 { 1186 struct skc_attach_args *sa = aux; 1187 1188 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1189 return 0; 1190 1191 return 1; 1192 } 1193 1194 /* 1195 * Each XMAC chip is attached as a separate logical IP interface. 1196 * Single port cards will have only one logical interface of course. 1197 */ 1198 void 1199 sk_attach(device_t parent, device_t self, void *aux) 1200 { 1201 struct sk_if_softc *sc_if = device_private(self); 1202 struct sk_softc *sc = device_private(parent); 1203 struct skc_attach_args *sa = aux; 1204 struct sk_txmap_entry *entry; 1205 struct ifnet *ifp; 1206 bus_dma_segment_t seg; 1207 bus_dmamap_t dmamap; 1208 prop_data_t data; 1209 void *kva; 1210 int i, rseg; 1211 int mii_flags = 0; 1212 1213 aprint_naive("\n"); 1214 1215 sc_if->sk_dev = self; 1216 sc_if->sk_port = sa->skc_port; 1217 sc_if->sk_softc = sc; 1218 sc->sk_if[sa->skc_port] = sc_if; 1219 1220 if (sa->skc_port == SK_PORT_A) 1221 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1222 if (sa->skc_port == SK_PORT_B) 1223 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1224 1225 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1226 1227 /* 1228 * Get station address for this interface. Note that 1229 * dual port cards actually come with three station 1230 * addresses: one for each port, plus an extra. The 1231 * extra one is used by the SysKonnect driver software 1232 * as a 'virtual' station address for when both ports 1233 * are operating in failover mode. Currently we don't 1234 * use this extra address. 1235 */ 1236 data = prop_dictionary_get(device_properties(self), "mac-address"); 1237 if (data != NULL) { 1238 /* 1239 * Try to get the station address from device properties 1240 * first, in case the ROM is missing. 1241 */ 1242 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 1243 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 1244 memcpy(sc_if->sk_enaddr, prop_data_data_nocopy(data), 1245 ETHER_ADDR_LEN); 1246 } else 1247 for (i = 0; i < ETHER_ADDR_LEN; i++) 1248 sc_if->sk_enaddr[i] = sk_win_read_1(sc, 1249 SK_MAC0_0 + (sa->skc_port * 8) + i); 1250 1251 aprint_normal(": Ethernet address %s\n", 1252 ether_sprintf(sc_if->sk_enaddr)); 1253 1254 /* 1255 * Set up RAM buffer addresses. The NIC will have a certain 1256 * amount of SRAM on it, somewhere between 512K and 2MB. We 1257 * need to divide this up a) between the transmitter and 1258 * receiver and b) between the two XMACs, if this is a 1259 * dual port NIC. Our algorithm is to divide up the memory 1260 * evenly so that everyone gets a fair share. 1261 */ 1262 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1263 u_int32_t chunk, val; 1264 1265 chunk = sc->sk_ramsize / 2; 1266 val = sc->sk_rboff / sizeof(u_int64_t); 1267 sc_if->sk_rx_ramstart = val; 1268 val += (chunk / sizeof(u_int64_t)); 1269 sc_if->sk_rx_ramend = val - 1; 1270 sc_if->sk_tx_ramstart = val; 1271 val += (chunk / sizeof(u_int64_t)); 1272 sc_if->sk_tx_ramend = val - 1; 1273 } else { 1274 u_int32_t chunk, val; 1275 1276 chunk = sc->sk_ramsize / 4; 1277 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1278 sizeof(u_int64_t); 1279 sc_if->sk_rx_ramstart = val; 1280 val += (chunk / sizeof(u_int64_t)); 1281 sc_if->sk_rx_ramend = val - 1; 1282 sc_if->sk_tx_ramstart = val; 1283 val += (chunk / sizeof(u_int64_t)); 1284 sc_if->sk_tx_ramend = val - 1; 1285 } 1286 1287 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1288 " tx_ramstart=%#x tx_ramend=%#x\n", 1289 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1290 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1291 1292 /* Read and save PHY type and set PHY address */ 1293 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1294 switch (sc_if->sk_phytype) { 1295 case SK_PHYTYPE_XMAC: 1296 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1297 break; 1298 case SK_PHYTYPE_BCOM: 1299 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1300 break; 1301 case SK_PHYTYPE_MARV_COPPER: 1302 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1303 break; 1304 default: 1305 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1306 sc_if->sk_phytype); 1307 return; 1308 } 1309 1310 /* Allocate the descriptor queues. */ 1311 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1312 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1313 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1314 goto fail; 1315 } 1316 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1317 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1318 aprint_error_dev(sc_if->sk_dev, 1319 "can't map dma buffers (%lu bytes)\n", 1320 (u_long) sizeof(struct sk_ring_data)); 1321 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1322 goto fail; 1323 } 1324 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1325 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1326 &sc_if->sk_ring_map)) { 1327 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1328 bus_dmamem_unmap(sc->sc_dmatag, kva, 1329 sizeof(struct sk_ring_data)); 1330 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1331 goto fail; 1332 } 1333 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1334 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1335 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1336 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1337 bus_dmamem_unmap(sc->sc_dmatag, kva, 1338 sizeof(struct sk_ring_data)); 1339 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1340 goto fail; 1341 } 1342 1343 for (i = 0; i < SK_RX_RING_CNT; i++) 1344 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1345 1346 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1347 for (i = 0; i < SK_TX_RING_CNT; i++) { 1348 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1349 1350 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1351 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1352 aprint_error_dev(sc_if->sk_dev, 1353 "Can't create TX dmamap\n"); 1354 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1355 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1356 bus_dmamem_unmap(sc->sc_dmatag, kva, 1357 sizeof(struct sk_ring_data)); 1358 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1359 goto fail; 1360 } 1361 1362 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1363 if (!entry) { 1364 aprint_error_dev(sc_if->sk_dev, 1365 "Can't alloc txmap entry\n"); 1366 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1367 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1368 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1369 bus_dmamem_unmap(sc->sc_dmatag, kva, 1370 sizeof(struct sk_ring_data)); 1371 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1372 goto fail; 1373 } 1374 entry->dmamap = dmamap; 1375 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1376 } 1377 1378 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1379 memset(sc_if->sk_rdata, 0, sizeof(struct sk_ring_data)); 1380 1381 ifp = &sc_if->sk_ethercom.ec_if; 1382 /* Try to allocate memory for jumbo buffers. */ 1383 if (sk_alloc_jumbo_mem(sc_if)) { 1384 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1385 goto fail; 1386 } 1387 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1388 | ETHERCAP_JUMBO_MTU; 1389 1390 ifp->if_softc = sc_if; 1391 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1392 ifp->if_ioctl = sk_ioctl; 1393 ifp->if_start = sk_start; 1394 ifp->if_stop = sk_stop; 1395 ifp->if_init = sk_init; 1396 ifp->if_watchdog = sk_watchdog; 1397 ifp->if_capabilities = 0; 1398 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1399 IFQ_SET_READY(&ifp->if_snd); 1400 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1401 1402 /* 1403 * Do miibus setup. 1404 */ 1405 switch (sc->sk_type) { 1406 case SK_GENESIS: 1407 sk_init_xmac(sc_if); 1408 break; 1409 case SK_YUKON: 1410 case SK_YUKON_LITE: 1411 case SK_YUKON_LP: 1412 sk_init_yukon(sc_if); 1413 break; 1414 default: 1415 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1416 sc->sk_type); 1417 goto fail; 1418 } 1419 1420 DPRINTFN(2, ("sk_attach: 1\n")); 1421 1422 sc_if->sk_mii.mii_ifp = ifp; 1423 switch (sc->sk_type) { 1424 case SK_GENESIS: 1425 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1426 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1427 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1428 break; 1429 case SK_YUKON: 1430 case SK_YUKON_LITE: 1431 case SK_YUKON_LP: 1432 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1433 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1434 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1435 mii_flags = MIIF_DOPAUSE; 1436 break; 1437 } 1438 1439 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1440 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1441 sk_ifmedia_upd, ether_mediastatus); 1442 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1443 MII_OFFSET_ANY, mii_flags); 1444 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1445 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1446 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1447 0, NULL); 1448 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1449 } else 1450 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1451 1452 callout_init(&sc_if->sk_tick_ch, 0); 1453 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1454 1455 DPRINTFN(2, ("sk_attach: 1\n")); 1456 1457 /* 1458 * Call MI attach routines. 1459 */ 1460 if_attach(ifp); 1461 1462 ether_ifattach(ifp, sc_if->sk_enaddr); 1463 1464 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1465 RND_TYPE_NET, 0); 1466 1467 if (pmf_device_register(self, NULL, sk_resume)) 1468 pmf_class_network_register(self, ifp); 1469 else 1470 aprint_error_dev(self, "couldn't establish power handler\n"); 1471 1472 DPRINTFN(2, ("sk_attach: end\n")); 1473 1474 return; 1475 1476 fail: 1477 sc->sk_if[sa->skc_port] = NULL; 1478 } 1479 1480 int 1481 skcprint(void *aux, const char *pnp) 1482 { 1483 struct skc_attach_args *sa = aux; 1484 1485 if (pnp) 1486 aprint_normal("sk port %c at %s", 1487 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1488 else 1489 aprint_normal(" port %c", 1490 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1491 return UNCONF; 1492 } 1493 1494 /* 1495 * Attach the interface. Allocate softc structures, do ifmedia 1496 * setup and ethernet/BPF attach. 1497 */ 1498 void 1499 skc_attach(device_t parent, device_t self, void *aux) 1500 { 1501 struct sk_softc *sc = device_private(self); 1502 struct pci_attach_args *pa = aux; 1503 struct skc_attach_args skca; 1504 pci_chipset_tag_t pc = pa->pa_pc; 1505 #ifndef SK_USEIOSPACE 1506 pcireg_t memtype; 1507 #endif 1508 pci_intr_handle_t ih; 1509 const char *intrstr = NULL; 1510 bus_addr_t iobase; 1511 bus_size_t iosize; 1512 int rc, sk_nodenum; 1513 u_int32_t command; 1514 const char *revstr; 1515 const struct sysctlnode *node; 1516 1517 sc->sk_dev = self; 1518 aprint_naive("\n"); 1519 1520 DPRINTFN(2, ("begin skc_attach\n")); 1521 1522 /* 1523 * Handle power management nonsense. 1524 */ 1525 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1526 1527 if (command == 0x01) { 1528 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1529 if (command & SK_PSTATE_MASK) { 1530 u_int32_t xiobase, membase, irq; 1531 1532 /* Save important PCI config data. */ 1533 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1534 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1535 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1536 1537 /* Reset the power state. */ 1538 aprint_normal_dev(sc->sk_dev, 1539 "chip is in D%d power mode -- setting to D0\n", 1540 command & SK_PSTATE_MASK); 1541 command &= 0xFFFFFFFC; 1542 pci_conf_write(pc, pa->pa_tag, 1543 SK_PCI_PWRMGMTCTRL, command); 1544 1545 /* Restore PCI config data. */ 1546 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1547 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1548 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1549 } 1550 } 1551 1552 /* 1553 * The firmware might have configured the interface to revert the 1554 * byte order in all descriptors. Make that undone. 1555 */ 1556 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_OURREG2); 1557 if (command & SK_REG2_REV_DESC) 1558 pci_conf_write(pc, pa->pa_tag, SK_PCI_OURREG2, 1559 command & ~SK_REG2_REV_DESC); 1560 1561 /* 1562 * Map control/status registers. 1563 */ 1564 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1565 command |= PCI_COMMAND_IO_ENABLE | 1566 PCI_COMMAND_MEM_ENABLE | 1567 PCI_COMMAND_MASTER_ENABLE; 1568 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1569 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1570 1571 #ifdef SK_USEIOSPACE 1572 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1573 aprint_error(": failed to enable I/O ports!\n"); 1574 return; 1575 } 1576 /* 1577 * Map control/status registers. 1578 */ 1579 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1580 &sc->sk_btag, &sc->sk_bhandle, 1581 &iobase, &iosize)) { 1582 aprint_error(": can't find i/o space\n"); 1583 return; 1584 } 1585 #else 1586 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1587 aprint_error(": failed to enable memory mapping!\n"); 1588 return; 1589 } 1590 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1591 switch (memtype) { 1592 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1593 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1594 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1595 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1596 &iobase, &iosize) == 0) 1597 break; 1598 default: 1599 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1600 return; 1601 } 1602 1603 DPRINTFN(2, ("skc_attach: iobase=%#" PRIxPADDR ", iosize=%zx\n", 1604 iobase, iosize)); 1605 #endif 1606 sc->sc_dmatag = pa->pa_dmat; 1607 1608 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1609 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1610 1611 /* bail out here if chip is not recognized */ 1612 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1613 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1614 goto fail; 1615 } 1616 if (SK_IS_YUKON2(sc)) { 1617 aprint_error_dev(sc->sk_dev, 1618 "Does not support Yukon2--try msk(4).\n"); 1619 goto fail; 1620 } 1621 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1622 1623 /* Allocate interrupt */ 1624 if (pci_intr_map(pa, &ih)) { 1625 aprint_error(": couldn't map interrupt\n"); 1626 goto fail; 1627 } 1628 1629 intrstr = pci_intr_string(pc, ih); 1630 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1631 if (sc->sk_intrhand == NULL) { 1632 aprint_error(": couldn't establish interrupt"); 1633 if (intrstr != NULL) 1634 aprint_error(" at %s", intrstr); 1635 aprint_error("\n"); 1636 goto fail; 1637 } 1638 aprint_normal(": %s\n", intrstr); 1639 1640 /* Reset the adapter. */ 1641 sk_reset(sc); 1642 1643 /* Read and save vital product data from EEPROM. */ 1644 sk_vpd_read(sc); 1645 1646 if (sc->sk_type == SK_GENESIS) { 1647 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1648 /* Read and save RAM size and RAMbuffer offset */ 1649 switch (val) { 1650 case SK_RAMSIZE_512K_64: 1651 sc->sk_ramsize = 0x80000; 1652 sc->sk_rboff = SK_RBOFF_0; 1653 break; 1654 case SK_RAMSIZE_1024K_64: 1655 sc->sk_ramsize = 0x100000; 1656 sc->sk_rboff = SK_RBOFF_80000; 1657 break; 1658 case SK_RAMSIZE_1024K_128: 1659 sc->sk_ramsize = 0x100000; 1660 sc->sk_rboff = SK_RBOFF_0; 1661 break; 1662 case SK_RAMSIZE_2048K_128: 1663 sc->sk_ramsize = 0x200000; 1664 sc->sk_rboff = SK_RBOFF_0; 1665 break; 1666 default: 1667 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1668 val); 1669 goto fail_1; 1670 break; 1671 } 1672 1673 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1674 sc->sk_ramsize, sc->sk_ramsize / 1024, 1675 sc->sk_rboff)); 1676 } else { 1677 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1678 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1679 sc->sk_rboff = SK_RBOFF_0; 1680 1681 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1682 sc->sk_ramsize / 1024, sc->sk_ramsize, 1683 sc->sk_rboff)); 1684 } 1685 1686 /* Read and save physical media type */ 1687 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1688 case SK_PMD_1000BASESX: 1689 sc->sk_pmd = IFM_1000_SX; 1690 break; 1691 case SK_PMD_1000BASELX: 1692 sc->sk_pmd = IFM_1000_LX; 1693 break; 1694 case SK_PMD_1000BASECX: 1695 sc->sk_pmd = IFM_1000_CX; 1696 break; 1697 case SK_PMD_1000BASETX: 1698 case SK_PMD_1000BASETX_ALT: 1699 sc->sk_pmd = IFM_1000_T; 1700 break; 1701 default: 1702 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1703 sk_win_read_1(sc, SK_PMDTYPE)); 1704 goto fail_1; 1705 } 1706 1707 /* determine whether to name it with vpd or just make it up */ 1708 /* Marvell Yukon VPD's can freqently be bogus */ 1709 1710 switch (pa->pa_id) { 1711 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1712 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1713 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1714 case PCI_PRODUCT_3COM_3C940: 1715 case PCI_PRODUCT_DLINK_DGE530T: 1716 case PCI_PRODUCT_DLINK_DGE560T: 1717 case PCI_PRODUCT_DLINK_DGE560T_2: 1718 case PCI_PRODUCT_LINKSYS_EG1032: 1719 case PCI_PRODUCT_LINKSYS_EG1064: 1720 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1721 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1722 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1723 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1724 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1725 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1726 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1727 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1728 sc->sk_name = sc->sk_vpd_prodname; 1729 break; 1730 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1731 /* whoops yukon vpd prodname bears no resemblance to reality */ 1732 switch (sc->sk_type) { 1733 case SK_GENESIS: 1734 sc->sk_name = sc->sk_vpd_prodname; 1735 break; 1736 case SK_YUKON: 1737 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1738 break; 1739 case SK_YUKON_LITE: 1740 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1741 break; 1742 case SK_YUKON_LP: 1743 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1744 break; 1745 default: 1746 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1747 } 1748 1749 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1750 1751 if ( sc->sk_type == SK_YUKON ) { 1752 uint32_t flashaddr; 1753 uint8_t testbyte; 1754 1755 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1756 1757 /* test Flash-Address Register */ 1758 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1759 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1760 1761 if (testbyte != 0) { 1762 /* this is yukon lite Rev. A0 */ 1763 sc->sk_type = SK_YUKON_LITE; 1764 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1765 /* restore Flash-Address Register */ 1766 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1767 } 1768 } 1769 break; 1770 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1771 sc->sk_name = sc->sk_vpd_prodname; 1772 break; 1773 default: 1774 sc->sk_name = "Unknown Marvell"; 1775 } 1776 1777 1778 if ( sc->sk_type == SK_YUKON_LITE ) { 1779 switch (sc->sk_rev) { 1780 case SK_YUKON_LITE_REV_A0: 1781 revstr = "A0"; 1782 break; 1783 case SK_YUKON_LITE_REV_A1: 1784 revstr = "A1"; 1785 break; 1786 case SK_YUKON_LITE_REV_A3: 1787 revstr = "A3"; 1788 break; 1789 default: 1790 revstr = ""; 1791 } 1792 } else { 1793 revstr = ""; 1794 } 1795 1796 /* Announce the product name. */ 1797 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1798 sc->sk_name, revstr, sc->sk_rev); 1799 1800 skca.skc_port = SK_PORT_A; 1801 (void)config_found(sc->sk_dev, &skca, skcprint); 1802 1803 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1804 skca.skc_port = SK_PORT_B; 1805 (void)config_found(sc->sk_dev, &skca, skcprint); 1806 } 1807 1808 /* Turn on the 'driver is loaded' LED. */ 1809 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1810 1811 /* skc sysctl setup */ 1812 1813 sc->sk_int_mod = SK_IM_DEFAULT; 1814 sc->sk_int_mod_pending = 0; 1815 1816 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1817 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1818 SYSCTL_DESCR("skc per-controller controls"), 1819 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1820 CTL_EOL)) != 0) { 1821 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1822 goto fail_1; 1823 } 1824 1825 sk_nodenum = node->sysctl_num; 1826 1827 /* interrupt moderation time in usecs */ 1828 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1829 CTLFLAG_READWRITE, 1830 CTLTYPE_INT, "int_mod", 1831 SYSCTL_DESCR("sk interrupt moderation timer"), 1832 sk_sysctl_handler, 0, (void *)sc, 1833 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1834 CTL_EOL)) != 0) { 1835 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1836 goto fail_1; 1837 } 1838 1839 if (!pmf_device_register(self, skc_suspend, skc_resume)) 1840 aprint_error_dev(self, "couldn't establish power handler\n"); 1841 1842 return; 1843 1844 fail_1: 1845 pci_intr_disestablish(pc, sc->sk_intrhand); 1846 fail: 1847 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1848 } 1849 1850 int 1851 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1852 { 1853 struct sk_softc *sc = sc_if->sk_softc; 1854 struct sk_tx_desc *f = NULL; 1855 u_int32_t frag, cur, cnt = 0, sk_ctl; 1856 int i; 1857 struct sk_txmap_entry *entry; 1858 bus_dmamap_t txmap; 1859 1860 DPRINTFN(3, ("sk_encap\n")); 1861 1862 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1863 if (entry == NULL) { 1864 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1865 return ENOBUFS; 1866 } 1867 txmap = entry->dmamap; 1868 1869 cur = frag = *txidx; 1870 1871 #ifdef SK_DEBUG 1872 if (skdebug >= 3) 1873 sk_dump_mbuf(m_head); 1874 #endif 1875 1876 /* 1877 * Start packing the mbufs in this chain into 1878 * the fragment pointers. Stop when we run out 1879 * of fragments or hit the end of the mbuf chain. 1880 */ 1881 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1882 BUS_DMA_NOWAIT)) { 1883 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1884 return ENOBUFS; 1885 } 1886 1887 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1888 1889 /* Sync the DMA map. */ 1890 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1891 BUS_DMASYNC_PREWRITE); 1892 1893 for (i = 0; i < txmap->dm_nsegs; i++) { 1894 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1895 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1896 return ENOBUFS; 1897 } 1898 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1899 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1900 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1901 if (cnt == 0) 1902 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1903 else 1904 sk_ctl |= SK_TXCTL_OWN; 1905 f->sk_ctl = htole32(sk_ctl); 1906 cur = frag; 1907 SK_INC(frag, SK_TX_RING_CNT); 1908 cnt++; 1909 } 1910 1911 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1912 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1913 1914 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1915 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1916 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1917 1918 /* Sync descriptors before handing to chip */ 1919 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1920 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1921 1922 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1923 htole32(SK_TXCTL_OWN); 1924 1925 /* Sync first descriptor to hand it off */ 1926 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1927 1928 sc_if->sk_cdata.sk_tx_cnt += cnt; 1929 1930 #ifdef SK_DEBUG 1931 if (skdebug >= 3) { 1932 struct sk_tx_desc *desc; 1933 u_int32_t idx; 1934 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1935 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1936 sk_dump_txdesc(desc, idx); 1937 } 1938 } 1939 #endif 1940 1941 *txidx = frag; 1942 1943 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1944 1945 return 0; 1946 } 1947 1948 void 1949 sk_start(struct ifnet *ifp) 1950 { 1951 struct sk_if_softc *sc_if = ifp->if_softc; 1952 struct sk_softc *sc = sc_if->sk_softc; 1953 struct mbuf *m_head = NULL; 1954 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1955 int pkts = 0; 1956 1957 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1958 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1959 1960 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1961 IFQ_POLL(&ifp->if_snd, m_head); 1962 if (m_head == NULL) 1963 break; 1964 1965 /* 1966 * Pack the data into the transmit ring. If we 1967 * don't have room, set the OACTIVE flag and wait 1968 * for the NIC to drain the ring. 1969 */ 1970 if (sk_encap(sc_if, m_head, &idx)) { 1971 ifp->if_flags |= IFF_OACTIVE; 1972 break; 1973 } 1974 1975 /* now we are committed to transmit the packet */ 1976 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1977 pkts++; 1978 1979 /* 1980 * If there's a BPF listener, bounce a copy of this frame 1981 * to him. 1982 */ 1983 bpf_mtap(ifp, m_head); 1984 } 1985 if (pkts == 0) 1986 return; 1987 1988 /* Transmit */ 1989 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1990 sc_if->sk_cdata.sk_tx_prod = idx; 1991 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1992 1993 /* Set a timeout in case the chip goes out to lunch. */ 1994 ifp->if_timer = 5; 1995 } 1996 } 1997 1998 1999 void 2000 sk_watchdog(struct ifnet *ifp) 2001 { 2002 struct sk_if_softc *sc_if = ifp->if_softc; 2003 2004 /* 2005 * Reclaim first as there is a possibility of losing Tx completion 2006 * interrupts. 2007 */ 2008 sk_txeof(sc_if); 2009 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2010 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 2011 2012 ifp->if_oerrors++; 2013 2014 sk_init(ifp); 2015 } 2016 } 2017 2018 void 2019 sk_shutdown(void *v) 2020 { 2021 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2022 struct sk_softc *sc = sc_if->sk_softc; 2023 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2024 2025 DPRINTFN(2, ("sk_shutdown\n")); 2026 sk_stop(ifp,1); 2027 2028 /* Turn off the 'driver is loaded' LED. */ 2029 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2030 2031 /* 2032 * Reset the GEnesis controller. Doing this should also 2033 * assert the resets on the attached XMAC(s). 2034 */ 2035 sk_reset(sc); 2036 } 2037 2038 void 2039 sk_rxeof(struct sk_if_softc *sc_if) 2040 { 2041 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2042 struct mbuf *m; 2043 struct sk_chain *cur_rx; 2044 struct sk_rx_desc *cur_desc; 2045 int i, cur, total_len = 0; 2046 u_int32_t rxstat, sk_ctl; 2047 bus_dmamap_t dmamap; 2048 2049 i = sc_if->sk_cdata.sk_rx_prod; 2050 2051 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2052 2053 for (;;) { 2054 cur = i; 2055 2056 /* Sync the descriptor */ 2057 SK_CDRXSYNC(sc_if, cur, 2058 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2059 2060 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2061 if (sk_ctl & SK_RXCTL_OWN) { 2062 /* Invalidate the descriptor -- it's not ready yet */ 2063 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2064 sc_if->sk_cdata.sk_rx_prod = i; 2065 break; 2066 } 2067 2068 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2069 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2070 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2071 2072 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2073 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2074 2075 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2076 m = cur_rx->sk_mbuf; 2077 cur_rx->sk_mbuf = NULL; 2078 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2079 2080 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2081 2082 SK_INC(i, SK_RX_RING_CNT); 2083 2084 if (rxstat & XM_RXSTAT_ERRFRAME) { 2085 ifp->if_ierrors++; 2086 sk_newbuf(sc_if, cur, m, dmamap); 2087 continue; 2088 } 2089 2090 /* 2091 * Try to allocate a new jumbo buffer. If that 2092 * fails, copy the packet to mbufs and put the 2093 * jumbo buffer back in the ring so it can be 2094 * re-used. If allocating mbufs fails, then we 2095 * have to drop the packet. 2096 */ 2097 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2098 struct mbuf *m0; 2099 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2100 total_len + ETHER_ALIGN, 0, ifp, NULL); 2101 sk_newbuf(sc_if, cur, m, dmamap); 2102 if (m0 == NULL) { 2103 aprint_error_dev(sc_if->sk_dev, "no receive " 2104 "buffers available -- packet dropped!\n"); 2105 ifp->if_ierrors++; 2106 continue; 2107 } 2108 m_adj(m0, ETHER_ALIGN); 2109 m = m0; 2110 } else { 2111 m->m_pkthdr.rcvif = ifp; 2112 m->m_pkthdr.len = m->m_len = total_len; 2113 } 2114 2115 ifp->if_ipackets++; 2116 2117 bpf_mtap(ifp, m); 2118 /* pass it on. */ 2119 (*ifp->if_input)(ifp, m); 2120 } 2121 } 2122 2123 void 2124 sk_txeof(struct sk_if_softc *sc_if) 2125 { 2126 struct sk_softc *sc = sc_if->sk_softc; 2127 struct sk_tx_desc *cur_tx; 2128 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2129 u_int32_t idx, sk_ctl; 2130 struct sk_txmap_entry *entry; 2131 2132 DPRINTFN(3, ("sk_txeof\n")); 2133 2134 /* 2135 * Go through our tx ring and free mbufs for those 2136 * frames that have been sent. 2137 */ 2138 idx = sc_if->sk_cdata.sk_tx_cons; 2139 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2140 SK_CDTXSYNC(sc_if, idx, 1, 2141 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2142 2143 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2144 sk_ctl = le32toh(cur_tx->sk_ctl); 2145 #ifdef SK_DEBUG 2146 if (skdebug >= 3) 2147 sk_dump_txdesc(cur_tx, idx); 2148 #endif 2149 if (sk_ctl & SK_TXCTL_OWN) { 2150 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2151 break; 2152 } 2153 if (sk_ctl & SK_TXCTL_LASTFRAG) 2154 ifp->if_opackets++; 2155 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2156 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2157 2158 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2159 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2160 2161 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2162 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2163 2164 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2165 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2166 link); 2167 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2168 } 2169 sc_if->sk_cdata.sk_tx_cnt--; 2170 SK_INC(idx, SK_TX_RING_CNT); 2171 } 2172 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2173 ifp->if_timer = 0; 2174 else /* nudge chip to keep tx ring moving */ 2175 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2176 2177 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2178 ifp->if_flags &= ~IFF_OACTIVE; 2179 2180 sc_if->sk_cdata.sk_tx_cons = idx; 2181 } 2182 2183 void 2184 sk_tick(void *xsc_if) 2185 { 2186 struct sk_if_softc *sc_if = xsc_if; 2187 struct mii_data *mii = &sc_if->sk_mii; 2188 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2189 int i; 2190 2191 DPRINTFN(3, ("sk_tick\n")); 2192 2193 if (!(ifp->if_flags & IFF_UP)) 2194 return; 2195 2196 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2197 sk_intr_bcom(sc_if); 2198 return; 2199 } 2200 2201 /* 2202 * According to SysKonnect, the correct way to verify that 2203 * the link has come back up is to poll bit 0 of the GPIO 2204 * register three times. This pin has the signal from the 2205 * link sync pin connected to it; if we read the same link 2206 * state 3 times in a row, we know the link is up. 2207 */ 2208 for (i = 0; i < 3; i++) { 2209 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2210 break; 2211 } 2212 2213 if (i != 3) { 2214 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2215 return; 2216 } 2217 2218 /* Turn the GP0 interrupt back on. */ 2219 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2220 SK_XM_READ_2(sc_if, XM_ISR); 2221 mii_tick(mii); 2222 mii_pollstat(mii); 2223 callout_stop(&sc_if->sk_tick_ch); 2224 } 2225 2226 void 2227 sk_intr_bcom(struct sk_if_softc *sc_if) 2228 { 2229 struct mii_data *mii = &sc_if->sk_mii; 2230 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2231 int status; 2232 2233 2234 DPRINTFN(3, ("sk_intr_bcom\n")); 2235 2236 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2237 2238 /* 2239 * Read the PHY interrupt register to make sure 2240 * we clear any pending interrupts. 2241 */ 2242 status = sk_xmac_miibus_readreg(sc_if->sk_dev, 2243 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2244 2245 if (!(ifp->if_flags & IFF_RUNNING)) { 2246 sk_init_xmac(sc_if); 2247 return; 2248 } 2249 2250 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2251 int lstat; 2252 lstat = sk_xmac_miibus_readreg(sc_if->sk_dev, 2253 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2254 2255 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2256 (void)mii_mediachg(mii); 2257 /* Turn off the link LED. */ 2258 SK_IF_WRITE_1(sc_if, 0, 2259 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2260 sc_if->sk_link = 0; 2261 } else if (status & BRGPHY_ISR_LNK_CHG) { 2262 sk_xmac_miibus_writereg(sc_if->sk_dev, 2263 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2264 mii_tick(mii); 2265 sc_if->sk_link = 1; 2266 /* Turn on the link LED. */ 2267 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2268 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2269 SK_LINKLED_BLINK_OFF); 2270 mii_pollstat(mii); 2271 } else { 2272 mii_tick(mii); 2273 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2274 } 2275 } 2276 2277 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2278 } 2279 2280 void 2281 sk_intr_xmac(struct sk_if_softc *sc_if) 2282 { 2283 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2284 2285 DPRINTFN(3, ("sk_intr_xmac\n")); 2286 2287 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2288 if (status & XM_ISR_GP0_SET) { 2289 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2290 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2291 } 2292 2293 if (status & XM_ISR_AUTONEG_DONE) { 2294 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2295 } 2296 } 2297 2298 if (status & XM_IMR_TX_UNDERRUN) 2299 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2300 2301 if (status & XM_IMR_RX_OVERRUN) 2302 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2303 } 2304 2305 void 2306 sk_intr_yukon(struct sk_if_softc *sc_if) 2307 { 2308 int status; 2309 2310 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2311 2312 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2313 } 2314 2315 int 2316 sk_intr(void *xsc) 2317 { 2318 struct sk_softc *sc = xsc; 2319 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2320 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2321 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2322 u_int32_t status; 2323 int claimed = 0; 2324 2325 if (sc_if0 != NULL) 2326 ifp0 = &sc_if0->sk_ethercom.ec_if; 2327 if (sc_if1 != NULL) 2328 ifp1 = &sc_if1->sk_ethercom.ec_if; 2329 2330 for (;;) { 2331 status = CSR_READ_4(sc, SK_ISSR); 2332 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2333 2334 if (!(status & sc->sk_intrmask)) 2335 break; 2336 2337 claimed = 1; 2338 2339 /* Handle receive interrupts first. */ 2340 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2341 sk_rxeof(sc_if0); 2342 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2343 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2344 } 2345 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2346 sk_rxeof(sc_if1); 2347 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2348 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2349 } 2350 2351 /* Then transmit interrupts. */ 2352 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2353 sk_txeof(sc_if0); 2354 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2355 SK_TXBMU_CLR_IRQ_EOF); 2356 } 2357 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2358 sk_txeof(sc_if1); 2359 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2360 SK_TXBMU_CLR_IRQ_EOF); 2361 } 2362 2363 /* Then MAC interrupts. */ 2364 if (sc_if0 && (status & SK_ISR_MAC1) && 2365 (ifp0->if_flags & IFF_RUNNING)) { 2366 if (sc->sk_type == SK_GENESIS) 2367 sk_intr_xmac(sc_if0); 2368 else 2369 sk_intr_yukon(sc_if0); 2370 } 2371 2372 if (sc_if1 && (status & SK_ISR_MAC2) && 2373 (ifp1->if_flags & IFF_RUNNING)) { 2374 if (sc->sk_type == SK_GENESIS) 2375 sk_intr_xmac(sc_if1); 2376 else 2377 sk_intr_yukon(sc_if1); 2378 2379 } 2380 2381 if (status & SK_ISR_EXTERNAL_REG) { 2382 if (sc_if0 != NULL && 2383 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2384 sk_intr_bcom(sc_if0); 2385 2386 if (sc_if1 != NULL && 2387 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2388 sk_intr_bcom(sc_if1); 2389 } 2390 } 2391 2392 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2393 2394 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2395 sk_start(ifp0); 2396 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2397 sk_start(ifp1); 2398 2399 rnd_add_uint32(&sc->rnd_source, status); 2400 2401 if (sc->sk_int_mod_pending) 2402 sk_update_int_mod(sc); 2403 2404 return claimed; 2405 } 2406 2407 void 2408 sk_init_xmac(struct sk_if_softc *sc_if) 2409 { 2410 struct sk_softc *sc = sc_if->sk_softc; 2411 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2412 static const struct sk_bcom_hack bhack[] = { 2413 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2414 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2415 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2416 { 0, 0 } }; 2417 2418 DPRINTFN(1, ("sk_init_xmac\n")); 2419 2420 /* Unreset the XMAC. */ 2421 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2422 DELAY(1000); 2423 2424 /* Reset the XMAC's internal state. */ 2425 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2426 2427 /* Save the XMAC II revision */ 2428 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2429 2430 /* 2431 * Perform additional initialization for external PHYs, 2432 * namely for the 1000baseTX cards that use the XMAC's 2433 * GMII mode. 2434 */ 2435 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2436 int i = 0; 2437 u_int32_t val; 2438 2439 /* Take PHY out of reset. */ 2440 val = sk_win_read_4(sc, SK_GPIO); 2441 if (sc_if->sk_port == SK_PORT_A) 2442 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2443 else 2444 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2445 sk_win_write_4(sc, SK_GPIO, val); 2446 2447 /* Enable GMII mode on the XMAC. */ 2448 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2449 2450 sk_xmac_miibus_writereg(sc_if->sk_dev, 2451 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2452 DELAY(10000); 2453 sk_xmac_miibus_writereg(sc_if->sk_dev, 2454 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2455 2456 /* 2457 * Early versions of the BCM5400 apparently have 2458 * a bug that requires them to have their reserved 2459 * registers initialized to some magic values. I don't 2460 * know what the numbers do, I'm just the messenger. 2461 */ 2462 if (sk_xmac_miibus_readreg(sc_if->sk_dev, 2463 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2464 while (bhack[i].reg) { 2465 sk_xmac_miibus_writereg(sc_if->sk_dev, 2466 SK_PHYADDR_BCOM, bhack[i].reg, 2467 bhack[i].val); 2468 i++; 2469 } 2470 } 2471 } 2472 2473 /* Set station address */ 2474 SK_XM_WRITE_2(sc_if, XM_PAR0, 2475 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2476 SK_XM_WRITE_2(sc_if, XM_PAR1, 2477 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2478 SK_XM_WRITE_2(sc_if, XM_PAR2, 2479 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2480 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2481 2482 if (ifp->if_flags & IFF_PROMISC) 2483 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2484 else 2485 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2486 2487 if (ifp->if_flags & IFF_BROADCAST) 2488 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2489 else 2490 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2491 2492 /* We don't need the FCS appended to the packet. */ 2493 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2494 2495 /* We want short frames padded to 60 bytes. */ 2496 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2497 2498 /* 2499 * Enable the reception of all error frames. This is is 2500 * a necessary evil due to the design of the XMAC. The 2501 * XMAC's receive FIFO is only 8K in size, however jumbo 2502 * frames can be up to 9000 bytes in length. When bad 2503 * frame filtering is enabled, the XMAC's RX FIFO operates 2504 * in 'store and forward' mode. For this to work, the 2505 * entire frame has to fit into the FIFO, but that means 2506 * that jumbo frames larger than 8192 bytes will be 2507 * truncated. Disabling all bad frame filtering causes 2508 * the RX FIFO to operate in streaming mode, in which 2509 * case the XMAC will start transfering frames out of the 2510 * RX FIFO as soon as the FIFO threshold is reached. 2511 */ 2512 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2513 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2514 XM_MODE_RX_INRANGELEN); 2515 2516 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2517 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2518 else 2519 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2520 2521 /* 2522 * Bump up the transmit threshold. This helps hold off transmit 2523 * underruns when we're blasting traffic from both ports at once. 2524 */ 2525 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2526 2527 /* Set multicast filter */ 2528 sk_setmulti(sc_if); 2529 2530 /* Clear and enable interrupts */ 2531 SK_XM_READ_2(sc_if, XM_ISR); 2532 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2533 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2534 else 2535 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2536 2537 /* Configure MAC arbiter */ 2538 switch (sc_if->sk_xmac_rev) { 2539 case XM_XMAC_REV_B2: 2540 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2541 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2542 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2543 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2544 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2545 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2546 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2547 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2548 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2549 break; 2550 case XM_XMAC_REV_C1: 2551 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2552 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2553 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2554 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2555 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2556 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2557 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2558 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2559 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2560 break; 2561 default: 2562 break; 2563 } 2564 sk_win_write_2(sc, SK_MACARB_CTL, 2565 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2566 2567 sc_if->sk_link = 1; 2568 } 2569 2570 void sk_init_yukon(struct sk_if_softc *sc_if) 2571 { 2572 u_int32_t /*mac, */phy; 2573 u_int16_t reg; 2574 struct sk_softc *sc; 2575 int i; 2576 2577 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2578 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2579 2580 sc = sc_if->sk_softc; 2581 if (sc->sk_type == SK_YUKON_LITE && 2582 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2583 /* Take PHY out of reset. */ 2584 sk_win_write_4(sc, SK_GPIO, 2585 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2586 } 2587 2588 2589 /* GMAC and GPHY Reset */ 2590 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2591 2592 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2593 2594 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2595 DELAY(1000); 2596 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2597 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2598 DELAY(1000); 2599 2600 2601 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2602 2603 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2604 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2605 2606 switch (sc_if->sk_softc->sk_pmd) { 2607 case IFM_1000_SX: 2608 case IFM_1000_LX: 2609 phy |= SK_GPHY_FIBER; 2610 break; 2611 2612 case IFM_1000_CX: 2613 case IFM_1000_T: 2614 phy |= SK_GPHY_COPPER; 2615 break; 2616 } 2617 2618 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2619 2620 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2621 DELAY(1000); 2622 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2623 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2624 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2625 2626 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2627 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2628 2629 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2630 2631 /* unused read of the interrupt source register */ 2632 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2633 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2634 2635 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2636 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2637 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2638 2639 /* MIB Counter Clear Mode set */ 2640 reg |= YU_PAR_MIB_CLR; 2641 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2642 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2643 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2644 2645 /* MIB Counter Clear Mode clear */ 2646 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2647 reg &= ~YU_PAR_MIB_CLR; 2648 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2649 2650 /* receive control reg */ 2651 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2652 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2653 YU_RCR_CRCR); 2654 2655 /* transmit parameter register */ 2656 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2657 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2658 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2659 2660 /* serial mode register */ 2661 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2662 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2663 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2664 YU_SMR_IPG_DATA(0x1e)); 2665 2666 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2667 /* Setup Yukon's address */ 2668 for (i = 0; i < 3; i++) { 2669 /* Write Source Address 1 (unicast filter) */ 2670 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2671 sc_if->sk_enaddr[i * 2] | 2672 sc_if->sk_enaddr[i * 2 + 1] << 8); 2673 } 2674 2675 for (i = 0; i < 3; i++) { 2676 reg = sk_win_read_2(sc_if->sk_softc, 2677 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2678 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2679 } 2680 2681 /* Set multicast filter */ 2682 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2683 sk_setmulti(sc_if); 2684 2685 /* enable interrupt mask for counter overflows */ 2686 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2687 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2688 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2689 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2690 2691 /* Configure RX MAC FIFO */ 2692 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2693 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2694 2695 /* Configure TX MAC FIFO */ 2696 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2697 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2698 2699 DPRINTFN(6, ("sk_init_yukon: end\n")); 2700 } 2701 2702 /* 2703 * Note that to properly initialize any part of the GEnesis chip, 2704 * you first have to take it out of reset mode. 2705 */ 2706 int 2707 sk_init(struct ifnet *ifp) 2708 { 2709 struct sk_if_softc *sc_if = ifp->if_softc; 2710 struct sk_softc *sc = sc_if->sk_softc; 2711 struct mii_data *mii = &sc_if->sk_mii; 2712 int rc = 0, s; 2713 u_int32_t imr, imtimer_ticks; 2714 2715 DPRINTFN(1, ("sk_init\n")); 2716 2717 s = splnet(); 2718 2719 if (ifp->if_flags & IFF_RUNNING) { 2720 splx(s); 2721 return 0; 2722 } 2723 2724 /* Cancel pending I/O and free all RX/TX buffers. */ 2725 sk_stop(ifp,0); 2726 2727 if (sc->sk_type == SK_GENESIS) { 2728 /* Configure LINK_SYNC LED */ 2729 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2730 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2731 SK_LINKLED_LINKSYNC_ON); 2732 2733 /* Configure RX LED */ 2734 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2735 SK_RXLEDCTL_COUNTER_START); 2736 2737 /* Configure TX LED */ 2738 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2739 SK_TXLEDCTL_COUNTER_START); 2740 } 2741 2742 /* Configure I2C registers */ 2743 2744 /* Configure XMAC(s) */ 2745 switch (sc->sk_type) { 2746 case SK_GENESIS: 2747 sk_init_xmac(sc_if); 2748 break; 2749 case SK_YUKON: 2750 case SK_YUKON_LITE: 2751 case SK_YUKON_LP: 2752 sk_init_yukon(sc_if); 2753 break; 2754 } 2755 if ((rc = mii_mediachg(mii)) == ENXIO) 2756 rc = 0; 2757 else if (rc != 0) 2758 goto out; 2759 2760 if (sc->sk_type == SK_GENESIS) { 2761 /* Configure MAC FIFOs */ 2762 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2763 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2764 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2765 2766 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2767 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2768 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2769 } 2770 2771 /* Configure transmit arbiter(s) */ 2772 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2773 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2774 2775 /* Configure RAMbuffers */ 2776 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2777 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2778 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2779 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2780 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2781 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2782 2783 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2784 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2785 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2786 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2787 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2788 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2789 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2790 2791 /* Configure BMUs */ 2792 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2793 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2794 SK_RX_RING_ADDR(sc_if, 0)); 2795 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2796 2797 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2798 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2799 SK_TX_RING_ADDR(sc_if, 0)); 2800 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2801 2802 /* Init descriptors */ 2803 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2804 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2805 "memory for rx buffers\n"); 2806 sk_stop(ifp,0); 2807 splx(s); 2808 return ENOBUFS; 2809 } 2810 2811 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2812 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2813 "memory for tx buffers\n"); 2814 sk_stop(ifp,0); 2815 splx(s); 2816 return ENOBUFS; 2817 } 2818 2819 /* Set interrupt moderation if changed via sysctl. */ 2820 switch (sc->sk_type) { 2821 case SK_GENESIS: 2822 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2823 break; 2824 case SK_YUKON_EC: 2825 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2826 break; 2827 default: 2828 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2829 } 2830 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2831 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2832 sk_win_write_4(sc, SK_IMTIMERINIT, 2833 SK_IM_USECS(sc->sk_int_mod)); 2834 aprint_verbose_dev(sc->sk_dev, 2835 "interrupt moderation is %d us\n", sc->sk_int_mod); 2836 } 2837 2838 /* Configure interrupt handling */ 2839 CSR_READ_4(sc, SK_ISSR); 2840 if (sc_if->sk_port == SK_PORT_A) 2841 sc->sk_intrmask |= SK_INTRS1; 2842 else 2843 sc->sk_intrmask |= SK_INTRS2; 2844 2845 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2846 2847 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2848 2849 /* Start BMUs. */ 2850 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2851 2852 if (sc->sk_type == SK_GENESIS) { 2853 /* Enable XMACs TX and RX state machines */ 2854 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2855 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2856 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2857 } 2858 2859 if (SK_YUKON_FAMILY(sc->sk_type)) { 2860 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2861 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2862 #if 0 2863 /* XXX disable 100Mbps and full duplex mode? */ 2864 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2865 #endif 2866 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2867 } 2868 2869 2870 ifp->if_flags |= IFF_RUNNING; 2871 ifp->if_flags &= ~IFF_OACTIVE; 2872 2873 out: 2874 splx(s); 2875 return rc; 2876 } 2877 2878 void 2879 sk_stop(struct ifnet *ifp, int disable) 2880 { 2881 struct sk_if_softc *sc_if = ifp->if_softc; 2882 struct sk_softc *sc = sc_if->sk_softc; 2883 int i; 2884 2885 DPRINTFN(1, ("sk_stop\n")); 2886 2887 callout_stop(&sc_if->sk_tick_ch); 2888 2889 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2890 u_int32_t val; 2891 2892 /* Put PHY back into reset. */ 2893 val = sk_win_read_4(sc, SK_GPIO); 2894 if (sc_if->sk_port == SK_PORT_A) { 2895 val |= SK_GPIO_DIR0; 2896 val &= ~SK_GPIO_DAT0; 2897 } else { 2898 val |= SK_GPIO_DIR2; 2899 val &= ~SK_GPIO_DAT2; 2900 } 2901 sk_win_write_4(sc, SK_GPIO, val); 2902 } 2903 2904 /* Turn off various components of this interface. */ 2905 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2906 switch (sc->sk_type) { 2907 case SK_GENESIS: 2908 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2909 SK_TXMACCTL_XMAC_RESET); 2910 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2911 break; 2912 case SK_YUKON: 2913 case SK_YUKON_LITE: 2914 case SK_YUKON_LP: 2915 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2916 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2917 break; 2918 } 2919 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2920 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2921 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2922 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2923 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2924 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2925 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2926 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2927 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2928 2929 /* Disable interrupts */ 2930 if (sc_if->sk_port == SK_PORT_A) 2931 sc->sk_intrmask &= ~SK_INTRS1; 2932 else 2933 sc->sk_intrmask &= ~SK_INTRS2; 2934 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2935 2936 SK_XM_READ_2(sc_if, XM_ISR); 2937 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2938 2939 /* Free RX and TX mbufs still in the queues. */ 2940 for (i = 0; i < SK_RX_RING_CNT; i++) { 2941 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2942 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2943 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2944 } 2945 } 2946 2947 for (i = 0; i < SK_TX_RING_CNT; i++) { 2948 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2949 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2950 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2951 } 2952 } 2953 2954 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2955 } 2956 2957 /* Power Management Framework */ 2958 2959 static bool 2960 skc_suspend(device_t dv, const pmf_qual_t *qual) 2961 { 2962 struct sk_softc *sc = device_private(dv); 2963 2964 DPRINTFN(2, ("skc_suspend\n")); 2965 2966 /* Turn off the driver is loaded LED */ 2967 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2968 2969 return true; 2970 } 2971 2972 static bool 2973 skc_resume(device_t dv, const pmf_qual_t *qual) 2974 { 2975 struct sk_softc *sc = device_private(dv); 2976 2977 DPRINTFN(2, ("skc_resume\n")); 2978 2979 sk_reset(sc); 2980 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2981 2982 return true; 2983 } 2984 2985 static bool 2986 sk_resume(device_t dv, const pmf_qual_t *qual) 2987 { 2988 struct sk_if_softc *sc_if = device_private(dv); 2989 2990 sk_init_yukon(sc_if); 2991 return true; 2992 } 2993 2994 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 2995 skc_probe, skc_attach, NULL, NULL); 2996 2997 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 2998 sk_probe, sk_attach, NULL, NULL); 2999 3000 #ifdef SK_DEBUG 3001 void 3002 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 3003 { 3004 #define DESC_PRINT(X) \ 3005 if (X) \ 3006 printf("txdesc[%d]." #X "=%#x\n", \ 3007 idx, X); 3008 3009 DESC_PRINT(le32toh(desc->sk_ctl)); 3010 DESC_PRINT(le32toh(desc->sk_next)); 3011 DESC_PRINT(le32toh(desc->sk_data_lo)); 3012 DESC_PRINT(le32toh(desc->sk_data_hi)); 3013 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 3014 DESC_PRINT(le16toh(desc->sk_rsvd0)); 3015 DESC_PRINT(le16toh(desc->sk_csum_startval)); 3016 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 3017 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 3018 DESC_PRINT(le16toh(desc->sk_rsvd1)); 3019 #undef PRINT 3020 } 3021 3022 void 3023 sk_dump_bytes(const char *data, int len) 3024 { 3025 int c, i, j; 3026 3027 for (i = 0; i < len; i += 16) { 3028 printf("%08x ", i); 3029 c = len - i; 3030 if (c > 16) c = 16; 3031 3032 for (j = 0; j < c; j++) { 3033 printf("%02x ", data[i + j] & 0xff); 3034 if ((j & 0xf) == 7 && j > 0) 3035 printf(" "); 3036 } 3037 3038 for (; j < 16; j++) 3039 printf(" "); 3040 printf(" "); 3041 3042 for (j = 0; j < c; j++) { 3043 int ch = data[i + j] & 0xff; 3044 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3045 } 3046 3047 printf("\n"); 3048 3049 if (c < 16) 3050 break; 3051 } 3052 } 3053 3054 void 3055 sk_dump_mbuf(struct mbuf *m) 3056 { 3057 int count = m->m_pkthdr.len; 3058 3059 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3060 3061 while (count > 0 && m) { 3062 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3063 m, m->m_data, m->m_len); 3064 sk_dump_bytes(mtod(m, char *), m->m_len); 3065 3066 count -= m->m_len; 3067 m = m->m_next; 3068 } 3069 } 3070 #endif 3071 3072 static int 3073 sk_sysctl_handler(SYSCTLFN_ARGS) 3074 { 3075 int error, t; 3076 struct sysctlnode node; 3077 struct sk_softc *sc; 3078 3079 node = *rnode; 3080 sc = node.sysctl_data; 3081 t = sc->sk_int_mod; 3082 node.sysctl_data = &t; 3083 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3084 if (error || newp == NULL) 3085 return error; 3086 3087 if (t < SK_IM_MIN || t > SK_IM_MAX) 3088 return EINVAL; 3089 3090 /* update the softc with sysctl-changed value, and mark 3091 for hardware update */ 3092 sc->sk_int_mod = t; 3093 sc->sk_int_mod_pending = 1; 3094 return 0; 3095 } 3096 3097 /* 3098 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3099 * set up in skc_attach() 3100 */ 3101 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3102 { 3103 int rc; 3104 const struct sysctlnode *node; 3105 3106 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 3107 0, CTLTYPE_NODE, "hw", NULL, 3108 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 3109 goto err; 3110 } 3111 3112 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3113 0, CTLTYPE_NODE, "sk", 3114 SYSCTL_DESCR("sk interface controls"), 3115 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3116 goto err; 3117 } 3118 3119 sk_root_num = node->sysctl_num; 3120 return; 3121 3122 err: 3123 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3124 } 3125
Indexes created Tue Sep 23 14:10:03 GMT 2025