if_sk.c revision 1.8
1 /* $NetBSD: if_sk.c,v 1.8 2004/05/07 00:03:39 kleink Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 126 #include <sys/param.h> 127 #include <sys/systm.h> 128 #include <sys/sockio.h> 129 #include <sys/mbuf.h> 130 #include <sys/malloc.h> 131 #include <sys/kernel.h> 132 #include <sys/socket.h> 133 #include <sys/device.h> 134 #include <sys/queue.h> 135 #include <sys/callout.h> 136 137 #include <net/if.h> 138 #include <net/if_dl.h> 139 #include <net/if_types.h> 140 141 #ifdef INET 142 #include <netinet/in.h> 143 #include <netinet/in_systm.h> 144 #include <netinet/in_var.h> 145 #include <netinet/ip.h> 146 #include <netinet/if_ether.h> 147 #endif 148 149 #include <net/if_media.h> 150 151 #if NBPFILTER > 0 152 #include <net/bpf.h> 153 #endif 154 155 #include <dev/mii/mii.h> 156 #include <dev/mii/miivar.h> 157 #include <dev/mii/brgphyreg.h> 158 159 #include <dev/pci/pcireg.h> 160 #include <dev/pci/pcivar.h> 161 #include <dev/pci/pcidevs.h> 162 163 #define SK_VERBOSE 164 /* #define SK_USEIOSPACE */ 165 166 #include <dev/pci/if_skreg.h> 167 #include <dev/pci/if_skvar.h> 168 169 int skc_probe(struct device *, struct cfdata *, void *); 170 void skc_attach(struct device *, struct device *self, void *aux); 171 int sk_probe(struct device *, struct cfdata *, void *); 172 void sk_attach(struct device *, struct device *self, void *aux); 173 int skcprint(void *, const char *); 174 int sk_intr(void *); 175 void sk_intr_bcom(struct sk_if_softc *); 176 void sk_intr_xmac(struct sk_if_softc *); 177 void sk_intr_yukon(struct sk_if_softc *); 178 void sk_rxeof(struct sk_if_softc *); 179 void sk_txeof(struct sk_if_softc *); 180 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 181 void sk_start(struct ifnet *); 182 int sk_ioctl(struct ifnet *, u_long, caddr_t); 183 int sk_init(struct ifnet *); 184 void sk_init_xmac(struct sk_if_softc *); 185 void sk_init_yukon(struct sk_if_softc *); 186 void sk_stop(struct ifnet *, int); 187 void sk_watchdog(struct ifnet *); 188 void sk_shutdown(void *); 189 int sk_ifmedia_upd(struct ifnet *); 190 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 191 void sk_reset(struct sk_softc *); 192 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 193 int sk_init_rx_ring(struct sk_if_softc *); 194 int sk_init_tx_ring(struct sk_if_softc *); 195 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 196 void sk_vpd_read_res(struct sk_softc *, 197 struct vpd_res *, int); 198 void sk_vpd_read(struct sk_softc *); 199 200 int sk_xmac_miibus_readreg(struct device *, int, int); 201 void sk_xmac_miibus_writereg(struct device *, int, int, int); 202 void sk_xmac_miibus_statchg(struct device *); 203 204 int sk_marv_miibus_readreg(struct device *, int, int); 205 void sk_marv_miibus_writereg(struct device *, int, int, int); 206 void sk_marv_miibus_statchg(struct device *); 207 208 u_int32_t sk_xmac_hash(caddr_t); 209 u_int32_t sk_yukon_hash(caddr_t); 210 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 211 void sk_setmulti(struct sk_if_softc *); 212 void sk_tick(void *); 213 214 /* #define SK_DEBUG 2 */ 215 #ifdef SK_DEBUG 216 #define DPRINTF(x) if (skdebug) printf x 217 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 218 int skdebug = SK_DEBUG; 219 220 void sk_dump_txdesc(struct sk_tx_desc *, int); 221 void sk_dump_mbuf(struct mbuf *); 222 void sk_dump_bytes(const char *, int); 223 #else 224 #define DPRINTF(x) 225 #define DPRINTFN(n,x) 226 #endif 227 228 #define SK_SETBIT(sc, reg, x) \ 229 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 230 231 #define SK_CLRBIT(sc, reg, x) \ 232 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 233 234 #define SK_WIN_SETBIT_4(sc, reg, x) \ 235 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 236 237 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 238 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 239 240 #define SK_WIN_SETBIT_2(sc, reg, x) \ 241 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 242 243 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 244 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 245 246 /* supported device vendors */ 247 static const struct sk_product { 248 pci_vendor_id_t sk_vendor; 249 pci_product_id_t sk_product; 250 } sk_products[] = { 251 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 252 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 253 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, }, 254 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 255 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 256 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 257 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_SKNET, }, 258 { 0, 0, } 259 }; 260 261 static inline u_int32_t 262 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 263 { 264 #ifdef SK_USEIOSPACE 265 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 266 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 267 #else 268 return CSR_READ_4(sc, reg); 269 #endif 270 } 271 272 static inline u_int16_t 273 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 274 { 275 #ifdef SK_USEIOSPACE 276 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 277 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 278 #else 279 return CSR_READ_2(sc, reg); 280 #endif 281 } 282 283 static inline u_int8_t 284 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 285 { 286 #ifdef SK_USEIOSPACE 287 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 288 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 289 #else 290 return CSR_READ_1(sc, reg); 291 #endif 292 } 293 294 static inline void 295 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 296 { 297 #ifdef SK_USEIOSPACE 298 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 299 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 300 #else 301 CSR_WRITE_4(sc, reg, x); 302 #endif 303 } 304 305 static inline void 306 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 307 { 308 #ifdef SK_USEIOSPACE 309 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 310 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 311 #else 312 CSR_WRITE_2(sc, reg, x); 313 #endif 314 } 315 316 static inline void 317 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 318 { 319 #ifdef SK_USEIOSPACE 320 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 321 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 322 #else 323 CSR_WRITE_1(sc, reg, x); 324 #endif 325 } 326 327 /* 328 * The VPD EEPROM contains Vital Product Data, as suggested in 329 * the PCI 2.1 specification. The VPD data is separared into areas 330 * denoted by resource IDs. The SysKonnect VPD contains an ID string 331 * resource (the name of the adapter), a read-only area resource 332 * containing various key/data fields and a read/write area which 333 * can be used to store asset management information or log messages. 334 * We read the ID string and read-only into buffers attached to 335 * the controller softc structure for later use. At the moment, 336 * we only use the ID string during sk_attach(). 337 */ 338 u_int8_t 339 sk_vpd_readbyte(struct sk_softc *sc, int addr) 340 { 341 int i; 342 343 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 344 for (i = 0; i < SK_TIMEOUT; i++) { 345 DELAY(1); 346 if (sk_win_read_2(sc, 347 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 348 break; 349 } 350 351 if (i == SK_TIMEOUT) 352 return(0); 353 354 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 355 } 356 357 void 358 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 359 { 360 int i; 361 u_int8_t *ptr; 362 363 ptr = (u_int8_t *)res; 364 for (i = 0; i < sizeof(struct vpd_res); i++) 365 ptr[i] = sk_vpd_readbyte(sc, i + addr); 366 } 367 368 void 369 sk_vpd_read(struct sk_softc *sc) 370 { 371 int pos = 0, i; 372 struct vpd_res res; 373 374 if (sc->sk_vpd_prodname != NULL) 375 free(sc->sk_vpd_prodname, M_DEVBUF); 376 if (sc->sk_vpd_readonly != NULL) 377 free(sc->sk_vpd_readonly, M_DEVBUF); 378 sc->sk_vpd_prodname = NULL; 379 sc->sk_vpd_readonly = NULL; 380 381 sk_vpd_read_res(sc, &res, pos); 382 383 if (res.vr_id != VPD_RES_ID) { 384 printf("%s: bad VPD resource id: expected %x got %x\n", 385 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 386 return; 387 } 388 389 pos += sizeof(res); 390 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 391 if (sc->sk_vpd_prodname == NULL) 392 panic("sk_vpd_read"); 393 for (i = 0; i < res.vr_len; i++) 394 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 395 sc->sk_vpd_prodname[i] = '\0'; 396 pos += i; 397 398 sk_vpd_read_res(sc, &res, pos); 399 400 if (res.vr_id != VPD_RES_READ) { 401 printf("%s: bad VPD resource id: expected %x got %x\n", 402 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 403 return; 404 } 405 406 pos += sizeof(res); 407 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 408 if (sc->sk_vpd_readonly == NULL) 409 panic("sk_vpd_read"); 410 for (i = 0; i < res.vr_len + 1; i++) 411 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 412 } 413 414 int 415 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 416 { 417 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 418 int i; 419 420 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 421 422 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 423 return(0); 424 425 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 426 SK_XM_READ_2(sc_if, XM_PHY_DATA); 427 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 428 for (i = 0; i < SK_TIMEOUT; i++) { 429 DELAY(1); 430 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 431 XM_MMUCMD_PHYDATARDY) 432 break; 433 } 434 435 if (i == SK_TIMEOUT) { 436 printf("%s: phy failed to come ready\n", 437 sc_if->sk_dev.dv_xname); 438 return(0); 439 } 440 } 441 DELAY(1); 442 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 443 } 444 445 void 446 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 447 { 448 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 449 int i; 450 451 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 452 453 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 454 for (i = 0; i < SK_TIMEOUT; i++) { 455 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 456 break; 457 } 458 459 if (i == SK_TIMEOUT) { 460 printf("%s: phy failed to come ready\n", 461 sc_if->sk_dev.dv_xname); 462 return; 463 } 464 465 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 466 for (i = 0; i < SK_TIMEOUT; i++) { 467 DELAY(1); 468 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 469 break; 470 } 471 472 if (i == SK_TIMEOUT) 473 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 474 } 475 476 void 477 sk_xmac_miibus_statchg(struct device *dev) 478 { 479 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 480 struct mii_data *mii = &sc_if->sk_mii; 481 482 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 483 484 /* 485 * If this is a GMII PHY, manually set the XMAC's 486 * duplex mode accordingly. 487 */ 488 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 489 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 490 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 491 } else { 492 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 493 } 494 } 495 } 496 497 int 498 sk_marv_miibus_readreg(dev, phy, reg) 499 struct device *dev; 500 int phy, reg; 501 { 502 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 503 u_int16_t val; 504 int i; 505 506 if (phy != 0 || 507 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 508 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 509 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 510 phy, reg)); 511 return(0); 512 } 513 514 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 515 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 516 517 for (i = 0; i < SK_TIMEOUT; i++) { 518 DELAY(1); 519 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 520 if (val & YU_SMICR_READ_VALID) 521 break; 522 } 523 524 if (i == SK_TIMEOUT) { 525 printf("%s: phy failed to come ready\n", 526 sc_if->sk_dev.dv_xname); 527 return 0; 528 } 529 530 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 531 SK_TIMEOUT)); 532 533 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 534 535 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 536 phy, reg, val)); 537 538 return val; 539 } 540 541 void 542 sk_marv_miibus_writereg(dev, phy, reg, val) 543 struct device *dev; 544 int phy, reg, val; 545 { 546 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 547 int i; 548 549 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 550 phy, reg, val)); 551 552 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 553 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 554 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 555 556 for (i = 0; i < SK_TIMEOUT; i++) { 557 DELAY(1); 558 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 559 break; 560 } 561 } 562 563 void 564 sk_marv_miibus_statchg(dev) 565 struct device *dev; 566 { 567 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 568 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 569 } 570 571 #define SK_HASH_BITS 6 572 573 u_int32_t 574 sk_xmac_hash(caddr_t addr) 575 { 576 u_int32_t crc; 577 578 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 579 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 580 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 581 return (crc); 582 } 583 584 u_int32_t 585 sk_yukon_hash(caddr_t addr) 586 { 587 u_int32_t crc; 588 589 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 590 crc &= ((1 << SK_HASH_BITS) - 1); 591 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 592 return (crc); 593 } 594 595 void 596 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 597 { 598 int base = XM_RXFILT_ENTRY(slot); 599 600 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 601 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 602 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 603 } 604 605 void 606 sk_setmulti(struct sk_if_softc *sc_if) 607 { 608 struct sk_softc *sc = sc_if->sk_softc; 609 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 610 u_int32_t hashes[2] = { 0, 0 }; 611 int h = 0, i; 612 struct ethercom *ec = &sc_if->sk_ethercom; 613 struct ether_multi *enm; 614 struct ether_multistep step; 615 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 616 617 /* First, zot all the existing filters. */ 618 switch(sc->sk_type) { 619 case SK_GENESIS: 620 for (i = 1; i < XM_RXFILT_MAX; i++) 621 sk_setfilt(sc_if, (caddr_t)&dummy, i); 622 623 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 624 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 625 break; 626 case SK_YUKON: 627 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 628 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 629 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 630 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 631 break; 632 } 633 634 /* Now program new ones. */ 635 allmulti: 636 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 637 hashes[0] = 0xFFFFFFFF; 638 hashes[1] = 0xFFFFFFFF; 639 } else { 640 i = 1; 641 /* First find the tail of the list. */ 642 ETHER_FIRST_MULTI(step, ec, enm); 643 while (enm != NULL) { 644 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 645 ETHER_ADDR_LEN)) { 646 ifp->if_flags |= IFF_ALLMULTI; 647 goto allmulti; 648 } 649 DPRINTFN(2,("multicast address %s\n", 650 ether_sprintf(enm->enm_addrlo))); 651 /* 652 * Program the first XM_RXFILT_MAX multicast groups 653 * into the perfect filter. For all others, 654 * use the hash table. 655 */ 656 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 657 sk_setfilt(sc_if, enm->enm_addrlo, i); 658 i++; 659 } 660 else { 661 switch (sc->sk_type) { 662 case SK_GENESIS: 663 h = sk_xmac_hash(enm->enm_addrlo); 664 break; 665 case SK_YUKON: 666 h = sk_yukon_hash(enm->enm_addrlo); 667 break; 668 } 669 if (h < 32) 670 hashes[0] |= (1 << h); 671 else 672 hashes[1] |= (1 << (h - 32)); 673 } 674 675 ETHER_NEXT_MULTI(step, enm); 676 } 677 } 678 679 switch(sc->sk_type) { 680 case SK_GENESIS: 681 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 682 XM_MODE_RX_USE_PERFECT); 683 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 684 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 685 break; 686 case SK_YUKON: 687 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 688 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 689 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 690 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 691 break; 692 } 693 } 694 695 int 696 sk_init_rx_ring(struct sk_if_softc *sc_if) 697 { 698 struct sk_chain_data *cd = &sc_if->sk_cdata; 699 struct sk_ring_data *rd = sc_if->sk_rdata; 700 int i; 701 702 bzero((char *)rd->sk_rx_ring, 703 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 704 705 for (i = 0; i < SK_RX_RING_CNT; i++) { 706 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 707 if (i == (SK_RX_RING_CNT - 1)) { 708 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 709 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 710 } else { 711 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 712 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 713 } 714 } 715 716 for (i = 0; i < SK_RX_RING_CNT; i++) { 717 if (sk_newbuf(sc_if, i, NULL, NULL) == ENOBUFS) { 718 printf("%s: failed alloc of %dth mbuf\n", 719 sc_if->sk_dev.dv_xname, i); 720 return(ENOBUFS); 721 } 722 } 723 sc_if->sk_cdata.sk_rx_prod = 0; 724 sc_if->sk_cdata.sk_rx_cons = 0; 725 726 return(0); 727 } 728 729 int 730 sk_init_tx_ring(struct sk_if_softc *sc_if) 731 { 732 struct sk_chain_data *cd = &sc_if->sk_cdata; 733 struct sk_ring_data *rd = sc_if->sk_rdata; 734 int i; 735 736 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 737 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 738 739 for (i = 0; i < SK_TX_RING_CNT; i++) { 740 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 741 if (i == (SK_TX_RING_CNT - 1)) { 742 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 743 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 744 } else { 745 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 746 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 747 } 748 } 749 750 sc_if->sk_cdata.sk_tx_prod = 0; 751 sc_if->sk_cdata.sk_tx_cons = 0; 752 sc_if->sk_cdata.sk_tx_cnt = 0; 753 754 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 755 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 756 757 return (0); 758 } 759 760 int 761 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 762 bus_dmamap_t dmamap) 763 { 764 struct sk_softc *sc = sc_if->sk_softc; 765 struct mbuf *m_new = NULL; 766 struct sk_chain *c; 767 struct sk_rx_desc *r; 768 769 if (dmamap == NULL) { 770 /* if (m) panic() */ 771 772 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES, 773 0, BUS_DMA_NOWAIT, &dmamap)) { 774 printf("%s: can't create recv map\n", 775 sc_if->sk_dev.dv_xname); 776 return(ENOMEM); 777 } 778 } else if (m == NULL) 779 bus_dmamap_unload(sc->sc_dmatag, dmamap); 780 781 sc_if->sk_cdata.sk_rx_map[i] = dmamap; 782 783 if (m == NULL) { 784 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 785 if (m_new == NULL) { 786 printf("%s: no memory for rx list -- " 787 "packet dropped!\n", sc_if->sk_dev.dv_xname); 788 return(ENOBUFS); 789 } 790 791 /* Allocate the jumbo buffer */ 792 MCLGET(m_new, M_DONTWAIT); 793 if (!(m_new->m_flags & M_EXT)) { 794 m_freem(m_new); 795 return (ENOBUFS); 796 } 797 798 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 799 800 m_adj(m_new, ETHER_ALIGN); 801 802 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new, 803 BUS_DMA_NOWAIT)) 804 return(ENOBUFS); 805 } else { 806 /* 807 * We're re-using a previously allocated mbuf; 808 * be sure to re-init pointers and lengths to 809 * default values. 810 */ 811 m_new = m; 812 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 813 m_adj(m_new, ETHER_ALIGN); 814 m_new->m_data = m_new->m_ext.ext_buf; 815 } 816 817 c = &sc_if->sk_cdata.sk_rx_chain[i]; 818 r = c->sk_desc; 819 c->sk_mbuf = m_new; 820 r->sk_data_lo = dmamap->dm_segs[0].ds_addr; 821 r->sk_ctl = dmamap->dm_segs[0].ds_len | SK_RXSTAT; 822 823 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 824 825 return(0); 826 } 827 828 /* 829 * Set media options. 830 */ 831 int 832 sk_ifmedia_upd(struct ifnet *ifp) 833 { 834 struct sk_if_softc *sc_if = ifp->if_softc; 835 836 (void) sk_init(ifp); 837 mii_mediachg(&sc_if->sk_mii); 838 return(0); 839 } 840 841 /* 842 * Report current media status. 843 */ 844 void 845 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 846 { 847 struct sk_if_softc *sc_if = ifp->if_softc; 848 849 mii_pollstat(&sc_if->sk_mii); 850 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 851 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 852 } 853 854 int 855 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 856 { 857 struct sk_if_softc *sc_if = ifp->if_softc; 858 struct sk_softc *sc = sc_if->sk_softc; 859 struct ifreq *ifr = (struct ifreq *) data; 860 /* struct ifaddr *ifa = (struct ifaddr *) data; */ 861 struct mii_data *mii; 862 int s, error = 0; 863 864 /* DPRINTFN(2, ("sk_ioctl\n")); */ 865 866 s = splnet(); 867 868 switch(command) { 869 870 case SIOCSIFFLAGS: 871 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 872 if (ifp->if_flags & IFF_UP) { 873 if (ifp->if_flags & IFF_RUNNING && 874 ifp->if_flags & IFF_PROMISC && 875 !(sc_if->sk_if_flags & IFF_PROMISC)) { 876 switch(sc->sk_type) { 877 case SK_GENESIS: 878 SK_XM_SETBIT_4(sc_if, XM_MODE, 879 XM_MODE_RX_PROMISC); 880 break; 881 case SK_YUKON: 882 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 883 YU_RCR_UFLEN | YU_RCR_MUFLEN); 884 break; 885 } 886 sk_setmulti(sc_if); 887 } else if (ifp->if_flags & IFF_RUNNING && 888 !(ifp->if_flags & IFF_PROMISC) && 889 sc_if->sk_if_flags & IFF_PROMISC) { 890 switch(sc->sk_type) { 891 case SK_GENESIS: 892 SK_XM_CLRBIT_4(sc_if, XM_MODE, 893 XM_MODE_RX_PROMISC); 894 break; 895 case SK_YUKON: 896 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 897 YU_RCR_UFLEN | YU_RCR_MUFLEN); 898 break; 899 } 900 901 sk_setmulti(sc_if); 902 } else 903 (void) sk_init(ifp); 904 } else { 905 if (ifp->if_flags & IFF_RUNNING) 906 sk_stop(ifp,0); 907 } 908 sc_if->sk_if_flags = ifp->if_flags; 909 error = 0; 910 break; 911 912 case SIOCGIFMEDIA: 913 case SIOCSIFMEDIA: 914 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 915 mii = &sc_if->sk_mii; 916 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 917 break; 918 default: 919 DPRINTFN(2, ("sk_ioctl ETHER\n")); 920 error = ether_ioctl(ifp, command, data); 921 922 if ( error == ENETRESET) { 923 sk_setmulti(sc_if); 924 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 925 error = 0; 926 } else if ( error ) { 927 splx(s); 928 return error; 929 } 930 break; 931 } 932 933 splx(s); 934 return(error); 935 } 936 937 /* 938 * Lookup: Check the PCI vendor and device, and return a pointer to 939 * The structure if the IDs match against our list. 940 */ 941 942 static const struct sk_product * 943 sk_lookup(const struct pci_attach_args *pa) 944 { 945 const struct sk_product *psk; 946 947 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 948 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 949 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 950 return (psk); 951 } 952 return (NULL); 953 } 954 955 /* 956 * Probe for a SysKonnect GEnesis chip. 957 */ 958 959 int 960 skc_probe(struct device *parent, struct cfdata *match, void *aux) 961 { 962 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 963 const struct sk_product *psk; 964 965 if ((psk = sk_lookup(pa))) { 966 return(1); 967 } 968 return(0); 969 } 970 971 /* 972 * Force the GEnesis into reset, then bring it out of reset. 973 */ 974 void sk_reset(struct sk_softc *sc) 975 { 976 DPRINTFN(2, ("sk_reset\n")); 977 978 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 979 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 980 if (sc->sk_type == SK_YUKON) 981 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 982 983 DELAY(1000); 984 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 985 DELAY(2); 986 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 987 if (sc->sk_type == SK_YUKON) 988 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 989 990 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 991 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 992 CSR_READ_2(sc, SK_LINK_CTRL))); 993 994 if (sc->sk_type == SK_GENESIS) { 995 /* Configure packet arbiter */ 996 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 997 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 998 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 999 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1000 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1001 } 1002 1003 /* Enable RAM interface */ 1004 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1005 1006 /* 1007 * Configure interrupt moderation. The moderation timer 1008 * defers interrupts specified in the interrupt moderation 1009 * timer mask based on the timeout specified in the interrupt 1010 * moderation timer init register. Each bit in the timer 1011 * register represents 18.825ns, so to specify a timeout in 1012 * microseconds, we have to multiply by 54. 1013 */ 1014 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1015 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1016 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1017 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1018 } 1019 1020 int 1021 sk_probe(struct device *parent, struct cfdata *match, void *aux) 1022 { 1023 struct skc_attach_args *sa = aux; 1024 1025 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1026 return(0); 1027 1028 return (1); 1029 } 1030 1031 /* 1032 * Each XMAC chip is attached as a separate logical IP interface. 1033 * Single port cards will have only one logical interface of course. 1034 */ 1035 void 1036 sk_attach(struct device *parent, struct device *self, void *aux) 1037 { 1038 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1039 struct sk_softc *sc = (struct sk_softc *)parent; 1040 struct skc_attach_args *sa = aux; 1041 struct sk_txmap_entry *entry; 1042 struct ifnet *ifp; 1043 bus_dma_segment_t seg; 1044 bus_dmamap_t dmamap; 1045 caddr_t kva; 1046 int i, rseg; 1047 1048 sc_if->sk_port = sa->skc_port; 1049 sc_if->sk_softc = sc; 1050 sc->sk_if[sa->skc_port] = sc_if; 1051 1052 if (sa->skc_port == SK_PORT_A) 1053 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1054 if (sa->skc_port == SK_PORT_B) 1055 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1056 1057 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1058 1059 /* 1060 * Get station address for this interface. Note that 1061 * dual port cards actually come with three station 1062 * addresses: one for each port, plus an extra. The 1063 * extra one is used by the SysKonnect driver software 1064 * as a 'virtual' station address for when both ports 1065 * are operating in failover mode. Currently we don't 1066 * use this extra address. 1067 */ 1068 for (i = 0; i < ETHER_ADDR_LEN; i++) 1069 sc_if->sk_enaddr[i] = 1070 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1071 1072 1073 aprint_normal(": Ethernet address %s\n", 1074 ether_sprintf(sc_if->sk_enaddr)); 1075 1076 /* 1077 * Set up RAM buffer addresses. The NIC will have a certain 1078 * amount of SRAM on it, somewhere between 512K and 2MB. We 1079 * need to divide this up a) between the transmitter and 1080 * receiver and b) between the two XMACs, if this is a 1081 * dual port NIC. Our algotithm is to divide up the memory 1082 * evenly so that everyone gets a fair share. 1083 */ 1084 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1085 u_int32_t chunk, val; 1086 1087 chunk = sc->sk_ramsize / 2; 1088 val = sc->sk_rboff / sizeof(u_int64_t); 1089 sc_if->sk_rx_ramstart = val; 1090 val += (chunk / sizeof(u_int64_t)); 1091 sc_if->sk_rx_ramend = val - 1; 1092 sc_if->sk_tx_ramstart = val; 1093 val += (chunk / sizeof(u_int64_t)); 1094 sc_if->sk_tx_ramend = val - 1; 1095 } else { 1096 u_int32_t chunk, val; 1097 1098 chunk = sc->sk_ramsize / 4; 1099 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1100 sizeof(u_int64_t); 1101 sc_if->sk_rx_ramstart = val; 1102 val += (chunk / sizeof(u_int64_t)); 1103 sc_if->sk_rx_ramend = val - 1; 1104 sc_if->sk_tx_ramstart = val; 1105 val += (chunk / sizeof(u_int64_t)); 1106 sc_if->sk_tx_ramend = val - 1; 1107 } 1108 1109 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1110 " tx_ramstart=%#x tx_ramend=%#x\n", 1111 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1112 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1113 1114 /* Read and save PHY type and set PHY address */ 1115 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1116 switch (sc_if->sk_phytype) { 1117 case SK_PHYTYPE_XMAC: 1118 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1119 break; 1120 case SK_PHYTYPE_BCOM: 1121 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1122 break; 1123 case SK_PHYTYPE_MARV_COPPER: 1124 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1125 break; 1126 default: 1127 aprint_error("%s: unsupported PHY type: %d\n", 1128 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1129 return; 1130 } 1131 1132 /* Allocate the descriptor queues. */ 1133 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1134 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1135 aprint_error("%s: can't alloc rx buffers\n", 1136 sc->sk_dev.dv_xname); 1137 goto fail; 1138 } 1139 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1140 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1141 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1142 sc_if->sk_dev.dv_xname, 1143 (u_long) sizeof(struct sk_ring_data)); 1144 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1145 goto fail; 1146 } 1147 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1148 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1149 &sc_if->sk_ring_map)) { 1150 aprint_error("%s: can't create dma map\n", 1151 sc_if->sk_dev.dv_xname); 1152 bus_dmamem_unmap(sc->sc_dmatag, kva, 1153 sizeof(struct sk_ring_data)); 1154 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1155 goto fail; 1156 } 1157 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1158 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1159 aprint_error("%s: can't load dma map\n", 1160 sc_if->sk_dev.dv_xname); 1161 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1162 bus_dmamem_unmap(sc->sc_dmatag, kva, 1163 sizeof(struct sk_ring_data)); 1164 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1165 goto fail; 1166 } 1167 1168 for (i = 0; i < SK_RX_RING_CNT; i++) 1169 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1170 1171 SLIST_INIT(&sc_if->sk_txmap_listhead); 1172 for (i = 0; i < SK_TX_RING_CNT; i++) { 1173 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1174 1175 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, SK_NTXSEG, 1176 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap)) { 1177 aprint_error("%s: Can't create TX dmamap\n", 1178 sc_if->sk_dev.dv_xname); 1179 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1180 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1181 bus_dmamem_unmap(sc->sc_dmatag, kva, 1182 sizeof(struct sk_ring_data)); 1183 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1184 goto fail; 1185 } 1186 1187 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1188 if (!entry) { 1189 aprint_error("%s: Can't alloc txmap entry\n", 1190 sc_if->sk_dev.dv_xname); 1191 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1192 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1193 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1194 bus_dmamem_unmap(sc->sc_dmatag, kva, 1195 sizeof(struct sk_ring_data)); 1196 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1197 goto fail; 1198 } 1199 entry->dmamap = dmamap; 1200 SLIST_INSERT_HEAD(&sc_if->sk_txmap_listhead, entry, link); 1201 } 1202 1203 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1204 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1205 1206 /* XXX TLS It's not clear what's wrong with the Jumbo MTU 1207 XXX TLS support in this driver, so we don't enable it. */ 1208 1209 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1210 1211 ifp = &sc_if->sk_ethercom.ec_if; 1212 ifp->if_softc = sc_if; 1213 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1214 ifp->if_ioctl = sk_ioctl; 1215 ifp->if_start = sk_start; 1216 ifp->if_stop = sk_stop; 1217 ifp->if_init = sk_init; 1218 ifp->if_watchdog = sk_watchdog; 1219 ifp->if_capabilities = 0; 1220 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1221 IFQ_SET_READY(&ifp->if_snd); 1222 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1223 1224 /* 1225 * Do miibus setup. 1226 */ 1227 switch (sc->sk_type) { 1228 case SK_GENESIS: 1229 sk_init_xmac(sc_if); 1230 break; 1231 case SK_YUKON: 1232 sk_init_yukon(sc_if); 1233 break; 1234 default: 1235 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1236 sc->sk_type); 1237 } 1238 1239 DPRINTFN(2, ("sk_attach: 1\n")); 1240 1241 sc_if->sk_mii.mii_ifp = ifp; 1242 switch (sc->sk_type) { 1243 case SK_GENESIS: 1244 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1245 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1246 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1247 break; 1248 case SK_YUKON: 1249 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1250 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1251 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1252 break; 1253 } 1254 1255 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1256 sk_ifmedia_upd, sk_ifmedia_sts); 1257 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1258 MII_OFFSET_ANY, 0); 1259 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1260 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1261 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1262 0, NULL); 1263 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1264 } 1265 else 1266 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1267 1268 callout_init(&sc_if->sk_tick_ch); 1269 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1270 1271 DPRINTFN(2, ("sk_attach: 1\n")); 1272 1273 /* 1274 * Call MI attach routines. 1275 */ 1276 if_attach(ifp); 1277 1278 ether_ifattach(ifp, sc_if->sk_enaddr); 1279 1280 #if NRND > 0 1281 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1282 RND_TYPE_NET, 0); 1283 #endif 1284 1285 DPRINTFN(2, ("sk_attach: end\n")); 1286 1287 return; 1288 1289 fail: 1290 sc->sk_if[sa->skc_port] = NULL; 1291 } 1292 1293 int 1294 skcprint(void *aux, const char *pnp) 1295 { 1296 struct skc_attach_args *sa = aux; 1297 1298 if (pnp) 1299 aprint_normal("sk port %c at %s", 1300 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1301 else 1302 aprint_normal(" port %c", 1303 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1304 return (UNCONF); 1305 } 1306 1307 /* 1308 * Attach the interface. Allocate softc structures, do ifmedia 1309 * setup and ethernet/BPF attach. 1310 */ 1311 void 1312 skc_attach(struct device *parent, struct device *self, void *aux) 1313 { 1314 struct sk_softc *sc = (struct sk_softc *)self; 1315 struct pci_attach_args *pa = aux; 1316 struct skc_attach_args skca; 1317 pci_chipset_tag_t pc = pa->pa_pc; 1318 pcireg_t memtype; 1319 pci_intr_handle_t ih; 1320 const char *intrstr = NULL; 1321 bus_addr_t iobase; 1322 bus_size_t iosize; 1323 int s; 1324 u_int32_t command; 1325 1326 DPRINTFN(2, ("begin skc_attach\n")); 1327 1328 s = splnet(); 1329 1330 /* 1331 * Handle power management nonsense. 1332 */ 1333 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1334 1335 if (command == 0x01) { 1336 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1337 if (command & SK_PSTATE_MASK) { 1338 u_int32_t iobase, membase, irq; 1339 1340 /* Save important PCI config data. */ 1341 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1342 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1343 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1344 1345 /* Reset the power state. */ 1346 aprint_normal("%s chip is in D%d power mode " 1347 "-- setting to D0\n", sc->sk_dev.dv_xname, 1348 command & SK_PSTATE_MASK); 1349 command &= 0xFFFFFFFC; 1350 pci_conf_write(pc, pa->pa_tag, 1351 SK_PCI_PWRMGMTCTRL, command); 1352 1353 /* Restore PCI config data. */ 1354 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1355 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1356 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1357 } 1358 } 1359 1360 /* 1361 * Map control/status registers. 1362 */ 1363 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1364 command |= PCI_COMMAND_IO_ENABLE | 1365 PCI_COMMAND_MEM_ENABLE | 1366 PCI_COMMAND_MASTER_ENABLE; 1367 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1368 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1369 1370 switch (PCI_PRODUCT(pa->pa_id)) { 1371 case PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE: 1372 sc->sk_type = SK_GENESIS; 1373 break; 1374 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1375 case PCI_PRODUCT_3COM_3C940: 1376 case PCI_PRODUCT_DLINK_DGE530T: 1377 case PCI_PRODUCT_LINKSYS_EG1032: 1378 case PCI_PRODUCT_LINKSYS_EG1064: 1379 sc->sk_type = SK_YUKON; 1380 break; 1381 default: 1382 aprint_error(": unknown device!\n"); 1383 goto fail; 1384 } 1385 1386 #ifdef SK_USEIOSPACE 1387 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1388 aprint_error(": failed to enable I/O ports!\n"); 1389 goto fail; 1390 } 1391 /* 1392 * Map control/status registers. 1393 */ 1394 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1395 &iobase, &iosize)) { 1396 aprint_error(": can't find i/o space\n"); 1397 goto fail; 1398 } 1399 #else 1400 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1401 aprint_error(": failed to enable memory mapping!\n"); 1402 goto fail; 1403 } 1404 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1405 switch (memtype) { 1406 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1407 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1408 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1409 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1410 &iobase, &iosize) == 0) 1411 break; 1412 default: 1413 aprint_error("%s: can't find mem space\n", 1414 sc->sk_dev.dv_xname); 1415 return; 1416 } 1417 1418 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1419 #endif 1420 sc->sc_dmatag = pa->pa_dmat; 1421 1422 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1423 1424 /* Allocate interrupt */ 1425 if (pci_intr_map(pa, &ih)) { 1426 aprint_error(": couldn't map interrupt\n"); 1427 goto fail; 1428 } 1429 1430 intrstr = pci_intr_string(pc, ih); 1431 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1432 if (sc->sk_intrhand == NULL) { 1433 aprint_error(": couldn't establish interrupt"); 1434 if (intrstr != NULL) 1435 aprint_normal(" at %s", intrstr); 1436 goto fail; 1437 } 1438 aprint_normal(": %s\n", intrstr); 1439 1440 /* Reset the adapter. */ 1441 sk_reset(sc); 1442 1443 /* Read and save vital product data from EEPROM. */ 1444 sk_vpd_read(sc); 1445 1446 if (sc->sk_type == SK_GENESIS) { 1447 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1448 /* Read and save RAM size and RAMbuffer offset */ 1449 switch(val) { 1450 case SK_RAMSIZE_512K_64: 1451 sc->sk_ramsize = 0x80000; 1452 sc->sk_rboff = SK_RBOFF_0; 1453 break; 1454 case SK_RAMSIZE_1024K_64: 1455 sc->sk_ramsize = 0x100000; 1456 sc->sk_rboff = SK_RBOFF_80000; 1457 break; 1458 case SK_RAMSIZE_1024K_128: 1459 sc->sk_ramsize = 0x100000; 1460 sc->sk_rboff = SK_RBOFF_0; 1461 break; 1462 case SK_RAMSIZE_2048K_128: 1463 sc->sk_ramsize = 0x200000; 1464 sc->sk_rboff = SK_RBOFF_0; 1465 break; 1466 default: 1467 aprint_error("%s: unknown ram size: %d\n", 1468 sc->sk_dev.dv_xname, val); 1469 goto fail; 1470 break; 1471 } 1472 1473 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1474 sc->sk_ramsize, sc->sk_ramsize / 1024, 1475 sc->sk_rboff)); 1476 } else { 1477 sc->sk_ramsize = 0x20000; 1478 sc->sk_rboff = SK_RBOFF_0; 1479 1480 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1481 sc->sk_ramsize / 1024, sc->sk_ramsize, 1482 sc->sk_rboff)); 1483 } 1484 1485 /* Read and save physical media type */ 1486 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1487 case SK_PMD_1000BASESX: 1488 sc->sk_pmd = IFM_1000_SX; 1489 break; 1490 case SK_PMD_1000BASELX: 1491 sc->sk_pmd = IFM_1000_LX; 1492 break; 1493 case SK_PMD_1000BASECX: 1494 sc->sk_pmd = IFM_1000_CX; 1495 break; 1496 case SK_PMD_1000BASETX: 1497 sc->sk_pmd = IFM_1000_T; 1498 break; 1499 default: 1500 aprint_error("%s: unknown media type: 0x%x\n", 1501 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1502 goto fail; 1503 } 1504 1505 /* Announce the product name. */ 1506 aprint_normal("%s: %s\n", sc->sk_dev.dv_xname, sc->sk_vpd_prodname); 1507 1508 skca.skc_port = SK_PORT_A; 1509 (void)config_found(&sc->sk_dev, &skca, skcprint); 1510 1511 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1512 skca.skc_port = SK_PORT_B; 1513 (void)config_found(&sc->sk_dev, &skca, skcprint); 1514 } 1515 1516 /* Turn on the 'driver is loaded' LED. */ 1517 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1518 1519 fail: 1520 splx(s); 1521 } 1522 1523 int 1524 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1525 { 1526 struct sk_softc *sc = sc_if->sk_softc; 1527 struct sk_tx_desc *f = NULL; 1528 u_int32_t frag, cur, cnt = 0; 1529 int i; 1530 struct sk_txmap_entry *entry; 1531 bus_dmamap_t txmap; 1532 1533 DPRINTFN(3, ("sk_encap\n")); 1534 1535 entry = SLIST_FIRST(&sc_if->sk_txmap_listhead); 1536 if (entry == NULL) { 1537 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1538 return ENOBUFS; 1539 } 1540 txmap = entry->dmamap; 1541 1542 cur = frag = *txidx; 1543 1544 #ifdef SK_DEBUG 1545 if (skdebug >= 3) 1546 sk_dump_mbuf(m_head); 1547 #endif 1548 1549 /* 1550 * Start packing the mbufs in this chain into 1551 * the fragment pointers. Stop when we run out 1552 * of fragments or hit the end of the mbuf chain. 1553 */ 1554 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1555 BUS_DMA_NOWAIT)) { 1556 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1557 return(ENOBUFS); 1558 } 1559 1560 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1561 1562 /* Sync the DMA map. */ 1563 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1564 BUS_DMASYNC_PREWRITE); 1565 1566 for (i = 0; i < txmap->dm_nsegs; i++) { 1567 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1568 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1569 return(ENOBUFS); 1570 } 1571 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1572 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1573 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1574 if (cnt == 0) 1575 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1576 else 1577 f->sk_ctl |= SK_TXCTL_OWN; 1578 1579 cur = frag; 1580 SK_INC(frag, SK_TX_RING_CNT); 1581 cnt++; 1582 } 1583 1584 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1585 SLIST_REMOVE_HEAD(&sc_if->sk_txmap_listhead, link); 1586 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1587 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1588 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1589 1590 /* Sync descriptors before handing to chip */ 1591 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1592 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1593 1594 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1595 1596 /* Sync first descriptor to hand it off */ 1597 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1598 1599 sc_if->sk_cdata.sk_tx_cnt += cnt; 1600 1601 #ifdef SK_DEBUG 1602 if (skdebug >= 3) { 1603 struct sk_tx_desc *desc; 1604 u_int32_t idx; 1605 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1606 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1607 sk_dump_txdesc(desc, idx); 1608 } 1609 } 1610 #endif 1611 1612 *txidx = frag; 1613 1614 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1615 1616 return(0); 1617 } 1618 1619 void 1620 sk_start(struct ifnet *ifp) 1621 { 1622 struct sk_if_softc *sc_if = ifp->if_softc; 1623 struct sk_softc *sc = sc_if->sk_softc; 1624 struct mbuf *m_head = NULL; 1625 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1626 int pkts = 0; 1627 1628 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1629 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1630 1631 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1632 1633 IFQ_POLL(&ifp->if_snd, m_head); 1634 if (m_head == NULL) 1635 break; 1636 1637 /* 1638 * Pack the data into the transmit ring. If we 1639 * don't have room, set the OACTIVE flag and wait 1640 * for the NIC to drain the ring. 1641 */ 1642 if (sk_encap(sc_if, m_head, &idx)) { 1643 ifp->if_flags |= IFF_OACTIVE; 1644 break; 1645 } 1646 1647 /* now we are committed to transmit the packet */ 1648 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1649 pkts++; 1650 1651 /* 1652 * If there's a BPF listener, bounce a copy of this frame 1653 * to him. 1654 */ 1655 #if NBPFILTER > 0 1656 if (ifp->if_bpf) 1657 bpf_mtap(ifp->if_bpf, m_head); 1658 #endif 1659 } 1660 if (pkts == 0) 1661 return; 1662 1663 /* Transmit */ 1664 sc_if->sk_cdata.sk_tx_prod = idx; 1665 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1666 1667 /* Set a timeout in case the chip goes out to lunch. */ 1668 ifp->if_timer = 5; 1669 } 1670 1671 1672 void 1673 sk_watchdog(struct ifnet *ifp) 1674 { 1675 struct sk_if_softc *sc_if = ifp->if_softc; 1676 1677 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1678 (void) sk_init(ifp); 1679 } 1680 1681 void 1682 sk_shutdown(void * v) 1683 { 1684 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1685 struct sk_softc *sc = sc_if->sk_softc; 1686 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1687 1688 DPRINTFN(2, ("sk_shutdown\n")); 1689 sk_stop(ifp,1); 1690 1691 /* Turn off the 'driver is loaded' LED. */ 1692 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1693 1694 /* 1695 * Reset the GEnesis controller. Doing this should also 1696 * assert the resets on the attached XMAC(s). 1697 */ 1698 sk_reset(sc); 1699 } 1700 1701 void 1702 sk_rxeof(struct sk_if_softc *sc_if) 1703 { 1704 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1705 struct mbuf *m; 1706 struct sk_chain *cur_rx; 1707 struct sk_rx_desc *cur_desc; 1708 int i, cur, total_len = 0; 1709 u_int32_t rxstat; 1710 bus_dmamap_t dmamap; 1711 1712 i = sc_if->sk_cdata.sk_rx_prod; 1713 1714 DPRINTFN(3, ("sk_rxeof %d\n", i)); 1715 1716 for (;;) { 1717 cur = i; 1718 1719 /* Sync the descriptor */ 1720 SK_CDRXSYNC(sc_if, cur, 1721 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1722 1723 if (sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl & SK_RXCTL_OWN) { 1724 /* Invalidate the descriptor -- it's not ready yet */ 1725 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 1726 sc_if->sk_cdata.sk_rx_prod = i; 1727 break; 1728 } 1729 1730 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1731 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1732 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1733 1734 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1735 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1736 1737 rxstat = cur_desc->sk_xmac_rxstat; 1738 m = cur_rx->sk_mbuf; 1739 cur_rx->sk_mbuf = NULL; 1740 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1741 1742 sc_if->sk_cdata.sk_rx_map[cur] = 0; 1743 1744 SK_INC(i, SK_RX_RING_CNT); 1745 1746 if (rxstat & XM_RXSTAT_ERRFRAME) { 1747 ifp->if_ierrors++; 1748 sk_newbuf(sc_if, cur, m, dmamap); 1749 continue; 1750 } 1751 1752 /* 1753 * Try to allocate a new jumbo buffer. If that 1754 * fails, copy the packet to mbufs and put the 1755 * jumbo buffer back in the ring so it can be 1756 * re-used. If allocating mbufs fails, then we 1757 * have to drop the packet. 1758 */ 1759 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1760 struct mbuf *m0; 1761 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1762 total_len + ETHER_ALIGN, 0, ifp, NULL); 1763 sk_newbuf(sc_if, cur, m, dmamap); 1764 if (m0 == NULL) { 1765 printf("%s: no receive buffers " 1766 "available -- packet dropped!\n", 1767 sc_if->sk_dev.dv_xname); 1768 ifp->if_ierrors++; 1769 continue; 1770 } 1771 m_adj(m0, ETHER_ALIGN); 1772 m = m0; 1773 } else { 1774 m->m_pkthdr.rcvif = ifp; 1775 m->m_pkthdr.len = m->m_len = total_len; 1776 } 1777 1778 ifp->if_ipackets++; 1779 1780 #if NBPFILTER > 0 1781 if (ifp->if_bpf) 1782 bpf_mtap(ifp->if_bpf, m); 1783 #endif 1784 /* pass it on. */ 1785 (*ifp->if_input)(ifp, m); 1786 } 1787 } 1788 1789 void 1790 sk_txeof(struct sk_if_softc *sc_if) 1791 { 1792 struct sk_softc *sc = sc_if->sk_softc; 1793 struct sk_tx_desc *cur_tx = NULL; 1794 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1795 u_int32_t idx; 1796 struct sk_txmap_entry *entry; 1797 1798 DPRINTFN(3, ("sk_txeof\n")); 1799 1800 /* 1801 * Go through our tx ring and free mbufs for those 1802 * frames that have been sent. 1803 */ 1804 idx = sc_if->sk_cdata.sk_tx_cons; 1805 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1806 SK_CDTXSYNC(sc_if, idx, 1, 1807 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1808 1809 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1810 #ifdef SK_DEBUG 1811 if (skdebug >= 3) 1812 sk_dump_txdesc(cur_tx, idx); 1813 #endif 1814 if (cur_tx->sk_ctl & SK_TXCTL_OWN) { 1815 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 1816 break; 1817 } 1818 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1819 ifp->if_opackets++; 1820 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1821 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1822 1823 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1824 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1825 1826 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1827 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1828 1829 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1830 SLIST_INSERT_HEAD(&sc_if->sk_txmap_listhead, entry, 1831 link); 1832 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1833 } 1834 sc_if->sk_cdata.sk_tx_cnt--; 1835 SK_INC(idx, SK_TX_RING_CNT); 1836 } 1837 if (sc_if->sk_cdata.sk_tx_cnt == 0) 1838 ifp->if_timer = 0; 1839 1840 sc_if->sk_cdata.sk_tx_cons = idx; 1841 1842 if (cur_tx != NULL) 1843 ifp->if_flags &= ~IFF_OACTIVE; 1844 } 1845 1846 void 1847 sk_tick(void *xsc_if) 1848 { 1849 struct sk_if_softc *sc_if = xsc_if; 1850 struct mii_data *mii = &sc_if->sk_mii; 1851 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1852 int i; 1853 1854 DPRINTFN(3, ("sk_tick\n")); 1855 1856 if (!(ifp->if_flags & IFF_UP)) 1857 return; 1858 1859 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1860 sk_intr_bcom(sc_if); 1861 return; 1862 } 1863 1864 /* 1865 * According to SysKonnect, the correct way to verify that 1866 * the link has come back up is to poll bit 0 of the GPIO 1867 * register three times. This pin has the signal from the 1868 * link sync pin connected to it; if we read the same link 1869 * state 3 times in a row, we know the link is up. 1870 */ 1871 for (i = 0; i < 3; i++) { 1872 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1873 break; 1874 } 1875 1876 if (i != 3) { 1877 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1878 return; 1879 } 1880 1881 /* Turn the GP0 interrupt back on. */ 1882 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1883 SK_XM_READ_2(sc_if, XM_ISR); 1884 mii_tick(mii); 1885 mii_pollstat(mii); 1886 callout_stop(&sc_if->sk_tick_ch); 1887 } 1888 1889 void 1890 sk_intr_bcom(struct sk_if_softc *sc_if) 1891 { 1892 struct mii_data *mii = &sc_if->sk_mii; 1893 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1894 int status; 1895 1896 1897 DPRINTFN(3, ("sk_intr_bcom\n")); 1898 1899 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1900 1901 /* 1902 * Read the PHY interrupt register to make sure 1903 * we clear any pending interrupts. 1904 */ 1905 status = sk_xmac_miibus_readreg((struct device *)sc_if, 1906 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1907 1908 if (!(ifp->if_flags & IFF_RUNNING)) { 1909 sk_init_xmac(sc_if); 1910 return; 1911 } 1912 1913 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1914 int lstat; 1915 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 1916 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 1917 1918 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1919 mii_mediachg(mii); 1920 /* Turn off the link LED. */ 1921 SK_IF_WRITE_1(sc_if, 0, 1922 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1923 sc_if->sk_link = 0; 1924 } else if (status & BRGPHY_ISR_LNK_CHG) { 1925 sk_xmac_miibus_writereg((struct device *)sc_if, 1926 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 1927 mii_tick(mii); 1928 sc_if->sk_link = 1; 1929 /* Turn on the link LED. */ 1930 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1931 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1932 SK_LINKLED_BLINK_OFF); 1933 mii_pollstat(mii); 1934 } else { 1935 mii_tick(mii); 1936 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 1937 } 1938 } 1939 1940 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1941 } 1942 1943 void 1944 sk_intr_xmac(struct sk_if_softc *sc_if) 1945 { 1946 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 1947 1948 DPRINTFN(3, ("sk_intr_xmac\n")); 1949 1950 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1951 if (status & XM_ISR_GP0_SET) { 1952 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1953 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1954 } 1955 1956 if (status & XM_ISR_AUTONEG_DONE) { 1957 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1958 } 1959 } 1960 1961 if (status & XM_IMR_TX_UNDERRUN) 1962 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1963 1964 if (status & XM_IMR_RX_OVERRUN) 1965 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1966 } 1967 1968 void 1969 sk_intr_yukon(sc_if) 1970 struct sk_if_softc *sc_if; 1971 { 1972 int status; 1973 1974 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1975 1976 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 1977 } 1978 1979 int 1980 sk_intr(void *xsc) 1981 { 1982 struct sk_softc *sc = xsc; 1983 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1984 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1985 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1986 u_int32_t status; 1987 int claimed = 0; 1988 1989 if (sc_if0 != NULL) 1990 ifp0 = &sc_if0->sk_ethercom.ec_if; 1991 if (sc_if1 != NULL) 1992 ifp1 = &sc_if1->sk_ethercom.ec_if; 1993 1994 for (;;) { 1995 status = CSR_READ_4(sc, SK_ISSR); 1996 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 1997 1998 if (!(status & sc->sk_intrmask)) 1999 break; 2000 2001 claimed = 1; 2002 2003 /* Handle receive interrupts first. */ 2004 if (status & SK_ISR_RX1_EOF) { 2005 sk_rxeof(sc_if0); 2006 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2007 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2008 } 2009 if (status & SK_ISR_RX2_EOF) { 2010 sk_rxeof(sc_if1); 2011 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2012 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2013 } 2014 2015 /* Then transmit interrupts. */ 2016 if (status & SK_ISR_TX1_S_EOF) { 2017 sk_txeof(sc_if0); 2018 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2019 SK_TXBMU_CLR_IRQ_EOF); 2020 } 2021 if (status & SK_ISR_TX2_S_EOF) { 2022 sk_txeof(sc_if1); 2023 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2024 SK_TXBMU_CLR_IRQ_EOF); 2025 } 2026 2027 /* Then MAC interrupts. */ 2028 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 2029 if (sc->sk_type == SK_GENESIS) 2030 sk_intr_xmac(sc_if0); 2031 else 2032 sk_intr_yukon(sc_if0); 2033 } 2034 2035 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 2036 if (sc->sk_type == SK_GENESIS) 2037 sk_intr_xmac(sc_if1); 2038 else 2039 sk_intr_yukon(sc_if1); 2040 2041 } 2042 2043 if (status & SK_ISR_EXTERNAL_REG) { 2044 if (ifp0 != NULL && 2045 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2046 sk_intr_bcom(sc_if0); 2047 2048 if (ifp1 != NULL && 2049 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2050 sk_intr_bcom(sc_if1); 2051 } 2052 } 2053 2054 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2055 2056 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2057 sk_start(ifp0); 2058 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2059 sk_start(ifp1); 2060 2061 return (claimed); 2062 } 2063 2064 void 2065 sk_init_xmac(struct sk_if_softc *sc_if) 2066 { 2067 struct sk_softc *sc = sc_if->sk_softc; 2068 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2069 static const struct sk_bcom_hack bhack[] = { 2070 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2071 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2072 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2073 { 0, 0 } }; 2074 2075 DPRINTFN(1, ("sk_init_xmac\n")); 2076 2077 /* Unreset the XMAC. */ 2078 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2079 DELAY(1000); 2080 2081 /* Reset the XMAC's internal state. */ 2082 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2083 2084 /* Save the XMAC II revision */ 2085 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2086 2087 /* 2088 * Perform additional initialization for external PHYs, 2089 * namely for the 1000baseTX cards that use the XMAC's 2090 * GMII mode. 2091 */ 2092 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2093 int i = 0; 2094 u_int32_t val; 2095 2096 /* Take PHY out of reset. */ 2097 val = sk_win_read_4(sc, SK_GPIO); 2098 if (sc_if->sk_port == SK_PORT_A) 2099 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2100 else 2101 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2102 sk_win_write_4(sc, SK_GPIO, val); 2103 2104 /* Enable GMII mode on the XMAC. */ 2105 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2106 2107 sk_xmac_miibus_writereg((struct device *)sc_if, 2108 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2109 DELAY(10000); 2110 sk_xmac_miibus_writereg((struct device *)sc_if, 2111 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2112 2113 /* 2114 * Early versions of the BCM5400 apparently have 2115 * a bug that requires them to have their reserved 2116 * registers initialized to some magic values. I don't 2117 * know what the numbers do, I'm just the messenger. 2118 */ 2119 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2120 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2121 while(bhack[i].reg) { 2122 sk_xmac_miibus_writereg((struct device *)sc_if, 2123 SK_PHYADDR_BCOM, bhack[i].reg, 2124 bhack[i].val); 2125 i++; 2126 } 2127 } 2128 } 2129 2130 /* Set station address */ 2131 SK_XM_WRITE_2(sc_if, XM_PAR0, 2132 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2133 SK_XM_WRITE_2(sc_if, XM_PAR1, 2134 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2135 SK_XM_WRITE_2(sc_if, XM_PAR2, 2136 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2137 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2138 2139 if (ifp->if_flags & IFF_PROMISC) { 2140 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2141 } else { 2142 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2143 } 2144 2145 if (ifp->if_flags & IFF_BROADCAST) { 2146 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2147 } else { 2148 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2149 } 2150 2151 /* We don't need the FCS appended to the packet. */ 2152 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2153 2154 /* We want short frames padded to 60 bytes. */ 2155 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2156 2157 /* 2158 * Enable the reception of all error frames. This is is 2159 * a necessary evil due to the design of the XMAC. The 2160 * XMAC's receive FIFO is only 8K in size, however jumbo 2161 * frames can be up to 9000 bytes in length. When bad 2162 * frame filtering is enabled, the XMAC's RX FIFO operates 2163 * in 'store and forward' mode. For this to work, the 2164 * entire frame has to fit into the FIFO, but that means 2165 * that jumbo frames larger than 8192 bytes will be 2166 * truncated. Disabling all bad frame filtering causes 2167 * the RX FIFO to operate in streaming mode, in which 2168 * case the XMAC will start transfering frames out of the 2169 * RX FIFO as soon as the FIFO threshold is reached. 2170 */ 2171 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2172 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2173 XM_MODE_RX_INRANGELEN); 2174 2175 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2176 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2177 else 2178 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2179 2180 /* 2181 * Bump up the transmit threshold. This helps hold off transmit 2182 * underruns when we're blasting traffic from both ports at once. 2183 */ 2184 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2185 2186 /* Set multicast filter */ 2187 sk_setmulti(sc_if); 2188 2189 /* Clear and enable interrupts */ 2190 SK_XM_READ_2(sc_if, XM_ISR); 2191 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2192 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2193 else 2194 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2195 2196 /* Configure MAC arbiter */ 2197 switch(sc_if->sk_xmac_rev) { 2198 case XM_XMAC_REV_B2: 2199 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2200 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2201 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2202 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2203 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2204 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2205 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2206 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2207 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2208 break; 2209 case XM_XMAC_REV_C1: 2210 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2211 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2212 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2213 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2214 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2215 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2216 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2217 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2218 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2219 break; 2220 default: 2221 break; 2222 } 2223 sk_win_write_2(sc, SK_MACARB_CTL, 2224 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2225 2226 sc_if->sk_link = 1; 2227 } 2228 2229 void sk_init_yukon(sc_if) 2230 struct sk_if_softc *sc_if; 2231 { 2232 u_int32_t /*mac, */phy; 2233 u_int16_t reg; 2234 int i; 2235 2236 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2237 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2238 2239 /* GMAC and GPHY Reset */ 2240 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2241 2242 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2243 2244 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2245 DELAY(1000); 2246 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2247 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2248 DELAY(1000); 2249 2250 2251 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2252 2253 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2254 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2255 2256 switch(sc_if->sk_softc->sk_pmd) { 2257 case IFM_1000_SX: 2258 case IFM_1000_LX: 2259 phy |= SK_GPHY_FIBER; 2260 break; 2261 2262 case IFM_1000_CX: 2263 case IFM_1000_T: 2264 phy |= SK_GPHY_COPPER; 2265 break; 2266 } 2267 2268 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2269 2270 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2271 DELAY(1000); 2272 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2273 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2274 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2275 2276 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2277 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2278 2279 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2280 2281 /* unused read of the interrupt source register */ 2282 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2283 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2284 2285 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2286 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2287 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2288 2289 /* MIB Counter Clear Mode set */ 2290 reg |= YU_PAR_MIB_CLR; 2291 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2292 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2293 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2294 2295 /* MIB Counter Clear Mode clear */ 2296 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2297 reg &= ~YU_PAR_MIB_CLR; 2298 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2299 2300 /* receive control reg */ 2301 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2302 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2303 YU_RCR_CRCR); 2304 2305 /* transmit parameter register */ 2306 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2307 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2308 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2309 2310 /* serial mode register */ 2311 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2312 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2313 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2314 2315 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2316 /* Setup Yukon's address */ 2317 for (i = 0; i < 3; i++) { 2318 /* Write Source Address 1 (unicast filter) */ 2319 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2320 sc_if->sk_enaddr[i * 2] | 2321 sc_if->sk_enaddr[i * 2 + 1] << 8); 2322 } 2323 2324 for (i = 0; i < 3; i++) { 2325 reg = sk_win_read_2(sc_if->sk_softc, 2326 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2327 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2328 } 2329 2330 /* clear all Multicast filter hash registers */ 2331 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2332 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 2333 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 2334 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 2335 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 2336 2337 /* enable interrupt mask for counter overflows */ 2338 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2339 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2340 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2341 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2342 2343 /* Configure RX MAC FIFO */ 2344 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2345 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2346 2347 /* Configure TX MAC FIFO */ 2348 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2349 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2350 2351 DPRINTFN(6, ("sk_init_yukon: end\n")); 2352 } 2353 2354 /* 2355 * Note that to properly initialize any part of the GEnesis chip, 2356 * you first have to take it out of reset mode. 2357 */ 2358 int 2359 sk_init(struct ifnet *ifp) 2360 { 2361 struct sk_if_softc *sc_if = ifp->if_softc; 2362 struct sk_softc *sc = sc_if->sk_softc; 2363 struct mii_data *mii = &sc_if->sk_mii; 2364 int s; 2365 2366 DPRINTFN(1, ("sk_init\n")); 2367 2368 s = splnet(); 2369 2370 /* Cancel pending I/O and free all RX/TX buffers. */ 2371 sk_stop(ifp,0); 2372 2373 if (sc->sk_type == SK_GENESIS) { 2374 /* Configure LINK_SYNC LED */ 2375 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2376 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2377 SK_LINKLED_LINKSYNC_ON); 2378 2379 /* Configure RX LED */ 2380 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2381 SK_RXLEDCTL_COUNTER_START); 2382 2383 /* Configure TX LED */ 2384 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2385 SK_TXLEDCTL_COUNTER_START); 2386 } 2387 2388 /* Configure I2C registers */ 2389 2390 /* Configure XMAC(s) */ 2391 switch (sc->sk_type) { 2392 case SK_GENESIS: 2393 sk_init_xmac(sc_if); 2394 break; 2395 case SK_YUKON: 2396 sk_init_yukon(sc_if); 2397 break; 2398 } 2399 mii_mediachg(mii); 2400 2401 if (sc->sk_type == SK_GENESIS) { 2402 /* Configure MAC FIFOs */ 2403 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2404 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2405 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2406 2407 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2408 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2409 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2410 } 2411 2412 /* Configure transmit arbiter(s) */ 2413 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2414 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2415 2416 /* Configure RAMbuffers */ 2417 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2418 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2419 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2420 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2421 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2422 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2423 2424 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2425 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2426 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2427 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2428 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2429 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2430 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2431 2432 /* Configure BMUs */ 2433 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2434 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2435 SK_RX_RING_ADDR(sc_if, 0)); 2436 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2437 2438 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2439 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2440 SK_TX_RING_ADDR(sc_if, 0)); 2441 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2442 2443 /* Init descriptors */ 2444 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2445 printf("%s: initialization failed: no " 2446 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2447 sk_stop(ifp,0); 2448 splx(s); 2449 return(ENOBUFS); 2450 } 2451 2452 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2453 printf("%s: initialization failed: no " 2454 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2455 sk_stop(ifp,0); 2456 splx(s); 2457 return(ENOBUFS); 2458 } 2459 2460 /* Configure interrupt handling */ 2461 CSR_READ_4(sc, SK_ISSR); 2462 if (sc_if->sk_port == SK_PORT_A) 2463 sc->sk_intrmask |= SK_INTRS1; 2464 else 2465 sc->sk_intrmask |= SK_INTRS2; 2466 2467 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2468 2469 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2470 2471 /* Start BMUs. */ 2472 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2473 2474 if (sc->sk_type == SK_GENESIS) { 2475 /* Enable XMACs TX and RX state machines */ 2476 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2477 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2478 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2479 } 2480 2481 if (sc->sk_type == SK_YUKON) { 2482 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2483 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2484 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2485 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2486 } 2487 2488 2489 ifp->if_flags |= IFF_RUNNING; 2490 ifp->if_flags &= ~IFF_OACTIVE; 2491 2492 splx(s); 2493 return(0); 2494 } 2495 2496 void 2497 sk_stop(struct ifnet *ifp, int disable) 2498 { 2499 struct sk_if_softc *sc_if = ifp->if_softc; 2500 struct sk_softc *sc = sc_if->sk_softc; 2501 int i; 2502 2503 DPRINTFN(1, ("sk_stop\n")); 2504 2505 callout_stop(&sc_if->sk_tick_ch); 2506 2507 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2508 u_int32_t val; 2509 2510 /* Put PHY back into reset. */ 2511 val = sk_win_read_4(sc, SK_GPIO); 2512 if (sc_if->sk_port == SK_PORT_A) { 2513 val |= SK_GPIO_DIR0; 2514 val &= ~SK_GPIO_DAT0; 2515 } else { 2516 val |= SK_GPIO_DIR2; 2517 val &= ~SK_GPIO_DAT2; 2518 } 2519 sk_win_write_4(sc, SK_GPIO, val); 2520 } 2521 2522 /* Turn off various components of this interface. */ 2523 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2524 switch (sc->sk_type) { 2525 case SK_GENESIS: 2526 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2527 SK_TXMACCTL_XMAC_RESET); 2528 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2529 break; 2530 case SK_YUKON: 2531 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2532 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2533 break; 2534 } 2535 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2536 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2537 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2538 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2539 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2540 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2541 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2542 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2543 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2544 2545 /* Disable interrupts */ 2546 if (sc_if->sk_port == SK_PORT_A) 2547 sc->sk_intrmask &= ~SK_INTRS1; 2548 else 2549 sc->sk_intrmask &= ~SK_INTRS2; 2550 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2551 2552 SK_XM_READ_2(sc_if, XM_ISR); 2553 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2554 2555 /* Free RX and TX mbufs still in the queues. */ 2556 for (i = 0; i < SK_RX_RING_CNT; i++) { 2557 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2558 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2559 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2560 } 2561 } 2562 2563 for (i = 0; i < SK_TX_RING_CNT; i++) { 2564 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2565 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2566 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2567 } 2568 } 2569 2570 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2571 } 2572 2573 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2574 2575 /* 2576 struct cfdriver skc_cd = { 2577 0, "skc", DV_DULL 2578 }; 2579 */ 2580 2581 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2582 2583 /* 2584 struct cfdriver sk_cd = { 2585 0, "sk", DV_IFNET 2586 }; 2587 */ 2588 2589 #ifdef SK_DEBUG 2590 void 2591 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2592 { 2593 #define DESC_PRINT(X) \ 2594 if (desc->X) \ 2595 printf("txdesc[%d]." #X "=%#x\n", \ 2596 idx, desc->X); 2597 2598 DESC_PRINT(sk_ctl); 2599 DESC_PRINT(sk_next); 2600 DESC_PRINT(sk_data_lo); 2601 DESC_PRINT(sk_data_hi); 2602 DESC_PRINT(sk_xmac_txstat); 2603 DESC_PRINT(sk_rsvd0); 2604 DESC_PRINT(sk_csum_startval); 2605 DESC_PRINT(sk_csum_startpos); 2606 DESC_PRINT(sk_csum_writepos); 2607 DESC_PRINT(sk_rsvd1); 2608 #undef PRINT 2609 } 2610 2611 void 2612 sk_dump_bytes(const char *data, int len) 2613 { 2614 int c, i, j; 2615 2616 for (i = 0; i < len; i += 16) { 2617 printf("%08x ", i); 2618 c = len - i; 2619 if (c > 16) c = 16; 2620 2621 for (j = 0; j < c; j++) { 2622 printf("%02x ", data[i + j] & 0xff); 2623 if ((j & 0xf) == 7 && j > 0) 2624 printf(" "); 2625 } 2626 2627 for (; j < 16; j++) 2628 printf(" "); 2629 printf(" "); 2630 2631 for (j = 0; j < c; j++) { 2632 int ch = data[i + j] & 0xff; 2633 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2634 } 2635 2636 printf("\n"); 2637 2638 if (c < 16) 2639 break; 2640 } 2641 } 2642 2643 void 2644 sk_dump_mbuf(struct mbuf *m) 2645 { 2646 int count = m->m_pkthdr.len; 2647 2648 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2649 2650 while (count > 0 && m) { 2651 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2652 m, m->m_data, m->m_len); 2653 sk_dump_bytes(mtod(m, char *), m->m_len); 2654 2655 count -= m->m_len; 2656 m = m->m_next; 2657 } 2658 } 2659 #endif 2660
Indexes created Tue Sep 23 07:09:52 GMT 2025