if_sk.c revision 1.84
1 /* $NetBSD: if_sk.c,v 1.84 2016/12/14 22:21:13 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.84 2016/12/14 22:21:13 christos Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/sockio.h> 123 #include <sys/mbuf.h> 124 #include <sys/malloc.h> 125 #include <sys/mutex.h> 126 #include <sys/kernel.h> 127 #include <sys/socket.h> 128 #include <sys/device.h> 129 #include <sys/queue.h> 130 #include <sys/callout.h> 131 #include <sys/sysctl.h> 132 #include <sys/endian.h> 133 134 #include <net/if.h> 135 #include <net/if_dl.h> 136 #include <net/if_types.h> 137 138 #include <net/if_media.h> 139 140 #include <net/bpf.h> 141 #include <sys/rndsource.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 #include <dev/mii/brgphyreg.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 #include <dev/pci/pcidevs.h> 150 151 /* #define SK_USEIOSPACE */ 152 153 #include <dev/pci/if_skreg.h> 154 #include <dev/pci/if_skvar.h> 155 156 int skc_probe(device_t, cfdata_t, void *); 157 void skc_attach(device_t, device_t, void *aux); 158 int sk_probe(device_t, cfdata_t, void *); 159 void sk_attach(device_t, device_t, void *aux); 160 int skcprint(void *, const char *); 161 int sk_intr(void *); 162 void sk_intr_bcom(struct sk_if_softc *); 163 void sk_intr_xmac(struct sk_if_softc *); 164 void sk_intr_yukon(struct sk_if_softc *); 165 void sk_rxeof(struct sk_if_softc *); 166 void sk_txeof(struct sk_if_softc *); 167 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 168 void sk_start(struct ifnet *); 169 int sk_ioctl(struct ifnet *, u_long, void *); 170 int sk_init(struct ifnet *); 171 void sk_init_xmac(struct sk_if_softc *); 172 void sk_init_yukon(struct sk_if_softc *); 173 void sk_stop(struct ifnet *, int); 174 void sk_watchdog(struct ifnet *); 175 void sk_shutdown(void *); 176 int sk_ifmedia_upd(struct ifnet *); 177 void sk_reset(struct sk_softc *); 178 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 179 int sk_alloc_jumbo_mem(struct sk_if_softc *); 180 void sk_free_jumbo_mem(struct sk_if_softc *); 181 void *sk_jalloc(struct sk_if_softc *); 182 void sk_jfree(struct mbuf *, void *, size_t, void *); 183 int sk_init_rx_ring(struct sk_if_softc *); 184 int sk_init_tx_ring(struct sk_if_softc *); 185 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 186 void sk_vpd_read_res(struct sk_softc *, 187 struct vpd_res *, int); 188 void sk_vpd_read(struct sk_softc *); 189 190 void sk_update_int_mod(struct sk_softc *); 191 192 int sk_xmac_miibus_readreg(device_t, int, int); 193 void sk_xmac_miibus_writereg(device_t, int, int, int); 194 void sk_xmac_miibus_statchg(struct ifnet *); 195 196 int sk_marv_miibus_readreg(device_t, int, int); 197 void sk_marv_miibus_writereg(device_t, int, int, int); 198 void sk_marv_miibus_statchg(struct ifnet *); 199 200 u_int32_t sk_xmac_hash(void *); 201 u_int32_t sk_yukon_hash(void *); 202 void sk_setfilt(struct sk_if_softc *, void *, int); 203 void sk_setmulti(struct sk_if_softc *); 204 void sk_tick(void *); 205 206 static bool skc_suspend(device_t, const pmf_qual_t *); 207 static bool skc_resume(device_t, const pmf_qual_t *); 208 static bool sk_resume(device_t dv, const pmf_qual_t *); 209 210 /* #define SK_DEBUG 2 */ 211 #ifdef SK_DEBUG 212 #define DPRINTF(x) if (skdebug) printf x 213 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 214 int skdebug = SK_DEBUG; 215 216 void sk_dump_txdesc(struct sk_tx_desc *, int); 217 void sk_dump_mbuf(struct mbuf *); 218 void sk_dump_bytes(const char *, int); 219 #else 220 #define DPRINTF(x) 221 #define DPRINTFN(n,x) 222 #endif 223 224 static int sk_sysctl_handler(SYSCTLFN_PROTO); 225 static int sk_root_num; 226 227 /* supported device vendors */ 228 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 229 static const struct sk_product { 230 pci_vendor_id_t sk_vendor; 231 pci_product_id_t sk_product; 232 } sk_products[] = { 233 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 234 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 235 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 236 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 237 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 238 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 239 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 240 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 241 { 0, 0, } 242 }; 243 244 #define SK_LINKSYS_EG1032_SUBID 0x00151737 245 246 static inline u_int32_t 247 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 248 { 249 #ifdef SK_USEIOSPACE 250 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 251 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 252 #else 253 return CSR_READ_4(sc, reg); 254 #endif 255 } 256 257 static inline u_int16_t 258 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 259 { 260 #ifdef SK_USEIOSPACE 261 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 262 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 263 #else 264 return CSR_READ_2(sc, reg); 265 #endif 266 } 267 268 static inline u_int8_t 269 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 270 { 271 #ifdef SK_USEIOSPACE 272 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 273 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 274 #else 275 return CSR_READ_1(sc, reg); 276 #endif 277 } 278 279 static inline void 280 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 281 { 282 #ifdef SK_USEIOSPACE 283 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 284 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 285 #else 286 CSR_WRITE_4(sc, reg, x); 287 #endif 288 } 289 290 static inline void 291 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 292 { 293 #ifdef SK_USEIOSPACE 294 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 295 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 296 #else 297 CSR_WRITE_2(sc, reg, x); 298 #endif 299 } 300 301 static inline void 302 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 303 { 304 #ifdef SK_USEIOSPACE 305 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 306 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 307 #else 308 CSR_WRITE_1(sc, reg, x); 309 #endif 310 } 311 312 /* 313 * The VPD EEPROM contains Vital Product Data, as suggested in 314 * the PCI 2.1 specification. The VPD data is separared into areas 315 * denoted by resource IDs. The SysKonnect VPD contains an ID string 316 * resource (the name of the adapter), a read-only area resource 317 * containing various key/data fields and a read/write area which 318 * can be used to store asset management information or log messages. 319 * We read the ID string and read-only into buffers attached to 320 * the controller softc structure for later use. At the moment, 321 * we only use the ID string during sk_attach(). 322 */ 323 u_int8_t 324 sk_vpd_readbyte(struct sk_softc *sc, int addr) 325 { 326 int i; 327 328 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 329 for (i = 0; i < SK_TIMEOUT; i++) { 330 DELAY(1); 331 if (sk_win_read_2(sc, 332 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 333 break; 334 } 335 336 if (i == SK_TIMEOUT) 337 return 0; 338 339 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 340 } 341 342 void 343 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 344 { 345 int i; 346 u_int8_t *ptr; 347 348 ptr = (u_int8_t *)res; 349 for (i = 0; i < sizeof(struct vpd_res); i++) 350 ptr[i] = sk_vpd_readbyte(sc, i + addr); 351 } 352 353 void 354 sk_vpd_read(struct sk_softc *sc) 355 { 356 int pos = 0, i; 357 struct vpd_res res; 358 359 if (sc->sk_vpd_prodname != NULL) 360 free(sc->sk_vpd_prodname, M_DEVBUF); 361 if (sc->sk_vpd_readonly != NULL) 362 free(sc->sk_vpd_readonly, M_DEVBUF); 363 sc->sk_vpd_prodname = NULL; 364 sc->sk_vpd_readonly = NULL; 365 366 sk_vpd_read_res(sc, &res, pos); 367 368 if (res.vr_id != VPD_RES_ID) { 369 aprint_error_dev(sc->sk_dev, 370 "bad VPD resource id: expected %x got %x\n", 371 VPD_RES_ID, res.vr_id); 372 return; 373 } 374 375 pos += sizeof(res); 376 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 377 if (sc->sk_vpd_prodname == NULL) 378 panic("sk_vpd_read"); 379 for (i = 0; i < res.vr_len; i++) 380 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 381 sc->sk_vpd_prodname[i] = '\0'; 382 pos += i; 383 384 sk_vpd_read_res(sc, &res, pos); 385 386 if (res.vr_id != VPD_RES_READ) { 387 aprint_error_dev(sc->sk_dev, 388 "bad VPD resource id: expected %x got %x\n", 389 VPD_RES_READ, res.vr_id); 390 return; 391 } 392 393 pos += sizeof(res); 394 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 395 if (sc->sk_vpd_readonly == NULL) 396 panic("sk_vpd_read"); 397 for (i = 0; i < res.vr_len ; i++) 398 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 399 } 400 401 int 402 sk_xmac_miibus_readreg(device_t dev, int phy, int reg) 403 { 404 struct sk_if_softc *sc_if = device_private(dev); 405 int i; 406 407 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 408 409 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 410 return 0; 411 412 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 413 SK_XM_READ_2(sc_if, XM_PHY_DATA); 414 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 415 for (i = 0; i < SK_TIMEOUT; i++) { 416 DELAY(1); 417 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 418 XM_MMUCMD_PHYDATARDY) 419 break; 420 } 421 422 if (i == SK_TIMEOUT) { 423 aprint_error_dev(sc_if->sk_dev, 424 "phy failed to come ready\n"); 425 return 0; 426 } 427 } 428 DELAY(1); 429 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 430 } 431 432 void 433 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, int val) 434 { 435 struct sk_if_softc *sc_if = device_private(dev); 436 int i; 437 438 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 439 440 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 441 for (i = 0; i < SK_TIMEOUT; i++) { 442 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 443 break; 444 } 445 446 if (i == SK_TIMEOUT) { 447 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 448 return; 449 } 450 451 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 452 for (i = 0; i < SK_TIMEOUT; i++) { 453 DELAY(1); 454 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 455 break; 456 } 457 458 if (i == SK_TIMEOUT) 459 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 460 } 461 462 void 463 sk_xmac_miibus_statchg(struct ifnet *ifp) 464 { 465 struct sk_if_softc *sc_if = ifp->if_softc; 466 struct mii_data *mii = &sc_if->sk_mii; 467 468 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 469 470 /* 471 * If this is a GMII PHY, manually set the XMAC's 472 * duplex mode accordingly. 473 */ 474 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 475 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 476 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 477 else 478 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 479 } 480 } 481 482 int 483 sk_marv_miibus_readreg(device_t dev, int phy, int reg) 484 { 485 struct sk_if_softc *sc_if = device_private(dev); 486 u_int16_t val; 487 int i; 488 489 if (phy != 0 || 490 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 491 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 492 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 493 phy, reg)); 494 return 0; 495 } 496 497 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 498 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 499 500 for (i = 0; i < SK_TIMEOUT; i++) { 501 DELAY(1); 502 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 503 if (val & YU_SMICR_READ_VALID) 504 break; 505 } 506 507 if (i == SK_TIMEOUT) { 508 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 509 return 0; 510 } 511 512 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 513 SK_TIMEOUT)); 514 515 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 516 517 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 518 phy, reg, val)); 519 520 return val; 521 } 522 523 void 524 sk_marv_miibus_writereg(device_t dev, int phy, int reg, int val) 525 { 526 struct sk_if_softc *sc_if = device_private(dev); 527 int i; 528 529 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 530 phy, reg, val)); 531 532 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 533 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 534 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 535 536 for (i = 0; i < SK_TIMEOUT; i++) { 537 DELAY(1); 538 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 539 break; 540 } 541 542 if (i == SK_TIMEOUT) 543 printf("%s: phy write timed out\n", 544 device_xname(sc_if->sk_dev)); 545 } 546 547 void 548 sk_marv_miibus_statchg(struct ifnet *ifp) 549 { 550 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 551 SK_YU_READ_2(((struct sk_if_softc *)ifp->if_softc), 552 YUKON_GPCR))); 553 } 554 555 #define SK_HASH_BITS 6 556 557 u_int32_t 558 sk_xmac_hash(void *addr) 559 { 560 u_int32_t crc; 561 562 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 563 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 564 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 565 return crc; 566 } 567 568 u_int32_t 569 sk_yukon_hash(void *addr) 570 { 571 u_int32_t crc; 572 573 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 574 crc &= ((1 << SK_HASH_BITS) - 1); 575 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 576 return crc; 577 } 578 579 void 580 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 581 { 582 char *addr = addrv; 583 int base = XM_RXFILT_ENTRY(slot); 584 585 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 586 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 587 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 588 } 589 590 void 591 sk_setmulti(struct sk_if_softc *sc_if) 592 { 593 struct sk_softc *sc = sc_if->sk_softc; 594 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 595 u_int32_t hashes[2] = { 0, 0 }; 596 int h = 0, i; 597 struct ethercom *ec = &sc_if->sk_ethercom; 598 struct ether_multi *enm; 599 struct ether_multistep step; 600 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 601 602 /* First, zot all the existing filters. */ 603 switch (sc->sk_type) { 604 case SK_GENESIS: 605 for (i = 1; i < XM_RXFILT_MAX; i++) 606 sk_setfilt(sc_if, (void *)&dummy, i); 607 608 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 609 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 610 break; 611 case SK_YUKON: 612 case SK_YUKON_LITE: 613 case SK_YUKON_LP: 614 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 615 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 616 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 617 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 618 break; 619 } 620 621 /* Now program new ones. */ 622 allmulti: 623 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 624 hashes[0] = 0xFFFFFFFF; 625 hashes[1] = 0xFFFFFFFF; 626 } else { 627 i = 1; 628 /* First find the tail of the list. */ 629 ETHER_FIRST_MULTI(step, ec, enm); 630 while (enm != NULL) { 631 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 632 ETHER_ADDR_LEN)) { 633 ifp->if_flags |= IFF_ALLMULTI; 634 goto allmulti; 635 } 636 DPRINTFN(2,("multicast address %s\n", 637 ether_sprintf(enm->enm_addrlo))); 638 /* 639 * Program the first XM_RXFILT_MAX multicast groups 640 * into the perfect filter. For all others, 641 * use the hash table. 642 */ 643 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 644 sk_setfilt(sc_if, enm->enm_addrlo, i); 645 i++; 646 } 647 else { 648 switch (sc->sk_type) { 649 case SK_GENESIS: 650 h = sk_xmac_hash(enm->enm_addrlo); 651 break; 652 case SK_YUKON: 653 case SK_YUKON_LITE: 654 case SK_YUKON_LP: 655 h = sk_yukon_hash(enm->enm_addrlo); 656 break; 657 } 658 if (h < 32) 659 hashes[0] |= (1 << h); 660 else 661 hashes[1] |= (1 << (h - 32)); 662 } 663 664 ETHER_NEXT_MULTI(step, enm); 665 } 666 } 667 668 switch (sc->sk_type) { 669 case SK_GENESIS: 670 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 671 XM_MODE_RX_USE_PERFECT); 672 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 673 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 674 break; 675 case SK_YUKON: 676 case SK_YUKON_LITE: 677 case SK_YUKON_LP: 678 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 679 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 680 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 681 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 682 break; 683 } 684 } 685 686 int 687 sk_init_rx_ring(struct sk_if_softc *sc_if) 688 { 689 struct sk_chain_data *cd = &sc_if->sk_cdata; 690 struct sk_ring_data *rd = sc_if->sk_rdata; 691 int i; 692 693 memset((char *)rd->sk_rx_ring, 0, 694 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 695 696 for (i = 0; i < SK_RX_RING_CNT; i++) { 697 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 698 if (i == (SK_RX_RING_CNT - 1)) { 699 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 700 rd->sk_rx_ring[i].sk_next = 701 htole32(SK_RX_RING_ADDR(sc_if, 0)); 702 } else { 703 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 704 rd->sk_rx_ring[i].sk_next = 705 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 706 } 707 } 708 709 for (i = 0; i < SK_RX_RING_CNT; i++) { 710 if (sk_newbuf(sc_if, i, NULL, 711 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 712 aprint_error_dev(sc_if->sk_dev, 713 "failed alloc of %dth mbuf\n", i); 714 return ENOBUFS; 715 } 716 } 717 sc_if->sk_cdata.sk_rx_prod = 0; 718 sc_if->sk_cdata.sk_rx_cons = 0; 719 720 return 0; 721 } 722 723 int 724 sk_init_tx_ring(struct sk_if_softc *sc_if) 725 { 726 struct sk_chain_data *cd = &sc_if->sk_cdata; 727 struct sk_ring_data *rd = sc_if->sk_rdata; 728 int i; 729 730 memset(sc_if->sk_rdata->sk_tx_ring, 0, 731 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 732 733 for (i = 0; i < SK_TX_RING_CNT; i++) { 734 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 735 if (i == (SK_TX_RING_CNT - 1)) { 736 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 737 rd->sk_tx_ring[i].sk_next = 738 htole32(SK_TX_RING_ADDR(sc_if, 0)); 739 } else { 740 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 741 rd->sk_tx_ring[i].sk_next = 742 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 743 } 744 } 745 746 sc_if->sk_cdata.sk_tx_prod = 0; 747 sc_if->sk_cdata.sk_tx_cons = 0; 748 sc_if->sk_cdata.sk_tx_cnt = 0; 749 750 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 751 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 752 753 return 0; 754 } 755 756 int 757 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 758 bus_dmamap_t dmamap) 759 { 760 struct mbuf *m_new = NULL; 761 struct sk_chain *c; 762 struct sk_rx_desc *r; 763 764 if (m == NULL) { 765 void *buf = NULL; 766 767 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 768 if (m_new == NULL) { 769 aprint_error_dev(sc_if->sk_dev, 770 "no memory for rx list -- packet dropped!\n"); 771 return ENOBUFS; 772 } 773 774 /* Allocate the jumbo buffer */ 775 buf = sk_jalloc(sc_if); 776 if (buf == NULL) { 777 m_freem(m_new); 778 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 779 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 780 return ENOBUFS; 781 } 782 783 /* Attach the buffer to the mbuf */ 784 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 785 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 786 787 } else { 788 /* 789 * We're re-using a previously allocated mbuf; 790 * be sure to re-init pointers and lengths to 791 * default values. 792 */ 793 m_new = m; 794 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 795 m_new->m_data = m_new->m_ext.ext_buf; 796 } 797 m_adj(m_new, ETHER_ALIGN); 798 799 c = &sc_if->sk_cdata.sk_rx_chain[i]; 800 r = c->sk_desc; 801 c->sk_mbuf = m_new; 802 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 803 (((vaddr_t)m_new->m_data 804 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 805 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 806 807 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 808 809 return 0; 810 } 811 812 /* 813 * Memory management for jumbo frames. 814 */ 815 816 int 817 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 818 { 819 struct sk_softc *sc = sc_if->sk_softc; 820 char *ptr, *kva; 821 bus_dma_segment_t seg; 822 int i, rseg, state, error; 823 struct sk_jpool_entry *entry; 824 825 state = error = 0; 826 827 /* Grab a big chunk o' storage. */ 828 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 829 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 830 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 831 return ENOBUFS; 832 } 833 834 state = 1; 835 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 836 BUS_DMA_NOWAIT)) { 837 aprint_error_dev(sc->sk_dev, 838 "can't map dma buffers (%d bytes)\n", 839 SK_JMEM); 840 error = ENOBUFS; 841 goto out; 842 } 843 844 state = 2; 845 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 846 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 847 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 848 error = ENOBUFS; 849 goto out; 850 } 851 852 state = 3; 853 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 854 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 855 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 856 error = ENOBUFS; 857 goto out; 858 } 859 860 state = 4; 861 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 862 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 863 864 LIST_INIT(&sc_if->sk_jfree_listhead); 865 LIST_INIT(&sc_if->sk_jinuse_listhead); 866 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 867 868 /* 869 * Now divide it up into 9K pieces and save the addresses 870 * in an array. 871 */ 872 ptr = sc_if->sk_cdata.sk_jumbo_buf; 873 for (i = 0; i < SK_JSLOTS; i++) { 874 sc_if->sk_cdata.sk_jslots[i] = ptr; 875 ptr += SK_JLEN; 876 entry = malloc(sizeof(struct sk_jpool_entry), 877 M_DEVBUF, M_NOWAIT); 878 if (entry == NULL) { 879 aprint_error_dev(sc->sk_dev, 880 "no memory for jumbo buffer queue!\n"); 881 error = ENOBUFS; 882 goto out; 883 } 884 entry->slot = i; 885 if (i) 886 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 887 entry, jpool_entries); 888 else 889 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 890 entry, jpool_entries); 891 } 892 out: 893 if (error != 0) { 894 switch (state) { 895 case 4: 896 bus_dmamap_unload(sc->sc_dmatag, 897 sc_if->sk_cdata.sk_rx_jumbo_map); 898 case 3: 899 bus_dmamap_destroy(sc->sc_dmatag, 900 sc_if->sk_cdata.sk_rx_jumbo_map); 901 case 2: 902 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 903 case 1: 904 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 905 break; 906 default: 907 break; 908 } 909 } 910 911 return error; 912 } 913 914 /* 915 * Allocate a jumbo buffer. 916 */ 917 void * 918 sk_jalloc(struct sk_if_softc *sc_if) 919 { 920 struct sk_jpool_entry *entry; 921 922 mutex_enter(&sc_if->sk_jpool_mtx); 923 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 924 925 if (entry == NULL) { 926 mutex_exit(&sc_if->sk_jpool_mtx); 927 return NULL; 928 } 929 930 LIST_REMOVE(entry, jpool_entries); 931 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 932 mutex_exit(&sc_if->sk_jpool_mtx); 933 return sc_if->sk_cdata.sk_jslots[entry->slot]; 934 } 935 936 /* 937 * Release a jumbo buffer. 938 */ 939 void 940 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 941 { 942 struct sk_jpool_entry *entry; 943 struct sk_if_softc *sc; 944 int i; 945 946 /* Extract the softc struct pointer. */ 947 sc = (struct sk_if_softc *)arg; 948 949 if (sc == NULL) 950 panic("sk_jfree: can't find softc pointer!"); 951 952 /* calculate the slot this buffer belongs to */ 953 954 i = ((vaddr_t)buf 955 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 956 957 if ((i < 0) || (i >= SK_JSLOTS)) 958 panic("sk_jfree: asked to free buffer that we don't manage!"); 959 960 mutex_enter(&sc->sk_jpool_mtx); 961 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 962 if (entry == NULL) 963 panic("sk_jfree: buffer not in use!"); 964 entry->slot = i; 965 LIST_REMOVE(entry, jpool_entries); 966 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 967 mutex_exit(&sc->sk_jpool_mtx); 968 969 if (__predict_true(m != NULL)) 970 pool_cache_put(mb_cache, m); 971 } 972 973 /* 974 * Set media options. 975 */ 976 int 977 sk_ifmedia_upd(struct ifnet *ifp) 978 { 979 struct sk_if_softc *sc_if = ifp->if_softc; 980 int rc; 981 982 (void) sk_init(ifp); 983 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 984 return 0; 985 return rc; 986 } 987 988 static void 989 sk_promisc(struct sk_if_softc *sc_if, int on) 990 { 991 struct sk_softc *sc = sc_if->sk_softc; 992 switch (sc->sk_type) { 993 case SK_GENESIS: 994 if (on) 995 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 996 else 997 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 998 break; 999 case SK_YUKON: 1000 case SK_YUKON_LITE: 1001 case SK_YUKON_LP: 1002 if (on) 1003 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1004 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1005 else 1006 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1007 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1008 break; 1009 default: 1010 aprint_error_dev(sc_if->sk_dev, "Can't set promisc for %d\n", 1011 sc->sk_type); 1012 break; 1013 } 1014 } 1015 1016 int 1017 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 1018 { 1019 struct sk_if_softc *sc_if = ifp->if_softc; 1020 int s, error = 0; 1021 1022 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1023 1024 s = splnet(); 1025 1026 switch (command) { 1027 1028 case SIOCSIFFLAGS: 1029 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1030 if ((error = ifioctl_common(ifp, command, data)) != 0) 1031 break; 1032 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1033 case IFF_RUNNING: 1034 sk_stop(ifp, 1); 1035 break; 1036 case IFF_UP: 1037 sk_init(ifp); 1038 break; 1039 case IFF_UP | IFF_RUNNING: 1040 if ((ifp->if_flags ^ sc_if->sk_if_flags) == IFF_PROMISC) { 1041 sk_promisc(sc_if, ifp->if_flags & IFF_PROMISC); 1042 sk_setmulti(sc_if); 1043 } else 1044 sk_init(ifp); 1045 break; 1046 } 1047 sc_if->sk_if_flags = ifp->if_flags; 1048 error = 0; 1049 break; 1050 1051 default: 1052 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1053 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1054 break; 1055 1056 error = 0; 1057 1058 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1059 ; 1060 else if (ifp->if_flags & IFF_RUNNING) { 1061 sk_setmulti(sc_if); 1062 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1063 } 1064 break; 1065 } 1066 1067 splx(s); 1068 return error; 1069 } 1070 1071 void 1072 sk_update_int_mod(struct sk_softc *sc) 1073 { 1074 u_int32_t imtimer_ticks; 1075 1076 /* 1077 * Configure interrupt moderation. The moderation timer 1078 * defers interrupts specified in the interrupt moderation 1079 * timer mask based on the timeout specified in the interrupt 1080 * moderation timer init register. Each bit in the timer 1081 * register represents one tick, so to specify a timeout in 1082 * microseconds, we have to multiply by the correct number of 1083 * ticks-per-microsecond. 1084 */ 1085 switch (sc->sk_type) { 1086 case SK_GENESIS: 1087 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1088 break; 1089 case SK_YUKON_EC: 1090 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1091 break; 1092 default: 1093 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1094 } 1095 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1096 sc->sk_int_mod); 1097 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1098 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1099 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1100 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1101 sc->sk_int_mod_pending = 0; 1102 } 1103 1104 /* 1105 * Lookup: Check the PCI vendor and device, and return a pointer to 1106 * The structure if the IDs match against our list. 1107 */ 1108 1109 static const struct sk_product * 1110 sk_lookup(const struct pci_attach_args *pa) 1111 { 1112 const struct sk_product *psk; 1113 1114 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1115 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1116 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1117 return psk; 1118 } 1119 return NULL; 1120 } 1121 1122 /* 1123 * Probe for a SysKonnect GEnesis chip. 1124 */ 1125 1126 int 1127 skc_probe(device_t parent, cfdata_t match, void *aux) 1128 { 1129 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1130 const struct sk_product *psk; 1131 pcireg_t subid; 1132 1133 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1134 1135 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1136 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1137 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1138 subid == SK_LINKSYS_EG1032_SUBID) 1139 return 1; 1140 1141 if ((psk = sk_lookup(pa))) { 1142 return 1; 1143 } 1144 return 0; 1145 } 1146 1147 /* 1148 * Force the GEnesis into reset, then bring it out of reset. 1149 */ 1150 void sk_reset(struct sk_softc *sc) 1151 { 1152 DPRINTFN(2, ("sk_reset\n")); 1153 1154 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1155 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1156 if (SK_YUKON_FAMILY(sc->sk_type)) 1157 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1158 1159 DELAY(1000); 1160 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1161 DELAY(2); 1162 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1163 if (SK_YUKON_FAMILY(sc->sk_type)) 1164 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1165 1166 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1167 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1168 CSR_READ_2(sc, SK_LINK_CTRL))); 1169 1170 if (sc->sk_type == SK_GENESIS) { 1171 /* Configure packet arbiter */ 1172 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1173 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1174 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1175 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1176 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1177 } 1178 1179 /* Enable RAM interface */ 1180 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1181 1182 sk_update_int_mod(sc); 1183 } 1184 1185 int 1186 sk_probe(device_t parent, cfdata_t match, void *aux) 1187 { 1188 struct skc_attach_args *sa = aux; 1189 1190 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1191 return 0; 1192 1193 return 1; 1194 } 1195 1196 /* 1197 * Each XMAC chip is attached as a separate logical IP interface. 1198 * Single port cards will have only one logical interface of course. 1199 */ 1200 void 1201 sk_attach(device_t parent, device_t self, void *aux) 1202 { 1203 struct sk_if_softc *sc_if = device_private(self); 1204 struct sk_softc *sc = device_private(parent); 1205 struct skc_attach_args *sa = aux; 1206 struct sk_txmap_entry *entry; 1207 struct ifnet *ifp; 1208 bus_dma_segment_t seg; 1209 bus_dmamap_t dmamap; 1210 prop_data_t data; 1211 void *kva; 1212 int i, rseg; 1213 int mii_flags = 0; 1214 1215 aprint_naive("\n"); 1216 1217 sc_if->sk_dev = self; 1218 sc_if->sk_port = sa->skc_port; 1219 sc_if->sk_softc = sc; 1220 sc->sk_if[sa->skc_port] = sc_if; 1221 1222 if (sa->skc_port == SK_PORT_A) 1223 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1224 if (sa->skc_port == SK_PORT_B) 1225 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1226 1227 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1228 1229 /* 1230 * Get station address for this interface. Note that 1231 * dual port cards actually come with three station 1232 * addresses: one for each port, plus an extra. The 1233 * extra one is used by the SysKonnect driver software 1234 * as a 'virtual' station address for when both ports 1235 * are operating in failover mode. Currently we don't 1236 * use this extra address. 1237 */ 1238 data = prop_dictionary_get(device_properties(self), "mac-address"); 1239 if (data != NULL) { 1240 /* 1241 * Try to get the station address from device properties 1242 * first, in case the ROM is missing. 1243 */ 1244 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 1245 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 1246 memcpy(sc_if->sk_enaddr, prop_data_data_nocopy(data), 1247 ETHER_ADDR_LEN); 1248 } else 1249 for (i = 0; i < ETHER_ADDR_LEN; i++) 1250 sc_if->sk_enaddr[i] = sk_win_read_1(sc, 1251 SK_MAC0_0 + (sa->skc_port * 8) + i); 1252 1253 aprint_normal(": Ethernet address %s\n", 1254 ether_sprintf(sc_if->sk_enaddr)); 1255 1256 /* 1257 * Set up RAM buffer addresses. The NIC will have a certain 1258 * amount of SRAM on it, somewhere between 512K and 2MB. We 1259 * need to divide this up a) between the transmitter and 1260 * receiver and b) between the two XMACs, if this is a 1261 * dual port NIC. Our algorithm is to divide up the memory 1262 * evenly so that everyone gets a fair share. 1263 */ 1264 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1265 u_int32_t chunk, val; 1266 1267 chunk = sc->sk_ramsize / 2; 1268 val = sc->sk_rboff / sizeof(u_int64_t); 1269 sc_if->sk_rx_ramstart = val; 1270 val += (chunk / sizeof(u_int64_t)); 1271 sc_if->sk_rx_ramend = val - 1; 1272 sc_if->sk_tx_ramstart = val; 1273 val += (chunk / sizeof(u_int64_t)); 1274 sc_if->sk_tx_ramend = val - 1; 1275 } else { 1276 u_int32_t chunk, val; 1277 1278 chunk = sc->sk_ramsize / 4; 1279 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1280 sizeof(u_int64_t); 1281 sc_if->sk_rx_ramstart = val; 1282 val += (chunk / sizeof(u_int64_t)); 1283 sc_if->sk_rx_ramend = val - 1; 1284 sc_if->sk_tx_ramstart = val; 1285 val += (chunk / sizeof(u_int64_t)); 1286 sc_if->sk_tx_ramend = val - 1; 1287 } 1288 1289 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1290 " tx_ramstart=%#x tx_ramend=%#x\n", 1291 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1292 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1293 1294 /* Read and save PHY type and set PHY address */ 1295 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1296 switch (sc_if->sk_phytype) { 1297 case SK_PHYTYPE_XMAC: 1298 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1299 break; 1300 case SK_PHYTYPE_BCOM: 1301 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1302 break; 1303 case SK_PHYTYPE_MARV_COPPER: 1304 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1305 break; 1306 default: 1307 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1308 sc_if->sk_phytype); 1309 return; 1310 } 1311 1312 /* Allocate the descriptor queues. */ 1313 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1314 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1315 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1316 goto fail; 1317 } 1318 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1319 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1320 aprint_error_dev(sc_if->sk_dev, 1321 "can't map dma buffers (%lu bytes)\n", 1322 (u_long) sizeof(struct sk_ring_data)); 1323 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1324 goto fail; 1325 } 1326 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1327 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1328 &sc_if->sk_ring_map)) { 1329 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1330 bus_dmamem_unmap(sc->sc_dmatag, kva, 1331 sizeof(struct sk_ring_data)); 1332 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1333 goto fail; 1334 } 1335 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1336 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1337 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1338 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1339 bus_dmamem_unmap(sc->sc_dmatag, kva, 1340 sizeof(struct sk_ring_data)); 1341 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1342 goto fail; 1343 } 1344 1345 for (i = 0; i < SK_RX_RING_CNT; i++) 1346 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1347 1348 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1349 for (i = 0; i < SK_TX_RING_CNT; i++) { 1350 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1351 1352 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1353 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1354 aprint_error_dev(sc_if->sk_dev, 1355 "Can't create TX dmamap\n"); 1356 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1357 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1358 bus_dmamem_unmap(sc->sc_dmatag, kva, 1359 sizeof(struct sk_ring_data)); 1360 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1361 goto fail; 1362 } 1363 1364 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1365 if (!entry) { 1366 aprint_error_dev(sc_if->sk_dev, 1367 "Can't alloc txmap entry\n"); 1368 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1369 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1370 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1371 bus_dmamem_unmap(sc->sc_dmatag, kva, 1372 sizeof(struct sk_ring_data)); 1373 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1374 goto fail; 1375 } 1376 entry->dmamap = dmamap; 1377 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1378 } 1379 1380 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1381 memset(sc_if->sk_rdata, 0, sizeof(struct sk_ring_data)); 1382 1383 ifp = &sc_if->sk_ethercom.ec_if; 1384 /* Try to allocate memory for jumbo buffers. */ 1385 if (sk_alloc_jumbo_mem(sc_if)) { 1386 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1387 goto fail; 1388 } 1389 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1390 | ETHERCAP_JUMBO_MTU; 1391 1392 ifp->if_softc = sc_if; 1393 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1394 ifp->if_ioctl = sk_ioctl; 1395 ifp->if_start = sk_start; 1396 ifp->if_stop = sk_stop; 1397 ifp->if_init = sk_init; 1398 ifp->if_watchdog = sk_watchdog; 1399 ifp->if_capabilities = 0; 1400 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1401 IFQ_SET_READY(&ifp->if_snd); 1402 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1403 1404 /* 1405 * Do miibus setup. 1406 */ 1407 switch (sc->sk_type) { 1408 case SK_GENESIS: 1409 sk_init_xmac(sc_if); 1410 break; 1411 case SK_YUKON: 1412 case SK_YUKON_LITE: 1413 case SK_YUKON_LP: 1414 sk_init_yukon(sc_if); 1415 break; 1416 default: 1417 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1418 sc->sk_type); 1419 goto fail; 1420 } 1421 1422 DPRINTFN(2, ("sk_attach: 1\n")); 1423 1424 sc_if->sk_mii.mii_ifp = ifp; 1425 switch (sc->sk_type) { 1426 case SK_GENESIS: 1427 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1428 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1429 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1430 break; 1431 case SK_YUKON: 1432 case SK_YUKON_LITE: 1433 case SK_YUKON_LP: 1434 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1435 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1436 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1437 mii_flags = MIIF_DOPAUSE; 1438 break; 1439 } 1440 1441 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1442 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1443 sk_ifmedia_upd, ether_mediastatus); 1444 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1445 MII_OFFSET_ANY, mii_flags); 1446 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1447 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1448 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1449 0, NULL); 1450 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1451 } else 1452 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1453 1454 callout_init(&sc_if->sk_tick_ch, 0); 1455 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1456 1457 DPRINTFN(2, ("sk_attach: 1\n")); 1458 1459 /* 1460 * Call MI attach routines. 1461 */ 1462 if_attach(ifp); 1463 if_deferred_start_init(ifp, NULL); 1464 1465 ether_ifattach(ifp, sc_if->sk_enaddr); 1466 1467 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1468 RND_TYPE_NET, RND_FLAG_DEFAULT); 1469 1470 if (pmf_device_register(self, NULL, sk_resume)) 1471 pmf_class_network_register(self, ifp); 1472 else 1473 aprint_error_dev(self, "couldn't establish power handler\n"); 1474 1475 DPRINTFN(2, ("sk_attach: end\n")); 1476 1477 return; 1478 1479 fail: 1480 sc->sk_if[sa->skc_port] = NULL; 1481 } 1482 1483 int 1484 skcprint(void *aux, const char *pnp) 1485 { 1486 struct skc_attach_args *sa = aux; 1487 1488 if (pnp) 1489 aprint_normal("sk port %c at %s", 1490 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1491 else 1492 aprint_normal(" port %c", 1493 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1494 return UNCONF; 1495 } 1496 1497 /* 1498 * Attach the interface. Allocate softc structures, do ifmedia 1499 * setup and ethernet/BPF attach. 1500 */ 1501 void 1502 skc_attach(device_t parent, device_t self, void *aux) 1503 { 1504 struct sk_softc *sc = device_private(self); 1505 struct pci_attach_args *pa = aux; 1506 struct skc_attach_args skca; 1507 pci_chipset_tag_t pc = pa->pa_pc; 1508 #ifndef SK_USEIOSPACE 1509 pcireg_t memtype; 1510 #endif 1511 pci_intr_handle_t ih; 1512 const char *intrstr = NULL; 1513 bus_addr_t iobase; 1514 bus_size_t iosize; 1515 int rc, sk_nodenum; 1516 u_int32_t command; 1517 const char *revstr; 1518 const struct sysctlnode *node; 1519 char intrbuf[PCI_INTRSTR_LEN]; 1520 1521 sc->sk_dev = self; 1522 aprint_naive("\n"); 1523 1524 DPRINTFN(2, ("begin skc_attach\n")); 1525 1526 /* 1527 * Handle power management nonsense. 1528 */ 1529 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1530 1531 if (command == 0x01) { 1532 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1533 if (command & SK_PSTATE_MASK) { 1534 u_int32_t xiobase, membase, irq; 1535 1536 /* Save important PCI config data. */ 1537 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1538 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1539 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1540 1541 /* Reset the power state. */ 1542 aprint_normal_dev(sc->sk_dev, 1543 "chip is in D%d power mode -- setting to D0\n", 1544 command & SK_PSTATE_MASK); 1545 command &= 0xFFFFFFFC; 1546 pci_conf_write(pc, pa->pa_tag, 1547 SK_PCI_PWRMGMTCTRL, command); 1548 1549 /* Restore PCI config data. */ 1550 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1551 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1552 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1553 } 1554 } 1555 1556 /* 1557 * The firmware might have configured the interface to revert the 1558 * byte order in all descriptors. Make that undone. 1559 */ 1560 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_OURREG2); 1561 if (command & SK_REG2_REV_DESC) 1562 pci_conf_write(pc, pa->pa_tag, SK_PCI_OURREG2, 1563 command & ~SK_REG2_REV_DESC); 1564 1565 /* 1566 * Map control/status registers. 1567 */ 1568 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1569 command |= PCI_COMMAND_IO_ENABLE | 1570 PCI_COMMAND_MEM_ENABLE | 1571 PCI_COMMAND_MASTER_ENABLE; 1572 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1573 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1574 1575 #ifdef SK_USEIOSPACE 1576 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1577 aprint_error(": failed to enable I/O ports!\n"); 1578 return; 1579 } 1580 /* 1581 * Map control/status registers. 1582 */ 1583 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1584 &sc->sk_btag, &sc->sk_bhandle, 1585 &iobase, &iosize)) { 1586 aprint_error(": can't find i/o space\n"); 1587 return; 1588 } 1589 #else 1590 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1591 aprint_error(": failed to enable memory mapping!\n"); 1592 return; 1593 } 1594 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1595 switch (memtype) { 1596 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1597 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1598 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1599 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1600 &iobase, &iosize) == 0) 1601 break; 1602 default: 1603 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1604 return; 1605 } 1606 1607 DPRINTFN(2, ("skc_attach: iobase=%#" PRIxPADDR ", iosize=%zx\n", 1608 iobase, iosize)); 1609 #endif 1610 sc->sc_dmatag = pa->pa_dmat; 1611 1612 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1613 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1614 1615 /* bail out here if chip is not recognized */ 1616 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1617 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1618 goto fail; 1619 } 1620 if (SK_IS_YUKON2(sc)) { 1621 aprint_error_dev(sc->sk_dev, 1622 "Does not support Yukon2--try msk(4).\n"); 1623 goto fail; 1624 } 1625 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1626 1627 /* Allocate interrupt */ 1628 if (pci_intr_map(pa, &ih)) { 1629 aprint_error(": couldn't map interrupt\n"); 1630 goto fail; 1631 } 1632 1633 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1634 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1635 if (sc->sk_intrhand == NULL) { 1636 aprint_error(": couldn't establish interrupt"); 1637 if (intrstr != NULL) 1638 aprint_error(" at %s", intrstr); 1639 aprint_error("\n"); 1640 goto fail; 1641 } 1642 aprint_normal(": %s\n", intrstr); 1643 1644 /* Reset the adapter. */ 1645 sk_reset(sc); 1646 1647 /* Read and save vital product data from EEPROM. */ 1648 sk_vpd_read(sc); 1649 1650 if (sc->sk_type == SK_GENESIS) { 1651 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1652 /* Read and save RAM size and RAMbuffer offset */ 1653 switch (val) { 1654 case SK_RAMSIZE_512K_64: 1655 sc->sk_ramsize = 0x80000; 1656 sc->sk_rboff = SK_RBOFF_0; 1657 break; 1658 case SK_RAMSIZE_1024K_64: 1659 sc->sk_ramsize = 0x100000; 1660 sc->sk_rboff = SK_RBOFF_80000; 1661 break; 1662 case SK_RAMSIZE_1024K_128: 1663 sc->sk_ramsize = 0x100000; 1664 sc->sk_rboff = SK_RBOFF_0; 1665 break; 1666 case SK_RAMSIZE_2048K_128: 1667 sc->sk_ramsize = 0x200000; 1668 sc->sk_rboff = SK_RBOFF_0; 1669 break; 1670 default: 1671 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1672 val); 1673 goto fail_1; 1674 break; 1675 } 1676 1677 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1678 sc->sk_ramsize, sc->sk_ramsize / 1024, 1679 sc->sk_rboff)); 1680 } else { 1681 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1682 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1683 sc->sk_rboff = SK_RBOFF_0; 1684 1685 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1686 sc->sk_ramsize / 1024, sc->sk_ramsize, 1687 sc->sk_rboff)); 1688 } 1689 1690 /* Read and save physical media type */ 1691 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1692 case SK_PMD_1000BASESX: 1693 sc->sk_pmd = IFM_1000_SX; 1694 break; 1695 case SK_PMD_1000BASELX: 1696 sc->sk_pmd = IFM_1000_LX; 1697 break; 1698 case SK_PMD_1000BASECX: 1699 sc->sk_pmd = IFM_1000_CX; 1700 break; 1701 case SK_PMD_1000BASETX: 1702 case SK_PMD_1000BASETX_ALT: 1703 sc->sk_pmd = IFM_1000_T; 1704 break; 1705 default: 1706 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1707 sk_win_read_1(sc, SK_PMDTYPE)); 1708 goto fail_1; 1709 } 1710 1711 /* determine whether to name it with vpd or just make it up */ 1712 /* Marvell Yukon VPD's can freqently be bogus */ 1713 1714 switch (pa->pa_id) { 1715 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1716 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1717 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1718 case PCI_PRODUCT_3COM_3C940: 1719 case PCI_PRODUCT_DLINK_DGE530T: 1720 case PCI_PRODUCT_DLINK_DGE560T: 1721 case PCI_PRODUCT_DLINK_DGE560T_2: 1722 case PCI_PRODUCT_LINKSYS_EG1032: 1723 case PCI_PRODUCT_LINKSYS_EG1064: 1724 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1725 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1726 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1727 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1728 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1729 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1730 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1731 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1732 sc->sk_name = sc->sk_vpd_prodname; 1733 break; 1734 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1735 /* whoops yukon vpd prodname bears no resemblance to reality */ 1736 switch (sc->sk_type) { 1737 case SK_GENESIS: 1738 sc->sk_name = sc->sk_vpd_prodname; 1739 break; 1740 case SK_YUKON: 1741 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1742 break; 1743 case SK_YUKON_LITE: 1744 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1745 break; 1746 case SK_YUKON_LP: 1747 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1748 break; 1749 default: 1750 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1751 } 1752 1753 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1754 1755 if ( sc->sk_type == SK_YUKON ) { 1756 uint32_t flashaddr; 1757 uint8_t testbyte; 1758 1759 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1760 1761 /* test Flash-Address Register */ 1762 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1763 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1764 1765 if (testbyte != 0) { 1766 /* this is yukon lite Rev. A0 */ 1767 sc->sk_type = SK_YUKON_LITE; 1768 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1769 /* restore Flash-Address Register */ 1770 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1771 } 1772 } 1773 break; 1774 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1775 sc->sk_name = sc->sk_vpd_prodname; 1776 break; 1777 default: 1778 sc->sk_name = "Unknown Marvell"; 1779 } 1780 1781 1782 if ( sc->sk_type == SK_YUKON_LITE ) { 1783 switch (sc->sk_rev) { 1784 case SK_YUKON_LITE_REV_A0: 1785 revstr = "A0"; 1786 break; 1787 case SK_YUKON_LITE_REV_A1: 1788 revstr = "A1"; 1789 break; 1790 case SK_YUKON_LITE_REV_A3: 1791 revstr = "A3"; 1792 break; 1793 default: 1794 revstr = ""; 1795 } 1796 } else { 1797 revstr = ""; 1798 } 1799 1800 /* Announce the product name. */ 1801 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1802 sc->sk_name, revstr, sc->sk_rev); 1803 1804 skca.skc_port = SK_PORT_A; 1805 (void)config_found(sc->sk_dev, &skca, skcprint); 1806 1807 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1808 skca.skc_port = SK_PORT_B; 1809 (void)config_found(sc->sk_dev, &skca, skcprint); 1810 } 1811 1812 /* Turn on the 'driver is loaded' LED. */ 1813 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1814 1815 /* skc sysctl setup */ 1816 1817 sc->sk_int_mod = SK_IM_DEFAULT; 1818 sc->sk_int_mod_pending = 0; 1819 1820 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1821 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1822 SYSCTL_DESCR("skc per-controller controls"), 1823 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1824 CTL_EOL)) != 0) { 1825 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1826 goto fail_1; 1827 } 1828 1829 sk_nodenum = node->sysctl_num; 1830 1831 /* interrupt moderation time in usecs */ 1832 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1833 CTLFLAG_READWRITE, 1834 CTLTYPE_INT, "int_mod", 1835 SYSCTL_DESCR("sk interrupt moderation timer"), 1836 sk_sysctl_handler, 0, (void *)sc, 1837 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1838 CTL_EOL)) != 0) { 1839 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1840 goto fail_1; 1841 } 1842 1843 if (!pmf_device_register(self, skc_suspend, skc_resume)) 1844 aprint_error_dev(self, "couldn't establish power handler\n"); 1845 1846 return; 1847 1848 fail_1: 1849 pci_intr_disestablish(pc, sc->sk_intrhand); 1850 fail: 1851 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1852 } 1853 1854 int 1855 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1856 { 1857 struct sk_softc *sc = sc_if->sk_softc; 1858 struct sk_tx_desc *f = NULL; 1859 u_int32_t frag, cur, cnt = 0, sk_ctl; 1860 int i; 1861 struct sk_txmap_entry *entry; 1862 bus_dmamap_t txmap; 1863 1864 DPRINTFN(3, ("sk_encap\n")); 1865 1866 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1867 if (entry == NULL) { 1868 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1869 return ENOBUFS; 1870 } 1871 txmap = entry->dmamap; 1872 1873 cur = frag = *txidx; 1874 1875 #ifdef SK_DEBUG 1876 if (skdebug >= 3) 1877 sk_dump_mbuf(m_head); 1878 #endif 1879 1880 /* 1881 * Start packing the mbufs in this chain into 1882 * the fragment pointers. Stop when we run out 1883 * of fragments or hit the end of the mbuf chain. 1884 */ 1885 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1886 BUS_DMA_NOWAIT)) { 1887 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1888 return ENOBUFS; 1889 } 1890 1891 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1892 1893 /* Sync the DMA map. */ 1894 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1895 BUS_DMASYNC_PREWRITE); 1896 1897 for (i = 0; i < txmap->dm_nsegs; i++) { 1898 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1899 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1900 return ENOBUFS; 1901 } 1902 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1903 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1904 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1905 if (cnt == 0) 1906 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1907 else 1908 sk_ctl |= SK_TXCTL_OWN; 1909 f->sk_ctl = htole32(sk_ctl); 1910 cur = frag; 1911 SK_INC(frag, SK_TX_RING_CNT); 1912 cnt++; 1913 } 1914 1915 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1916 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1917 1918 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1919 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1920 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1921 1922 /* Sync descriptors before handing to chip */ 1923 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1924 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1925 1926 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1927 htole32(SK_TXCTL_OWN); 1928 1929 /* Sync first descriptor to hand it off */ 1930 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1931 1932 sc_if->sk_cdata.sk_tx_cnt += cnt; 1933 1934 #ifdef SK_DEBUG 1935 if (skdebug >= 3) { 1936 struct sk_tx_desc *desc; 1937 u_int32_t idx; 1938 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1939 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1940 sk_dump_txdesc(desc, idx); 1941 } 1942 } 1943 #endif 1944 1945 *txidx = frag; 1946 1947 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1948 1949 return 0; 1950 } 1951 1952 void 1953 sk_start(struct ifnet *ifp) 1954 { 1955 struct sk_if_softc *sc_if = ifp->if_softc; 1956 struct sk_softc *sc = sc_if->sk_softc; 1957 struct mbuf *m_head = NULL; 1958 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1959 int pkts = 0; 1960 1961 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1962 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1963 1964 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1965 IFQ_POLL(&ifp->if_snd, m_head); 1966 if (m_head == NULL) 1967 break; 1968 1969 /* 1970 * Pack the data into the transmit ring. If we 1971 * don't have room, set the OACTIVE flag and wait 1972 * for the NIC to drain the ring. 1973 */ 1974 if (sk_encap(sc_if, m_head, &idx)) { 1975 ifp->if_flags |= IFF_OACTIVE; 1976 break; 1977 } 1978 1979 /* now we are committed to transmit the packet */ 1980 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1981 pkts++; 1982 1983 /* 1984 * If there's a BPF listener, bounce a copy of this frame 1985 * to him. 1986 */ 1987 bpf_mtap(ifp, m_head); 1988 } 1989 if (pkts == 0) 1990 return; 1991 1992 /* Transmit */ 1993 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1994 sc_if->sk_cdata.sk_tx_prod = idx; 1995 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1996 1997 /* Set a timeout in case the chip goes out to lunch. */ 1998 ifp->if_timer = 5; 1999 } 2000 } 2001 2002 2003 void 2004 sk_watchdog(struct ifnet *ifp) 2005 { 2006 struct sk_if_softc *sc_if = ifp->if_softc; 2007 2008 /* 2009 * Reclaim first as there is a possibility of losing Tx completion 2010 * interrupts. 2011 */ 2012 sk_txeof(sc_if); 2013 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2014 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 2015 2016 ifp->if_oerrors++; 2017 2018 sk_init(ifp); 2019 } 2020 } 2021 2022 void 2023 sk_shutdown(void *v) 2024 { 2025 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2026 struct sk_softc *sc = sc_if->sk_softc; 2027 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2028 2029 DPRINTFN(2, ("sk_shutdown\n")); 2030 sk_stop(ifp,1); 2031 2032 /* Turn off the 'driver is loaded' LED. */ 2033 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2034 2035 /* 2036 * Reset the GEnesis controller. Doing this should also 2037 * assert the resets on the attached XMAC(s). 2038 */ 2039 sk_reset(sc); 2040 } 2041 2042 void 2043 sk_rxeof(struct sk_if_softc *sc_if) 2044 { 2045 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2046 struct mbuf *m; 2047 struct sk_chain *cur_rx; 2048 struct sk_rx_desc *cur_desc; 2049 int i, cur, total_len = 0; 2050 u_int32_t rxstat, sk_ctl; 2051 bus_dmamap_t dmamap; 2052 2053 i = sc_if->sk_cdata.sk_rx_prod; 2054 2055 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2056 2057 for (;;) { 2058 cur = i; 2059 2060 /* Sync the descriptor */ 2061 SK_CDRXSYNC(sc_if, cur, 2062 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2063 2064 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2065 if (sk_ctl & SK_RXCTL_OWN) { 2066 /* Invalidate the descriptor -- it's not ready yet */ 2067 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2068 sc_if->sk_cdata.sk_rx_prod = i; 2069 break; 2070 } 2071 2072 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2073 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2074 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2075 2076 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2077 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2078 2079 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2080 m = cur_rx->sk_mbuf; 2081 cur_rx->sk_mbuf = NULL; 2082 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2083 2084 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2085 2086 SK_INC(i, SK_RX_RING_CNT); 2087 2088 if (rxstat & XM_RXSTAT_ERRFRAME) { 2089 ifp->if_ierrors++; 2090 sk_newbuf(sc_if, cur, m, dmamap); 2091 continue; 2092 } 2093 2094 /* 2095 * Try to allocate a new jumbo buffer. If that 2096 * fails, copy the packet to mbufs and put the 2097 * jumbo buffer back in the ring so it can be 2098 * re-used. If allocating mbufs fails, then we 2099 * have to drop the packet. 2100 */ 2101 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2102 struct mbuf *m0; 2103 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2104 total_len + ETHER_ALIGN, 0, ifp, NULL); 2105 sk_newbuf(sc_if, cur, m, dmamap); 2106 if (m0 == NULL) { 2107 aprint_error_dev(sc_if->sk_dev, "no receive " 2108 "buffers available -- packet dropped!\n"); 2109 ifp->if_ierrors++; 2110 continue; 2111 } 2112 m_adj(m0, ETHER_ALIGN); 2113 m = m0; 2114 } else { 2115 m_set_rcvif(m, ifp); 2116 m->m_pkthdr.len = m->m_len = total_len; 2117 } 2118 2119 ifp->if_ipackets++; 2120 2121 bpf_mtap(ifp, m); 2122 /* pass it on. */ 2123 if_percpuq_enqueue(ifp->if_percpuq, m); 2124 } 2125 } 2126 2127 void 2128 sk_txeof(struct sk_if_softc *sc_if) 2129 { 2130 struct sk_softc *sc = sc_if->sk_softc; 2131 struct sk_tx_desc *cur_tx; 2132 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2133 u_int32_t idx, sk_ctl; 2134 struct sk_txmap_entry *entry; 2135 2136 DPRINTFN(3, ("sk_txeof\n")); 2137 2138 /* 2139 * Go through our tx ring and free mbufs for those 2140 * frames that have been sent. 2141 */ 2142 idx = sc_if->sk_cdata.sk_tx_cons; 2143 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2144 SK_CDTXSYNC(sc_if, idx, 1, 2145 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2146 2147 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2148 sk_ctl = le32toh(cur_tx->sk_ctl); 2149 #ifdef SK_DEBUG 2150 if (skdebug >= 3) 2151 sk_dump_txdesc(cur_tx, idx); 2152 #endif 2153 if (sk_ctl & SK_TXCTL_OWN) { 2154 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2155 break; 2156 } 2157 if (sk_ctl & SK_TXCTL_LASTFRAG) 2158 ifp->if_opackets++; 2159 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2160 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2161 2162 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2163 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2164 2165 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2166 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2167 2168 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2169 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2170 link); 2171 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2172 } 2173 sc_if->sk_cdata.sk_tx_cnt--; 2174 SK_INC(idx, SK_TX_RING_CNT); 2175 } 2176 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2177 ifp->if_timer = 0; 2178 else /* nudge chip to keep tx ring moving */ 2179 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2180 2181 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2182 ifp->if_flags &= ~IFF_OACTIVE; 2183 2184 sc_if->sk_cdata.sk_tx_cons = idx; 2185 } 2186 2187 void 2188 sk_tick(void *xsc_if) 2189 { 2190 struct sk_if_softc *sc_if = xsc_if; 2191 struct mii_data *mii = &sc_if->sk_mii; 2192 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2193 int i; 2194 2195 DPRINTFN(3, ("sk_tick\n")); 2196 2197 if (!(ifp->if_flags & IFF_UP)) 2198 return; 2199 2200 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2201 sk_intr_bcom(sc_if); 2202 return; 2203 } 2204 2205 /* 2206 * According to SysKonnect, the correct way to verify that 2207 * the link has come back up is to poll bit 0 of the GPIO 2208 * register three times. This pin has the signal from the 2209 * link sync pin connected to it; if we read the same link 2210 * state 3 times in a row, we know the link is up. 2211 */ 2212 for (i = 0; i < 3; i++) { 2213 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2214 break; 2215 } 2216 2217 if (i != 3) { 2218 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2219 return; 2220 } 2221 2222 /* Turn the GP0 interrupt back on. */ 2223 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2224 SK_XM_READ_2(sc_if, XM_ISR); 2225 mii_tick(mii); 2226 if (ifp->if_link_state != LINK_STATE_UP) 2227 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2228 else 2229 callout_stop(&sc_if->sk_tick_ch); 2230 } 2231 2232 void 2233 sk_intr_bcom(struct sk_if_softc *sc_if) 2234 { 2235 struct mii_data *mii = &sc_if->sk_mii; 2236 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2237 int status; 2238 2239 2240 DPRINTFN(3, ("sk_intr_bcom\n")); 2241 2242 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2243 2244 /* 2245 * Read the PHY interrupt register to make sure 2246 * we clear any pending interrupts. 2247 */ 2248 status = sk_xmac_miibus_readreg(sc_if->sk_dev, 2249 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2250 2251 if (!(ifp->if_flags & IFF_RUNNING)) { 2252 sk_init_xmac(sc_if); 2253 return; 2254 } 2255 2256 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2257 int lstat; 2258 lstat = sk_xmac_miibus_readreg(sc_if->sk_dev, 2259 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2260 2261 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2262 (void)mii_mediachg(mii); 2263 /* Turn off the link LED. */ 2264 SK_IF_WRITE_1(sc_if, 0, 2265 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2266 sc_if->sk_link = 0; 2267 } else if (status & BRGPHY_ISR_LNK_CHG) { 2268 sk_xmac_miibus_writereg(sc_if->sk_dev, 2269 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2270 mii_tick(mii); 2271 sc_if->sk_link = 1; 2272 /* Turn on the link LED. */ 2273 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2274 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2275 SK_LINKLED_BLINK_OFF); 2276 mii_pollstat(mii); 2277 } else { 2278 mii_tick(mii); 2279 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2280 } 2281 } 2282 2283 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2284 } 2285 2286 void 2287 sk_intr_xmac(struct sk_if_softc *sc_if) 2288 { 2289 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2290 2291 DPRINTFN(3, ("sk_intr_xmac\n")); 2292 2293 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2294 if (status & XM_ISR_GP0_SET) { 2295 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2296 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2297 } 2298 2299 if (status & XM_ISR_AUTONEG_DONE) { 2300 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2301 } 2302 } 2303 2304 if (status & XM_IMR_TX_UNDERRUN) 2305 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2306 2307 if (status & XM_IMR_RX_OVERRUN) 2308 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2309 } 2310 2311 void 2312 sk_intr_yukon(struct sk_if_softc *sc_if) 2313 { 2314 #ifdef SK_DEBUG 2315 int status; 2316 2317 status = 2318 #endif 2319 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2320 2321 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2322 } 2323 2324 int 2325 sk_intr(void *xsc) 2326 { 2327 struct sk_softc *sc = xsc; 2328 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2329 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2330 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2331 u_int32_t status; 2332 int claimed = 0; 2333 2334 if (sc_if0 != NULL) 2335 ifp0 = &sc_if0->sk_ethercom.ec_if; 2336 if (sc_if1 != NULL) 2337 ifp1 = &sc_if1->sk_ethercom.ec_if; 2338 2339 for (;;) { 2340 status = CSR_READ_4(sc, SK_ISSR); 2341 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2342 2343 if (!(status & sc->sk_intrmask)) 2344 break; 2345 2346 claimed = 1; 2347 2348 /* Handle receive interrupts first. */ 2349 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2350 sk_rxeof(sc_if0); 2351 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2352 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2353 } 2354 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2355 sk_rxeof(sc_if1); 2356 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2357 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2358 } 2359 2360 /* Then transmit interrupts. */ 2361 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2362 sk_txeof(sc_if0); 2363 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2364 SK_TXBMU_CLR_IRQ_EOF); 2365 } 2366 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2367 sk_txeof(sc_if1); 2368 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2369 SK_TXBMU_CLR_IRQ_EOF); 2370 } 2371 2372 /* Then MAC interrupts. */ 2373 if (sc_if0 && (status & SK_ISR_MAC1) && 2374 (ifp0->if_flags & IFF_RUNNING)) { 2375 if (sc->sk_type == SK_GENESIS) 2376 sk_intr_xmac(sc_if0); 2377 else 2378 sk_intr_yukon(sc_if0); 2379 } 2380 2381 if (sc_if1 && (status & SK_ISR_MAC2) && 2382 (ifp1->if_flags & IFF_RUNNING)) { 2383 if (sc->sk_type == SK_GENESIS) 2384 sk_intr_xmac(sc_if1); 2385 else 2386 sk_intr_yukon(sc_if1); 2387 2388 } 2389 2390 if (status & SK_ISR_EXTERNAL_REG) { 2391 if (sc_if0 != NULL && 2392 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2393 sk_intr_bcom(sc_if0); 2394 2395 if (sc_if1 != NULL && 2396 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2397 sk_intr_bcom(sc_if1); 2398 } 2399 } 2400 2401 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2402 2403 if (ifp0 != NULL) 2404 if_schedule_deferred_start(ifp0); 2405 if (ifp1 != NULL) 2406 if_schedule_deferred_start(ifp1); 2407 2408 rnd_add_uint32(&sc->rnd_source, status); 2409 2410 if (sc->sk_int_mod_pending) 2411 sk_update_int_mod(sc); 2412 2413 return claimed; 2414 } 2415 2416 void 2417 sk_init_xmac(struct sk_if_softc *sc_if) 2418 { 2419 struct sk_softc *sc = sc_if->sk_softc; 2420 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2421 static const struct sk_bcom_hack bhack[] = { 2422 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2423 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2424 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2425 { 0, 0 } }; 2426 2427 DPRINTFN(1, ("sk_init_xmac\n")); 2428 2429 /* Unreset the XMAC. */ 2430 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2431 DELAY(1000); 2432 2433 /* Reset the XMAC's internal state. */ 2434 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2435 2436 /* Save the XMAC II revision */ 2437 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2438 2439 /* 2440 * Perform additional initialization for external PHYs, 2441 * namely for the 1000baseTX cards that use the XMAC's 2442 * GMII mode. 2443 */ 2444 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2445 int i = 0; 2446 u_int32_t val; 2447 2448 /* Take PHY out of reset. */ 2449 val = sk_win_read_4(sc, SK_GPIO); 2450 if (sc_if->sk_port == SK_PORT_A) 2451 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2452 else 2453 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2454 sk_win_write_4(sc, SK_GPIO, val); 2455 2456 /* Enable GMII mode on the XMAC. */ 2457 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2458 2459 sk_xmac_miibus_writereg(sc_if->sk_dev, 2460 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2461 DELAY(10000); 2462 sk_xmac_miibus_writereg(sc_if->sk_dev, 2463 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2464 2465 /* 2466 * Early versions of the BCM5400 apparently have 2467 * a bug that requires them to have their reserved 2468 * registers initialized to some magic values. I don't 2469 * know what the numbers do, I'm just the messenger. 2470 */ 2471 if (sk_xmac_miibus_readreg(sc_if->sk_dev, 2472 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2473 while (bhack[i].reg) { 2474 sk_xmac_miibus_writereg(sc_if->sk_dev, 2475 SK_PHYADDR_BCOM, bhack[i].reg, 2476 bhack[i].val); 2477 i++; 2478 } 2479 } 2480 } 2481 2482 /* Set station address */ 2483 SK_XM_WRITE_2(sc_if, XM_PAR0, 2484 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2485 SK_XM_WRITE_2(sc_if, XM_PAR1, 2486 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2487 SK_XM_WRITE_2(sc_if, XM_PAR2, 2488 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2489 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2490 2491 if (ifp->if_flags & IFF_PROMISC) 2492 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2493 else 2494 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2495 2496 if (ifp->if_flags & IFF_BROADCAST) 2497 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2498 else 2499 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2500 2501 /* We don't need the FCS appended to the packet. */ 2502 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2503 2504 /* We want short frames padded to 60 bytes. */ 2505 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2506 2507 /* 2508 * Enable the reception of all error frames. This is is 2509 * a necessary evil due to the design of the XMAC. The 2510 * XMAC's receive FIFO is only 8K in size, however jumbo 2511 * frames can be up to 9000 bytes in length. When bad 2512 * frame filtering is enabled, the XMAC's RX FIFO operates 2513 * in 'store and forward' mode. For this to work, the 2514 * entire frame has to fit into the FIFO, but that means 2515 * that jumbo frames larger than 8192 bytes will be 2516 * truncated. Disabling all bad frame filtering causes 2517 * the RX FIFO to operate in streaming mode, in which 2518 * case the XMAC will start transfering frames out of the 2519 * RX FIFO as soon as the FIFO threshold is reached. 2520 */ 2521 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2522 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2523 XM_MODE_RX_INRANGELEN); 2524 2525 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2526 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2527 else 2528 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2529 2530 /* 2531 * Bump up the transmit threshold. This helps hold off transmit 2532 * underruns when we're blasting traffic from both ports at once. 2533 */ 2534 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2535 2536 /* Set multicast filter */ 2537 sk_setmulti(sc_if); 2538 2539 /* Clear and enable interrupts */ 2540 SK_XM_READ_2(sc_if, XM_ISR); 2541 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2542 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2543 else 2544 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2545 2546 /* Configure MAC arbiter */ 2547 switch (sc_if->sk_xmac_rev) { 2548 case XM_XMAC_REV_B2: 2549 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2550 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2551 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2552 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2553 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2554 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2555 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2556 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2557 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2558 break; 2559 case XM_XMAC_REV_C1: 2560 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2561 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2562 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2563 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2564 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2565 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2566 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2567 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2568 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2569 break; 2570 default: 2571 break; 2572 } 2573 sk_win_write_2(sc, SK_MACARB_CTL, 2574 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2575 2576 sc_if->sk_link = 1; 2577 } 2578 2579 void sk_init_yukon(struct sk_if_softc *sc_if) 2580 { 2581 u_int32_t /*mac, */phy; 2582 u_int16_t reg; 2583 struct sk_softc *sc; 2584 int i; 2585 2586 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2587 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2588 2589 sc = sc_if->sk_softc; 2590 if (sc->sk_type == SK_YUKON_LITE && 2591 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2592 /* Take PHY out of reset. */ 2593 sk_win_write_4(sc, SK_GPIO, 2594 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2595 } 2596 2597 2598 /* GMAC and GPHY Reset */ 2599 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2600 2601 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2602 2603 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2604 DELAY(1000); 2605 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2606 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2607 DELAY(1000); 2608 2609 2610 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2611 2612 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2613 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2614 2615 switch (sc_if->sk_softc->sk_pmd) { 2616 case IFM_1000_SX: 2617 case IFM_1000_LX: 2618 phy |= SK_GPHY_FIBER; 2619 break; 2620 2621 case IFM_1000_CX: 2622 case IFM_1000_T: 2623 phy |= SK_GPHY_COPPER; 2624 break; 2625 } 2626 2627 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2628 2629 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2630 DELAY(1000); 2631 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2632 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2633 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2634 2635 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2636 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2637 2638 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2639 2640 /* unused read of the interrupt source register */ 2641 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2642 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2643 2644 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2645 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2646 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2647 2648 /* MIB Counter Clear Mode set */ 2649 reg |= YU_PAR_MIB_CLR; 2650 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2651 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2652 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2653 2654 /* MIB Counter Clear Mode clear */ 2655 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2656 reg &= ~YU_PAR_MIB_CLR; 2657 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2658 2659 /* receive control reg */ 2660 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2661 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2662 YU_RCR_CRCR); 2663 2664 /* transmit parameter register */ 2665 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2666 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2667 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2668 2669 /* serial mode register */ 2670 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2671 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2672 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2673 YU_SMR_IPG_DATA(0x1e)); 2674 2675 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2676 /* Setup Yukon's address */ 2677 for (i = 0; i < 3; i++) { 2678 /* Write Source Address 1 (unicast filter) */ 2679 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2680 sc_if->sk_enaddr[i * 2] | 2681 sc_if->sk_enaddr[i * 2 + 1] << 8); 2682 } 2683 2684 for (i = 0; i < 3; i++) { 2685 reg = sk_win_read_2(sc_if->sk_softc, 2686 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2687 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2688 } 2689 2690 /* Set multicast filter */ 2691 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2692 sk_setmulti(sc_if); 2693 2694 /* enable interrupt mask for counter overflows */ 2695 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2696 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2697 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2698 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2699 2700 /* Configure RX MAC FIFO */ 2701 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2702 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2703 2704 /* Configure TX MAC FIFO */ 2705 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2706 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2707 2708 DPRINTFN(6, ("sk_init_yukon: end\n")); 2709 } 2710 2711 /* 2712 * Note that to properly initialize any part of the GEnesis chip, 2713 * you first have to take it out of reset mode. 2714 */ 2715 int 2716 sk_init(struct ifnet *ifp) 2717 { 2718 struct sk_if_softc *sc_if = ifp->if_softc; 2719 struct sk_softc *sc = sc_if->sk_softc; 2720 struct mii_data *mii = &sc_if->sk_mii; 2721 int rc = 0, s; 2722 u_int32_t imr, imtimer_ticks; 2723 2724 DPRINTFN(1, ("sk_init\n")); 2725 2726 s = splnet(); 2727 2728 if (ifp->if_flags & IFF_RUNNING) { 2729 splx(s); 2730 return 0; 2731 } 2732 2733 /* Cancel pending I/O and free all RX/TX buffers. */ 2734 sk_stop(ifp,0); 2735 2736 if (sc->sk_type == SK_GENESIS) { 2737 /* Configure LINK_SYNC LED */ 2738 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2739 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2740 SK_LINKLED_LINKSYNC_ON); 2741 2742 /* Configure RX LED */ 2743 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2744 SK_RXLEDCTL_COUNTER_START); 2745 2746 /* Configure TX LED */ 2747 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2748 SK_TXLEDCTL_COUNTER_START); 2749 } 2750 2751 /* Configure I2C registers */ 2752 2753 /* Configure XMAC(s) */ 2754 switch (sc->sk_type) { 2755 case SK_GENESIS: 2756 sk_init_xmac(sc_if); 2757 break; 2758 case SK_YUKON: 2759 case SK_YUKON_LITE: 2760 case SK_YUKON_LP: 2761 sk_init_yukon(sc_if); 2762 break; 2763 } 2764 if ((rc = mii_mediachg(mii)) == ENXIO) 2765 rc = 0; 2766 else if (rc != 0) 2767 goto out; 2768 2769 if (sc->sk_type == SK_GENESIS) { 2770 /* Configure MAC FIFOs */ 2771 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2772 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2773 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2774 2775 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2776 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2777 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2778 } 2779 2780 /* Configure transmit arbiter(s) */ 2781 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2782 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2783 2784 /* Configure RAMbuffers */ 2785 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2786 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2787 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2788 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2789 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2790 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2791 2792 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2793 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2794 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2795 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2796 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2797 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2798 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2799 2800 /* Configure BMUs */ 2801 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2802 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2803 SK_RX_RING_ADDR(sc_if, 0)); 2804 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2805 2806 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2807 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2808 SK_TX_RING_ADDR(sc_if, 0)); 2809 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2810 2811 /* Init descriptors */ 2812 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2813 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2814 "memory for rx buffers\n"); 2815 sk_stop(ifp,0); 2816 splx(s); 2817 return ENOBUFS; 2818 } 2819 2820 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2821 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2822 "memory for tx buffers\n"); 2823 sk_stop(ifp,0); 2824 splx(s); 2825 return ENOBUFS; 2826 } 2827 2828 /* Set interrupt moderation if changed via sysctl. */ 2829 switch (sc->sk_type) { 2830 case SK_GENESIS: 2831 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2832 break; 2833 case SK_YUKON_EC: 2834 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2835 break; 2836 default: 2837 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2838 } 2839 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2840 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2841 sk_win_write_4(sc, SK_IMTIMERINIT, 2842 SK_IM_USECS(sc->sk_int_mod)); 2843 aprint_verbose_dev(sc->sk_dev, 2844 "interrupt moderation is %d us\n", sc->sk_int_mod); 2845 } 2846 2847 /* Configure interrupt handling */ 2848 CSR_READ_4(sc, SK_ISSR); 2849 if (sc_if->sk_port == SK_PORT_A) 2850 sc->sk_intrmask |= SK_INTRS1; 2851 else 2852 sc->sk_intrmask |= SK_INTRS2; 2853 2854 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2855 2856 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2857 2858 /* Start BMUs. */ 2859 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2860 2861 if (sc->sk_type == SK_GENESIS) { 2862 /* Enable XMACs TX and RX state machines */ 2863 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2864 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2865 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2866 } 2867 2868 if (SK_YUKON_FAMILY(sc->sk_type)) { 2869 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2870 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2871 #if 0 2872 /* XXX disable 100Mbps and full duplex mode? */ 2873 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2874 #endif 2875 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2876 } 2877 2878 2879 ifp->if_flags |= IFF_RUNNING; 2880 ifp->if_flags &= ~IFF_OACTIVE; 2881 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2882 2883 out: 2884 splx(s); 2885 return rc; 2886 } 2887 2888 void 2889 sk_stop(struct ifnet *ifp, int disable) 2890 { 2891 struct sk_if_softc *sc_if = ifp->if_softc; 2892 struct sk_softc *sc = sc_if->sk_softc; 2893 int i; 2894 2895 DPRINTFN(1, ("sk_stop\n")); 2896 2897 callout_stop(&sc_if->sk_tick_ch); 2898 2899 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2900 u_int32_t val; 2901 2902 /* Put PHY back into reset. */ 2903 val = sk_win_read_4(sc, SK_GPIO); 2904 if (sc_if->sk_port == SK_PORT_A) { 2905 val |= SK_GPIO_DIR0; 2906 val &= ~SK_GPIO_DAT0; 2907 } else { 2908 val |= SK_GPIO_DIR2; 2909 val &= ~SK_GPIO_DAT2; 2910 } 2911 sk_win_write_4(sc, SK_GPIO, val); 2912 } 2913 2914 /* Turn off various components of this interface. */ 2915 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2916 switch (sc->sk_type) { 2917 case SK_GENESIS: 2918 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2919 SK_TXMACCTL_XMAC_RESET); 2920 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2921 break; 2922 case SK_YUKON: 2923 case SK_YUKON_LITE: 2924 case SK_YUKON_LP: 2925 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2926 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2927 break; 2928 } 2929 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2930 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2931 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2932 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2933 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2934 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2935 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2936 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2937 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2938 2939 /* Disable interrupts */ 2940 if (sc_if->sk_port == SK_PORT_A) 2941 sc->sk_intrmask &= ~SK_INTRS1; 2942 else 2943 sc->sk_intrmask &= ~SK_INTRS2; 2944 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2945 2946 SK_XM_READ_2(sc_if, XM_ISR); 2947 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2948 2949 /* Free RX and TX mbufs still in the queues. */ 2950 for (i = 0; i < SK_RX_RING_CNT; i++) { 2951 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2952 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2953 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2954 } 2955 } 2956 2957 for (i = 0; i < SK_TX_RING_CNT; i++) { 2958 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2959 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2960 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2961 } 2962 } 2963 2964 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2965 } 2966 2967 /* Power Management Framework */ 2968 2969 static bool 2970 skc_suspend(device_t dv, const pmf_qual_t *qual) 2971 { 2972 struct sk_softc *sc = device_private(dv); 2973 2974 DPRINTFN(2, ("skc_suspend\n")); 2975 2976 /* Turn off the driver is loaded LED */ 2977 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2978 2979 return true; 2980 } 2981 2982 static bool 2983 skc_resume(device_t dv, const pmf_qual_t *qual) 2984 { 2985 struct sk_softc *sc = device_private(dv); 2986 2987 DPRINTFN(2, ("skc_resume\n")); 2988 2989 sk_reset(sc); 2990 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2991 2992 return true; 2993 } 2994 2995 static bool 2996 sk_resume(device_t dv, const pmf_qual_t *qual) 2997 { 2998 struct sk_if_softc *sc_if = device_private(dv); 2999 3000 sk_init_yukon(sc_if); 3001 return true; 3002 } 3003 3004 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 3005 skc_probe, skc_attach, NULL, NULL); 3006 3007 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 3008 sk_probe, sk_attach, NULL, NULL); 3009 3010 #ifdef SK_DEBUG 3011 void 3012 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 3013 { 3014 #define DESC_PRINT(X) \ 3015 if (X) \ 3016 printf("txdesc[%d]." #X "=%#x\n", \ 3017 idx, X); 3018 3019 DESC_PRINT(le32toh(desc->sk_ctl)); 3020 DESC_PRINT(le32toh(desc->sk_next)); 3021 DESC_PRINT(le32toh(desc->sk_data_lo)); 3022 DESC_PRINT(le32toh(desc->sk_data_hi)); 3023 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 3024 DESC_PRINT(le16toh(desc->sk_rsvd0)); 3025 DESC_PRINT(le16toh(desc->sk_csum_startval)); 3026 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 3027 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 3028 DESC_PRINT(le16toh(desc->sk_rsvd1)); 3029 #undef PRINT 3030 } 3031 3032 void 3033 sk_dump_bytes(const char *data, int len) 3034 { 3035 int c, i, j; 3036 3037 for (i = 0; i < len; i += 16) { 3038 printf("%08x ", i); 3039 c = len - i; 3040 if (c > 16) c = 16; 3041 3042 for (j = 0; j < c; j++) { 3043 printf("%02x ", data[i + j] & 0xff); 3044 if ((j & 0xf) == 7 && j > 0) 3045 printf(" "); 3046 } 3047 3048 for (; j < 16; j++) 3049 printf(" "); 3050 printf(" "); 3051 3052 for (j = 0; j < c; j++) { 3053 int ch = data[i + j] & 0xff; 3054 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3055 } 3056 3057 printf("\n"); 3058 3059 if (c < 16) 3060 break; 3061 } 3062 } 3063 3064 void 3065 sk_dump_mbuf(struct mbuf *m) 3066 { 3067 int count = m->m_pkthdr.len; 3068 3069 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3070 3071 while (count > 0 && m) { 3072 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3073 m, m->m_data, m->m_len); 3074 sk_dump_bytes(mtod(m, char *), m->m_len); 3075 3076 count -= m->m_len; 3077 m = m->m_next; 3078 } 3079 } 3080 #endif 3081 3082 static int 3083 sk_sysctl_handler(SYSCTLFN_ARGS) 3084 { 3085 int error, t; 3086 struct sysctlnode node; 3087 struct sk_softc *sc; 3088 3089 node = *rnode; 3090 sc = node.sysctl_data; 3091 t = sc->sk_int_mod; 3092 node.sysctl_data = &t; 3093 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3094 if (error || newp == NULL) 3095 return error; 3096 3097 if (t < SK_IM_MIN || t > SK_IM_MAX) 3098 return EINVAL; 3099 3100 /* update the softc with sysctl-changed value, and mark 3101 for hardware update */ 3102 sc->sk_int_mod = t; 3103 sc->sk_int_mod_pending = 1; 3104 return 0; 3105 } 3106 3107 /* 3108 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3109 * set up in skc_attach() 3110 */ 3111 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3112 { 3113 int rc; 3114 const struct sysctlnode *node; 3115 3116 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3117 0, CTLTYPE_NODE, "sk", 3118 SYSCTL_DESCR("sk interface controls"), 3119 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3120 goto err; 3121 } 3122 3123 sk_root_num = node->sysctl_num; 3124 return; 3125 3126 err: 3127 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3128 } 3129
Indexes created Tue Sep 23 23:09:58 GMT 2025