if_sk.c revision 1.92
1 /* $NetBSD: if_sk.c,v 1.92 2019/01/08 04:18:50 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.92 2019/01/08 04:18:50 msaitoh Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/sockio.h> 123 #include <sys/mbuf.h> 124 #include <sys/malloc.h> 125 #include <sys/mutex.h> 126 #include <sys/kernel.h> 127 #include <sys/socket.h> 128 #include <sys/device.h> 129 #include <sys/queue.h> 130 #include <sys/callout.h> 131 #include <sys/sysctl.h> 132 #include <sys/endian.h> 133 134 #include <net/if.h> 135 #include <net/if_dl.h> 136 #include <net/if_types.h> 137 138 #include <net/if_media.h> 139 140 #include <net/bpf.h> 141 #include <sys/rndsource.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 #include <dev/mii/brgphyreg.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 #include <dev/pci/pcidevs.h> 150 151 /* #define SK_USEIOSPACE */ 152 153 #include <dev/pci/if_skreg.h> 154 #include <dev/pci/if_skvar.h> 155 156 int skc_probe(device_t, cfdata_t, void *); 157 void skc_attach(device_t, device_t, void *aux); 158 int sk_probe(device_t, cfdata_t, void *); 159 void sk_attach(device_t, device_t, void *aux); 160 int skcprint(void *, const char *); 161 int sk_intr(void *); 162 void sk_intr_bcom(struct sk_if_softc *); 163 void sk_intr_xmac(struct sk_if_softc *); 164 void sk_intr_yukon(struct sk_if_softc *); 165 void sk_rxeof(struct sk_if_softc *); 166 void sk_txeof(struct sk_if_softc *); 167 int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 168 void sk_start(struct ifnet *); 169 int sk_ioctl(struct ifnet *, u_long, void *); 170 int sk_init(struct ifnet *); 171 void sk_init_xmac(struct sk_if_softc *); 172 void sk_init_yukon(struct sk_if_softc *); 173 void sk_stop(struct ifnet *, int); 174 void sk_watchdog(struct ifnet *); 175 void sk_shutdown(void *); 176 int sk_ifmedia_upd(struct ifnet *); 177 void sk_reset(struct sk_softc *); 178 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 179 int sk_alloc_jumbo_mem(struct sk_if_softc *); 180 void sk_free_jumbo_mem(struct sk_if_softc *); 181 void *sk_jalloc(struct sk_if_softc *); 182 void sk_jfree(struct mbuf *, void *, size_t, void *); 183 int sk_init_rx_ring(struct sk_if_softc *); 184 int sk_init_tx_ring(struct sk_if_softc *); 185 uint8_t sk_vpd_readbyte(struct sk_softc *, int); 186 void sk_vpd_read_res(struct sk_softc *, 187 struct vpd_res *, int); 188 void sk_vpd_read(struct sk_softc *); 189 190 void sk_update_int_mod(struct sk_softc *); 191 192 int sk_xmac_miibus_readreg(device_t, int, int); 193 void sk_xmac_miibus_writereg(device_t, int, int, int); 194 void sk_xmac_miibus_statchg(struct ifnet *); 195 196 int sk_marv_miibus_readreg(device_t, int, int); 197 void sk_marv_miibus_writereg(device_t, int, int, int); 198 void sk_marv_miibus_statchg(struct ifnet *); 199 200 uint32_t sk_xmac_hash(void *); 201 uint32_t sk_yukon_hash(void *); 202 void sk_setfilt(struct sk_if_softc *, void *, int); 203 void sk_setmulti(struct sk_if_softc *); 204 void sk_tick(void *); 205 206 static bool skc_suspend(device_t, const pmf_qual_t *); 207 static bool skc_resume(device_t, const pmf_qual_t *); 208 static bool sk_resume(device_t dv, const pmf_qual_t *); 209 210 /* #define SK_DEBUG 2 */ 211 #ifdef SK_DEBUG 212 #define DPRINTF(x) if (skdebug) printf x 213 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 214 int skdebug = SK_DEBUG; 215 216 void sk_dump_txdesc(struct sk_tx_desc *, int); 217 void sk_dump_mbuf(struct mbuf *); 218 void sk_dump_bytes(const char *, int); 219 #else 220 #define DPRINTF(x) 221 #define DPRINTFN(n,x) 222 #endif 223 224 static int sk_sysctl_handler(SYSCTLFN_PROTO); 225 static int sk_root_num; 226 227 /* supported device vendors */ 228 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 229 static const struct sk_product { 230 pci_vendor_id_t sk_vendor; 231 pci_product_id_t sk_product; 232 } sk_products[] = { 233 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 234 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 235 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 236 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 237 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 238 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 239 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 240 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 241 { 0, 0, } 242 }; 243 244 #define SK_LINKSYS_EG1032_SUBID 0x00151737 245 246 static inline uint32_t 247 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 248 { 249 #ifdef SK_USEIOSPACE 250 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 251 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 252 #else 253 return CSR_READ_4(sc, reg); 254 #endif 255 } 256 257 static inline uint16_t 258 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 259 { 260 #ifdef SK_USEIOSPACE 261 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 262 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 263 #else 264 return CSR_READ_2(sc, reg); 265 #endif 266 } 267 268 static inline uint8_t 269 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 270 { 271 #ifdef SK_USEIOSPACE 272 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 273 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 274 #else 275 return CSR_READ_1(sc, reg); 276 #endif 277 } 278 279 static inline void 280 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 281 { 282 #ifdef SK_USEIOSPACE 283 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 284 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 285 #else 286 CSR_WRITE_4(sc, reg, x); 287 #endif 288 } 289 290 static inline void 291 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 292 { 293 #ifdef SK_USEIOSPACE 294 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 295 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 296 #else 297 CSR_WRITE_2(sc, reg, x); 298 #endif 299 } 300 301 static inline void 302 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 303 { 304 #ifdef SK_USEIOSPACE 305 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 306 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 307 #else 308 CSR_WRITE_1(sc, reg, x); 309 #endif 310 } 311 312 /* 313 * The VPD EEPROM contains Vital Product Data, as suggested in 314 * the PCI 2.1 specification. The VPD data is separared into areas 315 * denoted by resource IDs. The SysKonnect VPD contains an ID string 316 * resource (the name of the adapter), a read-only area resource 317 * containing various key/data fields and a read/write area which 318 * can be used to store asset management information or log messages. 319 * We read the ID string and read-only into buffers attached to 320 * the controller softc structure for later use. At the moment, 321 * we only use the ID string during sk_attach(). 322 */ 323 uint8_t 324 sk_vpd_readbyte(struct sk_softc *sc, int addr) 325 { 326 int i; 327 328 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 329 for (i = 0; i < SK_TIMEOUT; i++) { 330 DELAY(1); 331 if (sk_win_read_2(sc, 332 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 333 break; 334 } 335 336 if (i == SK_TIMEOUT) 337 return 0; 338 339 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 340 } 341 342 void 343 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 344 { 345 int i; 346 uint8_t *ptr; 347 348 ptr = (uint8_t *)res; 349 for (i = 0; i < sizeof(struct vpd_res); i++) 350 ptr[i] = sk_vpd_readbyte(sc, i + addr); 351 } 352 353 void 354 sk_vpd_read(struct sk_softc *sc) 355 { 356 int pos = 0, i; 357 struct vpd_res res; 358 359 if (sc->sk_vpd_prodname != NULL) 360 free(sc->sk_vpd_prodname, M_DEVBUF); 361 if (sc->sk_vpd_readonly != NULL) 362 free(sc->sk_vpd_readonly, M_DEVBUF); 363 sc->sk_vpd_prodname = NULL; 364 sc->sk_vpd_readonly = NULL; 365 366 sk_vpd_read_res(sc, &res, pos); 367 368 if (res.vr_id != VPD_RES_ID) { 369 aprint_error_dev(sc->sk_dev, 370 "bad VPD resource id: expected %x got %x\n", 371 VPD_RES_ID, res.vr_id); 372 return; 373 } 374 375 pos += sizeof(res); 376 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 377 if (sc->sk_vpd_prodname == NULL) 378 panic("sk_vpd_read"); 379 for (i = 0; i < res.vr_len; i++) 380 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 381 sc->sk_vpd_prodname[i] = '\0'; 382 pos += i; 383 384 sk_vpd_read_res(sc, &res, pos); 385 386 if (res.vr_id != VPD_RES_READ) { 387 aprint_error_dev(sc->sk_dev, 388 "bad VPD resource id: expected %x got %x\n", 389 VPD_RES_READ, res.vr_id); 390 return; 391 } 392 393 pos += sizeof(res); 394 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 395 if (sc->sk_vpd_readonly == NULL) 396 panic("sk_vpd_read"); 397 for (i = 0; i < res.vr_len ; i++) 398 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 399 } 400 401 int 402 sk_xmac_miibus_readreg(device_t dev, int phy, int reg) 403 { 404 struct sk_if_softc *sc_if = device_private(dev); 405 int i; 406 407 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 408 409 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 410 return 0; 411 412 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 413 SK_XM_READ_2(sc_if, XM_PHY_DATA); 414 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 415 for (i = 0; i < SK_TIMEOUT; i++) { 416 DELAY(1); 417 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 418 XM_MMUCMD_PHYDATARDY) 419 break; 420 } 421 422 if (i == SK_TIMEOUT) { 423 aprint_error_dev(sc_if->sk_dev, 424 "phy failed to come ready\n"); 425 return 0; 426 } 427 } 428 DELAY(1); 429 return SK_XM_READ_2(sc_if, XM_PHY_DATA); 430 } 431 432 void 433 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, int val) 434 { 435 struct sk_if_softc *sc_if = device_private(dev); 436 int i; 437 438 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 439 440 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 441 for (i = 0; i < SK_TIMEOUT; i++) { 442 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 443 break; 444 } 445 446 if (i == SK_TIMEOUT) { 447 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 448 return; 449 } 450 451 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 452 for (i = 0; i < SK_TIMEOUT; i++) { 453 DELAY(1); 454 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 455 break; 456 } 457 458 if (i == SK_TIMEOUT) 459 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 460 } 461 462 void 463 sk_xmac_miibus_statchg(struct ifnet *ifp) 464 { 465 struct sk_if_softc *sc_if = ifp->if_softc; 466 struct mii_data *mii = &sc_if->sk_mii; 467 468 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 469 470 /* 471 * If this is a GMII PHY, manually set the XMAC's 472 * duplex mode accordingly. 473 */ 474 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 475 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 476 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 477 else 478 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 479 } 480 } 481 482 int 483 sk_marv_miibus_readreg(device_t dev, int phy, int reg) 484 { 485 struct sk_if_softc *sc_if = device_private(dev); 486 uint16_t val; 487 int i; 488 489 if (phy != 0 || 490 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 491 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 492 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 493 phy, reg)); 494 return 0; 495 } 496 497 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 498 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 499 500 for (i = 0; i < SK_TIMEOUT; i++) { 501 DELAY(1); 502 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 503 if (val & YU_SMICR_READ_VALID) 504 break; 505 } 506 507 if (i == SK_TIMEOUT) { 508 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 509 return 0; 510 } 511 512 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 513 SK_TIMEOUT)); 514 515 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 516 517 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 518 phy, reg, val)); 519 520 return val; 521 } 522 523 void 524 sk_marv_miibus_writereg(device_t dev, int phy, int reg, int val) 525 { 526 struct sk_if_softc *sc_if = device_private(dev); 527 int i; 528 529 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 530 phy, reg, val)); 531 532 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 533 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 534 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 535 536 for (i = 0; i < SK_TIMEOUT; i++) { 537 DELAY(1); 538 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 539 break; 540 } 541 542 if (i == SK_TIMEOUT) 543 printf("%s: phy write timed out\n", 544 device_xname(sc_if->sk_dev)); 545 } 546 547 void 548 sk_marv_miibus_statchg(struct ifnet *ifp) 549 { 550 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 551 SK_YU_READ_2(((struct sk_if_softc *)ifp->if_softc), 552 YUKON_GPCR))); 553 } 554 555 uint32_t 556 sk_xmac_hash(void *addr) 557 { 558 uint32_t crc; 559 560 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 561 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 562 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 563 return crc; 564 } 565 566 uint32_t 567 sk_yukon_hash(void *addr) 568 { 569 uint32_t crc; 570 571 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 572 crc &= ((1 << SK_HASH_BITS) - 1); 573 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 574 return crc; 575 } 576 577 void 578 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 579 { 580 char *addr = addrv; 581 int base = XM_RXFILT_ENTRY(slot); 582 583 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0])); 584 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2])); 585 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4])); 586 } 587 588 void 589 sk_setmulti(struct sk_if_softc *sc_if) 590 { 591 struct sk_softc *sc = sc_if->sk_softc; 592 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 593 uint32_t hashes[2] = { 0, 0 }; 594 int h = 0, i; 595 struct ethercom *ec = &sc_if->sk_ethercom; 596 struct ether_multi *enm; 597 struct ether_multistep step; 598 uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 599 600 /* First, zot all the existing filters. */ 601 switch (sc->sk_type) { 602 case SK_GENESIS: 603 for (i = 1; i < XM_RXFILT_MAX; i++) 604 sk_setfilt(sc_if, (void *)&dummy, i); 605 606 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 607 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 608 break; 609 case SK_YUKON: 610 case SK_YUKON_LITE: 611 case SK_YUKON_LP: 612 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 613 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 614 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 615 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 616 break; 617 } 618 619 /* Now program new ones. */ 620 allmulti: 621 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 622 hashes[0] = 0xFFFFFFFF; 623 hashes[1] = 0xFFFFFFFF; 624 } else { 625 i = 1; 626 /* First find the tail of the list. */ 627 ETHER_FIRST_MULTI(step, ec, enm); 628 while (enm != NULL) { 629 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 630 ETHER_ADDR_LEN)) { 631 ifp->if_flags |= IFF_ALLMULTI; 632 goto allmulti; 633 } 634 DPRINTFN(2,("multicast address %s\n", 635 ether_sprintf(enm->enm_addrlo))); 636 /* 637 * Program the first XM_RXFILT_MAX multicast groups 638 * into the perfect filter. For all others, 639 * use the hash table. 640 */ 641 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 642 sk_setfilt(sc_if, enm->enm_addrlo, i); 643 i++; 644 } 645 else { 646 switch (sc->sk_type) { 647 case SK_GENESIS: 648 h = sk_xmac_hash(enm->enm_addrlo); 649 break; 650 case SK_YUKON: 651 case SK_YUKON_LITE: 652 case SK_YUKON_LP: 653 h = sk_yukon_hash(enm->enm_addrlo); 654 break; 655 } 656 if (h < 32) 657 hashes[0] |= (1 << h); 658 else 659 hashes[1] |= (1 << (h - 32)); 660 } 661 662 ETHER_NEXT_MULTI(step, enm); 663 } 664 } 665 666 switch (sc->sk_type) { 667 case SK_GENESIS: 668 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 669 XM_MODE_RX_USE_PERFECT); 670 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 671 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 672 break; 673 case SK_YUKON: 674 case SK_YUKON_LITE: 675 case SK_YUKON_LP: 676 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 677 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 678 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 679 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 680 break; 681 } 682 } 683 684 int 685 sk_init_rx_ring(struct sk_if_softc *sc_if) 686 { 687 struct sk_chain_data *cd = &sc_if->sk_cdata; 688 struct sk_ring_data *rd = sc_if->sk_rdata; 689 int i; 690 691 memset((char *)rd->sk_rx_ring, 0, 692 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 693 694 for (i = 0; i < SK_RX_RING_CNT; i++) { 695 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 696 if (i == (SK_RX_RING_CNT - 1)) { 697 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 698 rd->sk_rx_ring[i].sk_next = 699 htole32(SK_RX_RING_ADDR(sc_if, 0)); 700 } else { 701 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 702 rd->sk_rx_ring[i].sk_next = 703 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 704 } 705 } 706 707 for (i = 0; i < SK_RX_RING_CNT; i++) { 708 if (sk_newbuf(sc_if, i, NULL, 709 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 710 aprint_error_dev(sc_if->sk_dev, 711 "failed alloc of %dth mbuf\n", i); 712 return ENOBUFS; 713 } 714 } 715 sc_if->sk_cdata.sk_rx_prod = 0; 716 sc_if->sk_cdata.sk_rx_cons = 0; 717 718 return 0; 719 } 720 721 int 722 sk_init_tx_ring(struct sk_if_softc *sc_if) 723 { 724 struct sk_chain_data *cd = &sc_if->sk_cdata; 725 struct sk_ring_data *rd = sc_if->sk_rdata; 726 int i; 727 728 memset(sc_if->sk_rdata->sk_tx_ring, 0, 729 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 730 731 for (i = 0; i < SK_TX_RING_CNT; i++) { 732 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 733 if (i == (SK_TX_RING_CNT - 1)) { 734 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 735 rd->sk_tx_ring[i].sk_next = 736 htole32(SK_TX_RING_ADDR(sc_if, 0)); 737 } else { 738 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 739 rd->sk_tx_ring[i].sk_next = 740 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 741 } 742 } 743 744 sc_if->sk_cdata.sk_tx_prod = 0; 745 sc_if->sk_cdata.sk_tx_cons = 0; 746 sc_if->sk_cdata.sk_tx_cnt = 0; 747 748 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 749 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 750 751 return 0; 752 } 753 754 int 755 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 756 bus_dmamap_t dmamap) 757 { 758 struct mbuf *m_new = NULL; 759 struct sk_chain *c; 760 struct sk_rx_desc *r; 761 762 if (m == NULL) { 763 void *buf = NULL; 764 765 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 766 if (m_new == NULL) { 767 aprint_error_dev(sc_if->sk_dev, 768 "no memory for rx list -- packet dropped!\n"); 769 return ENOBUFS; 770 } 771 772 /* Allocate the jumbo buffer */ 773 buf = sk_jalloc(sc_if); 774 if (buf == NULL) { 775 m_freem(m_new); 776 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 777 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 778 return ENOBUFS; 779 } 780 781 /* Attach the buffer to the mbuf */ 782 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 783 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 784 785 } else { 786 /* 787 * We're re-using a previously allocated mbuf; 788 * be sure to re-init pointers and lengths to 789 * default values. 790 */ 791 m_new = m; 792 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 793 m_new->m_data = m_new->m_ext.ext_buf; 794 } 795 m_adj(m_new, ETHER_ALIGN); 796 797 c = &sc_if->sk_cdata.sk_rx_chain[i]; 798 r = c->sk_desc; 799 c->sk_mbuf = m_new; 800 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 801 (((vaddr_t)m_new->m_data 802 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 803 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 804 805 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 806 807 return 0; 808 } 809 810 /* 811 * Memory management for jumbo frames. 812 */ 813 814 int 815 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 816 { 817 struct sk_softc *sc = sc_if->sk_softc; 818 char *ptr, *kva; 819 bus_dma_segment_t seg; 820 int i, rseg, state, error; 821 struct sk_jpool_entry *entry; 822 823 state = error = 0; 824 825 /* Grab a big chunk o' storage. */ 826 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 827 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 828 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 829 return ENOBUFS; 830 } 831 832 state = 1; 833 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 834 BUS_DMA_NOWAIT)) { 835 aprint_error_dev(sc->sk_dev, 836 "can't map dma buffers (%d bytes)\n", 837 SK_JMEM); 838 error = ENOBUFS; 839 goto out; 840 } 841 842 state = 2; 843 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 844 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 845 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 846 error = ENOBUFS; 847 goto out; 848 } 849 850 state = 3; 851 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 852 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 853 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 854 error = ENOBUFS; 855 goto out; 856 } 857 858 state = 4; 859 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 860 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 861 862 LIST_INIT(&sc_if->sk_jfree_listhead); 863 LIST_INIT(&sc_if->sk_jinuse_listhead); 864 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 865 866 /* 867 * Now divide it up into 9K pieces and save the addresses 868 * in an array. 869 */ 870 ptr = sc_if->sk_cdata.sk_jumbo_buf; 871 for (i = 0; i < SK_JSLOTS; i++) { 872 sc_if->sk_cdata.sk_jslots[i] = ptr; 873 ptr += SK_JLEN; 874 entry = malloc(sizeof(struct sk_jpool_entry), 875 M_DEVBUF, M_NOWAIT); 876 if (entry == NULL) { 877 aprint_error_dev(sc->sk_dev, 878 "no memory for jumbo buffer queue!\n"); 879 error = ENOBUFS; 880 goto out; 881 } 882 entry->slot = i; 883 if (i) 884 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 885 entry, jpool_entries); 886 else 887 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 888 entry, jpool_entries); 889 } 890 out: 891 if (error != 0) { 892 switch (state) { 893 case 4: 894 bus_dmamap_unload(sc->sc_dmatag, 895 sc_if->sk_cdata.sk_rx_jumbo_map); 896 case 3: 897 bus_dmamap_destroy(sc->sc_dmatag, 898 sc_if->sk_cdata.sk_rx_jumbo_map); 899 case 2: 900 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 901 case 1: 902 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 903 break; 904 default: 905 break; 906 } 907 } 908 909 return error; 910 } 911 912 /* 913 * Allocate a jumbo buffer. 914 */ 915 void * 916 sk_jalloc(struct sk_if_softc *sc_if) 917 { 918 struct sk_jpool_entry *entry; 919 920 mutex_enter(&sc_if->sk_jpool_mtx); 921 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 922 923 if (entry == NULL) { 924 mutex_exit(&sc_if->sk_jpool_mtx); 925 return NULL; 926 } 927 928 LIST_REMOVE(entry, jpool_entries); 929 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 930 mutex_exit(&sc_if->sk_jpool_mtx); 931 return sc_if->sk_cdata.sk_jslots[entry->slot]; 932 } 933 934 /* 935 * Release a jumbo buffer. 936 */ 937 void 938 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 939 { 940 struct sk_jpool_entry *entry; 941 struct sk_if_softc *sc; 942 int i; 943 944 /* Extract the softc struct pointer. */ 945 sc = (struct sk_if_softc *)arg; 946 947 if (sc == NULL) 948 panic("sk_jfree: can't find softc pointer!"); 949 950 /* calculate the slot this buffer belongs to */ 951 952 i = ((vaddr_t)buf 953 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 954 955 if ((i < 0) || (i >= SK_JSLOTS)) 956 panic("sk_jfree: asked to free buffer that we don't manage!"); 957 958 mutex_enter(&sc->sk_jpool_mtx); 959 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 960 if (entry == NULL) 961 panic("sk_jfree: buffer not in use!"); 962 entry->slot = i; 963 LIST_REMOVE(entry, jpool_entries); 964 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 965 mutex_exit(&sc->sk_jpool_mtx); 966 967 if (__predict_true(m != NULL)) 968 pool_cache_put(mb_cache, m); 969 } 970 971 /* 972 * Set media options. 973 */ 974 int 975 sk_ifmedia_upd(struct ifnet *ifp) 976 { 977 struct sk_if_softc *sc_if = ifp->if_softc; 978 int rc; 979 980 (void) sk_init(ifp); 981 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 982 return 0; 983 return rc; 984 } 985 986 static void 987 sk_promisc(struct sk_if_softc *sc_if, int on) 988 { 989 struct sk_softc *sc = sc_if->sk_softc; 990 switch (sc->sk_type) { 991 case SK_GENESIS: 992 if (on) 993 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 994 else 995 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 996 break; 997 case SK_YUKON: 998 case SK_YUKON_LITE: 999 case SK_YUKON_LP: 1000 if (on) 1001 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1002 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1003 else 1004 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1005 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1006 break; 1007 default: 1008 aprint_error_dev(sc_if->sk_dev, "Can't set promisc for %d\n", 1009 sc->sk_type); 1010 break; 1011 } 1012 } 1013 1014 int 1015 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 1016 { 1017 struct sk_if_softc *sc_if = ifp->if_softc; 1018 int s, error = 0; 1019 1020 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1021 1022 s = splnet(); 1023 1024 switch (command) { 1025 1026 case SIOCSIFFLAGS: 1027 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1028 if ((error = ifioctl_common(ifp, command, data)) != 0) 1029 break; 1030 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1031 case IFF_RUNNING: 1032 sk_stop(ifp, 1); 1033 break; 1034 case IFF_UP: 1035 sk_init(ifp); 1036 break; 1037 case IFF_UP | IFF_RUNNING: 1038 if ((ifp->if_flags ^ sc_if->sk_if_flags) == IFF_PROMISC) { 1039 sk_promisc(sc_if, ifp->if_flags & IFF_PROMISC); 1040 sk_setmulti(sc_if); 1041 } else 1042 sk_init(ifp); 1043 break; 1044 } 1045 sc_if->sk_if_flags = ifp->if_flags; 1046 error = 0; 1047 break; 1048 1049 default: 1050 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1051 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1052 break; 1053 1054 error = 0; 1055 1056 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1057 ; 1058 else if (ifp->if_flags & IFF_RUNNING) { 1059 sk_setmulti(sc_if); 1060 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1061 } 1062 break; 1063 } 1064 1065 splx(s); 1066 return error; 1067 } 1068 1069 void 1070 sk_update_int_mod(struct sk_softc *sc) 1071 { 1072 uint32_t imtimer_ticks; 1073 1074 /* 1075 * Configure interrupt moderation. The moderation timer 1076 * defers interrupts specified in the interrupt moderation 1077 * timer mask based on the timeout specified in the interrupt 1078 * moderation timer init register. Each bit in the timer 1079 * register represents one tick, so to specify a timeout in 1080 * microseconds, we have to multiply by the correct number of 1081 * ticks-per-microsecond. 1082 */ 1083 switch (sc->sk_type) { 1084 case SK_GENESIS: 1085 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1086 break; 1087 case SK_YUKON_EC: 1088 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1089 break; 1090 default: 1091 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1092 } 1093 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1094 sc->sk_int_mod); 1095 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1096 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1097 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1098 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1099 sc->sk_int_mod_pending = 0; 1100 } 1101 1102 /* 1103 * Lookup: Check the PCI vendor and device, and return a pointer to 1104 * The structure if the IDs match against our list. 1105 */ 1106 1107 static const struct sk_product * 1108 sk_lookup(const struct pci_attach_args *pa) 1109 { 1110 const struct sk_product *psk; 1111 1112 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1113 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1114 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1115 return psk; 1116 } 1117 return NULL; 1118 } 1119 1120 /* 1121 * Probe for a SysKonnect GEnesis chip. 1122 */ 1123 1124 int 1125 skc_probe(device_t parent, cfdata_t match, void *aux) 1126 { 1127 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1128 const struct sk_product *psk; 1129 pcireg_t subid; 1130 1131 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1132 1133 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1134 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1135 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1136 subid == SK_LINKSYS_EG1032_SUBID) 1137 return 1; 1138 1139 if ((psk = sk_lookup(pa))) { 1140 return 1; 1141 } 1142 return 0; 1143 } 1144 1145 /* 1146 * Force the GEnesis into reset, then bring it out of reset. 1147 */ 1148 void sk_reset(struct sk_softc *sc) 1149 { 1150 DPRINTFN(2, ("sk_reset\n")); 1151 1152 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1153 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1154 if (SK_YUKON_FAMILY(sc->sk_type)) 1155 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1156 1157 DELAY(1000); 1158 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1159 DELAY(2); 1160 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1161 if (SK_YUKON_FAMILY(sc->sk_type)) 1162 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1163 1164 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1165 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1166 CSR_READ_2(sc, SK_LINK_CTRL))); 1167 1168 if (sc->sk_type == SK_GENESIS) { 1169 /* Configure packet arbiter */ 1170 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1171 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1172 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1173 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1174 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1175 } 1176 1177 /* Enable RAM interface */ 1178 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1179 1180 sk_update_int_mod(sc); 1181 } 1182 1183 int 1184 sk_probe(device_t parent, cfdata_t match, void *aux) 1185 { 1186 struct skc_attach_args *sa = aux; 1187 1188 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1189 return 0; 1190 1191 return 1; 1192 } 1193 1194 /* 1195 * Each XMAC chip is attached as a separate logical IP interface. 1196 * Single port cards will have only one logical interface of course. 1197 */ 1198 void 1199 sk_attach(device_t parent, device_t self, void *aux) 1200 { 1201 struct sk_if_softc *sc_if = device_private(self); 1202 struct sk_softc *sc = device_private(parent); 1203 struct skc_attach_args *sa = aux; 1204 struct sk_txmap_entry *entry; 1205 struct ifnet *ifp; 1206 bus_dma_segment_t seg; 1207 bus_dmamap_t dmamap; 1208 prop_data_t data; 1209 void *kva; 1210 int i, rseg; 1211 int mii_flags = 0; 1212 1213 aprint_naive("\n"); 1214 1215 sc_if->sk_dev = self; 1216 sc_if->sk_port = sa->skc_port; 1217 sc_if->sk_softc = sc; 1218 sc->sk_if[sa->skc_port] = sc_if; 1219 1220 if (sa->skc_port == SK_PORT_A) 1221 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1222 if (sa->skc_port == SK_PORT_B) 1223 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1224 1225 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1226 1227 /* 1228 * Get station address for this interface. Note that 1229 * dual port cards actually come with three station 1230 * addresses: one for each port, plus an extra. The 1231 * extra one is used by the SysKonnect driver software 1232 * as a 'virtual' station address for when both ports 1233 * are operating in failover mode. Currently we don't 1234 * use this extra address. 1235 */ 1236 data = prop_dictionary_get(device_properties(self), "mac-address"); 1237 if (data != NULL) { 1238 /* 1239 * Try to get the station address from device properties 1240 * first, in case the ROM is missing. 1241 */ 1242 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 1243 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 1244 memcpy(sc_if->sk_enaddr, prop_data_data_nocopy(data), 1245 ETHER_ADDR_LEN); 1246 } else 1247 for (i = 0; i < ETHER_ADDR_LEN; i++) 1248 sc_if->sk_enaddr[i] = sk_win_read_1(sc, 1249 SK_MAC0_0 + (sa->skc_port * 8) + i); 1250 1251 aprint_normal(": Ethernet address %s\n", 1252 ether_sprintf(sc_if->sk_enaddr)); 1253 1254 /* 1255 * Set up RAM buffer addresses. The NIC will have a certain 1256 * amount of SRAM on it, somewhere between 512K and 2MB. We 1257 * need to divide this up a) between the transmitter and 1258 * receiver and b) between the two XMACs, if this is a 1259 * dual port NIC. Our algorithm is to divide up the memory 1260 * evenly so that everyone gets a fair share. 1261 */ 1262 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1263 uint32_t chunk, val; 1264 1265 chunk = sc->sk_ramsize / 2; 1266 val = sc->sk_rboff / sizeof(uint64_t); 1267 sc_if->sk_rx_ramstart = val; 1268 val += (chunk / sizeof(uint64_t)); 1269 sc_if->sk_rx_ramend = val - 1; 1270 sc_if->sk_tx_ramstart = val; 1271 val += (chunk / sizeof(uint64_t)); 1272 sc_if->sk_tx_ramend = val - 1; 1273 } else { 1274 uint32_t chunk, val; 1275 1276 chunk = sc->sk_ramsize / 4; 1277 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1278 sizeof(uint64_t); 1279 sc_if->sk_rx_ramstart = val; 1280 val += (chunk / sizeof(uint64_t)); 1281 sc_if->sk_rx_ramend = val - 1; 1282 sc_if->sk_tx_ramstart = val; 1283 val += (chunk / sizeof(uint64_t)); 1284 sc_if->sk_tx_ramend = val - 1; 1285 } 1286 1287 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1288 " tx_ramstart=%#x tx_ramend=%#x\n", 1289 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1290 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1291 1292 /* Read and save PHY type and set PHY address */ 1293 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1294 switch (sc_if->sk_phytype) { 1295 case SK_PHYTYPE_XMAC: 1296 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1297 break; 1298 case SK_PHYTYPE_BCOM: 1299 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1300 break; 1301 case SK_PHYTYPE_MARV_COPPER: 1302 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1303 break; 1304 default: 1305 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1306 sc_if->sk_phytype); 1307 return; 1308 } 1309 1310 /* Allocate the descriptor queues. */ 1311 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1312 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1313 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1314 goto fail; 1315 } 1316 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1317 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1318 aprint_error_dev(sc_if->sk_dev, 1319 "can't map dma buffers (%lu bytes)\n", 1320 (u_long) sizeof(struct sk_ring_data)); 1321 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1322 goto fail; 1323 } 1324 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1325 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1326 &sc_if->sk_ring_map)) { 1327 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1328 bus_dmamem_unmap(sc->sc_dmatag, kva, 1329 sizeof(struct sk_ring_data)); 1330 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1331 goto fail; 1332 } 1333 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1334 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1335 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1336 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1337 bus_dmamem_unmap(sc->sc_dmatag, kva, 1338 sizeof(struct sk_ring_data)); 1339 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1340 goto fail; 1341 } 1342 1343 for (i = 0; i < SK_RX_RING_CNT; i++) 1344 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1345 1346 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1347 for (i = 0; i < SK_TX_RING_CNT; i++) { 1348 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1349 1350 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1351 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1352 aprint_error_dev(sc_if->sk_dev, 1353 "Can't create TX dmamap\n"); 1354 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1355 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1356 bus_dmamem_unmap(sc->sc_dmatag, kva, 1357 sizeof(struct sk_ring_data)); 1358 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1359 goto fail; 1360 } 1361 1362 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1363 if (!entry) { 1364 aprint_error_dev(sc_if->sk_dev, 1365 "Can't alloc txmap entry\n"); 1366 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1367 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1368 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1369 bus_dmamem_unmap(sc->sc_dmatag, kva, 1370 sizeof(struct sk_ring_data)); 1371 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1372 goto fail; 1373 } 1374 entry->dmamap = dmamap; 1375 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1376 } 1377 1378 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1379 memset(sc_if->sk_rdata, 0, sizeof(struct sk_ring_data)); 1380 1381 ifp = &sc_if->sk_ethercom.ec_if; 1382 /* Try to allocate memory for jumbo buffers. */ 1383 if (sk_alloc_jumbo_mem(sc_if)) { 1384 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1385 goto fail; 1386 } 1387 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1388 | ETHERCAP_JUMBO_MTU; 1389 1390 ifp->if_softc = sc_if; 1391 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1392 ifp->if_ioctl = sk_ioctl; 1393 ifp->if_start = sk_start; 1394 ifp->if_stop = sk_stop; 1395 ifp->if_init = sk_init; 1396 ifp->if_watchdog = sk_watchdog; 1397 ifp->if_capabilities = 0; 1398 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1399 IFQ_SET_READY(&ifp->if_snd); 1400 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1401 1402 /* 1403 * Do miibus setup. 1404 */ 1405 switch (sc->sk_type) { 1406 case SK_GENESIS: 1407 sk_init_xmac(sc_if); 1408 break; 1409 case SK_YUKON: 1410 case SK_YUKON_LITE: 1411 case SK_YUKON_LP: 1412 sk_init_yukon(sc_if); 1413 break; 1414 default: 1415 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1416 sc->sk_type); 1417 goto fail; 1418 } 1419 1420 DPRINTFN(2, ("sk_attach: 1\n")); 1421 1422 sc_if->sk_mii.mii_ifp = ifp; 1423 switch (sc->sk_type) { 1424 case SK_GENESIS: 1425 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1426 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1427 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1428 break; 1429 case SK_YUKON: 1430 case SK_YUKON_LITE: 1431 case SK_YUKON_LP: 1432 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1433 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1434 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1435 mii_flags = MIIF_DOPAUSE; 1436 break; 1437 } 1438 1439 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1440 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1441 sk_ifmedia_upd, ether_mediastatus); 1442 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1443 MII_OFFSET_ANY, mii_flags); 1444 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1445 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1446 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1447 0, NULL); 1448 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1449 } else 1450 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1451 1452 callout_init(&sc_if->sk_tick_ch, 0); 1453 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1454 1455 DPRINTFN(2, ("sk_attach: 1\n")); 1456 1457 /* 1458 * Call MI attach routines. 1459 */ 1460 if_attach(ifp); 1461 if_deferred_start_init(ifp, NULL); 1462 1463 ether_ifattach(ifp, sc_if->sk_enaddr); 1464 1465 if (sc->rnd_attached++ == 0) { 1466 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1467 RND_TYPE_NET, RND_FLAG_DEFAULT); 1468 } 1469 1470 if (pmf_device_register(self, NULL, sk_resume)) 1471 pmf_class_network_register(self, ifp); 1472 else 1473 aprint_error_dev(self, "couldn't establish power handler\n"); 1474 1475 DPRINTFN(2, ("sk_attach: end\n")); 1476 1477 return; 1478 1479 fail: 1480 sc->sk_if[sa->skc_port] = NULL; 1481 } 1482 1483 int 1484 skcprint(void *aux, const char *pnp) 1485 { 1486 struct skc_attach_args *sa = aux; 1487 1488 if (pnp) 1489 aprint_normal("sk port %c at %s", 1490 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1491 else 1492 aprint_normal(" port %c", 1493 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1494 return UNCONF; 1495 } 1496 1497 /* 1498 * Attach the interface. Allocate softc structures, do ifmedia 1499 * setup and ethernet/BPF attach. 1500 */ 1501 void 1502 skc_attach(device_t parent, device_t self, void *aux) 1503 { 1504 struct sk_softc *sc = device_private(self); 1505 struct pci_attach_args *pa = aux; 1506 struct skc_attach_args skca; 1507 pci_chipset_tag_t pc = pa->pa_pc; 1508 #ifndef SK_USEIOSPACE 1509 pcireg_t memtype; 1510 #endif 1511 pci_intr_handle_t ih; 1512 const char *intrstr = NULL; 1513 bus_addr_t iobase; 1514 bus_size_t iosize; 1515 int rc, sk_nodenum; 1516 uint32_t command; 1517 const char *revstr; 1518 const struct sysctlnode *node; 1519 char intrbuf[PCI_INTRSTR_LEN]; 1520 1521 sc->sk_dev = self; 1522 aprint_naive("\n"); 1523 1524 DPRINTFN(2, ("begin skc_attach\n")); 1525 1526 /* 1527 * Handle power management nonsense. 1528 */ 1529 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1530 1531 if (command == 0x01) { 1532 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1533 if (command & SK_PSTATE_MASK) { 1534 uint32_t xiobase, membase, irq; 1535 1536 /* Save important PCI config data. */ 1537 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1538 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1539 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1540 1541 /* Reset the power state. */ 1542 aprint_normal_dev(sc->sk_dev, 1543 "chip is in D%d power mode -- setting to D0\n", 1544 command & SK_PSTATE_MASK); 1545 command &= 0xFFFFFFFC; 1546 pci_conf_write(pc, pa->pa_tag, 1547 SK_PCI_PWRMGMTCTRL, command); 1548 1549 /* Restore PCI config data. */ 1550 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1551 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1552 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1553 } 1554 } 1555 1556 /* 1557 * The firmware might have configured the interface to revert the 1558 * byte order in all descriptors. Make that undone. 1559 */ 1560 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_OURREG2); 1561 if (command & SK_REG2_REV_DESC) 1562 pci_conf_write(pc, pa->pa_tag, SK_PCI_OURREG2, 1563 command & ~SK_REG2_REV_DESC); 1564 1565 /* 1566 * Map control/status registers. 1567 */ 1568 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1569 command |= PCI_COMMAND_IO_ENABLE | 1570 PCI_COMMAND_MEM_ENABLE | 1571 PCI_COMMAND_MASTER_ENABLE; 1572 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1573 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1574 1575 #ifdef SK_USEIOSPACE 1576 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1577 aprint_error(": failed to enable I/O ports!\n"); 1578 return; 1579 } 1580 /* 1581 * Map control/status registers. 1582 */ 1583 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1584 &sc->sk_btag, &sc->sk_bhandle, 1585 &iobase, &iosize)) { 1586 aprint_error(": can't find i/o space\n"); 1587 return; 1588 } 1589 #else 1590 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1591 aprint_error(": failed to enable memory mapping!\n"); 1592 return; 1593 } 1594 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1595 switch (memtype) { 1596 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1597 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1598 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1599 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1600 &iobase, &iosize) == 0) 1601 break; 1602 default: 1603 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1604 return; 1605 } 1606 1607 DPRINTFN(2, ("skc_attach: iobase=%#" PRIxPADDR ", iosize=%zx\n", 1608 iobase, iosize)); 1609 #endif 1610 sc->sc_dmatag = pa->pa_dmat; 1611 1612 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1613 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1614 1615 /* bail out here if chip is not recognized */ 1616 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1617 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1618 goto fail; 1619 } 1620 if (SK_IS_YUKON2(sc)) { 1621 aprint_error_dev(sc->sk_dev, 1622 "Does not support Yukon2--try msk(4).\n"); 1623 goto fail; 1624 } 1625 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1626 1627 /* Allocate interrupt */ 1628 if (pci_intr_map(pa, &ih)) { 1629 aprint_error(": couldn't map interrupt\n"); 1630 goto fail; 1631 } 1632 1633 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1634 sc->sk_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, sk_intr, sc, 1635 device_xname(sc->sk_dev)); 1636 if (sc->sk_intrhand == NULL) { 1637 aprint_error(": couldn't establish interrupt"); 1638 if (intrstr != NULL) 1639 aprint_error(" at %s", intrstr); 1640 aprint_error("\n"); 1641 goto fail; 1642 } 1643 aprint_normal(": %s\n", intrstr); 1644 1645 /* Reset the adapter. */ 1646 sk_reset(sc); 1647 1648 /* Read and save vital product data from EEPROM. */ 1649 sk_vpd_read(sc); 1650 1651 if (sc->sk_type == SK_GENESIS) { 1652 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1653 /* Read and save RAM size and RAMbuffer offset */ 1654 switch (val) { 1655 case SK_RAMSIZE_512K_64: 1656 sc->sk_ramsize = 0x80000; 1657 sc->sk_rboff = SK_RBOFF_0; 1658 break; 1659 case SK_RAMSIZE_1024K_64: 1660 sc->sk_ramsize = 0x100000; 1661 sc->sk_rboff = SK_RBOFF_80000; 1662 break; 1663 case SK_RAMSIZE_1024K_128: 1664 sc->sk_ramsize = 0x100000; 1665 sc->sk_rboff = SK_RBOFF_0; 1666 break; 1667 case SK_RAMSIZE_2048K_128: 1668 sc->sk_ramsize = 0x200000; 1669 sc->sk_rboff = SK_RBOFF_0; 1670 break; 1671 default: 1672 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1673 val); 1674 goto fail_1; 1675 break; 1676 } 1677 1678 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1679 sc->sk_ramsize, sc->sk_ramsize / 1024, 1680 sc->sk_rboff)); 1681 } else { 1682 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1683 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1684 sc->sk_rboff = SK_RBOFF_0; 1685 1686 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1687 sc->sk_ramsize / 1024, sc->sk_ramsize, 1688 sc->sk_rboff)); 1689 } 1690 1691 /* Read and save physical media type */ 1692 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1693 case SK_PMD_1000BASESX: 1694 sc->sk_pmd = IFM_1000_SX; 1695 break; 1696 case SK_PMD_1000BASELX: 1697 sc->sk_pmd = IFM_1000_LX; 1698 break; 1699 case SK_PMD_1000BASECX: 1700 sc->sk_pmd = IFM_1000_CX; 1701 break; 1702 case SK_PMD_1000BASETX: 1703 case SK_PMD_1000BASETX_ALT: 1704 sc->sk_pmd = IFM_1000_T; 1705 break; 1706 default: 1707 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1708 sk_win_read_1(sc, SK_PMDTYPE)); 1709 goto fail_1; 1710 } 1711 1712 /* determine whether to name it with vpd or just make it up */ 1713 /* Marvell Yukon VPD's can freqently be bogus */ 1714 1715 switch (pa->pa_id) { 1716 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1717 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1718 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1719 case PCI_PRODUCT_3COM_3C940: 1720 case PCI_PRODUCT_DLINK_DGE530T: 1721 case PCI_PRODUCT_DLINK_DGE560T: 1722 case PCI_PRODUCT_DLINK_DGE560T_2: 1723 case PCI_PRODUCT_LINKSYS_EG1032: 1724 case PCI_PRODUCT_LINKSYS_EG1064: 1725 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1726 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1727 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1728 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1729 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1730 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1731 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1732 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1733 sc->sk_name = sc->sk_vpd_prodname; 1734 break; 1735 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1736 /* whoops yukon vpd prodname bears no resemblance to reality */ 1737 switch (sc->sk_type) { 1738 case SK_GENESIS: 1739 sc->sk_name = sc->sk_vpd_prodname; 1740 break; 1741 case SK_YUKON: 1742 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1743 break; 1744 case SK_YUKON_LITE: 1745 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1746 break; 1747 case SK_YUKON_LP: 1748 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1749 break; 1750 default: 1751 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1752 } 1753 1754 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1755 1756 if ( sc->sk_type == SK_YUKON ) { 1757 uint32_t flashaddr; 1758 uint8_t testbyte; 1759 1760 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1761 1762 /* test Flash-Address Register */ 1763 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1764 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1765 1766 if (testbyte != 0) { 1767 /* this is yukon lite Rev. A0 */ 1768 sc->sk_type = SK_YUKON_LITE; 1769 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1770 /* restore Flash-Address Register */ 1771 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1772 } 1773 } 1774 break; 1775 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1776 sc->sk_name = sc->sk_vpd_prodname; 1777 break; 1778 default: 1779 sc->sk_name = "Unknown Marvell"; 1780 } 1781 1782 1783 if ( sc->sk_type == SK_YUKON_LITE ) { 1784 switch (sc->sk_rev) { 1785 case SK_YUKON_LITE_REV_A0: 1786 revstr = "A0"; 1787 break; 1788 case SK_YUKON_LITE_REV_A1: 1789 revstr = "A1"; 1790 break; 1791 case SK_YUKON_LITE_REV_A3: 1792 revstr = "A3"; 1793 break; 1794 default: 1795 revstr = ""; 1796 } 1797 } else { 1798 revstr = ""; 1799 } 1800 1801 /* Announce the product name. */ 1802 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1803 sc->sk_name, revstr, sc->sk_rev); 1804 1805 skca.skc_port = SK_PORT_A; 1806 (void)config_found(sc->sk_dev, &skca, skcprint); 1807 1808 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1809 skca.skc_port = SK_PORT_B; 1810 (void)config_found(sc->sk_dev, &skca, skcprint); 1811 } 1812 1813 /* Turn on the 'driver is loaded' LED. */ 1814 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1815 1816 /* skc sysctl setup */ 1817 1818 sc->sk_int_mod = SK_IM_DEFAULT; 1819 sc->sk_int_mod_pending = 0; 1820 1821 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1822 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1823 SYSCTL_DESCR("skc per-controller controls"), 1824 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1825 CTL_EOL)) != 0) { 1826 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1827 goto fail_1; 1828 } 1829 1830 sk_nodenum = node->sysctl_num; 1831 1832 /* interrupt moderation time in usecs */ 1833 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1834 CTLFLAG_READWRITE, 1835 CTLTYPE_INT, "int_mod", 1836 SYSCTL_DESCR("sk interrupt moderation timer"), 1837 sk_sysctl_handler, 0, (void *)sc, 1838 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1839 CTL_EOL)) != 0) { 1840 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1841 goto fail_1; 1842 } 1843 1844 if (!pmf_device_register(self, skc_suspend, skc_resume)) 1845 aprint_error_dev(self, "couldn't establish power handler\n"); 1846 1847 return; 1848 1849 fail_1: 1850 pci_intr_disestablish(pc, sc->sk_intrhand); 1851 fail: 1852 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1853 } 1854 1855 int 1856 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1857 { 1858 struct sk_softc *sc = sc_if->sk_softc; 1859 struct sk_tx_desc *f = NULL; 1860 uint32_t frag, cur, cnt = 0, sk_ctl; 1861 int i; 1862 struct sk_txmap_entry *entry; 1863 bus_dmamap_t txmap; 1864 1865 DPRINTFN(3, ("sk_encap\n")); 1866 1867 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1868 if (entry == NULL) { 1869 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1870 return ENOBUFS; 1871 } 1872 txmap = entry->dmamap; 1873 1874 cur = frag = *txidx; 1875 1876 #ifdef SK_DEBUG 1877 if (skdebug >= 3) 1878 sk_dump_mbuf(m_head); 1879 #endif 1880 1881 /* 1882 * Start packing the mbufs in this chain into 1883 * the fragment pointers. Stop when we run out 1884 * of fragments or hit the end of the mbuf chain. 1885 */ 1886 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1887 BUS_DMA_NOWAIT)) { 1888 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1889 return ENOBUFS; 1890 } 1891 1892 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1893 1894 /* Sync the DMA map. */ 1895 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1896 BUS_DMASYNC_PREWRITE); 1897 1898 for (i = 0; i < txmap->dm_nsegs; i++) { 1899 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1900 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1901 return ENOBUFS; 1902 } 1903 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1904 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1905 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1906 if (cnt == 0) 1907 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1908 else 1909 sk_ctl |= SK_TXCTL_OWN; 1910 f->sk_ctl = htole32(sk_ctl); 1911 cur = frag; 1912 SK_INC(frag, SK_TX_RING_CNT); 1913 cnt++; 1914 } 1915 1916 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1917 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1918 1919 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1920 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1921 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1922 1923 /* Sync descriptors before handing to chip */ 1924 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1925 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1926 1927 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1928 htole32(SK_TXCTL_OWN); 1929 1930 /* Sync first descriptor to hand it off */ 1931 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1932 1933 sc_if->sk_cdata.sk_tx_cnt += cnt; 1934 1935 #ifdef SK_DEBUG 1936 if (skdebug >= 3) { 1937 struct sk_tx_desc *desc; 1938 uint32_t idx; 1939 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1940 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1941 sk_dump_txdesc(desc, idx); 1942 } 1943 } 1944 #endif 1945 1946 *txidx = frag; 1947 1948 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1949 1950 return 0; 1951 } 1952 1953 void 1954 sk_start(struct ifnet *ifp) 1955 { 1956 struct sk_if_softc *sc_if = ifp->if_softc; 1957 struct sk_softc *sc = sc_if->sk_softc; 1958 struct mbuf *m_head = NULL; 1959 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1960 int pkts = 0; 1961 1962 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1963 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1964 1965 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1966 IFQ_POLL(&ifp->if_snd, m_head); 1967 if (m_head == NULL) 1968 break; 1969 1970 /* 1971 * Pack the data into the transmit ring. If we 1972 * don't have room, set the OACTIVE flag and wait 1973 * for the NIC to drain the ring. 1974 */ 1975 if (sk_encap(sc_if, m_head, &idx)) { 1976 ifp->if_flags |= IFF_OACTIVE; 1977 break; 1978 } 1979 1980 /* now we are committed to transmit the packet */ 1981 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1982 pkts++; 1983 1984 /* 1985 * If there's a BPF listener, bounce a copy of this frame 1986 * to him. 1987 */ 1988 bpf_mtap(ifp, m_head, BPF_D_OUT); 1989 } 1990 if (pkts == 0) 1991 return; 1992 1993 /* Transmit */ 1994 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1995 sc_if->sk_cdata.sk_tx_prod = idx; 1996 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1997 1998 /* Set a timeout in case the chip goes out to lunch. */ 1999 ifp->if_timer = 5; 2000 } 2001 } 2002 2003 2004 void 2005 sk_watchdog(struct ifnet *ifp) 2006 { 2007 struct sk_if_softc *sc_if = ifp->if_softc; 2008 2009 /* 2010 * Reclaim first as there is a possibility of losing Tx completion 2011 * interrupts. 2012 */ 2013 sk_txeof(sc_if); 2014 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2015 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 2016 2017 ifp->if_oerrors++; 2018 2019 sk_init(ifp); 2020 } 2021 } 2022 2023 void 2024 sk_shutdown(void *v) 2025 { 2026 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2027 struct sk_softc *sc = sc_if->sk_softc; 2028 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2029 2030 DPRINTFN(2, ("sk_shutdown\n")); 2031 sk_stop(ifp,1); 2032 2033 /* Turn off the 'driver is loaded' LED. */ 2034 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2035 2036 /* 2037 * Reset the GEnesis controller. Doing this should also 2038 * assert the resets on the attached XMAC(s). 2039 */ 2040 sk_reset(sc); 2041 } 2042 2043 void 2044 sk_rxeof(struct sk_if_softc *sc_if) 2045 { 2046 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2047 struct mbuf *m; 2048 struct sk_chain *cur_rx; 2049 struct sk_rx_desc *cur_desc; 2050 int i, cur, total_len = 0; 2051 uint32_t rxstat, sk_ctl; 2052 bus_dmamap_t dmamap; 2053 2054 i = sc_if->sk_cdata.sk_rx_prod; 2055 2056 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2057 2058 for (;;) { 2059 cur = i; 2060 2061 /* Sync the descriptor */ 2062 SK_CDRXSYNC(sc_if, cur, 2063 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2064 2065 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2066 if (sk_ctl & SK_RXCTL_OWN) { 2067 /* Invalidate the descriptor -- it's not ready yet */ 2068 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2069 sc_if->sk_cdata.sk_rx_prod = i; 2070 break; 2071 } 2072 2073 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2074 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2075 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2076 2077 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2078 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2079 2080 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2081 m = cur_rx->sk_mbuf; 2082 cur_rx->sk_mbuf = NULL; 2083 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2084 2085 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2086 2087 SK_INC(i, SK_RX_RING_CNT); 2088 2089 if (rxstat & XM_RXSTAT_ERRFRAME) { 2090 ifp->if_ierrors++; 2091 sk_newbuf(sc_if, cur, m, dmamap); 2092 continue; 2093 } 2094 2095 /* 2096 * Try to allocate a new jumbo buffer. If that 2097 * fails, copy the packet to mbufs and put the 2098 * jumbo buffer back in the ring so it can be 2099 * re-used. If allocating mbufs fails, then we 2100 * have to drop the packet. 2101 */ 2102 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2103 struct mbuf *m0; 2104 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2105 total_len + ETHER_ALIGN, 0, ifp); 2106 sk_newbuf(sc_if, cur, m, dmamap); 2107 if (m0 == NULL) { 2108 aprint_error_dev(sc_if->sk_dev, "no receive " 2109 "buffers available -- packet dropped!\n"); 2110 ifp->if_ierrors++; 2111 continue; 2112 } 2113 m_adj(m0, ETHER_ALIGN); 2114 m = m0; 2115 } else { 2116 m_set_rcvif(m, ifp); 2117 m->m_pkthdr.len = m->m_len = total_len; 2118 } 2119 2120 /* pass it on. */ 2121 if_percpuq_enqueue(ifp->if_percpuq, m); 2122 } 2123 } 2124 2125 void 2126 sk_txeof(struct sk_if_softc *sc_if) 2127 { 2128 struct sk_softc *sc = sc_if->sk_softc; 2129 struct sk_tx_desc *cur_tx; 2130 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2131 uint32_t idx, sk_ctl; 2132 struct sk_txmap_entry *entry; 2133 2134 DPRINTFN(3, ("sk_txeof\n")); 2135 2136 /* 2137 * Go through our tx ring and free mbufs for those 2138 * frames that have been sent. 2139 */ 2140 idx = sc_if->sk_cdata.sk_tx_cons; 2141 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2142 SK_CDTXSYNC(sc_if, idx, 1, 2143 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2144 2145 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2146 sk_ctl = le32toh(cur_tx->sk_ctl); 2147 #ifdef SK_DEBUG 2148 if (skdebug >= 3) 2149 sk_dump_txdesc(cur_tx, idx); 2150 #endif 2151 if (sk_ctl & SK_TXCTL_OWN) { 2152 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2153 break; 2154 } 2155 if (sk_ctl & SK_TXCTL_LASTFRAG) 2156 ifp->if_opackets++; 2157 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2158 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2159 2160 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2161 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2162 2163 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2164 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2165 2166 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2167 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2168 link); 2169 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2170 } 2171 sc_if->sk_cdata.sk_tx_cnt--; 2172 SK_INC(idx, SK_TX_RING_CNT); 2173 } 2174 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2175 ifp->if_timer = 0; 2176 else /* nudge chip to keep tx ring moving */ 2177 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2178 2179 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2180 ifp->if_flags &= ~IFF_OACTIVE; 2181 2182 sc_if->sk_cdata.sk_tx_cons = idx; 2183 } 2184 2185 void 2186 sk_tick(void *xsc_if) 2187 { 2188 struct sk_if_softc *sc_if = xsc_if; 2189 struct mii_data *mii = &sc_if->sk_mii; 2190 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2191 int i; 2192 2193 DPRINTFN(3, ("sk_tick\n")); 2194 2195 if (!(ifp->if_flags & IFF_UP)) 2196 return; 2197 2198 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2199 sk_intr_bcom(sc_if); 2200 return; 2201 } 2202 2203 /* 2204 * According to SysKonnect, the correct way to verify that 2205 * the link has come back up is to poll bit 0 of the GPIO 2206 * register three times. This pin has the signal from the 2207 * link sync pin connected to it; if we read the same link 2208 * state 3 times in a row, we know the link is up. 2209 */ 2210 for (i = 0; i < 3; i++) { 2211 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2212 break; 2213 } 2214 2215 if (i != 3) { 2216 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2217 return; 2218 } 2219 2220 /* Turn the GP0 interrupt back on. */ 2221 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2222 SK_XM_READ_2(sc_if, XM_ISR); 2223 mii_tick(mii); 2224 if (ifp->if_link_state != LINK_STATE_UP) 2225 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2226 else 2227 callout_stop(&sc_if->sk_tick_ch); 2228 } 2229 2230 void 2231 sk_intr_bcom(struct sk_if_softc *sc_if) 2232 { 2233 struct mii_data *mii = &sc_if->sk_mii; 2234 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2235 int status; 2236 2237 2238 DPRINTFN(3, ("sk_intr_bcom\n")); 2239 2240 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2241 2242 /* 2243 * Read the PHY interrupt register to make sure 2244 * we clear any pending interrupts. 2245 */ 2246 status = sk_xmac_miibus_readreg(sc_if->sk_dev, 2247 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2248 2249 if (!(ifp->if_flags & IFF_RUNNING)) { 2250 sk_init_xmac(sc_if); 2251 return; 2252 } 2253 2254 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2255 int lstat; 2256 lstat = sk_xmac_miibus_readreg(sc_if->sk_dev, 2257 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2258 2259 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2260 (void)mii_mediachg(mii); 2261 /* Turn off the link LED. */ 2262 SK_IF_WRITE_1(sc_if, 0, 2263 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2264 sc_if->sk_link = 0; 2265 } else if (status & BRGPHY_ISR_LNK_CHG) { 2266 sk_xmac_miibus_writereg(sc_if->sk_dev, 2267 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2268 mii_tick(mii); 2269 sc_if->sk_link = 1; 2270 /* Turn on the link LED. */ 2271 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2272 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2273 SK_LINKLED_BLINK_OFF); 2274 mii_pollstat(mii); 2275 } else { 2276 mii_tick(mii); 2277 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2278 } 2279 } 2280 2281 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2282 } 2283 2284 void 2285 sk_intr_xmac(struct sk_if_softc *sc_if) 2286 { 2287 uint16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2288 2289 DPRINTFN(3, ("sk_intr_xmac\n")); 2290 2291 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2292 if (status & XM_ISR_GP0_SET) { 2293 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2294 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2295 } 2296 2297 if (status & XM_ISR_AUTONEG_DONE) { 2298 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2299 } 2300 } 2301 2302 if (status & XM_IMR_TX_UNDERRUN) 2303 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2304 2305 if (status & XM_IMR_RX_OVERRUN) 2306 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2307 } 2308 2309 void 2310 sk_intr_yukon(struct sk_if_softc *sc_if) 2311 { 2312 #ifdef SK_DEBUG 2313 int status; 2314 2315 status = 2316 #endif 2317 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2318 2319 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2320 } 2321 2322 int 2323 sk_intr(void *xsc) 2324 { 2325 struct sk_softc *sc = xsc; 2326 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2327 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2328 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2329 uint32_t status; 2330 int claimed = 0; 2331 2332 if (sc_if0 != NULL) 2333 ifp0 = &sc_if0->sk_ethercom.ec_if; 2334 if (sc_if1 != NULL) 2335 ifp1 = &sc_if1->sk_ethercom.ec_if; 2336 2337 for (;;) { 2338 status = CSR_READ_4(sc, SK_ISSR); 2339 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2340 2341 if (!(status & sc->sk_intrmask)) 2342 break; 2343 2344 claimed = 1; 2345 2346 /* Handle receive interrupts first. */ 2347 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2348 sk_rxeof(sc_if0); 2349 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2350 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2351 } 2352 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2353 sk_rxeof(sc_if1); 2354 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2355 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2356 } 2357 2358 /* Then transmit interrupts. */ 2359 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2360 sk_txeof(sc_if0); 2361 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2362 SK_TXBMU_CLR_IRQ_EOF); 2363 } 2364 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2365 sk_txeof(sc_if1); 2366 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2367 SK_TXBMU_CLR_IRQ_EOF); 2368 } 2369 2370 /* Then MAC interrupts. */ 2371 if (sc_if0 && (status & SK_ISR_MAC1) && 2372 (ifp0->if_flags & IFF_RUNNING)) { 2373 if (sc->sk_type == SK_GENESIS) 2374 sk_intr_xmac(sc_if0); 2375 else 2376 sk_intr_yukon(sc_if0); 2377 } 2378 2379 if (sc_if1 && (status & SK_ISR_MAC2) && 2380 (ifp1->if_flags & IFF_RUNNING)) { 2381 if (sc->sk_type == SK_GENESIS) 2382 sk_intr_xmac(sc_if1); 2383 else 2384 sk_intr_yukon(sc_if1); 2385 2386 } 2387 2388 if (status & SK_ISR_EXTERNAL_REG) { 2389 if (sc_if0 != NULL && 2390 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2391 sk_intr_bcom(sc_if0); 2392 2393 if (sc_if1 != NULL && 2394 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2395 sk_intr_bcom(sc_if1); 2396 } 2397 } 2398 2399 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2400 2401 if (ifp0 != NULL) 2402 if_schedule_deferred_start(ifp0); 2403 if (ifp1 != NULL) 2404 if_schedule_deferred_start(ifp1); 2405 2406 KASSERT(sc->rnd_attached > 0); 2407 rnd_add_uint32(&sc->rnd_source, status); 2408 2409 if (sc->sk_int_mod_pending) 2410 sk_update_int_mod(sc); 2411 2412 return claimed; 2413 } 2414 2415 void 2416 sk_init_xmac(struct sk_if_softc *sc_if) 2417 { 2418 struct sk_softc *sc = sc_if->sk_softc; 2419 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2420 static const struct sk_bcom_hack bhack[] = { 2421 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2422 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2423 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2424 { 0, 0 } }; 2425 2426 DPRINTFN(1, ("sk_init_xmac\n")); 2427 2428 /* Unreset the XMAC. */ 2429 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2430 DELAY(1000); 2431 2432 /* Reset the XMAC's internal state. */ 2433 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2434 2435 /* Save the XMAC II revision */ 2436 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2437 2438 /* 2439 * Perform additional initialization for external PHYs, 2440 * namely for the 1000baseTX cards that use the XMAC's 2441 * GMII mode. 2442 */ 2443 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2444 int i = 0; 2445 uint32_t val; 2446 2447 /* Take PHY out of reset. */ 2448 val = sk_win_read_4(sc, SK_GPIO); 2449 if (sc_if->sk_port == SK_PORT_A) 2450 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2451 else 2452 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2453 sk_win_write_4(sc, SK_GPIO, val); 2454 2455 /* Enable GMII mode on the XMAC. */ 2456 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2457 2458 sk_xmac_miibus_writereg(sc_if->sk_dev, 2459 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2460 DELAY(10000); 2461 sk_xmac_miibus_writereg(sc_if->sk_dev, 2462 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2463 2464 /* 2465 * Early versions of the BCM5400 apparently have 2466 * a bug that requires them to have their reserved 2467 * registers initialized to some magic values. I don't 2468 * know what the numbers do, I'm just the messenger. 2469 */ 2470 if (sk_xmac_miibus_readreg(sc_if->sk_dev, 2471 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2472 while (bhack[i].reg) { 2473 sk_xmac_miibus_writereg(sc_if->sk_dev, 2474 SK_PHYADDR_BCOM, bhack[i].reg, 2475 bhack[i].val); 2476 i++; 2477 } 2478 } 2479 } 2480 2481 /* Set station address */ 2482 SK_XM_WRITE_2(sc_if, XM_PAR0, 2483 *(uint16_t *)(&sc_if->sk_enaddr[0])); 2484 SK_XM_WRITE_2(sc_if, XM_PAR1, 2485 *(uint16_t *)(&sc_if->sk_enaddr[2])); 2486 SK_XM_WRITE_2(sc_if, XM_PAR2, 2487 *(uint16_t *)(&sc_if->sk_enaddr[4])); 2488 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2489 2490 if (ifp->if_flags & IFF_PROMISC) 2491 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2492 else 2493 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2494 2495 if (ifp->if_flags & IFF_BROADCAST) 2496 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2497 else 2498 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2499 2500 /* We don't need the FCS appended to the packet. */ 2501 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2502 2503 /* We want short frames padded to 60 bytes. */ 2504 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2505 2506 /* 2507 * Enable the reception of all error frames. This is is 2508 * a necessary evil due to the design of the XMAC. The 2509 * XMAC's receive FIFO is only 8K in size, however jumbo 2510 * frames can be up to 9000 bytes in length. When bad 2511 * frame filtering is enabled, the XMAC's RX FIFO operates 2512 * in 'store and forward' mode. For this to work, the 2513 * entire frame has to fit into the FIFO, but that means 2514 * that jumbo frames larger than 8192 bytes will be 2515 * truncated. Disabling all bad frame filtering causes 2516 * the RX FIFO to operate in streaming mode, in which 2517 * case the XMAC will start transfering frames out of the 2518 * RX FIFO as soon as the FIFO threshold is reached. 2519 */ 2520 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2521 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2522 XM_MODE_RX_INRANGELEN); 2523 2524 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2525 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2526 else 2527 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2528 2529 /* 2530 * Bump up the transmit threshold. This helps hold off transmit 2531 * underruns when we're blasting traffic from both ports at once. 2532 */ 2533 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2534 2535 /* Set multicast filter */ 2536 sk_setmulti(sc_if); 2537 2538 /* Clear and enable interrupts */ 2539 SK_XM_READ_2(sc_if, XM_ISR); 2540 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2541 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2542 else 2543 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2544 2545 /* Configure MAC arbiter */ 2546 switch (sc_if->sk_xmac_rev) { 2547 case XM_XMAC_REV_B2: 2548 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2549 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2550 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2551 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2552 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2553 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2554 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2555 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2556 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2557 break; 2558 case XM_XMAC_REV_C1: 2559 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2560 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2561 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2562 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2563 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2564 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2565 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2566 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2567 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2568 break; 2569 default: 2570 break; 2571 } 2572 sk_win_write_2(sc, SK_MACARB_CTL, 2573 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2574 2575 sc_if->sk_link = 1; 2576 } 2577 2578 void sk_init_yukon(struct sk_if_softc *sc_if) 2579 { 2580 uint32_t /*mac, */phy; 2581 uint16_t reg; 2582 struct sk_softc *sc; 2583 int i; 2584 2585 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2586 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2587 2588 sc = sc_if->sk_softc; 2589 if (sc->sk_type == SK_YUKON_LITE && 2590 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2591 /* Take PHY out of reset. */ 2592 sk_win_write_4(sc, SK_GPIO, 2593 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2594 } 2595 2596 2597 /* GMAC and GPHY Reset */ 2598 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2599 2600 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2601 2602 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2603 DELAY(1000); 2604 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2605 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2606 DELAY(1000); 2607 2608 2609 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2610 2611 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2612 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2613 2614 switch (sc_if->sk_softc->sk_pmd) { 2615 case IFM_1000_SX: 2616 case IFM_1000_LX: 2617 phy |= SK_GPHY_FIBER; 2618 break; 2619 2620 case IFM_1000_CX: 2621 case IFM_1000_T: 2622 phy |= SK_GPHY_COPPER; 2623 break; 2624 } 2625 2626 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2627 2628 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2629 DELAY(1000); 2630 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2631 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2632 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2633 2634 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2635 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2636 2637 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2638 2639 /* unused read of the interrupt source register */ 2640 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2641 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2642 2643 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2644 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2645 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2646 2647 /* MIB Counter Clear Mode set */ 2648 reg |= YU_PAR_MIB_CLR; 2649 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2650 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2651 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2652 2653 /* MIB Counter Clear Mode clear */ 2654 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2655 reg &= ~YU_PAR_MIB_CLR; 2656 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2657 2658 /* receive control reg */ 2659 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2660 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2661 YU_RCR_CRCR); 2662 2663 /* transmit parameter register */ 2664 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2665 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2666 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2667 2668 /* serial mode register */ 2669 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2670 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2671 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2672 YU_SMR_IPG_DATA(0x1e)); 2673 2674 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2675 /* Setup Yukon's address */ 2676 for (i = 0; i < 3; i++) { 2677 /* Write Source Address 1 (unicast filter) */ 2678 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2679 sc_if->sk_enaddr[i * 2] | 2680 sc_if->sk_enaddr[i * 2 + 1] << 8); 2681 } 2682 2683 for (i = 0; i < 3; i++) { 2684 reg = sk_win_read_2(sc_if->sk_softc, 2685 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2686 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2687 } 2688 2689 /* Set multicast filter */ 2690 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2691 sk_setmulti(sc_if); 2692 2693 /* enable interrupt mask for counter overflows */ 2694 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2695 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2696 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2697 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2698 2699 /* Configure RX MAC FIFO */ 2700 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2701 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2702 2703 /* Configure TX MAC FIFO */ 2704 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2705 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2706 2707 DPRINTFN(6, ("sk_init_yukon: end\n")); 2708 } 2709 2710 /* 2711 * Note that to properly initialize any part of the GEnesis chip, 2712 * you first have to take it out of reset mode. 2713 */ 2714 int 2715 sk_init(struct ifnet *ifp) 2716 { 2717 struct sk_if_softc *sc_if = ifp->if_softc; 2718 struct sk_softc *sc = sc_if->sk_softc; 2719 struct mii_data *mii = &sc_if->sk_mii; 2720 int rc = 0, s; 2721 uint32_t imr, imtimer_ticks; 2722 2723 DPRINTFN(1, ("sk_init\n")); 2724 2725 s = splnet(); 2726 2727 if (ifp->if_flags & IFF_RUNNING) { 2728 splx(s); 2729 return 0; 2730 } 2731 2732 /* Cancel pending I/O and free all RX/TX buffers. */ 2733 sk_stop(ifp,0); 2734 2735 if (sc->sk_type == SK_GENESIS) { 2736 /* Configure LINK_SYNC LED */ 2737 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2738 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2739 SK_LINKLED_LINKSYNC_ON); 2740 2741 /* Configure RX LED */ 2742 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2743 SK_RXLEDCTL_COUNTER_START); 2744 2745 /* Configure TX LED */ 2746 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2747 SK_TXLEDCTL_COUNTER_START); 2748 } 2749 2750 /* Configure I2C registers */ 2751 2752 /* Configure XMAC(s) */ 2753 switch (sc->sk_type) { 2754 case SK_GENESIS: 2755 sk_init_xmac(sc_if); 2756 break; 2757 case SK_YUKON: 2758 case SK_YUKON_LITE: 2759 case SK_YUKON_LP: 2760 sk_init_yukon(sc_if); 2761 break; 2762 } 2763 if ((rc = mii_mediachg(mii)) == ENXIO) 2764 rc = 0; 2765 else if (rc != 0) 2766 goto out; 2767 2768 if (sc->sk_type == SK_GENESIS) { 2769 /* Configure MAC FIFOs */ 2770 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2771 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2772 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2773 2774 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2775 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2776 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2777 } 2778 2779 /* Configure transmit arbiter(s) */ 2780 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2781 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2782 2783 /* Configure RAMbuffers */ 2784 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2785 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2786 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2787 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2788 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2789 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2790 2791 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2792 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2793 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2794 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2795 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2796 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2797 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2798 2799 /* Configure BMUs */ 2800 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2801 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2802 SK_RX_RING_ADDR(sc_if, 0)); 2803 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2804 2805 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2806 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2807 SK_TX_RING_ADDR(sc_if, 0)); 2808 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2809 2810 /* Init descriptors */ 2811 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2812 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2813 "memory for rx buffers\n"); 2814 sk_stop(ifp,0); 2815 splx(s); 2816 return ENOBUFS; 2817 } 2818 2819 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2820 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2821 "memory for tx buffers\n"); 2822 sk_stop(ifp,0); 2823 splx(s); 2824 return ENOBUFS; 2825 } 2826 2827 /* Set interrupt moderation if changed via sysctl. */ 2828 switch (sc->sk_type) { 2829 case SK_GENESIS: 2830 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2831 break; 2832 case SK_YUKON_EC: 2833 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2834 break; 2835 default: 2836 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2837 } 2838 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2839 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2840 sk_win_write_4(sc, SK_IMTIMERINIT, 2841 SK_IM_USECS(sc->sk_int_mod)); 2842 aprint_verbose_dev(sc->sk_dev, 2843 "interrupt moderation is %d us\n", sc->sk_int_mod); 2844 } 2845 2846 /* Configure interrupt handling */ 2847 CSR_READ_4(sc, SK_ISSR); 2848 if (sc_if->sk_port == SK_PORT_A) 2849 sc->sk_intrmask |= SK_INTRS1; 2850 else 2851 sc->sk_intrmask |= SK_INTRS2; 2852 2853 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2854 2855 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2856 2857 /* Start BMUs. */ 2858 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2859 2860 if (sc->sk_type == SK_GENESIS) { 2861 /* Enable XMACs TX and RX state machines */ 2862 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2863 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2864 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2865 } 2866 2867 if (SK_YUKON_FAMILY(sc->sk_type)) { 2868 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2869 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2870 #if 0 2871 /* XXX disable 100Mbps and full duplex mode? */ 2872 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2873 #endif 2874 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2875 } 2876 2877 2878 ifp->if_flags |= IFF_RUNNING; 2879 ifp->if_flags &= ~IFF_OACTIVE; 2880 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2881 2882 out: 2883 splx(s); 2884 return rc; 2885 } 2886 2887 void 2888 sk_stop(struct ifnet *ifp, int disable) 2889 { 2890 struct sk_if_softc *sc_if = ifp->if_softc; 2891 struct sk_softc *sc = sc_if->sk_softc; 2892 int i; 2893 2894 DPRINTFN(1, ("sk_stop\n")); 2895 2896 callout_stop(&sc_if->sk_tick_ch); 2897 2898 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2899 uint32_t val; 2900 2901 /* Put PHY back into reset. */ 2902 val = sk_win_read_4(sc, SK_GPIO); 2903 if (sc_if->sk_port == SK_PORT_A) { 2904 val |= SK_GPIO_DIR0; 2905 val &= ~SK_GPIO_DAT0; 2906 } else { 2907 val |= SK_GPIO_DIR2; 2908 val &= ~SK_GPIO_DAT2; 2909 } 2910 sk_win_write_4(sc, SK_GPIO, val); 2911 } 2912 2913 /* Turn off various components of this interface. */ 2914 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2915 switch (sc->sk_type) { 2916 case SK_GENESIS: 2917 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2918 SK_TXMACCTL_XMAC_RESET); 2919 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2920 break; 2921 case SK_YUKON: 2922 case SK_YUKON_LITE: 2923 case SK_YUKON_LP: 2924 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2925 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2926 break; 2927 } 2928 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2929 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2930 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2931 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2932 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2933 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2934 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2935 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2936 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2937 2938 /* Disable interrupts */ 2939 if (sc_if->sk_port == SK_PORT_A) 2940 sc->sk_intrmask &= ~SK_INTRS1; 2941 else 2942 sc->sk_intrmask &= ~SK_INTRS2; 2943 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2944 2945 SK_XM_READ_2(sc_if, XM_ISR); 2946 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2947 2948 /* Free RX and TX mbufs still in the queues. */ 2949 for (i = 0; i < SK_RX_RING_CNT; i++) { 2950 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2951 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2952 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2953 } 2954 } 2955 2956 for (i = 0; i < SK_TX_RING_CNT; i++) { 2957 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2958 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2959 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2960 } 2961 } 2962 2963 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2964 } 2965 2966 /* Power Management Framework */ 2967 2968 static bool 2969 skc_suspend(device_t dv, const pmf_qual_t *qual) 2970 { 2971 struct sk_softc *sc = device_private(dv); 2972 2973 DPRINTFN(2, ("skc_suspend\n")); 2974 2975 /* Turn off the driver is loaded LED */ 2976 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2977 2978 return true; 2979 } 2980 2981 static bool 2982 skc_resume(device_t dv, const pmf_qual_t *qual) 2983 { 2984 struct sk_softc *sc = device_private(dv); 2985 2986 DPRINTFN(2, ("skc_resume\n")); 2987 2988 sk_reset(sc); 2989 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 2990 2991 return true; 2992 } 2993 2994 static bool 2995 sk_resume(device_t dv, const pmf_qual_t *qual) 2996 { 2997 struct sk_if_softc *sc_if = device_private(dv); 2998 2999 sk_init_yukon(sc_if); 3000 return true; 3001 } 3002 3003 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 3004 skc_probe, skc_attach, NULL, NULL); 3005 3006 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 3007 sk_probe, sk_attach, NULL, NULL); 3008 3009 #ifdef SK_DEBUG 3010 void 3011 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 3012 { 3013 #define DESC_PRINT(X) \ 3014 if (X) \ 3015 printf("txdesc[%d]." #X "=%#x\n", \ 3016 idx, X); 3017 3018 DESC_PRINT(le32toh(desc->sk_ctl)); 3019 DESC_PRINT(le32toh(desc->sk_next)); 3020 DESC_PRINT(le32toh(desc->sk_data_lo)); 3021 DESC_PRINT(le32toh(desc->sk_data_hi)); 3022 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 3023 DESC_PRINT(le16toh(desc->sk_rsvd0)); 3024 DESC_PRINT(le16toh(desc->sk_csum_startval)); 3025 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 3026 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 3027 DESC_PRINT(le16toh(desc->sk_rsvd1)); 3028 #undef PRINT 3029 } 3030 3031 void 3032 sk_dump_bytes(const char *data, int len) 3033 { 3034 int c, i, j; 3035 3036 for (i = 0; i < len; i += 16) { 3037 printf("%08x ", i); 3038 c = len - i; 3039 if (c > 16) c = 16; 3040 3041 for (j = 0; j < c; j++) { 3042 printf("%02x ", data[i + j] & 0xff); 3043 if ((j & 0xf) == 7 && j > 0) 3044 printf(" "); 3045 } 3046 3047 for (; j < 16; j++) 3048 printf(" "); 3049 printf(" "); 3050 3051 for (j = 0; j < c; j++) { 3052 int ch = data[i + j] & 0xff; 3053 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3054 } 3055 3056 printf("\n"); 3057 3058 if (c < 16) 3059 break; 3060 } 3061 } 3062 3063 void 3064 sk_dump_mbuf(struct mbuf *m) 3065 { 3066 int count = m->m_pkthdr.len; 3067 3068 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3069 3070 while (count > 0 && m) { 3071 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3072 m, m->m_data, m->m_len); 3073 sk_dump_bytes(mtod(m, char *), m->m_len); 3074 3075 count -= m->m_len; 3076 m = m->m_next; 3077 } 3078 } 3079 #endif 3080 3081 static int 3082 sk_sysctl_handler(SYSCTLFN_ARGS) 3083 { 3084 int error, t; 3085 struct sysctlnode node; 3086 struct sk_softc *sc; 3087 3088 node = *rnode; 3089 sc = node.sysctl_data; 3090 t = sc->sk_int_mod; 3091 node.sysctl_data = &t; 3092 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3093 if (error || newp == NULL) 3094 return error; 3095 3096 if (t < SK_IM_MIN || t > SK_IM_MAX) 3097 return EINVAL; 3098 3099 /* update the softc with sysctl-changed value, and mark 3100 for hardware update */ 3101 sc->sk_int_mod = t; 3102 sc->sk_int_mod_pending = 1; 3103 return 0; 3104 } 3105 3106 /* 3107 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3108 * set up in skc_attach() 3109 */ 3110 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3111 { 3112 int rc; 3113 const struct sysctlnode *node; 3114 3115 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3116 0, CTLTYPE_NODE, "sk", 3117 SYSCTL_DESCR("sk interface controls"), 3118 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3119 goto err; 3120 } 3121 3122 sk_root_num = node->sysctl_num; 3123 return; 3124 3125 err: 3126 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3127 } 3128
Indexes created Tue Sep 23 07:09:52 GMT 2025