if_sk.c revision 1.93
1 /* $NetBSD: if_sk.c,v 1.93 2019/01/22 03:42:27 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.93 2019/01/22 03:42:27 msaitoh Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/sockio.h> 123 #include <sys/mbuf.h> 124 #include <sys/malloc.h> 125 #include <sys/mutex.h> 126 #include <sys/kernel.h> 127 #include <sys/socket.h> 128 #include <sys/device.h> 129 #include <sys/queue.h> 130 #include <sys/callout.h> 131 #include <sys/sysctl.h> 132 #include <sys/endian.h> 133 134 #include <net/if.h> 135 #include <net/if_dl.h> 136 #include <net/if_types.h> 137 138 #include <net/if_media.h> 139 140 #include <net/bpf.h> 141 #include <sys/rndsource.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 #include <dev/mii/brgphyreg.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 #include <dev/pci/pcidevs.h> 150 151 /* #define SK_USEIOSPACE */ 152 153 #include <dev/pci/if_skreg.h> 154 #include <dev/pci/if_skvar.h> 155 156 int skc_probe(device_t, cfdata_t, void *); 157 void skc_attach(device_t, device_t, void *aux); 158 int sk_probe(device_t, cfdata_t, void *); 159 void sk_attach(device_t, device_t, void *aux); 160 int skcprint(void *, const char *); 161 int sk_intr(void *); 162 void sk_intr_bcom(struct sk_if_softc *); 163 void sk_intr_xmac(struct sk_if_softc *); 164 void sk_intr_yukon(struct sk_if_softc *); 165 void sk_rxeof(struct sk_if_softc *); 166 void sk_txeof(struct sk_if_softc *); 167 int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 168 void sk_start(struct ifnet *); 169 int sk_ioctl(struct ifnet *, u_long, void *); 170 int sk_init(struct ifnet *); 171 void sk_init_xmac(struct sk_if_softc *); 172 void sk_init_yukon(struct sk_if_softc *); 173 void sk_stop(struct ifnet *, int); 174 void sk_watchdog(struct ifnet *); 175 void sk_shutdown(void *); 176 int sk_ifmedia_upd(struct ifnet *); 177 void sk_reset(struct sk_softc *); 178 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 179 int sk_alloc_jumbo_mem(struct sk_if_softc *); 180 void sk_free_jumbo_mem(struct sk_if_softc *); 181 void *sk_jalloc(struct sk_if_softc *); 182 void sk_jfree(struct mbuf *, void *, size_t, void *); 183 int sk_init_rx_ring(struct sk_if_softc *); 184 int sk_init_tx_ring(struct sk_if_softc *); 185 uint8_t sk_vpd_readbyte(struct sk_softc *, int); 186 void sk_vpd_read_res(struct sk_softc *, 187 struct vpd_res *, int); 188 void sk_vpd_read(struct sk_softc *); 189 190 void sk_update_int_mod(struct sk_softc *); 191 192 int sk_xmac_miibus_readreg(device_t, int, int, uint16_t *); 193 int sk_xmac_miibus_writereg(device_t, int, int, uint16_t); 194 void sk_xmac_miibus_statchg(struct ifnet *); 195 196 int sk_marv_miibus_readreg(device_t, int, int, uint16_t *); 197 int sk_marv_miibus_writereg(device_t, int, int, uint16_t); 198 void sk_marv_miibus_statchg(struct ifnet *); 199 200 uint32_t sk_xmac_hash(void *); 201 uint32_t sk_yukon_hash(void *); 202 void sk_setfilt(struct sk_if_softc *, void *, int); 203 void sk_setmulti(struct sk_if_softc *); 204 void sk_tick(void *); 205 206 static bool skc_suspend(device_t, const pmf_qual_t *); 207 static bool skc_resume(device_t, const pmf_qual_t *); 208 static bool sk_resume(device_t dv, const pmf_qual_t *); 209 210 /* #define SK_DEBUG 2 */ 211 #ifdef SK_DEBUG 212 #define DPRINTF(x) if (skdebug) printf x 213 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 214 int skdebug = SK_DEBUG; 215 216 void sk_dump_txdesc(struct sk_tx_desc *, int); 217 void sk_dump_mbuf(struct mbuf *); 218 void sk_dump_bytes(const char *, int); 219 #else 220 #define DPRINTF(x) 221 #define DPRINTFN(n,x) 222 #endif 223 224 static int sk_sysctl_handler(SYSCTLFN_PROTO); 225 static int sk_root_num; 226 227 /* supported device vendors */ 228 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 229 static const struct sk_product { 230 pci_vendor_id_t sk_vendor; 231 pci_product_id_t sk_product; 232 } sk_products[] = { 233 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 234 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 235 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 236 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 237 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 238 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 239 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 240 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 241 { 0, 0, } 242 }; 243 244 #define SK_LINKSYS_EG1032_SUBID 0x00151737 245 246 static inline uint32_t 247 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 248 { 249 #ifdef SK_USEIOSPACE 250 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 251 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 252 #else 253 return CSR_READ_4(sc, reg); 254 #endif 255 } 256 257 static inline uint16_t 258 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 259 { 260 #ifdef SK_USEIOSPACE 261 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 262 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 263 #else 264 return CSR_READ_2(sc, reg); 265 #endif 266 } 267 268 static inline uint8_t 269 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 270 { 271 #ifdef SK_USEIOSPACE 272 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 273 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 274 #else 275 return CSR_READ_1(sc, reg); 276 #endif 277 } 278 279 static inline void 280 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 281 { 282 #ifdef SK_USEIOSPACE 283 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 284 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 285 #else 286 CSR_WRITE_4(sc, reg, x); 287 #endif 288 } 289 290 static inline void 291 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 292 { 293 #ifdef SK_USEIOSPACE 294 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 295 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 296 #else 297 CSR_WRITE_2(sc, reg, x); 298 #endif 299 } 300 301 static inline void 302 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 303 { 304 #ifdef SK_USEIOSPACE 305 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 306 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 307 #else 308 CSR_WRITE_1(sc, reg, x); 309 #endif 310 } 311 312 /* 313 * The VPD EEPROM contains Vital Product Data, as suggested in 314 * the PCI 2.1 specification. The VPD data is separared into areas 315 * denoted by resource IDs. The SysKonnect VPD contains an ID string 316 * resource (the name of the adapter), a read-only area resource 317 * containing various key/data fields and a read/write area which 318 * can be used to store asset management information or log messages. 319 * We read the ID string and read-only into buffers attached to 320 * the controller softc structure for later use. At the moment, 321 * we only use the ID string during sk_attach(). 322 */ 323 uint8_t 324 sk_vpd_readbyte(struct sk_softc *sc, int addr) 325 { 326 int i; 327 328 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 329 for (i = 0; i < SK_TIMEOUT; i++) { 330 DELAY(1); 331 if (sk_win_read_2(sc, 332 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 333 break; 334 } 335 336 if (i == SK_TIMEOUT) 337 return 0; 338 339 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 340 } 341 342 void 343 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 344 { 345 int i; 346 uint8_t *ptr; 347 348 ptr = (uint8_t *)res; 349 for (i = 0; i < sizeof(struct vpd_res); i++) 350 ptr[i] = sk_vpd_readbyte(sc, i + addr); 351 } 352 353 void 354 sk_vpd_read(struct sk_softc *sc) 355 { 356 int pos = 0, i; 357 struct vpd_res res; 358 359 if (sc->sk_vpd_prodname != NULL) 360 free(sc->sk_vpd_prodname, M_DEVBUF); 361 if (sc->sk_vpd_readonly != NULL) 362 free(sc->sk_vpd_readonly, M_DEVBUF); 363 sc->sk_vpd_prodname = NULL; 364 sc->sk_vpd_readonly = NULL; 365 366 sk_vpd_read_res(sc, &res, pos); 367 368 if (res.vr_id != VPD_RES_ID) { 369 aprint_error_dev(sc->sk_dev, 370 "bad VPD resource id: expected %x got %x\n", 371 VPD_RES_ID, res.vr_id); 372 return; 373 } 374 375 pos += sizeof(res); 376 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 377 if (sc->sk_vpd_prodname == NULL) 378 panic("sk_vpd_read"); 379 for (i = 0; i < res.vr_len; i++) 380 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 381 sc->sk_vpd_prodname[i] = '\0'; 382 pos += i; 383 384 sk_vpd_read_res(sc, &res, pos); 385 386 if (res.vr_id != VPD_RES_READ) { 387 aprint_error_dev(sc->sk_dev, 388 "bad VPD resource id: expected %x got %x\n", 389 VPD_RES_READ, res.vr_id); 390 return; 391 } 392 393 pos += sizeof(res); 394 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 395 if (sc->sk_vpd_readonly == NULL) 396 panic("sk_vpd_read"); 397 for (i = 0; i < res.vr_len ; i++) 398 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 399 } 400 401 int 402 sk_xmac_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 403 { 404 struct sk_if_softc *sc_if = device_private(dev); 405 int i; 406 407 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 408 409 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 410 return -1; 411 412 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 413 SK_XM_READ_2(sc_if, XM_PHY_DATA); 414 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 415 for (i = 0; i < SK_TIMEOUT; i++) { 416 DELAY(1); 417 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 418 XM_MMUCMD_PHYDATARDY) 419 break; 420 } 421 422 if (i == SK_TIMEOUT) { 423 aprint_error_dev(sc_if->sk_dev, 424 "phy failed to come ready\n"); 425 return ETIMEDOUT; 426 } 427 } 428 DELAY(1); 429 *val = SK_XM_READ_2(sc_if, XM_PHY_DATA); 430 return 0; 431 } 432 433 int 434 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 435 { 436 struct sk_if_softc *sc_if = device_private(dev); 437 int i; 438 439 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 440 441 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 442 for (i = 0; i < SK_TIMEOUT; i++) { 443 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 444 break; 445 } 446 447 if (i == SK_TIMEOUT) { 448 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 449 return ETIMEDOUT; 450 } 451 452 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 453 for (i = 0; i < SK_TIMEOUT; i++) { 454 DELAY(1); 455 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 456 break; 457 } 458 459 if (i == SK_TIMEOUT) { 460 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 461 return ETIMEDOUT; 462 } 463 464 return 0; 465 } 466 467 void 468 sk_xmac_miibus_statchg(struct ifnet *ifp) 469 { 470 struct sk_if_softc *sc_if = ifp->if_softc; 471 struct mii_data *mii = &sc_if->sk_mii; 472 473 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 474 475 /* 476 * If this is a GMII PHY, manually set the XMAC's 477 * duplex mode accordingly. 478 */ 479 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 480 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 481 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 482 else 483 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 484 } 485 } 486 487 int 488 sk_marv_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 489 { 490 struct sk_if_softc *sc_if = device_private(dev); 491 uint16_t data; 492 int i; 493 494 if (phy != 0 || 495 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 496 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 497 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 498 phy, reg)); 499 return -1; 500 } 501 502 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 503 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 504 505 for (i = 0; i < SK_TIMEOUT; i++) { 506 DELAY(1); 507 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 508 if (data & YU_SMICR_READ_VALID) 509 break; 510 } 511 512 if (i == SK_TIMEOUT) { 513 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 514 return ETIMEDOUT; 515 } 516 517 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 518 SK_TIMEOUT)); 519 520 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 521 522 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 523 phy, reg, *val)); 524 525 return 0; 526 } 527 528 int 529 sk_marv_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 530 { 531 struct sk_if_softc *sc_if = device_private(dev); 532 int i; 533 534 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#hx\n", 535 phy, reg, val)); 536 537 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 538 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 539 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 540 541 for (i = 0; i < SK_TIMEOUT; i++) { 542 DELAY(1); 543 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 544 break; 545 } 546 547 if (i == SK_TIMEOUT) { 548 printf("%s: phy write timed out\n", 549 device_xname(sc_if->sk_dev)); 550 return ETIMEDOUT; 551 } 552 553 return 0; 554 } 555 556 void 557 sk_marv_miibus_statchg(struct ifnet *ifp) 558 { 559 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 560 SK_YU_READ_2(((struct sk_if_softc *)ifp->if_softc), 561 YUKON_GPCR))); 562 } 563 564 uint32_t 565 sk_xmac_hash(void *addr) 566 { 567 uint32_t crc; 568 569 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 570 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 571 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 572 return crc; 573 } 574 575 uint32_t 576 sk_yukon_hash(void *addr) 577 { 578 uint32_t crc; 579 580 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 581 crc &= ((1 << SK_HASH_BITS) - 1); 582 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 583 return crc; 584 } 585 586 void 587 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 588 { 589 char *addr = addrv; 590 int base = XM_RXFILT_ENTRY(slot); 591 592 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0])); 593 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2])); 594 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4])); 595 } 596 597 void 598 sk_setmulti(struct sk_if_softc *sc_if) 599 { 600 struct sk_softc *sc = sc_if->sk_softc; 601 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 602 uint32_t hashes[2] = { 0, 0 }; 603 int h = 0, i; 604 struct ethercom *ec = &sc_if->sk_ethercom; 605 struct ether_multi *enm; 606 struct ether_multistep step; 607 uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 608 609 /* First, zot all the existing filters. */ 610 switch (sc->sk_type) { 611 case SK_GENESIS: 612 for (i = 1; i < XM_RXFILT_MAX; i++) 613 sk_setfilt(sc_if, (void *)&dummy, i); 614 615 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 616 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 617 break; 618 case SK_YUKON: 619 case SK_YUKON_LITE: 620 case SK_YUKON_LP: 621 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 622 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 623 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 624 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 625 break; 626 } 627 628 /* Now program new ones. */ 629 allmulti: 630 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 631 hashes[0] = 0xFFFFFFFF; 632 hashes[1] = 0xFFFFFFFF; 633 } else { 634 i = 1; 635 /* First find the tail of the list. */ 636 ETHER_FIRST_MULTI(step, ec, enm); 637 while (enm != NULL) { 638 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 639 ETHER_ADDR_LEN)) { 640 ifp->if_flags |= IFF_ALLMULTI; 641 goto allmulti; 642 } 643 DPRINTFN(2,("multicast address %s\n", 644 ether_sprintf(enm->enm_addrlo))); 645 /* 646 * Program the first XM_RXFILT_MAX multicast groups 647 * into the perfect filter. For all others, 648 * use the hash table. 649 */ 650 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 651 sk_setfilt(sc_if, enm->enm_addrlo, i); 652 i++; 653 } 654 else { 655 switch (sc->sk_type) { 656 case SK_GENESIS: 657 h = sk_xmac_hash(enm->enm_addrlo); 658 break; 659 case SK_YUKON: 660 case SK_YUKON_LITE: 661 case SK_YUKON_LP: 662 h = sk_yukon_hash(enm->enm_addrlo); 663 break; 664 } 665 if (h < 32) 666 hashes[0] |= (1 << h); 667 else 668 hashes[1] |= (1 << (h - 32)); 669 } 670 671 ETHER_NEXT_MULTI(step, enm); 672 } 673 } 674 675 switch (sc->sk_type) { 676 case SK_GENESIS: 677 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 678 XM_MODE_RX_USE_PERFECT); 679 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 680 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 681 break; 682 case SK_YUKON: 683 case SK_YUKON_LITE: 684 case SK_YUKON_LP: 685 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 686 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 687 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 688 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 689 break; 690 } 691 } 692 693 int 694 sk_init_rx_ring(struct sk_if_softc *sc_if) 695 { 696 struct sk_chain_data *cd = &sc_if->sk_cdata; 697 struct sk_ring_data *rd = sc_if->sk_rdata; 698 int i; 699 700 memset((char *)rd->sk_rx_ring, 0, 701 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 702 703 for (i = 0; i < SK_RX_RING_CNT; i++) { 704 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 705 if (i == (SK_RX_RING_CNT - 1)) { 706 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 707 rd->sk_rx_ring[i].sk_next = 708 htole32(SK_RX_RING_ADDR(sc_if, 0)); 709 } else { 710 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 711 rd->sk_rx_ring[i].sk_next = 712 htole32(SK_RX_RING_ADDR(sc_if,i+1)); 713 } 714 } 715 716 for (i = 0; i < SK_RX_RING_CNT; i++) { 717 if (sk_newbuf(sc_if, i, NULL, 718 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 719 aprint_error_dev(sc_if->sk_dev, 720 "failed alloc of %dth mbuf\n", i); 721 return ENOBUFS; 722 } 723 } 724 sc_if->sk_cdata.sk_rx_prod = 0; 725 sc_if->sk_cdata.sk_rx_cons = 0; 726 727 return 0; 728 } 729 730 int 731 sk_init_tx_ring(struct sk_if_softc *sc_if) 732 { 733 struct sk_chain_data *cd = &sc_if->sk_cdata; 734 struct sk_ring_data *rd = sc_if->sk_rdata; 735 int i; 736 737 memset(sc_if->sk_rdata->sk_tx_ring, 0, 738 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 739 740 for (i = 0; i < SK_TX_RING_CNT; i++) { 741 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 742 if (i == (SK_TX_RING_CNT - 1)) { 743 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 744 rd->sk_tx_ring[i].sk_next = 745 htole32(SK_TX_RING_ADDR(sc_if, 0)); 746 } else { 747 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 748 rd->sk_tx_ring[i].sk_next = 749 htole32(SK_TX_RING_ADDR(sc_if,i+1)); 750 } 751 } 752 753 sc_if->sk_cdata.sk_tx_prod = 0; 754 sc_if->sk_cdata.sk_tx_cons = 0; 755 sc_if->sk_cdata.sk_tx_cnt = 0; 756 757 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 758 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 759 760 return 0; 761 } 762 763 int 764 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 765 bus_dmamap_t dmamap) 766 { 767 struct mbuf *m_new = NULL; 768 struct sk_chain *c; 769 struct sk_rx_desc *r; 770 771 if (m == NULL) { 772 void *buf = NULL; 773 774 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 775 if (m_new == NULL) { 776 aprint_error_dev(sc_if->sk_dev, 777 "no memory for rx list -- packet dropped!\n"); 778 return ENOBUFS; 779 } 780 781 /* Allocate the jumbo buffer */ 782 buf = sk_jalloc(sc_if); 783 if (buf == NULL) { 784 m_freem(m_new); 785 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 786 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 787 return ENOBUFS; 788 } 789 790 /* Attach the buffer to the mbuf */ 791 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 792 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 793 794 } else { 795 /* 796 * We're re-using a previously allocated mbuf; 797 * be sure to re-init pointers and lengths to 798 * default values. 799 */ 800 m_new = m; 801 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 802 m_new->m_data = m_new->m_ext.ext_buf; 803 } 804 m_adj(m_new, ETHER_ALIGN); 805 806 c = &sc_if->sk_cdata.sk_rx_chain[i]; 807 r = c->sk_desc; 808 c->sk_mbuf = m_new; 809 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 810 (((vaddr_t)m_new->m_data 811 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 812 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 813 814 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 815 816 return 0; 817 } 818 819 /* 820 * Memory management for jumbo frames. 821 */ 822 823 int 824 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 825 { 826 struct sk_softc *sc = sc_if->sk_softc; 827 char *ptr, *kva; 828 bus_dma_segment_t seg; 829 int i, rseg, state, error; 830 struct sk_jpool_entry *entry; 831 832 state = error = 0; 833 834 /* Grab a big chunk o' storage. */ 835 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 836 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 837 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 838 return ENOBUFS; 839 } 840 841 state = 1; 842 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 843 BUS_DMA_NOWAIT)) { 844 aprint_error_dev(sc->sk_dev, 845 "can't map dma buffers (%d bytes)\n", 846 SK_JMEM); 847 error = ENOBUFS; 848 goto out; 849 } 850 851 state = 2; 852 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 853 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 854 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 855 error = ENOBUFS; 856 goto out; 857 } 858 859 state = 3; 860 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 861 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 862 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 863 error = ENOBUFS; 864 goto out; 865 } 866 867 state = 4; 868 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 869 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 870 871 LIST_INIT(&sc_if->sk_jfree_listhead); 872 LIST_INIT(&sc_if->sk_jinuse_listhead); 873 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 874 875 /* 876 * Now divide it up into 9K pieces and save the addresses 877 * in an array. 878 */ 879 ptr = sc_if->sk_cdata.sk_jumbo_buf; 880 for (i = 0; i < SK_JSLOTS; i++) { 881 sc_if->sk_cdata.sk_jslots[i] = ptr; 882 ptr += SK_JLEN; 883 entry = malloc(sizeof(struct sk_jpool_entry), 884 M_DEVBUF, M_NOWAIT); 885 if (entry == NULL) { 886 aprint_error_dev(sc->sk_dev, 887 "no memory for jumbo buffer queue!\n"); 888 error = ENOBUFS; 889 goto out; 890 } 891 entry->slot = i; 892 if (i) 893 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 894 entry, jpool_entries); 895 else 896 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 897 entry, jpool_entries); 898 } 899 out: 900 if (error != 0) { 901 switch (state) { 902 case 4: 903 bus_dmamap_unload(sc->sc_dmatag, 904 sc_if->sk_cdata.sk_rx_jumbo_map); 905 case 3: 906 bus_dmamap_destroy(sc->sc_dmatag, 907 sc_if->sk_cdata.sk_rx_jumbo_map); 908 case 2: 909 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 910 case 1: 911 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 912 break; 913 default: 914 break; 915 } 916 } 917 918 return error; 919 } 920 921 /* 922 * Allocate a jumbo buffer. 923 */ 924 void * 925 sk_jalloc(struct sk_if_softc *sc_if) 926 { 927 struct sk_jpool_entry *entry; 928 929 mutex_enter(&sc_if->sk_jpool_mtx); 930 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 931 932 if (entry == NULL) { 933 mutex_exit(&sc_if->sk_jpool_mtx); 934 return NULL; 935 } 936 937 LIST_REMOVE(entry, jpool_entries); 938 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 939 mutex_exit(&sc_if->sk_jpool_mtx); 940 return sc_if->sk_cdata.sk_jslots[entry->slot]; 941 } 942 943 /* 944 * Release a jumbo buffer. 945 */ 946 void 947 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 948 { 949 struct sk_jpool_entry *entry; 950 struct sk_if_softc *sc; 951 int i; 952 953 /* Extract the softc struct pointer. */ 954 sc = (struct sk_if_softc *)arg; 955 956 if (sc == NULL) 957 panic("sk_jfree: can't find softc pointer!"); 958 959 /* calculate the slot this buffer belongs to */ 960 961 i = ((vaddr_t)buf 962 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 963 964 if ((i < 0) || (i >= SK_JSLOTS)) 965 panic("sk_jfree: asked to free buffer that we don't manage!"); 966 967 mutex_enter(&sc->sk_jpool_mtx); 968 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 969 if (entry == NULL) 970 panic("sk_jfree: buffer not in use!"); 971 entry->slot = i; 972 LIST_REMOVE(entry, jpool_entries); 973 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 974 mutex_exit(&sc->sk_jpool_mtx); 975 976 if (__predict_true(m != NULL)) 977 pool_cache_put(mb_cache, m); 978 } 979 980 /* 981 * Set media options. 982 */ 983 int 984 sk_ifmedia_upd(struct ifnet *ifp) 985 { 986 struct sk_if_softc *sc_if = ifp->if_softc; 987 int rc; 988 989 (void) sk_init(ifp); 990 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 991 return 0; 992 return rc; 993 } 994 995 static void 996 sk_promisc(struct sk_if_softc *sc_if, int on) 997 { 998 struct sk_softc *sc = sc_if->sk_softc; 999 switch (sc->sk_type) { 1000 case SK_GENESIS: 1001 if (on) 1002 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1003 else 1004 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1005 break; 1006 case SK_YUKON: 1007 case SK_YUKON_LITE: 1008 case SK_YUKON_LP: 1009 if (on) 1010 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1011 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1012 else 1013 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1014 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1015 break; 1016 default: 1017 aprint_error_dev(sc_if->sk_dev, "Can't set promisc for %d\n", 1018 sc->sk_type); 1019 break; 1020 } 1021 } 1022 1023 int 1024 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 1025 { 1026 struct sk_if_softc *sc_if = ifp->if_softc; 1027 int s, error = 0; 1028 1029 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1030 1031 s = splnet(); 1032 1033 switch (command) { 1034 1035 case SIOCSIFFLAGS: 1036 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1037 if ((error = ifioctl_common(ifp, command, data)) != 0) 1038 break; 1039 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1040 case IFF_RUNNING: 1041 sk_stop(ifp, 1); 1042 break; 1043 case IFF_UP: 1044 sk_init(ifp); 1045 break; 1046 case IFF_UP | IFF_RUNNING: 1047 if ((ifp->if_flags ^ sc_if->sk_if_flags) == IFF_PROMISC) { 1048 sk_promisc(sc_if, ifp->if_flags & IFF_PROMISC); 1049 sk_setmulti(sc_if); 1050 } else 1051 sk_init(ifp); 1052 break; 1053 } 1054 sc_if->sk_if_flags = ifp->if_flags; 1055 error = 0; 1056 break; 1057 1058 default: 1059 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1060 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1061 break; 1062 1063 error = 0; 1064 1065 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1066 ; 1067 else if (ifp->if_flags & IFF_RUNNING) { 1068 sk_setmulti(sc_if); 1069 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1070 } 1071 break; 1072 } 1073 1074 splx(s); 1075 return error; 1076 } 1077 1078 void 1079 sk_update_int_mod(struct sk_softc *sc) 1080 { 1081 uint32_t imtimer_ticks; 1082 1083 /* 1084 * Configure interrupt moderation. The moderation timer 1085 * defers interrupts specified in the interrupt moderation 1086 * timer mask based on the timeout specified in the interrupt 1087 * moderation timer init register. Each bit in the timer 1088 * register represents one tick, so to specify a timeout in 1089 * microseconds, we have to multiply by the correct number of 1090 * ticks-per-microsecond. 1091 */ 1092 switch (sc->sk_type) { 1093 case SK_GENESIS: 1094 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1095 break; 1096 case SK_YUKON_EC: 1097 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1098 break; 1099 default: 1100 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1101 } 1102 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1103 sc->sk_int_mod); 1104 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1105 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1106 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1107 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1108 sc->sk_int_mod_pending = 0; 1109 } 1110 1111 /* 1112 * Lookup: Check the PCI vendor and device, and return a pointer to 1113 * The structure if the IDs match against our list. 1114 */ 1115 1116 static const struct sk_product * 1117 sk_lookup(const struct pci_attach_args *pa) 1118 { 1119 const struct sk_product *psk; 1120 1121 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1122 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1123 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1124 return psk; 1125 } 1126 return NULL; 1127 } 1128 1129 /* 1130 * Probe for a SysKonnect GEnesis chip. 1131 */ 1132 1133 int 1134 skc_probe(device_t parent, cfdata_t match, void *aux) 1135 { 1136 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1137 const struct sk_product *psk; 1138 pcireg_t subid; 1139 1140 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1141 1142 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1143 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1144 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1145 subid == SK_LINKSYS_EG1032_SUBID) 1146 return 1; 1147 1148 if ((psk = sk_lookup(pa))) { 1149 return 1; 1150 } 1151 return 0; 1152 } 1153 1154 /* 1155 * Force the GEnesis into reset, then bring it out of reset. 1156 */ 1157 void sk_reset(struct sk_softc *sc) 1158 { 1159 DPRINTFN(2, ("sk_reset\n")); 1160 1161 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1162 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1163 if (SK_YUKON_FAMILY(sc->sk_type)) 1164 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1165 1166 DELAY(1000); 1167 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1168 DELAY(2); 1169 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1170 if (SK_YUKON_FAMILY(sc->sk_type)) 1171 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1172 1173 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1174 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1175 CSR_READ_2(sc, SK_LINK_CTRL))); 1176 1177 if (sc->sk_type == SK_GENESIS) { 1178 /* Configure packet arbiter */ 1179 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1180 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1181 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1182 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1183 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1184 } 1185 1186 /* Enable RAM interface */ 1187 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1188 1189 sk_update_int_mod(sc); 1190 } 1191 1192 int 1193 sk_probe(device_t parent, cfdata_t match, void *aux) 1194 { 1195 struct skc_attach_args *sa = aux; 1196 1197 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1198 return 0; 1199 1200 return 1; 1201 } 1202 1203 /* 1204 * Each XMAC chip is attached as a separate logical IP interface. 1205 * Single port cards will have only one logical interface of course. 1206 */ 1207 void 1208 sk_attach(device_t parent, device_t self, void *aux) 1209 { 1210 struct sk_if_softc *sc_if = device_private(self); 1211 struct sk_softc *sc = device_private(parent); 1212 struct skc_attach_args *sa = aux; 1213 struct sk_txmap_entry *entry; 1214 struct ifnet *ifp; 1215 bus_dma_segment_t seg; 1216 bus_dmamap_t dmamap; 1217 prop_data_t data; 1218 void *kva; 1219 int i, rseg; 1220 int mii_flags = 0; 1221 1222 aprint_naive("\n"); 1223 1224 sc_if->sk_dev = self; 1225 sc_if->sk_port = sa->skc_port; 1226 sc_if->sk_softc = sc; 1227 sc->sk_if[sa->skc_port] = sc_if; 1228 1229 if (sa->skc_port == SK_PORT_A) 1230 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1231 if (sa->skc_port == SK_PORT_B) 1232 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1233 1234 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1235 1236 /* 1237 * Get station address for this interface. Note that 1238 * dual port cards actually come with three station 1239 * addresses: one for each port, plus an extra. The 1240 * extra one is used by the SysKonnect driver software 1241 * as a 'virtual' station address for when both ports 1242 * are operating in failover mode. Currently we don't 1243 * use this extra address. 1244 */ 1245 data = prop_dictionary_get(device_properties(self), "mac-address"); 1246 if (data != NULL) { 1247 /* 1248 * Try to get the station address from device properties 1249 * first, in case the ROM is missing. 1250 */ 1251 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 1252 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 1253 memcpy(sc_if->sk_enaddr, prop_data_data_nocopy(data), 1254 ETHER_ADDR_LEN); 1255 } else 1256 for (i = 0; i < ETHER_ADDR_LEN; i++) 1257 sc_if->sk_enaddr[i] = sk_win_read_1(sc, 1258 SK_MAC0_0 + (sa->skc_port * 8) + i); 1259 1260 aprint_normal(": Ethernet address %s\n", 1261 ether_sprintf(sc_if->sk_enaddr)); 1262 1263 /* 1264 * Set up RAM buffer addresses. The NIC will have a certain 1265 * amount of SRAM on it, somewhere between 512K and 2MB. We 1266 * need to divide this up a) between the transmitter and 1267 * receiver and b) between the two XMACs, if this is a 1268 * dual port NIC. Our algorithm is to divide up the memory 1269 * evenly so that everyone gets a fair share. 1270 */ 1271 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1272 uint32_t chunk, val; 1273 1274 chunk = sc->sk_ramsize / 2; 1275 val = sc->sk_rboff / sizeof(uint64_t); 1276 sc_if->sk_rx_ramstart = val; 1277 val += (chunk / sizeof(uint64_t)); 1278 sc_if->sk_rx_ramend = val - 1; 1279 sc_if->sk_tx_ramstart = val; 1280 val += (chunk / sizeof(uint64_t)); 1281 sc_if->sk_tx_ramend = val - 1; 1282 } else { 1283 uint32_t chunk, val; 1284 1285 chunk = sc->sk_ramsize / 4; 1286 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1287 sizeof(uint64_t); 1288 sc_if->sk_rx_ramstart = val; 1289 val += (chunk / sizeof(uint64_t)); 1290 sc_if->sk_rx_ramend = val - 1; 1291 sc_if->sk_tx_ramstart = val; 1292 val += (chunk / sizeof(uint64_t)); 1293 sc_if->sk_tx_ramend = val - 1; 1294 } 1295 1296 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1297 " tx_ramstart=%#x tx_ramend=%#x\n", 1298 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1299 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1300 1301 /* Read and save PHY type and set PHY address */ 1302 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1303 switch (sc_if->sk_phytype) { 1304 case SK_PHYTYPE_XMAC: 1305 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1306 break; 1307 case SK_PHYTYPE_BCOM: 1308 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1309 break; 1310 case SK_PHYTYPE_MARV_COPPER: 1311 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1312 break; 1313 default: 1314 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1315 sc_if->sk_phytype); 1316 return; 1317 } 1318 1319 /* Allocate the descriptor queues. */ 1320 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1321 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1322 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1323 goto fail; 1324 } 1325 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1326 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1327 aprint_error_dev(sc_if->sk_dev, 1328 "can't map dma buffers (%lu bytes)\n", 1329 (u_long) sizeof(struct sk_ring_data)); 1330 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1331 goto fail; 1332 } 1333 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1334 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1335 &sc_if->sk_ring_map)) { 1336 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1337 bus_dmamem_unmap(sc->sc_dmatag, kva, 1338 sizeof(struct sk_ring_data)); 1339 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1340 goto fail; 1341 } 1342 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1343 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1344 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1345 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1346 bus_dmamem_unmap(sc->sc_dmatag, kva, 1347 sizeof(struct sk_ring_data)); 1348 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1349 goto fail; 1350 } 1351 1352 for (i = 0; i < SK_RX_RING_CNT; i++) 1353 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1354 1355 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1356 for (i = 0; i < SK_TX_RING_CNT; i++) { 1357 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1358 1359 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1360 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1361 aprint_error_dev(sc_if->sk_dev, 1362 "Can't create TX dmamap\n"); 1363 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1364 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1365 bus_dmamem_unmap(sc->sc_dmatag, kva, 1366 sizeof(struct sk_ring_data)); 1367 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1368 goto fail; 1369 } 1370 1371 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1372 if (!entry) { 1373 aprint_error_dev(sc_if->sk_dev, 1374 "Can't alloc txmap entry\n"); 1375 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1376 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1377 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1378 bus_dmamem_unmap(sc->sc_dmatag, kva, 1379 sizeof(struct sk_ring_data)); 1380 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1381 goto fail; 1382 } 1383 entry->dmamap = dmamap; 1384 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1385 } 1386 1387 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1388 memset(sc_if->sk_rdata, 0, sizeof(struct sk_ring_data)); 1389 1390 ifp = &sc_if->sk_ethercom.ec_if; 1391 /* Try to allocate memory for jumbo buffers. */ 1392 if (sk_alloc_jumbo_mem(sc_if)) { 1393 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1394 goto fail; 1395 } 1396 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1397 | ETHERCAP_JUMBO_MTU; 1398 1399 ifp->if_softc = sc_if; 1400 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1401 ifp->if_ioctl = sk_ioctl; 1402 ifp->if_start = sk_start; 1403 ifp->if_stop = sk_stop; 1404 ifp->if_init = sk_init; 1405 ifp->if_watchdog = sk_watchdog; 1406 ifp->if_capabilities = 0; 1407 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1408 IFQ_SET_READY(&ifp->if_snd); 1409 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1410 1411 /* 1412 * Do miibus setup. 1413 */ 1414 switch (sc->sk_type) { 1415 case SK_GENESIS: 1416 sk_init_xmac(sc_if); 1417 break; 1418 case SK_YUKON: 1419 case SK_YUKON_LITE: 1420 case SK_YUKON_LP: 1421 sk_init_yukon(sc_if); 1422 break; 1423 default: 1424 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1425 sc->sk_type); 1426 goto fail; 1427 } 1428 1429 DPRINTFN(2, ("sk_attach: 1\n")); 1430 1431 sc_if->sk_mii.mii_ifp = ifp; 1432 switch (sc->sk_type) { 1433 case SK_GENESIS: 1434 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1435 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1436 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1437 break; 1438 case SK_YUKON: 1439 case SK_YUKON_LITE: 1440 case SK_YUKON_LP: 1441 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1442 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1443 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1444 mii_flags = MIIF_DOPAUSE; 1445 break; 1446 } 1447 1448 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1449 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1450 sk_ifmedia_upd, ether_mediastatus); 1451 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1452 MII_OFFSET_ANY, mii_flags); 1453 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1454 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1455 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1456 0, NULL); 1457 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1458 } else 1459 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1460 1461 callout_init(&sc_if->sk_tick_ch, 0); 1462 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1463 1464 DPRINTFN(2, ("sk_attach: 1\n")); 1465 1466 /* 1467 * Call MI attach routines. 1468 */ 1469 if_attach(ifp); 1470 if_deferred_start_init(ifp, NULL); 1471 1472 ether_ifattach(ifp, sc_if->sk_enaddr); 1473 1474 if (sc->rnd_attached++ == 0) { 1475 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1476 RND_TYPE_NET, RND_FLAG_DEFAULT); 1477 } 1478 1479 if (pmf_device_register(self, NULL, sk_resume)) 1480 pmf_class_network_register(self, ifp); 1481 else 1482 aprint_error_dev(self, "couldn't establish power handler\n"); 1483 1484 DPRINTFN(2, ("sk_attach: end\n")); 1485 1486 return; 1487 1488 fail: 1489 sc->sk_if[sa->skc_port] = NULL; 1490 } 1491 1492 int 1493 skcprint(void *aux, const char *pnp) 1494 { 1495 struct skc_attach_args *sa = aux; 1496 1497 if (pnp) 1498 aprint_normal("sk port %c at %s", 1499 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1500 else 1501 aprint_normal(" port %c", 1502 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1503 return UNCONF; 1504 } 1505 1506 /* 1507 * Attach the interface. Allocate softc structures, do ifmedia 1508 * setup and ethernet/BPF attach. 1509 */ 1510 void 1511 skc_attach(device_t parent, device_t self, void *aux) 1512 { 1513 struct sk_softc *sc = device_private(self); 1514 struct pci_attach_args *pa = aux; 1515 struct skc_attach_args skca; 1516 pci_chipset_tag_t pc = pa->pa_pc; 1517 #ifndef SK_USEIOSPACE 1518 pcireg_t memtype; 1519 #endif 1520 pci_intr_handle_t ih; 1521 const char *intrstr = NULL; 1522 bus_addr_t iobase; 1523 bus_size_t iosize; 1524 int rc, sk_nodenum; 1525 uint32_t command; 1526 const char *revstr; 1527 const struct sysctlnode *node; 1528 char intrbuf[PCI_INTRSTR_LEN]; 1529 1530 sc->sk_dev = self; 1531 aprint_naive("\n"); 1532 1533 DPRINTFN(2, ("begin skc_attach\n")); 1534 1535 /* 1536 * Handle power management nonsense. 1537 */ 1538 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1539 1540 if (command == 0x01) { 1541 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1542 if (command & SK_PSTATE_MASK) { 1543 uint32_t xiobase, membase, irq; 1544 1545 /* Save important PCI config data. */ 1546 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1547 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1548 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1549 1550 /* Reset the power state. */ 1551 aprint_normal_dev(sc->sk_dev, 1552 "chip is in D%d power mode -- setting to D0\n", 1553 command & SK_PSTATE_MASK); 1554 command &= 0xFFFFFFFC; 1555 pci_conf_write(pc, pa->pa_tag, 1556 SK_PCI_PWRMGMTCTRL, command); 1557 1558 /* Restore PCI config data. */ 1559 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1560 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1561 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1562 } 1563 } 1564 1565 /* 1566 * The firmware might have configured the interface to revert the 1567 * byte order in all descriptors. Make that undone. 1568 */ 1569 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_OURREG2); 1570 if (command & SK_REG2_REV_DESC) 1571 pci_conf_write(pc, pa->pa_tag, SK_PCI_OURREG2, 1572 command & ~SK_REG2_REV_DESC); 1573 1574 /* 1575 * Map control/status registers. 1576 */ 1577 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1578 command |= PCI_COMMAND_IO_ENABLE | 1579 PCI_COMMAND_MEM_ENABLE | 1580 PCI_COMMAND_MASTER_ENABLE; 1581 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1582 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1583 1584 #ifdef SK_USEIOSPACE 1585 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1586 aprint_error(": failed to enable I/O ports!\n"); 1587 return; 1588 } 1589 /* 1590 * Map control/status registers. 1591 */ 1592 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1593 &sc->sk_btag, &sc->sk_bhandle, 1594 &iobase, &iosize)) { 1595 aprint_error(": can't find i/o space\n"); 1596 return; 1597 } 1598 #else 1599 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1600 aprint_error(": failed to enable memory mapping!\n"); 1601 return; 1602 } 1603 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1604 switch (memtype) { 1605 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1606 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1607 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1608 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1609 &iobase, &iosize) == 0) 1610 break; 1611 default: 1612 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1613 return; 1614 } 1615 1616 DPRINTFN(2, ("skc_attach: iobase=%#" PRIxPADDR ", iosize=%zx\n", 1617 iobase, iosize)); 1618 #endif 1619 sc->sc_dmatag = pa->pa_dmat; 1620 1621 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1622 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1623 1624 /* bail out here if chip is not recognized */ 1625 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1626 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1627 goto fail; 1628 } 1629 if (SK_IS_YUKON2(sc)) { 1630 aprint_error_dev(sc->sk_dev, 1631 "Does not support Yukon2--try msk(4).\n"); 1632 goto fail; 1633 } 1634 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1635 1636 /* Allocate interrupt */ 1637 if (pci_intr_map(pa, &ih)) { 1638 aprint_error(": couldn't map interrupt\n"); 1639 goto fail; 1640 } 1641 1642 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1643 sc->sk_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, sk_intr, sc, 1644 device_xname(sc->sk_dev)); 1645 if (sc->sk_intrhand == NULL) { 1646 aprint_error(": couldn't establish interrupt"); 1647 if (intrstr != NULL) 1648 aprint_error(" at %s", intrstr); 1649 aprint_error("\n"); 1650 goto fail; 1651 } 1652 aprint_normal(": %s\n", intrstr); 1653 1654 /* Reset the adapter. */ 1655 sk_reset(sc); 1656 1657 /* Read and save vital product data from EEPROM. */ 1658 sk_vpd_read(sc); 1659 1660 if (sc->sk_type == SK_GENESIS) { 1661 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1662 /* Read and save RAM size and RAMbuffer offset */ 1663 switch (val) { 1664 case SK_RAMSIZE_512K_64: 1665 sc->sk_ramsize = 0x80000; 1666 sc->sk_rboff = SK_RBOFF_0; 1667 break; 1668 case SK_RAMSIZE_1024K_64: 1669 sc->sk_ramsize = 0x100000; 1670 sc->sk_rboff = SK_RBOFF_80000; 1671 break; 1672 case SK_RAMSIZE_1024K_128: 1673 sc->sk_ramsize = 0x100000; 1674 sc->sk_rboff = SK_RBOFF_0; 1675 break; 1676 case SK_RAMSIZE_2048K_128: 1677 sc->sk_ramsize = 0x200000; 1678 sc->sk_rboff = SK_RBOFF_0; 1679 break; 1680 default: 1681 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1682 val); 1683 goto fail_1; 1684 break; 1685 } 1686 1687 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1688 sc->sk_ramsize, sc->sk_ramsize / 1024, 1689 sc->sk_rboff)); 1690 } else { 1691 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1692 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1693 sc->sk_rboff = SK_RBOFF_0; 1694 1695 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1696 sc->sk_ramsize / 1024, sc->sk_ramsize, 1697 sc->sk_rboff)); 1698 } 1699 1700 /* Read and save physical media type */ 1701 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1702 case SK_PMD_1000BASESX: 1703 sc->sk_pmd = IFM_1000_SX; 1704 break; 1705 case SK_PMD_1000BASELX: 1706 sc->sk_pmd = IFM_1000_LX; 1707 break; 1708 case SK_PMD_1000BASECX: 1709 sc->sk_pmd = IFM_1000_CX; 1710 break; 1711 case SK_PMD_1000BASETX: 1712 case SK_PMD_1000BASETX_ALT: 1713 sc->sk_pmd = IFM_1000_T; 1714 break; 1715 default: 1716 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1717 sk_win_read_1(sc, SK_PMDTYPE)); 1718 goto fail_1; 1719 } 1720 1721 /* determine whether to name it with vpd or just make it up */ 1722 /* Marvell Yukon VPD's can freqently be bogus */ 1723 1724 switch (pa->pa_id) { 1725 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1726 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1727 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1728 case PCI_PRODUCT_3COM_3C940: 1729 case PCI_PRODUCT_DLINK_DGE530T: 1730 case PCI_PRODUCT_DLINK_DGE560T: 1731 case PCI_PRODUCT_DLINK_DGE560T_2: 1732 case PCI_PRODUCT_LINKSYS_EG1032: 1733 case PCI_PRODUCT_LINKSYS_EG1064: 1734 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1735 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1736 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1737 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1738 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1739 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1740 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1741 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1742 sc->sk_name = sc->sk_vpd_prodname; 1743 break; 1744 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_SKNET): 1745 /* whoops yukon vpd prodname bears no resemblance to reality */ 1746 switch (sc->sk_type) { 1747 case SK_GENESIS: 1748 sc->sk_name = sc->sk_vpd_prodname; 1749 break; 1750 case SK_YUKON: 1751 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1752 break; 1753 case SK_YUKON_LITE: 1754 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1755 break; 1756 case SK_YUKON_LP: 1757 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1758 break; 1759 default: 1760 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1761 } 1762 1763 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1764 1765 if ( sc->sk_type == SK_YUKON ) { 1766 uint32_t flashaddr; 1767 uint8_t testbyte; 1768 1769 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1770 1771 /* test Flash-Address Register */ 1772 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1773 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1774 1775 if (testbyte != 0) { 1776 /* this is yukon lite Rev. A0 */ 1777 sc->sk_type = SK_YUKON_LITE; 1778 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1779 /* restore Flash-Address Register */ 1780 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1781 } 1782 } 1783 break; 1784 case PCI_ID_CODE(PCI_VENDOR_MARVELL,PCI_PRODUCT_MARVELL_BELKIN): 1785 sc->sk_name = sc->sk_vpd_prodname; 1786 break; 1787 default: 1788 sc->sk_name = "Unknown Marvell"; 1789 } 1790 1791 1792 if ( sc->sk_type == SK_YUKON_LITE ) { 1793 switch (sc->sk_rev) { 1794 case SK_YUKON_LITE_REV_A0: 1795 revstr = "A0"; 1796 break; 1797 case SK_YUKON_LITE_REV_A1: 1798 revstr = "A1"; 1799 break; 1800 case SK_YUKON_LITE_REV_A3: 1801 revstr = "A3"; 1802 break; 1803 default: 1804 revstr = ""; 1805 } 1806 } else { 1807 revstr = ""; 1808 } 1809 1810 /* Announce the product name. */ 1811 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1812 sc->sk_name, revstr, sc->sk_rev); 1813 1814 skca.skc_port = SK_PORT_A; 1815 (void)config_found(sc->sk_dev, &skca, skcprint); 1816 1817 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1818 skca.skc_port = SK_PORT_B; 1819 (void)config_found(sc->sk_dev, &skca, skcprint); 1820 } 1821 1822 /* Turn on the 'driver is loaded' LED. */ 1823 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1824 1825 /* skc sysctl setup */ 1826 1827 sc->sk_int_mod = SK_IM_DEFAULT; 1828 sc->sk_int_mod_pending = 0; 1829 1830 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1831 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1832 SYSCTL_DESCR("skc per-controller controls"), 1833 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1834 CTL_EOL)) != 0) { 1835 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1836 goto fail_1; 1837 } 1838 1839 sk_nodenum = node->sysctl_num; 1840 1841 /* interrupt moderation time in usecs */ 1842 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1843 CTLFLAG_READWRITE, 1844 CTLTYPE_INT, "int_mod", 1845 SYSCTL_DESCR("sk interrupt moderation timer"), 1846 sk_sysctl_handler, 0, (void *)sc, 1847 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1848 CTL_EOL)) != 0) { 1849 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1850 goto fail_1; 1851 } 1852 1853 if (!pmf_device_register(self, skc_suspend, skc_resume)) 1854 aprint_error_dev(self, "couldn't establish power handler\n"); 1855 1856 return; 1857 1858 fail_1: 1859 pci_intr_disestablish(pc, sc->sk_intrhand); 1860 fail: 1861 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1862 } 1863 1864 int 1865 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1866 { 1867 struct sk_softc *sc = sc_if->sk_softc; 1868 struct sk_tx_desc *f = NULL; 1869 uint32_t frag, cur, cnt = 0, sk_ctl; 1870 int i; 1871 struct sk_txmap_entry *entry; 1872 bus_dmamap_t txmap; 1873 1874 DPRINTFN(3, ("sk_encap\n")); 1875 1876 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1877 if (entry == NULL) { 1878 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1879 return ENOBUFS; 1880 } 1881 txmap = entry->dmamap; 1882 1883 cur = frag = *txidx; 1884 1885 #ifdef SK_DEBUG 1886 if (skdebug >= 3) 1887 sk_dump_mbuf(m_head); 1888 #endif 1889 1890 /* 1891 * Start packing the mbufs in this chain into 1892 * the fragment pointers. Stop when we run out 1893 * of fragments or hit the end of the mbuf chain. 1894 */ 1895 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1896 BUS_DMA_NOWAIT)) { 1897 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1898 return ENOBUFS; 1899 } 1900 1901 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1902 1903 /* Sync the DMA map. */ 1904 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1905 BUS_DMASYNC_PREWRITE); 1906 1907 for (i = 0; i < txmap->dm_nsegs; i++) { 1908 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1909 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1910 return ENOBUFS; 1911 } 1912 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1913 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1914 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1915 if (cnt == 0) 1916 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1917 else 1918 sk_ctl |= SK_TXCTL_OWN; 1919 f->sk_ctl = htole32(sk_ctl); 1920 cur = frag; 1921 SK_INC(frag, SK_TX_RING_CNT); 1922 cnt++; 1923 } 1924 1925 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1926 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1927 1928 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1929 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1930 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR); 1931 1932 /* Sync descriptors before handing to chip */ 1933 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1934 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1935 1936 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1937 htole32(SK_TXCTL_OWN); 1938 1939 /* Sync first descriptor to hand it off */ 1940 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1941 1942 sc_if->sk_cdata.sk_tx_cnt += cnt; 1943 1944 #ifdef SK_DEBUG 1945 if (skdebug >= 3) { 1946 struct sk_tx_desc *desc; 1947 uint32_t idx; 1948 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1949 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1950 sk_dump_txdesc(desc, idx); 1951 } 1952 } 1953 #endif 1954 1955 *txidx = frag; 1956 1957 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1958 1959 return 0; 1960 } 1961 1962 void 1963 sk_start(struct ifnet *ifp) 1964 { 1965 struct sk_if_softc *sc_if = ifp->if_softc; 1966 struct sk_softc *sc = sc_if->sk_softc; 1967 struct mbuf *m_head = NULL; 1968 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1969 int pkts = 0; 1970 1971 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1972 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1973 1974 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1975 IFQ_POLL(&ifp->if_snd, m_head); 1976 if (m_head == NULL) 1977 break; 1978 1979 /* 1980 * Pack the data into the transmit ring. If we 1981 * don't have room, set the OACTIVE flag and wait 1982 * for the NIC to drain the ring. 1983 */ 1984 if (sk_encap(sc_if, m_head, &idx)) { 1985 ifp->if_flags |= IFF_OACTIVE; 1986 break; 1987 } 1988 1989 /* now we are committed to transmit the packet */ 1990 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1991 pkts++; 1992 1993 /* 1994 * If there's a BPF listener, bounce a copy of this frame 1995 * to him. 1996 */ 1997 bpf_mtap(ifp, m_head, BPF_D_OUT); 1998 } 1999 if (pkts == 0) 2000 return; 2001 2002 /* Transmit */ 2003 if (idx != sc_if->sk_cdata.sk_tx_prod) { 2004 sc_if->sk_cdata.sk_tx_prod = idx; 2005 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2006 2007 /* Set a timeout in case the chip goes out to lunch. */ 2008 ifp->if_timer = 5; 2009 } 2010 } 2011 2012 2013 void 2014 sk_watchdog(struct ifnet *ifp) 2015 { 2016 struct sk_if_softc *sc_if = ifp->if_softc; 2017 2018 /* 2019 * Reclaim first as there is a possibility of losing Tx completion 2020 * interrupts. 2021 */ 2022 sk_txeof(sc_if); 2023 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2024 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 2025 2026 ifp->if_oerrors++; 2027 2028 sk_init(ifp); 2029 } 2030 } 2031 2032 void 2033 sk_shutdown(void *v) 2034 { 2035 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2036 struct sk_softc *sc = sc_if->sk_softc; 2037 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2038 2039 DPRINTFN(2, ("sk_shutdown\n")); 2040 sk_stop(ifp,1); 2041 2042 /* Turn off the 'driver is loaded' LED. */ 2043 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2044 2045 /* 2046 * Reset the GEnesis controller. Doing this should also 2047 * assert the resets on the attached XMAC(s). 2048 */ 2049 sk_reset(sc); 2050 } 2051 2052 void 2053 sk_rxeof(struct sk_if_softc *sc_if) 2054 { 2055 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2056 struct mbuf *m; 2057 struct sk_chain *cur_rx; 2058 struct sk_rx_desc *cur_desc; 2059 int i, cur, total_len = 0; 2060 uint32_t rxstat, sk_ctl; 2061 bus_dmamap_t dmamap; 2062 2063 i = sc_if->sk_cdata.sk_rx_prod; 2064 2065 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2066 2067 for (;;) { 2068 cur = i; 2069 2070 /* Sync the descriptor */ 2071 SK_CDRXSYNC(sc_if, cur, 2072 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2073 2074 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2075 if (sk_ctl & SK_RXCTL_OWN) { 2076 /* Invalidate the descriptor -- it's not ready yet */ 2077 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2078 sc_if->sk_cdata.sk_rx_prod = i; 2079 break; 2080 } 2081 2082 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2083 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2084 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2085 2086 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2087 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2088 2089 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2090 m = cur_rx->sk_mbuf; 2091 cur_rx->sk_mbuf = NULL; 2092 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2093 2094 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2095 2096 SK_INC(i, SK_RX_RING_CNT); 2097 2098 if (rxstat & XM_RXSTAT_ERRFRAME) { 2099 ifp->if_ierrors++; 2100 sk_newbuf(sc_if, cur, m, dmamap); 2101 continue; 2102 } 2103 2104 /* 2105 * Try to allocate a new jumbo buffer. If that 2106 * fails, copy the packet to mbufs and put the 2107 * jumbo buffer back in the ring so it can be 2108 * re-used. If allocating mbufs fails, then we 2109 * have to drop the packet. 2110 */ 2111 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2112 struct mbuf *m0; 2113 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2114 total_len + ETHER_ALIGN, 0, ifp); 2115 sk_newbuf(sc_if, cur, m, dmamap); 2116 if (m0 == NULL) { 2117 aprint_error_dev(sc_if->sk_dev, "no receive " 2118 "buffers available -- packet dropped!\n"); 2119 ifp->if_ierrors++; 2120 continue; 2121 } 2122 m_adj(m0, ETHER_ALIGN); 2123 m = m0; 2124 } else { 2125 m_set_rcvif(m, ifp); 2126 m->m_pkthdr.len = m->m_len = total_len; 2127 } 2128 2129 /* pass it on. */ 2130 if_percpuq_enqueue(ifp->if_percpuq, m); 2131 } 2132 } 2133 2134 void 2135 sk_txeof(struct sk_if_softc *sc_if) 2136 { 2137 struct sk_softc *sc = sc_if->sk_softc; 2138 struct sk_tx_desc *cur_tx; 2139 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2140 uint32_t idx, sk_ctl; 2141 struct sk_txmap_entry *entry; 2142 2143 DPRINTFN(3, ("sk_txeof\n")); 2144 2145 /* 2146 * Go through our tx ring and free mbufs for those 2147 * frames that have been sent. 2148 */ 2149 idx = sc_if->sk_cdata.sk_tx_cons; 2150 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2151 SK_CDTXSYNC(sc_if, idx, 1, 2152 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2153 2154 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2155 sk_ctl = le32toh(cur_tx->sk_ctl); 2156 #ifdef SK_DEBUG 2157 if (skdebug >= 3) 2158 sk_dump_txdesc(cur_tx, idx); 2159 #endif 2160 if (sk_ctl & SK_TXCTL_OWN) { 2161 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2162 break; 2163 } 2164 if (sk_ctl & SK_TXCTL_LASTFRAG) 2165 ifp->if_opackets++; 2166 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2167 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2168 2169 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2170 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2171 2172 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2173 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2174 2175 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2176 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2177 link); 2178 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2179 } 2180 sc_if->sk_cdata.sk_tx_cnt--; 2181 SK_INC(idx, SK_TX_RING_CNT); 2182 } 2183 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2184 ifp->if_timer = 0; 2185 else /* nudge chip to keep tx ring moving */ 2186 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2187 2188 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2189 ifp->if_flags &= ~IFF_OACTIVE; 2190 2191 sc_if->sk_cdata.sk_tx_cons = idx; 2192 } 2193 2194 void 2195 sk_tick(void *xsc_if) 2196 { 2197 struct sk_if_softc *sc_if = xsc_if; 2198 struct mii_data *mii = &sc_if->sk_mii; 2199 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2200 int i; 2201 2202 DPRINTFN(3, ("sk_tick\n")); 2203 2204 if (!(ifp->if_flags & IFF_UP)) 2205 return; 2206 2207 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2208 sk_intr_bcom(sc_if); 2209 return; 2210 } 2211 2212 /* 2213 * According to SysKonnect, the correct way to verify that 2214 * the link has come back up is to poll bit 0 of the GPIO 2215 * register three times. This pin has the signal from the 2216 * link sync pin connected to it; if we read the same link 2217 * state 3 times in a row, we know the link is up. 2218 */ 2219 for (i = 0; i < 3; i++) { 2220 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2221 break; 2222 } 2223 2224 if (i != 3) { 2225 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2226 return; 2227 } 2228 2229 /* Turn the GP0 interrupt back on. */ 2230 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2231 SK_XM_READ_2(sc_if, XM_ISR); 2232 mii_tick(mii); 2233 if (ifp->if_link_state != LINK_STATE_UP) 2234 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2235 else 2236 callout_stop(&sc_if->sk_tick_ch); 2237 } 2238 2239 void 2240 sk_intr_bcom(struct sk_if_softc *sc_if) 2241 { 2242 struct mii_data *mii = &sc_if->sk_mii; 2243 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2244 uint16_t status; 2245 2246 2247 DPRINTFN(3, ("sk_intr_bcom\n")); 2248 2249 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2250 2251 /* 2252 * Read the PHY interrupt register to make sure 2253 * we clear any pending interrupts. 2254 */ 2255 sk_xmac_miibus_readreg(sc_if->sk_dev, 2256 SK_PHYADDR_BCOM, BRGPHY_MII_ISR, &status); 2257 2258 if (!(ifp->if_flags & IFF_RUNNING)) { 2259 sk_init_xmac(sc_if); 2260 return; 2261 } 2262 2263 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2264 uint16_t lstat; 2265 sk_xmac_miibus_readreg(sc_if->sk_dev, 2266 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS, &lstat); 2267 2268 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2269 (void)mii_mediachg(mii); 2270 /* Turn off the link LED. */ 2271 SK_IF_WRITE_1(sc_if, 0, 2272 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2273 sc_if->sk_link = 0; 2274 } else if (status & BRGPHY_ISR_LNK_CHG) { 2275 sk_xmac_miibus_writereg(sc_if->sk_dev, 2276 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2277 mii_tick(mii); 2278 sc_if->sk_link = 1; 2279 /* Turn on the link LED. */ 2280 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2281 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2282 SK_LINKLED_BLINK_OFF); 2283 mii_pollstat(mii); 2284 } else { 2285 mii_tick(mii); 2286 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2287 } 2288 } 2289 2290 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2291 } 2292 2293 void 2294 sk_intr_xmac(struct sk_if_softc *sc_if) 2295 { 2296 uint16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2297 2298 DPRINTFN(3, ("sk_intr_xmac\n")); 2299 2300 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2301 if (status & XM_ISR_GP0_SET) { 2302 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2303 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2304 } 2305 2306 if (status & XM_ISR_AUTONEG_DONE) { 2307 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2308 } 2309 } 2310 2311 if (status & XM_IMR_TX_UNDERRUN) 2312 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2313 2314 if (status & XM_IMR_RX_OVERRUN) 2315 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2316 } 2317 2318 void 2319 sk_intr_yukon(struct sk_if_softc *sc_if) 2320 { 2321 #ifdef SK_DEBUG 2322 int status; 2323 2324 status = 2325 #endif 2326 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2327 2328 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2329 } 2330 2331 int 2332 sk_intr(void *xsc) 2333 { 2334 struct sk_softc *sc = xsc; 2335 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2336 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2337 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2338 uint32_t status; 2339 int claimed = 0; 2340 2341 if (sc_if0 != NULL) 2342 ifp0 = &sc_if0->sk_ethercom.ec_if; 2343 if (sc_if1 != NULL) 2344 ifp1 = &sc_if1->sk_ethercom.ec_if; 2345 2346 for (;;) { 2347 status = CSR_READ_4(sc, SK_ISSR); 2348 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2349 2350 if (!(status & sc->sk_intrmask)) 2351 break; 2352 2353 claimed = 1; 2354 2355 /* Handle receive interrupts first. */ 2356 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2357 sk_rxeof(sc_if0); 2358 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2359 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2360 } 2361 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2362 sk_rxeof(sc_if1); 2363 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2364 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2365 } 2366 2367 /* Then transmit interrupts. */ 2368 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2369 sk_txeof(sc_if0); 2370 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2371 SK_TXBMU_CLR_IRQ_EOF); 2372 } 2373 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2374 sk_txeof(sc_if1); 2375 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2376 SK_TXBMU_CLR_IRQ_EOF); 2377 } 2378 2379 /* Then MAC interrupts. */ 2380 if (sc_if0 && (status & SK_ISR_MAC1) && 2381 (ifp0->if_flags & IFF_RUNNING)) { 2382 if (sc->sk_type == SK_GENESIS) 2383 sk_intr_xmac(sc_if0); 2384 else 2385 sk_intr_yukon(sc_if0); 2386 } 2387 2388 if (sc_if1 && (status & SK_ISR_MAC2) && 2389 (ifp1->if_flags & IFF_RUNNING)) { 2390 if (sc->sk_type == SK_GENESIS) 2391 sk_intr_xmac(sc_if1); 2392 else 2393 sk_intr_yukon(sc_if1); 2394 2395 } 2396 2397 if (status & SK_ISR_EXTERNAL_REG) { 2398 if (sc_if0 != NULL && 2399 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2400 sk_intr_bcom(sc_if0); 2401 2402 if (sc_if1 != NULL && 2403 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2404 sk_intr_bcom(sc_if1); 2405 } 2406 } 2407 2408 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2409 2410 if (ifp0 != NULL) 2411 if_schedule_deferred_start(ifp0); 2412 if (ifp1 != NULL) 2413 if_schedule_deferred_start(ifp1); 2414 2415 KASSERT(sc->rnd_attached > 0); 2416 rnd_add_uint32(&sc->rnd_source, status); 2417 2418 if (sc->sk_int_mod_pending) 2419 sk_update_int_mod(sc); 2420 2421 return claimed; 2422 } 2423 2424 void 2425 sk_init_xmac(struct sk_if_softc *sc_if) 2426 { 2427 struct sk_softc *sc = sc_if->sk_softc; 2428 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2429 static const struct sk_bcom_hack bhack[] = { 2430 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2431 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2432 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2433 { 0, 0 } }; 2434 2435 DPRINTFN(1, ("sk_init_xmac\n")); 2436 2437 /* Unreset the XMAC. */ 2438 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2439 DELAY(1000); 2440 2441 /* Reset the XMAC's internal state. */ 2442 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2443 2444 /* Save the XMAC II revision */ 2445 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2446 2447 /* 2448 * Perform additional initialization for external PHYs, 2449 * namely for the 1000baseTX cards that use the XMAC's 2450 * GMII mode. 2451 */ 2452 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2453 int i = 0; 2454 uint32_t val; 2455 uint16_t phyval; 2456 2457 /* Take PHY out of reset. */ 2458 val = sk_win_read_4(sc, SK_GPIO); 2459 if (sc_if->sk_port == SK_PORT_A) 2460 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2461 else 2462 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2463 sk_win_write_4(sc, SK_GPIO, val); 2464 2465 /* Enable GMII mode on the XMAC. */ 2466 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2467 2468 sk_xmac_miibus_writereg(sc_if->sk_dev, 2469 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2470 DELAY(10000); 2471 sk_xmac_miibus_writereg(sc_if->sk_dev, 2472 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2473 2474 /* 2475 * Early versions of the BCM5400 apparently have 2476 * a bug that requires them to have their reserved 2477 * registers initialized to some magic values. I don't 2478 * know what the numbers do, I'm just the messenger. 2479 */ 2480 sk_xmac_miibus_readreg(sc_if->sk_dev, 2481 SK_PHYADDR_BCOM, 0x03, &phyval); 2482 if (phyval == 0x6041) { 2483 while (bhack[i].reg) { 2484 sk_xmac_miibus_writereg(sc_if->sk_dev, 2485 SK_PHYADDR_BCOM, bhack[i].reg, 2486 bhack[i].val); 2487 i++; 2488 } 2489 } 2490 } 2491 2492 /* Set station address */ 2493 SK_XM_WRITE_2(sc_if, XM_PAR0, 2494 *(uint16_t *)(&sc_if->sk_enaddr[0])); 2495 SK_XM_WRITE_2(sc_if, XM_PAR1, 2496 *(uint16_t *)(&sc_if->sk_enaddr[2])); 2497 SK_XM_WRITE_2(sc_if, XM_PAR2, 2498 *(uint16_t *)(&sc_if->sk_enaddr[4])); 2499 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2500 2501 if (ifp->if_flags & IFF_PROMISC) 2502 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2503 else 2504 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2505 2506 if (ifp->if_flags & IFF_BROADCAST) 2507 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2508 else 2509 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2510 2511 /* We don't need the FCS appended to the packet. */ 2512 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2513 2514 /* We want short frames padded to 60 bytes. */ 2515 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2516 2517 /* 2518 * Enable the reception of all error frames. This is is 2519 * a necessary evil due to the design of the XMAC. The 2520 * XMAC's receive FIFO is only 8K in size, however jumbo 2521 * frames can be up to 9000 bytes in length. When bad 2522 * frame filtering is enabled, the XMAC's RX FIFO operates 2523 * in 'store and forward' mode. For this to work, the 2524 * entire frame has to fit into the FIFO, but that means 2525 * that jumbo frames larger than 8192 bytes will be 2526 * truncated. Disabling all bad frame filtering causes 2527 * the RX FIFO to operate in streaming mode, in which 2528 * case the XMAC will start transfering frames out of the 2529 * RX FIFO as soon as the FIFO threshold is reached. 2530 */ 2531 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2532 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2533 XM_MODE_RX_INRANGELEN); 2534 2535 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2536 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2537 else 2538 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2539 2540 /* 2541 * Bump up the transmit threshold. This helps hold off transmit 2542 * underruns when we're blasting traffic from both ports at once. 2543 */ 2544 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2545 2546 /* Set multicast filter */ 2547 sk_setmulti(sc_if); 2548 2549 /* Clear and enable interrupts */ 2550 SK_XM_READ_2(sc_if, XM_ISR); 2551 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2552 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2553 else 2554 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2555 2556 /* Configure MAC arbiter */ 2557 switch (sc_if->sk_xmac_rev) { 2558 case XM_XMAC_REV_B2: 2559 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2560 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2561 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2562 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2563 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2564 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2565 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2566 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2567 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2568 break; 2569 case XM_XMAC_REV_C1: 2570 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2571 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2572 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2573 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2574 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2575 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2576 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2577 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2578 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2579 break; 2580 default: 2581 break; 2582 } 2583 sk_win_write_2(sc, SK_MACARB_CTL, 2584 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2585 2586 sc_if->sk_link = 1; 2587 } 2588 2589 void sk_init_yukon(struct sk_if_softc *sc_if) 2590 { 2591 uint32_t /*mac, */phy; 2592 uint16_t reg; 2593 struct sk_softc *sc; 2594 int i; 2595 2596 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2597 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2598 2599 sc = sc_if->sk_softc; 2600 if (sc->sk_type == SK_YUKON_LITE && 2601 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2602 /* Take PHY out of reset. */ 2603 sk_win_write_4(sc, SK_GPIO, 2604 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2605 } 2606 2607 2608 /* GMAC and GPHY Reset */ 2609 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2610 2611 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2612 2613 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2614 DELAY(1000); 2615 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2616 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2617 DELAY(1000); 2618 2619 2620 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2621 2622 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2623 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2624 2625 switch (sc_if->sk_softc->sk_pmd) { 2626 case IFM_1000_SX: 2627 case IFM_1000_LX: 2628 phy |= SK_GPHY_FIBER; 2629 break; 2630 2631 case IFM_1000_CX: 2632 case IFM_1000_T: 2633 phy |= SK_GPHY_COPPER; 2634 break; 2635 } 2636 2637 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2638 2639 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2640 DELAY(1000); 2641 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2642 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2643 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2644 2645 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2646 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2647 2648 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2649 2650 /* unused read of the interrupt source register */ 2651 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2652 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2653 2654 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2655 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2656 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2657 2658 /* MIB Counter Clear Mode set */ 2659 reg |= YU_PAR_MIB_CLR; 2660 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2661 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2662 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2663 2664 /* MIB Counter Clear Mode clear */ 2665 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2666 reg &= ~YU_PAR_MIB_CLR; 2667 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2668 2669 /* receive control reg */ 2670 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2671 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2672 YU_RCR_CRCR); 2673 2674 /* transmit parameter register */ 2675 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2676 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2677 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2678 2679 /* serial mode register */ 2680 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2681 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2682 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2683 YU_SMR_IPG_DATA(0x1e)); 2684 2685 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2686 /* Setup Yukon's address */ 2687 for (i = 0; i < 3; i++) { 2688 /* Write Source Address 1 (unicast filter) */ 2689 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2690 sc_if->sk_enaddr[i * 2] | 2691 sc_if->sk_enaddr[i * 2 + 1] << 8); 2692 } 2693 2694 for (i = 0; i < 3; i++) { 2695 reg = sk_win_read_2(sc_if->sk_softc, 2696 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2697 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2698 } 2699 2700 /* Set multicast filter */ 2701 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2702 sk_setmulti(sc_if); 2703 2704 /* enable interrupt mask for counter overflows */ 2705 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2706 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2707 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2708 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2709 2710 /* Configure RX MAC FIFO */ 2711 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2712 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2713 2714 /* Configure TX MAC FIFO */ 2715 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2716 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2717 2718 DPRINTFN(6, ("sk_init_yukon: end\n")); 2719 } 2720 2721 /* 2722 * Note that to properly initialize any part of the GEnesis chip, 2723 * you first have to take it out of reset mode. 2724 */ 2725 int 2726 sk_init(struct ifnet *ifp) 2727 { 2728 struct sk_if_softc *sc_if = ifp->if_softc; 2729 struct sk_softc *sc = sc_if->sk_softc; 2730 struct mii_data *mii = &sc_if->sk_mii; 2731 int rc = 0, s; 2732 uint32_t imr, imtimer_ticks; 2733 2734 DPRINTFN(1, ("sk_init\n")); 2735 2736 s = splnet(); 2737 2738 if (ifp->if_flags & IFF_RUNNING) { 2739 splx(s); 2740 return 0; 2741 } 2742 2743 /* Cancel pending I/O and free all RX/TX buffers. */ 2744 sk_stop(ifp,0); 2745 2746 if (sc->sk_type == SK_GENESIS) { 2747 /* Configure LINK_SYNC LED */ 2748 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2749 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2750 SK_LINKLED_LINKSYNC_ON); 2751 2752 /* Configure RX LED */ 2753 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2754 SK_RXLEDCTL_COUNTER_START); 2755 2756 /* Configure TX LED */ 2757 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2758 SK_TXLEDCTL_COUNTER_START); 2759 } 2760 2761 /* Configure I2C registers */ 2762 2763 /* Configure XMAC(s) */ 2764 switch (sc->sk_type) { 2765 case SK_GENESIS: 2766 sk_init_xmac(sc_if); 2767 break; 2768 case SK_YUKON: 2769 case SK_YUKON_LITE: 2770 case SK_YUKON_LP: 2771 sk_init_yukon(sc_if); 2772 break; 2773 } 2774 if ((rc = mii_mediachg(mii)) == ENXIO) 2775 rc = 0; 2776 else if (rc != 0) 2777 goto out; 2778 2779 if (sc->sk_type == SK_GENESIS) { 2780 /* Configure MAC FIFOs */ 2781 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2782 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2783 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2784 2785 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2786 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2787 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2788 } 2789 2790 /* Configure transmit arbiter(s) */ 2791 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2792 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2793 2794 /* Configure RAMbuffers */ 2795 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2796 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2797 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2798 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2799 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2800 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2801 2802 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2803 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2804 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2805 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2806 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2807 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2808 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2809 2810 /* Configure BMUs */ 2811 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2812 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2813 SK_RX_RING_ADDR(sc_if, 0)); 2814 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2815 2816 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2817 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2818 SK_TX_RING_ADDR(sc_if, 0)); 2819 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2820 2821 /* Init descriptors */ 2822 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2823 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2824 "memory for rx buffers\n"); 2825 sk_stop(ifp,0); 2826 splx(s); 2827 return ENOBUFS; 2828 } 2829 2830 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2831 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2832 "memory for tx buffers\n"); 2833 sk_stop(ifp,0); 2834 splx(s); 2835 return ENOBUFS; 2836 } 2837 2838 /* Set interrupt moderation if changed via sysctl. */ 2839 switch (sc->sk_type) { 2840 case SK_GENESIS: 2841 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2842 break; 2843 case SK_YUKON_EC: 2844 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2845 break; 2846 default: 2847 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2848 } 2849 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2850 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2851 sk_win_write_4(sc, SK_IMTIMERINIT, 2852 SK_IM_USECS(sc->sk_int_mod)); 2853 aprint_verbose_dev(sc->sk_dev, 2854 "interrupt moderation is %d us\n", sc->sk_int_mod); 2855 } 2856 2857 /* Configure interrupt handling */ 2858 CSR_READ_4(sc, SK_ISSR); 2859 if (sc_if->sk_port == SK_PORT_A) 2860 sc->sk_intrmask |= SK_INTRS1; 2861 else 2862 sc->sk_intrmask |= SK_INTRS2; 2863 2864 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2865 2866 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2867 2868 /* Start BMUs. */ 2869 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2870 2871 if (sc->sk_type == SK_GENESIS) { 2872 /* Enable XMACs TX and RX state machines */ 2873 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2874 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2875 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2876 } 2877 2878 if (SK_YUKON_FAMILY(sc->sk_type)) { 2879 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2880 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2881 #if 0 2882 /* XXX disable 100Mbps and full duplex mode? */ 2883 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2884 #endif 2885 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2886 } 2887 2888 2889 ifp->if_flags |= IFF_RUNNING; 2890 ifp->if_flags &= ~IFF_OACTIVE; 2891 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2892 2893 out: 2894 splx(s); 2895 return rc; 2896 } 2897 2898 void 2899 sk_stop(struct ifnet *ifp, int disable) 2900 { 2901 struct sk_if_softc *sc_if = ifp->if_softc; 2902 struct sk_softc *sc = sc_if->sk_softc; 2903 int i; 2904 2905 DPRINTFN(1, ("sk_stop\n")); 2906 2907 callout_stop(&sc_if->sk_tick_ch); 2908 2909 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2910 uint32_t val; 2911 2912 /* Put PHY back into reset. */ 2913 val = sk_win_read_4(sc, SK_GPIO); 2914 if (sc_if->sk_port == SK_PORT_A) { 2915 val |= SK_GPIO_DIR0; 2916 val &= ~SK_GPIO_DAT0; 2917 } else { 2918 val |= SK_GPIO_DIR2; 2919 val &= ~SK_GPIO_DAT2; 2920 } 2921 sk_win_write_4(sc, SK_GPIO, val); 2922 } 2923 2924 /* Turn off various components of this interface. */ 2925 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2926 switch (sc->sk_type) { 2927 case SK_GENESIS: 2928 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2929 SK_TXMACCTL_XMAC_RESET); 2930 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2931 break; 2932 case SK_YUKON: 2933 case SK_YUKON_LITE: 2934 case SK_YUKON_LP: 2935 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2936 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2937 break; 2938 } 2939 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2940 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2941 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2942 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2943 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2944 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2945 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2946 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2947 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2948 2949 /* Disable interrupts */ 2950 if (sc_if->sk_port == SK_PORT_A) 2951 sc->sk_intrmask &= ~SK_INTRS1; 2952 else 2953 sc->sk_intrmask &= ~SK_INTRS2; 2954 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2955 2956 SK_XM_READ_2(sc_if, XM_ISR); 2957 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2958 2959 /* Free RX and TX mbufs still in the queues. */ 2960 for (i = 0; i < SK_RX_RING_CNT; i++) { 2961 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2962 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2963 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2964 } 2965 } 2966 2967 for (i = 0; i < SK_TX_RING_CNT; i++) { 2968 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2969 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2970 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2971 } 2972 } 2973 2974 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2975 } 2976 2977 /* Power Management Framework */ 2978 2979 static bool 2980 skc_suspend(device_t dv, const pmf_qual_t *qual) 2981 { 2982 struct sk_softc *sc = device_private(dv); 2983 2984 DPRINTFN(2, ("skc_suspend\n")); 2985 2986 /* Turn off the driver is loaded LED */ 2987 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2988 2989 return true; 2990 } 2991 2992 static bool 2993 skc_resume(device_t dv, const pmf_qual_t *qual) 2994 { 2995 struct sk_softc *sc = device_private(dv); 2996 2997 DPRINTFN(2, ("skc_resume\n")); 2998 2999 sk_reset(sc); 3000 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 3001 3002 return true; 3003 } 3004 3005 static bool 3006 sk_resume(device_t dv, const pmf_qual_t *qual) 3007 { 3008 struct sk_if_softc *sc_if = device_private(dv); 3009 3010 sk_init_yukon(sc_if); 3011 return true; 3012 } 3013 3014 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 3015 skc_probe, skc_attach, NULL, NULL); 3016 3017 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 3018 sk_probe, sk_attach, NULL, NULL); 3019 3020 #ifdef SK_DEBUG 3021 void 3022 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 3023 { 3024 #define DESC_PRINT(X) \ 3025 if (X) \ 3026 printf("txdesc[%d]." #X "=%#x\n", \ 3027 idx, X); 3028 3029 DESC_PRINT(le32toh(desc->sk_ctl)); 3030 DESC_PRINT(le32toh(desc->sk_next)); 3031 DESC_PRINT(le32toh(desc->sk_data_lo)); 3032 DESC_PRINT(le32toh(desc->sk_data_hi)); 3033 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 3034 DESC_PRINT(le16toh(desc->sk_rsvd0)); 3035 DESC_PRINT(le16toh(desc->sk_csum_startval)); 3036 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 3037 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 3038 DESC_PRINT(le16toh(desc->sk_rsvd1)); 3039 #undef PRINT 3040 } 3041 3042 void 3043 sk_dump_bytes(const char *data, int len) 3044 { 3045 int c, i, j; 3046 3047 for (i = 0; i < len; i += 16) { 3048 printf("%08x ", i); 3049 c = len - i; 3050 if (c > 16) c = 16; 3051 3052 for (j = 0; j < c; j++) { 3053 printf("%02x ", data[i + j] & 0xff); 3054 if ((j & 0xf) == 7 && j > 0) 3055 printf(" "); 3056 } 3057 3058 for (; j < 16; j++) 3059 printf(" "); 3060 printf(" "); 3061 3062 for (j = 0; j < c; j++) { 3063 int ch = data[i + j] & 0xff; 3064 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3065 } 3066 3067 printf("\n"); 3068 3069 if (c < 16) 3070 break; 3071 } 3072 } 3073 3074 void 3075 sk_dump_mbuf(struct mbuf *m) 3076 { 3077 int count = m->m_pkthdr.len; 3078 3079 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3080 3081 while (count > 0 && m) { 3082 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3083 m, m->m_data, m->m_len); 3084 sk_dump_bytes(mtod(m, char *), m->m_len); 3085 3086 count -= m->m_len; 3087 m = m->m_next; 3088 } 3089 } 3090 #endif 3091 3092 static int 3093 sk_sysctl_handler(SYSCTLFN_ARGS) 3094 { 3095 int error, t; 3096 struct sysctlnode node; 3097 struct sk_softc *sc; 3098 3099 node = *rnode; 3100 sc = node.sysctl_data; 3101 t = sc->sk_int_mod; 3102 node.sysctl_data = &t; 3103 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3104 if (error || newp == NULL) 3105 return error; 3106 3107 if (t < SK_IM_MIN || t > SK_IM_MAX) 3108 return EINVAL; 3109 3110 /* update the softc with sysctl-changed value, and mark 3111 for hardware update */ 3112 sc->sk_int_mod = t; 3113 sc->sk_int_mod_pending = 1; 3114 return 0; 3115 } 3116 3117 /* 3118 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3119 * set up in skc_attach() 3120 */ 3121 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3122 { 3123 int rc; 3124 const struct sysctlnode *node; 3125 3126 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3127 0, CTLTYPE_NODE, "sk", 3128 SYSCTL_DESCR("sk interface controls"), 3129 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3130 goto err; 3131 } 3132 3133 sk_root_num = node->sysctl_num; 3134 return; 3135 3136 err: 3137 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3138 } 3139
Indexes created Wed Sep 24 05:09:52 GMT 2025