if_sk.c revision 1.96
1 /* $NetBSD: if_sk.c,v 1.96 2019/05/23 10:57:28 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.96 2019/05/23 10:57:28 msaitoh Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/sockio.h> 123 #include <sys/mbuf.h> 124 #include <sys/malloc.h> 125 #include <sys/mutex.h> 126 #include <sys/kernel.h> 127 #include <sys/socket.h> 128 #include <sys/device.h> 129 #include <sys/queue.h> 130 #include <sys/callout.h> 131 #include <sys/sysctl.h> 132 #include <sys/endian.h> 133 134 #include <net/if.h> 135 #include <net/if_dl.h> 136 #include <net/if_types.h> 137 138 #include <net/if_media.h> 139 140 #include <net/bpf.h> 141 #include <sys/rndsource.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 #include <dev/mii/brgphyreg.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 #include <dev/pci/pcidevs.h> 150 151 /* #define SK_USEIOSPACE */ 152 153 #include <dev/pci/if_skreg.h> 154 #include <dev/pci/if_skvar.h> 155 156 int skc_probe(device_t, cfdata_t, void *); 157 void skc_attach(device_t, device_t, void *aux); 158 int sk_probe(device_t, cfdata_t, void *); 159 void sk_attach(device_t, device_t, void *aux); 160 int skcprint(void *, const char *); 161 int sk_intr(void *); 162 void sk_intr_bcom(struct sk_if_softc *); 163 void sk_intr_xmac(struct sk_if_softc *); 164 void sk_intr_yukon(struct sk_if_softc *); 165 void sk_rxeof(struct sk_if_softc *); 166 void sk_txeof(struct sk_if_softc *); 167 int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 168 void sk_start(struct ifnet *); 169 int sk_ioctl(struct ifnet *, u_long, void *); 170 int sk_init(struct ifnet *); 171 void sk_init_xmac(struct sk_if_softc *); 172 void sk_init_yukon(struct sk_if_softc *); 173 void sk_stop(struct ifnet *, int); 174 void sk_watchdog(struct ifnet *); 175 void sk_shutdown(void *); 176 int sk_ifmedia_upd(struct ifnet *); 177 void sk_reset(struct sk_softc *); 178 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 179 int sk_alloc_jumbo_mem(struct sk_if_softc *); 180 void sk_free_jumbo_mem(struct sk_if_softc *); 181 void *sk_jalloc(struct sk_if_softc *); 182 void sk_jfree(struct mbuf *, void *, size_t, void *); 183 int sk_init_rx_ring(struct sk_if_softc *); 184 int sk_init_tx_ring(struct sk_if_softc *); 185 uint8_t sk_vpd_readbyte(struct sk_softc *, int); 186 void sk_vpd_read_res(struct sk_softc *, 187 struct vpd_res *, int); 188 void sk_vpd_read(struct sk_softc *); 189 190 void sk_update_int_mod(struct sk_softc *); 191 192 int sk_xmac_miibus_readreg(device_t, int, int, uint16_t *); 193 int sk_xmac_miibus_writereg(device_t, int, int, uint16_t); 194 void sk_xmac_miibus_statchg(struct ifnet *); 195 196 int sk_marv_miibus_readreg(device_t, int, int, uint16_t *); 197 int sk_marv_miibus_writereg(device_t, int, int, uint16_t); 198 void sk_marv_miibus_statchg(struct ifnet *); 199 200 uint32_t sk_xmac_hash(void *); 201 uint32_t sk_yukon_hash(void *); 202 void sk_setfilt(struct sk_if_softc *, void *, int); 203 void sk_setmulti(struct sk_if_softc *); 204 void sk_tick(void *); 205 206 static bool skc_suspend(device_t, const pmf_qual_t *); 207 static bool skc_resume(device_t, const pmf_qual_t *); 208 static bool sk_resume(device_t dv, const pmf_qual_t *); 209 210 /* #define SK_DEBUG 2 */ 211 #ifdef SK_DEBUG 212 #define DPRINTF(x) if (skdebug) printf x 213 #define DPRINTFN(n, x) if (skdebug >= (n)) printf x 214 int skdebug = SK_DEBUG; 215 216 void sk_dump_txdesc(struct sk_tx_desc *, int); 217 void sk_dump_mbuf(struct mbuf *); 218 void sk_dump_bytes(const char *, int); 219 #else 220 #define DPRINTF(x) 221 #define DPRINTFN(n, x) 222 #endif 223 224 static int sk_sysctl_handler(SYSCTLFN_PROTO); 225 static int sk_root_num; 226 227 /* supported device vendors */ 228 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 229 static const struct sk_product { 230 pci_vendor_id_t sk_vendor; 231 pci_product_id_t sk_product; 232 } sk_products[] = { 233 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 234 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 235 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 236 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 237 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 238 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 239 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 240 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 241 { 0, 0, } 242 }; 243 244 #define SK_LINKSYS_EG1032_SUBID 0x00151737 245 246 static inline uint32_t 247 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 248 { 249 #ifdef SK_USEIOSPACE 250 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 251 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 252 #else 253 return CSR_READ_4(sc, reg); 254 #endif 255 } 256 257 static inline uint16_t 258 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 259 { 260 #ifdef SK_USEIOSPACE 261 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 262 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 263 #else 264 return CSR_READ_2(sc, reg); 265 #endif 266 } 267 268 static inline uint8_t 269 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 270 { 271 #ifdef SK_USEIOSPACE 272 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 273 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 274 #else 275 return CSR_READ_1(sc, reg); 276 #endif 277 } 278 279 static inline void 280 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 281 { 282 #ifdef SK_USEIOSPACE 283 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 284 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 285 #else 286 CSR_WRITE_4(sc, reg, x); 287 #endif 288 } 289 290 static inline void 291 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 292 { 293 #ifdef SK_USEIOSPACE 294 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 295 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 296 #else 297 CSR_WRITE_2(sc, reg, x); 298 #endif 299 } 300 301 static inline void 302 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 303 { 304 #ifdef SK_USEIOSPACE 305 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 306 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 307 #else 308 CSR_WRITE_1(sc, reg, x); 309 #endif 310 } 311 312 /* 313 * The VPD EEPROM contains Vital Product Data, as suggested in 314 * the PCI 2.1 specification. The VPD data is separared into areas 315 * denoted by resource IDs. The SysKonnect VPD contains an ID string 316 * resource (the name of the adapter), a read-only area resource 317 * containing various key/data fields and a read/write area which 318 * can be used to store asset management information or log messages. 319 * We read the ID string and read-only into buffers attached to 320 * the controller softc structure for later use. At the moment, 321 * we only use the ID string during sk_attach(). 322 */ 323 uint8_t 324 sk_vpd_readbyte(struct sk_softc *sc, int addr) 325 { 326 int i; 327 328 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 329 for (i = 0; i < SK_TIMEOUT; i++) { 330 DELAY(1); 331 if (sk_win_read_2(sc, 332 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 333 break; 334 } 335 336 if (i == SK_TIMEOUT) 337 return 0; 338 339 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 340 } 341 342 void 343 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 344 { 345 int i; 346 uint8_t *ptr; 347 348 ptr = (uint8_t *)res; 349 for (i = 0; i < sizeof(struct vpd_res); i++) 350 ptr[i] = sk_vpd_readbyte(sc, i + addr); 351 } 352 353 void 354 sk_vpd_read(struct sk_softc *sc) 355 { 356 int pos = 0, i; 357 struct vpd_res res; 358 359 if (sc->sk_vpd_prodname != NULL) 360 free(sc->sk_vpd_prodname, M_DEVBUF); 361 if (sc->sk_vpd_readonly != NULL) 362 free(sc->sk_vpd_readonly, M_DEVBUF); 363 sc->sk_vpd_prodname = NULL; 364 sc->sk_vpd_readonly = NULL; 365 366 sk_vpd_read_res(sc, &res, pos); 367 368 if (res.vr_id != VPD_RES_ID) { 369 aprint_error_dev(sc->sk_dev, 370 "bad VPD resource id: expected %x got %x\n", 371 VPD_RES_ID, res.vr_id); 372 return; 373 } 374 375 pos += sizeof(res); 376 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 377 if (sc->sk_vpd_prodname == NULL) 378 panic("sk_vpd_read"); 379 for (i = 0; i < res.vr_len; i++) 380 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 381 sc->sk_vpd_prodname[i] = '\0'; 382 pos += i; 383 384 sk_vpd_read_res(sc, &res, pos); 385 386 if (res.vr_id != VPD_RES_READ) { 387 aprint_error_dev(sc->sk_dev, 388 "bad VPD resource id: expected %x got %x\n", 389 VPD_RES_READ, res.vr_id); 390 return; 391 } 392 393 pos += sizeof(res); 394 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 395 if (sc->sk_vpd_readonly == NULL) 396 panic("sk_vpd_read"); 397 for (i = 0; i < res.vr_len ; i++) 398 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 399 } 400 401 int 402 sk_xmac_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 403 { 404 struct sk_if_softc *sc_if = device_private(dev); 405 int i; 406 407 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 408 409 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 410 return -1; 411 412 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 413 SK_XM_READ_2(sc_if, XM_PHY_DATA); 414 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 415 for (i = 0; i < SK_TIMEOUT; i++) { 416 DELAY(1); 417 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 418 XM_MMUCMD_PHYDATARDY) 419 break; 420 } 421 422 if (i == SK_TIMEOUT) { 423 aprint_error_dev(sc_if->sk_dev, 424 "phy failed to come ready\n"); 425 return ETIMEDOUT; 426 } 427 } 428 DELAY(1); 429 *val = SK_XM_READ_2(sc_if, XM_PHY_DATA); 430 return 0; 431 } 432 433 int 434 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 435 { 436 struct sk_if_softc *sc_if = device_private(dev); 437 int i; 438 439 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 440 441 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 442 for (i = 0; i < SK_TIMEOUT; i++) { 443 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 444 break; 445 } 446 447 if (i == SK_TIMEOUT) { 448 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 449 return ETIMEDOUT; 450 } 451 452 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 453 for (i = 0; i < SK_TIMEOUT; i++) { 454 DELAY(1); 455 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 456 break; 457 } 458 459 if (i == SK_TIMEOUT) { 460 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 461 return ETIMEDOUT; 462 } 463 464 return 0; 465 } 466 467 void 468 sk_xmac_miibus_statchg(struct ifnet *ifp) 469 { 470 struct sk_if_softc *sc_if = ifp->if_softc; 471 struct mii_data *mii = &sc_if->sk_mii; 472 473 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 474 475 /* 476 * If this is a GMII PHY, manually set the XMAC's 477 * duplex mode accordingly. 478 */ 479 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 480 if ((mii->mii_media_active & IFM_FDX) != 0) 481 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 482 else 483 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 484 } 485 } 486 487 int 488 sk_marv_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 489 { 490 struct sk_if_softc *sc_if = device_private(dev); 491 uint16_t data; 492 int i; 493 494 if (phy != 0 || 495 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 496 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 497 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 498 phy, reg)); 499 return -1; 500 } 501 502 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 503 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 504 505 for (i = 0; i < SK_TIMEOUT; i++) { 506 DELAY(1); 507 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 508 if (data & YU_SMICR_READ_VALID) 509 break; 510 } 511 512 if (i == SK_TIMEOUT) { 513 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 514 return ETIMEDOUT; 515 } 516 517 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 518 SK_TIMEOUT)); 519 520 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 521 522 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 523 phy, reg, *val)); 524 525 return 0; 526 } 527 528 int 529 sk_marv_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 530 { 531 struct sk_if_softc *sc_if = device_private(dev); 532 int i; 533 534 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#hx\n", 535 phy, reg, val)); 536 537 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 538 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 539 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 540 541 for (i = 0; i < SK_TIMEOUT; i++) { 542 DELAY(1); 543 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 544 break; 545 } 546 547 if (i == SK_TIMEOUT) { 548 printf("%s: phy write timed out\n", 549 device_xname(sc_if->sk_dev)); 550 return ETIMEDOUT; 551 } 552 553 return 0; 554 } 555 556 void 557 sk_marv_miibus_statchg(struct ifnet *ifp) 558 { 559 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 560 SK_YU_READ_2(((struct sk_if_softc *)ifp->if_softc), 561 YUKON_GPCR))); 562 } 563 564 uint32_t 565 sk_xmac_hash(void *addr) 566 { 567 uint32_t crc; 568 569 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 570 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 571 DPRINTFN(2,("multicast hash for %s is %x\n", ether_sprintf(addr),crc)); 572 return crc; 573 } 574 575 uint32_t 576 sk_yukon_hash(void *addr) 577 { 578 uint32_t crc; 579 580 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 581 crc &= ((1 << SK_HASH_BITS) - 1); 582 DPRINTFN(2,("multicast hash for %s is %x\n", ether_sprintf(addr),crc)); 583 return crc; 584 } 585 586 void 587 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 588 { 589 char *addr = addrv; 590 int base = XM_RXFILT_ENTRY(slot); 591 592 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0])); 593 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2])); 594 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4])); 595 } 596 597 void 598 sk_setmulti(struct sk_if_softc *sc_if) 599 { 600 struct sk_softc *sc = sc_if->sk_softc; 601 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 602 uint32_t hashes[2] = { 0, 0 }; 603 int h = 0, i; 604 struct ethercom *ec = &sc_if->sk_ethercom; 605 struct ether_multi *enm; 606 struct ether_multistep step; 607 uint8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 608 609 /* First, zot all the existing filters. */ 610 switch (sc->sk_type) { 611 case SK_GENESIS: 612 for (i = 1; i < XM_RXFILT_MAX; i++) 613 sk_setfilt(sc_if, (void *)&dummy, i); 614 615 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 616 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 617 break; 618 case SK_YUKON: 619 case SK_YUKON_LITE: 620 case SK_YUKON_LP: 621 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 622 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 623 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 624 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 625 break; 626 } 627 628 /* Now program new ones. */ 629 allmulti: 630 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 631 hashes[0] = 0xFFFFFFFF; 632 hashes[1] = 0xFFFFFFFF; 633 } else { 634 i = 1; 635 /* First find the tail of the list. */ 636 ETHER_FIRST_MULTI(step, ec, enm); 637 while (enm != NULL) { 638 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 639 ETHER_ADDR_LEN)) { 640 ifp->if_flags |= IFF_ALLMULTI; 641 goto allmulti; 642 } 643 DPRINTFN(2,("multicast address %s\n", 644 ether_sprintf(enm->enm_addrlo))); 645 /* 646 * Program the first XM_RXFILT_MAX multicast groups 647 * into the perfect filter. For all others, 648 * use the hash table. 649 */ 650 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 651 sk_setfilt(sc_if, enm->enm_addrlo, i); 652 i++; 653 } 654 else { 655 switch (sc->sk_type) { 656 case SK_GENESIS: 657 h = sk_xmac_hash(enm->enm_addrlo); 658 break; 659 case SK_YUKON: 660 case SK_YUKON_LITE: 661 case SK_YUKON_LP: 662 h = sk_yukon_hash(enm->enm_addrlo); 663 break; 664 } 665 if (h < 32) 666 hashes[0] |= (1 << h); 667 else 668 hashes[1] |= (1 << (h - 32)); 669 } 670 671 ETHER_NEXT_MULTI(step, enm); 672 } 673 } 674 675 switch (sc->sk_type) { 676 case SK_GENESIS: 677 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH | 678 XM_MODE_RX_USE_PERFECT); 679 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 680 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 681 break; 682 case SK_YUKON: 683 case SK_YUKON_LITE: 684 case SK_YUKON_LP: 685 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 686 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 687 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 688 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 689 break; 690 } 691 } 692 693 int 694 sk_init_rx_ring(struct sk_if_softc *sc_if) 695 { 696 struct sk_chain_data *cd = &sc_if->sk_cdata; 697 struct sk_ring_data *rd = sc_if->sk_rdata; 698 int i; 699 700 memset((char *)rd->sk_rx_ring, 0, 701 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 702 703 for (i = 0; i < SK_RX_RING_CNT; i++) { 704 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 705 if (i == (SK_RX_RING_CNT - 1)) { 706 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 707 rd->sk_rx_ring[i].sk_next = 708 htole32(SK_RX_RING_ADDR(sc_if, 0)); 709 } else { 710 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 711 rd->sk_rx_ring[i].sk_next = 712 htole32(SK_RX_RING_ADDR(sc_if, i+1)); 713 } 714 } 715 716 for (i = 0; i < SK_RX_RING_CNT; i++) { 717 if (sk_newbuf(sc_if, i, NULL, 718 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 719 aprint_error_dev(sc_if->sk_dev, 720 "failed alloc of %dth mbuf\n", i); 721 return ENOBUFS; 722 } 723 } 724 sc_if->sk_cdata.sk_rx_prod = 0; 725 sc_if->sk_cdata.sk_rx_cons = 0; 726 727 return 0; 728 } 729 730 int 731 sk_init_tx_ring(struct sk_if_softc *sc_if) 732 { 733 struct sk_chain_data *cd = &sc_if->sk_cdata; 734 struct sk_ring_data *rd = sc_if->sk_rdata; 735 int i; 736 737 memset(sc_if->sk_rdata->sk_tx_ring, 0, 738 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 739 740 for (i = 0; i < SK_TX_RING_CNT; i++) { 741 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 742 if (i == (SK_TX_RING_CNT - 1)) { 743 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 744 rd->sk_tx_ring[i].sk_next = 745 htole32(SK_TX_RING_ADDR(sc_if, 0)); 746 } else { 747 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 748 rd->sk_tx_ring[i].sk_next = 749 htole32(SK_TX_RING_ADDR(sc_if, i+1)); 750 } 751 } 752 753 sc_if->sk_cdata.sk_tx_prod = 0; 754 sc_if->sk_cdata.sk_tx_cons = 0; 755 sc_if->sk_cdata.sk_tx_cnt = 0; 756 757 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 758 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 759 760 return 0; 761 } 762 763 int 764 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 765 bus_dmamap_t dmamap) 766 { 767 struct mbuf *m_new = NULL; 768 struct sk_chain *c; 769 struct sk_rx_desc *r; 770 771 if (m == NULL) { 772 void *buf = NULL; 773 774 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 775 if (m_new == NULL) { 776 aprint_error_dev(sc_if->sk_dev, 777 "no memory for rx list -- packet dropped!\n"); 778 return ENOBUFS; 779 } 780 781 /* Allocate the jumbo buffer */ 782 buf = sk_jalloc(sc_if); 783 if (buf == NULL) { 784 m_freem(m_new); 785 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 786 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 787 return ENOBUFS; 788 } 789 790 /* Attach the buffer to the mbuf */ 791 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 792 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 793 794 } else { 795 /* 796 * We're re-using a previously allocated mbuf; 797 * be sure to re-init pointers and lengths to 798 * default values. 799 */ 800 m_new = m; 801 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 802 m_new->m_data = m_new->m_ext.ext_buf; 803 } 804 m_adj(m_new, ETHER_ALIGN); 805 806 c = &sc_if->sk_cdata.sk_rx_chain[i]; 807 r = c->sk_desc; 808 c->sk_mbuf = m_new; 809 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 810 (((vaddr_t)m_new->m_data 811 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 812 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 813 814 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 815 816 return 0; 817 } 818 819 /* 820 * Memory management for jumbo frames. 821 */ 822 823 int 824 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 825 { 826 struct sk_softc *sc = sc_if->sk_softc; 827 char *ptr, *kva; 828 bus_dma_segment_t seg; 829 int i, rseg, state, error; 830 struct sk_jpool_entry *entry; 831 832 state = error = 0; 833 834 /* Grab a big chunk o' storage. */ 835 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 836 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 837 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 838 return ENOBUFS; 839 } 840 841 state = 1; 842 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 843 BUS_DMA_NOWAIT)) { 844 aprint_error_dev(sc->sk_dev, 845 "can't map dma buffers (%d bytes)\n", 846 SK_JMEM); 847 error = ENOBUFS; 848 goto out; 849 } 850 851 state = 2; 852 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 853 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 854 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 855 error = ENOBUFS; 856 goto out; 857 } 858 859 state = 3; 860 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 861 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 862 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 863 error = ENOBUFS; 864 goto out; 865 } 866 867 state = 4; 868 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 869 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 870 871 LIST_INIT(&sc_if->sk_jfree_listhead); 872 LIST_INIT(&sc_if->sk_jinuse_listhead); 873 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 874 875 /* 876 * Now divide it up into 9K pieces and save the addresses 877 * in an array. 878 */ 879 ptr = sc_if->sk_cdata.sk_jumbo_buf; 880 for (i = 0; i < SK_JSLOTS; i++) { 881 sc_if->sk_cdata.sk_jslots[i] = ptr; 882 ptr += SK_JLEN; 883 entry = malloc(sizeof(struct sk_jpool_entry), 884 M_DEVBUF, M_NOWAIT); 885 if (entry == NULL) { 886 aprint_error_dev(sc->sk_dev, 887 "no memory for jumbo buffer queue!\n"); 888 error = ENOBUFS; 889 goto out; 890 } 891 entry->slot = i; 892 if (i) 893 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 894 entry, jpool_entries); 895 else 896 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 897 entry, jpool_entries); 898 } 899 out: 900 if (error != 0) { 901 switch (state) { 902 case 4: 903 bus_dmamap_unload(sc->sc_dmatag, 904 sc_if->sk_cdata.sk_rx_jumbo_map); 905 /* FALLTHROUGH */ 906 case 3: 907 bus_dmamap_destroy(sc->sc_dmatag, 908 sc_if->sk_cdata.sk_rx_jumbo_map); 909 /* FALLTHROUGH */ 910 case 2: 911 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 912 /* FALLTHROUGH */ 913 case 1: 914 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 915 break; 916 default: 917 break; 918 } 919 } 920 921 return error; 922 } 923 924 /* 925 * Allocate a jumbo buffer. 926 */ 927 void * 928 sk_jalloc(struct sk_if_softc *sc_if) 929 { 930 struct sk_jpool_entry *entry; 931 932 mutex_enter(&sc_if->sk_jpool_mtx); 933 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 934 935 if (entry == NULL) { 936 mutex_exit(&sc_if->sk_jpool_mtx); 937 return NULL; 938 } 939 940 LIST_REMOVE(entry, jpool_entries); 941 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 942 mutex_exit(&sc_if->sk_jpool_mtx); 943 return sc_if->sk_cdata.sk_jslots[entry->slot]; 944 } 945 946 /* 947 * Release a jumbo buffer. 948 */ 949 void 950 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 951 { 952 struct sk_jpool_entry *entry; 953 struct sk_if_softc *sc; 954 int i; 955 956 /* Extract the softc struct pointer. */ 957 sc = (struct sk_if_softc *)arg; 958 959 if (sc == NULL) 960 panic("sk_jfree: can't find softc pointer!"); 961 962 /* calculate the slot this buffer belongs to */ 963 964 i = ((vaddr_t)buf 965 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 966 967 if ((i < 0) || (i >= SK_JSLOTS)) 968 panic("sk_jfree: asked to free buffer that we don't manage!"); 969 970 mutex_enter(&sc->sk_jpool_mtx); 971 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 972 if (entry == NULL) 973 panic("sk_jfree: buffer not in use!"); 974 entry->slot = i; 975 LIST_REMOVE(entry, jpool_entries); 976 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 977 mutex_exit(&sc->sk_jpool_mtx); 978 979 if (__predict_true(m != NULL)) 980 pool_cache_put(mb_cache, m); 981 } 982 983 /* 984 * Set media options. 985 */ 986 int 987 sk_ifmedia_upd(struct ifnet *ifp) 988 { 989 struct sk_if_softc *sc_if = ifp->if_softc; 990 int rc; 991 992 (void) sk_init(ifp); 993 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 994 return 0; 995 return rc; 996 } 997 998 static void 999 sk_promisc(struct sk_if_softc *sc_if, int on) 1000 { 1001 struct sk_softc *sc = sc_if->sk_softc; 1002 switch (sc->sk_type) { 1003 case SK_GENESIS: 1004 if (on) 1005 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1006 else 1007 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1008 break; 1009 case SK_YUKON: 1010 case SK_YUKON_LITE: 1011 case SK_YUKON_LP: 1012 if (on) 1013 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1014 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1015 else 1016 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1017 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1018 break; 1019 default: 1020 aprint_error_dev(sc_if->sk_dev, "Can't set promisc for %d\n", 1021 sc->sk_type); 1022 break; 1023 } 1024 } 1025 1026 int 1027 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 1028 { 1029 struct sk_if_softc *sc_if = ifp->if_softc; 1030 int s, error = 0; 1031 1032 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1033 1034 s = splnet(); 1035 1036 switch (command) { 1037 1038 case SIOCSIFFLAGS: 1039 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1040 if ((error = ifioctl_common(ifp, command, data)) != 0) 1041 break; 1042 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1043 case IFF_RUNNING: 1044 sk_stop(ifp, 1); 1045 break; 1046 case IFF_UP: 1047 sk_init(ifp); 1048 break; 1049 case IFF_UP | IFF_RUNNING: 1050 if ((ifp->if_flags ^ sc_if->sk_if_flags) == IFF_PROMISC) { 1051 sk_promisc(sc_if, ifp->if_flags & IFF_PROMISC); 1052 sk_setmulti(sc_if); 1053 } else 1054 sk_init(ifp); 1055 break; 1056 } 1057 sc_if->sk_if_flags = ifp->if_flags; 1058 error = 0; 1059 break; 1060 1061 default: 1062 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1063 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1064 break; 1065 1066 error = 0; 1067 1068 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1069 ; 1070 else if (ifp->if_flags & IFF_RUNNING) { 1071 sk_setmulti(sc_if); 1072 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1073 } 1074 break; 1075 } 1076 1077 splx(s); 1078 return error; 1079 } 1080 1081 void 1082 sk_update_int_mod(struct sk_softc *sc) 1083 { 1084 uint32_t imtimer_ticks; 1085 1086 /* 1087 * Configure interrupt moderation. The moderation timer 1088 * defers interrupts specified in the interrupt moderation 1089 * timer mask based on the timeout specified in the interrupt 1090 * moderation timer init register. Each bit in the timer 1091 * register represents one tick, so to specify a timeout in 1092 * microseconds, we have to multiply by the correct number of 1093 * ticks-per-microsecond. 1094 */ 1095 switch (sc->sk_type) { 1096 case SK_GENESIS: 1097 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1098 break; 1099 case SK_YUKON_EC: 1100 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1101 break; 1102 default: 1103 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1104 } 1105 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1106 sc->sk_int_mod); 1107 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1108 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF | 1109 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF); 1110 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1111 sc->sk_int_mod_pending = 0; 1112 } 1113 1114 /* 1115 * Lookup: Check the PCI vendor and device, and return a pointer to 1116 * The structure if the IDs match against our list. 1117 */ 1118 1119 static const struct sk_product * 1120 sk_lookup(const struct pci_attach_args *pa) 1121 { 1122 const struct sk_product *psk; 1123 1124 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1125 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1126 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1127 return psk; 1128 } 1129 return NULL; 1130 } 1131 1132 /* 1133 * Probe for a SysKonnect GEnesis chip. 1134 */ 1135 1136 int 1137 skc_probe(device_t parent, cfdata_t match, void *aux) 1138 { 1139 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1140 const struct sk_product *psk; 1141 pcireg_t subid; 1142 1143 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1144 1145 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1146 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1147 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1148 subid == SK_LINKSYS_EG1032_SUBID) 1149 return 1; 1150 1151 if ((psk = sk_lookup(pa))) { 1152 return 1; 1153 } 1154 return 0; 1155 } 1156 1157 /* 1158 * Force the GEnesis into reset, then bring it out of reset. 1159 */ 1160 void sk_reset(struct sk_softc *sc) 1161 { 1162 DPRINTFN(2, ("sk_reset\n")); 1163 1164 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1165 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1166 if (SK_YUKON_FAMILY(sc->sk_type)) 1167 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1168 1169 DELAY(1000); 1170 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1171 DELAY(2); 1172 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1173 if (SK_YUKON_FAMILY(sc->sk_type)) 1174 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1175 1176 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1177 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1178 CSR_READ_2(sc, SK_LINK_CTRL))); 1179 1180 if (sc->sk_type == SK_GENESIS) { 1181 /* Configure packet arbiter */ 1182 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1183 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1184 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1185 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1186 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1187 } 1188 1189 /* Enable RAM interface */ 1190 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1191 1192 sk_update_int_mod(sc); 1193 } 1194 1195 int 1196 sk_probe(device_t parent, cfdata_t match, void *aux) 1197 { 1198 struct skc_attach_args *sa = aux; 1199 1200 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1201 return 0; 1202 1203 return 1; 1204 } 1205 1206 /* 1207 * Each XMAC chip is attached as a separate logical IP interface. 1208 * Single port cards will have only one logical interface of course. 1209 */ 1210 void 1211 sk_attach(device_t parent, device_t self, void *aux) 1212 { 1213 struct sk_if_softc *sc_if = device_private(self); 1214 struct sk_softc *sc = device_private(parent); 1215 struct skc_attach_args *sa = aux; 1216 struct sk_txmap_entry *entry; 1217 struct ifnet *ifp; 1218 bus_dma_segment_t seg; 1219 bus_dmamap_t dmamap; 1220 prop_data_t data; 1221 void *kva; 1222 int i, rseg; 1223 int mii_flags = 0; 1224 1225 aprint_naive("\n"); 1226 1227 sc_if->sk_dev = self; 1228 sc_if->sk_port = sa->skc_port; 1229 sc_if->sk_softc = sc; 1230 sc->sk_if[sa->skc_port] = sc_if; 1231 1232 if (sa->skc_port == SK_PORT_A) 1233 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1234 if (sa->skc_port == SK_PORT_B) 1235 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1236 1237 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1238 1239 /* 1240 * Get station address for this interface. Note that 1241 * dual port cards actually come with three station 1242 * addresses: one for each port, plus an extra. The 1243 * extra one is used by the SysKonnect driver software 1244 * as a 'virtual' station address for when both ports 1245 * are operating in failover mode. Currently we don't 1246 * use this extra address. 1247 */ 1248 data = prop_dictionary_get(device_properties(self), "mac-address"); 1249 if (data != NULL) { 1250 /* 1251 * Try to get the station address from device properties 1252 * first, in case the ROM is missing. 1253 */ 1254 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 1255 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 1256 memcpy(sc_if->sk_enaddr, prop_data_data_nocopy(data), 1257 ETHER_ADDR_LEN); 1258 } else 1259 for (i = 0; i < ETHER_ADDR_LEN; i++) 1260 sc_if->sk_enaddr[i] = sk_win_read_1(sc, 1261 SK_MAC0_0 + (sa->skc_port * 8) + i); 1262 1263 aprint_normal(": Ethernet address %s\n", 1264 ether_sprintf(sc_if->sk_enaddr)); 1265 1266 /* 1267 * Set up RAM buffer addresses. The NIC will have a certain 1268 * amount of SRAM on it, somewhere between 512K and 2MB. We 1269 * need to divide this up a) between the transmitter and 1270 * receiver and b) between the two XMACs, if this is a 1271 * dual port NIC. Our algorithm is to divide up the memory 1272 * evenly so that everyone gets a fair share. 1273 */ 1274 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1275 uint32_t chunk, val; 1276 1277 chunk = sc->sk_ramsize / 2; 1278 val = sc->sk_rboff / sizeof(uint64_t); 1279 sc_if->sk_rx_ramstart = val; 1280 val += (chunk / sizeof(uint64_t)); 1281 sc_if->sk_rx_ramend = val - 1; 1282 sc_if->sk_tx_ramstart = val; 1283 val += (chunk / sizeof(uint64_t)); 1284 sc_if->sk_tx_ramend = val - 1; 1285 } else { 1286 uint32_t chunk, val; 1287 1288 chunk = sc->sk_ramsize / 4; 1289 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1290 sizeof(uint64_t); 1291 sc_if->sk_rx_ramstart = val; 1292 val += (chunk / sizeof(uint64_t)); 1293 sc_if->sk_rx_ramend = val - 1; 1294 sc_if->sk_tx_ramstart = val; 1295 val += (chunk / sizeof(uint64_t)); 1296 sc_if->sk_tx_ramend = val - 1; 1297 } 1298 1299 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1300 " tx_ramstart=%#x tx_ramend=%#x\n", 1301 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1302 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1303 1304 /* Read and save PHY type and set PHY address */ 1305 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1306 switch (sc_if->sk_phytype) { 1307 case SK_PHYTYPE_XMAC: 1308 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1309 break; 1310 case SK_PHYTYPE_BCOM: 1311 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1312 break; 1313 case SK_PHYTYPE_MARV_COPPER: 1314 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1315 break; 1316 default: 1317 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1318 sc_if->sk_phytype); 1319 return; 1320 } 1321 1322 /* Allocate the descriptor queues. */ 1323 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1324 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1325 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1326 goto fail; 1327 } 1328 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1329 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1330 aprint_error_dev(sc_if->sk_dev, 1331 "can't map dma buffers (%lu bytes)\n", 1332 (u_long) sizeof(struct sk_ring_data)); 1333 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1334 goto fail; 1335 } 1336 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1337 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1338 &sc_if->sk_ring_map)) { 1339 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1340 bus_dmamem_unmap(sc->sc_dmatag, kva, 1341 sizeof(struct sk_ring_data)); 1342 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1343 goto fail; 1344 } 1345 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1346 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1347 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1348 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1349 bus_dmamem_unmap(sc->sc_dmatag, kva, 1350 sizeof(struct sk_ring_data)); 1351 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1352 goto fail; 1353 } 1354 1355 for (i = 0; i < SK_RX_RING_CNT; i++) 1356 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1357 1358 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1359 for (i = 0; i < SK_TX_RING_CNT; i++) { 1360 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1361 1362 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1363 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1364 aprint_error_dev(sc_if->sk_dev, 1365 "Can't create TX dmamap\n"); 1366 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1367 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1368 bus_dmamem_unmap(sc->sc_dmatag, kva, 1369 sizeof(struct sk_ring_data)); 1370 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1371 goto fail; 1372 } 1373 1374 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1375 if (!entry) { 1376 aprint_error_dev(sc_if->sk_dev, 1377 "Can't alloc txmap entry\n"); 1378 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1379 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1380 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1381 bus_dmamem_unmap(sc->sc_dmatag, kva, 1382 sizeof(struct sk_ring_data)); 1383 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1384 goto fail; 1385 } 1386 entry->dmamap = dmamap; 1387 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1388 } 1389 1390 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1391 memset(sc_if->sk_rdata, 0, sizeof(struct sk_ring_data)); 1392 1393 ifp = &sc_if->sk_ethercom.ec_if; 1394 /* Try to allocate memory for jumbo buffers. */ 1395 if (sk_alloc_jumbo_mem(sc_if)) { 1396 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1397 goto fail; 1398 } 1399 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1400 | ETHERCAP_JUMBO_MTU; 1401 1402 ifp->if_softc = sc_if; 1403 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1404 ifp->if_ioctl = sk_ioctl; 1405 ifp->if_start = sk_start; 1406 ifp->if_stop = sk_stop; 1407 ifp->if_init = sk_init; 1408 ifp->if_watchdog = sk_watchdog; 1409 ifp->if_capabilities = 0; 1410 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1411 IFQ_SET_READY(&ifp->if_snd); 1412 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1413 1414 /* 1415 * Do miibus setup. 1416 */ 1417 switch (sc->sk_type) { 1418 case SK_GENESIS: 1419 sk_init_xmac(sc_if); 1420 break; 1421 case SK_YUKON: 1422 case SK_YUKON_LITE: 1423 case SK_YUKON_LP: 1424 sk_init_yukon(sc_if); 1425 break; 1426 default: 1427 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1428 sc->sk_type); 1429 goto fail; 1430 } 1431 1432 DPRINTFN(2, ("sk_attach: 1\n")); 1433 1434 sc_if->sk_mii.mii_ifp = ifp; 1435 switch (sc->sk_type) { 1436 case SK_GENESIS: 1437 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1438 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1439 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1440 break; 1441 case SK_YUKON: 1442 case SK_YUKON_LITE: 1443 case SK_YUKON_LP: 1444 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1445 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1446 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1447 mii_flags = MIIF_DOPAUSE; 1448 break; 1449 } 1450 1451 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1452 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1453 sk_ifmedia_upd, ether_mediastatus); 1454 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1455 MII_OFFSET_ANY, mii_flags); 1456 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1457 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1458 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER | IFM_MANUAL, 1459 0, NULL); 1460 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER | IFM_MANUAL); 1461 } else 1462 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER | IFM_AUTO); 1463 1464 callout_init(&sc_if->sk_tick_ch, 0); 1465 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1466 1467 DPRINTFN(2, ("sk_attach: 1\n")); 1468 1469 /* 1470 * Call MI attach routines. 1471 */ 1472 if_attach(ifp); 1473 if_deferred_start_init(ifp, NULL); 1474 1475 ether_ifattach(ifp, sc_if->sk_enaddr); 1476 1477 if (sc->rnd_attached++ == 0) { 1478 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1479 RND_TYPE_NET, RND_FLAG_DEFAULT); 1480 } 1481 1482 if (pmf_device_register(self, NULL, sk_resume)) 1483 pmf_class_network_register(self, ifp); 1484 else 1485 aprint_error_dev(self, "couldn't establish power handler\n"); 1486 1487 DPRINTFN(2, ("sk_attach: end\n")); 1488 1489 return; 1490 1491 fail: 1492 sc->sk_if[sa->skc_port] = NULL; 1493 } 1494 1495 int 1496 skcprint(void *aux, const char *pnp) 1497 { 1498 struct skc_attach_args *sa = aux; 1499 1500 if (pnp) 1501 aprint_normal("sk port %c at %s", 1502 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1503 else 1504 aprint_normal(" port %c", 1505 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1506 return UNCONF; 1507 } 1508 1509 /* 1510 * Attach the interface. Allocate softc structures, do ifmedia 1511 * setup and ethernet/BPF attach. 1512 */ 1513 void 1514 skc_attach(device_t parent, device_t self, void *aux) 1515 { 1516 struct sk_softc *sc = device_private(self); 1517 struct pci_attach_args *pa = aux; 1518 struct skc_attach_args skca; 1519 pci_chipset_tag_t pc = pa->pa_pc; 1520 #ifndef SK_USEIOSPACE 1521 pcireg_t memtype; 1522 #endif 1523 pci_intr_handle_t ih; 1524 const char *intrstr = NULL; 1525 bus_addr_t iobase; 1526 bus_size_t iosize; 1527 int rc, sk_nodenum; 1528 uint32_t command; 1529 const char *revstr; 1530 const struct sysctlnode *node; 1531 char intrbuf[PCI_INTRSTR_LEN]; 1532 1533 sc->sk_dev = self; 1534 aprint_naive("\n"); 1535 1536 DPRINTFN(2, ("begin skc_attach\n")); 1537 1538 /* 1539 * Handle power management nonsense. 1540 */ 1541 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1542 1543 if (command == 0x01) { 1544 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1545 if (command & SK_PSTATE_MASK) { 1546 uint32_t xiobase, membase, irq; 1547 1548 /* Save important PCI config data. */ 1549 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1550 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1551 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1552 1553 /* Reset the power state. */ 1554 aprint_normal_dev(sc->sk_dev, 1555 "chip is in D%d power mode -- setting to D0\n", 1556 command & SK_PSTATE_MASK); 1557 command &= 0xFFFFFFFC; 1558 pci_conf_write(pc, pa->pa_tag, 1559 SK_PCI_PWRMGMTCTRL, command); 1560 1561 /* Restore PCI config data. */ 1562 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1563 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1564 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1565 } 1566 } 1567 1568 /* 1569 * The firmware might have configured the interface to revert the 1570 * byte order in all descriptors. Make that undone. 1571 */ 1572 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_OURREG2); 1573 if (command & SK_REG2_REV_DESC) 1574 pci_conf_write(pc, pa->pa_tag, SK_PCI_OURREG2, 1575 command & ~SK_REG2_REV_DESC); 1576 1577 /* 1578 * Map control/status registers. 1579 */ 1580 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1581 command |= PCI_COMMAND_IO_ENABLE | 1582 PCI_COMMAND_MEM_ENABLE | 1583 PCI_COMMAND_MASTER_ENABLE; 1584 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1585 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1586 1587 #ifdef SK_USEIOSPACE 1588 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1589 aprint_error(": failed to enable I/O ports!\n"); 1590 return; 1591 } 1592 /* 1593 * Map control/status registers. 1594 */ 1595 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1596 &sc->sk_btag, &sc->sk_bhandle, 1597 &iobase, &iosize)) { 1598 aprint_error(": can't find i/o space\n"); 1599 return; 1600 } 1601 #else 1602 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1603 aprint_error(": failed to enable memory mapping!\n"); 1604 return; 1605 } 1606 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1607 switch (memtype) { 1608 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1609 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1610 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1611 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1612 &iobase, &iosize) == 0) 1613 break; 1614 /* FALLTHROUGH */ 1615 default: 1616 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1617 return; 1618 } 1619 1620 DPRINTFN(2, ("skc_attach: iobase=%#" PRIxPADDR ", iosize=%zx\n", 1621 iobase, iosize)); 1622 #endif 1623 sc->sc_dmatag = pa->pa_dmat; 1624 1625 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1626 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1627 1628 /* bail out here if chip is not recognized */ 1629 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1630 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1631 goto fail; 1632 } 1633 if (SK_IS_YUKON2(sc)) { 1634 aprint_error_dev(sc->sk_dev, 1635 "Does not support Yukon2--try msk(4).\n"); 1636 goto fail; 1637 } 1638 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1639 1640 /* Allocate interrupt */ 1641 if (pci_intr_map(pa, &ih)) { 1642 aprint_error(": couldn't map interrupt\n"); 1643 goto fail; 1644 } 1645 1646 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1647 sc->sk_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, sk_intr, sc, 1648 device_xname(sc->sk_dev)); 1649 if (sc->sk_intrhand == NULL) { 1650 aprint_error(": couldn't establish interrupt"); 1651 if (intrstr != NULL) 1652 aprint_error(" at %s", intrstr); 1653 aprint_error("\n"); 1654 goto fail; 1655 } 1656 aprint_normal(": %s\n", intrstr); 1657 1658 /* Reset the adapter. */ 1659 sk_reset(sc); 1660 1661 /* Read and save vital product data from EEPROM. */ 1662 sk_vpd_read(sc); 1663 1664 if (sc->sk_type == SK_GENESIS) { 1665 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1666 /* Read and save RAM size and RAMbuffer offset */ 1667 switch (val) { 1668 case SK_RAMSIZE_512K_64: 1669 sc->sk_ramsize = 0x80000; 1670 sc->sk_rboff = SK_RBOFF_0; 1671 break; 1672 case SK_RAMSIZE_1024K_64: 1673 sc->sk_ramsize = 0x100000; 1674 sc->sk_rboff = SK_RBOFF_80000; 1675 break; 1676 case SK_RAMSIZE_1024K_128: 1677 sc->sk_ramsize = 0x100000; 1678 sc->sk_rboff = SK_RBOFF_0; 1679 break; 1680 case SK_RAMSIZE_2048K_128: 1681 sc->sk_ramsize = 0x200000; 1682 sc->sk_rboff = SK_RBOFF_0; 1683 break; 1684 default: 1685 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1686 val); 1687 goto fail_1; 1688 break; 1689 } 1690 1691 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1692 sc->sk_ramsize, sc->sk_ramsize / 1024, 1693 sc->sk_rboff)); 1694 } else { 1695 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1696 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1697 sc->sk_rboff = SK_RBOFF_0; 1698 1699 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1700 sc->sk_ramsize / 1024, sc->sk_ramsize, 1701 sc->sk_rboff)); 1702 } 1703 1704 /* Read and save physical media type */ 1705 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1706 case SK_PMD_1000BASESX: 1707 sc->sk_pmd = IFM_1000_SX; 1708 break; 1709 case SK_PMD_1000BASELX: 1710 sc->sk_pmd = IFM_1000_LX; 1711 break; 1712 case SK_PMD_1000BASECX: 1713 sc->sk_pmd = IFM_1000_CX; 1714 break; 1715 case SK_PMD_1000BASETX: 1716 case SK_PMD_1000BASETX_ALT: 1717 sc->sk_pmd = IFM_1000_T; 1718 break; 1719 default: 1720 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1721 sk_win_read_1(sc, SK_PMDTYPE)); 1722 goto fail_1; 1723 } 1724 1725 /* determine whether to name it with vpd or just make it up */ 1726 /* Marvell Yukon VPD's can freqently be bogus */ 1727 1728 switch (pa->pa_id) { 1729 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1730 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1731 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1732 case PCI_PRODUCT_3COM_3C940: 1733 case PCI_PRODUCT_DLINK_DGE530T: 1734 case PCI_PRODUCT_DLINK_DGE560T: 1735 case PCI_PRODUCT_DLINK_DGE560T_2: 1736 case PCI_PRODUCT_LINKSYS_EG1032: 1737 case PCI_PRODUCT_LINKSYS_EG1064: 1738 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1739 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1740 case PCI_ID_CODE(PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940): 1741 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T): 1742 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T): 1743 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2): 1744 case PCI_ID_CODE(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032): 1745 case PCI_ID_CODE(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064): 1746 sc->sk_name = sc->sk_vpd_prodname; 1747 break; 1748 case PCI_ID_CODE(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET): 1749 /* whoops yukon vpd prodname bears no resemblance to reality */ 1750 switch (sc->sk_type) { 1751 case SK_GENESIS: 1752 sc->sk_name = sc->sk_vpd_prodname; 1753 break; 1754 case SK_YUKON: 1755 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1756 break; 1757 case SK_YUKON_LITE: 1758 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1759 break; 1760 case SK_YUKON_LP: 1761 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1762 break; 1763 default: 1764 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1765 } 1766 1767 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1768 1769 if ( sc->sk_type == SK_YUKON ) { 1770 uint32_t flashaddr; 1771 uint8_t testbyte; 1772 1773 flashaddr = sk_win_read_4(sc, SK_EP_ADDR); 1774 1775 /* test Flash-Address Register */ 1776 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff); 1777 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1778 1779 if (testbyte != 0) { 1780 /* this is yukon lite Rev. A0 */ 1781 sc->sk_type = SK_YUKON_LITE; 1782 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1783 /* restore Flash-Address Register */ 1784 sk_win_write_4(sc, SK_EP_ADDR, flashaddr); 1785 } 1786 } 1787 break; 1788 case PCI_ID_CODE(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN): 1789 sc->sk_name = sc->sk_vpd_prodname; 1790 break; 1791 default: 1792 sc->sk_name = "Unknown Marvell"; 1793 } 1794 1795 1796 if ( sc->sk_type == SK_YUKON_LITE ) { 1797 switch (sc->sk_rev) { 1798 case SK_YUKON_LITE_REV_A0: 1799 revstr = "A0"; 1800 break; 1801 case SK_YUKON_LITE_REV_A1: 1802 revstr = "A1"; 1803 break; 1804 case SK_YUKON_LITE_REV_A3: 1805 revstr = "A3"; 1806 break; 1807 default: 1808 revstr = ""; 1809 } 1810 } else { 1811 revstr = ""; 1812 } 1813 1814 /* Announce the product name. */ 1815 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1816 sc->sk_name, revstr, sc->sk_rev); 1817 1818 skca.skc_port = SK_PORT_A; 1819 (void)config_found(sc->sk_dev, &skca, skcprint); 1820 1821 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1822 skca.skc_port = SK_PORT_B; 1823 (void)config_found(sc->sk_dev, &skca, skcprint); 1824 } 1825 1826 /* Turn on the 'driver is loaded' LED. */ 1827 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1828 1829 /* skc sysctl setup */ 1830 1831 sc->sk_int_mod = SK_IM_DEFAULT; 1832 sc->sk_int_mod_pending = 0; 1833 1834 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1835 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1836 SYSCTL_DESCR("skc per-controller controls"), 1837 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1838 CTL_EOL)) != 0) { 1839 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1840 goto fail_1; 1841 } 1842 1843 sk_nodenum = node->sysctl_num; 1844 1845 /* interrupt moderation time in usecs */ 1846 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1847 CTLFLAG_READWRITE, 1848 CTLTYPE_INT, "int_mod", 1849 SYSCTL_DESCR("sk interrupt moderation timer"), 1850 sk_sysctl_handler, 0, (void *)sc, 1851 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1852 CTL_EOL)) != 0) { 1853 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1854 goto fail_1; 1855 } 1856 1857 if (!pmf_device_register(self, skc_suspend, skc_resume)) 1858 aprint_error_dev(self, "couldn't establish power handler\n"); 1859 1860 return; 1861 1862 fail_1: 1863 pci_intr_disestablish(pc, sc->sk_intrhand); 1864 fail: 1865 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1866 } 1867 1868 int 1869 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1870 { 1871 struct sk_softc *sc = sc_if->sk_softc; 1872 struct sk_tx_desc *f = NULL; 1873 uint32_t frag, cur, cnt = 0, sk_ctl; 1874 int i; 1875 struct sk_txmap_entry *entry; 1876 bus_dmamap_t txmap; 1877 1878 DPRINTFN(3, ("sk_encap\n")); 1879 1880 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1881 if (entry == NULL) { 1882 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1883 return ENOBUFS; 1884 } 1885 txmap = entry->dmamap; 1886 1887 cur = frag = *txidx; 1888 1889 #ifdef SK_DEBUG 1890 if (skdebug >= 3) 1891 sk_dump_mbuf(m_head); 1892 #endif 1893 1894 /* 1895 * Start packing the mbufs in this chain into 1896 * the fragment pointers. Stop when we run out 1897 * of fragments or hit the end of the mbuf chain. 1898 */ 1899 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1900 BUS_DMA_NOWAIT)) { 1901 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1902 return ENOBUFS; 1903 } 1904 1905 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1906 1907 /* Sync the DMA map. */ 1908 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1909 BUS_DMASYNC_PREWRITE); 1910 1911 for (i = 0; i < txmap->dm_nsegs; i++) { 1912 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1913 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1914 return ENOBUFS; 1915 } 1916 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1917 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1918 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1919 if (cnt == 0) 1920 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1921 else 1922 sk_ctl |= SK_TXCTL_OWN; 1923 f->sk_ctl = htole32(sk_ctl); 1924 cur = frag; 1925 SK_INC(frag, SK_TX_RING_CNT); 1926 cnt++; 1927 } 1928 1929 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1930 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1931 1932 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1933 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1934 htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 1935 1936 /* Sync descriptors before handing to chip */ 1937 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1938 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1939 1940 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1941 htole32(SK_TXCTL_OWN); 1942 1943 /* Sync first descriptor to hand it off */ 1944 SK_CDTXSYNC(sc_if, *txidx, 1, 1945 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1946 1947 sc_if->sk_cdata.sk_tx_cnt += cnt; 1948 1949 #ifdef SK_DEBUG 1950 if (skdebug >= 3) { 1951 struct sk_tx_desc *desc; 1952 uint32_t idx; 1953 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1954 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1955 sk_dump_txdesc(desc, idx); 1956 } 1957 } 1958 #endif 1959 1960 *txidx = frag; 1961 1962 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1963 1964 return 0; 1965 } 1966 1967 void 1968 sk_start(struct ifnet *ifp) 1969 { 1970 struct sk_if_softc *sc_if = ifp->if_softc; 1971 struct sk_softc *sc = sc_if->sk_softc; 1972 struct mbuf *m_head = NULL; 1973 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1974 int pkts = 0; 1975 1976 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1977 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1978 1979 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1980 IFQ_POLL(&ifp->if_snd, m_head); 1981 if (m_head == NULL) 1982 break; 1983 1984 /* 1985 * Pack the data into the transmit ring. If we 1986 * don't have room, set the OACTIVE flag and wait 1987 * for the NIC to drain the ring. 1988 */ 1989 if (sk_encap(sc_if, m_head, &idx)) { 1990 ifp->if_flags |= IFF_OACTIVE; 1991 break; 1992 } 1993 1994 /* now we are committed to transmit the packet */ 1995 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1996 pkts++; 1997 1998 /* 1999 * If there's a BPF listener, bounce a copy of this frame 2000 * to him. 2001 */ 2002 bpf_mtap(ifp, m_head, BPF_D_OUT); 2003 } 2004 if (pkts == 0) 2005 return; 2006 2007 /* Transmit */ 2008 if (idx != sc_if->sk_cdata.sk_tx_prod) { 2009 sc_if->sk_cdata.sk_tx_prod = idx; 2010 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2011 2012 /* Set a timeout in case the chip goes out to lunch. */ 2013 ifp->if_timer = 5; 2014 } 2015 } 2016 2017 2018 void 2019 sk_watchdog(struct ifnet *ifp) 2020 { 2021 struct sk_if_softc *sc_if = ifp->if_softc; 2022 2023 /* 2024 * Reclaim first as there is a possibility of losing Tx completion 2025 * interrupts. 2026 */ 2027 sk_txeof(sc_if); 2028 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2029 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 2030 2031 ifp->if_oerrors++; 2032 2033 sk_init(ifp); 2034 } 2035 } 2036 2037 void 2038 sk_shutdown(void *v) 2039 { 2040 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2041 struct sk_softc *sc = sc_if->sk_softc; 2042 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2043 2044 DPRINTFN(2, ("sk_shutdown\n")); 2045 sk_stop(ifp, 1); 2046 2047 /* Turn off the 'driver is loaded' LED. */ 2048 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2049 2050 /* 2051 * Reset the GEnesis controller. Doing this should also 2052 * assert the resets on the attached XMAC(s). 2053 */ 2054 sk_reset(sc); 2055 } 2056 2057 void 2058 sk_rxeof(struct sk_if_softc *sc_if) 2059 { 2060 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2061 struct mbuf *m; 2062 struct sk_chain *cur_rx; 2063 struct sk_rx_desc *cur_desc; 2064 int i, cur, total_len = 0; 2065 uint32_t rxstat, sk_ctl; 2066 bus_dmamap_t dmamap; 2067 2068 i = sc_if->sk_cdata.sk_rx_prod; 2069 2070 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2071 2072 for (;;) { 2073 cur = i; 2074 2075 /* Sync the descriptor */ 2076 SK_CDRXSYNC(sc_if, cur, 2077 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2078 2079 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2080 if (sk_ctl & SK_RXCTL_OWN) { 2081 /* Invalidate the descriptor -- it's not ready yet */ 2082 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2083 sc_if->sk_cdata.sk_rx_prod = i; 2084 break; 2085 } 2086 2087 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2088 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2089 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2090 2091 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2092 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2093 2094 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2095 m = cur_rx->sk_mbuf; 2096 cur_rx->sk_mbuf = NULL; 2097 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2098 2099 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2100 2101 SK_INC(i, SK_RX_RING_CNT); 2102 2103 if (rxstat & XM_RXSTAT_ERRFRAME) { 2104 ifp->if_ierrors++; 2105 sk_newbuf(sc_if, cur, m, dmamap); 2106 continue; 2107 } 2108 2109 /* 2110 * Try to allocate a new jumbo buffer. If that 2111 * fails, copy the packet to mbufs and put the 2112 * jumbo buffer back in the ring so it can be 2113 * re-used. If allocating mbufs fails, then we 2114 * have to drop the packet. 2115 */ 2116 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2117 struct mbuf *m0; 2118 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2119 total_len + ETHER_ALIGN, 0, ifp); 2120 sk_newbuf(sc_if, cur, m, dmamap); 2121 if (m0 == NULL) { 2122 aprint_error_dev(sc_if->sk_dev, "no receive " 2123 "buffers available -- packet dropped!\n"); 2124 ifp->if_ierrors++; 2125 continue; 2126 } 2127 m_adj(m0, ETHER_ALIGN); 2128 m = m0; 2129 } else { 2130 m_set_rcvif(m, ifp); 2131 m->m_pkthdr.len = m->m_len = total_len; 2132 } 2133 2134 /* pass it on. */ 2135 if_percpuq_enqueue(ifp->if_percpuq, m); 2136 } 2137 } 2138 2139 void 2140 sk_txeof(struct sk_if_softc *sc_if) 2141 { 2142 struct sk_softc *sc = sc_if->sk_softc; 2143 struct sk_tx_desc *cur_tx; 2144 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2145 uint32_t idx, sk_ctl; 2146 struct sk_txmap_entry *entry; 2147 2148 DPRINTFN(3, ("sk_txeof\n")); 2149 2150 /* 2151 * Go through our tx ring and free mbufs for those 2152 * frames that have been sent. 2153 */ 2154 idx = sc_if->sk_cdata.sk_tx_cons; 2155 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2156 SK_CDTXSYNC(sc_if, idx, 1, 2157 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2158 2159 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2160 sk_ctl = le32toh(cur_tx->sk_ctl); 2161 #ifdef SK_DEBUG 2162 if (skdebug >= 3) 2163 sk_dump_txdesc(cur_tx, idx); 2164 #endif 2165 if (sk_ctl & SK_TXCTL_OWN) { 2166 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2167 break; 2168 } 2169 if (sk_ctl & SK_TXCTL_LASTFRAG) 2170 ifp->if_opackets++; 2171 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2172 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2173 2174 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2175 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2176 2177 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2178 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2179 2180 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2181 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2182 link); 2183 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2184 } 2185 sc_if->sk_cdata.sk_tx_cnt--; 2186 SK_INC(idx, SK_TX_RING_CNT); 2187 } 2188 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2189 ifp->if_timer = 0; 2190 else /* nudge chip to keep tx ring moving */ 2191 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2192 2193 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2194 ifp->if_flags &= ~IFF_OACTIVE; 2195 2196 sc_if->sk_cdata.sk_tx_cons = idx; 2197 } 2198 2199 void 2200 sk_tick(void *xsc_if) 2201 { 2202 struct sk_if_softc *sc_if = xsc_if; 2203 struct mii_data *mii = &sc_if->sk_mii; 2204 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2205 int i; 2206 2207 DPRINTFN(3, ("sk_tick\n")); 2208 2209 if (!(ifp->if_flags & IFF_UP)) 2210 return; 2211 2212 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2213 sk_intr_bcom(sc_if); 2214 return; 2215 } 2216 2217 /* 2218 * According to SysKonnect, the correct way to verify that 2219 * the link has come back up is to poll bit 0 of the GPIO 2220 * register three times. This pin has the signal from the 2221 * link sync pin connected to it; if we read the same link 2222 * state 3 times in a row, we know the link is up. 2223 */ 2224 for (i = 0; i < 3; i++) { 2225 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2226 break; 2227 } 2228 2229 if (i != 3) { 2230 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2231 return; 2232 } 2233 2234 /* Turn the GP0 interrupt back on. */ 2235 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2236 SK_XM_READ_2(sc_if, XM_ISR); 2237 mii_tick(mii); 2238 if (ifp->if_link_state != LINK_STATE_UP) 2239 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2240 else 2241 callout_stop(&sc_if->sk_tick_ch); 2242 } 2243 2244 void 2245 sk_intr_bcom(struct sk_if_softc *sc_if) 2246 { 2247 struct mii_data *mii = &sc_if->sk_mii; 2248 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2249 uint16_t status; 2250 2251 2252 DPRINTFN(3, ("sk_intr_bcom\n")); 2253 2254 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2255 2256 /* 2257 * Read the PHY interrupt register to make sure 2258 * we clear any pending interrupts. 2259 */ 2260 sk_xmac_miibus_readreg(sc_if->sk_dev, 2261 SK_PHYADDR_BCOM, BRGPHY_MII_ISR, &status); 2262 2263 if (!(ifp->if_flags & IFF_RUNNING)) { 2264 sk_init_xmac(sc_if); 2265 return; 2266 } 2267 2268 if (status & (BRGPHY_ISR_LNK_CHG | BRGPHY_ISR_AN_PR)) { 2269 uint16_t lstat; 2270 sk_xmac_miibus_readreg(sc_if->sk_dev, 2271 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS, &lstat); 2272 2273 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2274 (void)mii_mediachg(mii); 2275 /* Turn off the link LED. */ 2276 SK_IF_WRITE_1(sc_if, 0, 2277 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2278 sc_if->sk_link = 0; 2279 } else if (status & BRGPHY_ISR_LNK_CHG) { 2280 sk_xmac_miibus_writereg(sc_if->sk_dev, 2281 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2282 mii_tick(mii); 2283 sc_if->sk_link = 1; 2284 /* Turn on the link LED. */ 2285 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2286 SK_LINKLED_ON | SK_LINKLED_LINKSYNC_OFF | 2287 SK_LINKLED_BLINK_OFF); 2288 mii_pollstat(mii); 2289 } else { 2290 mii_tick(mii); 2291 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2292 } 2293 } 2294 2295 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2296 } 2297 2298 void 2299 sk_intr_xmac(struct sk_if_softc *sc_if) 2300 { 2301 uint16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2302 2303 DPRINTFN(3, ("sk_intr_xmac\n")); 2304 2305 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2306 if (status & XM_ISR_GP0_SET) { 2307 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2308 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2309 } 2310 2311 if (status & XM_ISR_AUTONEG_DONE) { 2312 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2313 } 2314 } 2315 2316 if (status & XM_IMR_TX_UNDERRUN) 2317 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2318 2319 if (status & XM_IMR_RX_OVERRUN) 2320 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2321 } 2322 2323 void 2324 sk_intr_yukon(struct sk_if_softc *sc_if) 2325 { 2326 #ifdef SK_DEBUG 2327 int status; 2328 2329 status = 2330 #endif 2331 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2332 2333 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2334 } 2335 2336 int 2337 sk_intr(void *xsc) 2338 { 2339 struct sk_softc *sc = xsc; 2340 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2341 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2342 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2343 uint32_t status; 2344 int claimed = 0; 2345 2346 if (sc_if0 != NULL) 2347 ifp0 = &sc_if0->sk_ethercom.ec_if; 2348 if (sc_if1 != NULL) 2349 ifp1 = &sc_if1->sk_ethercom.ec_if; 2350 2351 for (;;) { 2352 status = CSR_READ_4(sc, SK_ISSR); 2353 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2354 2355 if (!(status & sc->sk_intrmask)) 2356 break; 2357 2358 claimed = 1; 2359 2360 /* Handle receive interrupts first. */ 2361 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2362 sk_rxeof(sc_if0); 2363 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2364 SK_RXBMU_CLR_IRQ_EOF | SK_RXBMU_RX_START); 2365 } 2366 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2367 sk_rxeof(sc_if1); 2368 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2369 SK_RXBMU_CLR_IRQ_EOF | SK_RXBMU_RX_START); 2370 } 2371 2372 /* Then transmit interrupts. */ 2373 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2374 sk_txeof(sc_if0); 2375 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2376 SK_TXBMU_CLR_IRQ_EOF); 2377 } 2378 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2379 sk_txeof(sc_if1); 2380 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2381 SK_TXBMU_CLR_IRQ_EOF); 2382 } 2383 2384 /* Then MAC interrupts. */ 2385 if (sc_if0 && (status & SK_ISR_MAC1) && 2386 (ifp0->if_flags & IFF_RUNNING)) { 2387 if (sc->sk_type == SK_GENESIS) 2388 sk_intr_xmac(sc_if0); 2389 else 2390 sk_intr_yukon(sc_if0); 2391 } 2392 2393 if (sc_if1 && (status & SK_ISR_MAC2) && 2394 (ifp1->if_flags & IFF_RUNNING)) { 2395 if (sc->sk_type == SK_GENESIS) 2396 sk_intr_xmac(sc_if1); 2397 else 2398 sk_intr_yukon(sc_if1); 2399 2400 } 2401 2402 if (status & SK_ISR_EXTERNAL_REG) { 2403 if (sc_if0 != NULL && 2404 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2405 sk_intr_bcom(sc_if0); 2406 2407 if (sc_if1 != NULL && 2408 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2409 sk_intr_bcom(sc_if1); 2410 } 2411 } 2412 2413 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2414 2415 if (ifp0 != NULL) 2416 if_schedule_deferred_start(ifp0); 2417 if (ifp1 != NULL) 2418 if_schedule_deferred_start(ifp1); 2419 2420 KASSERT(sc->rnd_attached > 0); 2421 rnd_add_uint32(&sc->rnd_source, status); 2422 2423 if (sc->sk_int_mod_pending) 2424 sk_update_int_mod(sc); 2425 2426 return claimed; 2427 } 2428 2429 void 2430 sk_init_xmac(struct sk_if_softc *sc_if) 2431 { 2432 struct sk_softc *sc = sc_if->sk_softc; 2433 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2434 static const struct sk_bcom_hack bhack[] = { 2435 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2436 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2437 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2438 { 0, 0 } }; 2439 2440 DPRINTFN(1, ("sk_init_xmac\n")); 2441 2442 /* Unreset the XMAC. */ 2443 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2444 DELAY(1000); 2445 2446 /* Reset the XMAC's internal state. */ 2447 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2448 2449 /* Save the XMAC II revision */ 2450 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2451 2452 /* 2453 * Perform additional initialization for external PHYs, 2454 * namely for the 1000baseTX cards that use the XMAC's 2455 * GMII mode. 2456 */ 2457 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2458 int i = 0; 2459 uint32_t val; 2460 uint16_t phyval; 2461 2462 /* Take PHY out of reset. */ 2463 val = sk_win_read_4(sc, SK_GPIO); 2464 if (sc_if->sk_port == SK_PORT_A) 2465 val |= SK_GPIO_DIR0 | SK_GPIO_DAT0; 2466 else 2467 val |= SK_GPIO_DIR2 | SK_GPIO_DAT2; 2468 sk_win_write_4(sc, SK_GPIO, val); 2469 2470 /* Enable GMII mode on the XMAC. */ 2471 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2472 2473 sk_xmac_miibus_writereg(sc_if->sk_dev, 2474 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2475 DELAY(10000); 2476 sk_xmac_miibus_writereg(sc_if->sk_dev, 2477 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2478 2479 /* 2480 * Early versions of the BCM5400 apparently have 2481 * a bug that requires them to have their reserved 2482 * registers initialized to some magic values. I don't 2483 * know what the numbers do, I'm just the messenger. 2484 */ 2485 sk_xmac_miibus_readreg(sc_if->sk_dev, 2486 SK_PHYADDR_BCOM, 0x03, &phyval); 2487 if (phyval == 0x6041) { 2488 while (bhack[i].reg) { 2489 sk_xmac_miibus_writereg(sc_if->sk_dev, 2490 SK_PHYADDR_BCOM, bhack[i].reg, 2491 bhack[i].val); 2492 i++; 2493 } 2494 } 2495 } 2496 2497 /* Set station address */ 2498 SK_XM_WRITE_2(sc_if, XM_PAR0, 2499 *(uint16_t *)(&sc_if->sk_enaddr[0])); 2500 SK_XM_WRITE_2(sc_if, XM_PAR1, 2501 *(uint16_t *)(&sc_if->sk_enaddr[2])); 2502 SK_XM_WRITE_2(sc_if, XM_PAR2, 2503 *(uint16_t *)(&sc_if->sk_enaddr[4])); 2504 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2505 2506 if (ifp->if_flags & IFF_PROMISC) 2507 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2508 else 2509 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2510 2511 if (ifp->if_flags & IFF_BROADCAST) 2512 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2513 else 2514 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2515 2516 /* We don't need the FCS appended to the packet. */ 2517 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2518 2519 /* We want short frames padded to 60 bytes. */ 2520 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2521 2522 /* 2523 * Enable the reception of all error frames. This is is 2524 * a necessary evil due to the design of the XMAC. The 2525 * XMAC's receive FIFO is only 8K in size, however jumbo 2526 * frames can be up to 9000 bytes in length. When bad 2527 * frame filtering is enabled, the XMAC's RX FIFO operates 2528 * in 'store and forward' mode. For this to work, the 2529 * entire frame has to fit into the FIFO, but that means 2530 * that jumbo frames larger than 8192 bytes will be 2531 * truncated. Disabling all bad frame filtering causes 2532 * the RX FIFO to operate in streaming mode, in which 2533 * case the XMAC will start transfering frames out of the 2534 * RX FIFO as soon as the FIFO threshold is reached. 2535 */ 2536 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES | 2537 XM_MODE_RX_GIANTS | XM_MODE_RX_RUNTS | XM_MODE_RX_CRCERRS | 2538 XM_MODE_RX_INRANGELEN); 2539 2540 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2541 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2542 else 2543 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2544 2545 /* 2546 * Bump up the transmit threshold. This helps hold off transmit 2547 * underruns when we're blasting traffic from both ports at once. 2548 */ 2549 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2550 2551 /* Set multicast filter */ 2552 sk_setmulti(sc_if); 2553 2554 /* Clear and enable interrupts */ 2555 SK_XM_READ_2(sc_if, XM_ISR); 2556 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2557 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2558 else 2559 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2560 2561 /* Configure MAC arbiter */ 2562 switch (sc_if->sk_xmac_rev) { 2563 case XM_XMAC_REV_B2: 2564 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2565 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2566 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2567 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2568 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2569 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2570 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2571 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2572 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2573 break; 2574 case XM_XMAC_REV_C1: 2575 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2576 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2577 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2578 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2579 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2580 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2581 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2582 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2583 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2584 break; 2585 default: 2586 break; 2587 } 2588 sk_win_write_2(sc, SK_MACARB_CTL, 2589 SK_MACARBCTL_UNRESET | SK_MACARBCTL_FASTOE_OFF); 2590 2591 sc_if->sk_link = 1; 2592 } 2593 2594 void sk_init_yukon(struct sk_if_softc *sc_if) 2595 { 2596 uint32_t /*mac, */phy; 2597 uint16_t reg; 2598 struct sk_softc *sc; 2599 int i; 2600 2601 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2602 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2603 2604 sc = sc_if->sk_softc; 2605 if (sc->sk_type == SK_YUKON_LITE && 2606 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2607 /* Take PHY out of reset. */ 2608 sk_win_write_4(sc, SK_GPIO, 2609 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2610 } 2611 2612 2613 /* GMAC and GPHY Reset */ 2614 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2615 2616 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2617 2618 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2619 DELAY(1000); 2620 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2621 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2622 DELAY(1000); 2623 2624 2625 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2626 2627 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2628 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2629 2630 switch (sc_if->sk_softc->sk_pmd) { 2631 case IFM_1000_SX: 2632 case IFM_1000_LX: 2633 phy |= SK_GPHY_FIBER; 2634 break; 2635 2636 case IFM_1000_CX: 2637 case IFM_1000_T: 2638 phy |= SK_GPHY_COPPER; 2639 break; 2640 } 2641 2642 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2643 2644 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2645 DELAY(1000); 2646 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2647 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2648 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2649 2650 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2651 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2652 2653 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2654 2655 /* unused read of the interrupt source register */ 2656 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2657 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2658 2659 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2660 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2661 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2662 2663 /* MIB Counter Clear Mode set */ 2664 reg |= YU_PAR_MIB_CLR; 2665 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2666 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2667 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2668 2669 /* MIB Counter Clear Mode clear */ 2670 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2671 reg &= ~YU_PAR_MIB_CLR; 2672 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2673 2674 /* receive control reg */ 2675 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2676 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2677 YU_RCR_CRCR); 2678 2679 /* transmit parameter register */ 2680 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2681 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2682 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2683 2684 /* serial mode register */ 2685 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2686 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2687 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2688 YU_SMR_IPG_DATA(0x1e)); 2689 2690 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2691 /* Setup Yukon's address */ 2692 for (i = 0; i < 3; i++) { 2693 /* Write Source Address 1 (unicast filter) */ 2694 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2695 sc_if->sk_enaddr[i * 2] | 2696 sc_if->sk_enaddr[i * 2 + 1] << 8); 2697 } 2698 2699 for (i = 0; i < 3; i++) { 2700 reg = sk_win_read_2(sc_if->sk_softc, 2701 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2702 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2703 } 2704 2705 /* Set multicast filter */ 2706 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2707 sk_setmulti(sc_if); 2708 2709 /* enable interrupt mask for counter overflows */ 2710 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2711 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2712 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2713 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2714 2715 /* Configure RX MAC FIFO */ 2716 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2717 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2718 2719 /* Configure TX MAC FIFO */ 2720 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2721 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2722 2723 DPRINTFN(6, ("sk_init_yukon: end\n")); 2724 } 2725 2726 /* 2727 * Note that to properly initialize any part of the GEnesis chip, 2728 * you first have to take it out of reset mode. 2729 */ 2730 int 2731 sk_init(struct ifnet *ifp) 2732 { 2733 struct sk_if_softc *sc_if = ifp->if_softc; 2734 struct sk_softc *sc = sc_if->sk_softc; 2735 struct mii_data *mii = &sc_if->sk_mii; 2736 int rc = 0, s; 2737 uint32_t imr, imtimer_ticks; 2738 2739 DPRINTFN(1, ("sk_init\n")); 2740 2741 s = splnet(); 2742 2743 if (ifp->if_flags & IFF_RUNNING) { 2744 splx(s); 2745 return 0; 2746 } 2747 2748 /* Cancel pending I/O and free all RX/TX buffers. */ 2749 sk_stop(ifp, 0); 2750 2751 if (sc->sk_type == SK_GENESIS) { 2752 /* Configure LINK_SYNC LED */ 2753 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2754 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2755 SK_LINKLED_LINKSYNC_ON); 2756 2757 /* Configure RX LED */ 2758 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2759 SK_RXLEDCTL_COUNTER_START); 2760 2761 /* Configure TX LED */ 2762 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2763 SK_TXLEDCTL_COUNTER_START); 2764 } 2765 2766 /* Configure I2C registers */ 2767 2768 /* Configure XMAC(s) */ 2769 switch (sc->sk_type) { 2770 case SK_GENESIS: 2771 sk_init_xmac(sc_if); 2772 break; 2773 case SK_YUKON: 2774 case SK_YUKON_LITE: 2775 case SK_YUKON_LP: 2776 sk_init_yukon(sc_if); 2777 break; 2778 } 2779 if ((rc = mii_mediachg(mii)) == ENXIO) 2780 rc = 0; 2781 else if (rc != 0) 2782 goto out; 2783 2784 if (sc->sk_type == SK_GENESIS) { 2785 /* Configure MAC FIFOs */ 2786 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2787 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2788 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2789 2790 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2791 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2792 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2793 } 2794 2795 /* Configure transmit arbiter(s) */ 2796 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2797 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2798 2799 /* Configure RAMbuffers */ 2800 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2801 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2802 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2803 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2804 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2805 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2806 2807 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2808 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2809 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2810 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2811 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2812 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2813 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2814 2815 /* Configure BMUs */ 2816 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2817 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2818 SK_RX_RING_ADDR(sc_if, 0)); 2819 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2820 2821 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2822 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2823 SK_TX_RING_ADDR(sc_if, 0)); 2824 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2825 2826 /* Init descriptors */ 2827 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2828 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2829 "memory for rx buffers\n"); 2830 sk_stop(ifp, 0); 2831 splx(s); 2832 return ENOBUFS; 2833 } 2834 2835 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2836 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2837 "memory for tx buffers\n"); 2838 sk_stop(ifp, 0); 2839 splx(s); 2840 return ENOBUFS; 2841 } 2842 2843 /* Set interrupt moderation if changed via sysctl. */ 2844 switch (sc->sk_type) { 2845 case SK_GENESIS: 2846 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2847 break; 2848 case SK_YUKON_EC: 2849 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2850 break; 2851 default: 2852 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2853 } 2854 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2855 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2856 sk_win_write_4(sc, SK_IMTIMERINIT, 2857 SK_IM_USECS(sc->sk_int_mod)); 2858 aprint_verbose_dev(sc->sk_dev, 2859 "interrupt moderation is %d us\n", sc->sk_int_mod); 2860 } 2861 2862 /* Configure interrupt handling */ 2863 CSR_READ_4(sc, SK_ISSR); 2864 if (sc_if->sk_port == SK_PORT_A) 2865 sc->sk_intrmask |= SK_INTRS1; 2866 else 2867 sc->sk_intrmask |= SK_INTRS2; 2868 2869 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2870 2871 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2872 2873 /* Start BMUs. */ 2874 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2875 2876 if (sc->sk_type == SK_GENESIS) { 2877 /* Enable XMACs TX and RX state machines */ 2878 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2879 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2880 XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2881 } 2882 2883 if (SK_YUKON_FAMILY(sc->sk_type)) { 2884 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2885 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2886 #if 0 2887 /* XXX disable 100Mbps and full duplex mode? */ 2888 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2889 #endif 2890 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2891 } 2892 2893 2894 ifp->if_flags |= IFF_RUNNING; 2895 ifp->if_flags &= ~IFF_OACTIVE; 2896 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2897 2898 out: 2899 splx(s); 2900 return rc; 2901 } 2902 2903 void 2904 sk_stop(struct ifnet *ifp, int disable) 2905 { 2906 struct sk_if_softc *sc_if = ifp->if_softc; 2907 struct sk_softc *sc = sc_if->sk_softc; 2908 int i; 2909 2910 DPRINTFN(1, ("sk_stop\n")); 2911 2912 callout_stop(&sc_if->sk_tick_ch); 2913 2914 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2915 uint32_t val; 2916 2917 /* Put PHY back into reset. */ 2918 val = sk_win_read_4(sc, SK_GPIO); 2919 if (sc_if->sk_port == SK_PORT_A) { 2920 val |= SK_GPIO_DIR0; 2921 val &= ~SK_GPIO_DAT0; 2922 } else { 2923 val |= SK_GPIO_DIR2; 2924 val &= ~SK_GPIO_DAT2; 2925 } 2926 sk_win_write_4(sc, SK_GPIO, val); 2927 } 2928 2929 /* Turn off various components of this interface. */ 2930 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2931 switch (sc->sk_type) { 2932 case SK_GENESIS: 2933 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2934 SK_TXMACCTL_XMAC_RESET); 2935 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2936 break; 2937 case SK_YUKON: 2938 case SK_YUKON_LITE: 2939 case SK_YUKON_LP: 2940 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2941 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2942 break; 2943 } 2944 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2945 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET |SK_RBCTL_OFF); 2946 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2947 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2948 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2949 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2950 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2951 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2952 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2953 2954 /* Disable interrupts */ 2955 if (sc_if->sk_port == SK_PORT_A) 2956 sc->sk_intrmask &= ~SK_INTRS1; 2957 else 2958 sc->sk_intrmask &= ~SK_INTRS2; 2959 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2960 2961 SK_XM_READ_2(sc_if, XM_ISR); 2962 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2963 2964 /* Free RX and TX mbufs still in the queues. */ 2965 for (i = 0; i < SK_RX_RING_CNT; i++) { 2966 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2967 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2968 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2969 } 2970 } 2971 2972 for (i = 0; i < SK_TX_RING_CNT; i++) { 2973 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2974 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2975 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2976 } 2977 } 2978 2979 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2980 } 2981 2982 /* Power Management Framework */ 2983 2984 static bool 2985 skc_suspend(device_t dv, const pmf_qual_t *qual) 2986 { 2987 struct sk_softc *sc = device_private(dv); 2988 2989 DPRINTFN(2, ("skc_suspend\n")); 2990 2991 /* Turn off the driver is loaded LED */ 2992 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2993 2994 return true; 2995 } 2996 2997 static bool 2998 skc_resume(device_t dv, const pmf_qual_t *qual) 2999 { 3000 struct sk_softc *sc = device_private(dv); 3001 3002 DPRINTFN(2, ("skc_resume\n")); 3003 3004 sk_reset(sc); 3005 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 3006 3007 return true; 3008 } 3009 3010 static bool 3011 sk_resume(device_t dv, const pmf_qual_t *qual) 3012 { 3013 struct sk_if_softc *sc_if = device_private(dv); 3014 3015 sk_init_yukon(sc_if); 3016 return true; 3017 } 3018 3019 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 3020 skc_probe, skc_attach, NULL, NULL); 3021 3022 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 3023 sk_probe, sk_attach, NULL, NULL); 3024 3025 #ifdef SK_DEBUG 3026 void 3027 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 3028 { 3029 #define DESC_PRINT(X) \ 3030 if (X) \ 3031 printf("txdesc[%d]." #X "=%#x\n", \ 3032 idx, X); 3033 3034 DESC_PRINT(le32toh(desc->sk_ctl)); 3035 DESC_PRINT(le32toh(desc->sk_next)); 3036 DESC_PRINT(le32toh(desc->sk_data_lo)); 3037 DESC_PRINT(le32toh(desc->sk_data_hi)); 3038 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 3039 DESC_PRINT(le16toh(desc->sk_rsvd0)); 3040 DESC_PRINT(le16toh(desc->sk_csum_startval)); 3041 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 3042 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 3043 DESC_PRINT(le16toh(desc->sk_rsvd1)); 3044 #undef PRINT 3045 } 3046 3047 void 3048 sk_dump_bytes(const char *data, int len) 3049 { 3050 int c, i, j; 3051 3052 for (i = 0; i < len; i += 16) { 3053 printf("%08x ", i); 3054 c = len - i; 3055 if (c > 16) c = 16; 3056 3057 for (j = 0; j < c; j++) { 3058 printf("%02x ", data[i + j] & 0xff); 3059 if ((j & 0xf) == 7 && j > 0) 3060 printf(" "); 3061 } 3062 3063 for (; j < 16; j++) 3064 printf(" "); 3065 printf(" "); 3066 3067 for (j = 0; j < c; j++) { 3068 int ch = data[i + j] & 0xff; 3069 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3070 } 3071 3072 printf("\n"); 3073 3074 if (c < 16) 3075 break; 3076 } 3077 } 3078 3079 void 3080 sk_dump_mbuf(struct mbuf *m) 3081 { 3082 int count = m->m_pkthdr.len; 3083 3084 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3085 3086 while (count > 0 && m) { 3087 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3088 m, m->m_data, m->m_len); 3089 sk_dump_bytes(mtod(m, char *), m->m_len); 3090 3091 count -= m->m_len; 3092 m = m->m_next; 3093 } 3094 } 3095 #endif 3096 3097 static int 3098 sk_sysctl_handler(SYSCTLFN_ARGS) 3099 { 3100 int error, t; 3101 struct sysctlnode node; 3102 struct sk_softc *sc; 3103 3104 node = *rnode; 3105 sc = node.sysctl_data; 3106 t = sc->sk_int_mod; 3107 node.sysctl_data = &t; 3108 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3109 if (error || newp == NULL) 3110 return error; 3111 3112 if (t < SK_IM_MIN || t > SK_IM_MAX) 3113 return EINVAL; 3114 3115 /* update the softc with sysctl-changed value, and mark 3116 for hardware update */ 3117 sc->sk_int_mod = t; 3118 sc->sk_int_mod_pending = 1; 3119 return 0; 3120 } 3121 3122 /* 3123 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3124 * set up in skc_attach() 3125 */ 3126 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3127 { 3128 int rc; 3129 const struct sysctlnode *node; 3130 3131 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3132 0, CTLTYPE_NODE, "sk", 3133 SYSCTL_DESCR("sk interface controls"), 3134 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3135 goto err; 3136 } 3137 3138 sk_root_num = node->sysctl_num; 3139 return; 3140 3141 err: 3142 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3143 } 3144
Indexes created Tue Sep 23 02:09:52 GMT 2025