if_sk.c revision 1.97
1 /* $NetBSD: if_sk.c,v 1.97 2019/05/28 07:41:49 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.97 2019/05/28 07:41:49 msaitoh Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/sockio.h> 123 #include <sys/mbuf.h> 124 #include <sys/malloc.h> 125 #include <sys/mutex.h> 126 #include <sys/kernel.h> 127 #include <sys/socket.h> 128 #include <sys/device.h> 129 #include <sys/queue.h> 130 #include <sys/callout.h> 131 #include <sys/sysctl.h> 132 #include <sys/endian.h> 133 134 #include <net/if.h> 135 #include <net/if_dl.h> 136 #include <net/if_types.h> 137 138 #include <net/if_media.h> 139 140 #include <net/bpf.h> 141 #include <sys/rndsource.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 #include <dev/mii/brgphyreg.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 #include <dev/pci/pcidevs.h> 150 151 /* #define SK_USEIOSPACE */ 152 153 #include <dev/pci/if_skreg.h> 154 #include <dev/pci/if_skvar.h> 155 156 int skc_probe(device_t, cfdata_t, void *); 157 void skc_attach(device_t, device_t, void *aux); 158 int sk_probe(device_t, cfdata_t, void *); 159 void sk_attach(device_t, device_t, void *aux); 160 int skcprint(void *, const char *); 161 int sk_intr(void *); 162 void sk_intr_bcom(struct sk_if_softc *); 163 void sk_intr_xmac(struct sk_if_softc *); 164 void sk_intr_yukon(struct sk_if_softc *); 165 void sk_rxeof(struct sk_if_softc *); 166 void sk_txeof(struct sk_if_softc *); 167 int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 168 void sk_start(struct ifnet *); 169 int sk_ioctl(struct ifnet *, u_long, void *); 170 int sk_init(struct ifnet *); 171 void sk_init_xmac(struct sk_if_softc *); 172 void sk_init_yukon(struct sk_if_softc *); 173 void sk_stop(struct ifnet *, int); 174 void sk_watchdog(struct ifnet *); 175 void sk_shutdown(void *); 176 int sk_ifmedia_upd(struct ifnet *); 177 void sk_reset(struct sk_softc *); 178 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 179 int sk_alloc_jumbo_mem(struct sk_if_softc *); 180 void sk_free_jumbo_mem(struct sk_if_softc *); 181 void *sk_jalloc(struct sk_if_softc *); 182 void sk_jfree(struct mbuf *, void *, size_t, void *); 183 int sk_init_rx_ring(struct sk_if_softc *); 184 int sk_init_tx_ring(struct sk_if_softc *); 185 uint8_t sk_vpd_readbyte(struct sk_softc *, int); 186 void sk_vpd_read_res(struct sk_softc *, 187 struct vpd_res *, int); 188 void sk_vpd_read(struct sk_softc *); 189 190 void sk_update_int_mod(struct sk_softc *); 191 192 int sk_xmac_miibus_readreg(device_t, int, int, uint16_t *); 193 int sk_xmac_miibus_writereg(device_t, int, int, uint16_t); 194 void sk_xmac_miibus_statchg(struct ifnet *); 195 196 int sk_marv_miibus_readreg(device_t, int, int, uint16_t *); 197 int sk_marv_miibus_writereg(device_t, int, int, uint16_t); 198 void sk_marv_miibus_statchg(struct ifnet *); 199 200 uint32_t sk_xmac_hash(void *); 201 uint32_t sk_yukon_hash(void *); 202 void sk_setfilt(struct sk_if_softc *, void *, int); 203 void sk_setmulti(struct sk_if_softc *); 204 void sk_tick(void *); 205 206 static bool skc_suspend(device_t, const pmf_qual_t *); 207 static bool skc_resume(device_t, const pmf_qual_t *); 208 static bool sk_resume(device_t dv, const pmf_qual_t *); 209 210 /* #define SK_DEBUG 2 */ 211 #ifdef SK_DEBUG 212 #define DPRINTF(x) if (skdebug) printf x 213 #define DPRINTFN(n, x) if (skdebug >= (n)) printf x 214 int skdebug = SK_DEBUG; 215 216 void sk_dump_txdesc(struct sk_tx_desc *, int); 217 void sk_dump_mbuf(struct mbuf *); 218 void sk_dump_bytes(const char *, int); 219 #else 220 #define DPRINTF(x) 221 #define DPRINTFN(n, x) 222 #endif 223 224 static int sk_sysctl_handler(SYSCTLFN_PROTO); 225 static int sk_root_num; 226 227 /* supported device vendors */ 228 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 229 static const struct sk_product { 230 pci_vendor_id_t sk_vendor; 231 pci_product_id_t sk_product; 232 } sk_products[] = { 233 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 234 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 235 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 236 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 237 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 238 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 239 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 240 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 241 { 0, 0, } 242 }; 243 244 #define SK_LINKSYS_EG1032_SUBID 0x00151737 245 246 static inline uint32_t 247 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 248 { 249 #ifdef SK_USEIOSPACE 250 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 251 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 252 #else 253 return CSR_READ_4(sc, reg); 254 #endif 255 } 256 257 static inline uint16_t 258 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 259 { 260 #ifdef SK_USEIOSPACE 261 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 262 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 263 #else 264 return CSR_READ_2(sc, reg); 265 #endif 266 } 267 268 static inline uint8_t 269 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 270 { 271 #ifdef SK_USEIOSPACE 272 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 273 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 274 #else 275 return CSR_READ_1(sc, reg); 276 #endif 277 } 278 279 static inline void 280 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 281 { 282 #ifdef SK_USEIOSPACE 283 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 284 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 285 #else 286 CSR_WRITE_4(sc, reg, x); 287 #endif 288 } 289 290 static inline void 291 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 292 { 293 #ifdef SK_USEIOSPACE 294 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 295 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 296 #else 297 CSR_WRITE_2(sc, reg, x); 298 #endif 299 } 300 301 static inline void 302 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 303 { 304 #ifdef SK_USEIOSPACE 305 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 306 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 307 #else 308 CSR_WRITE_1(sc, reg, x); 309 #endif 310 } 311 312 /* 313 * The VPD EEPROM contains Vital Product Data, as suggested in 314 * the PCI 2.1 specification. The VPD data is separared into areas 315 * denoted by resource IDs. The SysKonnect VPD contains an ID string 316 * resource (the name of the adapter), a read-only area resource 317 * containing various key/data fields and a read/write area which 318 * can be used to store asset management information or log messages. 319 * We read the ID string and read-only into buffers attached to 320 * the controller softc structure for later use. At the moment, 321 * we only use the ID string during sk_attach(). 322 */ 323 uint8_t 324 sk_vpd_readbyte(struct sk_softc *sc, int addr) 325 { 326 int i; 327 328 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 329 for (i = 0; i < SK_TIMEOUT; i++) { 330 DELAY(1); 331 if (sk_win_read_2(sc, 332 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 333 break; 334 } 335 336 if (i == SK_TIMEOUT) 337 return 0; 338 339 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 340 } 341 342 void 343 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 344 { 345 int i; 346 uint8_t *ptr; 347 348 ptr = (uint8_t *)res; 349 for (i = 0; i < sizeof(struct vpd_res); i++) 350 ptr[i] = sk_vpd_readbyte(sc, i + addr); 351 } 352 353 void 354 sk_vpd_read(struct sk_softc *sc) 355 { 356 int pos = 0, i; 357 struct vpd_res res; 358 359 if (sc->sk_vpd_prodname != NULL) 360 free(sc->sk_vpd_prodname, M_DEVBUF); 361 if (sc->sk_vpd_readonly != NULL) 362 free(sc->sk_vpd_readonly, M_DEVBUF); 363 sc->sk_vpd_prodname = NULL; 364 sc->sk_vpd_readonly = NULL; 365 366 sk_vpd_read_res(sc, &res, pos); 367 368 if (res.vr_id != VPD_RES_ID) { 369 aprint_error_dev(sc->sk_dev, 370 "bad VPD resource id: expected %x got %x\n", 371 VPD_RES_ID, res.vr_id); 372 return; 373 } 374 375 pos += sizeof(res); 376 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 377 if (sc->sk_vpd_prodname == NULL) 378 panic("sk_vpd_read"); 379 for (i = 0; i < res.vr_len; i++) 380 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 381 sc->sk_vpd_prodname[i] = '\0'; 382 pos += i; 383 384 sk_vpd_read_res(sc, &res, pos); 385 386 if (res.vr_id != VPD_RES_READ) { 387 aprint_error_dev(sc->sk_dev, 388 "bad VPD resource id: expected %x got %x\n", 389 VPD_RES_READ, res.vr_id); 390 return; 391 } 392 393 pos += sizeof(res); 394 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 395 if (sc->sk_vpd_readonly == NULL) 396 panic("sk_vpd_read"); 397 for (i = 0; i < res.vr_len ; i++) 398 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 399 } 400 401 int 402 sk_xmac_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 403 { 404 struct sk_if_softc *sc_if = device_private(dev); 405 int i; 406 407 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 408 409 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 410 return -1; 411 412 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 413 SK_XM_READ_2(sc_if, XM_PHY_DATA); 414 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 415 for (i = 0; i < SK_TIMEOUT; i++) { 416 DELAY(1); 417 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 418 XM_MMUCMD_PHYDATARDY) 419 break; 420 } 421 422 if (i == SK_TIMEOUT) { 423 aprint_error_dev(sc_if->sk_dev, 424 "phy failed to come ready\n"); 425 return ETIMEDOUT; 426 } 427 } 428 DELAY(1); 429 *val = SK_XM_READ_2(sc_if, XM_PHY_DATA); 430 return 0; 431 } 432 433 int 434 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 435 { 436 struct sk_if_softc *sc_if = device_private(dev); 437 int i; 438 439 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 440 441 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 442 for (i = 0; i < SK_TIMEOUT; i++) { 443 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 444 break; 445 } 446 447 if (i == SK_TIMEOUT) { 448 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 449 return ETIMEDOUT; 450 } 451 452 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 453 for (i = 0; i < SK_TIMEOUT; i++) { 454 DELAY(1); 455 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 456 break; 457 } 458 459 if (i == SK_TIMEOUT) { 460 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 461 return ETIMEDOUT; 462 } 463 464 return 0; 465 } 466 467 void 468 sk_xmac_miibus_statchg(struct ifnet *ifp) 469 { 470 struct sk_if_softc *sc_if = ifp->if_softc; 471 struct mii_data *mii = &sc_if->sk_mii; 472 473 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 474 475 /* 476 * If this is a GMII PHY, manually set the XMAC's 477 * duplex mode accordingly. 478 */ 479 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 480 if ((mii->mii_media_active & IFM_FDX) != 0) 481 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 482 else 483 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 484 } 485 } 486 487 int 488 sk_marv_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 489 { 490 struct sk_if_softc *sc_if = device_private(dev); 491 uint16_t data; 492 int i; 493 494 if (phy != 0 || 495 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 496 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 497 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 498 phy, reg)); 499 return -1; 500 } 501 502 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 503 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 504 505 for (i = 0; i < SK_TIMEOUT; i++) { 506 DELAY(1); 507 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 508 if (data & YU_SMICR_READ_VALID) 509 break; 510 } 511 512 if (i == SK_TIMEOUT) { 513 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 514 return ETIMEDOUT; 515 } 516 517 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 518 SK_TIMEOUT)); 519 520 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 521 522 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 523 phy, reg, *val)); 524 525 return 0; 526 } 527 528 int 529 sk_marv_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 530 { 531 struct sk_if_softc *sc_if = device_private(dev); 532 int i; 533 534 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#hx\n", 535 phy, reg, val)); 536 537 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 538 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 539 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 540 541 for (i = 0; i < SK_TIMEOUT; i++) { 542 DELAY(1); 543 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 544 break; 545 } 546 547 if (i == SK_TIMEOUT) { 548 printf("%s: phy write timed out\n", 549 device_xname(sc_if->sk_dev)); 550 return ETIMEDOUT; 551 } 552 553 return 0; 554 } 555 556 void 557 sk_marv_miibus_statchg(struct ifnet *ifp) 558 { 559 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 560 SK_YU_READ_2(((struct sk_if_softc *)ifp->if_softc), 561 YUKON_GPCR))); 562 } 563 564 uint32_t 565 sk_xmac_hash(void *addr) 566 { 567 uint32_t crc; 568 569 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 570 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 571 DPRINTFN(2,("multicast hash for %s is %x\n", ether_sprintf(addr),crc)); 572 return crc; 573 } 574 575 uint32_t 576 sk_yukon_hash(void *addr) 577 { 578 uint32_t crc; 579 580 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 581 crc &= ((1 << SK_HASH_BITS) - 1); 582 DPRINTFN(2,("multicast hash for %s is %x\n", ether_sprintf(addr),crc)); 583 return crc; 584 } 585 586 void 587 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 588 { 589 char *addr = addrv; 590 int base = XM_RXFILT_ENTRY(slot); 591 592 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0])); 593 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2])); 594 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4])); 595 } 596 597 void 598 sk_setmulti(struct sk_if_softc *sc_if) 599 { 600 struct sk_softc *sc = sc_if->sk_softc; 601 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 602 uint32_t hashes[2] = { 0, 0 }; 603 int h = 0, i; 604 struct ethercom *ec = &sc_if->sk_ethercom; 605 struct ether_multi *enm; 606 struct ether_multistep step; 607 uint8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 608 609 /* First, zot all the existing filters. */ 610 switch (sc->sk_type) { 611 case SK_GENESIS: 612 for (i = 1; i < XM_RXFILT_MAX; i++) 613 sk_setfilt(sc_if, (void *)&dummy, i); 614 615 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 616 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 617 break; 618 case SK_YUKON: 619 case SK_YUKON_LITE: 620 case SK_YUKON_LP: 621 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 622 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 623 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 624 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 625 break; 626 } 627 628 /* Now program new ones. */ 629 allmulti: 630 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 631 hashes[0] = 0xFFFFFFFF; 632 hashes[1] = 0xFFFFFFFF; 633 } else { 634 i = 1; 635 /* First find the tail of the list. */ 636 ETHER_LOCK(ec); 637 ETHER_FIRST_MULTI(step, ec, enm); 638 while (enm != NULL) { 639 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 640 ETHER_ADDR_LEN)) { 641 ifp->if_flags |= IFF_ALLMULTI; 642 ETHER_UNLOCK(ec); 643 goto allmulti; 644 } 645 DPRINTFN(2,("multicast address %s\n", 646 ether_sprintf(enm->enm_addrlo))); 647 /* 648 * Program the first XM_RXFILT_MAX multicast groups 649 * into the perfect filter. For all others, 650 * use the hash table. 651 */ 652 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 653 sk_setfilt(sc_if, enm->enm_addrlo, i); 654 i++; 655 } 656 else { 657 switch (sc->sk_type) { 658 case SK_GENESIS: 659 h = sk_xmac_hash(enm->enm_addrlo); 660 break; 661 case SK_YUKON: 662 case SK_YUKON_LITE: 663 case SK_YUKON_LP: 664 h = sk_yukon_hash(enm->enm_addrlo); 665 break; 666 } 667 if (h < 32) 668 hashes[0] |= (1 << h); 669 else 670 hashes[1] |= (1 << (h - 32)); 671 } 672 673 ETHER_NEXT_MULTI(step, enm); 674 } 675 ETHER_UNLOCK(ec); 676 } 677 678 switch (sc->sk_type) { 679 case SK_GENESIS: 680 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH | 681 XM_MODE_RX_USE_PERFECT); 682 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 683 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 684 break; 685 case SK_YUKON: 686 case SK_YUKON_LITE: 687 case SK_YUKON_LP: 688 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 689 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 690 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 691 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 692 break; 693 } 694 } 695 696 int 697 sk_init_rx_ring(struct sk_if_softc *sc_if) 698 { 699 struct sk_chain_data *cd = &sc_if->sk_cdata; 700 struct sk_ring_data *rd = sc_if->sk_rdata; 701 int i; 702 703 memset((char *)rd->sk_rx_ring, 0, 704 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 705 706 for (i = 0; i < SK_RX_RING_CNT; i++) { 707 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 708 if (i == (SK_RX_RING_CNT - 1)) { 709 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 710 rd->sk_rx_ring[i].sk_next = 711 htole32(SK_RX_RING_ADDR(sc_if, 0)); 712 } else { 713 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 714 rd->sk_rx_ring[i].sk_next = 715 htole32(SK_RX_RING_ADDR(sc_if, i+1)); 716 } 717 } 718 719 for (i = 0; i < SK_RX_RING_CNT; i++) { 720 if (sk_newbuf(sc_if, i, NULL, 721 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 722 aprint_error_dev(sc_if->sk_dev, 723 "failed alloc of %dth mbuf\n", i); 724 return ENOBUFS; 725 } 726 } 727 sc_if->sk_cdata.sk_rx_prod = 0; 728 sc_if->sk_cdata.sk_rx_cons = 0; 729 730 return 0; 731 } 732 733 int 734 sk_init_tx_ring(struct sk_if_softc *sc_if) 735 { 736 struct sk_chain_data *cd = &sc_if->sk_cdata; 737 struct sk_ring_data *rd = sc_if->sk_rdata; 738 int i; 739 740 memset(sc_if->sk_rdata->sk_tx_ring, 0, 741 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 742 743 for (i = 0; i < SK_TX_RING_CNT; i++) { 744 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 745 if (i == (SK_TX_RING_CNT - 1)) { 746 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 747 rd->sk_tx_ring[i].sk_next = 748 htole32(SK_TX_RING_ADDR(sc_if, 0)); 749 } else { 750 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 751 rd->sk_tx_ring[i].sk_next = 752 htole32(SK_TX_RING_ADDR(sc_if, i+1)); 753 } 754 } 755 756 sc_if->sk_cdata.sk_tx_prod = 0; 757 sc_if->sk_cdata.sk_tx_cons = 0; 758 sc_if->sk_cdata.sk_tx_cnt = 0; 759 760 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 761 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 762 763 return 0; 764 } 765 766 int 767 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 768 bus_dmamap_t dmamap) 769 { 770 struct mbuf *m_new = NULL; 771 struct sk_chain *c; 772 struct sk_rx_desc *r; 773 774 if (m == NULL) { 775 void *buf = NULL; 776 777 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 778 if (m_new == NULL) { 779 aprint_error_dev(sc_if->sk_dev, 780 "no memory for rx list -- packet dropped!\n"); 781 return ENOBUFS; 782 } 783 784 /* Allocate the jumbo buffer */ 785 buf = sk_jalloc(sc_if); 786 if (buf == NULL) { 787 m_freem(m_new); 788 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 789 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 790 return ENOBUFS; 791 } 792 793 /* Attach the buffer to the mbuf */ 794 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 795 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 796 797 } else { 798 /* 799 * We're re-using a previously allocated mbuf; 800 * be sure to re-init pointers and lengths to 801 * default values. 802 */ 803 m_new = m; 804 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 805 m_new->m_data = m_new->m_ext.ext_buf; 806 } 807 m_adj(m_new, ETHER_ALIGN); 808 809 c = &sc_if->sk_cdata.sk_rx_chain[i]; 810 r = c->sk_desc; 811 c->sk_mbuf = m_new; 812 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 813 (((vaddr_t)m_new->m_data 814 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 815 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 816 817 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 818 819 return 0; 820 } 821 822 /* 823 * Memory management for jumbo frames. 824 */ 825 826 int 827 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 828 { 829 struct sk_softc *sc = sc_if->sk_softc; 830 char *ptr, *kva; 831 bus_dma_segment_t seg; 832 int i, rseg, state, error; 833 struct sk_jpool_entry *entry; 834 835 state = error = 0; 836 837 /* Grab a big chunk o' storage. */ 838 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 839 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 840 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 841 return ENOBUFS; 842 } 843 844 state = 1; 845 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 846 BUS_DMA_NOWAIT)) { 847 aprint_error_dev(sc->sk_dev, 848 "can't map dma buffers (%d bytes)\n", 849 SK_JMEM); 850 error = ENOBUFS; 851 goto out; 852 } 853 854 state = 2; 855 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 856 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 857 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 858 error = ENOBUFS; 859 goto out; 860 } 861 862 state = 3; 863 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 864 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 865 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 866 error = ENOBUFS; 867 goto out; 868 } 869 870 state = 4; 871 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 872 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 873 874 LIST_INIT(&sc_if->sk_jfree_listhead); 875 LIST_INIT(&sc_if->sk_jinuse_listhead); 876 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 877 878 /* 879 * Now divide it up into 9K pieces and save the addresses 880 * in an array. 881 */ 882 ptr = sc_if->sk_cdata.sk_jumbo_buf; 883 for (i = 0; i < SK_JSLOTS; i++) { 884 sc_if->sk_cdata.sk_jslots[i] = ptr; 885 ptr += SK_JLEN; 886 entry = malloc(sizeof(struct sk_jpool_entry), 887 M_DEVBUF, M_NOWAIT); 888 if (entry == NULL) { 889 aprint_error_dev(sc->sk_dev, 890 "no memory for jumbo buffer queue!\n"); 891 error = ENOBUFS; 892 goto out; 893 } 894 entry->slot = i; 895 if (i) 896 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 897 entry, jpool_entries); 898 else 899 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 900 entry, jpool_entries); 901 } 902 out: 903 if (error != 0) { 904 switch (state) { 905 case 4: 906 bus_dmamap_unload(sc->sc_dmatag, 907 sc_if->sk_cdata.sk_rx_jumbo_map); 908 /* FALLTHROUGH */ 909 case 3: 910 bus_dmamap_destroy(sc->sc_dmatag, 911 sc_if->sk_cdata.sk_rx_jumbo_map); 912 /* FALLTHROUGH */ 913 case 2: 914 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 915 /* FALLTHROUGH */ 916 case 1: 917 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 918 break; 919 default: 920 break; 921 } 922 } 923 924 return error; 925 } 926 927 /* 928 * Allocate a jumbo buffer. 929 */ 930 void * 931 sk_jalloc(struct sk_if_softc *sc_if) 932 { 933 struct sk_jpool_entry *entry; 934 935 mutex_enter(&sc_if->sk_jpool_mtx); 936 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 937 938 if (entry == NULL) { 939 mutex_exit(&sc_if->sk_jpool_mtx); 940 return NULL; 941 } 942 943 LIST_REMOVE(entry, jpool_entries); 944 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 945 mutex_exit(&sc_if->sk_jpool_mtx); 946 return sc_if->sk_cdata.sk_jslots[entry->slot]; 947 } 948 949 /* 950 * Release a jumbo buffer. 951 */ 952 void 953 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 954 { 955 struct sk_jpool_entry *entry; 956 struct sk_if_softc *sc; 957 int i; 958 959 /* Extract the softc struct pointer. */ 960 sc = (struct sk_if_softc *)arg; 961 962 if (sc == NULL) 963 panic("sk_jfree: can't find softc pointer!"); 964 965 /* calculate the slot this buffer belongs to */ 966 967 i = ((vaddr_t)buf 968 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 969 970 if ((i < 0) || (i >= SK_JSLOTS)) 971 panic("sk_jfree: asked to free buffer that we don't manage!"); 972 973 mutex_enter(&sc->sk_jpool_mtx); 974 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 975 if (entry == NULL) 976 panic("sk_jfree: buffer not in use!"); 977 entry->slot = i; 978 LIST_REMOVE(entry, jpool_entries); 979 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 980 mutex_exit(&sc->sk_jpool_mtx); 981 982 if (__predict_true(m != NULL)) 983 pool_cache_put(mb_cache, m); 984 } 985 986 /* 987 * Set media options. 988 */ 989 int 990 sk_ifmedia_upd(struct ifnet *ifp) 991 { 992 struct sk_if_softc *sc_if = ifp->if_softc; 993 int rc; 994 995 (void) sk_init(ifp); 996 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 997 return 0; 998 return rc; 999 } 1000 1001 static void 1002 sk_promisc(struct sk_if_softc *sc_if, int on) 1003 { 1004 struct sk_softc *sc = sc_if->sk_softc; 1005 switch (sc->sk_type) { 1006 case SK_GENESIS: 1007 if (on) 1008 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1009 else 1010 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1011 break; 1012 case SK_YUKON: 1013 case SK_YUKON_LITE: 1014 case SK_YUKON_LP: 1015 if (on) 1016 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1017 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1018 else 1019 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1020 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1021 break; 1022 default: 1023 aprint_error_dev(sc_if->sk_dev, "Can't set promisc for %d\n", 1024 sc->sk_type); 1025 break; 1026 } 1027 } 1028 1029 int 1030 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 1031 { 1032 struct sk_if_softc *sc_if = ifp->if_softc; 1033 int s, error = 0; 1034 1035 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1036 1037 s = splnet(); 1038 1039 switch (command) { 1040 1041 case SIOCSIFFLAGS: 1042 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1043 if ((error = ifioctl_common(ifp, command, data)) != 0) 1044 break; 1045 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1046 case IFF_RUNNING: 1047 sk_stop(ifp, 1); 1048 break; 1049 case IFF_UP: 1050 sk_init(ifp); 1051 break; 1052 case IFF_UP | IFF_RUNNING: 1053 if ((ifp->if_flags ^ sc_if->sk_if_flags) == IFF_PROMISC) { 1054 sk_promisc(sc_if, ifp->if_flags & IFF_PROMISC); 1055 sk_setmulti(sc_if); 1056 } else 1057 sk_init(ifp); 1058 break; 1059 } 1060 sc_if->sk_if_flags = ifp->if_flags; 1061 error = 0; 1062 break; 1063 1064 default: 1065 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1066 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1067 break; 1068 1069 error = 0; 1070 1071 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1072 ; 1073 else if (ifp->if_flags & IFF_RUNNING) { 1074 sk_setmulti(sc_if); 1075 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1076 } 1077 break; 1078 } 1079 1080 splx(s); 1081 return error; 1082 } 1083 1084 void 1085 sk_update_int_mod(struct sk_softc *sc) 1086 { 1087 uint32_t imtimer_ticks; 1088 1089 /* 1090 * Configure interrupt moderation. The moderation timer 1091 * defers interrupts specified in the interrupt moderation 1092 * timer mask based on the timeout specified in the interrupt 1093 * moderation timer init register. Each bit in the timer 1094 * register represents one tick, so to specify a timeout in 1095 * microseconds, we have to multiply by the correct number of 1096 * ticks-per-microsecond. 1097 */ 1098 switch (sc->sk_type) { 1099 case SK_GENESIS: 1100 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1101 break; 1102 case SK_YUKON_EC: 1103 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1104 break; 1105 default: 1106 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1107 } 1108 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1109 sc->sk_int_mod); 1110 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1111 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF | 1112 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF); 1113 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1114 sc->sk_int_mod_pending = 0; 1115 } 1116 1117 /* 1118 * Lookup: Check the PCI vendor and device, and return a pointer to 1119 * The structure if the IDs match against our list. 1120 */ 1121 1122 static const struct sk_product * 1123 sk_lookup(const struct pci_attach_args *pa) 1124 { 1125 const struct sk_product *psk; 1126 1127 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1128 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1129 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1130 return psk; 1131 } 1132 return NULL; 1133 } 1134 1135 /* 1136 * Probe for a SysKonnect GEnesis chip. 1137 */ 1138 1139 int 1140 skc_probe(device_t parent, cfdata_t match, void *aux) 1141 { 1142 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1143 const struct sk_product *psk; 1144 pcireg_t subid; 1145 1146 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1147 1148 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1149 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1150 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1151 subid == SK_LINKSYS_EG1032_SUBID) 1152 return 1; 1153 1154 if ((psk = sk_lookup(pa))) { 1155 return 1; 1156 } 1157 return 0; 1158 } 1159 1160 /* 1161 * Force the GEnesis into reset, then bring it out of reset. 1162 */ 1163 void sk_reset(struct sk_softc *sc) 1164 { 1165 DPRINTFN(2, ("sk_reset\n")); 1166 1167 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1168 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1169 if (SK_YUKON_FAMILY(sc->sk_type)) 1170 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1171 1172 DELAY(1000); 1173 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1174 DELAY(2); 1175 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1176 if (SK_YUKON_FAMILY(sc->sk_type)) 1177 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1178 1179 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1180 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1181 CSR_READ_2(sc, SK_LINK_CTRL))); 1182 1183 if (sc->sk_type == SK_GENESIS) { 1184 /* Configure packet arbiter */ 1185 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1186 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1187 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1188 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1189 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1190 } 1191 1192 /* Enable RAM interface */ 1193 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1194 1195 sk_update_int_mod(sc); 1196 } 1197 1198 int 1199 sk_probe(device_t parent, cfdata_t match, void *aux) 1200 { 1201 struct skc_attach_args *sa = aux; 1202 1203 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1204 return 0; 1205 1206 return 1; 1207 } 1208 1209 /* 1210 * Each XMAC chip is attached as a separate logical IP interface. 1211 * Single port cards will have only one logical interface of course. 1212 */ 1213 void 1214 sk_attach(device_t parent, device_t self, void *aux) 1215 { 1216 struct sk_if_softc *sc_if = device_private(self); 1217 struct sk_softc *sc = device_private(parent); 1218 struct skc_attach_args *sa = aux; 1219 struct sk_txmap_entry *entry; 1220 struct ifnet *ifp; 1221 bus_dma_segment_t seg; 1222 bus_dmamap_t dmamap; 1223 prop_data_t data; 1224 void *kva; 1225 int i, rseg; 1226 int mii_flags = 0; 1227 1228 aprint_naive("\n"); 1229 1230 sc_if->sk_dev = self; 1231 sc_if->sk_port = sa->skc_port; 1232 sc_if->sk_softc = sc; 1233 sc->sk_if[sa->skc_port] = sc_if; 1234 1235 if (sa->skc_port == SK_PORT_A) 1236 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1237 if (sa->skc_port == SK_PORT_B) 1238 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1239 1240 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1241 1242 /* 1243 * Get station address for this interface. Note that 1244 * dual port cards actually come with three station 1245 * addresses: one for each port, plus an extra. The 1246 * extra one is used by the SysKonnect driver software 1247 * as a 'virtual' station address for when both ports 1248 * are operating in failover mode. Currently we don't 1249 * use this extra address. 1250 */ 1251 data = prop_dictionary_get(device_properties(self), "mac-address"); 1252 if (data != NULL) { 1253 /* 1254 * Try to get the station address from device properties 1255 * first, in case the ROM is missing. 1256 */ 1257 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 1258 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 1259 memcpy(sc_if->sk_enaddr, prop_data_data_nocopy(data), 1260 ETHER_ADDR_LEN); 1261 } else 1262 for (i = 0; i < ETHER_ADDR_LEN; i++) 1263 sc_if->sk_enaddr[i] = sk_win_read_1(sc, 1264 SK_MAC0_0 + (sa->skc_port * 8) + i); 1265 1266 aprint_normal(": Ethernet address %s\n", 1267 ether_sprintf(sc_if->sk_enaddr)); 1268 1269 /* 1270 * Set up RAM buffer addresses. The NIC will have a certain 1271 * amount of SRAM on it, somewhere between 512K and 2MB. We 1272 * need to divide this up a) between the transmitter and 1273 * receiver and b) between the two XMACs, if this is a 1274 * dual port NIC. Our algorithm is to divide up the memory 1275 * evenly so that everyone gets a fair share. 1276 */ 1277 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1278 uint32_t chunk, val; 1279 1280 chunk = sc->sk_ramsize / 2; 1281 val = sc->sk_rboff / sizeof(uint64_t); 1282 sc_if->sk_rx_ramstart = val; 1283 val += (chunk / sizeof(uint64_t)); 1284 sc_if->sk_rx_ramend = val - 1; 1285 sc_if->sk_tx_ramstart = val; 1286 val += (chunk / sizeof(uint64_t)); 1287 sc_if->sk_tx_ramend = val - 1; 1288 } else { 1289 uint32_t chunk, val; 1290 1291 chunk = sc->sk_ramsize / 4; 1292 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1293 sizeof(uint64_t); 1294 sc_if->sk_rx_ramstart = val; 1295 val += (chunk / sizeof(uint64_t)); 1296 sc_if->sk_rx_ramend = val - 1; 1297 sc_if->sk_tx_ramstart = val; 1298 val += (chunk / sizeof(uint64_t)); 1299 sc_if->sk_tx_ramend = val - 1; 1300 } 1301 1302 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1303 " tx_ramstart=%#x tx_ramend=%#x\n", 1304 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1305 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1306 1307 /* Read and save PHY type and set PHY address */ 1308 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1309 switch (sc_if->sk_phytype) { 1310 case SK_PHYTYPE_XMAC: 1311 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1312 break; 1313 case SK_PHYTYPE_BCOM: 1314 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1315 break; 1316 case SK_PHYTYPE_MARV_COPPER: 1317 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1318 break; 1319 default: 1320 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1321 sc_if->sk_phytype); 1322 return; 1323 } 1324 1325 /* Allocate the descriptor queues. */ 1326 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1327 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1328 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1329 goto fail; 1330 } 1331 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1332 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1333 aprint_error_dev(sc_if->sk_dev, 1334 "can't map dma buffers (%lu bytes)\n", 1335 (u_long) sizeof(struct sk_ring_data)); 1336 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1337 goto fail; 1338 } 1339 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1340 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1341 &sc_if->sk_ring_map)) { 1342 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1343 bus_dmamem_unmap(sc->sc_dmatag, kva, 1344 sizeof(struct sk_ring_data)); 1345 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1346 goto fail; 1347 } 1348 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1349 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1350 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1351 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1352 bus_dmamem_unmap(sc->sc_dmatag, kva, 1353 sizeof(struct sk_ring_data)); 1354 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1355 goto fail; 1356 } 1357 1358 for (i = 0; i < SK_RX_RING_CNT; i++) 1359 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1360 1361 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1362 for (i = 0; i < SK_TX_RING_CNT; i++) { 1363 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1364 1365 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1366 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1367 aprint_error_dev(sc_if->sk_dev, 1368 "Can't create TX dmamap\n"); 1369 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1370 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1371 bus_dmamem_unmap(sc->sc_dmatag, kva, 1372 sizeof(struct sk_ring_data)); 1373 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1374 goto fail; 1375 } 1376 1377 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1378 if (!entry) { 1379 aprint_error_dev(sc_if->sk_dev, 1380 "Can't alloc txmap entry\n"); 1381 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1382 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1383 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1384 bus_dmamem_unmap(sc->sc_dmatag, kva, 1385 sizeof(struct sk_ring_data)); 1386 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1387 goto fail; 1388 } 1389 entry->dmamap = dmamap; 1390 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1391 } 1392 1393 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1394 memset(sc_if->sk_rdata, 0, sizeof(struct sk_ring_data)); 1395 1396 ifp = &sc_if->sk_ethercom.ec_if; 1397 /* Try to allocate memory for jumbo buffers. */ 1398 if (sk_alloc_jumbo_mem(sc_if)) { 1399 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1400 goto fail; 1401 } 1402 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1403 | ETHERCAP_JUMBO_MTU; 1404 1405 ifp->if_softc = sc_if; 1406 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1407 ifp->if_ioctl = sk_ioctl; 1408 ifp->if_start = sk_start; 1409 ifp->if_stop = sk_stop; 1410 ifp->if_init = sk_init; 1411 ifp->if_watchdog = sk_watchdog; 1412 ifp->if_capabilities = 0; 1413 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1414 IFQ_SET_READY(&ifp->if_snd); 1415 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1416 1417 /* 1418 * Do miibus setup. 1419 */ 1420 switch (sc->sk_type) { 1421 case SK_GENESIS: 1422 sk_init_xmac(sc_if); 1423 break; 1424 case SK_YUKON: 1425 case SK_YUKON_LITE: 1426 case SK_YUKON_LP: 1427 sk_init_yukon(sc_if); 1428 break; 1429 default: 1430 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1431 sc->sk_type); 1432 goto fail; 1433 } 1434 1435 DPRINTFN(2, ("sk_attach: 1\n")); 1436 1437 sc_if->sk_mii.mii_ifp = ifp; 1438 switch (sc->sk_type) { 1439 case SK_GENESIS: 1440 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1441 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1442 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1443 break; 1444 case SK_YUKON: 1445 case SK_YUKON_LITE: 1446 case SK_YUKON_LP: 1447 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1448 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1449 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1450 mii_flags = MIIF_DOPAUSE; 1451 break; 1452 } 1453 1454 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii; 1455 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1456 sk_ifmedia_upd, ether_mediastatus); 1457 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1458 MII_OFFSET_ANY, mii_flags); 1459 if (LIST_EMPTY(&sc_if->sk_mii.mii_phys)) { 1460 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1461 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER | IFM_MANUAL, 1462 0, NULL); 1463 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER | IFM_MANUAL); 1464 } else 1465 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER | IFM_AUTO); 1466 1467 callout_init(&sc_if->sk_tick_ch, 0); 1468 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1469 1470 DPRINTFN(2, ("sk_attach: 1\n")); 1471 1472 /* 1473 * Call MI attach routines. 1474 */ 1475 if_attach(ifp); 1476 if_deferred_start_init(ifp, NULL); 1477 1478 ether_ifattach(ifp, sc_if->sk_enaddr); 1479 1480 if (sc->rnd_attached++ == 0) { 1481 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1482 RND_TYPE_NET, RND_FLAG_DEFAULT); 1483 } 1484 1485 if (pmf_device_register(self, NULL, sk_resume)) 1486 pmf_class_network_register(self, ifp); 1487 else 1488 aprint_error_dev(self, "couldn't establish power handler\n"); 1489 1490 DPRINTFN(2, ("sk_attach: end\n")); 1491 1492 return; 1493 1494 fail: 1495 sc->sk_if[sa->skc_port] = NULL; 1496 } 1497 1498 int 1499 skcprint(void *aux, const char *pnp) 1500 { 1501 struct skc_attach_args *sa = aux; 1502 1503 if (pnp) 1504 aprint_normal("sk port %c at %s", 1505 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1506 else 1507 aprint_normal(" port %c", 1508 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1509 return UNCONF; 1510 } 1511 1512 /* 1513 * Attach the interface. Allocate softc structures, do ifmedia 1514 * setup and ethernet/BPF attach. 1515 */ 1516 void 1517 skc_attach(device_t parent, device_t self, void *aux) 1518 { 1519 struct sk_softc *sc = device_private(self); 1520 struct pci_attach_args *pa = aux; 1521 struct skc_attach_args skca; 1522 pci_chipset_tag_t pc = pa->pa_pc; 1523 #ifndef SK_USEIOSPACE 1524 pcireg_t memtype; 1525 #endif 1526 pci_intr_handle_t ih; 1527 const char *intrstr = NULL; 1528 bus_addr_t iobase; 1529 bus_size_t iosize; 1530 int rc, sk_nodenum; 1531 uint32_t command; 1532 const char *revstr; 1533 const struct sysctlnode *node; 1534 char intrbuf[PCI_INTRSTR_LEN]; 1535 1536 sc->sk_dev = self; 1537 aprint_naive("\n"); 1538 1539 DPRINTFN(2, ("begin skc_attach\n")); 1540 1541 /* 1542 * Handle power management nonsense. 1543 */ 1544 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1545 1546 if (command == 0x01) { 1547 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1548 if (command & SK_PSTATE_MASK) { 1549 uint32_t xiobase, membase, irq; 1550 1551 /* Save important PCI config data. */ 1552 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1553 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1554 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1555 1556 /* Reset the power state. */ 1557 aprint_normal_dev(sc->sk_dev, 1558 "chip is in D%d power mode -- setting to D0\n", 1559 command & SK_PSTATE_MASK); 1560 command &= 0xFFFFFFFC; 1561 pci_conf_write(pc, pa->pa_tag, 1562 SK_PCI_PWRMGMTCTRL, command); 1563 1564 /* Restore PCI config data. */ 1565 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1566 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1567 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1568 } 1569 } 1570 1571 /* 1572 * The firmware might have configured the interface to revert the 1573 * byte order in all descriptors. Make that undone. 1574 */ 1575 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_OURREG2); 1576 if (command & SK_REG2_REV_DESC) 1577 pci_conf_write(pc, pa->pa_tag, SK_PCI_OURREG2, 1578 command & ~SK_REG2_REV_DESC); 1579 1580 /* 1581 * Map control/status registers. 1582 */ 1583 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1584 command |= PCI_COMMAND_IO_ENABLE | 1585 PCI_COMMAND_MEM_ENABLE | 1586 PCI_COMMAND_MASTER_ENABLE; 1587 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1588 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1589 1590 #ifdef SK_USEIOSPACE 1591 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1592 aprint_error(": failed to enable I/O ports!\n"); 1593 return; 1594 } 1595 /* 1596 * Map control/status registers. 1597 */ 1598 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1599 &sc->sk_btag, &sc->sk_bhandle, 1600 &iobase, &iosize)) { 1601 aprint_error(": can't find i/o space\n"); 1602 return; 1603 } 1604 #else 1605 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1606 aprint_error(": failed to enable memory mapping!\n"); 1607 return; 1608 } 1609 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1610 switch (memtype) { 1611 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1612 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1613 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1614 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1615 &iobase, &iosize) == 0) 1616 break; 1617 /* FALLTHROUGH */ 1618 default: 1619 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1620 return; 1621 } 1622 1623 DPRINTFN(2, ("skc_attach: iobase=%#" PRIxPADDR ", iosize=%zx\n", 1624 iobase, iosize)); 1625 #endif 1626 sc->sc_dmatag = pa->pa_dmat; 1627 1628 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1629 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1630 1631 /* bail out here if chip is not recognized */ 1632 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1633 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1634 goto fail; 1635 } 1636 if (SK_IS_YUKON2(sc)) { 1637 aprint_error_dev(sc->sk_dev, 1638 "Does not support Yukon2--try msk(4).\n"); 1639 goto fail; 1640 } 1641 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1642 1643 /* Allocate interrupt */ 1644 if (pci_intr_map(pa, &ih)) { 1645 aprint_error(": couldn't map interrupt\n"); 1646 goto fail; 1647 } 1648 1649 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1650 sc->sk_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, sk_intr, sc, 1651 device_xname(sc->sk_dev)); 1652 if (sc->sk_intrhand == NULL) { 1653 aprint_error(": couldn't establish interrupt"); 1654 if (intrstr != NULL) 1655 aprint_error(" at %s", intrstr); 1656 aprint_error("\n"); 1657 goto fail; 1658 } 1659 aprint_normal(": %s\n", intrstr); 1660 1661 /* Reset the adapter. */ 1662 sk_reset(sc); 1663 1664 /* Read and save vital product data from EEPROM. */ 1665 sk_vpd_read(sc); 1666 1667 if (sc->sk_type == SK_GENESIS) { 1668 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1669 /* Read and save RAM size and RAMbuffer offset */ 1670 switch (val) { 1671 case SK_RAMSIZE_512K_64: 1672 sc->sk_ramsize = 0x80000; 1673 sc->sk_rboff = SK_RBOFF_0; 1674 break; 1675 case SK_RAMSIZE_1024K_64: 1676 sc->sk_ramsize = 0x100000; 1677 sc->sk_rboff = SK_RBOFF_80000; 1678 break; 1679 case SK_RAMSIZE_1024K_128: 1680 sc->sk_ramsize = 0x100000; 1681 sc->sk_rboff = SK_RBOFF_0; 1682 break; 1683 case SK_RAMSIZE_2048K_128: 1684 sc->sk_ramsize = 0x200000; 1685 sc->sk_rboff = SK_RBOFF_0; 1686 break; 1687 default: 1688 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1689 val); 1690 goto fail_1; 1691 break; 1692 } 1693 1694 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1695 sc->sk_ramsize, sc->sk_ramsize / 1024, 1696 sc->sk_rboff)); 1697 } else { 1698 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1699 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1700 sc->sk_rboff = SK_RBOFF_0; 1701 1702 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1703 sc->sk_ramsize / 1024, sc->sk_ramsize, 1704 sc->sk_rboff)); 1705 } 1706 1707 /* Read and save physical media type */ 1708 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1709 case SK_PMD_1000BASESX: 1710 sc->sk_pmd = IFM_1000_SX; 1711 break; 1712 case SK_PMD_1000BASELX: 1713 sc->sk_pmd = IFM_1000_LX; 1714 break; 1715 case SK_PMD_1000BASECX: 1716 sc->sk_pmd = IFM_1000_CX; 1717 break; 1718 case SK_PMD_1000BASETX: 1719 case SK_PMD_1000BASETX_ALT: 1720 sc->sk_pmd = IFM_1000_T; 1721 break; 1722 default: 1723 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1724 sk_win_read_1(sc, SK_PMDTYPE)); 1725 goto fail_1; 1726 } 1727 1728 /* determine whether to name it with vpd or just make it up */ 1729 /* Marvell Yukon VPD's can freqently be bogus */ 1730 1731 switch (pa->pa_id) { 1732 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1733 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1734 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1735 case PCI_PRODUCT_3COM_3C940: 1736 case PCI_PRODUCT_DLINK_DGE530T: 1737 case PCI_PRODUCT_DLINK_DGE560T: 1738 case PCI_PRODUCT_DLINK_DGE560T_2: 1739 case PCI_PRODUCT_LINKSYS_EG1032: 1740 case PCI_PRODUCT_LINKSYS_EG1064: 1741 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1742 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1743 case PCI_ID_CODE(PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940): 1744 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T): 1745 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T): 1746 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2): 1747 case PCI_ID_CODE(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032): 1748 case PCI_ID_CODE(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064): 1749 sc->sk_name = sc->sk_vpd_prodname; 1750 break; 1751 case PCI_ID_CODE(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET): 1752 /* whoops yukon vpd prodname bears no resemblance to reality */ 1753 switch (sc->sk_type) { 1754 case SK_GENESIS: 1755 sc->sk_name = sc->sk_vpd_prodname; 1756 break; 1757 case SK_YUKON: 1758 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1759 break; 1760 case SK_YUKON_LITE: 1761 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1762 break; 1763 case SK_YUKON_LP: 1764 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1765 break; 1766 default: 1767 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1768 } 1769 1770 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1771 1772 if ( sc->sk_type == SK_YUKON ) { 1773 uint32_t flashaddr; 1774 uint8_t testbyte; 1775 1776 flashaddr = sk_win_read_4(sc, SK_EP_ADDR); 1777 1778 /* test Flash-Address Register */ 1779 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff); 1780 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1781 1782 if (testbyte != 0) { 1783 /* this is yukon lite Rev. A0 */ 1784 sc->sk_type = SK_YUKON_LITE; 1785 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1786 /* restore Flash-Address Register */ 1787 sk_win_write_4(sc, SK_EP_ADDR, flashaddr); 1788 } 1789 } 1790 break; 1791 case PCI_ID_CODE(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN): 1792 sc->sk_name = sc->sk_vpd_prodname; 1793 break; 1794 default: 1795 sc->sk_name = "Unknown Marvell"; 1796 } 1797 1798 1799 if ( sc->sk_type == SK_YUKON_LITE ) { 1800 switch (sc->sk_rev) { 1801 case SK_YUKON_LITE_REV_A0: 1802 revstr = "A0"; 1803 break; 1804 case SK_YUKON_LITE_REV_A1: 1805 revstr = "A1"; 1806 break; 1807 case SK_YUKON_LITE_REV_A3: 1808 revstr = "A3"; 1809 break; 1810 default: 1811 revstr = ""; 1812 } 1813 } else { 1814 revstr = ""; 1815 } 1816 1817 /* Announce the product name. */ 1818 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1819 sc->sk_name, revstr, sc->sk_rev); 1820 1821 skca.skc_port = SK_PORT_A; 1822 (void)config_found(sc->sk_dev, &skca, skcprint); 1823 1824 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1825 skca.skc_port = SK_PORT_B; 1826 (void)config_found(sc->sk_dev, &skca, skcprint); 1827 } 1828 1829 /* Turn on the 'driver is loaded' LED. */ 1830 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1831 1832 /* skc sysctl setup */ 1833 1834 sc->sk_int_mod = SK_IM_DEFAULT; 1835 sc->sk_int_mod_pending = 0; 1836 1837 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1838 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1839 SYSCTL_DESCR("skc per-controller controls"), 1840 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1841 CTL_EOL)) != 0) { 1842 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1843 goto fail_1; 1844 } 1845 1846 sk_nodenum = node->sysctl_num; 1847 1848 /* interrupt moderation time in usecs */ 1849 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1850 CTLFLAG_READWRITE, 1851 CTLTYPE_INT, "int_mod", 1852 SYSCTL_DESCR("sk interrupt moderation timer"), 1853 sk_sysctl_handler, 0, (void *)sc, 1854 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1855 CTL_EOL)) != 0) { 1856 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1857 goto fail_1; 1858 } 1859 1860 if (!pmf_device_register(self, skc_suspend, skc_resume)) 1861 aprint_error_dev(self, "couldn't establish power handler\n"); 1862 1863 return; 1864 1865 fail_1: 1866 pci_intr_disestablish(pc, sc->sk_intrhand); 1867 fail: 1868 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1869 } 1870 1871 int 1872 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1873 { 1874 struct sk_softc *sc = sc_if->sk_softc; 1875 struct sk_tx_desc *f = NULL; 1876 uint32_t frag, cur, cnt = 0, sk_ctl; 1877 int i; 1878 struct sk_txmap_entry *entry; 1879 bus_dmamap_t txmap; 1880 1881 DPRINTFN(3, ("sk_encap\n")); 1882 1883 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1884 if (entry == NULL) { 1885 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1886 return ENOBUFS; 1887 } 1888 txmap = entry->dmamap; 1889 1890 cur = frag = *txidx; 1891 1892 #ifdef SK_DEBUG 1893 if (skdebug >= 3) 1894 sk_dump_mbuf(m_head); 1895 #endif 1896 1897 /* 1898 * Start packing the mbufs in this chain into 1899 * the fragment pointers. Stop when we run out 1900 * of fragments or hit the end of the mbuf chain. 1901 */ 1902 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1903 BUS_DMA_NOWAIT)) { 1904 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1905 return ENOBUFS; 1906 } 1907 1908 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1909 1910 /* Sync the DMA map. */ 1911 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1912 BUS_DMASYNC_PREWRITE); 1913 1914 for (i = 0; i < txmap->dm_nsegs; i++) { 1915 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1916 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1917 return ENOBUFS; 1918 } 1919 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1920 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1921 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1922 if (cnt == 0) 1923 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1924 else 1925 sk_ctl |= SK_TXCTL_OWN; 1926 f->sk_ctl = htole32(sk_ctl); 1927 cur = frag; 1928 SK_INC(frag, SK_TX_RING_CNT); 1929 cnt++; 1930 } 1931 1932 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1933 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1934 1935 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1936 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1937 htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 1938 1939 /* Sync descriptors before handing to chip */ 1940 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1941 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1942 1943 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1944 htole32(SK_TXCTL_OWN); 1945 1946 /* Sync first descriptor to hand it off */ 1947 SK_CDTXSYNC(sc_if, *txidx, 1, 1948 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1949 1950 sc_if->sk_cdata.sk_tx_cnt += cnt; 1951 1952 #ifdef SK_DEBUG 1953 if (skdebug >= 3) { 1954 struct sk_tx_desc *desc; 1955 uint32_t idx; 1956 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1957 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1958 sk_dump_txdesc(desc, idx); 1959 } 1960 } 1961 #endif 1962 1963 *txidx = frag; 1964 1965 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1966 1967 return 0; 1968 } 1969 1970 void 1971 sk_start(struct ifnet *ifp) 1972 { 1973 struct sk_if_softc *sc_if = ifp->if_softc; 1974 struct sk_softc *sc = sc_if->sk_softc; 1975 struct mbuf *m_head = NULL; 1976 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1977 int pkts = 0; 1978 1979 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1980 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1981 1982 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1983 IFQ_POLL(&ifp->if_snd, m_head); 1984 if (m_head == NULL) 1985 break; 1986 1987 /* 1988 * Pack the data into the transmit ring. If we 1989 * don't have room, set the OACTIVE flag and wait 1990 * for the NIC to drain the ring. 1991 */ 1992 if (sk_encap(sc_if, m_head, &idx)) { 1993 ifp->if_flags |= IFF_OACTIVE; 1994 break; 1995 } 1996 1997 /* now we are committed to transmit the packet */ 1998 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1999 pkts++; 2000 2001 /* 2002 * If there's a BPF listener, bounce a copy of this frame 2003 * to him. 2004 */ 2005 bpf_mtap(ifp, m_head, BPF_D_OUT); 2006 } 2007 if (pkts == 0) 2008 return; 2009 2010 /* Transmit */ 2011 if (idx != sc_if->sk_cdata.sk_tx_prod) { 2012 sc_if->sk_cdata.sk_tx_prod = idx; 2013 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2014 2015 /* Set a timeout in case the chip goes out to lunch. */ 2016 ifp->if_timer = 5; 2017 } 2018 } 2019 2020 2021 void 2022 sk_watchdog(struct ifnet *ifp) 2023 { 2024 struct sk_if_softc *sc_if = ifp->if_softc; 2025 2026 /* 2027 * Reclaim first as there is a possibility of losing Tx completion 2028 * interrupts. 2029 */ 2030 sk_txeof(sc_if); 2031 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2032 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 2033 2034 ifp->if_oerrors++; 2035 2036 sk_init(ifp); 2037 } 2038 } 2039 2040 void 2041 sk_shutdown(void *v) 2042 { 2043 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2044 struct sk_softc *sc = sc_if->sk_softc; 2045 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2046 2047 DPRINTFN(2, ("sk_shutdown\n")); 2048 sk_stop(ifp, 1); 2049 2050 /* Turn off the 'driver is loaded' LED. */ 2051 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2052 2053 /* 2054 * Reset the GEnesis controller. Doing this should also 2055 * assert the resets on the attached XMAC(s). 2056 */ 2057 sk_reset(sc); 2058 } 2059 2060 void 2061 sk_rxeof(struct sk_if_softc *sc_if) 2062 { 2063 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2064 struct mbuf *m; 2065 struct sk_chain *cur_rx; 2066 struct sk_rx_desc *cur_desc; 2067 int i, cur, total_len = 0; 2068 uint32_t rxstat, sk_ctl; 2069 bus_dmamap_t dmamap; 2070 2071 i = sc_if->sk_cdata.sk_rx_prod; 2072 2073 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2074 2075 for (;;) { 2076 cur = i; 2077 2078 /* Sync the descriptor */ 2079 SK_CDRXSYNC(sc_if, cur, 2080 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2081 2082 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2083 if (sk_ctl & SK_RXCTL_OWN) { 2084 /* Invalidate the descriptor -- it's not ready yet */ 2085 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2086 sc_if->sk_cdata.sk_rx_prod = i; 2087 break; 2088 } 2089 2090 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2091 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2092 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2093 2094 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2095 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2096 2097 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2098 m = cur_rx->sk_mbuf; 2099 cur_rx->sk_mbuf = NULL; 2100 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2101 2102 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2103 2104 SK_INC(i, SK_RX_RING_CNT); 2105 2106 if (rxstat & XM_RXSTAT_ERRFRAME) { 2107 ifp->if_ierrors++; 2108 sk_newbuf(sc_if, cur, m, dmamap); 2109 continue; 2110 } 2111 2112 /* 2113 * Try to allocate a new jumbo buffer. If that 2114 * fails, copy the packet to mbufs and put the 2115 * jumbo buffer back in the ring so it can be 2116 * re-used. If allocating mbufs fails, then we 2117 * have to drop the packet. 2118 */ 2119 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2120 struct mbuf *m0; 2121 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2122 total_len + ETHER_ALIGN, 0, ifp); 2123 sk_newbuf(sc_if, cur, m, dmamap); 2124 if (m0 == NULL) { 2125 aprint_error_dev(sc_if->sk_dev, "no receive " 2126 "buffers available -- packet dropped!\n"); 2127 ifp->if_ierrors++; 2128 continue; 2129 } 2130 m_adj(m0, ETHER_ALIGN); 2131 m = m0; 2132 } else { 2133 m_set_rcvif(m, ifp); 2134 m->m_pkthdr.len = m->m_len = total_len; 2135 } 2136 2137 /* pass it on. */ 2138 if_percpuq_enqueue(ifp->if_percpuq, m); 2139 } 2140 } 2141 2142 void 2143 sk_txeof(struct sk_if_softc *sc_if) 2144 { 2145 struct sk_softc *sc = sc_if->sk_softc; 2146 struct sk_tx_desc *cur_tx; 2147 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2148 uint32_t idx, sk_ctl; 2149 struct sk_txmap_entry *entry; 2150 2151 DPRINTFN(3, ("sk_txeof\n")); 2152 2153 /* 2154 * Go through our tx ring and free mbufs for those 2155 * frames that have been sent. 2156 */ 2157 idx = sc_if->sk_cdata.sk_tx_cons; 2158 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2159 SK_CDTXSYNC(sc_if, idx, 1, 2160 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2161 2162 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2163 sk_ctl = le32toh(cur_tx->sk_ctl); 2164 #ifdef SK_DEBUG 2165 if (skdebug >= 3) 2166 sk_dump_txdesc(cur_tx, idx); 2167 #endif 2168 if (sk_ctl & SK_TXCTL_OWN) { 2169 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2170 break; 2171 } 2172 if (sk_ctl & SK_TXCTL_LASTFRAG) 2173 ifp->if_opackets++; 2174 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2175 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2176 2177 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2178 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2179 2180 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2181 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2182 2183 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2184 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2185 link); 2186 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2187 } 2188 sc_if->sk_cdata.sk_tx_cnt--; 2189 SK_INC(idx, SK_TX_RING_CNT); 2190 } 2191 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2192 ifp->if_timer = 0; 2193 else /* nudge chip to keep tx ring moving */ 2194 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2195 2196 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2197 ifp->if_flags &= ~IFF_OACTIVE; 2198 2199 sc_if->sk_cdata.sk_tx_cons = idx; 2200 } 2201 2202 void 2203 sk_tick(void *xsc_if) 2204 { 2205 struct sk_if_softc *sc_if = xsc_if; 2206 struct mii_data *mii = &sc_if->sk_mii; 2207 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2208 int i; 2209 2210 DPRINTFN(3, ("sk_tick\n")); 2211 2212 if (!(ifp->if_flags & IFF_UP)) 2213 return; 2214 2215 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2216 sk_intr_bcom(sc_if); 2217 return; 2218 } 2219 2220 /* 2221 * According to SysKonnect, the correct way to verify that 2222 * the link has come back up is to poll bit 0 of the GPIO 2223 * register three times. This pin has the signal from the 2224 * link sync pin connected to it; if we read the same link 2225 * state 3 times in a row, we know the link is up. 2226 */ 2227 for (i = 0; i < 3; i++) { 2228 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2229 break; 2230 } 2231 2232 if (i != 3) { 2233 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2234 return; 2235 } 2236 2237 /* Turn the GP0 interrupt back on. */ 2238 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2239 SK_XM_READ_2(sc_if, XM_ISR); 2240 mii_tick(mii); 2241 if (ifp->if_link_state != LINK_STATE_UP) 2242 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2243 else 2244 callout_stop(&sc_if->sk_tick_ch); 2245 } 2246 2247 void 2248 sk_intr_bcom(struct sk_if_softc *sc_if) 2249 { 2250 struct mii_data *mii = &sc_if->sk_mii; 2251 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2252 uint16_t status; 2253 2254 2255 DPRINTFN(3, ("sk_intr_bcom\n")); 2256 2257 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2258 2259 /* 2260 * Read the PHY interrupt register to make sure 2261 * we clear any pending interrupts. 2262 */ 2263 sk_xmac_miibus_readreg(sc_if->sk_dev, 2264 SK_PHYADDR_BCOM, BRGPHY_MII_ISR, &status); 2265 2266 if (!(ifp->if_flags & IFF_RUNNING)) { 2267 sk_init_xmac(sc_if); 2268 return; 2269 } 2270 2271 if (status & (BRGPHY_ISR_LNK_CHG | BRGPHY_ISR_AN_PR)) { 2272 uint16_t lstat; 2273 sk_xmac_miibus_readreg(sc_if->sk_dev, 2274 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS, &lstat); 2275 2276 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2277 (void)mii_mediachg(mii); 2278 /* Turn off the link LED. */ 2279 SK_IF_WRITE_1(sc_if, 0, 2280 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2281 sc_if->sk_link = 0; 2282 } else if (status & BRGPHY_ISR_LNK_CHG) { 2283 sk_xmac_miibus_writereg(sc_if->sk_dev, 2284 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2285 mii_tick(mii); 2286 sc_if->sk_link = 1; 2287 /* Turn on the link LED. */ 2288 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2289 SK_LINKLED_ON | SK_LINKLED_LINKSYNC_OFF | 2290 SK_LINKLED_BLINK_OFF); 2291 mii_pollstat(mii); 2292 } else { 2293 mii_tick(mii); 2294 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2295 } 2296 } 2297 2298 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2299 } 2300 2301 void 2302 sk_intr_xmac(struct sk_if_softc *sc_if) 2303 { 2304 uint16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2305 2306 DPRINTFN(3, ("sk_intr_xmac\n")); 2307 2308 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2309 if (status & XM_ISR_GP0_SET) { 2310 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2311 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2312 } 2313 2314 if (status & XM_ISR_AUTONEG_DONE) { 2315 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2316 } 2317 } 2318 2319 if (status & XM_IMR_TX_UNDERRUN) 2320 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2321 2322 if (status & XM_IMR_RX_OVERRUN) 2323 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2324 } 2325 2326 void 2327 sk_intr_yukon(struct sk_if_softc *sc_if) 2328 { 2329 #ifdef SK_DEBUG 2330 int status; 2331 2332 status = 2333 #endif 2334 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2335 2336 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2337 } 2338 2339 int 2340 sk_intr(void *xsc) 2341 { 2342 struct sk_softc *sc = xsc; 2343 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2344 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2345 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2346 uint32_t status; 2347 int claimed = 0; 2348 2349 if (sc_if0 != NULL) 2350 ifp0 = &sc_if0->sk_ethercom.ec_if; 2351 if (sc_if1 != NULL) 2352 ifp1 = &sc_if1->sk_ethercom.ec_if; 2353 2354 for (;;) { 2355 status = CSR_READ_4(sc, SK_ISSR); 2356 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2357 2358 if (!(status & sc->sk_intrmask)) 2359 break; 2360 2361 claimed = 1; 2362 2363 /* Handle receive interrupts first. */ 2364 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2365 sk_rxeof(sc_if0); 2366 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2367 SK_RXBMU_CLR_IRQ_EOF | SK_RXBMU_RX_START); 2368 } 2369 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2370 sk_rxeof(sc_if1); 2371 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2372 SK_RXBMU_CLR_IRQ_EOF | SK_RXBMU_RX_START); 2373 } 2374 2375 /* Then transmit interrupts. */ 2376 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2377 sk_txeof(sc_if0); 2378 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2379 SK_TXBMU_CLR_IRQ_EOF); 2380 } 2381 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2382 sk_txeof(sc_if1); 2383 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2384 SK_TXBMU_CLR_IRQ_EOF); 2385 } 2386 2387 /* Then MAC interrupts. */ 2388 if (sc_if0 && (status & SK_ISR_MAC1) && 2389 (ifp0->if_flags & IFF_RUNNING)) { 2390 if (sc->sk_type == SK_GENESIS) 2391 sk_intr_xmac(sc_if0); 2392 else 2393 sk_intr_yukon(sc_if0); 2394 } 2395 2396 if (sc_if1 && (status & SK_ISR_MAC2) && 2397 (ifp1->if_flags & IFF_RUNNING)) { 2398 if (sc->sk_type == SK_GENESIS) 2399 sk_intr_xmac(sc_if1); 2400 else 2401 sk_intr_yukon(sc_if1); 2402 2403 } 2404 2405 if (status & SK_ISR_EXTERNAL_REG) { 2406 if (sc_if0 != NULL && 2407 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2408 sk_intr_bcom(sc_if0); 2409 2410 if (sc_if1 != NULL && 2411 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2412 sk_intr_bcom(sc_if1); 2413 } 2414 } 2415 2416 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2417 2418 if (ifp0 != NULL) 2419 if_schedule_deferred_start(ifp0); 2420 if (ifp1 != NULL) 2421 if_schedule_deferred_start(ifp1); 2422 2423 KASSERT(sc->rnd_attached > 0); 2424 rnd_add_uint32(&sc->rnd_source, status); 2425 2426 if (sc->sk_int_mod_pending) 2427 sk_update_int_mod(sc); 2428 2429 return claimed; 2430 } 2431 2432 void 2433 sk_init_xmac(struct sk_if_softc *sc_if) 2434 { 2435 struct sk_softc *sc = sc_if->sk_softc; 2436 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2437 static const struct sk_bcom_hack bhack[] = { 2438 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2439 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2440 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2441 { 0, 0 } }; 2442 2443 DPRINTFN(1, ("sk_init_xmac\n")); 2444 2445 /* Unreset the XMAC. */ 2446 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2447 DELAY(1000); 2448 2449 /* Reset the XMAC's internal state. */ 2450 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2451 2452 /* Save the XMAC II revision */ 2453 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2454 2455 /* 2456 * Perform additional initialization for external PHYs, 2457 * namely for the 1000baseTX cards that use the XMAC's 2458 * GMII mode. 2459 */ 2460 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2461 int i = 0; 2462 uint32_t val; 2463 uint16_t phyval; 2464 2465 /* Take PHY out of reset. */ 2466 val = sk_win_read_4(sc, SK_GPIO); 2467 if (sc_if->sk_port == SK_PORT_A) 2468 val |= SK_GPIO_DIR0 | SK_GPIO_DAT0; 2469 else 2470 val |= SK_GPIO_DIR2 | SK_GPIO_DAT2; 2471 sk_win_write_4(sc, SK_GPIO, val); 2472 2473 /* Enable GMII mode on the XMAC. */ 2474 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2475 2476 sk_xmac_miibus_writereg(sc_if->sk_dev, 2477 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2478 DELAY(10000); 2479 sk_xmac_miibus_writereg(sc_if->sk_dev, 2480 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2481 2482 /* 2483 * Early versions of the BCM5400 apparently have 2484 * a bug that requires them to have their reserved 2485 * registers initialized to some magic values. I don't 2486 * know what the numbers do, I'm just the messenger. 2487 */ 2488 sk_xmac_miibus_readreg(sc_if->sk_dev, 2489 SK_PHYADDR_BCOM, 0x03, &phyval); 2490 if (phyval == 0x6041) { 2491 while (bhack[i].reg) { 2492 sk_xmac_miibus_writereg(sc_if->sk_dev, 2493 SK_PHYADDR_BCOM, bhack[i].reg, 2494 bhack[i].val); 2495 i++; 2496 } 2497 } 2498 } 2499 2500 /* Set station address */ 2501 SK_XM_WRITE_2(sc_if, XM_PAR0, 2502 *(uint16_t *)(&sc_if->sk_enaddr[0])); 2503 SK_XM_WRITE_2(sc_if, XM_PAR1, 2504 *(uint16_t *)(&sc_if->sk_enaddr[2])); 2505 SK_XM_WRITE_2(sc_if, XM_PAR2, 2506 *(uint16_t *)(&sc_if->sk_enaddr[4])); 2507 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2508 2509 if (ifp->if_flags & IFF_PROMISC) 2510 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2511 else 2512 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2513 2514 if (ifp->if_flags & IFF_BROADCAST) 2515 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2516 else 2517 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2518 2519 /* We don't need the FCS appended to the packet. */ 2520 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2521 2522 /* We want short frames padded to 60 bytes. */ 2523 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2524 2525 /* 2526 * Enable the reception of all error frames. This is is 2527 * a necessary evil due to the design of the XMAC. The 2528 * XMAC's receive FIFO is only 8K in size, however jumbo 2529 * frames can be up to 9000 bytes in length. When bad 2530 * frame filtering is enabled, the XMAC's RX FIFO operates 2531 * in 'store and forward' mode. For this to work, the 2532 * entire frame has to fit into the FIFO, but that means 2533 * that jumbo frames larger than 8192 bytes will be 2534 * truncated. Disabling all bad frame filtering causes 2535 * the RX FIFO to operate in streaming mode, in which 2536 * case the XMAC will start transfering frames out of the 2537 * RX FIFO as soon as the FIFO threshold is reached. 2538 */ 2539 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES | 2540 XM_MODE_RX_GIANTS | XM_MODE_RX_RUNTS | XM_MODE_RX_CRCERRS | 2541 XM_MODE_RX_INRANGELEN); 2542 2543 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2544 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2545 else 2546 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2547 2548 /* 2549 * Bump up the transmit threshold. This helps hold off transmit 2550 * underruns when we're blasting traffic from both ports at once. 2551 */ 2552 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2553 2554 /* Set multicast filter */ 2555 sk_setmulti(sc_if); 2556 2557 /* Clear and enable interrupts */ 2558 SK_XM_READ_2(sc_if, XM_ISR); 2559 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2560 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2561 else 2562 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2563 2564 /* Configure MAC arbiter */ 2565 switch (sc_if->sk_xmac_rev) { 2566 case XM_XMAC_REV_B2: 2567 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2568 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2569 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2570 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2571 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2572 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2573 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2574 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2575 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2576 break; 2577 case XM_XMAC_REV_C1: 2578 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2579 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2580 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2581 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2582 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2583 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2584 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2585 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2586 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2587 break; 2588 default: 2589 break; 2590 } 2591 sk_win_write_2(sc, SK_MACARB_CTL, 2592 SK_MACARBCTL_UNRESET | SK_MACARBCTL_FASTOE_OFF); 2593 2594 sc_if->sk_link = 1; 2595 } 2596 2597 void sk_init_yukon(struct sk_if_softc *sc_if) 2598 { 2599 uint32_t /*mac, */phy; 2600 uint16_t reg; 2601 struct sk_softc *sc; 2602 int i; 2603 2604 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2605 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2606 2607 sc = sc_if->sk_softc; 2608 if (sc->sk_type == SK_YUKON_LITE && 2609 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2610 /* Take PHY out of reset. */ 2611 sk_win_write_4(sc, SK_GPIO, 2612 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2613 } 2614 2615 2616 /* GMAC and GPHY Reset */ 2617 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2618 2619 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2620 2621 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2622 DELAY(1000); 2623 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2624 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2625 DELAY(1000); 2626 2627 2628 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2629 2630 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2631 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2632 2633 switch (sc_if->sk_softc->sk_pmd) { 2634 case IFM_1000_SX: 2635 case IFM_1000_LX: 2636 phy |= SK_GPHY_FIBER; 2637 break; 2638 2639 case IFM_1000_CX: 2640 case IFM_1000_T: 2641 phy |= SK_GPHY_COPPER; 2642 break; 2643 } 2644 2645 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2646 2647 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2648 DELAY(1000); 2649 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2650 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2651 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2652 2653 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2654 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2655 2656 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2657 2658 /* unused read of the interrupt source register */ 2659 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2660 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2661 2662 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2663 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2664 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2665 2666 /* MIB Counter Clear Mode set */ 2667 reg |= YU_PAR_MIB_CLR; 2668 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2669 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2670 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2671 2672 /* MIB Counter Clear Mode clear */ 2673 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2674 reg &= ~YU_PAR_MIB_CLR; 2675 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2676 2677 /* receive control reg */ 2678 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2679 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2680 YU_RCR_CRCR); 2681 2682 /* transmit parameter register */ 2683 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2684 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2685 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2686 2687 /* serial mode register */ 2688 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2689 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2690 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2691 YU_SMR_IPG_DATA(0x1e)); 2692 2693 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2694 /* Setup Yukon's address */ 2695 for (i = 0; i < 3; i++) { 2696 /* Write Source Address 1 (unicast filter) */ 2697 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2698 sc_if->sk_enaddr[i * 2] | 2699 sc_if->sk_enaddr[i * 2 + 1] << 8); 2700 } 2701 2702 for (i = 0; i < 3; i++) { 2703 reg = sk_win_read_2(sc_if->sk_softc, 2704 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2705 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2706 } 2707 2708 /* Set multicast filter */ 2709 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2710 sk_setmulti(sc_if); 2711 2712 /* enable interrupt mask for counter overflows */ 2713 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2714 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2715 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2716 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2717 2718 /* Configure RX MAC FIFO */ 2719 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2720 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2721 2722 /* Configure TX MAC FIFO */ 2723 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2724 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2725 2726 DPRINTFN(6, ("sk_init_yukon: end\n")); 2727 } 2728 2729 /* 2730 * Note that to properly initialize any part of the GEnesis chip, 2731 * you first have to take it out of reset mode. 2732 */ 2733 int 2734 sk_init(struct ifnet *ifp) 2735 { 2736 struct sk_if_softc *sc_if = ifp->if_softc; 2737 struct sk_softc *sc = sc_if->sk_softc; 2738 struct mii_data *mii = &sc_if->sk_mii; 2739 int rc = 0, s; 2740 uint32_t imr, imtimer_ticks; 2741 2742 DPRINTFN(1, ("sk_init\n")); 2743 2744 s = splnet(); 2745 2746 if (ifp->if_flags & IFF_RUNNING) { 2747 splx(s); 2748 return 0; 2749 } 2750 2751 /* Cancel pending I/O and free all RX/TX buffers. */ 2752 sk_stop(ifp, 0); 2753 2754 if (sc->sk_type == SK_GENESIS) { 2755 /* Configure LINK_SYNC LED */ 2756 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2757 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2758 SK_LINKLED_LINKSYNC_ON); 2759 2760 /* Configure RX LED */ 2761 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2762 SK_RXLEDCTL_COUNTER_START); 2763 2764 /* Configure TX LED */ 2765 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2766 SK_TXLEDCTL_COUNTER_START); 2767 } 2768 2769 /* Configure I2C registers */ 2770 2771 /* Configure XMAC(s) */ 2772 switch (sc->sk_type) { 2773 case SK_GENESIS: 2774 sk_init_xmac(sc_if); 2775 break; 2776 case SK_YUKON: 2777 case SK_YUKON_LITE: 2778 case SK_YUKON_LP: 2779 sk_init_yukon(sc_if); 2780 break; 2781 } 2782 if ((rc = mii_mediachg(mii)) == ENXIO) 2783 rc = 0; 2784 else if (rc != 0) 2785 goto out; 2786 2787 if (sc->sk_type == SK_GENESIS) { 2788 /* Configure MAC FIFOs */ 2789 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2790 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2791 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2792 2793 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2794 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2795 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2796 } 2797 2798 /* Configure transmit arbiter(s) */ 2799 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2800 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2801 2802 /* Configure RAMbuffers */ 2803 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2804 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2805 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2806 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2807 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2808 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2809 2810 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2811 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2812 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2813 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2814 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2815 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2816 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2817 2818 /* Configure BMUs */ 2819 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2820 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2821 SK_RX_RING_ADDR(sc_if, 0)); 2822 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2823 2824 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2825 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2826 SK_TX_RING_ADDR(sc_if, 0)); 2827 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2828 2829 /* Init descriptors */ 2830 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2831 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2832 "memory for rx buffers\n"); 2833 sk_stop(ifp, 0); 2834 splx(s); 2835 return ENOBUFS; 2836 } 2837 2838 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2839 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2840 "memory for tx buffers\n"); 2841 sk_stop(ifp, 0); 2842 splx(s); 2843 return ENOBUFS; 2844 } 2845 2846 /* Set interrupt moderation if changed via sysctl. */ 2847 switch (sc->sk_type) { 2848 case SK_GENESIS: 2849 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2850 break; 2851 case SK_YUKON_EC: 2852 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2853 break; 2854 default: 2855 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2856 } 2857 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2858 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2859 sk_win_write_4(sc, SK_IMTIMERINIT, 2860 SK_IM_USECS(sc->sk_int_mod)); 2861 aprint_verbose_dev(sc->sk_dev, 2862 "interrupt moderation is %d us\n", sc->sk_int_mod); 2863 } 2864 2865 /* Configure interrupt handling */ 2866 CSR_READ_4(sc, SK_ISSR); 2867 if (sc_if->sk_port == SK_PORT_A) 2868 sc->sk_intrmask |= SK_INTRS1; 2869 else 2870 sc->sk_intrmask |= SK_INTRS2; 2871 2872 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2873 2874 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2875 2876 /* Start BMUs. */ 2877 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2878 2879 if (sc->sk_type == SK_GENESIS) { 2880 /* Enable XMACs TX and RX state machines */ 2881 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2882 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2883 XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2884 } 2885 2886 if (SK_YUKON_FAMILY(sc->sk_type)) { 2887 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2888 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2889 #if 0 2890 /* XXX disable 100Mbps and full duplex mode? */ 2891 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2892 #endif 2893 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2894 } 2895 2896 2897 ifp->if_flags |= IFF_RUNNING; 2898 ifp->if_flags &= ~IFF_OACTIVE; 2899 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2900 2901 out: 2902 splx(s); 2903 return rc; 2904 } 2905 2906 void 2907 sk_stop(struct ifnet *ifp, int disable) 2908 { 2909 struct sk_if_softc *sc_if = ifp->if_softc; 2910 struct sk_softc *sc = sc_if->sk_softc; 2911 int i; 2912 2913 DPRINTFN(1, ("sk_stop\n")); 2914 2915 callout_stop(&sc_if->sk_tick_ch); 2916 2917 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2918 uint32_t val; 2919 2920 /* Put PHY back into reset. */ 2921 val = sk_win_read_4(sc, SK_GPIO); 2922 if (sc_if->sk_port == SK_PORT_A) { 2923 val |= SK_GPIO_DIR0; 2924 val &= ~SK_GPIO_DAT0; 2925 } else { 2926 val |= SK_GPIO_DIR2; 2927 val &= ~SK_GPIO_DAT2; 2928 } 2929 sk_win_write_4(sc, SK_GPIO, val); 2930 } 2931 2932 /* Turn off various components of this interface. */ 2933 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2934 switch (sc->sk_type) { 2935 case SK_GENESIS: 2936 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2937 SK_TXMACCTL_XMAC_RESET); 2938 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2939 break; 2940 case SK_YUKON: 2941 case SK_YUKON_LITE: 2942 case SK_YUKON_LP: 2943 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2944 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2945 break; 2946 } 2947 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2948 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET |SK_RBCTL_OFF); 2949 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2950 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2951 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2952 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2953 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2954 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2955 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2956 2957 /* Disable interrupts */ 2958 if (sc_if->sk_port == SK_PORT_A) 2959 sc->sk_intrmask &= ~SK_INTRS1; 2960 else 2961 sc->sk_intrmask &= ~SK_INTRS2; 2962 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2963 2964 SK_XM_READ_2(sc_if, XM_ISR); 2965 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2966 2967 /* Free RX and TX mbufs still in the queues. */ 2968 for (i = 0; i < SK_RX_RING_CNT; i++) { 2969 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2970 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2971 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2972 } 2973 } 2974 2975 for (i = 0; i < SK_TX_RING_CNT; i++) { 2976 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2977 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2978 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2979 } 2980 } 2981 2982 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2983 } 2984 2985 /* Power Management Framework */ 2986 2987 static bool 2988 skc_suspend(device_t dv, const pmf_qual_t *qual) 2989 { 2990 struct sk_softc *sc = device_private(dv); 2991 2992 DPRINTFN(2, ("skc_suspend\n")); 2993 2994 /* Turn off the driver is loaded LED */ 2995 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2996 2997 return true; 2998 } 2999 3000 static bool 3001 skc_resume(device_t dv, const pmf_qual_t *qual) 3002 { 3003 struct sk_softc *sc = device_private(dv); 3004 3005 DPRINTFN(2, ("skc_resume\n")); 3006 3007 sk_reset(sc); 3008 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 3009 3010 return true; 3011 } 3012 3013 static bool 3014 sk_resume(device_t dv, const pmf_qual_t *qual) 3015 { 3016 struct sk_if_softc *sc_if = device_private(dv); 3017 3018 sk_init_yukon(sc_if); 3019 return true; 3020 } 3021 3022 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 3023 skc_probe, skc_attach, NULL, NULL); 3024 3025 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 3026 sk_probe, sk_attach, NULL, NULL); 3027 3028 #ifdef SK_DEBUG 3029 void 3030 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 3031 { 3032 #define DESC_PRINT(X) \ 3033 if (X) \ 3034 printf("txdesc[%d]." #X "=%#x\n", \ 3035 idx, X); 3036 3037 DESC_PRINT(le32toh(desc->sk_ctl)); 3038 DESC_PRINT(le32toh(desc->sk_next)); 3039 DESC_PRINT(le32toh(desc->sk_data_lo)); 3040 DESC_PRINT(le32toh(desc->sk_data_hi)); 3041 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 3042 DESC_PRINT(le16toh(desc->sk_rsvd0)); 3043 DESC_PRINT(le16toh(desc->sk_csum_startval)); 3044 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 3045 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 3046 DESC_PRINT(le16toh(desc->sk_rsvd1)); 3047 #undef PRINT 3048 } 3049 3050 void 3051 sk_dump_bytes(const char *data, int len) 3052 { 3053 int c, i, j; 3054 3055 for (i = 0; i < len; i += 16) { 3056 printf("%08x ", i); 3057 c = len - i; 3058 if (c > 16) c = 16; 3059 3060 for (j = 0; j < c; j++) { 3061 printf("%02x ", data[i + j] & 0xff); 3062 if ((j & 0xf) == 7 && j > 0) 3063 printf(" "); 3064 } 3065 3066 for (; j < 16; j++) 3067 printf(" "); 3068 printf(" "); 3069 3070 for (j = 0; j < c; j++) { 3071 int ch = data[i + j] & 0xff; 3072 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3073 } 3074 3075 printf("\n"); 3076 3077 if (c < 16) 3078 break; 3079 } 3080 } 3081 3082 void 3083 sk_dump_mbuf(struct mbuf *m) 3084 { 3085 int count = m->m_pkthdr.len; 3086 3087 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3088 3089 while (count > 0 && m) { 3090 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3091 m, m->m_data, m->m_len); 3092 sk_dump_bytes(mtod(m, char *), m->m_len); 3093 3094 count -= m->m_len; 3095 m = m->m_next; 3096 } 3097 } 3098 #endif 3099 3100 static int 3101 sk_sysctl_handler(SYSCTLFN_ARGS) 3102 { 3103 int error, t; 3104 struct sysctlnode node; 3105 struct sk_softc *sc; 3106 3107 node = *rnode; 3108 sc = node.sysctl_data; 3109 t = sc->sk_int_mod; 3110 node.sysctl_data = &t; 3111 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3112 if (error || newp == NULL) 3113 return error; 3114 3115 if (t < SK_IM_MIN || t > SK_IM_MAX) 3116 return EINVAL; 3117 3118 /* update the softc with sysctl-changed value, and mark 3119 for hardware update */ 3120 sc->sk_int_mod = t; 3121 sc->sk_int_mod_pending = 1; 3122 return 0; 3123 } 3124 3125 /* 3126 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3127 * set up in skc_attach() 3128 */ 3129 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3130 { 3131 int rc; 3132 const struct sysctlnode *node; 3133 3134 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3135 0, CTLTYPE_NODE, "sk", 3136 SYSCTL_DESCR("sk interface controls"), 3137 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3138 goto err; 3139 } 3140 3141 sk_root_num = node->sysctl_num; 3142 return; 3143 3144 err: 3145 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3146 } 3147
Indexes created Tue Sep 23 23:09:58 GMT 2025