if_sk.c revision 1.98
1 /* $NetBSD: if_sk.c,v 1.98 2019/05/30 02:32:18 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.98 2019/05/30 02:32:18 msaitoh Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/sockio.h> 123 #include <sys/mbuf.h> 124 #include <sys/malloc.h> 125 #include <sys/mutex.h> 126 #include <sys/kernel.h> 127 #include <sys/socket.h> 128 #include <sys/device.h> 129 #include <sys/queue.h> 130 #include <sys/callout.h> 131 #include <sys/sysctl.h> 132 #include <sys/endian.h> 133 134 #include <net/if.h> 135 #include <net/if_dl.h> 136 #include <net/if_types.h> 137 138 #include <net/if_media.h> 139 140 #include <net/bpf.h> 141 #include <sys/rndsource.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 #include <dev/mii/brgphyreg.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 #include <dev/pci/pcidevs.h> 150 151 /* #define SK_USEIOSPACE */ 152 153 #include <dev/pci/if_skreg.h> 154 #include <dev/pci/if_skvar.h> 155 156 int skc_probe(device_t, cfdata_t, void *); 157 void skc_attach(device_t, device_t, void *aux); 158 int sk_probe(device_t, cfdata_t, void *); 159 void sk_attach(device_t, device_t, void *aux); 160 int skcprint(void *, const char *); 161 int sk_intr(void *); 162 void sk_intr_bcom(struct sk_if_softc *); 163 void sk_intr_xmac(struct sk_if_softc *); 164 void sk_intr_yukon(struct sk_if_softc *); 165 void sk_rxeof(struct sk_if_softc *); 166 void sk_txeof(struct sk_if_softc *); 167 int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 168 void sk_start(struct ifnet *); 169 int sk_ioctl(struct ifnet *, u_long, void *); 170 int sk_init(struct ifnet *); 171 void sk_init_xmac(struct sk_if_softc *); 172 void sk_init_yukon(struct sk_if_softc *); 173 void sk_stop(struct ifnet *, int); 174 void sk_watchdog(struct ifnet *); 175 void sk_shutdown(void *); 176 int sk_ifmedia_upd(struct ifnet *); 177 void sk_reset(struct sk_softc *); 178 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 179 int sk_alloc_jumbo_mem(struct sk_if_softc *); 180 void sk_free_jumbo_mem(struct sk_if_softc *); 181 void *sk_jalloc(struct sk_if_softc *); 182 void sk_jfree(struct mbuf *, void *, size_t, void *); 183 int sk_init_rx_ring(struct sk_if_softc *); 184 int sk_init_tx_ring(struct sk_if_softc *); 185 uint8_t sk_vpd_readbyte(struct sk_softc *, int); 186 void sk_vpd_read_res(struct sk_softc *, 187 struct vpd_res *, int); 188 void sk_vpd_read(struct sk_softc *); 189 190 void sk_update_int_mod(struct sk_softc *); 191 192 int sk_xmac_miibus_readreg(device_t, int, int, uint16_t *); 193 int sk_xmac_miibus_writereg(device_t, int, int, uint16_t); 194 void sk_xmac_miibus_statchg(struct ifnet *); 195 196 int sk_marv_miibus_readreg(device_t, int, int, uint16_t *); 197 int sk_marv_miibus_writereg(device_t, int, int, uint16_t); 198 void sk_marv_miibus_statchg(struct ifnet *); 199 200 uint32_t sk_xmac_hash(void *); 201 uint32_t sk_yukon_hash(void *); 202 void sk_setfilt(struct sk_if_softc *, void *, int); 203 void sk_setmulti(struct sk_if_softc *); 204 void sk_tick(void *); 205 206 static bool skc_suspend(device_t, const pmf_qual_t *); 207 static bool skc_resume(device_t, const pmf_qual_t *); 208 static bool sk_resume(device_t dv, const pmf_qual_t *); 209 210 /* #define SK_DEBUG 2 */ 211 #ifdef SK_DEBUG 212 #define DPRINTF(x) if (skdebug) printf x 213 #define DPRINTFN(n, x) if (skdebug >= (n)) printf x 214 int skdebug = SK_DEBUG; 215 216 void sk_dump_txdesc(struct sk_tx_desc *, int); 217 void sk_dump_mbuf(struct mbuf *); 218 void sk_dump_bytes(const char *, int); 219 #else 220 #define DPRINTF(x) 221 #define DPRINTFN(n, x) 222 #endif 223 224 static int sk_sysctl_handler(SYSCTLFN_PROTO); 225 static int sk_root_num; 226 227 /* supported device vendors */ 228 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 229 static const struct sk_product { 230 pci_vendor_id_t sk_vendor; 231 pci_product_id_t sk_product; 232 } sk_products[] = { 233 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 234 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 235 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 236 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 237 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 238 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 239 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 240 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 241 { 0, 0, } 242 }; 243 244 #define SK_LINKSYS_EG1032_SUBID 0x00151737 245 246 static inline uint32_t 247 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 248 { 249 #ifdef SK_USEIOSPACE 250 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 251 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 252 #else 253 return CSR_READ_4(sc, reg); 254 #endif 255 } 256 257 static inline uint16_t 258 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 259 { 260 #ifdef SK_USEIOSPACE 261 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 262 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 263 #else 264 return CSR_READ_2(sc, reg); 265 #endif 266 } 267 268 static inline uint8_t 269 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 270 { 271 #ifdef SK_USEIOSPACE 272 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 273 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 274 #else 275 return CSR_READ_1(sc, reg); 276 #endif 277 } 278 279 static inline void 280 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 281 { 282 #ifdef SK_USEIOSPACE 283 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 284 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 285 #else 286 CSR_WRITE_4(sc, reg, x); 287 #endif 288 } 289 290 static inline void 291 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 292 { 293 #ifdef SK_USEIOSPACE 294 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 295 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 296 #else 297 CSR_WRITE_2(sc, reg, x); 298 #endif 299 } 300 301 static inline void 302 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 303 { 304 #ifdef SK_USEIOSPACE 305 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 306 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 307 #else 308 CSR_WRITE_1(sc, reg, x); 309 #endif 310 } 311 312 /* 313 * The VPD EEPROM contains Vital Product Data, as suggested in 314 * the PCI 2.1 specification. The VPD data is separared into areas 315 * denoted by resource IDs. The SysKonnect VPD contains an ID string 316 * resource (the name of the adapter), a read-only area resource 317 * containing various key/data fields and a read/write area which 318 * can be used to store asset management information or log messages. 319 * We read the ID string and read-only into buffers attached to 320 * the controller softc structure for later use. At the moment, 321 * we only use the ID string during sk_attach(). 322 */ 323 uint8_t 324 sk_vpd_readbyte(struct sk_softc *sc, int addr) 325 { 326 int i; 327 328 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 329 for (i = 0; i < SK_TIMEOUT; i++) { 330 DELAY(1); 331 if (sk_win_read_2(sc, 332 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 333 break; 334 } 335 336 if (i == SK_TIMEOUT) 337 return 0; 338 339 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 340 } 341 342 void 343 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 344 { 345 int i; 346 uint8_t *ptr; 347 348 ptr = (uint8_t *)res; 349 for (i = 0; i < sizeof(struct vpd_res); i++) 350 ptr[i] = sk_vpd_readbyte(sc, i + addr); 351 } 352 353 void 354 sk_vpd_read(struct sk_softc *sc) 355 { 356 int pos = 0, i; 357 struct vpd_res res; 358 359 if (sc->sk_vpd_prodname != NULL) 360 free(sc->sk_vpd_prodname, M_DEVBUF); 361 if (sc->sk_vpd_readonly != NULL) 362 free(sc->sk_vpd_readonly, M_DEVBUF); 363 sc->sk_vpd_prodname = NULL; 364 sc->sk_vpd_readonly = NULL; 365 366 sk_vpd_read_res(sc, &res, pos); 367 368 if (res.vr_id != VPD_RES_ID) { 369 aprint_error_dev(sc->sk_dev, 370 "bad VPD resource id: expected %x got %x\n", 371 VPD_RES_ID, res.vr_id); 372 return; 373 } 374 375 pos += sizeof(res); 376 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 377 if (sc->sk_vpd_prodname == NULL) 378 panic("sk_vpd_read"); 379 for (i = 0; i < res.vr_len; i++) 380 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 381 sc->sk_vpd_prodname[i] = '\0'; 382 pos += i; 383 384 sk_vpd_read_res(sc, &res, pos); 385 386 if (res.vr_id != VPD_RES_READ) { 387 aprint_error_dev(sc->sk_dev, 388 "bad VPD resource id: expected %x got %x\n", 389 VPD_RES_READ, res.vr_id); 390 return; 391 } 392 393 pos += sizeof(res); 394 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 395 if (sc->sk_vpd_readonly == NULL) 396 panic("sk_vpd_read"); 397 for (i = 0; i < res.vr_len ; i++) 398 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 399 } 400 401 int 402 sk_xmac_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 403 { 404 struct sk_if_softc *sc_if = device_private(dev); 405 int i; 406 407 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 408 409 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 410 return -1; 411 412 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 413 SK_XM_READ_2(sc_if, XM_PHY_DATA); 414 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 415 for (i = 0; i < SK_TIMEOUT; i++) { 416 DELAY(1); 417 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 418 XM_MMUCMD_PHYDATARDY) 419 break; 420 } 421 422 if (i == SK_TIMEOUT) { 423 aprint_error_dev(sc_if->sk_dev, 424 "phy failed to come ready\n"); 425 return ETIMEDOUT; 426 } 427 } 428 DELAY(1); 429 *val = SK_XM_READ_2(sc_if, XM_PHY_DATA); 430 return 0; 431 } 432 433 int 434 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 435 { 436 struct sk_if_softc *sc_if = device_private(dev); 437 int i; 438 439 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 440 441 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 442 for (i = 0; i < SK_TIMEOUT; i++) { 443 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 444 break; 445 } 446 447 if (i == SK_TIMEOUT) { 448 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 449 return ETIMEDOUT; 450 } 451 452 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 453 for (i = 0; i < SK_TIMEOUT; i++) { 454 DELAY(1); 455 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 456 break; 457 } 458 459 if (i == SK_TIMEOUT) { 460 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 461 return ETIMEDOUT; 462 } 463 464 return 0; 465 } 466 467 void 468 sk_xmac_miibus_statchg(struct ifnet *ifp) 469 { 470 struct sk_if_softc *sc_if = ifp->if_softc; 471 struct mii_data *mii = &sc_if->sk_mii; 472 473 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 474 475 /* 476 * If this is a GMII PHY, manually set the XMAC's 477 * duplex mode accordingly. 478 */ 479 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 480 if ((mii->mii_media_active & IFM_FDX) != 0) 481 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 482 else 483 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 484 } 485 } 486 487 int 488 sk_marv_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 489 { 490 struct sk_if_softc *sc_if = device_private(dev); 491 uint16_t data; 492 int i; 493 494 if (phy != 0 || 495 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 496 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 497 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 498 phy, reg)); 499 return -1; 500 } 501 502 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 503 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 504 505 for (i = 0; i < SK_TIMEOUT; i++) { 506 DELAY(1); 507 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 508 if (data & YU_SMICR_READ_VALID) 509 break; 510 } 511 512 if (i == SK_TIMEOUT) { 513 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 514 return ETIMEDOUT; 515 } 516 517 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 518 SK_TIMEOUT)); 519 520 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 521 522 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 523 phy, reg, *val)); 524 525 return 0; 526 } 527 528 int 529 sk_marv_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 530 { 531 struct sk_if_softc *sc_if = device_private(dev); 532 int i; 533 534 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#hx\n", 535 phy, reg, val)); 536 537 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 538 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 539 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 540 541 for (i = 0; i < SK_TIMEOUT; i++) { 542 DELAY(1); 543 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 544 break; 545 } 546 547 if (i == SK_TIMEOUT) { 548 printf("%s: phy write timed out\n", 549 device_xname(sc_if->sk_dev)); 550 return ETIMEDOUT; 551 } 552 553 return 0; 554 } 555 556 void 557 sk_marv_miibus_statchg(struct ifnet *ifp) 558 { 559 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 560 SK_YU_READ_2(((struct sk_if_softc *)ifp->if_softc), 561 YUKON_GPCR))); 562 } 563 564 uint32_t 565 sk_xmac_hash(void *addr) 566 { 567 uint32_t crc; 568 569 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 570 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 571 DPRINTFN(2,("multicast hash for %s is %x\n", ether_sprintf(addr),crc)); 572 return crc; 573 } 574 575 uint32_t 576 sk_yukon_hash(void *addr) 577 { 578 uint32_t crc; 579 580 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 581 crc &= ((1 << SK_HASH_BITS) - 1); 582 DPRINTFN(2,("multicast hash for %s is %x\n", ether_sprintf(addr),crc)); 583 return crc; 584 } 585 586 void 587 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 588 { 589 char *addr = addrv; 590 int base = XM_RXFILT_ENTRY(slot); 591 592 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0])); 593 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2])); 594 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4])); 595 } 596 597 void 598 sk_setmulti(struct sk_if_softc *sc_if) 599 { 600 struct sk_softc *sc = sc_if->sk_softc; 601 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 602 uint32_t hashes[2] = { 0, 0 }; 603 int h = 0, i; 604 struct ethercom *ec = &sc_if->sk_ethercom; 605 struct ether_multi *enm; 606 struct ether_multistep step; 607 uint8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 608 609 /* First, zot all the existing filters. */ 610 switch (sc->sk_type) { 611 case SK_GENESIS: 612 for (i = 1; i < XM_RXFILT_MAX; i++) 613 sk_setfilt(sc_if, (void *)&dummy, i); 614 615 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 616 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 617 break; 618 case SK_YUKON: 619 case SK_YUKON_LITE: 620 case SK_YUKON_LP: 621 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 622 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 623 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 624 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 625 break; 626 } 627 628 /* Now program new ones. */ 629 allmulti: 630 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 631 hashes[0] = 0xFFFFFFFF; 632 hashes[1] = 0xFFFFFFFF; 633 } else { 634 i = 1; 635 /* First find the tail of the list. */ 636 ETHER_LOCK(ec); 637 ETHER_FIRST_MULTI(step, ec, enm); 638 while (enm != NULL) { 639 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 640 ETHER_ADDR_LEN)) { 641 ifp->if_flags |= IFF_ALLMULTI; 642 ETHER_UNLOCK(ec); 643 goto allmulti; 644 } 645 DPRINTFN(2,("multicast address %s\n", 646 ether_sprintf(enm->enm_addrlo))); 647 /* 648 * Program the first XM_RXFILT_MAX multicast groups 649 * into the perfect filter. For all others, 650 * use the hash table. 651 */ 652 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 653 sk_setfilt(sc_if, enm->enm_addrlo, i); 654 i++; 655 } 656 else { 657 switch (sc->sk_type) { 658 case SK_GENESIS: 659 h = sk_xmac_hash(enm->enm_addrlo); 660 break; 661 case SK_YUKON: 662 case SK_YUKON_LITE: 663 case SK_YUKON_LP: 664 h = sk_yukon_hash(enm->enm_addrlo); 665 break; 666 } 667 if (h < 32) 668 hashes[0] |= (1 << h); 669 else 670 hashes[1] |= (1 << (h - 32)); 671 } 672 673 ETHER_NEXT_MULTI(step, enm); 674 } 675 ETHER_UNLOCK(ec); 676 } 677 678 switch (sc->sk_type) { 679 case SK_GENESIS: 680 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH | 681 XM_MODE_RX_USE_PERFECT); 682 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 683 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 684 break; 685 case SK_YUKON: 686 case SK_YUKON_LITE: 687 case SK_YUKON_LP: 688 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 689 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 690 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 691 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 692 break; 693 } 694 } 695 696 int 697 sk_init_rx_ring(struct sk_if_softc *sc_if) 698 { 699 struct sk_chain_data *cd = &sc_if->sk_cdata; 700 struct sk_ring_data *rd = sc_if->sk_rdata; 701 int i; 702 703 memset((char *)rd->sk_rx_ring, 0, 704 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 705 706 for (i = 0; i < SK_RX_RING_CNT; i++) { 707 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 708 if (i == (SK_RX_RING_CNT - 1)) { 709 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 710 rd->sk_rx_ring[i].sk_next = 711 htole32(SK_RX_RING_ADDR(sc_if, 0)); 712 } else { 713 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 714 rd->sk_rx_ring[i].sk_next = 715 htole32(SK_RX_RING_ADDR(sc_if, i+1)); 716 } 717 } 718 719 for (i = 0; i < SK_RX_RING_CNT; i++) { 720 if (sk_newbuf(sc_if, i, NULL, 721 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 722 aprint_error_dev(sc_if->sk_dev, 723 "failed alloc of %dth mbuf\n", i); 724 return ENOBUFS; 725 } 726 } 727 sc_if->sk_cdata.sk_rx_prod = 0; 728 sc_if->sk_cdata.sk_rx_cons = 0; 729 730 return 0; 731 } 732 733 int 734 sk_init_tx_ring(struct sk_if_softc *sc_if) 735 { 736 struct sk_chain_data *cd = &sc_if->sk_cdata; 737 struct sk_ring_data *rd = sc_if->sk_rdata; 738 int i; 739 740 memset(sc_if->sk_rdata->sk_tx_ring, 0, 741 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 742 743 for (i = 0; i < SK_TX_RING_CNT; i++) { 744 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 745 if (i == (SK_TX_RING_CNT - 1)) { 746 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 747 rd->sk_tx_ring[i].sk_next = 748 htole32(SK_TX_RING_ADDR(sc_if, 0)); 749 } else { 750 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 751 rd->sk_tx_ring[i].sk_next = 752 htole32(SK_TX_RING_ADDR(sc_if, i+1)); 753 } 754 } 755 756 sc_if->sk_cdata.sk_tx_prod = 0; 757 sc_if->sk_cdata.sk_tx_cons = 0; 758 sc_if->sk_cdata.sk_tx_cnt = 0; 759 760 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 761 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 762 763 return 0; 764 } 765 766 int 767 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 768 bus_dmamap_t dmamap) 769 { 770 struct mbuf *m_new = NULL; 771 struct sk_chain *c; 772 struct sk_rx_desc *r; 773 774 if (m == NULL) { 775 void *buf = NULL; 776 777 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 778 if (m_new == NULL) { 779 aprint_error_dev(sc_if->sk_dev, 780 "no memory for rx list -- packet dropped!\n"); 781 return ENOBUFS; 782 } 783 784 /* Allocate the jumbo buffer */ 785 buf = sk_jalloc(sc_if); 786 if (buf == NULL) { 787 m_freem(m_new); 788 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 789 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 790 return ENOBUFS; 791 } 792 793 /* Attach the buffer to the mbuf */ 794 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 795 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 796 797 } else { 798 /* 799 * We're re-using a previously allocated mbuf; 800 * be sure to re-init pointers and lengths to 801 * default values. 802 */ 803 m_new = m; 804 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 805 m_new->m_data = m_new->m_ext.ext_buf; 806 } 807 m_adj(m_new, ETHER_ALIGN); 808 809 c = &sc_if->sk_cdata.sk_rx_chain[i]; 810 r = c->sk_desc; 811 c->sk_mbuf = m_new; 812 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 813 (((vaddr_t)m_new->m_data 814 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 815 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 816 817 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 818 819 return 0; 820 } 821 822 /* 823 * Memory management for jumbo frames. 824 */ 825 826 int 827 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 828 { 829 struct sk_softc *sc = sc_if->sk_softc; 830 char *ptr, *kva; 831 bus_dma_segment_t seg; 832 int i, rseg, state, error; 833 struct sk_jpool_entry *entry; 834 835 state = error = 0; 836 837 /* Grab a big chunk o' storage. */ 838 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 839 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 840 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 841 return ENOBUFS; 842 } 843 844 state = 1; 845 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 846 BUS_DMA_NOWAIT)) { 847 aprint_error_dev(sc->sk_dev, 848 "can't map dma buffers (%d bytes)\n", 849 SK_JMEM); 850 error = ENOBUFS; 851 goto out; 852 } 853 854 state = 2; 855 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 856 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 857 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 858 error = ENOBUFS; 859 goto out; 860 } 861 862 state = 3; 863 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 864 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 865 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 866 error = ENOBUFS; 867 goto out; 868 } 869 870 state = 4; 871 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 872 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 873 874 LIST_INIT(&sc_if->sk_jfree_listhead); 875 LIST_INIT(&sc_if->sk_jinuse_listhead); 876 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 877 878 /* 879 * Now divide it up into 9K pieces and save the addresses 880 * in an array. 881 */ 882 ptr = sc_if->sk_cdata.sk_jumbo_buf; 883 for (i = 0; i < SK_JSLOTS; i++) { 884 sc_if->sk_cdata.sk_jslots[i] = ptr; 885 ptr += SK_JLEN; 886 entry = malloc(sizeof(struct sk_jpool_entry), 887 M_DEVBUF, M_NOWAIT); 888 if (entry == NULL) { 889 aprint_error_dev(sc->sk_dev, 890 "no memory for jumbo buffer queue!\n"); 891 error = ENOBUFS; 892 goto out; 893 } 894 entry->slot = i; 895 if (i) 896 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 897 entry, jpool_entries); 898 else 899 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 900 entry, jpool_entries); 901 } 902 out: 903 if (error != 0) { 904 switch (state) { 905 case 4: 906 bus_dmamap_unload(sc->sc_dmatag, 907 sc_if->sk_cdata.sk_rx_jumbo_map); 908 /* FALLTHROUGH */ 909 case 3: 910 bus_dmamap_destroy(sc->sc_dmatag, 911 sc_if->sk_cdata.sk_rx_jumbo_map); 912 /* FALLTHROUGH */ 913 case 2: 914 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 915 /* FALLTHROUGH */ 916 case 1: 917 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 918 break; 919 default: 920 break; 921 } 922 } 923 924 return error; 925 } 926 927 /* 928 * Allocate a jumbo buffer. 929 */ 930 void * 931 sk_jalloc(struct sk_if_softc *sc_if) 932 { 933 struct sk_jpool_entry *entry; 934 935 mutex_enter(&sc_if->sk_jpool_mtx); 936 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 937 938 if (entry == NULL) { 939 mutex_exit(&sc_if->sk_jpool_mtx); 940 return NULL; 941 } 942 943 LIST_REMOVE(entry, jpool_entries); 944 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 945 mutex_exit(&sc_if->sk_jpool_mtx); 946 return sc_if->sk_cdata.sk_jslots[entry->slot]; 947 } 948 949 /* 950 * Release a jumbo buffer. 951 */ 952 void 953 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 954 { 955 struct sk_jpool_entry *entry; 956 struct sk_if_softc *sc; 957 int i; 958 959 /* Extract the softc struct pointer. */ 960 sc = (struct sk_if_softc *)arg; 961 962 if (sc == NULL) 963 panic("sk_jfree: can't find softc pointer!"); 964 965 /* calculate the slot this buffer belongs to */ 966 967 i = ((vaddr_t)buf 968 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 969 970 if ((i < 0) || (i >= SK_JSLOTS)) 971 panic("sk_jfree: asked to free buffer that we don't manage!"); 972 973 mutex_enter(&sc->sk_jpool_mtx); 974 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 975 if (entry == NULL) 976 panic("sk_jfree: buffer not in use!"); 977 entry->slot = i; 978 LIST_REMOVE(entry, jpool_entries); 979 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 980 mutex_exit(&sc->sk_jpool_mtx); 981 982 if (__predict_true(m != NULL)) 983 pool_cache_put(mb_cache, m); 984 } 985 986 /* 987 * Set media options. 988 */ 989 int 990 sk_ifmedia_upd(struct ifnet *ifp) 991 { 992 struct sk_if_softc *sc_if = ifp->if_softc; 993 int rc; 994 995 (void) sk_init(ifp); 996 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 997 return 0; 998 return rc; 999 } 1000 1001 static void 1002 sk_promisc(struct sk_if_softc *sc_if, int on) 1003 { 1004 struct sk_softc *sc = sc_if->sk_softc; 1005 switch (sc->sk_type) { 1006 case SK_GENESIS: 1007 if (on) 1008 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1009 else 1010 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1011 break; 1012 case SK_YUKON: 1013 case SK_YUKON_LITE: 1014 case SK_YUKON_LP: 1015 if (on) 1016 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1017 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1018 else 1019 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1020 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1021 break; 1022 default: 1023 aprint_error_dev(sc_if->sk_dev, "Can't set promisc for %d\n", 1024 sc->sk_type); 1025 break; 1026 } 1027 } 1028 1029 int 1030 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 1031 { 1032 struct sk_if_softc *sc_if = ifp->if_softc; 1033 int s, error = 0; 1034 1035 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1036 1037 s = splnet(); 1038 1039 switch (command) { 1040 1041 case SIOCSIFFLAGS: 1042 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1043 if ((error = ifioctl_common(ifp, command, data)) != 0) 1044 break; 1045 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1046 case IFF_RUNNING: 1047 sk_stop(ifp, 1); 1048 break; 1049 case IFF_UP: 1050 sk_init(ifp); 1051 break; 1052 case IFF_UP | IFF_RUNNING: 1053 if ((ifp->if_flags ^ sc_if->sk_if_flags) == IFF_PROMISC) { 1054 sk_promisc(sc_if, ifp->if_flags & IFF_PROMISC); 1055 sk_setmulti(sc_if); 1056 } else 1057 sk_init(ifp); 1058 break; 1059 } 1060 sc_if->sk_if_flags = ifp->if_flags; 1061 error = 0; 1062 break; 1063 1064 default: 1065 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1066 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1067 break; 1068 1069 error = 0; 1070 1071 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1072 ; 1073 else if (ifp->if_flags & IFF_RUNNING) { 1074 sk_setmulti(sc_if); 1075 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1076 } 1077 break; 1078 } 1079 1080 splx(s); 1081 return error; 1082 } 1083 1084 void 1085 sk_update_int_mod(struct sk_softc *sc) 1086 { 1087 uint32_t imtimer_ticks; 1088 1089 /* 1090 * Configure interrupt moderation. The moderation timer 1091 * defers interrupts specified in the interrupt moderation 1092 * timer mask based on the timeout specified in the interrupt 1093 * moderation timer init register. Each bit in the timer 1094 * register represents one tick, so to specify a timeout in 1095 * microseconds, we have to multiply by the correct number of 1096 * ticks-per-microsecond. 1097 */ 1098 switch (sc->sk_type) { 1099 case SK_GENESIS: 1100 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1101 break; 1102 case SK_YUKON_EC: 1103 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1104 break; 1105 default: 1106 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1107 } 1108 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1109 sc->sk_int_mod); 1110 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1111 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF | 1112 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF); 1113 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1114 sc->sk_int_mod_pending = 0; 1115 } 1116 1117 /* 1118 * Lookup: Check the PCI vendor and device, and return a pointer to 1119 * The structure if the IDs match against our list. 1120 */ 1121 1122 static const struct sk_product * 1123 sk_lookup(const struct pci_attach_args *pa) 1124 { 1125 const struct sk_product *psk; 1126 1127 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1128 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1129 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1130 return psk; 1131 } 1132 return NULL; 1133 } 1134 1135 /* 1136 * Probe for a SysKonnect GEnesis chip. 1137 */ 1138 1139 int 1140 skc_probe(device_t parent, cfdata_t match, void *aux) 1141 { 1142 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1143 const struct sk_product *psk; 1144 pcireg_t subid; 1145 1146 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1147 1148 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1149 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1150 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1151 subid == SK_LINKSYS_EG1032_SUBID) 1152 return 1; 1153 1154 if ((psk = sk_lookup(pa))) { 1155 return 1; 1156 } 1157 return 0; 1158 } 1159 1160 /* 1161 * Force the GEnesis into reset, then bring it out of reset. 1162 */ 1163 void sk_reset(struct sk_softc *sc) 1164 { 1165 DPRINTFN(2, ("sk_reset\n")); 1166 1167 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1168 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1169 if (SK_YUKON_FAMILY(sc->sk_type)) 1170 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1171 1172 DELAY(1000); 1173 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1174 DELAY(2); 1175 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1176 if (SK_YUKON_FAMILY(sc->sk_type)) 1177 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1178 1179 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1180 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1181 CSR_READ_2(sc, SK_LINK_CTRL))); 1182 1183 if (sc->sk_type == SK_GENESIS) { 1184 /* Configure packet arbiter */ 1185 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1186 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1187 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1188 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1189 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1190 } 1191 1192 /* Enable RAM interface */ 1193 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1194 1195 sk_update_int_mod(sc); 1196 } 1197 1198 int 1199 sk_probe(device_t parent, cfdata_t match, void *aux) 1200 { 1201 struct skc_attach_args *sa = aux; 1202 1203 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1204 return 0; 1205 1206 return 1; 1207 } 1208 1209 /* 1210 * Each XMAC chip is attached as a separate logical IP interface. 1211 * Single port cards will have only one logical interface of course. 1212 */ 1213 void 1214 sk_attach(device_t parent, device_t self, void *aux) 1215 { 1216 struct sk_if_softc *sc_if = device_private(self); 1217 struct mii_data *mii = &sc_if->sk_mii; 1218 struct sk_softc *sc = device_private(parent); 1219 struct skc_attach_args *sa = aux; 1220 struct sk_txmap_entry *entry; 1221 struct ifnet *ifp; 1222 bus_dma_segment_t seg; 1223 bus_dmamap_t dmamap; 1224 prop_data_t data; 1225 void *kva; 1226 int i, rseg; 1227 int mii_flags = 0; 1228 1229 aprint_naive("\n"); 1230 1231 sc_if->sk_dev = self; 1232 sc_if->sk_port = sa->skc_port; 1233 sc_if->sk_softc = sc; 1234 sc->sk_if[sa->skc_port] = sc_if; 1235 1236 if (sa->skc_port == SK_PORT_A) 1237 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1238 if (sa->skc_port == SK_PORT_B) 1239 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1240 1241 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1242 1243 /* 1244 * Get station address for this interface. Note that 1245 * dual port cards actually come with three station 1246 * addresses: one for each port, plus an extra. The 1247 * extra one is used by the SysKonnect driver software 1248 * as a 'virtual' station address for when both ports 1249 * are operating in failover mode. Currently we don't 1250 * use this extra address. 1251 */ 1252 data = prop_dictionary_get(device_properties(self), "mac-address"); 1253 if (data != NULL) { 1254 /* 1255 * Try to get the station address from device properties 1256 * first, in case the ROM is missing. 1257 */ 1258 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 1259 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 1260 memcpy(sc_if->sk_enaddr, prop_data_data_nocopy(data), 1261 ETHER_ADDR_LEN); 1262 } else 1263 for (i = 0; i < ETHER_ADDR_LEN; i++) 1264 sc_if->sk_enaddr[i] = sk_win_read_1(sc, 1265 SK_MAC0_0 + (sa->skc_port * 8) + i); 1266 1267 aprint_normal(": Ethernet address %s\n", 1268 ether_sprintf(sc_if->sk_enaddr)); 1269 1270 /* 1271 * Set up RAM buffer addresses. The NIC will have a certain 1272 * amount of SRAM on it, somewhere between 512K and 2MB. We 1273 * need to divide this up a) between the transmitter and 1274 * receiver and b) between the two XMACs, if this is a 1275 * dual port NIC. Our algorithm is to divide up the memory 1276 * evenly so that everyone gets a fair share. 1277 */ 1278 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1279 uint32_t chunk, val; 1280 1281 chunk = sc->sk_ramsize / 2; 1282 val = sc->sk_rboff / sizeof(uint64_t); 1283 sc_if->sk_rx_ramstart = val; 1284 val += (chunk / sizeof(uint64_t)); 1285 sc_if->sk_rx_ramend = val - 1; 1286 sc_if->sk_tx_ramstart = val; 1287 val += (chunk / sizeof(uint64_t)); 1288 sc_if->sk_tx_ramend = val - 1; 1289 } else { 1290 uint32_t chunk, val; 1291 1292 chunk = sc->sk_ramsize / 4; 1293 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1294 sizeof(uint64_t); 1295 sc_if->sk_rx_ramstart = val; 1296 val += (chunk / sizeof(uint64_t)); 1297 sc_if->sk_rx_ramend = val - 1; 1298 sc_if->sk_tx_ramstart = val; 1299 val += (chunk / sizeof(uint64_t)); 1300 sc_if->sk_tx_ramend = val - 1; 1301 } 1302 1303 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1304 " tx_ramstart=%#x tx_ramend=%#x\n", 1305 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1306 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1307 1308 /* Read and save PHY type and set PHY address */ 1309 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1310 switch (sc_if->sk_phytype) { 1311 case SK_PHYTYPE_XMAC: 1312 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1313 break; 1314 case SK_PHYTYPE_BCOM: 1315 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1316 break; 1317 case SK_PHYTYPE_MARV_COPPER: 1318 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1319 break; 1320 default: 1321 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1322 sc_if->sk_phytype); 1323 return; 1324 } 1325 1326 /* Allocate the descriptor queues. */ 1327 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1328 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1329 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1330 goto fail; 1331 } 1332 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1333 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1334 aprint_error_dev(sc_if->sk_dev, 1335 "can't map dma buffers (%lu bytes)\n", 1336 (u_long) sizeof(struct sk_ring_data)); 1337 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1338 goto fail; 1339 } 1340 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1341 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1342 &sc_if->sk_ring_map)) { 1343 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1344 bus_dmamem_unmap(sc->sc_dmatag, kva, 1345 sizeof(struct sk_ring_data)); 1346 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1347 goto fail; 1348 } 1349 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1350 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1351 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1352 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1353 bus_dmamem_unmap(sc->sc_dmatag, kva, 1354 sizeof(struct sk_ring_data)); 1355 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1356 goto fail; 1357 } 1358 1359 for (i = 0; i < SK_RX_RING_CNT; i++) 1360 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1361 1362 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1363 for (i = 0; i < SK_TX_RING_CNT; i++) { 1364 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1365 1366 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1367 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1368 aprint_error_dev(sc_if->sk_dev, 1369 "Can't create TX dmamap\n"); 1370 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1371 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1372 bus_dmamem_unmap(sc->sc_dmatag, kva, 1373 sizeof(struct sk_ring_data)); 1374 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1375 goto fail; 1376 } 1377 1378 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1379 if (!entry) { 1380 aprint_error_dev(sc_if->sk_dev, 1381 "Can't alloc txmap entry\n"); 1382 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1383 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1384 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1385 bus_dmamem_unmap(sc->sc_dmatag, kva, 1386 sizeof(struct sk_ring_data)); 1387 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1388 goto fail; 1389 } 1390 entry->dmamap = dmamap; 1391 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1392 } 1393 1394 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1395 memset(sc_if->sk_rdata, 0, sizeof(struct sk_ring_data)); 1396 1397 ifp = &sc_if->sk_ethercom.ec_if; 1398 /* Try to allocate memory for jumbo buffers. */ 1399 if (sk_alloc_jumbo_mem(sc_if)) { 1400 aprint_error("%s: jumbo buffer allocation failed\n", ifp->if_xname); 1401 goto fail; 1402 } 1403 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1404 | ETHERCAP_JUMBO_MTU; 1405 1406 ifp->if_softc = sc_if; 1407 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1408 ifp->if_ioctl = sk_ioctl; 1409 ifp->if_start = sk_start; 1410 ifp->if_stop = sk_stop; 1411 ifp->if_init = sk_init; 1412 ifp->if_watchdog = sk_watchdog; 1413 ifp->if_capabilities = 0; 1414 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1415 IFQ_SET_READY(&ifp->if_snd); 1416 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1417 1418 /* 1419 * Do miibus setup. 1420 */ 1421 switch (sc->sk_type) { 1422 case SK_GENESIS: 1423 sk_init_xmac(sc_if); 1424 break; 1425 case SK_YUKON: 1426 case SK_YUKON_LITE: 1427 case SK_YUKON_LP: 1428 sk_init_yukon(sc_if); 1429 break; 1430 default: 1431 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1432 sc->sk_type); 1433 goto fail; 1434 } 1435 1436 DPRINTFN(2, ("sk_attach: 1\n")); 1437 1438 mii->mii_ifp = ifp; 1439 switch (sc->sk_type) { 1440 case SK_GENESIS: 1441 mii->mii_readreg = sk_xmac_miibus_readreg; 1442 mii->mii_writereg = sk_xmac_miibus_writereg; 1443 mii->mii_statchg = sk_xmac_miibus_statchg; 1444 break; 1445 case SK_YUKON: 1446 case SK_YUKON_LITE: 1447 case SK_YUKON_LP: 1448 mii->mii_readreg = sk_marv_miibus_readreg; 1449 mii->mii_writereg = sk_marv_miibus_writereg; 1450 mii->mii_statchg = sk_marv_miibus_statchg; 1451 mii_flags = MIIF_DOPAUSE; 1452 break; 1453 } 1454 1455 sc_if->sk_ethercom.ec_mii = mii; 1456 ifmedia_init(&mii->mii_media, 0, sk_ifmedia_upd, ether_mediastatus); 1457 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 1458 MII_OFFSET_ANY, mii_flags); 1459 if (LIST_EMPTY(&mii->mii_phys)) { 1460 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1461 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 1462 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1463 } else 1464 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1465 1466 callout_init(&sc_if->sk_tick_ch, 0); 1467 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1468 1469 DPRINTFN(2, ("sk_attach: 1\n")); 1470 1471 /* 1472 * Call MI attach routines. 1473 */ 1474 if_attach(ifp); 1475 if_deferred_start_init(ifp, NULL); 1476 1477 ether_ifattach(ifp, sc_if->sk_enaddr); 1478 1479 if (sc->rnd_attached++ == 0) { 1480 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1481 RND_TYPE_NET, RND_FLAG_DEFAULT); 1482 } 1483 1484 if (pmf_device_register(self, NULL, sk_resume)) 1485 pmf_class_network_register(self, ifp); 1486 else 1487 aprint_error_dev(self, "couldn't establish power handler\n"); 1488 1489 DPRINTFN(2, ("sk_attach: end\n")); 1490 1491 return; 1492 1493 fail: 1494 sc->sk_if[sa->skc_port] = NULL; 1495 } 1496 1497 int 1498 skcprint(void *aux, const char *pnp) 1499 { 1500 struct skc_attach_args *sa = aux; 1501 1502 if (pnp) 1503 aprint_normal("sk port %c at %s", 1504 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1505 else 1506 aprint_normal(" port %c", 1507 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1508 return UNCONF; 1509 } 1510 1511 /* 1512 * Attach the interface. Allocate softc structures, do ifmedia 1513 * setup and ethernet/BPF attach. 1514 */ 1515 void 1516 skc_attach(device_t parent, device_t self, void *aux) 1517 { 1518 struct sk_softc *sc = device_private(self); 1519 struct pci_attach_args *pa = aux; 1520 struct skc_attach_args skca; 1521 pci_chipset_tag_t pc = pa->pa_pc; 1522 #ifndef SK_USEIOSPACE 1523 pcireg_t memtype; 1524 #endif 1525 pci_intr_handle_t ih; 1526 const char *intrstr = NULL; 1527 bus_addr_t iobase; 1528 bus_size_t iosize; 1529 int rc, sk_nodenum; 1530 uint32_t command; 1531 const char *revstr; 1532 const struct sysctlnode *node; 1533 char intrbuf[PCI_INTRSTR_LEN]; 1534 1535 sc->sk_dev = self; 1536 aprint_naive("\n"); 1537 1538 DPRINTFN(2, ("begin skc_attach\n")); 1539 1540 /* 1541 * Handle power management nonsense. 1542 */ 1543 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1544 1545 if (command == 0x01) { 1546 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1547 if (command & SK_PSTATE_MASK) { 1548 uint32_t xiobase, membase, irq; 1549 1550 /* Save important PCI config data. */ 1551 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1552 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1553 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1554 1555 /* Reset the power state. */ 1556 aprint_normal_dev(sc->sk_dev, 1557 "chip is in D%d power mode -- setting to D0\n", 1558 command & SK_PSTATE_MASK); 1559 command &= 0xFFFFFFFC; 1560 pci_conf_write(pc, pa->pa_tag, 1561 SK_PCI_PWRMGMTCTRL, command); 1562 1563 /* Restore PCI config data. */ 1564 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1565 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1566 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1567 } 1568 } 1569 1570 /* 1571 * The firmware might have configured the interface to revert the 1572 * byte order in all descriptors. Make that undone. 1573 */ 1574 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_OURREG2); 1575 if (command & SK_REG2_REV_DESC) 1576 pci_conf_write(pc, pa->pa_tag, SK_PCI_OURREG2, 1577 command & ~SK_REG2_REV_DESC); 1578 1579 /* 1580 * Map control/status registers. 1581 */ 1582 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1583 command |= PCI_COMMAND_IO_ENABLE | 1584 PCI_COMMAND_MEM_ENABLE | 1585 PCI_COMMAND_MASTER_ENABLE; 1586 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1587 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1588 1589 #ifdef SK_USEIOSPACE 1590 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1591 aprint_error(": failed to enable I/O ports!\n"); 1592 return; 1593 } 1594 /* 1595 * Map control/status registers. 1596 */ 1597 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1598 &sc->sk_btag, &sc->sk_bhandle, 1599 &iobase, &iosize)) { 1600 aprint_error(": can't find i/o space\n"); 1601 return; 1602 } 1603 #else 1604 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1605 aprint_error(": failed to enable memory mapping!\n"); 1606 return; 1607 } 1608 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1609 switch (memtype) { 1610 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1611 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1612 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1613 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1614 &iobase, &iosize) == 0) 1615 break; 1616 /* FALLTHROUGH */ 1617 default: 1618 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1619 return; 1620 } 1621 1622 DPRINTFN(2, ("skc_attach: iobase=%#" PRIxPADDR ", iosize=%zx\n", 1623 iobase, iosize)); 1624 #endif 1625 sc->sc_dmatag = pa->pa_dmat; 1626 1627 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1628 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1629 1630 /* bail out here if chip is not recognized */ 1631 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1632 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1633 goto fail; 1634 } 1635 if (SK_IS_YUKON2(sc)) { 1636 aprint_error_dev(sc->sk_dev, 1637 "Does not support Yukon2--try msk(4).\n"); 1638 goto fail; 1639 } 1640 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1641 1642 /* Allocate interrupt */ 1643 if (pci_intr_map(pa, &ih)) { 1644 aprint_error(": couldn't map interrupt\n"); 1645 goto fail; 1646 } 1647 1648 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1649 sc->sk_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, sk_intr, sc, 1650 device_xname(sc->sk_dev)); 1651 if (sc->sk_intrhand == NULL) { 1652 aprint_error(": couldn't establish interrupt"); 1653 if (intrstr != NULL) 1654 aprint_error(" at %s", intrstr); 1655 aprint_error("\n"); 1656 goto fail; 1657 } 1658 aprint_normal(": %s\n", intrstr); 1659 1660 /* Reset the adapter. */ 1661 sk_reset(sc); 1662 1663 /* Read and save vital product data from EEPROM. */ 1664 sk_vpd_read(sc); 1665 1666 if (sc->sk_type == SK_GENESIS) { 1667 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1668 /* Read and save RAM size and RAMbuffer offset */ 1669 switch (val) { 1670 case SK_RAMSIZE_512K_64: 1671 sc->sk_ramsize = 0x80000; 1672 sc->sk_rboff = SK_RBOFF_0; 1673 break; 1674 case SK_RAMSIZE_1024K_64: 1675 sc->sk_ramsize = 0x100000; 1676 sc->sk_rboff = SK_RBOFF_80000; 1677 break; 1678 case SK_RAMSIZE_1024K_128: 1679 sc->sk_ramsize = 0x100000; 1680 sc->sk_rboff = SK_RBOFF_0; 1681 break; 1682 case SK_RAMSIZE_2048K_128: 1683 sc->sk_ramsize = 0x200000; 1684 sc->sk_rboff = SK_RBOFF_0; 1685 break; 1686 default: 1687 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1688 val); 1689 goto fail_1; 1690 break; 1691 } 1692 1693 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1694 sc->sk_ramsize, sc->sk_ramsize / 1024, 1695 sc->sk_rboff)); 1696 } else { 1697 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1698 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1699 sc->sk_rboff = SK_RBOFF_0; 1700 1701 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1702 sc->sk_ramsize / 1024, sc->sk_ramsize, 1703 sc->sk_rboff)); 1704 } 1705 1706 /* Read and save physical media type */ 1707 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1708 case SK_PMD_1000BASESX: 1709 sc->sk_pmd = IFM_1000_SX; 1710 break; 1711 case SK_PMD_1000BASELX: 1712 sc->sk_pmd = IFM_1000_LX; 1713 break; 1714 case SK_PMD_1000BASECX: 1715 sc->sk_pmd = IFM_1000_CX; 1716 break; 1717 case SK_PMD_1000BASETX: 1718 case SK_PMD_1000BASETX_ALT: 1719 sc->sk_pmd = IFM_1000_T; 1720 break; 1721 default: 1722 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1723 sk_win_read_1(sc, SK_PMDTYPE)); 1724 goto fail_1; 1725 } 1726 1727 /* determine whether to name it with vpd or just make it up */ 1728 /* Marvell Yukon VPD's can freqently be bogus */ 1729 1730 switch (pa->pa_id) { 1731 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1732 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1733 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1734 case PCI_PRODUCT_3COM_3C940: 1735 case PCI_PRODUCT_DLINK_DGE530T: 1736 case PCI_PRODUCT_DLINK_DGE560T: 1737 case PCI_PRODUCT_DLINK_DGE560T_2: 1738 case PCI_PRODUCT_LINKSYS_EG1032: 1739 case PCI_PRODUCT_LINKSYS_EG1064: 1740 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1741 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1742 case PCI_ID_CODE(PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940): 1743 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T): 1744 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T): 1745 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2): 1746 case PCI_ID_CODE(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032): 1747 case PCI_ID_CODE(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064): 1748 sc->sk_name = sc->sk_vpd_prodname; 1749 break; 1750 case PCI_ID_CODE(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET): 1751 /* whoops yukon vpd prodname bears no resemblance to reality */ 1752 switch (sc->sk_type) { 1753 case SK_GENESIS: 1754 sc->sk_name = sc->sk_vpd_prodname; 1755 break; 1756 case SK_YUKON: 1757 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1758 break; 1759 case SK_YUKON_LITE: 1760 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1761 break; 1762 case SK_YUKON_LP: 1763 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1764 break; 1765 default: 1766 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1767 } 1768 1769 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1770 1771 if ( sc->sk_type == SK_YUKON ) { 1772 uint32_t flashaddr; 1773 uint8_t testbyte; 1774 1775 flashaddr = sk_win_read_4(sc, SK_EP_ADDR); 1776 1777 /* test Flash-Address Register */ 1778 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff); 1779 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1780 1781 if (testbyte != 0) { 1782 /* this is yukon lite Rev. A0 */ 1783 sc->sk_type = SK_YUKON_LITE; 1784 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1785 /* restore Flash-Address Register */ 1786 sk_win_write_4(sc, SK_EP_ADDR, flashaddr); 1787 } 1788 } 1789 break; 1790 case PCI_ID_CODE(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN): 1791 sc->sk_name = sc->sk_vpd_prodname; 1792 break; 1793 default: 1794 sc->sk_name = "Unknown Marvell"; 1795 } 1796 1797 1798 if ( sc->sk_type == SK_YUKON_LITE ) { 1799 switch (sc->sk_rev) { 1800 case SK_YUKON_LITE_REV_A0: 1801 revstr = "A0"; 1802 break; 1803 case SK_YUKON_LITE_REV_A1: 1804 revstr = "A1"; 1805 break; 1806 case SK_YUKON_LITE_REV_A3: 1807 revstr = "A3"; 1808 break; 1809 default: 1810 revstr = ""; 1811 } 1812 } else { 1813 revstr = ""; 1814 } 1815 1816 /* Announce the product name. */ 1817 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1818 sc->sk_name, revstr, sc->sk_rev); 1819 1820 skca.skc_port = SK_PORT_A; 1821 (void)config_found(sc->sk_dev, &skca, skcprint); 1822 1823 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1824 skca.skc_port = SK_PORT_B; 1825 (void)config_found(sc->sk_dev, &skca, skcprint); 1826 } 1827 1828 /* Turn on the 'driver is loaded' LED. */ 1829 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1830 1831 /* skc sysctl setup */ 1832 1833 sc->sk_int_mod = SK_IM_DEFAULT; 1834 sc->sk_int_mod_pending = 0; 1835 1836 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1837 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1838 SYSCTL_DESCR("skc per-controller controls"), 1839 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1840 CTL_EOL)) != 0) { 1841 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1842 goto fail_1; 1843 } 1844 1845 sk_nodenum = node->sysctl_num; 1846 1847 /* interrupt moderation time in usecs */ 1848 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1849 CTLFLAG_READWRITE, 1850 CTLTYPE_INT, "int_mod", 1851 SYSCTL_DESCR("sk interrupt moderation timer"), 1852 sk_sysctl_handler, 0, (void *)sc, 1853 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1854 CTL_EOL)) != 0) { 1855 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n"); 1856 goto fail_1; 1857 } 1858 1859 if (!pmf_device_register(self, skc_suspend, skc_resume)) 1860 aprint_error_dev(self, "couldn't establish power handler\n"); 1861 1862 return; 1863 1864 fail_1: 1865 pci_intr_disestablish(pc, sc->sk_intrhand); 1866 fail: 1867 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1868 } 1869 1870 int 1871 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1872 { 1873 struct sk_softc *sc = sc_if->sk_softc; 1874 struct sk_tx_desc *f = NULL; 1875 uint32_t frag, cur, cnt = 0, sk_ctl; 1876 int i; 1877 struct sk_txmap_entry *entry; 1878 bus_dmamap_t txmap; 1879 1880 DPRINTFN(3, ("sk_encap\n")); 1881 1882 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1883 if (entry == NULL) { 1884 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1885 return ENOBUFS; 1886 } 1887 txmap = entry->dmamap; 1888 1889 cur = frag = *txidx; 1890 1891 #ifdef SK_DEBUG 1892 if (skdebug >= 3) 1893 sk_dump_mbuf(m_head); 1894 #endif 1895 1896 /* 1897 * Start packing the mbufs in this chain into 1898 * the fragment pointers. Stop when we run out 1899 * of fragments or hit the end of the mbuf chain. 1900 */ 1901 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1902 BUS_DMA_NOWAIT)) { 1903 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1904 return ENOBUFS; 1905 } 1906 1907 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1908 1909 /* Sync the DMA map. */ 1910 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1911 BUS_DMASYNC_PREWRITE); 1912 1913 for (i = 0; i < txmap->dm_nsegs; i++) { 1914 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1915 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1916 return ENOBUFS; 1917 } 1918 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1919 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1920 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1921 if (cnt == 0) 1922 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1923 else 1924 sk_ctl |= SK_TXCTL_OWN; 1925 f->sk_ctl = htole32(sk_ctl); 1926 cur = frag; 1927 SK_INC(frag, SK_TX_RING_CNT); 1928 cnt++; 1929 } 1930 1931 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1932 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1933 1934 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1935 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1936 htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 1937 1938 /* Sync descriptors before handing to chip */ 1939 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1940 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1941 1942 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1943 htole32(SK_TXCTL_OWN); 1944 1945 /* Sync first descriptor to hand it off */ 1946 SK_CDTXSYNC(sc_if, *txidx, 1, 1947 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1948 1949 sc_if->sk_cdata.sk_tx_cnt += cnt; 1950 1951 #ifdef SK_DEBUG 1952 if (skdebug >= 3) { 1953 struct sk_tx_desc *desc; 1954 uint32_t idx; 1955 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1956 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1957 sk_dump_txdesc(desc, idx); 1958 } 1959 } 1960 #endif 1961 1962 *txidx = frag; 1963 1964 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1965 1966 return 0; 1967 } 1968 1969 void 1970 sk_start(struct ifnet *ifp) 1971 { 1972 struct sk_if_softc *sc_if = ifp->if_softc; 1973 struct sk_softc *sc = sc_if->sk_softc; 1974 struct mbuf *m_head = NULL; 1975 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1976 int pkts = 0; 1977 1978 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1979 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1980 1981 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1982 IFQ_POLL(&ifp->if_snd, m_head); 1983 if (m_head == NULL) 1984 break; 1985 1986 /* 1987 * Pack the data into the transmit ring. If we 1988 * don't have room, set the OACTIVE flag and wait 1989 * for the NIC to drain the ring. 1990 */ 1991 if (sk_encap(sc_if, m_head, &idx)) { 1992 ifp->if_flags |= IFF_OACTIVE; 1993 break; 1994 } 1995 1996 /* now we are committed to transmit the packet */ 1997 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1998 pkts++; 1999 2000 /* 2001 * If there's a BPF listener, bounce a copy of this frame 2002 * to him. 2003 */ 2004 bpf_mtap(ifp, m_head, BPF_D_OUT); 2005 } 2006 if (pkts == 0) 2007 return; 2008 2009 /* Transmit */ 2010 if (idx != sc_if->sk_cdata.sk_tx_prod) { 2011 sc_if->sk_cdata.sk_tx_prod = idx; 2012 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2013 2014 /* Set a timeout in case the chip goes out to lunch. */ 2015 ifp->if_timer = 5; 2016 } 2017 } 2018 2019 2020 void 2021 sk_watchdog(struct ifnet *ifp) 2022 { 2023 struct sk_if_softc *sc_if = ifp->if_softc; 2024 2025 /* 2026 * Reclaim first as there is a possibility of losing Tx completion 2027 * interrupts. 2028 */ 2029 sk_txeof(sc_if); 2030 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2031 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 2032 2033 ifp->if_oerrors++; 2034 2035 sk_init(ifp); 2036 } 2037 } 2038 2039 void 2040 sk_shutdown(void *v) 2041 { 2042 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2043 struct sk_softc *sc = sc_if->sk_softc; 2044 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2045 2046 DPRINTFN(2, ("sk_shutdown\n")); 2047 sk_stop(ifp, 1); 2048 2049 /* Turn off the 'driver is loaded' LED. */ 2050 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2051 2052 /* 2053 * Reset the GEnesis controller. Doing this should also 2054 * assert the resets on the attached XMAC(s). 2055 */ 2056 sk_reset(sc); 2057 } 2058 2059 void 2060 sk_rxeof(struct sk_if_softc *sc_if) 2061 { 2062 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2063 struct mbuf *m; 2064 struct sk_chain *cur_rx; 2065 struct sk_rx_desc *cur_desc; 2066 int i, cur, total_len = 0; 2067 uint32_t rxstat, sk_ctl; 2068 bus_dmamap_t dmamap; 2069 2070 i = sc_if->sk_cdata.sk_rx_prod; 2071 2072 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2073 2074 for (;;) { 2075 cur = i; 2076 2077 /* Sync the descriptor */ 2078 SK_CDRXSYNC(sc_if, cur, 2079 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2080 2081 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2082 if (sk_ctl & SK_RXCTL_OWN) { 2083 /* Invalidate the descriptor -- it's not ready yet */ 2084 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2085 sc_if->sk_cdata.sk_rx_prod = i; 2086 break; 2087 } 2088 2089 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2090 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2091 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2092 2093 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2094 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2095 2096 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2097 m = cur_rx->sk_mbuf; 2098 cur_rx->sk_mbuf = NULL; 2099 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2100 2101 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2102 2103 SK_INC(i, SK_RX_RING_CNT); 2104 2105 if (rxstat & XM_RXSTAT_ERRFRAME) { 2106 ifp->if_ierrors++; 2107 sk_newbuf(sc_if, cur, m, dmamap); 2108 continue; 2109 } 2110 2111 /* 2112 * Try to allocate a new jumbo buffer. If that 2113 * fails, copy the packet to mbufs and put the 2114 * jumbo buffer back in the ring so it can be 2115 * re-used. If allocating mbufs fails, then we 2116 * have to drop the packet. 2117 */ 2118 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2119 struct mbuf *m0; 2120 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2121 total_len + ETHER_ALIGN, 0, ifp); 2122 sk_newbuf(sc_if, cur, m, dmamap); 2123 if (m0 == NULL) { 2124 aprint_error_dev(sc_if->sk_dev, "no receive " 2125 "buffers available -- packet dropped!\n"); 2126 ifp->if_ierrors++; 2127 continue; 2128 } 2129 m_adj(m0, ETHER_ALIGN); 2130 m = m0; 2131 } else { 2132 m_set_rcvif(m, ifp); 2133 m->m_pkthdr.len = m->m_len = total_len; 2134 } 2135 2136 /* pass it on. */ 2137 if_percpuq_enqueue(ifp->if_percpuq, m); 2138 } 2139 } 2140 2141 void 2142 sk_txeof(struct sk_if_softc *sc_if) 2143 { 2144 struct sk_softc *sc = sc_if->sk_softc; 2145 struct sk_tx_desc *cur_tx; 2146 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2147 uint32_t idx, sk_ctl; 2148 struct sk_txmap_entry *entry; 2149 2150 DPRINTFN(3, ("sk_txeof\n")); 2151 2152 /* 2153 * Go through our tx ring and free mbufs for those 2154 * frames that have been sent. 2155 */ 2156 idx = sc_if->sk_cdata.sk_tx_cons; 2157 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2158 SK_CDTXSYNC(sc_if, idx, 1, 2159 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2160 2161 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2162 sk_ctl = le32toh(cur_tx->sk_ctl); 2163 #ifdef SK_DEBUG 2164 if (skdebug >= 3) 2165 sk_dump_txdesc(cur_tx, idx); 2166 #endif 2167 if (sk_ctl & SK_TXCTL_OWN) { 2168 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2169 break; 2170 } 2171 if (sk_ctl & SK_TXCTL_LASTFRAG) 2172 ifp->if_opackets++; 2173 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2174 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2175 2176 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2177 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2178 2179 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2180 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2181 2182 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2183 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2184 link); 2185 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2186 } 2187 sc_if->sk_cdata.sk_tx_cnt--; 2188 SK_INC(idx, SK_TX_RING_CNT); 2189 } 2190 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2191 ifp->if_timer = 0; 2192 else /* nudge chip to keep tx ring moving */ 2193 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2194 2195 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2196 ifp->if_flags &= ~IFF_OACTIVE; 2197 2198 sc_if->sk_cdata.sk_tx_cons = idx; 2199 } 2200 2201 void 2202 sk_tick(void *xsc_if) 2203 { 2204 struct sk_if_softc *sc_if = xsc_if; 2205 struct mii_data *mii = &sc_if->sk_mii; 2206 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2207 int i; 2208 2209 DPRINTFN(3, ("sk_tick\n")); 2210 2211 if (!(ifp->if_flags & IFF_UP)) 2212 return; 2213 2214 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2215 sk_intr_bcom(sc_if); 2216 return; 2217 } 2218 2219 /* 2220 * According to SysKonnect, the correct way to verify that 2221 * the link has come back up is to poll bit 0 of the GPIO 2222 * register three times. This pin has the signal from the 2223 * link sync pin connected to it; if we read the same link 2224 * state 3 times in a row, we know the link is up. 2225 */ 2226 for (i = 0; i < 3; i++) { 2227 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2228 break; 2229 } 2230 2231 if (i != 3) { 2232 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2233 return; 2234 } 2235 2236 /* Turn the GP0 interrupt back on. */ 2237 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2238 SK_XM_READ_2(sc_if, XM_ISR); 2239 mii_tick(mii); 2240 if (ifp->if_link_state != LINK_STATE_UP) 2241 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2242 else 2243 callout_stop(&sc_if->sk_tick_ch); 2244 } 2245 2246 void 2247 sk_intr_bcom(struct sk_if_softc *sc_if) 2248 { 2249 struct mii_data *mii = &sc_if->sk_mii; 2250 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2251 uint16_t status; 2252 2253 2254 DPRINTFN(3, ("sk_intr_bcom\n")); 2255 2256 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2257 2258 /* 2259 * Read the PHY interrupt register to make sure 2260 * we clear any pending interrupts. 2261 */ 2262 sk_xmac_miibus_readreg(sc_if->sk_dev, 2263 SK_PHYADDR_BCOM, BRGPHY_MII_ISR, &status); 2264 2265 if (!(ifp->if_flags & IFF_RUNNING)) { 2266 sk_init_xmac(sc_if); 2267 return; 2268 } 2269 2270 if (status & (BRGPHY_ISR_LNK_CHG | BRGPHY_ISR_AN_PR)) { 2271 uint16_t lstat; 2272 sk_xmac_miibus_readreg(sc_if->sk_dev, 2273 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS, &lstat); 2274 2275 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2276 (void)mii_mediachg(mii); 2277 /* Turn off the link LED. */ 2278 SK_IF_WRITE_1(sc_if, 0, 2279 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2280 sc_if->sk_link = 0; 2281 } else if (status & BRGPHY_ISR_LNK_CHG) { 2282 sk_xmac_miibus_writereg(sc_if->sk_dev, 2283 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2284 mii_tick(mii); 2285 sc_if->sk_link = 1; 2286 /* Turn on the link LED. */ 2287 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2288 SK_LINKLED_ON | SK_LINKLED_LINKSYNC_OFF | 2289 SK_LINKLED_BLINK_OFF); 2290 mii_pollstat(mii); 2291 } else { 2292 mii_tick(mii); 2293 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2294 } 2295 } 2296 2297 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2298 } 2299 2300 void 2301 sk_intr_xmac(struct sk_if_softc *sc_if) 2302 { 2303 uint16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2304 2305 DPRINTFN(3, ("sk_intr_xmac\n")); 2306 2307 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2308 if (status & XM_ISR_GP0_SET) { 2309 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2310 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2311 } 2312 2313 if (status & XM_ISR_AUTONEG_DONE) { 2314 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2315 } 2316 } 2317 2318 if (status & XM_IMR_TX_UNDERRUN) 2319 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2320 2321 if (status & XM_IMR_RX_OVERRUN) 2322 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2323 } 2324 2325 void 2326 sk_intr_yukon(struct sk_if_softc *sc_if) 2327 { 2328 #ifdef SK_DEBUG 2329 int status; 2330 2331 status = 2332 #endif 2333 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2334 2335 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2336 } 2337 2338 int 2339 sk_intr(void *xsc) 2340 { 2341 struct sk_softc *sc = xsc; 2342 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2343 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2344 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2345 uint32_t status; 2346 int claimed = 0; 2347 2348 if (sc_if0 != NULL) 2349 ifp0 = &sc_if0->sk_ethercom.ec_if; 2350 if (sc_if1 != NULL) 2351 ifp1 = &sc_if1->sk_ethercom.ec_if; 2352 2353 for (;;) { 2354 status = CSR_READ_4(sc, SK_ISSR); 2355 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2356 2357 if (!(status & sc->sk_intrmask)) 2358 break; 2359 2360 claimed = 1; 2361 2362 /* Handle receive interrupts first. */ 2363 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2364 sk_rxeof(sc_if0); 2365 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2366 SK_RXBMU_CLR_IRQ_EOF | SK_RXBMU_RX_START); 2367 } 2368 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2369 sk_rxeof(sc_if1); 2370 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2371 SK_RXBMU_CLR_IRQ_EOF | SK_RXBMU_RX_START); 2372 } 2373 2374 /* Then transmit interrupts. */ 2375 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2376 sk_txeof(sc_if0); 2377 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2378 SK_TXBMU_CLR_IRQ_EOF); 2379 } 2380 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2381 sk_txeof(sc_if1); 2382 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2383 SK_TXBMU_CLR_IRQ_EOF); 2384 } 2385 2386 /* Then MAC interrupts. */ 2387 if (sc_if0 && (status & SK_ISR_MAC1) && 2388 (ifp0->if_flags & IFF_RUNNING)) { 2389 if (sc->sk_type == SK_GENESIS) 2390 sk_intr_xmac(sc_if0); 2391 else 2392 sk_intr_yukon(sc_if0); 2393 } 2394 2395 if (sc_if1 && (status & SK_ISR_MAC2) && 2396 (ifp1->if_flags & IFF_RUNNING)) { 2397 if (sc->sk_type == SK_GENESIS) 2398 sk_intr_xmac(sc_if1); 2399 else 2400 sk_intr_yukon(sc_if1); 2401 2402 } 2403 2404 if (status & SK_ISR_EXTERNAL_REG) { 2405 if (sc_if0 != NULL && 2406 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2407 sk_intr_bcom(sc_if0); 2408 2409 if (sc_if1 != NULL && 2410 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2411 sk_intr_bcom(sc_if1); 2412 } 2413 } 2414 2415 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2416 2417 if (ifp0 != NULL) 2418 if_schedule_deferred_start(ifp0); 2419 if (ifp1 != NULL) 2420 if_schedule_deferred_start(ifp1); 2421 2422 KASSERT(sc->rnd_attached > 0); 2423 rnd_add_uint32(&sc->rnd_source, status); 2424 2425 if (sc->sk_int_mod_pending) 2426 sk_update_int_mod(sc); 2427 2428 return claimed; 2429 } 2430 2431 void 2432 sk_init_xmac(struct sk_if_softc *sc_if) 2433 { 2434 struct sk_softc *sc = sc_if->sk_softc; 2435 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2436 static const struct sk_bcom_hack bhack[] = { 2437 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2438 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2439 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2440 { 0, 0 } }; 2441 2442 DPRINTFN(1, ("sk_init_xmac\n")); 2443 2444 /* Unreset the XMAC. */ 2445 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2446 DELAY(1000); 2447 2448 /* Reset the XMAC's internal state. */ 2449 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2450 2451 /* Save the XMAC II revision */ 2452 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2453 2454 /* 2455 * Perform additional initialization for external PHYs, 2456 * namely for the 1000baseTX cards that use the XMAC's 2457 * GMII mode. 2458 */ 2459 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2460 int i = 0; 2461 uint32_t val; 2462 uint16_t phyval; 2463 2464 /* Take PHY out of reset. */ 2465 val = sk_win_read_4(sc, SK_GPIO); 2466 if (sc_if->sk_port == SK_PORT_A) 2467 val |= SK_GPIO_DIR0 | SK_GPIO_DAT0; 2468 else 2469 val |= SK_GPIO_DIR2 | SK_GPIO_DAT2; 2470 sk_win_write_4(sc, SK_GPIO, val); 2471 2472 /* Enable GMII mode on the XMAC. */ 2473 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2474 2475 sk_xmac_miibus_writereg(sc_if->sk_dev, 2476 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2477 DELAY(10000); 2478 sk_xmac_miibus_writereg(sc_if->sk_dev, 2479 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2480 2481 /* 2482 * Early versions of the BCM5400 apparently have 2483 * a bug that requires them to have their reserved 2484 * registers initialized to some magic values. I don't 2485 * know what the numbers do, I'm just the messenger. 2486 */ 2487 sk_xmac_miibus_readreg(sc_if->sk_dev, 2488 SK_PHYADDR_BCOM, 0x03, &phyval); 2489 if (phyval == 0x6041) { 2490 while (bhack[i].reg) { 2491 sk_xmac_miibus_writereg(sc_if->sk_dev, 2492 SK_PHYADDR_BCOM, bhack[i].reg, 2493 bhack[i].val); 2494 i++; 2495 } 2496 } 2497 } 2498 2499 /* Set station address */ 2500 SK_XM_WRITE_2(sc_if, XM_PAR0, 2501 *(uint16_t *)(&sc_if->sk_enaddr[0])); 2502 SK_XM_WRITE_2(sc_if, XM_PAR1, 2503 *(uint16_t *)(&sc_if->sk_enaddr[2])); 2504 SK_XM_WRITE_2(sc_if, XM_PAR2, 2505 *(uint16_t *)(&sc_if->sk_enaddr[4])); 2506 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2507 2508 if (ifp->if_flags & IFF_PROMISC) 2509 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2510 else 2511 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2512 2513 if (ifp->if_flags & IFF_BROADCAST) 2514 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2515 else 2516 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2517 2518 /* We don't need the FCS appended to the packet. */ 2519 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2520 2521 /* We want short frames padded to 60 bytes. */ 2522 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2523 2524 /* 2525 * Enable the reception of all error frames. This is is 2526 * a necessary evil due to the design of the XMAC. The 2527 * XMAC's receive FIFO is only 8K in size, however jumbo 2528 * frames can be up to 9000 bytes in length. When bad 2529 * frame filtering is enabled, the XMAC's RX FIFO operates 2530 * in 'store and forward' mode. For this to work, the 2531 * entire frame has to fit into the FIFO, but that means 2532 * that jumbo frames larger than 8192 bytes will be 2533 * truncated. Disabling all bad frame filtering causes 2534 * the RX FIFO to operate in streaming mode, in which 2535 * case the XMAC will start transfering frames out of the 2536 * RX FIFO as soon as the FIFO threshold is reached. 2537 */ 2538 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES | 2539 XM_MODE_RX_GIANTS | XM_MODE_RX_RUNTS | XM_MODE_RX_CRCERRS | 2540 XM_MODE_RX_INRANGELEN); 2541 2542 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2543 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2544 else 2545 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2546 2547 /* 2548 * Bump up the transmit threshold. This helps hold off transmit 2549 * underruns when we're blasting traffic from both ports at once. 2550 */ 2551 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2552 2553 /* Set multicast filter */ 2554 sk_setmulti(sc_if); 2555 2556 /* Clear and enable interrupts */ 2557 SK_XM_READ_2(sc_if, XM_ISR); 2558 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2559 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2560 else 2561 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2562 2563 /* Configure MAC arbiter */ 2564 switch (sc_if->sk_xmac_rev) { 2565 case XM_XMAC_REV_B2: 2566 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2567 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2568 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2569 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2570 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2571 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2572 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2573 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2574 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2575 break; 2576 case XM_XMAC_REV_C1: 2577 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2578 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2579 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2580 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2581 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2582 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2583 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2584 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2585 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2586 break; 2587 default: 2588 break; 2589 } 2590 sk_win_write_2(sc, SK_MACARB_CTL, 2591 SK_MACARBCTL_UNRESET | SK_MACARBCTL_FASTOE_OFF); 2592 2593 sc_if->sk_link = 1; 2594 } 2595 2596 void sk_init_yukon(struct sk_if_softc *sc_if) 2597 { 2598 uint32_t /*mac, */phy; 2599 uint16_t reg; 2600 struct sk_softc *sc; 2601 int i; 2602 2603 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2604 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2605 2606 sc = sc_if->sk_softc; 2607 if (sc->sk_type == SK_YUKON_LITE && 2608 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2609 /* Take PHY out of reset. */ 2610 sk_win_write_4(sc, SK_GPIO, 2611 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2612 } 2613 2614 2615 /* GMAC and GPHY Reset */ 2616 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2617 2618 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2619 2620 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2621 DELAY(1000); 2622 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2623 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2624 DELAY(1000); 2625 2626 2627 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2628 2629 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2630 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2631 2632 switch (sc_if->sk_softc->sk_pmd) { 2633 case IFM_1000_SX: 2634 case IFM_1000_LX: 2635 phy |= SK_GPHY_FIBER; 2636 break; 2637 2638 case IFM_1000_CX: 2639 case IFM_1000_T: 2640 phy |= SK_GPHY_COPPER; 2641 break; 2642 } 2643 2644 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2645 2646 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2647 DELAY(1000); 2648 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2649 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2650 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2651 2652 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2653 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2654 2655 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2656 2657 /* unused read of the interrupt source register */ 2658 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2659 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2660 2661 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2662 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2663 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2664 2665 /* MIB Counter Clear Mode set */ 2666 reg |= YU_PAR_MIB_CLR; 2667 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2668 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2669 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2670 2671 /* MIB Counter Clear Mode clear */ 2672 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2673 reg &= ~YU_PAR_MIB_CLR; 2674 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2675 2676 /* receive control reg */ 2677 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2678 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2679 YU_RCR_CRCR); 2680 2681 /* transmit parameter register */ 2682 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2683 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2684 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2685 2686 /* serial mode register */ 2687 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2688 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2689 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2690 YU_SMR_IPG_DATA(0x1e)); 2691 2692 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2693 /* Setup Yukon's address */ 2694 for (i = 0; i < 3; i++) { 2695 /* Write Source Address 1 (unicast filter) */ 2696 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2697 sc_if->sk_enaddr[i * 2] | 2698 sc_if->sk_enaddr[i * 2 + 1] << 8); 2699 } 2700 2701 for (i = 0; i < 3; i++) { 2702 reg = sk_win_read_2(sc_if->sk_softc, 2703 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2704 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2705 } 2706 2707 /* Set multicast filter */ 2708 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2709 sk_setmulti(sc_if); 2710 2711 /* enable interrupt mask for counter overflows */ 2712 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2713 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2714 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2715 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2716 2717 /* Configure RX MAC FIFO */ 2718 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2719 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2720 2721 /* Configure TX MAC FIFO */ 2722 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2723 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2724 2725 DPRINTFN(6, ("sk_init_yukon: end\n")); 2726 } 2727 2728 /* 2729 * Note that to properly initialize any part of the GEnesis chip, 2730 * you first have to take it out of reset mode. 2731 */ 2732 int 2733 sk_init(struct ifnet *ifp) 2734 { 2735 struct sk_if_softc *sc_if = ifp->if_softc; 2736 struct sk_softc *sc = sc_if->sk_softc; 2737 struct mii_data *mii = &sc_if->sk_mii; 2738 int rc = 0, s; 2739 uint32_t imr, imtimer_ticks; 2740 2741 DPRINTFN(1, ("sk_init\n")); 2742 2743 s = splnet(); 2744 2745 if (ifp->if_flags & IFF_RUNNING) { 2746 splx(s); 2747 return 0; 2748 } 2749 2750 /* Cancel pending I/O and free all RX/TX buffers. */ 2751 sk_stop(ifp, 0); 2752 2753 if (sc->sk_type == SK_GENESIS) { 2754 /* Configure LINK_SYNC LED */ 2755 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2756 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2757 SK_LINKLED_LINKSYNC_ON); 2758 2759 /* Configure RX LED */ 2760 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2761 SK_RXLEDCTL_COUNTER_START); 2762 2763 /* Configure TX LED */ 2764 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2765 SK_TXLEDCTL_COUNTER_START); 2766 } 2767 2768 /* Configure I2C registers */ 2769 2770 /* Configure XMAC(s) */ 2771 switch (sc->sk_type) { 2772 case SK_GENESIS: 2773 sk_init_xmac(sc_if); 2774 break; 2775 case SK_YUKON: 2776 case SK_YUKON_LITE: 2777 case SK_YUKON_LP: 2778 sk_init_yukon(sc_if); 2779 break; 2780 } 2781 if ((rc = mii_mediachg(mii)) == ENXIO) 2782 rc = 0; 2783 else if (rc != 0) 2784 goto out; 2785 2786 if (sc->sk_type == SK_GENESIS) { 2787 /* Configure MAC FIFOs */ 2788 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2789 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2790 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2791 2792 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2793 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2794 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2795 } 2796 2797 /* Configure transmit arbiter(s) */ 2798 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2799 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2800 2801 /* Configure RAMbuffers */ 2802 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2803 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2804 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2805 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2806 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2807 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2808 2809 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2810 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2811 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2812 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2813 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2814 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2815 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2816 2817 /* Configure BMUs */ 2818 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2819 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2820 SK_RX_RING_ADDR(sc_if, 0)); 2821 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2822 2823 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2824 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2825 SK_TX_RING_ADDR(sc_if, 0)); 2826 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2827 2828 /* Init descriptors */ 2829 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2830 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2831 "memory for rx buffers\n"); 2832 sk_stop(ifp, 0); 2833 splx(s); 2834 return ENOBUFS; 2835 } 2836 2837 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2838 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2839 "memory for tx buffers\n"); 2840 sk_stop(ifp, 0); 2841 splx(s); 2842 return ENOBUFS; 2843 } 2844 2845 /* Set interrupt moderation if changed via sysctl. */ 2846 switch (sc->sk_type) { 2847 case SK_GENESIS: 2848 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2849 break; 2850 case SK_YUKON_EC: 2851 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2852 break; 2853 default: 2854 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2855 } 2856 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2857 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2858 sk_win_write_4(sc, SK_IMTIMERINIT, 2859 SK_IM_USECS(sc->sk_int_mod)); 2860 aprint_verbose_dev(sc->sk_dev, 2861 "interrupt moderation is %d us\n", sc->sk_int_mod); 2862 } 2863 2864 /* Configure interrupt handling */ 2865 CSR_READ_4(sc, SK_ISSR); 2866 if (sc_if->sk_port == SK_PORT_A) 2867 sc->sk_intrmask |= SK_INTRS1; 2868 else 2869 sc->sk_intrmask |= SK_INTRS2; 2870 2871 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2872 2873 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2874 2875 /* Start BMUs. */ 2876 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2877 2878 if (sc->sk_type == SK_GENESIS) { 2879 /* Enable XMACs TX and RX state machines */ 2880 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2881 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2882 XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2883 } 2884 2885 if (SK_YUKON_FAMILY(sc->sk_type)) { 2886 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2887 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2888 #if 0 2889 /* XXX disable 100Mbps and full duplex mode? */ 2890 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2891 #endif 2892 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2893 } 2894 2895 2896 ifp->if_flags |= IFF_RUNNING; 2897 ifp->if_flags &= ~IFF_OACTIVE; 2898 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2899 2900 out: 2901 splx(s); 2902 return rc; 2903 } 2904 2905 void 2906 sk_stop(struct ifnet *ifp, int disable) 2907 { 2908 struct sk_if_softc *sc_if = ifp->if_softc; 2909 struct sk_softc *sc = sc_if->sk_softc; 2910 int i; 2911 2912 DPRINTFN(1, ("sk_stop\n")); 2913 2914 callout_stop(&sc_if->sk_tick_ch); 2915 2916 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2917 uint32_t val; 2918 2919 /* Put PHY back into reset. */ 2920 val = sk_win_read_4(sc, SK_GPIO); 2921 if (sc_if->sk_port == SK_PORT_A) { 2922 val |= SK_GPIO_DIR0; 2923 val &= ~SK_GPIO_DAT0; 2924 } else { 2925 val |= SK_GPIO_DIR2; 2926 val &= ~SK_GPIO_DAT2; 2927 } 2928 sk_win_write_4(sc, SK_GPIO, val); 2929 } 2930 2931 /* Turn off various components of this interface. */ 2932 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2933 switch (sc->sk_type) { 2934 case SK_GENESIS: 2935 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2936 SK_TXMACCTL_XMAC_RESET); 2937 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2938 break; 2939 case SK_YUKON: 2940 case SK_YUKON_LITE: 2941 case SK_YUKON_LP: 2942 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2943 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2944 break; 2945 } 2946 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2947 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET |SK_RBCTL_OFF); 2948 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2949 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2950 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2951 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2952 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2953 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2954 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2955 2956 /* Disable interrupts */ 2957 if (sc_if->sk_port == SK_PORT_A) 2958 sc->sk_intrmask &= ~SK_INTRS1; 2959 else 2960 sc->sk_intrmask &= ~SK_INTRS2; 2961 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2962 2963 SK_XM_READ_2(sc_if, XM_ISR); 2964 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2965 2966 /* Free RX and TX mbufs still in the queues. */ 2967 for (i = 0; i < SK_RX_RING_CNT; i++) { 2968 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2969 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2970 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2971 } 2972 } 2973 2974 for (i = 0; i < SK_TX_RING_CNT; i++) { 2975 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2976 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2977 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2978 } 2979 } 2980 2981 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2982 } 2983 2984 /* Power Management Framework */ 2985 2986 static bool 2987 skc_suspend(device_t dv, const pmf_qual_t *qual) 2988 { 2989 struct sk_softc *sc = device_private(dv); 2990 2991 DPRINTFN(2, ("skc_suspend\n")); 2992 2993 /* Turn off the driver is loaded LED */ 2994 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2995 2996 return true; 2997 } 2998 2999 static bool 3000 skc_resume(device_t dv, const pmf_qual_t *qual) 3001 { 3002 struct sk_softc *sc = device_private(dv); 3003 3004 DPRINTFN(2, ("skc_resume\n")); 3005 3006 sk_reset(sc); 3007 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 3008 3009 return true; 3010 } 3011 3012 static bool 3013 sk_resume(device_t dv, const pmf_qual_t *qual) 3014 { 3015 struct sk_if_softc *sc_if = device_private(dv); 3016 3017 sk_init_yukon(sc_if); 3018 return true; 3019 } 3020 3021 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 3022 skc_probe, skc_attach, NULL, NULL); 3023 3024 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 3025 sk_probe, sk_attach, NULL, NULL); 3026 3027 #ifdef SK_DEBUG 3028 void 3029 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 3030 { 3031 #define DESC_PRINT(X) \ 3032 if (X) \ 3033 printf("txdesc[%d]." #X "=%#x\n", \ 3034 idx, X); 3035 3036 DESC_PRINT(le32toh(desc->sk_ctl)); 3037 DESC_PRINT(le32toh(desc->sk_next)); 3038 DESC_PRINT(le32toh(desc->sk_data_lo)); 3039 DESC_PRINT(le32toh(desc->sk_data_hi)); 3040 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 3041 DESC_PRINT(le16toh(desc->sk_rsvd0)); 3042 DESC_PRINT(le16toh(desc->sk_csum_startval)); 3043 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 3044 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 3045 DESC_PRINT(le16toh(desc->sk_rsvd1)); 3046 #undef PRINT 3047 } 3048 3049 void 3050 sk_dump_bytes(const char *data, int len) 3051 { 3052 int c, i, j; 3053 3054 for (i = 0; i < len; i += 16) { 3055 printf("%08x ", i); 3056 c = len - i; 3057 if (c > 16) c = 16; 3058 3059 for (j = 0; j < c; j++) { 3060 printf("%02x ", data[i + j] & 0xff); 3061 if ((j & 0xf) == 7 && j > 0) 3062 printf(" "); 3063 } 3064 3065 for (; j < 16; j++) 3066 printf(" "); 3067 printf(" "); 3068 3069 for (j = 0; j < c; j++) { 3070 int ch = data[i + j] & 0xff; 3071 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3072 } 3073 3074 printf("\n"); 3075 3076 if (c < 16) 3077 break; 3078 } 3079 } 3080 3081 void 3082 sk_dump_mbuf(struct mbuf *m) 3083 { 3084 int count = m->m_pkthdr.len; 3085 3086 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3087 3088 while (count > 0 && m) { 3089 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3090 m, m->m_data, m->m_len); 3091 sk_dump_bytes(mtod(m, char *), m->m_len); 3092 3093 count -= m->m_len; 3094 m = m->m_next; 3095 } 3096 } 3097 #endif 3098 3099 static int 3100 sk_sysctl_handler(SYSCTLFN_ARGS) 3101 { 3102 int error, t; 3103 struct sysctlnode node; 3104 struct sk_softc *sc; 3105 3106 node = *rnode; 3107 sc = node.sysctl_data; 3108 t = sc->sk_int_mod; 3109 node.sysctl_data = &t; 3110 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3111 if (error || newp == NULL) 3112 return error; 3113 3114 if (t < SK_IM_MIN || t > SK_IM_MAX) 3115 return EINVAL; 3116 3117 /* update the softc with sysctl-changed value, and mark 3118 for hardware update */ 3119 sc->sk_int_mod = t; 3120 sc->sk_int_mod_pending = 1; 3121 return 0; 3122 } 3123 3124 /* 3125 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3126 * set up in skc_attach() 3127 */ 3128 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3129 { 3130 int rc; 3131 const struct sysctlnode *node; 3132 3133 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3134 0, CTLTYPE_NODE, "sk", 3135 SYSCTL_DESCR("sk interface controls"), 3136 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3137 goto err; 3138 } 3139 3140 sk_root_num = node->sysctl_num; 3141 return; 3142 3143 err: 3144 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3145 } 3146
Indexes created Tue Sep 23 07:09:52 GMT 2025