if_skreg.h revision 1.1
1 /* $NetBSD: if_skreg.h,v 1.1 2003/08/26 21:11:00 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 /* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */ 36 /* $OpenBSD: yukonreg.h,v 1.2 2003/08/12 05:23:06 nate Exp $ */ 37 /* $OpenBSD: xmaciireg.h,v 1.2.4.1 2001/05/14 22:26:01 niklas Exp $ */ 38 39 /* 40 * Copyright (c) 1997, 1998, 1999, 2000 41 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Bill Paul. 54 * 4. Neither the name of the author nor the names of any co-contributors 55 * may be used to endorse or promote products derived from this software 56 * without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 59 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 61 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 62 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 63 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 64 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 65 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 66 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 67 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 68 * THE POSSIBILITY OF SUCH DAMAGE. 69 * 70 * $FreeBSD: /c/ncvs/src/sys/pci/if_skreg.h,v 1.9 2000/04/22 02:16:37 wpaul Exp $ 71 */ 72 73 /* 74 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 75 * 76 * Permission to use, copy, modify, and distribute this software for any 77 * purpose with or without fee is hereby granted, provided that the above 78 * copyright notice and this permission notice appear in all copies. 79 * 80 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 81 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 82 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 83 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 84 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 85 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 86 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 87 */ 88 89 #ifndef _DEV_PCI_IF_SKREG_H_ 90 #define _DEV_PCI_IF_SKREG_H_ 91 92 #include <net/if.h> 93 #include <net/if_ether.h> 94 #include <net/if_media.h> 95 96 /* Values to keep the different chip revisions apart */ 97 #define SK_GENESIS 0 98 #define SK_YUKON 1 99 100 /* 101 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 102 * but internally it has a 16K register space. This 16K space is 103 * divided into 128-byte blocks. The first 128 bytes of the I/O 104 * window represent the first block, which is permanently mapped 105 * at the start of the window. The other 127 blocks can be mapped 106 * to the second 128 bytes of the I/O window by setting the desired 107 * block value in the RAP register in block 0. Not all of the 127 108 * blocks are actually used. Most registers are 32 bits wide, but 109 * there are a few 16-bit and 8-bit ones as well. 110 */ 111 112 113 /* Start of remappable register window. */ 114 #define SK_WIN_BASE 0x0080 115 116 /* Size of a window */ 117 #define SK_WIN_LEN 0x80 118 119 #define SK_WIN_MASK 0x3F80 120 #define SK_REG_MASK 0x7F 121 122 /* Compute the window of a given register (for the RAP register) */ 123 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 124 125 /* Compute the relative offset of a register within the window */ 126 #define SK_REG(reg) ((reg) & SK_REG_MASK) 127 128 #define SK_PORT_A 0 129 #define SK_PORT_B 1 130 131 /* 132 * Compute offset of port-specific register. Since there are two 133 * ports, there are two of some GEnesis modules (e.g. two sets of 134 * DMA queues, two sets of FIFO control registers, etc...). Normally, 135 * the block for port 0 is at offset 0x0 and the block for port 1 is 136 * at offset 0x80 (i.e. the next page over). However for the transmit 137 * BMUs and RAMbuffers, there are two blocks for each port: one for 138 * the sync transmit queue and one for the async queue (which we don't 139 * use). However instead of ordering them like this: 140 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 141 * SysKonnect has instead ordered them like this: 142 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 143 * This means that when referencing the TX BMU and RAMbuffer registers, 144 * we have to double the block offset (0x80 * 2) in order to reach the 145 * second queue. This prevents us from using the same formula 146 * (sk_port * 0x80) to compute the offsets for all of the port-specific 147 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 148 * The simplest thing is to provide an extra argument to these macros: 149 * the 'skip' parameter. The 'skip' value is the number of extra pages 150 * for skip when computing the port0/port1 offsets. For most registers, 151 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 152 */ 153 #define SK_IF_READ_4(sc_if, skip, reg) \ 154 sk_win_read_4(sc_if->sk_softc, reg + \ 155 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 156 #define SK_IF_READ_2(sc_if, skip, reg) \ 157 sk_win_read_2(sc_if->sk_softc, reg + \ 158 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 159 #define SK_IF_READ_1(sc_if, skip, reg) \ 160 sk_win_read_1(sc_if->sk_softc, reg + \ 161 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 162 163 #define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 164 sk_win_write_4(sc_if->sk_softc, \ 165 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 166 #define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 167 sk_win_write_2(sc_if->sk_softc, \ 168 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 169 #define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 170 sk_win_write_1(sc_if->sk_softc, \ 171 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 172 173 /* Block 0 registers, permanently mapped at iobase. */ 174 #define SK_RAP 0x0000 175 #define SK_CSR 0x0004 176 #define SK_LED 0x0006 177 #define SK_ISR 0x0008 /* interrupt source */ 178 #define SK_IMR 0x000C /* interrupt mask */ 179 #define SK_IESR 0x0010 /* interrupt hardware error source */ 180 #define SK_IEMR 0x0014 /* interrupt hardware error mask */ 181 #define SK_ISSR 0x0018 /* special interrupt source */ 182 #define SK_XM_IMR0 0x0020 183 #define SK_XM_ISR0 0x0028 184 #define SK_XM_PHYADDR0 0x0030 185 #define SK_XM_PHYDATA0 0x0034 186 #define SK_XM_IMR1 0x0040 187 #define SK_XM_ISR1 0x0048 188 #define SK_XM_PHYADDR1 0x0050 189 #define SK_XM_PHYDATA1 0x0054 190 #define SK_BMU_RX_CSR0 0x0060 191 #define SK_BMU_RX_CSR1 0x0064 192 #define SK_BMU_TXS_CSR0 0x0068 193 #define SK_BMU_TXA_CSR0 0x006C 194 #define SK_BMU_TXS_CSR1 0x0070 195 #define SK_BMU_TXA_CSR1 0x0074 196 197 /* SK_CSR register */ 198 #define SK_CSR_SW_RESET 0x0001 199 #define SK_CSR_SW_UNRESET 0x0002 200 #define SK_CSR_MASTER_RESET 0x0004 201 #define SK_CSR_MASTER_UNRESET 0x0008 202 #define SK_CSR_MASTER_STOP 0x0010 203 #define SK_CSR_MASTER_DONE 0x0020 204 #define SK_CSR_SW_IRQ_CLEAR 0x0040 205 #define SK_CSR_SW_IRQ_SET 0x0080 206 #define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 207 #define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 MHz, = 33 */ 208 209 /* SK_LED register */ 210 #define SK_LED_GREEN_OFF 0x01 211 #define SK_LED_GREEN_ON 0x02 212 213 /* SK_ISR register */ 214 #define SK_ISR_TX2_AS_CHECK 0x00000001 215 #define SK_ISR_TX2_AS_EOF 0x00000002 216 #define SK_ISR_TX2_AS_EOB 0x00000004 217 #define SK_ISR_TX2_S_CHECK 0x00000008 218 #define SK_ISR_TX2_S_EOF 0x00000010 219 #define SK_ISR_TX2_S_EOB 0x00000020 220 #define SK_ISR_TX1_AS_CHECK 0x00000040 221 #define SK_ISR_TX1_AS_EOF 0x00000080 222 #define SK_ISR_TX1_AS_EOB 0x00000100 223 #define SK_ISR_TX1_S_CHECK 0x00000200 224 #define SK_ISR_TX1_S_EOF 0x00000400 225 #define SK_ISR_TX1_S_EOB 0x00000800 226 #define SK_ISR_RX2_CHECK 0x00001000 227 #define SK_ISR_RX2_EOF 0x00002000 228 #define SK_ISR_RX2_EOB 0x00004000 229 #define SK_ISR_RX1_CHECK 0x00008000 230 #define SK_ISR_RX1_EOF 0x00010000 231 #define SK_ISR_RX1_EOB 0x00020000 232 #define SK_ISR_LINK2_OFLOW 0x00040000 233 #define SK_ISR_MAC2 0x00080000 234 #define SK_ISR_LINK1_OFLOW 0x00100000 235 #define SK_ISR_MAC1 0x00200000 236 #define SK_ISR_TIMER 0x00400000 237 #define SK_ISR_EXTERNAL_REG 0x00800000 238 #define SK_ISR_SW 0x01000000 239 #define SK_ISR_I2C_RDY 0x02000000 240 #define SK_ISR_TX2_TIMEO 0x04000000 241 #define SK_ISR_TX1_TIMEO 0x08000000 242 #define SK_ISR_RX2_TIMEO 0x10000000 243 #define SK_ISR_RX1_TIMEO 0x20000000 244 #define SK_ISR_RSVD 0x40000000 245 #define SK_ISR_HWERR 0x80000000 246 247 /* SK_IMR register */ 248 #define SK_IMR_TX2_AS_CHECK 0x00000001 249 #define SK_IMR_TX2_AS_EOF 0x00000002 250 #define SK_IMR_TX2_AS_EOB 0x00000004 251 #define SK_IMR_TX2_S_CHECK 0x00000008 252 #define SK_IMR_TX2_S_EOF 0x00000010 253 #define SK_IMR_TX2_S_EOB 0x00000020 254 #define SK_IMR_TX1_AS_CHECK 0x00000040 255 #define SK_IMR_TX1_AS_EOF 0x00000080 256 #define SK_IMR_TX1_AS_EOB 0x00000100 257 #define SK_IMR_TX1_S_CHECK 0x00000200 258 #define SK_IMR_TX1_S_EOF 0x00000400 259 #define SK_IMR_TX1_S_EOB 0x00000800 260 #define SK_IMR_RX2_CHECK 0x00001000 261 #define SK_IMR_RX2_EOF 0x00002000 262 #define SK_IMR_RX2_EOB 0x00004000 263 #define SK_IMR_RX1_CHECK 0x00008000 264 #define SK_IMR_RX1_EOF 0x00010000 265 #define SK_IMR_RX1_EOB 0x00020000 266 #define SK_IMR_LINK2_OFLOW 0x00040000 267 #define SK_IMR_MAC2 0x00080000 268 #define SK_IMR_LINK1_OFLOW 0x00100000 269 #define SK_IMR_MAC1 0x00200000 270 #define SK_IMR_TIMER 0x00400000 271 #define SK_IMR_EXTERNAL_REG 0x00800000 272 #define SK_IMR_SW 0x01000000 273 #define SK_IMR_I2C_RDY 0x02000000 274 #define SK_IMR_TX2_TIMEO 0x04000000 275 #define SK_IMR_TX1_TIMEO 0x08000000 276 #define SK_IMR_RX2_TIMEO 0x10000000 277 #define SK_IMR_RX1_TIMEO 0x20000000 278 #define SK_IMR_RSVD 0x40000000 279 #define SK_IMR_HWERR 0x80000000 280 281 #define SK_INTRS1 \ 282 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 283 284 #define SK_INTRS2 \ 285 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 286 287 /* SK_IESR register */ 288 #define SK_IESR_PAR_RX2 0x00000001 289 #define SK_IESR_PAR_RX1 0x00000002 290 #define SK_IESR_PAR_MAC2 0x00000004 291 #define SK_IESR_PAR_MAC1 0x00000008 292 #define SK_IESR_PAR_WR_RAM 0x00000010 293 #define SK_IESR_PAR_RD_RAM 0x00000020 294 #define SK_IESR_NO_TSTAMP_MAC2 0x00000040 295 #define SK_IESR_NO_TSTAMO_MAC1 0x00000080 296 #define SK_IESR_NO_STS_MAC2 0x00000100 297 #define SK_IESR_NO_STS_MAC1 0x00000200 298 #define SK_IESR_IRQ_STS 0x00000400 299 #define SK_IESR_MASTERERR 0x00000800 300 301 /* SK_IEMR register */ 302 #define SK_IEMR_PAR_RX2 0x00000001 303 #define SK_IEMR_PAR_RX1 0x00000002 304 #define SK_IEMR_PAR_MAC2 0x00000004 305 #define SK_IEMR_PAR_MAC1 0x00000008 306 #define SK_IEMR_PAR_WR_RAM 0x00000010 307 #define SK_IEMR_PAR_RD_RAM 0x00000020 308 #define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 309 #define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 310 #define SK_IEMR_NO_STS_MAC2 0x00000100 311 #define SK_IEMR_NO_STS_MAC1 0x00000200 312 #define SK_IEMR_IRQ_STS 0x00000400 313 #define SK_IEMR_MASTERERR 0x00000800 314 315 /* Block 2 */ 316 #define SK_MAC0_0 0x0100 317 #define SK_MAC0_1 0x0104 318 #define SK_MAC1_0 0x0108 319 #define SK_MAC1_1 0x010C 320 #define SK_MAC2_0 0x0110 321 #define SK_MAC2_1 0x0114 322 #define SK_CONNTYPE 0x0118 323 #define SK_PMDTYPE 0x0119 324 #define SK_CONFIG 0x011A 325 #define SK_CHIPVER 0x011B 326 #define SK_EPROM0 0x011C 327 #define SK_EPROM1 0x011D 328 #define SK_EPROM2 0x011E 329 #define SK_EPROM3 0x011F 330 #define SK_EP_ADDR 0x0120 331 #define SK_EP_DATA 0x0124 332 #define SK_EP_LOADCTL 0x0128 333 #define SK_EP_LOADTST 0x0129 334 #define SK_TIMERINIT 0x0130 335 #define SK_TIMER 0x0134 336 #define SK_TIMERCTL 0x0138 337 #define SK_TIMERTST 0x0139 338 #define SK_IMTIMERINIT 0x0140 339 #define SK_IMTIMER 0x0144 340 #define SK_IMTIMERCTL 0x0148 341 #define SK_IMTIMERTST 0x0149 342 #define SK_IMMR 0x014C 343 #define SK_IHWEMR 0x0150 344 #define SK_TESTCTL1 0x0158 345 #define SK_TESTCTL2 0x0159 346 #define SK_GPIO 0x015C 347 #define SK_I2CHWCTL 0x0160 348 #define SK_I2CHWDATA 0x0164 349 #define SK_I2CHWIRQ 0x0168 350 #define SK_I2CSW 0x016C 351 #define SK_BLNKINIT 0x0170 352 #define SK_BLNKCOUNT 0x0174 353 #define SK_BLNKCTL 0x0178 354 #define SK_BLNKSTS 0x0179 355 #define SK_BLNKTST 0x017A 356 357 #define SK_IMCTL_STOP 0x02 358 #define SK_IMCTL_START 0x04 359 360 #define SK_IMTIMER_TICKS 54 361 #define SK_IM_USECS(x) ((x) * SK_IMTIMER_TICKS) 362 363 /* 364 * The SK_EPROM0 register contains a byte that describes the 365 * amount of SRAM mounted on the NIC. The value also tells if 366 * the chips are 64K or 128K. This affects the RAMbuffer address 367 * offset that we need to use. 368 */ 369 #define SK_RAMSIZE_512K_64 0x1 370 #define SK_RAMSIZE_1024K_128 0x2 371 #define SK_RAMSIZE_1024K_64 0x3 372 #define SK_RAMSIZE_2048K_128 0x4 373 374 #define SK_RBOFF_0 0x0 375 #define SK_RBOFF_80000 0x80000 376 377 /* 378 * SK_EEPROM1 contains the PHY type, which may be XMAC for 379 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 380 * PHY. 381 */ 382 #define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 383 #define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 384 #define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 385 #define SK_PHYTYPE_NAT 3 /* National DP83891 */ 386 #define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ 387 #define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ 388 389 /* 390 * PHY addresses. 391 */ 392 #define SK_PHYADDR_XMAC 0x0 393 #define SK_PHYADDR_BCOM 0x1 394 #define SK_PHYADDR_LONE 0x3 395 #define SK_PHYADDR_NAT 0x0 396 #define SK_PHYADDR_MARV 0x0 397 398 #define SK_CONFIG_SINGLEMAC 0x01 399 #define SK_CONFIG_DIS_DSL_CLK 0x02 400 401 #define SK_PMD_1000BASELX 0x4C 402 #define SK_PMD_1000BASESX 0x53 403 #define SK_PMD_1000BASECX 0x43 404 #define SK_PMD_1000BASETX 0x54 405 406 /* GPIO bits */ 407 #define SK_GPIO_DAT0 0x00000001 408 #define SK_GPIO_DAT1 0x00000002 409 #define SK_GPIO_DAT2 0x00000004 410 #define SK_GPIO_DAT3 0x00000008 411 #define SK_GPIO_DAT4 0x00000010 412 #define SK_GPIO_DAT5 0x00000020 413 #define SK_GPIO_DAT6 0x00000040 414 #define SK_GPIO_DAT7 0x00000080 415 #define SK_GPIO_DAT8 0x00000100 416 #define SK_GPIO_DAT9 0x00000200 417 #define SK_GPIO_DIR0 0x00010000 418 #define SK_GPIO_DIR1 0x00020000 419 #define SK_GPIO_DIR2 0x00040000 420 #define SK_GPIO_DIR3 0x00080000 421 #define SK_GPIO_DIR4 0x00100000 422 #define SK_GPIO_DIR5 0x00200000 423 #define SK_GPIO_DIR6 0x00400000 424 #define SK_GPIO_DIR7 0x00800000 425 #define SK_GPIO_DIR8 0x01000000 426 #define SK_GPIO_DIR9 0x02000000 427 428 /* Block 3 Ram interface and MAC arbiter registers */ 429 #define SK_RAMADDR 0x0180 430 #define SK_RAMDATA0 0x0184 431 #define SK_RAMDATA1 0x0188 432 #define SK_TO0 0x0190 433 #define SK_TO1 0x0191 434 #define SK_TO2 0x0192 435 #define SK_TO3 0x0193 436 #define SK_TO4 0x0194 437 #define SK_TO5 0x0195 438 #define SK_TO6 0x0196 439 #define SK_TO7 0x0197 440 #define SK_TO8 0x0198 441 #define SK_TO9 0x0199 442 #define SK_TO10 0x019A 443 #define SK_TO11 0x019B 444 #define SK_RITIMEO_TMR 0x019C 445 #define SK_RAMCTL 0x01A0 446 #define SK_RITIMER_TST 0x01A2 447 448 #define SK_RAMCTL_RESET 0x0001 449 #define SK_RAMCTL_UNRESET 0x0002 450 #define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 451 #define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 452 453 /* Mac arbiter registers */ 454 #define SK_MINIT_RX1 0x01B0 455 #define SK_MINIT_RX2 0x01B1 456 #define SK_MINIT_TX1 0x01B2 457 #define SK_MINIT_TX2 0x01B3 458 #define SK_MTIMEO_RX1 0x01B4 459 #define SK_MTIMEO_RX2 0x01B5 460 #define SK_MTIMEO_TX1 0x01B6 461 #define SK_MTIEMO_TX2 0x01B7 462 #define SK_MACARB_CTL 0x01B8 463 #define SK_MTIMER_TST 0x01BA 464 #define SK_RCINIT_RX1 0x01C0 465 #define SK_RCINIT_RX2 0x01C1 466 #define SK_RCINIT_TX1 0x01C2 467 #define SK_RCINIT_TX2 0x01C3 468 #define SK_RCTIMEO_RX1 0x01C4 469 #define SK_RCTIMEO_RX2 0x01C5 470 #define SK_RCTIMEO_TX1 0x01C6 471 #define SK_RCTIMEO_TX2 0x01C7 472 #define SK_RECOVERY_CTL 0x01C8 473 #define SK_RCTIMER_TST 0x01CA 474 475 /* Packet arbiter registers */ 476 #define SK_RXPA1_TINIT 0x01D0 477 #define SK_RXPA2_TINIT 0x01D4 478 #define SK_TXPA1_TINIT 0x01D8 479 #define SK_TXPA2_TINIT 0x01DC 480 #define SK_RXPA1_TIMEO 0x01E0 481 #define SK_RXPA2_TIMEO 0x01E4 482 #define SK_TXPA1_TIMEO 0x01E8 483 #define SK_TXPA2_TIMEO 0x01EC 484 #define SK_PKTARB_CTL 0x01F0 485 #define SK_PKTATB_TST 0x01F2 486 487 #define SK_PKTARB_TIMEOUT 0x2000 488 489 #define SK_PKTARBCTL_RESET 0x0001 490 #define SK_PKTARBCTL_UNRESET 0x0002 491 #define SK_PKTARBCTL_RXTO1_OFF 0x0004 492 #define SK_PKTARBCTL_RXTO1_ON 0x0008 493 #define SK_PKTARBCTL_RXTO2_OFF 0x0010 494 #define SK_PKTARBCTL_RXTO2_ON 0x0020 495 #define SK_PKTARBCTL_TXTO1_OFF 0x0040 496 #define SK_PKTARBCTL_TXTO1_ON 0x0080 497 #define SK_PKTARBCTL_TXTO2_OFF 0x0100 498 #define SK_PKTARBCTL_TXTO2_ON 0x0200 499 #define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 500 #define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 501 #define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 502 #define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 503 504 #define SK_MINIT_XMAC_B2 54 505 #define SK_MINIT_XMAC_C1 63 506 507 #define SK_MACARBCTL_RESET 0x0001 508 #define SK_MACARBCTL_UNRESET 0x0002 509 #define SK_MACARBCTL_FASTOE_OFF 0x0004 510 #define SK_MACARBCRL_FASTOE_ON 0x0008 511 512 #define SK_RCINIT_XMAC_B2 54 513 #define SK_RCINIT_XMAC_C1 0 514 515 #define SK_RECOVERYCTL_RX1_OFF 0x0001 516 #define SK_RECOVERYCTL_RX1_ON 0x0002 517 #define SK_RECOVERYCTL_RX2_OFF 0x0004 518 #define SK_RECOVERYCTL_RX2_ON 0x0008 519 #define SK_RECOVERYCTL_TX1_OFF 0x0010 520 #define SK_RECOVERYCTL_TX1_ON 0x0020 521 #define SK_RECOVERYCTL_TX2_OFF 0x0040 522 #define SK_RECOVERYCTL_TX2_ON 0x0080 523 524 #define SK_RECOVERY_XMAC_B2 \ 525 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 526 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 527 528 #define SK_RECOVERY_XMAC_C1 \ 529 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 530 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 531 532 /* Block 4 -- TX Arbiter MAC 1 */ 533 #define SK_TXAR1_TIMERINIT 0x0200 534 #define SK_TXAR1_TIMERVAL 0x0204 535 #define SK_TXAR1_LIMITINIT 0x0208 536 #define SK_TXAR1_LIMITCNT 0x020C 537 #define SK_TXAR1_COUNTERCTL 0x0210 538 #define SK_TXAR1_COUNTERTST 0x0212 539 #define SK_TXAR1_COUNTERSTS 0x0212 540 541 /* Block 5 -- TX Arbiter MAC 2 */ 542 #define SK_TXAR2_TIMERINIT 0x0280 543 #define SK_TXAR2_TIMERVAL 0x0284 544 #define SK_TXAR2_LIMITINIT 0x0288 545 #define SK_TXAR2_LIMITCNT 0x028C 546 #define SK_TXAR2_COUNTERCTL 0x0290 547 #define SK_TXAR2_COUNTERTST 0x0291 548 #define SK_TXAR2_COUNTERSTS 0x0292 549 550 #define SK_TXARCTL_OFF 0x01 551 #define SK_TXARCTL_ON 0x02 552 #define SK_TXARCTL_RATECTL_OFF 0x04 553 #define SK_TXARCTL_RATECTL_ON 0x08 554 #define SK_TXARCTL_ALLOC_OFF 0x10 555 #define SK_TXARCTL_ALLOC_ON 0x20 556 #define SK_TXARCTL_FSYNC_OFF 0x40 557 #define SK_TXARCTL_FSYNC_ON 0x80 558 559 /* Block 6 -- External registers */ 560 #define SK_EXTREG_BASE 0x300 561 #define SK_EXTREG_END 0x37C 562 563 /* Block 7 -- PCI config registers */ 564 #define SK_PCI_BASE 0x0380 565 #define SK_PCI_END 0x03FC 566 567 /* Compute offset of mirrored PCI register */ 568 #define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 569 570 /* Block 8 -- RX queue 1 */ 571 #define SK_RXQ1_BUFCNT 0x0400 572 #define SK_RXQ1_BUFCTL 0x0402 573 #define SK_RXQ1_NEXTDESC 0x0404 574 #define SK_RXQ1_RXBUF_LO 0x0408 575 #define SK_RXQ1_RXBUF_HI 0x040C 576 #define SK_RXQ1_RXSTAT 0x0410 577 #define SK_RXQ1_TIMESTAMP 0x0414 578 #define SK_RXQ1_CSUM1 0x0418 579 #define SK_RXQ1_CSUM2 0x041A 580 #define SK_RXQ1_CSUM1_START 0x041C 581 #define SK_RXQ1_CSUM2_START 0x041E 582 #define SK_RXQ1_CURADDR_LO 0x0420 583 #define SK_RXQ1_CURADDR_HI 0x0424 584 #define SK_RXQ1_CURCNT_LO 0x0428 585 #define SK_RXQ1_CURCNT_HI 0x042C 586 #define SK_RXQ1_CURBYTES 0x0430 587 #define SK_RXQ1_BMU_CSR 0x0434 588 #define SK_RXQ1_WATERMARK 0x0438 589 #define SK_RXQ1_FLAG 0x043A 590 #define SK_RXQ1_TEST1 0x043C 591 #define SK_RXQ1_TEST2 0x0440 592 #define SK_RXQ1_TEST3 0x0444 593 594 /* Block 9 -- RX queue 2 */ 595 #define SK_RXQ2_BUFCNT 0x0480 596 #define SK_RXQ2_BUFCTL 0x0482 597 #define SK_RXQ2_NEXTDESC 0x0484 598 #define SK_RXQ2_RXBUF_LO 0x0488 599 #define SK_RXQ2_RXBUF_HI 0x048C 600 #define SK_RXQ2_RXSTAT 0x0490 601 #define SK_RXQ2_TIMESTAMP 0x0494 602 #define SK_RXQ2_CSUM1 0x0498 603 #define SK_RXQ2_CSUM2 0x049A 604 #define SK_RXQ2_CSUM1_START 0x049C 605 #define SK_RXQ2_CSUM2_START 0x049E 606 #define SK_RXQ2_CURADDR_LO 0x04A0 607 #define SK_RXQ2_CURADDR_HI 0x04A4 608 #define SK_RXQ2_CURCNT_LO 0x04A8 609 #define SK_RXQ2_CURCNT_HI 0x04AC 610 #define SK_RXQ2_CURBYTES 0x04B0 611 #define SK_RXQ2_BMU_CSR 0x04B4 612 #define SK_RXQ2_WATERMARK 0x04B8 613 #define SK_RXQ2_FLAG 0x04BA 614 #define SK_RXQ2_TEST1 0x04BC 615 #define SK_RXQ2_TEST2 0x04C0 616 #define SK_RXQ2_TEST3 0x04C4 617 618 #define SK_RXBMU_CLR_IRQ_ERR 0x00000001 619 #define SK_RXBMU_CLR_IRQ_EOF 0x00000002 620 #define SK_RXBMU_CLR_IRQ_EOB 0x00000004 621 #define SK_RXBMU_CLR_IRQ_PAR 0x00000008 622 #define SK_RXBMU_RX_START 0x00000010 623 #define SK_RXBMU_RX_STOP 0x00000020 624 #define SK_RXBMU_POLL_OFF 0x00000040 625 #define SK_RXBMU_POLL_ON 0x00000080 626 #define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 627 #define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 628 #define SK_RXBMU_DESCWR_SM_RESET 0x00000400 629 #define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 630 #define SK_RXBMU_DESCRD_SM_RESET 0x00001000 631 #define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 632 #define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 633 #define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 634 #define SK_RXBMU_PFI_SM_RESET 0x00010000 635 #define SK_RXBMU_PFI_SM_UNRESET 0x00020000 636 #define SK_RXBMU_FIFO_RESET 0x00040000 637 #define SK_RXBMU_FIFO_UNRESET 0x00080000 638 #define SK_RXBMU_DESC_RESET 0x00100000 639 #define SK_RXBMU_DESC_UNRESET 0x00200000 640 #define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 641 642 #define SK_RXBMU_ONLINE \ 643 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 644 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 645 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 646 SK_RXBMU_DESC_UNRESET) 647 648 #define SK_RXBMU_OFFLINE \ 649 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 650 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 651 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 652 SK_RXBMU_DESC_RESET) 653 654 /* Block 12 -- TX sync queue 1 */ 655 #define SK_TXQS1_BUFCNT 0x0600 656 #define SK_TXQS1_BUFCTL 0x0602 657 #define SK_TXQS1_NEXTDESC 0x0604 658 #define SK_TXQS1_RXBUF_LO 0x0608 659 #define SK_TXQS1_RXBUF_HI 0x060C 660 #define SK_TXQS1_RXSTAT 0x0610 661 #define SK_TXQS1_CSUM_STARTVAL 0x0614 662 #define SK_TXQS1_CSUM_STARTPOS 0x0618 663 #define SK_TXQS1_CSUM_WRITEPOS 0x061A 664 #define SK_TXQS1_CURADDR_LO 0x0620 665 #define SK_TXQS1_CURADDR_HI 0x0624 666 #define SK_TXQS1_CURCNT_LO 0x0628 667 #define SK_TXQS1_CURCNT_HI 0x062C 668 #define SK_TXQS1_CURBYTES 0x0630 669 #define SK_TXQS1_BMU_CSR 0x0634 670 #define SK_TXQS1_WATERMARK 0x0638 671 #define SK_TXQS1_FLAG 0x063A 672 #define SK_TXQS1_TEST1 0x063C 673 #define SK_TXQS1_TEST2 0x0640 674 #define SK_TXQS1_TEST3 0x0644 675 676 /* Block 13 -- TX async queue 1 */ 677 #define SK_TXQA1_BUFCNT 0x0680 678 #define SK_TXQA1_BUFCTL 0x0682 679 #define SK_TXQA1_NEXTDESC 0x0684 680 #define SK_TXQA1_RXBUF_LO 0x0688 681 #define SK_TXQA1_RXBUF_HI 0x068C 682 #define SK_TXQA1_RXSTAT 0x0690 683 #define SK_TXQA1_CSUM_STARTVAL 0x0694 684 #define SK_TXQA1_CSUM_STARTPOS 0x0698 685 #define SK_TXQA1_CSUM_WRITEPOS 0x069A 686 #define SK_TXQA1_CURADDR_LO 0x06A0 687 #define SK_TXQA1_CURADDR_HI 0x06A4 688 #define SK_TXQA1_CURCNT_LO 0x06A8 689 #define SK_TXQA1_CURCNT_HI 0x06AC 690 #define SK_TXQA1_CURBYTES 0x06B0 691 #define SK_TXQA1_BMU_CSR 0x06B4 692 #define SK_TXQA1_WATERMARK 0x06B8 693 #define SK_TXQA1_FLAG 0x06BA 694 #define SK_TXQA1_TEST1 0x06BC 695 #define SK_TXQA1_TEST2 0x06C0 696 #define SK_TXQA1_TEST3 0x06C4 697 698 /* Block 14 -- TX sync queue 2 */ 699 #define SK_TXQS2_BUFCNT 0x0700 700 #define SK_TXQS2_BUFCTL 0x0702 701 #define SK_TXQS2_NEXTDESC 0x0704 702 #define SK_TXQS2_RXBUF_LO 0x0708 703 #define SK_TXQS2_RXBUF_HI 0x070C 704 #define SK_TXQS2_RXSTAT 0x0710 705 #define SK_TXQS2_CSUM_STARTVAL 0x0714 706 #define SK_TXQS2_CSUM_STARTPOS 0x0718 707 #define SK_TXQS2_CSUM_WRITEPOS 0x071A 708 #define SK_TXQS2_CURADDR_LO 0x0720 709 #define SK_TXQS2_CURADDR_HI 0x0724 710 #define SK_TXQS2_CURCNT_LO 0x0728 711 #define SK_TXQS2_CURCNT_HI 0x072C 712 #define SK_TXQS2_CURBYTES 0x0730 713 #define SK_TXQS2_BMU_CSR 0x0734 714 #define SK_TXQS2_WATERMARK 0x0738 715 #define SK_TXQS2_FLAG 0x073A 716 #define SK_TXQS2_TEST1 0x073C 717 #define SK_TXQS2_TEST2 0x0740 718 #define SK_TXQS2_TEST3 0x0744 719 720 /* Block 15 -- TX async queue 2 */ 721 #define SK_TXQA2_BUFCNT 0x0780 722 #define SK_TXQA2_BUFCTL 0x0782 723 #define SK_TXQA2_NEXTDESC 0x0784 724 #define SK_TXQA2_RXBUF_LO 0x0788 725 #define SK_TXQA2_RXBUF_HI 0x078C 726 #define SK_TXQA2_RXSTAT 0x0790 727 #define SK_TXQA2_CSUM_STARTVAL 0x0794 728 #define SK_TXQA2_CSUM_STARTPOS 0x0798 729 #define SK_TXQA2_CSUM_WRITEPOS 0x079A 730 #define SK_TXQA2_CURADDR_LO 0x07A0 731 #define SK_TXQA2_CURADDR_HI 0x07A4 732 #define SK_TXQA2_CURCNT_LO 0x07A8 733 #define SK_TXQA2_CURCNT_HI 0x07AC 734 #define SK_TXQA2_CURBYTES 0x07B0 735 #define SK_TXQA2_BMU_CSR 0x07B4 736 #define SK_TXQA2_WATERMARK 0x07B8 737 #define SK_TXQA2_FLAG 0x07BA 738 #define SK_TXQA2_TEST1 0x07BC 739 #define SK_TXQA2_TEST2 0x07C0 740 #define SK_TXQA2_TEST3 0x07C4 741 742 #define SK_TXBMU_CLR_IRQ_ERR 0x00000001 743 #define SK_TXBMU_CLR_IRQ_EOF 0x00000002 744 #define SK_TXBMU_CLR_IRQ_EOB 0x00000004 745 #define SK_TXBMU_TX_START 0x00000010 746 #define SK_TXBMU_TX_STOP 0x00000020 747 #define SK_TXBMU_POLL_OFF 0x00000040 748 #define SK_TXBMU_POLL_ON 0x00000080 749 #define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 750 #define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 751 #define SK_TXBMU_DESCWR_SM_RESET 0x00000400 752 #define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 753 #define SK_TXBMU_DESCRD_SM_RESET 0x00001000 754 #define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 755 #define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 756 #define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 757 #define SK_TXBMU_PFI_SM_RESET 0x00010000 758 #define SK_TXBMU_PFI_SM_UNRESET 0x00020000 759 #define SK_TXBMU_FIFO_RESET 0x00040000 760 #define SK_TXBMU_FIFO_UNRESET 0x00080000 761 #define SK_TXBMU_DESC_RESET 0x00100000 762 #define SK_TXBMU_DESC_UNRESET 0x00200000 763 #define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 764 765 #define SK_TXBMU_ONLINE \ 766 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 767 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 768 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 769 SK_TXBMU_DESC_UNRESET) 770 771 #define SK_TXBMU_OFFLINE \ 772 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 773 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 774 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 775 SK_TXBMU_DESC_RESET) 776 777 /* Block 16 -- Receive RAMbuffer 1 */ 778 #define SK_RXRB1_START 0x0800 779 #define SK_RXRB1_END 0x0804 780 #define SK_RXRB1_WR_PTR 0x0808 781 #define SK_RXRB1_RD_PTR 0x080C 782 #define SK_RXRB1_UTHR_PAUSE 0x0810 783 #define SK_RXRB1_LTHR_PAUSE 0x0814 784 #define SK_RXRB1_UTHR_HIPRIO 0x0818 785 #define SK_RXRB1_UTHR_LOPRIO 0x081C 786 #define SK_RXRB1_PKTCNT 0x0820 787 #define SK_RXRB1_LVL 0x0824 788 #define SK_RXRB1_CTLTST 0x0828 789 790 /* Block 17 -- Receive RAMbuffer 2 */ 791 #define SK_RXRB2_START 0x0880 792 #define SK_RXRB2_END 0x0884 793 #define SK_RXRB2_WR_PTR 0x0888 794 #define SK_RXRB2_RD_PTR 0x088C 795 #define SK_RXRB2_UTHR_PAUSE 0x0890 796 #define SK_RXRB2_LTHR_PAUSE 0x0894 797 #define SK_RXRB2_UTHR_HIPRIO 0x0898 798 #define SK_RXRB2_UTHR_LOPRIO 0x089C 799 #define SK_RXRB2_PKTCNT 0x08A0 800 #define SK_RXRB2_LVL 0x08A4 801 #define SK_RXRB2_CTLTST 0x08A8 802 803 /* Block 20 -- Sync. Transmit RAMbuffer 1 */ 804 #define SK_TXRBS1_START 0x0A00 805 #define SK_TXRBS1_END 0x0A04 806 #define SK_TXRBS1_WR_PTR 0x0A08 807 #define SK_TXRBS1_RD_PTR 0x0A0C 808 #define SK_TXRBS1_PKTCNT 0x0A20 809 #define SK_TXRBS1_LVL 0x0A24 810 #define SK_TXRBS1_CTLTST 0x0A28 811 812 /* Block 21 -- Async. Transmit RAMbuffer 1 */ 813 #define SK_TXRBA1_START 0x0A80 814 #define SK_TXRBA1_END 0x0A84 815 #define SK_TXRBA1_WR_PTR 0x0A88 816 #define SK_TXRBA1_RD_PTR 0x0A8C 817 #define SK_TXRBA1_PKTCNT 0x0AA0 818 #define SK_TXRBA1_LVL 0x0AA4 819 #define SK_TXRBA1_CTLTST 0x0AA8 820 821 /* Block 22 -- Sync. Transmit RAMbuffer 2 */ 822 #define SK_TXRBS2_START 0x0B00 823 #define SK_TXRBS2_END 0x0B04 824 #define SK_TXRBS2_WR_PTR 0x0B08 825 #define SK_TXRBS2_RD_PTR 0x0B0C 826 #define SK_TXRBS2_PKTCNT 0x0B20 827 #define SK_TXRBS2_LVL 0x0B24 828 #define SK_TXRBS2_CTLTST 0x0B28 829 830 /* Block 23 -- Async. Transmit RAMbuffer 2 */ 831 #define SK_TXRBA2_START 0x0B80 832 #define SK_TXRBA2_END 0x0B84 833 #define SK_TXRBA2_WR_PTR 0x0B88 834 #define SK_TXRBA2_RD_PTR 0x0B8C 835 #define SK_TXRBA2_PKTCNT 0x0BA0 836 #define SK_TXRBA2_LVL 0x0BA4 837 #define SK_TXRBA2_CTLTST 0x0BA8 838 839 #define SK_RBCTL_RESET 0x00000001 840 #define SK_RBCTL_UNRESET 0x00000002 841 #define SK_RBCTL_OFF 0x00000004 842 #define SK_RBCTL_ON 0x00000008 843 #define SK_RBCTL_STORENFWD_OFF 0x00000010 844 #define SK_RBCTL_STORENFWD_ON 0x00000020 845 846 /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 847 #define SK_RXF1_END 0x0C00 848 #define SK_RXF1_WPTR 0x0C04 849 #define SK_RXF1_RPTR 0x0C0C 850 #define SK_RXF1_PKTCNT 0x0C10 851 #define SK_RXF1_LVL 0x0C14 852 #define SK_RXF1_MACCTL 0x0C18 853 #define SK_RXF1_CTL 0x0C1C 854 #define SK_RXLED1_CNTINIT 0x0C20 855 #define SK_RXLED1_COUNTER 0x0C24 856 #define SK_RXLED1_CTL 0x0C28 857 #define SK_RXLED1_TST 0x0C29 858 #define SK_LINK_SYNC1_CINIT 0x0C30 859 #define SK_LINK_SYNC1_COUNTER 0x0C34 860 #define SK_LINK_SYNC1_CTL 0x0C38 861 #define SK_LINK_SYNC1_TST 0x0C39 862 #define SK_LINKLED1_CTL 0x0C3C 863 864 #define SK_FIFO_END 0x3F 865 866 /* Receive MAC FIFO 1 (Yukon Only) */ 867 #define SK_RXMF1_END 0x0C40 868 #define SK_RXMF1_THRESHOLD 0x0C44 869 #define SK_RXMF1_CTRL_TEST 0x0C48 870 #define SK_RXMF1_WRITE_PTR 0x0C60 871 #define SK_RXMF1_WRITE_LEVEL 0x0C68 872 #define SK_RXMF1_READ_PTR 0x0C70 873 #define SK_RXMF1_READ_LEVEL 0x0C78 874 875 #define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 876 #define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 877 #define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 878 #define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 879 #define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 880 #define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 881 #define SK_RFCTL_RX_FIFO_OVER 0x00000040 /* Clear IRQ RX FIFO Overrun */ 882 #define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ 883 #define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 884 #define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 885 #define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 886 #define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 887 888 889 /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 890 #define SK_RXF2_END 0x0C80 891 #define SK_RXF2_WPTR 0x0C84 892 #define SK_RXF2_RPTR 0x0C8C 893 #define SK_RXF2_PKTCNT 0x0C90 894 #define SK_RXF2_LVL 0x0C94 895 #define SK_RXF2_MACCTL 0x0C98 896 #define SK_RXF2_CTL 0x0C9C 897 #define SK_RXLED2_CNTINIT 0x0CA0 898 #define SK_RXLED2_COUNTER 0x0CA4 899 #define SK_RXLED2_CTL 0x0CA8 900 #define SK_RXLED2_TST 0x0CA9 901 #define SK_LINK_SYNC2_CINIT 0x0CB0 902 #define SK_LINK_SYNC2_COUNTER 0x0CB4 903 #define SK_LINK_SYNC2_CTL 0x0CB8 904 #define SK_LINK_SYNC2_TST 0x0CB9 905 #define SK_LINKLED2_CTL 0x0CBC 906 907 #define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 908 #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 909 #define SK_RXMACCTL_TSTAMP_OFF 0x00000004 910 #define SK_RXMACCTL_RSTAMP_ON 0x00000008 911 #define SK_RXMACCTL_FLUSH_OFF 0x00000010 912 #define SK_RXMACCTL_FLUSH_ON 0x00000020 913 #define SK_RXMACCTL_PAUSE_OFF 0x00000040 914 #define SK_RXMACCTL_PAUSE_ON 0x00000080 915 #define SK_RXMACCTL_AFULL_OFF 0x00000100 916 #define SK_RXMACCTL_AFULL_ON 0x00000200 917 #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 918 #define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 919 #define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 920 #define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 921 #define SK_RXMACCTL_STS_TIMEO 0x00FF0000 922 #define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 923 924 #define SK_RXLEDCTL_ENABLE 0x0001 925 #define SK_RXLEDCTL_COUNTER_STOP 0x0002 926 #define SK_RXLEDCTL_COUNTER_START 0x0004 927 928 #define SK_LINKLED_OFF 0x0001 929 #define SK_LINKLED_ON 0x0002 930 #define SK_LINKLED_LINKSYNC_OFF 0x0004 931 #define SK_LINKLED_LINKSYNC_ON 0x0008 932 #define SK_LINKLED_BLINK_OFF 0x0010 933 #define SK_LINKLED_BLINK_ON 0x0020 934 935 /* Block 26 -- TX MAC FIFO 1 regisrers */ 936 #define SK_TXF1_END 0x0D00 937 #define SK_TXF1_WPTR 0x0D04 938 #define SK_TXF1_RPTR 0x0D0C 939 #define SK_TXF1_PKTCNT 0x0D10 940 #define SK_TXF1_LVL 0x0D14 941 #define SK_TXF1_MACCTL 0x0D18 942 #define SK_TXF1_CTL 0x0D1C 943 #define SK_TXLED1_CNTINIT 0x0D20 944 #define SK_TXLED1_COUNTER 0x0D24 945 #define SK_TXLED1_CTL 0x0D28 946 #define SK_TXLED1_TST 0x0D29 947 948 /* Receive MAC FIFO 1 (Yukon Only) */ 949 #define SK_TXMF1_END 0x0D40 950 #define SK_TXMF1_THRESHOLD 0x0D44 951 #define SK_TXMF1_CTRL_TEST 0x0D48 952 #define SK_TXMF1_WRITE_PTR 0x0D60 953 #define SK_TXMF1_WRITE_SHADOW 0x0D64 954 #define SK_TXMF1_WRITE_LEVEL 0x0D68 955 #define SK_TXMF1_READ_PTR 0x0D70 956 #define SK_TXMF1_RESTART_PTR 0x0D74 957 #define SK_TXMF1_READ_LEVEL 0x0D78 958 959 #define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 960 #define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 961 #define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 962 #define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 963 #define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 964 #define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 965 #define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ 966 #define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ 967 #define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ 968 #define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 969 #define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 970 #define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 971 #define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 972 973 /* Block 27 -- TX MAC FIFO 2 regisrers */ 974 #define SK_TXF2_END 0x0D80 975 #define SK_TXF2_WPTR 0x0D84 976 #define SK_TXF2_RPTR 0x0D8C 977 #define SK_TXF2_PKTCNT 0x0D90 978 #define SK_TXF2_LVL 0x0D94 979 #define SK_TXF2_MACCTL 0x0D98 980 #define SK_TXF2_CTL 0x0D9C 981 #define SK_TXLED2_CNTINIT 0x0DA0 982 #define SK_TXLED2_COUNTER 0x0DA4 983 #define SK_TXLED2_CTL 0x0DA8 984 #define SK_TXLED2_TST 0x0DA9 985 986 #define SK_TXMACCTL_XMAC_RESET 0x00000001 987 #define SK_TXMACCTL_XMAC_UNRESET 0x00000002 988 #define SK_TXMACCTL_LOOP_OFF 0x00000004 989 #define SK_TXMACCTL_LOOP_ON 0x00000008 990 #define SK_TXMACCTL_FLUSH_OFF 0x00000010 991 #define SK_TXMACCTL_FLUSH_ON 0x00000020 992 #define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 993 #define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 994 #define SK_TXMACCTL_AFULL_OFF 0x00000100 995 #define SK_TXMACCTL_AFULL_ON 0x00000200 996 #define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 997 #define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 998 #define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 999 #define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 1000 #define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 1001 #define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 1002 1003 #define SK_TXLEDCTL_ENABLE 0x0001 1004 #define SK_TXLEDCTL_COUNTER_STOP 0x0002 1005 #define SK_TXLEDCTL_COUNTER_START 0x0004 1006 1007 #define SK_FIFO_RESET 0x00000001 1008 #define SK_FIFO_UNRESET 0x00000002 1009 #define SK_FIFO_OFF 0x00000004 1010 #define SK_FIFO_ON 0x00000008 1011 1012 /* Block 28 -- Descriptor Poll Timer */ 1013 #define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ 1014 #define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ 1015 1016 #define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */ 1017 #define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */ 1018 #define SK_DPT_TCTL_START 0x0002 /* Start Timer */ 1019 1020 #define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ 1021 #define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ 1022 #define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ 1023 #define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ 1024 1025 /* Block 29 -- reserved */ 1026 1027 /* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ 1028 #define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ 1029 #define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ 1030 #define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ 1031 #define SK_GMAC_IMR 0x0f08 /* GMAC Interrupt Mask Register */ 1032 #define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ 1033 #define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ 1034 #define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ 1035 #define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ 1036 #define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ 1037 #define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ 1038 #define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ 1039 #define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ 1040 #define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ 1041 #define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ 1042 #define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ 1043 #define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ 1044 #define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ 1045 #define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ 1046 #define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ 1047 #define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ 1048 #define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ 1049 #define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ 1050 #define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ 1051 #define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ 1052 #define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ 1053 #define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ 1054 #define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ 1055 #define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ 1056 #define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ 1057 1058 #define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ 1059 #define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ 1060 #define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ 1061 #define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ 1062 #define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ 1063 #define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ 1064 1065 #define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ 1066 #define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ 1067 #define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ 1068 #define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ 1069 #define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ 1070 #define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ 1071 #define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ 1072 #define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ 1073 #define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ 1074 #define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ 1075 #define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ 1076 #define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ 1077 #define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ 1078 #define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ 1079 #define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ 1080 #define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ 1081 #define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ 1082 #define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ 1083 #define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ 1084 #define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ 1085 #define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ 1086 #define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ 1087 #define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ 1088 1089 #define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1090 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) 1091 #define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1092 SK_GPHY_HWCFG_M_2 ) 1093 #define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ 1094 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) 1095 1096 #define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ 1097 #define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ 1098 #define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ 1099 #define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ 1100 #define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ 1101 #define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ 1102 1103 #define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ 1104 #define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ 1105 1106 /* Block 31 -- reserved */ 1107 1108 /* Block 32-33 -- Pattern Ram */ 1109 #define SK_WOL_PRAM 0x1000 1110 1111 /* Block 0x22 - 0x3f -- reserved */ 1112 1113 /* Block 0x40 to 0x4F -- XMAC 1 registers */ 1114 #define SK_XMAC1_BASE 0x2000 1115 1116 /* Block 0x50 to 0x5F -- MARV 1 registers */ 1117 #define SK_MARV1_BASE 0x2800 1118 1119 /* Block 0x60 to 0x6F -- XMAC 2 registers */ 1120 #define SK_XMAC2_BASE 0x3000 1121 1122 /* Block 0x70 to 0x7F -- MARV 2 registers */ 1123 #define SK_MARV2_BASE 0x3800 1124 1125 /* Compute relative offset of an XMAC register in the XMAC window(s). */ 1126 #define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ 1127 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 1128 1129 #if 0 1130 #define SK_XM_READ_4(sc, reg) \ 1131 ((sk_win_read_2(sc->sk_softc, \ 1132 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ 1133 ((sk_win_read_2(sc->sk_softc, \ 1134 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) 1135 1136 #define SK_XM_WRITE_4(sc, reg, val) \ 1137 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ 1138 ((val) & 0xFFFF)); \ 1139 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ 1140 ((val) >> 16) & 0xFFFF) 1141 #else 1142 #define SK_XM_READ_4(sc, reg) \ 1143 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1144 1145 #define SK_XM_WRITE_4(sc, reg, val) \ 1146 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) 1147 #endif 1148 1149 #define SK_XM_READ_2(sc, reg) \ 1150 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1151 1152 #define SK_XM_WRITE_2(sc, reg, val) \ 1153 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) 1154 1155 #define SK_XM_SETBIT_4(sc, reg, x) \ 1156 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1157 1158 #define SK_XM_CLRBIT_4(sc, reg, x) \ 1159 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1160 1161 #define SK_XM_SETBIT_2(sc, reg, x) \ 1162 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1163 1164 #define SK_XM_CLRBIT_2(sc, reg, x) \ 1165 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1166 1167 /* Compute relative offset of an MARV register in the MARV window(s). */ 1168 #define SK_YU_REG(sc, reg) \ 1169 ((reg) + SK_MARV1_BASE + \ 1170 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) 1171 1172 #define SK_YU_READ_4(sc, reg) \ 1173 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1174 1175 #define SK_YU_READ_2(sc, reg) \ 1176 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1177 1178 #define SK_YU_WRITE_4(sc, reg, val) \ 1179 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1180 1181 #define SK_YU_WRITE_2(sc, reg, val) \ 1182 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1183 1184 #define SK_YU_SETBIT_4(sc, reg, x) \ 1185 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1186 1187 #define SK_YU_CLRBIT_4(sc, reg, x) \ 1188 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1189 1190 #define SK_YU_SETBIT_2(sc, reg, x) \ 1191 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) 1192 1193 #define SK_YU_CLRBIT_2(sc, reg, x) \ 1194 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) 1195 1196 /* 1197 * The default FIFO threshold on the XMAC II is 4 bytes. On 1198 * dual port NICs, this often leads to transmit underruns, so we 1199 * bump the threshold a little. 1200 */ 1201 #define SK_XM_TX_FIFOTHRESH 512 1202 1203 #define SK_PCI_VENDOR_ID 0x0000 1204 #define SK_PCI_DEVICE_ID 0x0002 1205 #define SK_PCI_COMMAND 0x0004 1206 #define SK_PCI_STATUS 0x0006 1207 #define SK_PCI_REVID 0x0008 1208 #define SK_PCI_CLASSCODE 0x0009 1209 #define SK_PCI_CACHELEN 0x000C 1210 #define SK_PCI_LATENCY_TIMER 0x000D 1211 #define SK_PCI_HEADER_TYPE 0x000E 1212 #define SK_PCI_LOMEM 0x0010 1213 #define SK_PCI_LOIO 0x0014 1214 #define SK_PCI_SUBVEN_ID 0x002C 1215 #define SK_PCI_SYBSYS_ID 0x002E 1216 #define SK_PCI_BIOSROM 0x0030 1217 #define SK_PCI_INTLINE 0x003C 1218 #define SK_PCI_INTPIN 0x003D 1219 #define SK_PCI_MINGNT 0x003E 1220 #define SK_PCI_MINLAT 0x003F 1221 1222 /* device specific PCI registers */ 1223 #define SK_PCI_OURREG1 0x0040 1224 #define SK_PCI_OURREG2 0x0044 1225 #define SK_PCI_CAPID 0x0048 /* 8 bits */ 1226 #define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 1227 #define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 1228 #define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 1229 #define SK_PCI_PME_EVENT 0x004F 1230 #define SK_PCI_VPD_CAPID 0x0050 1231 #define SK_PCI_VPD_NEXTPTR 0x0051 1232 #define SK_PCI_VPD_ADDR 0x0052 1233 #define SK_PCI_VPD_DATA 0x0054 1234 1235 #define SK_PSTATE_MASK 0x0003 1236 #define SK_PSTATE_D0 0x0000 1237 #define SK_PSTATE_D1 0x0001 1238 #define SK_PSTATE_D2 0x0002 1239 #define SK_PSTATE_D3 0x0003 1240 #define SK_PME_EN 0x0010 1241 #define SK_PME_STATUS 0x8000 1242 1243 /* 1244 * VPD flag bit. Set to 0 to initiate a read, will become 1 when 1245 * read is complete. Set to 1 to initiate a write, will become 0 1246 * when write is finished. 1247 */ 1248 #define SK_VPD_FLAG 0x8000 1249 1250 /* VPD structures */ 1251 struct vpd_res { 1252 u_int8_t vr_id; 1253 u_int8_t vr_len; 1254 u_int8_t vr_pad; 1255 }; 1256 1257 struct vpd_key { 1258 char vk_key[2]; 1259 u_int8_t vk_len; 1260 }; 1261 1262 #define VPD_RES_ID 0x82 /* ID string */ 1263 #define VPD_RES_READ 0x90 /* start of read only area */ 1264 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 1265 #define VPD_RES_END 0x78 /* end tag */ 1266 1267 #define CSR_WRITE_4(sc, reg, val) \ 1268 bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1269 #define CSR_WRITE_2(sc, reg, val) \ 1270 bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1271 #define CSR_WRITE_1(sc, reg, val) \ 1272 bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1273 1274 #define CSR_READ_4(sc, reg) \ 1275 bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1276 #define CSR_READ_2(sc, reg) \ 1277 bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1278 #define CSR_READ_1(sc, reg) \ 1279 bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1280 1281 struct sk_type { 1282 u_int16_t sk_vid; 1283 u_int16_t sk_did; 1284 char *sk_name; 1285 }; 1286 1287 /* RX queue descriptor data structure */ 1288 struct sk_rx_desc { 1289 u_int32_t sk_ctl; 1290 u_int32_t sk_next; 1291 u_int32_t sk_data_lo; 1292 u_int32_t sk_data_hi; 1293 u_int32_t sk_xmac_rxstat; 1294 u_int32_t sk_timestamp; 1295 u_int16_t sk_csum2; 1296 u_int16_t sk_csum1; 1297 u_int16_t sk_csum2_start; 1298 u_int16_t sk_csum1_start; 1299 }; 1300 1301 #define SK_OPCODE_DEFAULT 0x00550000 1302 #define SK_OPCODE_CSUM 0x00560000 1303 1304 #define SK_RXCTL_LEN 0x0000FFFF 1305 #define SK_RXCTL_OPCODE 0x00FF0000 1306 #define SK_RXCTL_TSTAMP_VALID 0x01000000 1307 #define SK_RXCTL_STATUS_VALID 0x02000000 1308 #define SK_RXCTL_DEV0 0x04000000 1309 #define SK_RXCTL_EOF_INTR 0x08000000 1310 #define SK_RXCTL_EOB_INTR 0x10000000 1311 #define SK_RXCTL_LASTFRAG 0x20000000 1312 #define SK_RXCTL_FIRSTFRAG 0x40000000 1313 #define SK_RXCTL_OWN 0x80000000 1314 1315 #define SK_RXSTAT \ 1316 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \ 1317 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1318 1319 struct sk_tx_desc { 1320 u_int32_t sk_ctl; 1321 u_int32_t sk_next; 1322 u_int32_t sk_data_lo; 1323 u_int32_t sk_data_hi; 1324 u_int32_t sk_xmac_txstat; 1325 u_int16_t sk_rsvd0; 1326 u_int16_t sk_csum_startval; 1327 u_int16_t sk_csum_startpos; 1328 u_int16_t sk_csum_writepos; 1329 u_int32_t sk_rsvd1; 1330 }; 1331 1332 #define SK_TXCTL_LEN 0x0000FFFF 1333 #define SK_TXCTL_OPCODE 0x00FF0000 1334 #define SK_TXCTL_SW 0x01000000 1335 #define SK_TXCTL_NOCRC 0x02000000 1336 #define SK_TXCTL_STORENFWD 0x04000000 1337 #define SK_TXCTL_EOF_INTR 0x08000000 1338 #define SK_TXCTL_EOB_INTR 0x10000000 1339 #define SK_TXCTL_LASTFRAG 0x20000000 1340 #define SK_TXCTL_FIRSTFRAG 0x40000000 1341 #define SK_TXCTL_OWN 0x80000000 1342 1343 #define SK_TXSTAT \ 1344 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1345 1346 #define SK_RXBYTES(x) (x) & 0x0000FFFF; 1347 #define SK_TXBYTES SK_RXBYTES 1348 1349 #define SK_TX_RING_CNT 512 1350 #define SK_RX_RING_CNT 256 1351 1352 /* 1353 * Jumbo buffer stuff. Note that we must allocate more jumbo 1354 * buffers than there are descriptors in the receive ring. This 1355 * is because we don't know how long it will take for a packet 1356 * to be released after we hand it off to the upper protocol 1357 * layers. To be safe, we allocate 1.5 times the number of 1358 * receive descriptors. 1359 */ 1360 #define SK_JUMBO_FRAMELEN 9018 1361 #define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1362 #define SK_JSLOTS 384 1363 1364 #define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN) 1365 #define SK_JLEN SK_JRAWLEN 1366 #define SK_MCLBYTES SK_JLEN 1367 #define SK_JPAGESZ PAGE_SIZE 1368 #define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) 1369 #define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) 1370 1371 #define SK_MAXUNIT 256 1372 #define SK_TIMEOUT 1000 1373 #define ETHER_ALIGN 2 1374 1375 /* YUKON registers */ 1376 1377 /* General Purpose Status Register (GPSR) */ 1378 #define YUKON_GPSR 0x0000 1379 1380 #define YU_GPSR_SPEED 0x8000 /* speed 0 - 10Mbps, 1 - 100Mbps */ 1381 #define YU_GPSR_DUPLEX 0x4000 /* 0 - half duplex, 1 - full duplex */ 1382 #define YU_GPSR_FCTL_TX 0x2000 /* flow control */ 1383 #define YU_GPSR_LINK 0x1000 /* link status (down/up) */ 1384 #define YU_GPSR_PAUSE 0x0800 /* flow control enable/disable */ 1385 #define YU_GPSR_TX_IN_PROG 0x0400 /* transmit in progress */ 1386 #define YU_GPSR_EXCESS_COL 0x0200 /* excessive collisions occurred */ 1387 #define YU_GPSR_LATE_COL 0x0100 /* late collision occurred */ 1388 #define YU_GPSR_MII_PHY_STC 0x0020 /* MII PHY status change */ 1389 #define YU_GPSR_GIG_SPEED 0x0010 /* Gigabit Speed (0 - use speed bit) */ 1390 #define YU_GPSR_PARTITION 0x0008 /* partition mode */ 1391 #define YU_GPSR_FCTL_RX 0x0004 /* flow control enable/disable */ 1392 #define YU_GPSR_PROMS_EN 0x0002 /* promiscuous mode enable/disable */ 1393 1394 /* General Purpose Control Register (GPCR) */ 1395 #define YUKON_GPCR 0x0004 1396 1397 #define YU_GPCR_FCTL_TX 0x2000 /* Transmit flow control 802.3x */ 1398 #define YU_GPCR_TXEN 0x1000 /* Transmit Enable */ 1399 #define YU_GPCR_RXEN 0x0800 /* Receive Enable */ 1400 #define YU_GPCR_LPBK 0x0200 /* Loopback Enable */ 1401 #define YU_GPCR_PAR 0x0100 /* Partition Enable */ 1402 #define YU_GPCR_GIG 0x0080 /* Gigabit Speed */ 1403 #define YU_GPCR_FLP 0x0040 /* Force Link Pass */ 1404 #define YU_GPCR_DUPLEX 0x0020 /* Duplex Enable */ 1405 #define YU_GPCR_FCTL_RX 0x0010 /* Receive flow control 802.3x */ 1406 #define YU_GPCR_SPEED 0x0008 /* Port Speed */ 1407 #define YU_GPCR_DPLX_EN 0x0004 /* Enable Auto-Update for duplex */ 1408 #define YU_GPCR_FCTL_EN 0x0002 /* Enabel Auto-Update for 802.3x */ 1409 #define YU_GPCR_SPEED_EN 0x0001 /* Enable Auto-Update for speed */ 1410 1411 /* Transmit Control Register (TCR) */ 1412 #define YUKON_TCR 0x0008 1413 1414 #define YU_TCR_FJ 0x8000 /* force jam / flow control */ 1415 #define YU_TCR_CRCD 0x4000 /* insert CRC (0 - enable) */ 1416 #define YU_TCR_PADD 0x2000 /* pad packets to 64b (0 - enable) */ 1417 #define YU_TCR_COLTH 0x1c00 /* collision threshold */ 1418 1419 /* Receive Control Register (RCR) */ 1420 #define YUKON_RCR 0x000c 1421 1422 #define YU_RCR_UFLEN 0x8000 /* unicast filter enable */ 1423 #define YU_RCR_MUFLEN 0x4000 /* multicast filter enable */ 1424 #define YU_RCR_CRCR 0x2000 /* remove CRC */ 1425 #define YU_RCR_PASSFC 0x1000 /* pass flow control packets */ 1426 1427 /* Transmit Flow Control Register (TFCR) */ 1428 #define YUKON_TFCR 0x0010 /* Pause Time */ 1429 1430 /* Transmit Parameter Register (TPR) */ 1431 #define YUKON_TPR 0x0014 1432 1433 #define YU_TPR_JAM_LEN(x) (((x) & 0x3) << 14) 1434 #define YU_TPR_JAM_IPG(x) (((x) & 0x1f) << 9) 1435 #define YU_TPR_JAM2DATA_IPG(x) (((x) & 0x1f) << 4) 1436 1437 /* Serial Mode Register (SMR) */ 1438 #define YUKON_SMR 0x0018 1439 1440 #define YU_SMR_DATA_BLIND(x) (((x) & 0x1f) << 11) 1441 #define YU_SMR_LIMIT4 0x0400 /* reset after 16 / 4 collisions */ 1442 #define YU_SMR_MFL_JUMBO 0x0100 /* max frame length for jumbo frames */ 1443 #define YU_SMR_MFL_VLAN 0x0200 /* max frame length + vlan tag */ 1444 #define YU_SMR_IPG_DATA(x) ((x) & 0x1f) 1445 1446 /* Source Address Low #1 (SAL1) */ 1447 #define YUKON_SAL1 0x001c /* SA1[15:0] */ 1448 1449 /* Source Address Middle #1 (SAM1) */ 1450 #define YUKON_SAM1 0x0020 /* SA1[31:16] */ 1451 1452 /* Source Address High #1 (SAH1) */ 1453 #define YUKON_SAH1 0x0024 /* SA1[47:32] */ 1454 1455 /* Source Address Low #2 (SAL2) */ 1456 #define YUKON_SAL2 0x0028 /* SA2[15:0] */ 1457 1458 /* Source Address Middle #2 (SAM2) */ 1459 #define YUKON_SAM2 0x002c /* SA2[31:16] */ 1460 1461 /* Source Address High #2 (SAH2) */ 1462 #define YUKON_SAH2 0x0030 /* SA2[47:32] */ 1463 1464 /* Multicatst Address Hash Register 1 (MCAH1) */ 1465 #define YUKON_MCAH1 0x0034 1466 1467 /* Multicatst Address Hash Register 2 (MCAH2) */ 1468 #define YUKON_MCAH2 0x0038 1469 1470 /* Multicatst Address Hash Register 3 (MCAH3) */ 1471 #define YUKON_MCAH3 0x003c 1472 1473 /* Multicatst Address Hash Register 4 (MCAH4) */ 1474 #define YUKON_MCAH4 0x0040 1475 1476 /* Transmit Interrupt Register (TIR) */ 1477 #define YUKON_TIR 0x0044 1478 1479 #define YU_TIR_OUT_UNICAST 0x0001 /* Num Unicast Packets Transmitted */ 1480 #define YU_TIR_OUT_BROADCAST 0x0002 /* Num Broadcast Packets Transmitted */ 1481 #define YU_TIR_OUT_PAUSE 0x0004 /* Num Pause Packets Transmitted */ 1482 #define YU_TIR_OUT_MULTICAST 0x0008 /* Num Multicast Packets Transmitted */ 1483 #define YU_TIR_OUT_OCTETS 0x0030 /* Num Bytes Transmitted */ 1484 #define YU_TIR_OUT_64_OCTETS 0x0000 /* Num Packets Transmitted */ 1485 #define YU_TIR_OUT_127_OCTETS 0x0000 /* Num Packets Transmitted */ 1486 #define YU_TIR_OUT_255_OCTETS 0x0000 /* Num Packets Transmitted */ 1487 #define YU_TIR_OUT_511_OCTETS 0x0000 /* Num Packets Transmitted */ 1488 #define YU_TIR_OUT_1023_OCTETS 0x0000 /* Num Packets Transmitted */ 1489 #define YU_TIR_OUT_1518_OCTETS 0x0000 /* Num Packets Transmitted */ 1490 #define YU_TIR_OUT_MAX_OCTETS 0x0000 /* Num Packets Transmitted */ 1491 #define YU_TIR_OUT_SPARE 0x0000 /* Num Packets Transmitted */ 1492 #define YU_TIR_OUT_COLLISIONS 0x0000 /* Num Packets Transmitted */ 1493 #define YU_TIR_OUT_LATE 0x0000 /* Num Packets Transmitted */ 1494 1495 /* Receive Interrupt Register (RIR) */ 1496 #define YUKON_RIR 0x0048 1497 1498 /* Transmit and Receive Interrupt Register (TRIR) */ 1499 #define YUKON_TRIR 0x004c 1500 1501 /* Transmit Interrupt Mask Register (TIMR) */ 1502 #define YUKON_TIMR 0x0050 1503 1504 /* Receive Interrupt Mask Register (RIMR) */ 1505 #define YUKON_RIMR 0x0054 1506 1507 /* Transmit and Receive Interrupt Mask Register (TRIMR) */ 1508 #define YUKON_TRIMR 0x0058 1509 1510 /* SMI Control Register (SMICR) */ 1511 #define YUKON_SMICR 0x0080 1512 1513 #define YU_SMICR_PHYAD(x) (((x) & 0x1f) << 11) 1514 #define YU_SMICR_REGAD(x) (((x) & 0x1f) << 6) 1515 #define YU_SMICR_OPCODE 0x0020 /* opcode (0 - write, 1 - read) */ 1516 #define YU_SMICR_OP_READ 0x0020 /* opcode read */ 1517 #define YU_SMICR_OP_WRITE 0x0000 /* opcode write */ 1518 #define YU_SMICR_READ_VALID 0x0010 /* read valid */ 1519 #define YU_SMICR_BUSY 0x0008 /* busy (writing) */ 1520 1521 /* SMI Data Register (SMIDR) */ 1522 #define YUKON_SMIDR 0x0084 1523 1524 /* PHY Addres Register (PAR) */ 1525 #define YUKON_PAR 0x0088 1526 1527 #define YU_PAR_MIB_CLR 0x0020 /* MIB Counters Clear Mode */ 1528 #define YU_PAR_LOAD_TSTCNT 0x0010 /* Load count 0xfffffff0 into cntr */ 1529 1530 /* 1531 * Registers and data structures for the XaQti Corporation XMAC II 1532 * Gigabit Ethernet MAC. Datasheet is available from http://www.xaqti.com. 1533 * The XMAC can be programmed for 16-bit or 32-bit register access modes. 1534 * The SysKonnect gigabit ethernet adapters use 16-bit mode, so that's 1535 * how the registers are laid out here. 1536 */ 1537 1538 #define XM_DEVICEID 0x00E0AE20 1539 #define XM_XAQTI_OUI 0x00E0AE 1540 1541 #define XM_XMAC_REV(x) (((x) & 0x000000E0) >> 5) 1542 1543 #define XM_XMAC_REV_B2 0x0 1544 #define XM_XMAC_REV_C1 0x1 1545 1546 #define XM_MMUCMD 0x0000 1547 #define XM_POFF 0x0008 1548 #define XM_BURST 0x000C 1549 #define XM_VLAN_TAGLEV1 0x0010 1550 #define XM_VLAN_TAGLEV2 0x0014 1551 #define XM_TXCMD 0x0020 1552 #define XM_TX_RETRYLIMIT 0x0024 1553 #define XM_TX_SLOTTIME 0x0028 1554 #define XM_TX_IPG 0x003C 1555 #define XM_RXCMD 0x0030 1556 #define XM_PHY_ADDR 0x0034 1557 #define XM_PHY_DATA 0x0038 1558 #define XM_GPIO 0x0040 1559 #define XM_IMR 0x0044 1560 #define XM_ISR 0x0048 1561 #define XM_HWCFG 0x004C 1562 #define XM_TX_LOWAT 0x0060 1563 #define XM_TX_HIWAT 0x0062 1564 #define XM_TX_REQTHRESH_LO 0x0064 1565 #define XM_TX_REQTHRESH_HI 0x0066 1566 #define XM_TX_REQTHRESH XM_TX_REQTHRESH_LO 1567 #define XM_PAUSEDST0 0x0068 1568 #define XM_PAUSEDST1 0x006A 1569 #define XM_PAUSEDST2 0x006C 1570 #define XM_CTLPARM_LO 0x0070 1571 #define XM_CTLPARM_HI 0x0072 1572 #define XM_CTLPARM XM_CTLPARM_LO 1573 #define XM_OPCODE_PAUSE_TIMER 0x0074 1574 #define XM_TXSTAT_LIFO 0x0078 1575 1576 /* 1577 * Perfect filter registers. The XMAC has a table of 16 perfect 1578 * filter entries, spaced 8 bytes apart. This is in addition to 1579 * the station address registers, which appear below. 1580 */ 1581 #define XM_RXFILT_BASE 0x0080 1582 #define XM_RXFILT_END 0x0107 1583 #define XM_RXFILT_MAX 16 1584 #define XM_RXFILT_ENTRY(ent) (XM_RXFILT_BASE + ((ent * 8))) 1585 1586 /* Primary station address. */ 1587 #define XM_PAR0 0x0108 1588 #define XM_PAR1 0x010A 1589 #define XM_PAR2 0x010C 1590 1591 /* 64-bit multicast hash table registers */ 1592 #define XM_MAR0 0x0110 1593 #define XM_MAR1 0x0112 1594 #define XM_MAR2 0x0114 1595 #define XM_MAR3 0x0116 1596 #define XM_RX_LOWAT 0x0118 1597 #define XM_RX_HIWAT 0x011A 1598 #define XM_RX_REQTHRESH_LO 0x011C 1599 #define XM_RX_REQTHRESH_HI 0x011E 1600 #define XM_RX_REQTHRESH XM_RX_REQTHRESH_LO 1601 #define XM_DEVID_LO 0x0120 1602 #define XM_DEVID_HI 0x0122 1603 #define XM_DEVID XM_DEVID_LO 1604 #define XM_MODE_LO 0x0124 1605 #define XM_MODE_HI 0x0126 1606 #define XM_MODE XM_MODE_LO 1607 #define XM_LASTSRC0 0x0128 1608 #define XM_LASTSRC1 0x012A 1609 #define XM_LASTSRC2 0x012C 1610 #define XM_TSTAMP_READ 0x0130 1611 #define XM_TSTAMP_LOAD 0x0134 1612 #define XM_STATS_CMD 0x0200 1613 #define XM_RXCNT_EVENT_LO 0x0204 1614 #define XM_RXCNT_EVENT_HI 0x0206 1615 #define XM_RXCNT_EVENT XM_RXCNT_EVENT_LO 1616 #define XM_TXCNT_EVENT_LO 0x0208 1617 #define XM_TXCNT_EVENT_HI 0x020A 1618 #define XM_TXCNT_EVENT XM_TXCNT_EVENT_LO 1619 #define XM_RXCNT_EVMASK_LO 0x020C 1620 #define XM_RXCNT_EVMASK_HI 0x020E 1621 #define XM_RXCNT_EVMASK XM_RXCNT_EVMASK_LO 1622 #define XM_TXCNT_EVMASK_LO 0x0210 1623 #define XM_TXCNT_EVMASK_HI 0x0212 1624 #define XM_TXCNT_EVMASK XM_TXCNT_EVMASK_LO 1625 1626 /* Statistics command register */ 1627 #define XM_STATCMD_CLR_TX 0x0001 1628 #define XM_STATCMD_CLR_RX 0x0002 1629 #define XM_STATCMD_COPY_TX 0x0004 1630 #define XM_STATCMD_COPY_RX 0x0008 1631 #define XM_STATCMD_SNAP_TX 0x0010 1632 #define XM_STATCMD_SNAP_RX 0x0020 1633 1634 /* TX statistics registers */ 1635 #define XM_TXSTATS_PKTSOK 0x280 1636 #define XM_TXSTATS_BYTESOK_HI 0x284 1637 #define XM_TXSTATS_BYTESOK_LO 0x288 1638 #define XM_TXSTATS_BCASTSOK 0x28C 1639 #define XM_TXSTATS_MCASTSOK 0x290 1640 #define XM_TXSTATS_UCASTSOK 0x294 1641 #define XM_TXSTATS_GIANTS 0x298 1642 #define XM_TXSTATS_BURSTCNT 0x29C 1643 #define XM_TXSTATS_PAUSEPKTS 0x2A0 1644 #define XM_TXSTATS_MACCTLPKTS 0x2A4 1645 #define XM_TXSTATS_SINGLECOLS 0x2A8 1646 #define XM_TXSTATS_MULTICOLS 0x2AC 1647 #define XM_TXSTATS_EXCESSCOLS 0x2B0 1648 #define XM_TXSTATS_LATECOLS 0x2B4 1649 #define XM_TXSTATS_DEFER 0x2B8 1650 #define XM_TXSTATS_EXCESSDEFER 0x2BC 1651 #define XM_TXSTATS_UNDERRUN 0x2C0 1652 #define XM_TXSTATS_CARRIERSENSE 0x2C4 1653 #define XM_TXSTATS_UTILIZATION 0x2C8 1654 #define XM_TXSTATS_64 0x2D0 1655 #define XM_TXSTATS_65_127 0x2D4 1656 #define XM_TXSTATS_128_255 0x2D8 1657 #define XM_TXSTATS_256_511 0x2DC 1658 #define XM_TXSTATS_512_1023 0x2E0 1659 #define XM_TXSTATS_1024_MAX 0x2E4 1660 1661 /* RX statistics registers */ 1662 #define XM_RXSTATS_PKTSOK 0x300 1663 #define XM_RXSTATS_BYTESOK_HI 0x304 1664 #define XM_RXSTATS_BYTESOK_LO 0x308 1665 #define XM_RXSTATS_BCASTSOK 0x30C 1666 #define XM_RXSTATS_MCASTSOK 0x310 1667 #define XM_RXSTATS_UCASTSOK 0x314 1668 #define XM_RXSTATS_PAUSEPKTS 0x318 1669 #define XM_RXSTATS_MACCTLPKTS 0x31C 1670 #define XM_RXSTATS_BADPAUSEPKTS 0x320 1671 #define XM_RXSTATS_BADMACCTLPKTS 0x324 1672 #define XM_RXSTATS_BURSTCNT 0x328 1673 #define XM_RXSTATS_MISSEDPKTS 0x32C 1674 #define XM_RXSTATS_FRAMEERRS 0x330 1675 #define XM_RXSTATS_OVERRUN 0x334 1676 #define XM_RXSTATS_JABBER 0x338 1677 #define XM_RXSTATS_CARRLOSS 0x33C 1678 #define XM_RXSTATS_INRNGLENERR 0x340 1679 #define XM_RXSTATS_SYMERR 0x344 1680 #define XM_RXSTATS_SHORTEVENT 0x348 1681 #define XM_RXSTATS_RUNTS 0x34C 1682 #define XM_RXSTATS_GIANTS 0x350 1683 #define XM_RXSTATS_CRCERRS 0x354 1684 #define XM_RXSTATS_CEXTERRS 0x35C 1685 #define XM_RXSTATS_UTILIZATION 0x360 1686 #define XM_RXSTATS_64 0x368 1687 #define XM_RXSTATS_65_127 0x36C 1688 #define XM_RXSTATS_128_255 0x370 1689 #define XM_RXSTATS_256_511 0x374 1690 #define XM_RXSTATS_512_1023 0x378 1691 #define XM_RXSTATS_1024_MAX 0x37C 1692 1693 #define XM_MMUCMD_TX_ENB 0x0001 1694 #define XM_MMUCMD_RX_ENB 0x0002 1695 #define XM_MMUCMD_GMIILOOP 0x0004 1696 #define XM_MMUCMD_RATECTL 0x0008 1697 #define XM_MMUCMD_GMIIFDX 0x0010 1698 #define XM_MMUCMD_NO_MGMT_PRMB 0x0020 1699 #define XM_MMUCMD_SIMCOL 0x0040 1700 #define XM_MMUCMD_FORCETX 0x0080 1701 #define XM_MMUCMD_LOOPENB 0x0200 1702 #define XM_MMUCMD_IGNPAUSE 0x0400 1703 #define XM_MMUCMD_PHYBUSY 0x0800 1704 #define XM_MMUCMD_PHYDATARDY 0x1000 1705 1706 #define XM_TXCMD_AUTOPAD 0x0001 1707 #define XM_TXCMD_NOCRC 0x0002 1708 #define XM_TXCMD_NOPREAMBLE 0x0004 1709 #define XM_TXCMD_NOGIGAMODE 0x0008 1710 #define XM_TXCMD_SAMPLELINE 0x0010 1711 #define XM_TXCMD_ENCBYPASS 0x0020 1712 #define XM_TXCMD_XMITBK2BK 0x0040 1713 #define XM_TXCMD_FAIRSHARE 0x0080 1714 1715 #define XM_RXCMD_DISABLE_CEXT 0x0001 1716 #define XM_RXCMD_STRIPPAD 0x0002 1717 #define XM_RXCMD_SAMPLELINE 0x0004 1718 #define XM_RXCMD_SELFRX 0x0008 1719 #define XM_RXCMD_STRIPFCS 0x0010 1720 #define XM_RXCMD_TRANSPARENT 0x0020 1721 #define XM_RXCMD_IPGCAPTURE 0x0040 1722 #define XM_RXCMD_BIGPKTOK 0x0080 1723 #define XM_RXCMD_LENERROK 0x0100 1724 1725 #define XM_GPIO_GP0_SET 0x0001 1726 #define XM_GPIO_RESETSTATS 0x0004 1727 #define XM_GPIO_RESETMAC 0x0008 1728 #define XM_GPIO_FORCEINT 0x0020 1729 #define XM_GPIO_ANEGINPROG 0x0040 1730 1731 #define XM_IMR_RX_EOF 0x0001 1732 #define XM_IMR_TX_EOF 0x0002 1733 #define XM_IMR_TX_UNDERRUN 0x0004 1734 #define XM_IMR_RX_OVERRUN 0x0008 1735 #define XM_IMR_TX_STATS_OFLOW 0x0010 1736 #define XM_IMR_RX_STATS_OFLOW 0x0020 1737 #define XM_IMR_TSTAMP_OFLOW 0x0040 1738 #define XM_IMR_AUTONEG_DONE 0x0080 1739 #define XM_IMR_NEXTPAGE_RDY 0x0100 1740 #define XM_IMR_PAGE_RECEIVED 0x0200 1741 #define XM_IMR_LP_REQCFG 0x0400 1742 #define XM_IMR_GP0_SET 0x0800 1743 #define XM_IMR_FORCEINTR 0x1000 1744 #define XM_IMR_TX_ABORT 0x2000 1745 #define XM_IMR_LINKEVENT 0x4000 1746 1747 #define XM_INTRS \ 1748 (~(XM_IMR_GP0_SET|XM_IMR_AUTONEG_DONE|XM_IMR_TX_UNDERRUN)) 1749 1750 #define XM_ISR_RX_EOF 0x0001 1751 #define XM_ISR_TX_EOF 0x0002 1752 #define XM_ISR_TX_UNDERRUN 0x0004 1753 #define XM_ISR_RX_OVERRUN 0x0008 1754 #define XM_ISR_TX_STATS_OFLOW 0x0010 1755 #define XM_ISR_RX_STATS_OFLOW 0x0020 1756 #define XM_ISR_TSTAMP_OFLOW 0x0040 1757 #define XM_ISR_AUTONEG_DONE 0x0080 1758 #define XM_ISR_NEXTPAGE_RDY 0x0100 1759 #define XM_ISR_PAGE_RECEIVED 0x0200 1760 #define XM_ISR_LP_REQCFG 0x0400 1761 #define XM_ISR_GP0_SET 0x0800 1762 #define XM_ISR_FORCEINTR 0x1000 1763 #define XM_ISR_TX_ABORT 0x2000 1764 #define XM_ISR_LINKEVENT 0x4000 1765 1766 #define XM_HWCFG_GENEOP 0x0008 1767 #define XM_HWCFG_SIGSTATCKH 0x0004 1768 #define XM_HWCFG_GMIIMODE 0x0001 1769 1770 #define XM_MODE_FLUSH_RXFIFO 0x00000001 1771 #define XM_MODE_FLUSH_TXFIFO 0x00000002 1772 #define XM_MODE_BIGENDIAN 0x00000004 1773 #define XM_MODE_RX_PROMISC 0x00000008 1774 #define XM_MODE_RX_NOBROAD 0x00000010 1775 #define XM_MODE_RX_NOMULTI 0x00000020 1776 #define XM_MODE_RX_NOUNI 0x00000040 1777 #define XM_MODE_RX_BADFRAMES 0x00000080 1778 #define XM_MODE_RX_CRCERRS 0x00000100 1779 #define XM_MODE_RX_GIANTS 0x00000200 1780 #define XM_MODE_RX_INRANGELEN 0x00000400 1781 #define XM_MODE_RX_RUNTS 0x00000800 1782 #define XM_MODE_RX_MACCTL 0x00001000 1783 #define XM_MODE_RX_USE_PERFECT 0x00002000 1784 #define XM_MODE_RX_USE_STATION 0x00004000 1785 #define XM_MODE_RX_USE_HASH 0x00008000 1786 #define XM_MODE_RX_ADDRPAIR 0x00010000 1787 #define XM_MODE_PAUSEONHI 0x00020000 1788 #define XM_MODE_PAUSEONLO 0x00040000 1789 #define XM_MODE_TIMESTAMP 0x00080000 1790 #define XM_MODE_SENDPAUSE 0x00100000 1791 #define XM_MODE_SENDCONTINUOUS 0x00200000 1792 #define XM_MODE_LE_STATUSWORD 0x00400000 1793 #define XM_MODE_AUTOFIFOPAUSE 0x00800000 1794 #define XM_MODE_EXPAUSEGEN 0x02000000 1795 #define XM_MODE_RX_INVERSE 0x04000000 1796 1797 #define XM_RXSTAT_MACCTL 0x00000001 1798 #define XM_RXSTAT_ERRFRAME 0x00000002 1799 #define XM_RXSTAT_CRCERR 0x00000004 1800 #define XM_RXSTAT_GIANT 0x00000008 1801 #define XM_RXSTAT_RUNT 0x00000010 1802 #define XM_RXSTAT_FRAMEERR 0x00000020 1803 #define XM_RXSTAT_INRANGEERR 0x00000040 1804 #define XM_RXSTAT_CARRIERERR 0x00000080 1805 #define XM_RXSTAT_COLLERR 0x00000100 1806 #define XM_RXSTAT_802_3 0x00000200 1807 #define XM_RXSTAT_CARREXTERR 0x00000400 1808 #define XM_RXSTAT_BURSTMODE 0x00000800 1809 #define XM_RXSTAT_UNICAST 0x00002000 1810 #define XM_RXSTAT_MULTICAST 0x00004000 1811 #define XM_RXSTAT_BROADCAST 0x00008000 1812 #define XM_RXSTAT_VLAN_LEV1 0x00010000 1813 #define XM_RXSTAT_VLAN_LEV2 0x00020000 1814 #define XM_RXSTAT_LEN 0xFFFC0000 1815 1816 /* 1817 * XMAC PHY registers, indirectly accessed through 1818 * XM_PHY_ADDR and XM_PHY_REG. 1819 */ 1820 1821 #define XM_PHY_BMCR 0x0000 /* control */ 1822 #define XM_PHY_BMSR 0x0001 /* status */ 1823 #define XM_PHY_VENID 0x0002 /* vendor id */ 1824 #define XM_PHY_DEVID 0x0003 /* device id */ 1825 #define XM_PHY_ANAR 0x0004 /* autoneg advertisenemt */ 1826 #define XM_PHY_LPAR 0x0005 /* link partner ability */ 1827 #define XM_PHY_ANEXP 0x0006 /* autoneg expansion */ 1828 #define XM_PHY_NEXTP 0x0007 /* nextpage */ 1829 #define XM_PHY_LPNEXTP 0x0008 /* link partner's nextpage */ 1830 #define XM_PHY_EXTSTS 0x000F /* extented status */ 1831 #define XM_PHY_RESAB 0x0010 /* resolved ability */ 1832 1833 #define XM_BMCR_DUPLEX 0x0100 1834 #define XM_BMCR_RENEGOTIATE 0x0200 1835 #define XM_BMCR_AUTONEGENBL 0x1000 1836 #define XM_BMCR_LOOPBACK 0x4000 1837 #define XM_BMCR_RESET 0x8000 1838 1839 #define XM_BMSR_EXTCAP 0x0001 1840 #define XM_BMSR_LINKSTAT 0x0004 1841 #define XM_BMSR_AUTONEGABLE 0x0008 1842 #define XM_BMSR_REMFAULT 0x0010 1843 #define XM_BMSR_AUTONEGDONE 0x0020 1844 #define XM_BMSR_EXTSTAT 0x0100 1845 1846 #define XM_VENID_XAQTI 0xD14C 1847 #define XM_DEVID_XMAC 0x0002 1848 1849 #define XM_ANAR_FULLDUPLEX 0x0020 1850 #define XM_ANAR_HALFDUPLEX 0x0040 1851 #define XM_ANAR_PAUSEBITS 0x0180 1852 #define XM_ANAR_REMFAULTBITS 0x1800 1853 #define XM_ANAR_ACK 0x4000 1854 #define XM_ANAR_NEXTPAGE 0x8000 1855 1856 #define XM_LPAR_FULLDUPLEX 0x0020 1857 #define XM_LPAR_HALFDUPLEX 0x0040 1858 #define XM_LPAR_PAUSEBITS 0x0180 1859 #define XM_LPAR_REMFAULTBITS 0x1800 1860 #define XM_LPAR_ACK 0x4000 1861 #define XM_LPAR_NEXTPAGE 0x8000 1862 1863 #define XM_PAUSE_NOPAUSE 0x0000 1864 #define XM_PAUSE_SYMPAUSE 0x0080 1865 #define XM_PAUSE_ASYMPAUSE 0x0100 1866 #define XM_PAUSE_BOTH 0x0180 1867 1868 #define XM_REMFAULT_LINKOK 0x0000 1869 #define XM_REMFAULT_LINKFAIL 0x0800 1870 #define XM_REMFAULT_OFFLINE 0x1000 1871 #define XM_REMFAULT_ANEGERR 0x1800 1872 1873 #define XM_ANEXP_GOTPAGE 0x0002 1874 #define XM_ANEXP_NEXTPAGE_SELF 0x0004 1875 #define XM_ANEXP_NEXTPAGE_LP 0x0008 1876 1877 #define XM_NEXTP_MESSAGE 0x07FF 1878 #define XM_NEXTP_TOGGLE 0x0800 1879 #define XM_NEXTP_ACK2 0x1000 1880 #define XM_NEXTP_MPAGE 0x2000 1881 #define XM_NEXTP_ACK1 0x4000 1882 #define XM_NEXTP_NPAGE 0x8000 1883 1884 #define XM_LPNEXTP_MESSAGE 0x07FF 1885 #define XM_LPNEXTP_TOGGLE 0x0800 1886 #define XM_LPNEXTP_ACK2 0x1000 1887 #define XM_LPNEXTP_MPAGE 0x2000 1888 #define XM_LPNEXTP_ACK1 0x4000 1889 #define XM_LPNEXTP_NPAGE 0x8000 1890 1891 #define XM_EXTSTS_HALFDUPLEX 0x4000 1892 #define XM_EXTSTS_FULLDUPLEX 0x8000 1893 1894 #define XM_RESAB_PAUSEMISMATCH 0x0008 1895 #define XM_RESAB_ABLMISMATCH 0x0010 1896 #define XM_RESAB_FDMODESEL 0x0020 1897 #define XM_RESAB_HDMODESEL 0x0040 1898 #define XM_RESAB_PAUSEBITS 0x0180 1899 #endif /* _DEV_PCI_IF_SKREG_H_ */ 1900
Indexes created Sat Sep 27 14:09:57 GMT 2025