if_skreg.h revision 1.2
1 /* $NetBSD: if_skreg.h,v 1.2 2003/08/26 21:14:08 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 /* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */ 36 /* $OpenBSD: yukonreg.h,v 1.2 2003/08/12 05:23:06 nate Exp $ */ 37 /* $OpenBSD: xmaciireg.h,v 1.2.4.1 2001/05/14 22:26:01 niklas Exp $ */ 38 39 /* 40 * Copyright (c) 1997, 1998, 1999, 2000 41 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Bill Paul. 54 * 4. Neither the name of the author nor the names of any co-contributors 55 * may be used to endorse or promote products derived from this software 56 * without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 59 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 61 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 62 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 63 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 64 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 65 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 66 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 67 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 68 * THE POSSIBILITY OF SUCH DAMAGE. 69 * 70 * $FreeBSD: /c/ncvs/src/sys/pci/if_skreg.h,v 1.9 2000/04/22 02:16:37 wpaul Exp $ 71 * $FreeBSD: /c/ncvs/src/sys/pci/xmaciireg.h,v 1.3 2000/04/22 02:16:37 wpaul Exp $ 72 */ 73 74 /* 75 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 76 * 77 * Permission to use, copy, modify, and distribute this software for any 78 * purpose with or without fee is hereby granted, provided that the above 79 * copyright notice and this permission notice appear in all copies. 80 * 81 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 82 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 83 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 84 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 85 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 86 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 87 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 88 */ 89 90 #ifndef _DEV_PCI_IF_SKREG_H_ 91 #define _DEV_PCI_IF_SKREG_H_ 92 93 #include <net/if.h> 94 #include <net/if_ether.h> 95 #include <net/if_media.h> 96 97 /* Values to keep the different chip revisions apart */ 98 #define SK_GENESIS 0 99 #define SK_YUKON 1 100 101 /* 102 * GEnesis registers. The GEnesis chip has a 256-byte I/O window 103 * but internally it has a 16K register space. This 16K space is 104 * divided into 128-byte blocks. The first 128 bytes of the I/O 105 * window represent the first block, which is permanently mapped 106 * at the start of the window. The other 127 blocks can be mapped 107 * to the second 128 bytes of the I/O window by setting the desired 108 * block value in the RAP register in block 0. Not all of the 127 109 * blocks are actually used. Most registers are 32 bits wide, but 110 * there are a few 16-bit and 8-bit ones as well. 111 */ 112 113 114 /* Start of remappable register window. */ 115 #define SK_WIN_BASE 0x0080 116 117 /* Size of a window */ 118 #define SK_WIN_LEN 0x80 119 120 #define SK_WIN_MASK 0x3F80 121 #define SK_REG_MASK 0x7F 122 123 /* Compute the window of a given register (for the RAP register) */ 124 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) 125 126 /* Compute the relative offset of a register within the window */ 127 #define SK_REG(reg) ((reg) & SK_REG_MASK) 128 129 #define SK_PORT_A 0 130 #define SK_PORT_B 1 131 132 /* 133 * Compute offset of port-specific register. Since there are two 134 * ports, there are two of some GEnesis modules (e.g. two sets of 135 * DMA queues, two sets of FIFO control registers, etc...). Normally, 136 * the block for port 0 is at offset 0x0 and the block for port 1 is 137 * at offset 0x80 (i.e. the next page over). However for the transmit 138 * BMUs and RAMbuffers, there are two blocks for each port: one for 139 * the sync transmit queue and one for the async queue (which we don't 140 * use). However instead of ordering them like this: 141 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2 142 * SysKonnect has instead ordered them like this: 143 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2 144 * This means that when referencing the TX BMU and RAMbuffer registers, 145 * we have to double the block offset (0x80 * 2) in order to reach the 146 * second queue. This prevents us from using the same formula 147 * (sk_port * 0x80) to compute the offsets for all of the port-specific 148 * blocks: we need an extra offset for the BMU and RAMbuffer registers. 149 * The simplest thing is to provide an extra argument to these macros: 150 * the 'skip' parameter. The 'skip' value is the number of extra pages 151 * for skip when computing the port0/port1 offsets. For most registers, 152 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1. 153 */ 154 #define SK_IF_READ_4(sc_if, skip, reg) \ 155 sk_win_read_4(sc_if->sk_softc, reg + \ 156 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 157 #define SK_IF_READ_2(sc_if, skip, reg) \ 158 sk_win_read_2(sc_if->sk_softc, reg + \ 159 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 160 #define SK_IF_READ_1(sc_if, skip, reg) \ 161 sk_win_read_1(sc_if->sk_softc, reg + \ 162 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN)) 163 164 #define SK_IF_WRITE_4(sc_if, skip, reg, val) \ 165 sk_win_write_4(sc_if->sk_softc, \ 166 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 167 #define SK_IF_WRITE_2(sc_if, skip, reg, val) \ 168 sk_win_write_2(sc_if->sk_softc, \ 169 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 170 #define SK_IF_WRITE_1(sc_if, skip, reg, val) \ 171 sk_win_write_1(sc_if->sk_softc, \ 172 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val) 173 174 /* Block 0 registers, permanently mapped at iobase. */ 175 #define SK_RAP 0x0000 176 #define SK_CSR 0x0004 177 #define SK_LED 0x0006 178 #define SK_ISR 0x0008 /* interrupt source */ 179 #define SK_IMR 0x000C /* interrupt mask */ 180 #define SK_IESR 0x0010 /* interrupt hardware error source */ 181 #define SK_IEMR 0x0014 /* interrupt hardware error mask */ 182 #define SK_ISSR 0x0018 /* special interrupt source */ 183 #define SK_XM_IMR0 0x0020 184 #define SK_XM_ISR0 0x0028 185 #define SK_XM_PHYADDR0 0x0030 186 #define SK_XM_PHYDATA0 0x0034 187 #define SK_XM_IMR1 0x0040 188 #define SK_XM_ISR1 0x0048 189 #define SK_XM_PHYADDR1 0x0050 190 #define SK_XM_PHYDATA1 0x0054 191 #define SK_BMU_RX_CSR0 0x0060 192 #define SK_BMU_RX_CSR1 0x0064 193 #define SK_BMU_TXS_CSR0 0x0068 194 #define SK_BMU_TXA_CSR0 0x006C 195 #define SK_BMU_TXS_CSR1 0x0070 196 #define SK_BMU_TXA_CSR1 0x0074 197 198 /* SK_CSR register */ 199 #define SK_CSR_SW_RESET 0x0001 200 #define SK_CSR_SW_UNRESET 0x0002 201 #define SK_CSR_MASTER_RESET 0x0004 202 #define SK_CSR_MASTER_UNRESET 0x0008 203 #define SK_CSR_MASTER_STOP 0x0010 204 #define SK_CSR_MASTER_DONE 0x0020 205 #define SK_CSR_SW_IRQ_CLEAR 0x0040 206 #define SK_CSR_SW_IRQ_SET 0x0080 207 #define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */ 208 #define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 MHz, = 33 */ 209 210 /* SK_LED register */ 211 #define SK_LED_GREEN_OFF 0x01 212 #define SK_LED_GREEN_ON 0x02 213 214 /* SK_ISR register */ 215 #define SK_ISR_TX2_AS_CHECK 0x00000001 216 #define SK_ISR_TX2_AS_EOF 0x00000002 217 #define SK_ISR_TX2_AS_EOB 0x00000004 218 #define SK_ISR_TX2_S_CHECK 0x00000008 219 #define SK_ISR_TX2_S_EOF 0x00000010 220 #define SK_ISR_TX2_S_EOB 0x00000020 221 #define SK_ISR_TX1_AS_CHECK 0x00000040 222 #define SK_ISR_TX1_AS_EOF 0x00000080 223 #define SK_ISR_TX1_AS_EOB 0x00000100 224 #define SK_ISR_TX1_S_CHECK 0x00000200 225 #define SK_ISR_TX1_S_EOF 0x00000400 226 #define SK_ISR_TX1_S_EOB 0x00000800 227 #define SK_ISR_RX2_CHECK 0x00001000 228 #define SK_ISR_RX2_EOF 0x00002000 229 #define SK_ISR_RX2_EOB 0x00004000 230 #define SK_ISR_RX1_CHECK 0x00008000 231 #define SK_ISR_RX1_EOF 0x00010000 232 #define SK_ISR_RX1_EOB 0x00020000 233 #define SK_ISR_LINK2_OFLOW 0x00040000 234 #define SK_ISR_MAC2 0x00080000 235 #define SK_ISR_LINK1_OFLOW 0x00100000 236 #define SK_ISR_MAC1 0x00200000 237 #define SK_ISR_TIMER 0x00400000 238 #define SK_ISR_EXTERNAL_REG 0x00800000 239 #define SK_ISR_SW 0x01000000 240 #define SK_ISR_I2C_RDY 0x02000000 241 #define SK_ISR_TX2_TIMEO 0x04000000 242 #define SK_ISR_TX1_TIMEO 0x08000000 243 #define SK_ISR_RX2_TIMEO 0x10000000 244 #define SK_ISR_RX1_TIMEO 0x20000000 245 #define SK_ISR_RSVD 0x40000000 246 #define SK_ISR_HWERR 0x80000000 247 248 /* SK_IMR register */ 249 #define SK_IMR_TX2_AS_CHECK 0x00000001 250 #define SK_IMR_TX2_AS_EOF 0x00000002 251 #define SK_IMR_TX2_AS_EOB 0x00000004 252 #define SK_IMR_TX2_S_CHECK 0x00000008 253 #define SK_IMR_TX2_S_EOF 0x00000010 254 #define SK_IMR_TX2_S_EOB 0x00000020 255 #define SK_IMR_TX1_AS_CHECK 0x00000040 256 #define SK_IMR_TX1_AS_EOF 0x00000080 257 #define SK_IMR_TX1_AS_EOB 0x00000100 258 #define SK_IMR_TX1_S_CHECK 0x00000200 259 #define SK_IMR_TX1_S_EOF 0x00000400 260 #define SK_IMR_TX1_S_EOB 0x00000800 261 #define SK_IMR_RX2_CHECK 0x00001000 262 #define SK_IMR_RX2_EOF 0x00002000 263 #define SK_IMR_RX2_EOB 0x00004000 264 #define SK_IMR_RX1_CHECK 0x00008000 265 #define SK_IMR_RX1_EOF 0x00010000 266 #define SK_IMR_RX1_EOB 0x00020000 267 #define SK_IMR_LINK2_OFLOW 0x00040000 268 #define SK_IMR_MAC2 0x00080000 269 #define SK_IMR_LINK1_OFLOW 0x00100000 270 #define SK_IMR_MAC1 0x00200000 271 #define SK_IMR_TIMER 0x00400000 272 #define SK_IMR_EXTERNAL_REG 0x00800000 273 #define SK_IMR_SW 0x01000000 274 #define SK_IMR_I2C_RDY 0x02000000 275 #define SK_IMR_TX2_TIMEO 0x04000000 276 #define SK_IMR_TX1_TIMEO 0x08000000 277 #define SK_IMR_RX2_TIMEO 0x10000000 278 #define SK_IMR_RX1_TIMEO 0x20000000 279 #define SK_IMR_RSVD 0x40000000 280 #define SK_IMR_HWERR 0x80000000 281 282 #define SK_INTRS1 \ 283 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1) 284 285 #define SK_INTRS2 \ 286 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2) 287 288 /* SK_IESR register */ 289 #define SK_IESR_PAR_RX2 0x00000001 290 #define SK_IESR_PAR_RX1 0x00000002 291 #define SK_IESR_PAR_MAC2 0x00000004 292 #define SK_IESR_PAR_MAC1 0x00000008 293 #define SK_IESR_PAR_WR_RAM 0x00000010 294 #define SK_IESR_PAR_RD_RAM 0x00000020 295 #define SK_IESR_NO_TSTAMP_MAC2 0x00000040 296 #define SK_IESR_NO_TSTAMO_MAC1 0x00000080 297 #define SK_IESR_NO_STS_MAC2 0x00000100 298 #define SK_IESR_NO_STS_MAC1 0x00000200 299 #define SK_IESR_IRQ_STS 0x00000400 300 #define SK_IESR_MASTERERR 0x00000800 301 302 /* SK_IEMR register */ 303 #define SK_IEMR_PAR_RX2 0x00000001 304 #define SK_IEMR_PAR_RX1 0x00000002 305 #define SK_IEMR_PAR_MAC2 0x00000004 306 #define SK_IEMR_PAR_MAC1 0x00000008 307 #define SK_IEMR_PAR_WR_RAM 0x00000010 308 #define SK_IEMR_PAR_RD_RAM 0x00000020 309 #define SK_IEMR_NO_TSTAMP_MAC2 0x00000040 310 #define SK_IEMR_NO_TSTAMO_MAC1 0x00000080 311 #define SK_IEMR_NO_STS_MAC2 0x00000100 312 #define SK_IEMR_NO_STS_MAC1 0x00000200 313 #define SK_IEMR_IRQ_STS 0x00000400 314 #define SK_IEMR_MASTERERR 0x00000800 315 316 /* Block 2 */ 317 #define SK_MAC0_0 0x0100 318 #define SK_MAC0_1 0x0104 319 #define SK_MAC1_0 0x0108 320 #define SK_MAC1_1 0x010C 321 #define SK_MAC2_0 0x0110 322 #define SK_MAC2_1 0x0114 323 #define SK_CONNTYPE 0x0118 324 #define SK_PMDTYPE 0x0119 325 #define SK_CONFIG 0x011A 326 #define SK_CHIPVER 0x011B 327 #define SK_EPROM0 0x011C 328 #define SK_EPROM1 0x011D 329 #define SK_EPROM2 0x011E 330 #define SK_EPROM3 0x011F 331 #define SK_EP_ADDR 0x0120 332 #define SK_EP_DATA 0x0124 333 #define SK_EP_LOADCTL 0x0128 334 #define SK_EP_LOADTST 0x0129 335 #define SK_TIMERINIT 0x0130 336 #define SK_TIMER 0x0134 337 #define SK_TIMERCTL 0x0138 338 #define SK_TIMERTST 0x0139 339 #define SK_IMTIMERINIT 0x0140 340 #define SK_IMTIMER 0x0144 341 #define SK_IMTIMERCTL 0x0148 342 #define SK_IMTIMERTST 0x0149 343 #define SK_IMMR 0x014C 344 #define SK_IHWEMR 0x0150 345 #define SK_TESTCTL1 0x0158 346 #define SK_TESTCTL2 0x0159 347 #define SK_GPIO 0x015C 348 #define SK_I2CHWCTL 0x0160 349 #define SK_I2CHWDATA 0x0164 350 #define SK_I2CHWIRQ 0x0168 351 #define SK_I2CSW 0x016C 352 #define SK_BLNKINIT 0x0170 353 #define SK_BLNKCOUNT 0x0174 354 #define SK_BLNKCTL 0x0178 355 #define SK_BLNKSTS 0x0179 356 #define SK_BLNKTST 0x017A 357 358 #define SK_IMCTL_STOP 0x02 359 #define SK_IMCTL_START 0x04 360 361 #define SK_IMTIMER_TICKS 54 362 #define SK_IM_USECS(x) ((x) * SK_IMTIMER_TICKS) 363 364 /* 365 * The SK_EPROM0 register contains a byte that describes the 366 * amount of SRAM mounted on the NIC. The value also tells if 367 * the chips are 64K or 128K. This affects the RAMbuffer address 368 * offset that we need to use. 369 */ 370 #define SK_RAMSIZE_512K_64 0x1 371 #define SK_RAMSIZE_1024K_128 0x2 372 #define SK_RAMSIZE_1024K_64 0x3 373 #define SK_RAMSIZE_2048K_128 0x4 374 375 #define SK_RBOFF_0 0x0 376 #define SK_RBOFF_80000 0x80000 377 378 /* 379 * SK_EEPROM1 contains the PHY type, which may be XMAC for 380 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom 381 * PHY. 382 */ 383 #define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */ 384 #define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */ 385 #define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */ 386 #define SK_PHYTYPE_NAT 3 /* National DP83891 */ 387 #define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */ 388 #define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */ 389 390 /* 391 * PHY addresses. 392 */ 393 #define SK_PHYADDR_XMAC 0x0 394 #define SK_PHYADDR_BCOM 0x1 395 #define SK_PHYADDR_LONE 0x3 396 #define SK_PHYADDR_NAT 0x0 397 #define SK_PHYADDR_MARV 0x0 398 399 #define SK_CONFIG_SINGLEMAC 0x01 400 #define SK_CONFIG_DIS_DSL_CLK 0x02 401 402 #define SK_PMD_1000BASELX 0x4C 403 #define SK_PMD_1000BASESX 0x53 404 #define SK_PMD_1000BASECX 0x43 405 #define SK_PMD_1000BASETX 0x54 406 407 /* GPIO bits */ 408 #define SK_GPIO_DAT0 0x00000001 409 #define SK_GPIO_DAT1 0x00000002 410 #define SK_GPIO_DAT2 0x00000004 411 #define SK_GPIO_DAT3 0x00000008 412 #define SK_GPIO_DAT4 0x00000010 413 #define SK_GPIO_DAT5 0x00000020 414 #define SK_GPIO_DAT6 0x00000040 415 #define SK_GPIO_DAT7 0x00000080 416 #define SK_GPIO_DAT8 0x00000100 417 #define SK_GPIO_DAT9 0x00000200 418 #define SK_GPIO_DIR0 0x00010000 419 #define SK_GPIO_DIR1 0x00020000 420 #define SK_GPIO_DIR2 0x00040000 421 #define SK_GPIO_DIR3 0x00080000 422 #define SK_GPIO_DIR4 0x00100000 423 #define SK_GPIO_DIR5 0x00200000 424 #define SK_GPIO_DIR6 0x00400000 425 #define SK_GPIO_DIR7 0x00800000 426 #define SK_GPIO_DIR8 0x01000000 427 #define SK_GPIO_DIR9 0x02000000 428 429 /* Block 3 Ram interface and MAC arbiter registers */ 430 #define SK_RAMADDR 0x0180 431 #define SK_RAMDATA0 0x0184 432 #define SK_RAMDATA1 0x0188 433 #define SK_TO0 0x0190 434 #define SK_TO1 0x0191 435 #define SK_TO2 0x0192 436 #define SK_TO3 0x0193 437 #define SK_TO4 0x0194 438 #define SK_TO5 0x0195 439 #define SK_TO6 0x0196 440 #define SK_TO7 0x0197 441 #define SK_TO8 0x0198 442 #define SK_TO9 0x0199 443 #define SK_TO10 0x019A 444 #define SK_TO11 0x019B 445 #define SK_RITIMEO_TMR 0x019C 446 #define SK_RAMCTL 0x01A0 447 #define SK_RITIMER_TST 0x01A2 448 449 #define SK_RAMCTL_RESET 0x0001 450 #define SK_RAMCTL_UNRESET 0x0002 451 #define SK_RAMCTL_CLR_IRQ_WPAR 0x0100 452 #define SK_RAMCTL_CLR_IRQ_RPAR 0x0200 453 454 /* Mac arbiter registers */ 455 #define SK_MINIT_RX1 0x01B0 456 #define SK_MINIT_RX2 0x01B1 457 #define SK_MINIT_TX1 0x01B2 458 #define SK_MINIT_TX2 0x01B3 459 #define SK_MTIMEO_RX1 0x01B4 460 #define SK_MTIMEO_RX2 0x01B5 461 #define SK_MTIMEO_TX1 0x01B6 462 #define SK_MTIEMO_TX2 0x01B7 463 #define SK_MACARB_CTL 0x01B8 464 #define SK_MTIMER_TST 0x01BA 465 #define SK_RCINIT_RX1 0x01C0 466 #define SK_RCINIT_RX2 0x01C1 467 #define SK_RCINIT_TX1 0x01C2 468 #define SK_RCINIT_TX2 0x01C3 469 #define SK_RCTIMEO_RX1 0x01C4 470 #define SK_RCTIMEO_RX2 0x01C5 471 #define SK_RCTIMEO_TX1 0x01C6 472 #define SK_RCTIMEO_TX2 0x01C7 473 #define SK_RECOVERY_CTL 0x01C8 474 #define SK_RCTIMER_TST 0x01CA 475 476 /* Packet arbiter registers */ 477 #define SK_RXPA1_TINIT 0x01D0 478 #define SK_RXPA2_TINIT 0x01D4 479 #define SK_TXPA1_TINIT 0x01D8 480 #define SK_TXPA2_TINIT 0x01DC 481 #define SK_RXPA1_TIMEO 0x01E0 482 #define SK_RXPA2_TIMEO 0x01E4 483 #define SK_TXPA1_TIMEO 0x01E8 484 #define SK_TXPA2_TIMEO 0x01EC 485 #define SK_PKTARB_CTL 0x01F0 486 #define SK_PKTATB_TST 0x01F2 487 488 #define SK_PKTARB_TIMEOUT 0x2000 489 490 #define SK_PKTARBCTL_RESET 0x0001 491 #define SK_PKTARBCTL_UNRESET 0x0002 492 #define SK_PKTARBCTL_RXTO1_OFF 0x0004 493 #define SK_PKTARBCTL_RXTO1_ON 0x0008 494 #define SK_PKTARBCTL_RXTO2_OFF 0x0010 495 #define SK_PKTARBCTL_RXTO2_ON 0x0020 496 #define SK_PKTARBCTL_TXTO1_OFF 0x0040 497 #define SK_PKTARBCTL_TXTO1_ON 0x0080 498 #define SK_PKTARBCTL_TXTO2_OFF 0x0100 499 #define SK_PKTARBCTL_TXTO2_ON 0x0200 500 #define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400 501 #define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800 502 #define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000 503 #define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000 504 505 #define SK_MINIT_XMAC_B2 54 506 #define SK_MINIT_XMAC_C1 63 507 508 #define SK_MACARBCTL_RESET 0x0001 509 #define SK_MACARBCTL_UNRESET 0x0002 510 #define SK_MACARBCTL_FASTOE_OFF 0x0004 511 #define SK_MACARBCRL_FASTOE_ON 0x0008 512 513 #define SK_RCINIT_XMAC_B2 54 514 #define SK_RCINIT_XMAC_C1 0 515 516 #define SK_RECOVERYCTL_RX1_OFF 0x0001 517 #define SK_RECOVERYCTL_RX1_ON 0x0002 518 #define SK_RECOVERYCTL_RX2_OFF 0x0004 519 #define SK_RECOVERYCTL_RX2_ON 0x0008 520 #define SK_RECOVERYCTL_TX1_OFF 0x0010 521 #define SK_RECOVERYCTL_TX1_ON 0x0020 522 #define SK_RECOVERYCTL_TX2_OFF 0x0040 523 #define SK_RECOVERYCTL_TX2_ON 0x0080 524 525 #define SK_RECOVERY_XMAC_B2 \ 526 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \ 527 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON) 528 529 #define SK_RECOVERY_XMAC_C1 \ 530 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \ 531 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF) 532 533 /* Block 4 -- TX Arbiter MAC 1 */ 534 #define SK_TXAR1_TIMERINIT 0x0200 535 #define SK_TXAR1_TIMERVAL 0x0204 536 #define SK_TXAR1_LIMITINIT 0x0208 537 #define SK_TXAR1_LIMITCNT 0x020C 538 #define SK_TXAR1_COUNTERCTL 0x0210 539 #define SK_TXAR1_COUNTERTST 0x0212 540 #define SK_TXAR1_COUNTERSTS 0x0212 541 542 /* Block 5 -- TX Arbiter MAC 2 */ 543 #define SK_TXAR2_TIMERINIT 0x0280 544 #define SK_TXAR2_TIMERVAL 0x0284 545 #define SK_TXAR2_LIMITINIT 0x0288 546 #define SK_TXAR2_LIMITCNT 0x028C 547 #define SK_TXAR2_COUNTERCTL 0x0290 548 #define SK_TXAR2_COUNTERTST 0x0291 549 #define SK_TXAR2_COUNTERSTS 0x0292 550 551 #define SK_TXARCTL_OFF 0x01 552 #define SK_TXARCTL_ON 0x02 553 #define SK_TXARCTL_RATECTL_OFF 0x04 554 #define SK_TXARCTL_RATECTL_ON 0x08 555 #define SK_TXARCTL_ALLOC_OFF 0x10 556 #define SK_TXARCTL_ALLOC_ON 0x20 557 #define SK_TXARCTL_FSYNC_OFF 0x40 558 #define SK_TXARCTL_FSYNC_ON 0x80 559 560 /* Block 6 -- External registers */ 561 #define SK_EXTREG_BASE 0x300 562 #define SK_EXTREG_END 0x37C 563 564 /* Block 7 -- PCI config registers */ 565 #define SK_PCI_BASE 0x0380 566 #define SK_PCI_END 0x03FC 567 568 /* Compute offset of mirrored PCI register */ 569 #define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) 570 571 /* Block 8 -- RX queue 1 */ 572 #define SK_RXQ1_BUFCNT 0x0400 573 #define SK_RXQ1_BUFCTL 0x0402 574 #define SK_RXQ1_NEXTDESC 0x0404 575 #define SK_RXQ1_RXBUF_LO 0x0408 576 #define SK_RXQ1_RXBUF_HI 0x040C 577 #define SK_RXQ1_RXSTAT 0x0410 578 #define SK_RXQ1_TIMESTAMP 0x0414 579 #define SK_RXQ1_CSUM1 0x0418 580 #define SK_RXQ1_CSUM2 0x041A 581 #define SK_RXQ1_CSUM1_START 0x041C 582 #define SK_RXQ1_CSUM2_START 0x041E 583 #define SK_RXQ1_CURADDR_LO 0x0420 584 #define SK_RXQ1_CURADDR_HI 0x0424 585 #define SK_RXQ1_CURCNT_LO 0x0428 586 #define SK_RXQ1_CURCNT_HI 0x042C 587 #define SK_RXQ1_CURBYTES 0x0430 588 #define SK_RXQ1_BMU_CSR 0x0434 589 #define SK_RXQ1_WATERMARK 0x0438 590 #define SK_RXQ1_FLAG 0x043A 591 #define SK_RXQ1_TEST1 0x043C 592 #define SK_RXQ1_TEST2 0x0440 593 #define SK_RXQ1_TEST3 0x0444 594 595 /* Block 9 -- RX queue 2 */ 596 #define SK_RXQ2_BUFCNT 0x0480 597 #define SK_RXQ2_BUFCTL 0x0482 598 #define SK_RXQ2_NEXTDESC 0x0484 599 #define SK_RXQ2_RXBUF_LO 0x0488 600 #define SK_RXQ2_RXBUF_HI 0x048C 601 #define SK_RXQ2_RXSTAT 0x0490 602 #define SK_RXQ2_TIMESTAMP 0x0494 603 #define SK_RXQ2_CSUM1 0x0498 604 #define SK_RXQ2_CSUM2 0x049A 605 #define SK_RXQ2_CSUM1_START 0x049C 606 #define SK_RXQ2_CSUM2_START 0x049E 607 #define SK_RXQ2_CURADDR_LO 0x04A0 608 #define SK_RXQ2_CURADDR_HI 0x04A4 609 #define SK_RXQ2_CURCNT_LO 0x04A8 610 #define SK_RXQ2_CURCNT_HI 0x04AC 611 #define SK_RXQ2_CURBYTES 0x04B0 612 #define SK_RXQ2_BMU_CSR 0x04B4 613 #define SK_RXQ2_WATERMARK 0x04B8 614 #define SK_RXQ2_FLAG 0x04BA 615 #define SK_RXQ2_TEST1 0x04BC 616 #define SK_RXQ2_TEST2 0x04C0 617 #define SK_RXQ2_TEST3 0x04C4 618 619 #define SK_RXBMU_CLR_IRQ_ERR 0x00000001 620 #define SK_RXBMU_CLR_IRQ_EOF 0x00000002 621 #define SK_RXBMU_CLR_IRQ_EOB 0x00000004 622 #define SK_RXBMU_CLR_IRQ_PAR 0x00000008 623 #define SK_RXBMU_RX_START 0x00000010 624 #define SK_RXBMU_RX_STOP 0x00000020 625 #define SK_RXBMU_POLL_OFF 0x00000040 626 #define SK_RXBMU_POLL_ON 0x00000080 627 #define SK_RXBMU_TRANSFER_SM_RESET 0x00000100 628 #define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200 629 #define SK_RXBMU_DESCWR_SM_RESET 0x00000400 630 #define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800 631 #define SK_RXBMU_DESCRD_SM_RESET 0x00001000 632 #define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000 633 #define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000 634 #define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 635 #define SK_RXBMU_PFI_SM_RESET 0x00010000 636 #define SK_RXBMU_PFI_SM_UNRESET 0x00020000 637 #define SK_RXBMU_FIFO_RESET 0x00040000 638 #define SK_RXBMU_FIFO_UNRESET 0x00080000 639 #define SK_RXBMU_DESC_RESET 0x00100000 640 #define SK_RXBMU_DESC_UNRESET 0x00200000 641 #define SK_RXBMU_SUPERVISOR_IDLE 0x01000000 642 643 #define SK_RXBMU_ONLINE \ 644 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \ 645 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \ 646 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \ 647 SK_RXBMU_DESC_UNRESET) 648 649 #define SK_RXBMU_OFFLINE \ 650 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \ 651 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \ 652 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \ 653 SK_RXBMU_DESC_RESET) 654 655 /* Block 12 -- TX sync queue 1 */ 656 #define SK_TXQS1_BUFCNT 0x0600 657 #define SK_TXQS1_BUFCTL 0x0602 658 #define SK_TXQS1_NEXTDESC 0x0604 659 #define SK_TXQS1_RXBUF_LO 0x0608 660 #define SK_TXQS1_RXBUF_HI 0x060C 661 #define SK_TXQS1_RXSTAT 0x0610 662 #define SK_TXQS1_CSUM_STARTVAL 0x0614 663 #define SK_TXQS1_CSUM_STARTPOS 0x0618 664 #define SK_TXQS1_CSUM_WRITEPOS 0x061A 665 #define SK_TXQS1_CURADDR_LO 0x0620 666 #define SK_TXQS1_CURADDR_HI 0x0624 667 #define SK_TXQS1_CURCNT_LO 0x0628 668 #define SK_TXQS1_CURCNT_HI 0x062C 669 #define SK_TXQS1_CURBYTES 0x0630 670 #define SK_TXQS1_BMU_CSR 0x0634 671 #define SK_TXQS1_WATERMARK 0x0638 672 #define SK_TXQS1_FLAG 0x063A 673 #define SK_TXQS1_TEST1 0x063C 674 #define SK_TXQS1_TEST2 0x0640 675 #define SK_TXQS1_TEST3 0x0644 676 677 /* Block 13 -- TX async queue 1 */ 678 #define SK_TXQA1_BUFCNT 0x0680 679 #define SK_TXQA1_BUFCTL 0x0682 680 #define SK_TXQA1_NEXTDESC 0x0684 681 #define SK_TXQA1_RXBUF_LO 0x0688 682 #define SK_TXQA1_RXBUF_HI 0x068C 683 #define SK_TXQA1_RXSTAT 0x0690 684 #define SK_TXQA1_CSUM_STARTVAL 0x0694 685 #define SK_TXQA1_CSUM_STARTPOS 0x0698 686 #define SK_TXQA1_CSUM_WRITEPOS 0x069A 687 #define SK_TXQA1_CURADDR_LO 0x06A0 688 #define SK_TXQA1_CURADDR_HI 0x06A4 689 #define SK_TXQA1_CURCNT_LO 0x06A8 690 #define SK_TXQA1_CURCNT_HI 0x06AC 691 #define SK_TXQA1_CURBYTES 0x06B0 692 #define SK_TXQA1_BMU_CSR 0x06B4 693 #define SK_TXQA1_WATERMARK 0x06B8 694 #define SK_TXQA1_FLAG 0x06BA 695 #define SK_TXQA1_TEST1 0x06BC 696 #define SK_TXQA1_TEST2 0x06C0 697 #define SK_TXQA1_TEST3 0x06C4 698 699 /* Block 14 -- TX sync queue 2 */ 700 #define SK_TXQS2_BUFCNT 0x0700 701 #define SK_TXQS2_BUFCTL 0x0702 702 #define SK_TXQS2_NEXTDESC 0x0704 703 #define SK_TXQS2_RXBUF_LO 0x0708 704 #define SK_TXQS2_RXBUF_HI 0x070C 705 #define SK_TXQS2_RXSTAT 0x0710 706 #define SK_TXQS2_CSUM_STARTVAL 0x0714 707 #define SK_TXQS2_CSUM_STARTPOS 0x0718 708 #define SK_TXQS2_CSUM_WRITEPOS 0x071A 709 #define SK_TXQS2_CURADDR_LO 0x0720 710 #define SK_TXQS2_CURADDR_HI 0x0724 711 #define SK_TXQS2_CURCNT_LO 0x0728 712 #define SK_TXQS2_CURCNT_HI 0x072C 713 #define SK_TXQS2_CURBYTES 0x0730 714 #define SK_TXQS2_BMU_CSR 0x0734 715 #define SK_TXQS2_WATERMARK 0x0738 716 #define SK_TXQS2_FLAG 0x073A 717 #define SK_TXQS2_TEST1 0x073C 718 #define SK_TXQS2_TEST2 0x0740 719 #define SK_TXQS2_TEST3 0x0744 720 721 /* Block 15 -- TX async queue 2 */ 722 #define SK_TXQA2_BUFCNT 0x0780 723 #define SK_TXQA2_BUFCTL 0x0782 724 #define SK_TXQA2_NEXTDESC 0x0784 725 #define SK_TXQA2_RXBUF_LO 0x0788 726 #define SK_TXQA2_RXBUF_HI 0x078C 727 #define SK_TXQA2_RXSTAT 0x0790 728 #define SK_TXQA2_CSUM_STARTVAL 0x0794 729 #define SK_TXQA2_CSUM_STARTPOS 0x0798 730 #define SK_TXQA2_CSUM_WRITEPOS 0x079A 731 #define SK_TXQA2_CURADDR_LO 0x07A0 732 #define SK_TXQA2_CURADDR_HI 0x07A4 733 #define SK_TXQA2_CURCNT_LO 0x07A8 734 #define SK_TXQA2_CURCNT_HI 0x07AC 735 #define SK_TXQA2_CURBYTES 0x07B0 736 #define SK_TXQA2_BMU_CSR 0x07B4 737 #define SK_TXQA2_WATERMARK 0x07B8 738 #define SK_TXQA2_FLAG 0x07BA 739 #define SK_TXQA2_TEST1 0x07BC 740 #define SK_TXQA2_TEST2 0x07C0 741 #define SK_TXQA2_TEST3 0x07C4 742 743 #define SK_TXBMU_CLR_IRQ_ERR 0x00000001 744 #define SK_TXBMU_CLR_IRQ_EOF 0x00000002 745 #define SK_TXBMU_CLR_IRQ_EOB 0x00000004 746 #define SK_TXBMU_TX_START 0x00000010 747 #define SK_TXBMU_TX_STOP 0x00000020 748 #define SK_TXBMU_POLL_OFF 0x00000040 749 #define SK_TXBMU_POLL_ON 0x00000080 750 #define SK_TXBMU_TRANSFER_SM_RESET 0x00000100 751 #define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200 752 #define SK_TXBMU_DESCWR_SM_RESET 0x00000400 753 #define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800 754 #define SK_TXBMU_DESCRD_SM_RESET 0x00001000 755 #define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000 756 #define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000 757 #define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 758 #define SK_TXBMU_PFI_SM_RESET 0x00010000 759 #define SK_TXBMU_PFI_SM_UNRESET 0x00020000 760 #define SK_TXBMU_FIFO_RESET 0x00040000 761 #define SK_TXBMU_FIFO_UNRESET 0x00080000 762 #define SK_TXBMU_DESC_RESET 0x00100000 763 #define SK_TXBMU_DESC_UNRESET 0x00200000 764 #define SK_TXBMU_SUPERVISOR_IDLE 0x01000000 765 766 #define SK_TXBMU_ONLINE \ 767 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \ 768 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \ 769 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \ 770 SK_TXBMU_DESC_UNRESET) 771 772 #define SK_TXBMU_OFFLINE \ 773 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \ 774 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \ 775 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \ 776 SK_TXBMU_DESC_RESET) 777 778 /* Block 16 -- Receive RAMbuffer 1 */ 779 #define SK_RXRB1_START 0x0800 780 #define SK_RXRB1_END 0x0804 781 #define SK_RXRB1_WR_PTR 0x0808 782 #define SK_RXRB1_RD_PTR 0x080C 783 #define SK_RXRB1_UTHR_PAUSE 0x0810 784 #define SK_RXRB1_LTHR_PAUSE 0x0814 785 #define SK_RXRB1_UTHR_HIPRIO 0x0818 786 #define SK_RXRB1_UTHR_LOPRIO 0x081C 787 #define SK_RXRB1_PKTCNT 0x0820 788 #define SK_RXRB1_LVL 0x0824 789 #define SK_RXRB1_CTLTST 0x0828 790 791 /* Block 17 -- Receive RAMbuffer 2 */ 792 #define SK_RXRB2_START 0x0880 793 #define SK_RXRB2_END 0x0884 794 #define SK_RXRB2_WR_PTR 0x0888 795 #define SK_RXRB2_RD_PTR 0x088C 796 #define SK_RXRB2_UTHR_PAUSE 0x0890 797 #define SK_RXRB2_LTHR_PAUSE 0x0894 798 #define SK_RXRB2_UTHR_HIPRIO 0x0898 799 #define SK_RXRB2_UTHR_LOPRIO 0x089C 800 #define SK_RXRB2_PKTCNT 0x08A0 801 #define SK_RXRB2_LVL 0x08A4 802 #define SK_RXRB2_CTLTST 0x08A8 803 804 /* Block 20 -- Sync. Transmit RAMbuffer 1 */ 805 #define SK_TXRBS1_START 0x0A00 806 #define SK_TXRBS1_END 0x0A04 807 #define SK_TXRBS1_WR_PTR 0x0A08 808 #define SK_TXRBS1_RD_PTR 0x0A0C 809 #define SK_TXRBS1_PKTCNT 0x0A20 810 #define SK_TXRBS1_LVL 0x0A24 811 #define SK_TXRBS1_CTLTST 0x0A28 812 813 /* Block 21 -- Async. Transmit RAMbuffer 1 */ 814 #define SK_TXRBA1_START 0x0A80 815 #define SK_TXRBA1_END 0x0A84 816 #define SK_TXRBA1_WR_PTR 0x0A88 817 #define SK_TXRBA1_RD_PTR 0x0A8C 818 #define SK_TXRBA1_PKTCNT 0x0AA0 819 #define SK_TXRBA1_LVL 0x0AA4 820 #define SK_TXRBA1_CTLTST 0x0AA8 821 822 /* Block 22 -- Sync. Transmit RAMbuffer 2 */ 823 #define SK_TXRBS2_START 0x0B00 824 #define SK_TXRBS2_END 0x0B04 825 #define SK_TXRBS2_WR_PTR 0x0B08 826 #define SK_TXRBS2_RD_PTR 0x0B0C 827 #define SK_TXRBS2_PKTCNT 0x0B20 828 #define SK_TXRBS2_LVL 0x0B24 829 #define SK_TXRBS2_CTLTST 0x0B28 830 831 /* Block 23 -- Async. Transmit RAMbuffer 2 */ 832 #define SK_TXRBA2_START 0x0B80 833 #define SK_TXRBA2_END 0x0B84 834 #define SK_TXRBA2_WR_PTR 0x0B88 835 #define SK_TXRBA2_RD_PTR 0x0B8C 836 #define SK_TXRBA2_PKTCNT 0x0BA0 837 #define SK_TXRBA2_LVL 0x0BA4 838 #define SK_TXRBA2_CTLTST 0x0BA8 839 840 #define SK_RBCTL_RESET 0x00000001 841 #define SK_RBCTL_UNRESET 0x00000002 842 #define SK_RBCTL_OFF 0x00000004 843 #define SK_RBCTL_ON 0x00000008 844 #define SK_RBCTL_STORENFWD_OFF 0x00000010 845 #define SK_RBCTL_STORENFWD_ON 0x00000020 846 847 /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */ 848 #define SK_RXF1_END 0x0C00 849 #define SK_RXF1_WPTR 0x0C04 850 #define SK_RXF1_RPTR 0x0C0C 851 #define SK_RXF1_PKTCNT 0x0C10 852 #define SK_RXF1_LVL 0x0C14 853 #define SK_RXF1_MACCTL 0x0C18 854 #define SK_RXF1_CTL 0x0C1C 855 #define SK_RXLED1_CNTINIT 0x0C20 856 #define SK_RXLED1_COUNTER 0x0C24 857 #define SK_RXLED1_CTL 0x0C28 858 #define SK_RXLED1_TST 0x0C29 859 #define SK_LINK_SYNC1_CINIT 0x0C30 860 #define SK_LINK_SYNC1_COUNTER 0x0C34 861 #define SK_LINK_SYNC1_CTL 0x0C38 862 #define SK_LINK_SYNC1_TST 0x0C39 863 #define SK_LINKLED1_CTL 0x0C3C 864 865 #define SK_FIFO_END 0x3F 866 867 /* Receive MAC FIFO 1 (Yukon Only) */ 868 #define SK_RXMF1_END 0x0C40 869 #define SK_RXMF1_THRESHOLD 0x0C44 870 #define SK_RXMF1_CTRL_TEST 0x0C48 871 #define SK_RXMF1_WRITE_PTR 0x0C60 872 #define SK_RXMF1_WRITE_LEVEL 0x0C68 873 #define SK_RXMF1_READ_PTR 0x0C70 874 #define SK_RXMF1_READ_LEVEL 0x0C78 875 876 #define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 877 #define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 878 #define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 879 #define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 880 #define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 881 #define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 882 #define SK_RFCTL_RX_FIFO_OVER 0x00000040 /* Clear IRQ RX FIFO Overrun */ 883 #define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */ 884 #define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 885 #define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 886 #define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 887 #define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 888 889 890 /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */ 891 #define SK_RXF2_END 0x0C80 892 #define SK_RXF2_WPTR 0x0C84 893 #define SK_RXF2_RPTR 0x0C8C 894 #define SK_RXF2_PKTCNT 0x0C90 895 #define SK_RXF2_LVL 0x0C94 896 #define SK_RXF2_MACCTL 0x0C98 897 #define SK_RXF2_CTL 0x0C9C 898 #define SK_RXLED2_CNTINIT 0x0CA0 899 #define SK_RXLED2_COUNTER 0x0CA4 900 #define SK_RXLED2_CTL 0x0CA8 901 #define SK_RXLED2_TST 0x0CA9 902 #define SK_LINK_SYNC2_CINIT 0x0CB0 903 #define SK_LINK_SYNC2_COUNTER 0x0CB4 904 #define SK_LINK_SYNC2_CTL 0x0CB8 905 #define SK_LINK_SYNC2_TST 0x0CB9 906 #define SK_LINKLED2_CTL 0x0CBC 907 908 #define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001 909 #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002 910 #define SK_RXMACCTL_TSTAMP_OFF 0x00000004 911 #define SK_RXMACCTL_RSTAMP_ON 0x00000008 912 #define SK_RXMACCTL_FLUSH_OFF 0x00000010 913 #define SK_RXMACCTL_FLUSH_ON 0x00000020 914 #define SK_RXMACCTL_PAUSE_OFF 0x00000040 915 #define SK_RXMACCTL_PAUSE_ON 0x00000080 916 #define SK_RXMACCTL_AFULL_OFF 0x00000100 917 #define SK_RXMACCTL_AFULL_ON 0x00000200 918 #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400 919 #define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800 920 #define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000 921 #define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000 922 #define SK_RXMACCTL_STS_TIMEO 0x00FF0000 923 #define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000 924 925 #define SK_RXLEDCTL_ENABLE 0x0001 926 #define SK_RXLEDCTL_COUNTER_STOP 0x0002 927 #define SK_RXLEDCTL_COUNTER_START 0x0004 928 929 #define SK_LINKLED_OFF 0x0001 930 #define SK_LINKLED_ON 0x0002 931 #define SK_LINKLED_LINKSYNC_OFF 0x0004 932 #define SK_LINKLED_LINKSYNC_ON 0x0008 933 #define SK_LINKLED_BLINK_OFF 0x0010 934 #define SK_LINKLED_BLINK_ON 0x0020 935 936 /* Block 26 -- TX MAC FIFO 1 regisrers */ 937 #define SK_TXF1_END 0x0D00 938 #define SK_TXF1_WPTR 0x0D04 939 #define SK_TXF1_RPTR 0x0D0C 940 #define SK_TXF1_PKTCNT 0x0D10 941 #define SK_TXF1_LVL 0x0D14 942 #define SK_TXF1_MACCTL 0x0D18 943 #define SK_TXF1_CTL 0x0D1C 944 #define SK_TXLED1_CNTINIT 0x0D20 945 #define SK_TXLED1_COUNTER 0x0D24 946 #define SK_TXLED1_CTL 0x0D28 947 #define SK_TXLED1_TST 0x0D29 948 949 /* Receive MAC FIFO 1 (Yukon Only) */ 950 #define SK_TXMF1_END 0x0D40 951 #define SK_TXMF1_THRESHOLD 0x0D44 952 #define SK_TXMF1_CTRL_TEST 0x0D48 953 #define SK_TXMF1_WRITE_PTR 0x0D60 954 #define SK_TXMF1_WRITE_SHADOW 0x0D64 955 #define SK_TXMF1_WRITE_LEVEL 0x0D68 956 #define SK_TXMF1_READ_PTR 0x0D70 957 #define SK_TXMF1_RESTART_PTR 0x0D74 958 #define SK_TXMF1_READ_LEVEL 0x0D78 959 960 #define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/ 961 #define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */ 962 #define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */ 963 #define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */ 964 #define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */ 965 #define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */ 966 #define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */ 967 #define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */ 968 #define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */ 969 #define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */ 970 #define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */ 971 #define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */ 972 #define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */ 973 974 /* Block 27 -- TX MAC FIFO 2 regisrers */ 975 #define SK_TXF2_END 0x0D80 976 #define SK_TXF2_WPTR 0x0D84 977 #define SK_TXF2_RPTR 0x0D8C 978 #define SK_TXF2_PKTCNT 0x0D90 979 #define SK_TXF2_LVL 0x0D94 980 #define SK_TXF2_MACCTL 0x0D98 981 #define SK_TXF2_CTL 0x0D9C 982 #define SK_TXLED2_CNTINIT 0x0DA0 983 #define SK_TXLED2_COUNTER 0x0DA4 984 #define SK_TXLED2_CTL 0x0DA8 985 #define SK_TXLED2_TST 0x0DA9 986 987 #define SK_TXMACCTL_XMAC_RESET 0x00000001 988 #define SK_TXMACCTL_XMAC_UNRESET 0x00000002 989 #define SK_TXMACCTL_LOOP_OFF 0x00000004 990 #define SK_TXMACCTL_LOOP_ON 0x00000008 991 #define SK_TXMACCTL_FLUSH_OFF 0x00000010 992 #define SK_TXMACCTL_FLUSH_ON 0x00000020 993 #define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040 994 #define SK_TXMACCTL_WAITEMPTY_ON 0x00000080 995 #define SK_TXMACCTL_AFULL_OFF 0x00000100 996 #define SK_TXMACCTL_AFULL_ON 0x00000200 997 #define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400 998 #define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800 999 #define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000 1000 #define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000 1001 #define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000 1002 #define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000 1003 1004 #define SK_TXLEDCTL_ENABLE 0x0001 1005 #define SK_TXLEDCTL_COUNTER_STOP 0x0002 1006 #define SK_TXLEDCTL_COUNTER_START 0x0004 1007 1008 #define SK_FIFO_RESET 0x00000001 1009 #define SK_FIFO_UNRESET 0x00000002 1010 #define SK_FIFO_OFF 0x00000004 1011 #define SK_FIFO_ON 0x00000008 1012 1013 /* Block 28 -- Descriptor Poll Timer */ 1014 #define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */ 1015 #define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */ 1016 1017 #define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */ 1018 #define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */ 1019 #define SK_DPT_TCTL_START 0x0002 /* Start Timer */ 1020 1021 #define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */ 1022 #define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */ 1023 #define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */ 1024 #define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */ 1025 1026 /* Block 29 -- reserved */ 1027 1028 /* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/ 1029 #define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */ 1030 #define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */ 1031 #define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */ 1032 #define SK_GMAC_IMR 0x0f08 /* GMAC Interrupt Mask Register */ 1033 #define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */ 1034 #define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */ 1035 #define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */ 1036 #define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */ 1037 #define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */ 1038 #define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */ 1039 #define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */ 1040 #define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */ 1041 #define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */ 1042 #define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */ 1043 #define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */ 1044 #define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */ 1045 #define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */ 1046 #define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */ 1047 #define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */ 1048 #define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */ 1049 #define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */ 1050 #define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */ 1051 #define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */ 1052 #define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */ 1053 #define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */ 1054 #define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */ 1055 #define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */ 1056 #define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */ 1057 #define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */ 1058 1059 #define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */ 1060 #define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */ 1061 #define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */ 1062 #define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */ 1063 #define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */ 1064 #define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */ 1065 1066 #define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */ 1067 #define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */ 1068 #define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */ 1069 #define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */ 1070 #define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */ 1071 #define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */ 1072 #define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */ 1073 #define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */ 1074 #define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */ 1075 #define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */ 1076 #define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */ 1077 #define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */ 1078 #define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */ 1079 #define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */ 1080 #define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */ 1081 #define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */ 1082 #define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */ 1083 #define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */ 1084 #define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */ 1085 #define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */ 1086 #define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */ 1087 #define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */ 1088 #define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */ 1089 1090 #define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1091 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 ) 1092 #define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \ 1093 SK_GPHY_HWCFG_M_2 ) 1094 #define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \ 1095 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 ) 1096 1097 #define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */ 1098 #define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */ 1099 #define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */ 1100 #define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */ 1101 #define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */ 1102 #define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */ 1103 1104 #define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */ 1105 #define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */ 1106 1107 /* Block 31 -- reserved */ 1108 1109 /* Block 32-33 -- Pattern Ram */ 1110 #define SK_WOL_PRAM 0x1000 1111 1112 /* Block 0x22 - 0x3f -- reserved */ 1113 1114 /* Block 0x40 to 0x4F -- XMAC 1 registers */ 1115 #define SK_XMAC1_BASE 0x2000 1116 1117 /* Block 0x50 to 0x5F -- MARV 1 registers */ 1118 #define SK_MARV1_BASE 0x2800 1119 1120 /* Block 0x60 to 0x6F -- XMAC 2 registers */ 1121 #define SK_XMAC2_BASE 0x3000 1122 1123 /* Block 0x70 to 0x7F -- MARV 2 registers */ 1124 #define SK_MARV2_BASE 0x3800 1125 1126 /* Compute relative offset of an XMAC register in the XMAC window(s). */ 1127 #define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \ 1128 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE))) 1129 1130 #if 0 1131 #define SK_XM_READ_4(sc, reg) \ 1132 ((sk_win_read_2(sc->sk_softc, \ 1133 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \ 1134 ((sk_win_read_2(sc->sk_softc, \ 1135 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16)) 1136 1137 #define SK_XM_WRITE_4(sc, reg, val) \ 1138 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \ 1139 ((val) & 0xFFFF)); \ 1140 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \ 1141 ((val) >> 16) & 0xFFFF) 1142 #else 1143 #define SK_XM_READ_4(sc, reg) \ 1144 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1145 1146 #define SK_XM_WRITE_4(sc, reg, val) \ 1147 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val)) 1148 #endif 1149 1150 #define SK_XM_READ_2(sc, reg) \ 1151 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg)) 1152 1153 #define SK_XM_WRITE_2(sc, reg, val) \ 1154 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val) 1155 1156 #define SK_XM_SETBIT_4(sc, reg, x) \ 1157 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1158 1159 #define SK_XM_CLRBIT_4(sc, reg, x) \ 1160 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1161 1162 #define SK_XM_SETBIT_2(sc, reg, x) \ 1163 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1164 1165 #define SK_XM_CLRBIT_2(sc, reg, x) \ 1166 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1167 1168 /* Compute relative offset of an MARV register in the MARV window(s). */ 1169 #define SK_YU_REG(sc, reg) \ 1170 ((reg) + SK_MARV1_BASE + \ 1171 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE))) 1172 1173 #define SK_YU_READ_4(sc, reg) \ 1174 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1175 1176 #define SK_YU_READ_2(sc, reg) \ 1177 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg))) 1178 1179 #define SK_YU_WRITE_4(sc, reg, val) \ 1180 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1181 1182 #define SK_YU_WRITE_2(sc, reg, val) \ 1183 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val)) 1184 1185 #define SK_YU_SETBIT_4(sc, reg, x) \ 1186 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1187 1188 #define SK_YU_CLRBIT_4(sc, reg, x) \ 1189 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1190 1191 #define SK_YU_SETBIT_2(sc, reg, x) \ 1192 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) 1193 1194 #define SK_YU_CLRBIT_2(sc, reg, x) \ 1195 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x)) 1196 1197 /* 1198 * The default FIFO threshold on the XMAC II is 4 bytes. On 1199 * dual port NICs, this often leads to transmit underruns, so we 1200 * bump the threshold a little. 1201 */ 1202 #define SK_XM_TX_FIFOTHRESH 512 1203 1204 #define SK_PCI_VENDOR_ID 0x0000 1205 #define SK_PCI_DEVICE_ID 0x0002 1206 #define SK_PCI_COMMAND 0x0004 1207 #define SK_PCI_STATUS 0x0006 1208 #define SK_PCI_REVID 0x0008 1209 #define SK_PCI_CLASSCODE 0x0009 1210 #define SK_PCI_CACHELEN 0x000C 1211 #define SK_PCI_LATENCY_TIMER 0x000D 1212 #define SK_PCI_HEADER_TYPE 0x000E 1213 #define SK_PCI_LOMEM 0x0010 1214 #define SK_PCI_LOIO 0x0014 1215 #define SK_PCI_SUBVEN_ID 0x002C 1216 #define SK_PCI_SYBSYS_ID 0x002E 1217 #define SK_PCI_BIOSROM 0x0030 1218 #define SK_PCI_INTLINE 0x003C 1219 #define SK_PCI_INTPIN 0x003D 1220 #define SK_PCI_MINGNT 0x003E 1221 #define SK_PCI_MINLAT 0x003F 1222 1223 /* device specific PCI registers */ 1224 #define SK_PCI_OURREG1 0x0040 1225 #define SK_PCI_OURREG2 0x0044 1226 #define SK_PCI_CAPID 0x0048 /* 8 bits */ 1227 #define SK_PCI_NEXTPTR 0x0049 /* 8 bits */ 1228 #define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */ 1229 #define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */ 1230 #define SK_PCI_PME_EVENT 0x004F 1231 #define SK_PCI_VPD_CAPID 0x0050 1232 #define SK_PCI_VPD_NEXTPTR 0x0051 1233 #define SK_PCI_VPD_ADDR 0x0052 1234 #define SK_PCI_VPD_DATA 0x0054 1235 1236 #define SK_PSTATE_MASK 0x0003 1237 #define SK_PSTATE_D0 0x0000 1238 #define SK_PSTATE_D1 0x0001 1239 #define SK_PSTATE_D2 0x0002 1240 #define SK_PSTATE_D3 0x0003 1241 #define SK_PME_EN 0x0010 1242 #define SK_PME_STATUS 0x8000 1243 1244 /* 1245 * VPD flag bit. Set to 0 to initiate a read, will become 1 when 1246 * read is complete. Set to 1 to initiate a write, will become 0 1247 * when write is finished. 1248 */ 1249 #define SK_VPD_FLAG 0x8000 1250 1251 /* VPD structures */ 1252 struct vpd_res { 1253 u_int8_t vr_id; 1254 u_int8_t vr_len; 1255 u_int8_t vr_pad; 1256 }; 1257 1258 struct vpd_key { 1259 char vk_key[2]; 1260 u_int8_t vk_len; 1261 }; 1262 1263 #define VPD_RES_ID 0x82 /* ID string */ 1264 #define VPD_RES_READ 0x90 /* start of read only area */ 1265 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 1266 #define VPD_RES_END 0x78 /* end tag */ 1267 1268 #define CSR_WRITE_4(sc, reg, val) \ 1269 bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1270 #define CSR_WRITE_2(sc, reg, val) \ 1271 bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1272 #define CSR_WRITE_1(sc, reg, val) \ 1273 bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val)) 1274 1275 #define CSR_READ_4(sc, reg) \ 1276 bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1277 #define CSR_READ_2(sc, reg) \ 1278 bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1279 #define CSR_READ_1(sc, reg) \ 1280 bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg)) 1281 1282 struct sk_type { 1283 u_int16_t sk_vid; 1284 u_int16_t sk_did; 1285 char *sk_name; 1286 }; 1287 1288 /* RX queue descriptor data structure */ 1289 struct sk_rx_desc { 1290 u_int32_t sk_ctl; 1291 u_int32_t sk_next; 1292 u_int32_t sk_data_lo; 1293 u_int32_t sk_data_hi; 1294 u_int32_t sk_xmac_rxstat; 1295 u_int32_t sk_timestamp; 1296 u_int16_t sk_csum2; 1297 u_int16_t sk_csum1; 1298 u_int16_t sk_csum2_start; 1299 u_int16_t sk_csum1_start; 1300 }; 1301 1302 #define SK_OPCODE_DEFAULT 0x00550000 1303 #define SK_OPCODE_CSUM 0x00560000 1304 1305 #define SK_RXCTL_LEN 0x0000FFFF 1306 #define SK_RXCTL_OPCODE 0x00FF0000 1307 #define SK_RXCTL_TSTAMP_VALID 0x01000000 1308 #define SK_RXCTL_STATUS_VALID 0x02000000 1309 #define SK_RXCTL_DEV0 0x04000000 1310 #define SK_RXCTL_EOF_INTR 0x08000000 1311 #define SK_RXCTL_EOB_INTR 0x10000000 1312 #define SK_RXCTL_LASTFRAG 0x20000000 1313 #define SK_RXCTL_FIRSTFRAG 0x40000000 1314 #define SK_RXCTL_OWN 0x80000000 1315 1316 #define SK_RXSTAT \ 1317 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \ 1318 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN) 1319 1320 struct sk_tx_desc { 1321 u_int32_t sk_ctl; 1322 u_int32_t sk_next; 1323 u_int32_t sk_data_lo; 1324 u_int32_t sk_data_hi; 1325 u_int32_t sk_xmac_txstat; 1326 u_int16_t sk_rsvd0; 1327 u_int16_t sk_csum_startval; 1328 u_int16_t sk_csum_startpos; 1329 u_int16_t sk_csum_writepos; 1330 u_int32_t sk_rsvd1; 1331 }; 1332 1333 #define SK_TXCTL_LEN 0x0000FFFF 1334 #define SK_TXCTL_OPCODE 0x00FF0000 1335 #define SK_TXCTL_SW 0x01000000 1336 #define SK_TXCTL_NOCRC 0x02000000 1337 #define SK_TXCTL_STORENFWD 0x04000000 1338 #define SK_TXCTL_EOF_INTR 0x08000000 1339 #define SK_TXCTL_EOB_INTR 0x10000000 1340 #define SK_TXCTL_LASTFRAG 0x20000000 1341 #define SK_TXCTL_FIRSTFRAG 0x40000000 1342 #define SK_TXCTL_OWN 0x80000000 1343 1344 #define SK_TXSTAT \ 1345 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN) 1346 1347 #define SK_RXBYTES(x) (x) & 0x0000FFFF; 1348 #define SK_TXBYTES SK_RXBYTES 1349 1350 #define SK_TX_RING_CNT 512 1351 #define SK_RX_RING_CNT 256 1352 1353 /* 1354 * Jumbo buffer stuff. Note that we must allocate more jumbo 1355 * buffers than there are descriptors in the receive ring. This 1356 * is because we don't know how long it will take for a packet 1357 * to be released after we hand it off to the upper protocol 1358 * layers. To be safe, we allocate 1.5 times the number of 1359 * receive descriptors. 1360 */ 1361 #define SK_JUMBO_FRAMELEN 9018 1362 #define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1363 #define SK_JSLOTS 384 1364 1365 #define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN) 1366 #define SK_JLEN SK_JRAWLEN 1367 #define SK_MCLBYTES SK_JLEN 1368 #define SK_JPAGESZ PAGE_SIZE 1369 #define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ) 1370 #define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID) 1371 1372 #define SK_MAXUNIT 256 1373 #define SK_TIMEOUT 1000 1374 #define ETHER_ALIGN 2 1375 1376 /* YUKON registers */ 1377 1378 /* General Purpose Status Register (GPSR) */ 1379 #define YUKON_GPSR 0x0000 1380 1381 #define YU_GPSR_SPEED 0x8000 /* speed 0 - 10Mbps, 1 - 100Mbps */ 1382 #define YU_GPSR_DUPLEX 0x4000 /* 0 - half duplex, 1 - full duplex */ 1383 #define YU_GPSR_FCTL_TX 0x2000 /* flow control */ 1384 #define YU_GPSR_LINK 0x1000 /* link status (down/up) */ 1385 #define YU_GPSR_PAUSE 0x0800 /* flow control enable/disable */ 1386 #define YU_GPSR_TX_IN_PROG 0x0400 /* transmit in progress */ 1387 #define YU_GPSR_EXCESS_COL 0x0200 /* excessive collisions occurred */ 1388 #define YU_GPSR_LATE_COL 0x0100 /* late collision occurred */ 1389 #define YU_GPSR_MII_PHY_STC 0x0020 /* MII PHY status change */ 1390 #define YU_GPSR_GIG_SPEED 0x0010 /* Gigabit Speed (0 - use speed bit) */ 1391 #define YU_GPSR_PARTITION 0x0008 /* partition mode */ 1392 #define YU_GPSR_FCTL_RX 0x0004 /* flow control enable/disable */ 1393 #define YU_GPSR_PROMS_EN 0x0002 /* promiscuous mode enable/disable */ 1394 1395 /* General Purpose Control Register (GPCR) */ 1396 #define YUKON_GPCR 0x0004 1397 1398 #define YU_GPCR_FCTL_TX 0x2000 /* Transmit flow control 802.3x */ 1399 #define YU_GPCR_TXEN 0x1000 /* Transmit Enable */ 1400 #define YU_GPCR_RXEN 0x0800 /* Receive Enable */ 1401 #define YU_GPCR_LPBK 0x0200 /* Loopback Enable */ 1402 #define YU_GPCR_PAR 0x0100 /* Partition Enable */ 1403 #define YU_GPCR_GIG 0x0080 /* Gigabit Speed */ 1404 #define YU_GPCR_FLP 0x0040 /* Force Link Pass */ 1405 #define YU_GPCR_DUPLEX 0x0020 /* Duplex Enable */ 1406 #define YU_GPCR_FCTL_RX 0x0010 /* Receive flow control 802.3x */ 1407 #define YU_GPCR_SPEED 0x0008 /* Port Speed */ 1408 #define YU_GPCR_DPLX_EN 0x0004 /* Enable Auto-Update for duplex */ 1409 #define YU_GPCR_FCTL_EN 0x0002 /* Enabel Auto-Update for 802.3x */ 1410 #define YU_GPCR_SPEED_EN 0x0001 /* Enable Auto-Update for speed */ 1411 1412 /* Transmit Control Register (TCR) */ 1413 #define YUKON_TCR 0x0008 1414 1415 #define YU_TCR_FJ 0x8000 /* force jam / flow control */ 1416 #define YU_TCR_CRCD 0x4000 /* insert CRC (0 - enable) */ 1417 #define YU_TCR_PADD 0x2000 /* pad packets to 64b (0 - enable) */ 1418 #define YU_TCR_COLTH 0x1c00 /* collision threshold */ 1419 1420 /* Receive Control Register (RCR) */ 1421 #define YUKON_RCR 0x000c 1422 1423 #define YU_RCR_UFLEN 0x8000 /* unicast filter enable */ 1424 #define YU_RCR_MUFLEN 0x4000 /* multicast filter enable */ 1425 #define YU_RCR_CRCR 0x2000 /* remove CRC */ 1426 #define YU_RCR_PASSFC 0x1000 /* pass flow control packets */ 1427 1428 /* Transmit Flow Control Register (TFCR) */ 1429 #define YUKON_TFCR 0x0010 /* Pause Time */ 1430 1431 /* Transmit Parameter Register (TPR) */ 1432 #define YUKON_TPR 0x0014 1433 1434 #define YU_TPR_JAM_LEN(x) (((x) & 0x3) << 14) 1435 #define YU_TPR_JAM_IPG(x) (((x) & 0x1f) << 9) 1436 #define YU_TPR_JAM2DATA_IPG(x) (((x) & 0x1f) << 4) 1437 1438 /* Serial Mode Register (SMR) */ 1439 #define YUKON_SMR 0x0018 1440 1441 #define YU_SMR_DATA_BLIND(x) (((x) & 0x1f) << 11) 1442 #define YU_SMR_LIMIT4 0x0400 /* reset after 16 / 4 collisions */ 1443 #define YU_SMR_MFL_JUMBO 0x0100 /* max frame length for jumbo frames */ 1444 #define YU_SMR_MFL_VLAN 0x0200 /* max frame length + vlan tag */ 1445 #define YU_SMR_IPG_DATA(x) ((x) & 0x1f) 1446 1447 /* Source Address Low #1 (SAL1) */ 1448 #define YUKON_SAL1 0x001c /* SA1[15:0] */ 1449 1450 /* Source Address Middle #1 (SAM1) */ 1451 #define YUKON_SAM1 0x0020 /* SA1[31:16] */ 1452 1453 /* Source Address High #1 (SAH1) */ 1454 #define YUKON_SAH1 0x0024 /* SA1[47:32] */ 1455 1456 /* Source Address Low #2 (SAL2) */ 1457 #define YUKON_SAL2 0x0028 /* SA2[15:0] */ 1458 1459 /* Source Address Middle #2 (SAM2) */ 1460 #define YUKON_SAM2 0x002c /* SA2[31:16] */ 1461 1462 /* Source Address High #2 (SAH2) */ 1463 #define YUKON_SAH2 0x0030 /* SA2[47:32] */ 1464 1465 /* Multicatst Address Hash Register 1 (MCAH1) */ 1466 #define YUKON_MCAH1 0x0034 1467 1468 /* Multicatst Address Hash Register 2 (MCAH2) */ 1469 #define YUKON_MCAH2 0x0038 1470 1471 /* Multicatst Address Hash Register 3 (MCAH3) */ 1472 #define YUKON_MCAH3 0x003c 1473 1474 /* Multicatst Address Hash Register 4 (MCAH4) */ 1475 #define YUKON_MCAH4 0x0040 1476 1477 /* Transmit Interrupt Register (TIR) */ 1478 #define YUKON_TIR 0x0044 1479 1480 #define YU_TIR_OUT_UNICAST 0x0001 /* Num Unicast Packets Transmitted */ 1481 #define YU_TIR_OUT_BROADCAST 0x0002 /* Num Broadcast Packets Transmitted */ 1482 #define YU_TIR_OUT_PAUSE 0x0004 /* Num Pause Packets Transmitted */ 1483 #define YU_TIR_OUT_MULTICAST 0x0008 /* Num Multicast Packets Transmitted */ 1484 #define YU_TIR_OUT_OCTETS 0x0030 /* Num Bytes Transmitted */ 1485 #define YU_TIR_OUT_64_OCTETS 0x0000 /* Num Packets Transmitted */ 1486 #define YU_TIR_OUT_127_OCTETS 0x0000 /* Num Packets Transmitted */ 1487 #define YU_TIR_OUT_255_OCTETS 0x0000 /* Num Packets Transmitted */ 1488 #define YU_TIR_OUT_511_OCTETS 0x0000 /* Num Packets Transmitted */ 1489 #define YU_TIR_OUT_1023_OCTETS 0x0000 /* Num Packets Transmitted */ 1490 #define YU_TIR_OUT_1518_OCTETS 0x0000 /* Num Packets Transmitted */ 1491 #define YU_TIR_OUT_MAX_OCTETS 0x0000 /* Num Packets Transmitted */ 1492 #define YU_TIR_OUT_SPARE 0x0000 /* Num Packets Transmitted */ 1493 #define YU_TIR_OUT_COLLISIONS 0x0000 /* Num Packets Transmitted */ 1494 #define YU_TIR_OUT_LATE 0x0000 /* Num Packets Transmitted */ 1495 1496 /* Receive Interrupt Register (RIR) */ 1497 #define YUKON_RIR 0x0048 1498 1499 /* Transmit and Receive Interrupt Register (TRIR) */ 1500 #define YUKON_TRIR 0x004c 1501 1502 /* Transmit Interrupt Mask Register (TIMR) */ 1503 #define YUKON_TIMR 0x0050 1504 1505 /* Receive Interrupt Mask Register (RIMR) */ 1506 #define YUKON_RIMR 0x0054 1507 1508 /* Transmit and Receive Interrupt Mask Register (TRIMR) */ 1509 #define YUKON_TRIMR 0x0058 1510 1511 /* SMI Control Register (SMICR) */ 1512 #define YUKON_SMICR 0x0080 1513 1514 #define YU_SMICR_PHYAD(x) (((x) & 0x1f) << 11) 1515 #define YU_SMICR_REGAD(x) (((x) & 0x1f) << 6) 1516 #define YU_SMICR_OPCODE 0x0020 /* opcode (0 - write, 1 - read) */ 1517 #define YU_SMICR_OP_READ 0x0020 /* opcode read */ 1518 #define YU_SMICR_OP_WRITE 0x0000 /* opcode write */ 1519 #define YU_SMICR_READ_VALID 0x0010 /* read valid */ 1520 #define YU_SMICR_BUSY 0x0008 /* busy (writing) */ 1521 1522 /* SMI Data Register (SMIDR) */ 1523 #define YUKON_SMIDR 0x0084 1524 1525 /* PHY Addres Register (PAR) */ 1526 #define YUKON_PAR 0x0088 1527 1528 #define YU_PAR_MIB_CLR 0x0020 /* MIB Counters Clear Mode */ 1529 #define YU_PAR_LOAD_TSTCNT 0x0010 /* Load count 0xfffffff0 into cntr */ 1530 1531 /* 1532 * Registers and data structures for the XaQti Corporation XMAC II 1533 * Gigabit Ethernet MAC. Datasheet is available from http://www.xaqti.com. 1534 * The XMAC can be programmed for 16-bit or 32-bit register access modes. 1535 * The SysKonnect gigabit ethernet adapters use 16-bit mode, so that's 1536 * how the registers are laid out here. 1537 */ 1538 1539 #define XM_DEVICEID 0x00E0AE20 1540 #define XM_XAQTI_OUI 0x00E0AE 1541 1542 #define XM_XMAC_REV(x) (((x) & 0x000000E0) >> 5) 1543 1544 #define XM_XMAC_REV_B2 0x0 1545 #define XM_XMAC_REV_C1 0x1 1546 1547 #define XM_MMUCMD 0x0000 1548 #define XM_POFF 0x0008 1549 #define XM_BURST 0x000C 1550 #define XM_VLAN_TAGLEV1 0x0010 1551 #define XM_VLAN_TAGLEV2 0x0014 1552 #define XM_TXCMD 0x0020 1553 #define XM_TX_RETRYLIMIT 0x0024 1554 #define XM_TX_SLOTTIME 0x0028 1555 #define XM_TX_IPG 0x003C 1556 #define XM_RXCMD 0x0030 1557 #define XM_PHY_ADDR 0x0034 1558 #define XM_PHY_DATA 0x0038 1559 #define XM_GPIO 0x0040 1560 #define XM_IMR 0x0044 1561 #define XM_ISR 0x0048 1562 #define XM_HWCFG 0x004C 1563 #define XM_TX_LOWAT 0x0060 1564 #define XM_TX_HIWAT 0x0062 1565 #define XM_TX_REQTHRESH_LO 0x0064 1566 #define XM_TX_REQTHRESH_HI 0x0066 1567 #define XM_TX_REQTHRESH XM_TX_REQTHRESH_LO 1568 #define XM_PAUSEDST0 0x0068 1569 #define XM_PAUSEDST1 0x006A 1570 #define XM_PAUSEDST2 0x006C 1571 #define XM_CTLPARM_LO 0x0070 1572 #define XM_CTLPARM_HI 0x0072 1573 #define XM_CTLPARM XM_CTLPARM_LO 1574 #define XM_OPCODE_PAUSE_TIMER 0x0074 1575 #define XM_TXSTAT_LIFO 0x0078 1576 1577 /* 1578 * Perfect filter registers. The XMAC has a table of 16 perfect 1579 * filter entries, spaced 8 bytes apart. This is in addition to 1580 * the station address registers, which appear below. 1581 */ 1582 #define XM_RXFILT_BASE 0x0080 1583 #define XM_RXFILT_END 0x0107 1584 #define XM_RXFILT_MAX 16 1585 #define XM_RXFILT_ENTRY(ent) (XM_RXFILT_BASE + ((ent * 8))) 1586 1587 /* Primary station address. */ 1588 #define XM_PAR0 0x0108 1589 #define XM_PAR1 0x010A 1590 #define XM_PAR2 0x010C 1591 1592 /* 64-bit multicast hash table registers */ 1593 #define XM_MAR0 0x0110 1594 #define XM_MAR1 0x0112 1595 #define XM_MAR2 0x0114 1596 #define XM_MAR3 0x0116 1597 #define XM_RX_LOWAT 0x0118 1598 #define XM_RX_HIWAT 0x011A 1599 #define XM_RX_REQTHRESH_LO 0x011C 1600 #define XM_RX_REQTHRESH_HI 0x011E 1601 #define XM_RX_REQTHRESH XM_RX_REQTHRESH_LO 1602 #define XM_DEVID_LO 0x0120 1603 #define XM_DEVID_HI 0x0122 1604 #define XM_DEVID XM_DEVID_LO 1605 #define XM_MODE_LO 0x0124 1606 #define XM_MODE_HI 0x0126 1607 #define XM_MODE XM_MODE_LO 1608 #define XM_LASTSRC0 0x0128 1609 #define XM_LASTSRC1 0x012A 1610 #define XM_LASTSRC2 0x012C 1611 #define XM_TSTAMP_READ 0x0130 1612 #define XM_TSTAMP_LOAD 0x0134 1613 #define XM_STATS_CMD 0x0200 1614 #define XM_RXCNT_EVENT_LO 0x0204 1615 #define XM_RXCNT_EVENT_HI 0x0206 1616 #define XM_RXCNT_EVENT XM_RXCNT_EVENT_LO 1617 #define XM_TXCNT_EVENT_LO 0x0208 1618 #define XM_TXCNT_EVENT_HI 0x020A 1619 #define XM_TXCNT_EVENT XM_TXCNT_EVENT_LO 1620 #define XM_RXCNT_EVMASK_LO 0x020C 1621 #define XM_RXCNT_EVMASK_HI 0x020E 1622 #define XM_RXCNT_EVMASK XM_RXCNT_EVMASK_LO 1623 #define XM_TXCNT_EVMASK_LO 0x0210 1624 #define XM_TXCNT_EVMASK_HI 0x0212 1625 #define XM_TXCNT_EVMASK XM_TXCNT_EVMASK_LO 1626 1627 /* Statistics command register */ 1628 #define XM_STATCMD_CLR_TX 0x0001 1629 #define XM_STATCMD_CLR_RX 0x0002 1630 #define XM_STATCMD_COPY_TX 0x0004 1631 #define XM_STATCMD_COPY_RX 0x0008 1632 #define XM_STATCMD_SNAP_TX 0x0010 1633 #define XM_STATCMD_SNAP_RX 0x0020 1634 1635 /* TX statistics registers */ 1636 #define XM_TXSTATS_PKTSOK 0x280 1637 #define XM_TXSTATS_BYTESOK_HI 0x284 1638 #define XM_TXSTATS_BYTESOK_LO 0x288 1639 #define XM_TXSTATS_BCASTSOK 0x28C 1640 #define XM_TXSTATS_MCASTSOK 0x290 1641 #define XM_TXSTATS_UCASTSOK 0x294 1642 #define XM_TXSTATS_GIANTS 0x298 1643 #define XM_TXSTATS_BURSTCNT 0x29C 1644 #define XM_TXSTATS_PAUSEPKTS 0x2A0 1645 #define XM_TXSTATS_MACCTLPKTS 0x2A4 1646 #define XM_TXSTATS_SINGLECOLS 0x2A8 1647 #define XM_TXSTATS_MULTICOLS 0x2AC 1648 #define XM_TXSTATS_EXCESSCOLS 0x2B0 1649 #define XM_TXSTATS_LATECOLS 0x2B4 1650 #define XM_TXSTATS_DEFER 0x2B8 1651 #define XM_TXSTATS_EXCESSDEFER 0x2BC 1652 #define XM_TXSTATS_UNDERRUN 0x2C0 1653 #define XM_TXSTATS_CARRIERSENSE 0x2C4 1654 #define XM_TXSTATS_UTILIZATION 0x2C8 1655 #define XM_TXSTATS_64 0x2D0 1656 #define XM_TXSTATS_65_127 0x2D4 1657 #define XM_TXSTATS_128_255 0x2D8 1658 #define XM_TXSTATS_256_511 0x2DC 1659 #define XM_TXSTATS_512_1023 0x2E0 1660 #define XM_TXSTATS_1024_MAX 0x2E4 1661 1662 /* RX statistics registers */ 1663 #define XM_RXSTATS_PKTSOK 0x300 1664 #define XM_RXSTATS_BYTESOK_HI 0x304 1665 #define XM_RXSTATS_BYTESOK_LO 0x308 1666 #define XM_RXSTATS_BCASTSOK 0x30C 1667 #define XM_RXSTATS_MCASTSOK 0x310 1668 #define XM_RXSTATS_UCASTSOK 0x314 1669 #define XM_RXSTATS_PAUSEPKTS 0x318 1670 #define XM_RXSTATS_MACCTLPKTS 0x31C 1671 #define XM_RXSTATS_BADPAUSEPKTS 0x320 1672 #define XM_RXSTATS_BADMACCTLPKTS 0x324 1673 #define XM_RXSTATS_BURSTCNT 0x328 1674 #define XM_RXSTATS_MISSEDPKTS 0x32C 1675 #define XM_RXSTATS_FRAMEERRS 0x330 1676 #define XM_RXSTATS_OVERRUN 0x334 1677 #define XM_RXSTATS_JABBER 0x338 1678 #define XM_RXSTATS_CARRLOSS 0x33C 1679 #define XM_RXSTATS_INRNGLENERR 0x340 1680 #define XM_RXSTATS_SYMERR 0x344 1681 #define XM_RXSTATS_SHORTEVENT 0x348 1682 #define XM_RXSTATS_RUNTS 0x34C 1683 #define XM_RXSTATS_GIANTS 0x350 1684 #define XM_RXSTATS_CRCERRS 0x354 1685 #define XM_RXSTATS_CEXTERRS 0x35C 1686 #define XM_RXSTATS_UTILIZATION 0x360 1687 #define XM_RXSTATS_64 0x368 1688 #define XM_RXSTATS_65_127 0x36C 1689 #define XM_RXSTATS_128_255 0x370 1690 #define XM_RXSTATS_256_511 0x374 1691 #define XM_RXSTATS_512_1023 0x378 1692 #define XM_RXSTATS_1024_MAX 0x37C 1693 1694 #define XM_MMUCMD_TX_ENB 0x0001 1695 #define XM_MMUCMD_RX_ENB 0x0002 1696 #define XM_MMUCMD_GMIILOOP 0x0004 1697 #define XM_MMUCMD_RATECTL 0x0008 1698 #define XM_MMUCMD_GMIIFDX 0x0010 1699 #define XM_MMUCMD_NO_MGMT_PRMB 0x0020 1700 #define XM_MMUCMD_SIMCOL 0x0040 1701 #define XM_MMUCMD_FORCETX 0x0080 1702 #define XM_MMUCMD_LOOPENB 0x0200 1703 #define XM_MMUCMD_IGNPAUSE 0x0400 1704 #define XM_MMUCMD_PHYBUSY 0x0800 1705 #define XM_MMUCMD_PHYDATARDY 0x1000 1706 1707 #define XM_TXCMD_AUTOPAD 0x0001 1708 #define XM_TXCMD_NOCRC 0x0002 1709 #define XM_TXCMD_NOPREAMBLE 0x0004 1710 #define XM_TXCMD_NOGIGAMODE 0x0008 1711 #define XM_TXCMD_SAMPLELINE 0x0010 1712 #define XM_TXCMD_ENCBYPASS 0x0020 1713 #define XM_TXCMD_XMITBK2BK 0x0040 1714 #define XM_TXCMD_FAIRSHARE 0x0080 1715 1716 #define XM_RXCMD_DISABLE_CEXT 0x0001 1717 #define XM_RXCMD_STRIPPAD 0x0002 1718 #define XM_RXCMD_SAMPLELINE 0x0004 1719 #define XM_RXCMD_SELFRX 0x0008 1720 #define XM_RXCMD_STRIPFCS 0x0010 1721 #define XM_RXCMD_TRANSPARENT 0x0020 1722 #define XM_RXCMD_IPGCAPTURE 0x0040 1723 #define XM_RXCMD_BIGPKTOK 0x0080 1724 #define XM_RXCMD_LENERROK 0x0100 1725 1726 #define XM_GPIO_GP0_SET 0x0001 1727 #define XM_GPIO_RESETSTATS 0x0004 1728 #define XM_GPIO_RESETMAC 0x0008 1729 #define XM_GPIO_FORCEINT 0x0020 1730 #define XM_GPIO_ANEGINPROG 0x0040 1731 1732 #define XM_IMR_RX_EOF 0x0001 1733 #define XM_IMR_TX_EOF 0x0002 1734 #define XM_IMR_TX_UNDERRUN 0x0004 1735 #define XM_IMR_RX_OVERRUN 0x0008 1736 #define XM_IMR_TX_STATS_OFLOW 0x0010 1737 #define XM_IMR_RX_STATS_OFLOW 0x0020 1738 #define XM_IMR_TSTAMP_OFLOW 0x0040 1739 #define XM_IMR_AUTONEG_DONE 0x0080 1740 #define XM_IMR_NEXTPAGE_RDY 0x0100 1741 #define XM_IMR_PAGE_RECEIVED 0x0200 1742 #define XM_IMR_LP_REQCFG 0x0400 1743 #define XM_IMR_GP0_SET 0x0800 1744 #define XM_IMR_FORCEINTR 0x1000 1745 #define XM_IMR_TX_ABORT 0x2000 1746 #define XM_IMR_LINKEVENT 0x4000 1747 1748 #define XM_INTRS \ 1749 (~(XM_IMR_GP0_SET|XM_IMR_AUTONEG_DONE|XM_IMR_TX_UNDERRUN)) 1750 1751 #define XM_ISR_RX_EOF 0x0001 1752 #define XM_ISR_TX_EOF 0x0002 1753 #define XM_ISR_TX_UNDERRUN 0x0004 1754 #define XM_ISR_RX_OVERRUN 0x0008 1755 #define XM_ISR_TX_STATS_OFLOW 0x0010 1756 #define XM_ISR_RX_STATS_OFLOW 0x0020 1757 #define XM_ISR_TSTAMP_OFLOW 0x0040 1758 #define XM_ISR_AUTONEG_DONE 0x0080 1759 #define XM_ISR_NEXTPAGE_RDY 0x0100 1760 #define XM_ISR_PAGE_RECEIVED 0x0200 1761 #define XM_ISR_LP_REQCFG 0x0400 1762 #define XM_ISR_GP0_SET 0x0800 1763 #define XM_ISR_FORCEINTR 0x1000 1764 #define XM_ISR_TX_ABORT 0x2000 1765 #define XM_ISR_LINKEVENT 0x4000 1766 1767 #define XM_HWCFG_GENEOP 0x0008 1768 #define XM_HWCFG_SIGSTATCKH 0x0004 1769 #define XM_HWCFG_GMIIMODE 0x0001 1770 1771 #define XM_MODE_FLUSH_RXFIFO 0x00000001 1772 #define XM_MODE_FLUSH_TXFIFO 0x00000002 1773 #define XM_MODE_BIGENDIAN 0x00000004 1774 #define XM_MODE_RX_PROMISC 0x00000008 1775 #define XM_MODE_RX_NOBROAD 0x00000010 1776 #define XM_MODE_RX_NOMULTI 0x00000020 1777 #define XM_MODE_RX_NOUNI 0x00000040 1778 #define XM_MODE_RX_BADFRAMES 0x00000080 1779 #define XM_MODE_RX_CRCERRS 0x00000100 1780 #define XM_MODE_RX_GIANTS 0x00000200 1781 #define XM_MODE_RX_INRANGELEN 0x00000400 1782 #define XM_MODE_RX_RUNTS 0x00000800 1783 #define XM_MODE_RX_MACCTL 0x00001000 1784 #define XM_MODE_RX_USE_PERFECT 0x00002000 1785 #define XM_MODE_RX_USE_STATION 0x00004000 1786 #define XM_MODE_RX_USE_HASH 0x00008000 1787 #define XM_MODE_RX_ADDRPAIR 0x00010000 1788 #define XM_MODE_PAUSEONHI 0x00020000 1789 #define XM_MODE_PAUSEONLO 0x00040000 1790 #define XM_MODE_TIMESTAMP 0x00080000 1791 #define XM_MODE_SENDPAUSE 0x00100000 1792 #define XM_MODE_SENDCONTINUOUS 0x00200000 1793 #define XM_MODE_LE_STATUSWORD 0x00400000 1794 #define XM_MODE_AUTOFIFOPAUSE 0x00800000 1795 #define XM_MODE_EXPAUSEGEN 0x02000000 1796 #define XM_MODE_RX_INVERSE 0x04000000 1797 1798 #define XM_RXSTAT_MACCTL 0x00000001 1799 #define XM_RXSTAT_ERRFRAME 0x00000002 1800 #define XM_RXSTAT_CRCERR 0x00000004 1801 #define XM_RXSTAT_GIANT 0x00000008 1802 #define XM_RXSTAT_RUNT 0x00000010 1803 #define XM_RXSTAT_FRAMEERR 0x00000020 1804 #define XM_RXSTAT_INRANGEERR 0x00000040 1805 #define XM_RXSTAT_CARRIERERR 0x00000080 1806 #define XM_RXSTAT_COLLERR 0x00000100 1807 #define XM_RXSTAT_802_3 0x00000200 1808 #define XM_RXSTAT_CARREXTERR 0x00000400 1809 #define XM_RXSTAT_BURSTMODE 0x00000800 1810 #define XM_RXSTAT_UNICAST 0x00002000 1811 #define XM_RXSTAT_MULTICAST 0x00004000 1812 #define XM_RXSTAT_BROADCAST 0x00008000 1813 #define XM_RXSTAT_VLAN_LEV1 0x00010000 1814 #define XM_RXSTAT_VLAN_LEV2 0x00020000 1815 #define XM_RXSTAT_LEN 0xFFFC0000 1816 1817 /* 1818 * XMAC PHY registers, indirectly accessed through 1819 * XM_PHY_ADDR and XM_PHY_REG. 1820 */ 1821 1822 #define XM_PHY_BMCR 0x0000 /* control */ 1823 #define XM_PHY_BMSR 0x0001 /* status */ 1824 #define XM_PHY_VENID 0x0002 /* vendor id */ 1825 #define XM_PHY_DEVID 0x0003 /* device id */ 1826 #define XM_PHY_ANAR 0x0004 /* autoneg advertisenemt */ 1827 #define XM_PHY_LPAR 0x0005 /* link partner ability */ 1828 #define XM_PHY_ANEXP 0x0006 /* autoneg expansion */ 1829 #define XM_PHY_NEXTP 0x0007 /* nextpage */ 1830 #define XM_PHY_LPNEXTP 0x0008 /* link partner's nextpage */ 1831 #define XM_PHY_EXTSTS 0x000F /* extented status */ 1832 #define XM_PHY_RESAB 0x0010 /* resolved ability */ 1833 1834 #define XM_BMCR_DUPLEX 0x0100 1835 #define XM_BMCR_RENEGOTIATE 0x0200 1836 #define XM_BMCR_AUTONEGENBL 0x1000 1837 #define XM_BMCR_LOOPBACK 0x4000 1838 #define XM_BMCR_RESET 0x8000 1839 1840 #define XM_BMSR_EXTCAP 0x0001 1841 #define XM_BMSR_LINKSTAT 0x0004 1842 #define XM_BMSR_AUTONEGABLE 0x0008 1843 #define XM_BMSR_REMFAULT 0x0010 1844 #define XM_BMSR_AUTONEGDONE 0x0020 1845 #define XM_BMSR_EXTSTAT 0x0100 1846 1847 #define XM_VENID_XAQTI 0xD14C 1848 #define XM_DEVID_XMAC 0x0002 1849 1850 #define XM_ANAR_FULLDUPLEX 0x0020 1851 #define XM_ANAR_HALFDUPLEX 0x0040 1852 #define XM_ANAR_PAUSEBITS 0x0180 1853 #define XM_ANAR_REMFAULTBITS 0x1800 1854 #define XM_ANAR_ACK 0x4000 1855 #define XM_ANAR_NEXTPAGE 0x8000 1856 1857 #define XM_LPAR_FULLDUPLEX 0x0020 1858 #define XM_LPAR_HALFDUPLEX 0x0040 1859 #define XM_LPAR_PAUSEBITS 0x0180 1860 #define XM_LPAR_REMFAULTBITS 0x1800 1861 #define XM_LPAR_ACK 0x4000 1862 #define XM_LPAR_NEXTPAGE 0x8000 1863 1864 #define XM_PAUSE_NOPAUSE 0x0000 1865 #define XM_PAUSE_SYMPAUSE 0x0080 1866 #define XM_PAUSE_ASYMPAUSE 0x0100 1867 #define XM_PAUSE_BOTH 0x0180 1868 1869 #define XM_REMFAULT_LINKOK 0x0000 1870 #define XM_REMFAULT_LINKFAIL 0x0800 1871 #define XM_REMFAULT_OFFLINE 0x1000 1872 #define XM_REMFAULT_ANEGERR 0x1800 1873 1874 #define XM_ANEXP_GOTPAGE 0x0002 1875 #define XM_ANEXP_NEXTPAGE_SELF 0x0004 1876 #define XM_ANEXP_NEXTPAGE_LP 0x0008 1877 1878 #define XM_NEXTP_MESSAGE 0x07FF 1879 #define XM_NEXTP_TOGGLE 0x0800 1880 #define XM_NEXTP_ACK2 0x1000 1881 #define XM_NEXTP_MPAGE 0x2000 1882 #define XM_NEXTP_ACK1 0x4000 1883 #define XM_NEXTP_NPAGE 0x8000 1884 1885 #define XM_LPNEXTP_MESSAGE 0x07FF 1886 #define XM_LPNEXTP_TOGGLE 0x0800 1887 #define XM_LPNEXTP_ACK2 0x1000 1888 #define XM_LPNEXTP_MPAGE 0x2000 1889 #define XM_LPNEXTP_ACK1 0x4000 1890 #define XM_LPNEXTP_NPAGE 0x8000 1891 1892 #define XM_EXTSTS_HALFDUPLEX 0x4000 1893 #define XM_EXTSTS_FULLDUPLEX 0x8000 1894 1895 #define XM_RESAB_PAUSEMISMATCH 0x0008 1896 #define XM_RESAB_ABLMISMATCH 0x0010 1897 #define XM_RESAB_FDMODESEL 0x0020 1898 #define XM_RESAB_HDMODESEL 0x0040 1899 #define XM_RESAB_PAUSEBITS 0x0180 1900 #endif /* _DEV_PCI_IF_SKREG_H_ */ 1901
Indexes created Thu Sep 25 16:09:42 GMT 2025