if_ste.c revision 1.58.2.1
1 /* $NetBSD: if_ste.c,v 1.58.2.1 2020/02/29 20:19:10 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. ST-201 10/100 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_ste.c,v 1.58.2.1 2020/02/29 20:19:10 ad Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/mii_bitbang.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_stereg.h> 72 73 /* 74 * Transmit descriptor list size. 75 */ 76 #define STE_NTXDESC 256 77 #define STE_NTXDESC_MASK (STE_NTXDESC - 1) 78 #define STE_NEXTTX(x) (((x) + 1) & STE_NTXDESC_MASK) 79 80 /* 81 * Receive descriptor list size. 82 */ 83 #define STE_NRXDESC 128 84 #define STE_NRXDESC_MASK (STE_NRXDESC - 1) 85 #define STE_NEXTRX(x) (((x) + 1) & STE_NRXDESC_MASK) 86 87 /* 88 * Control structures are DMA'd to the ST-201 chip. We allocate them in 89 * a single clump that maps to a single DMA segment to make several things 90 * easier. 91 */ 92 struct ste_control_data { 93 /* 94 * The transmit descriptors. 95 */ 96 struct ste_tfd scd_txdescs[STE_NTXDESC]; 97 98 /* 99 * The receive descriptors. 100 */ 101 struct ste_rfd scd_rxdescs[STE_NRXDESC]; 102 }; 103 104 #define STE_CDOFF(x) offsetof(struct ste_control_data, x) 105 #define STE_CDTXOFF(x) STE_CDOFF(scd_txdescs[(x)]) 106 #define STE_CDRXOFF(x) STE_CDOFF(scd_rxdescs[(x)]) 107 108 /* 109 * Software state for transmit and receive jobs. 110 */ 111 struct ste_descsoft { 112 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 113 bus_dmamap_t ds_dmamap; /* our DMA map */ 114 }; 115 116 /* 117 * Software state per device. 118 */ 119 struct ste_softc { 120 device_t sc_dev; /* generic device information */ 121 bus_space_tag_t sc_st; /* bus space tag */ 122 bus_space_handle_t sc_sh; /* bus space handle */ 123 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 124 struct ethercom sc_ethercom; /* ethernet common data */ 125 126 void *sc_ih; /* interrupt cookie */ 127 128 struct mii_data sc_mii; /* MII/media information */ 129 130 callout_t sc_tick_ch; /* tick callout */ 131 132 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 133 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 134 135 /* 136 * Software state for transmit and receive descriptors. 137 */ 138 struct ste_descsoft sc_txsoft[STE_NTXDESC]; 139 struct ste_descsoft sc_rxsoft[STE_NRXDESC]; 140 141 /* 142 * Control data structures. 143 */ 144 struct ste_control_data *sc_control_data; 145 #define sc_txdescs sc_control_data->scd_txdescs 146 #define sc_rxdescs sc_control_data->scd_rxdescs 147 148 int sc_txpending; /* number of Tx requests pending */ 149 int sc_txdirty; /* first dirty Tx descriptor */ 150 int sc_txlast; /* last used Tx descriptor */ 151 152 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 153 154 int sc_txthresh; /* Tx threshold */ 155 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 156 uint16_t sc_IntEnable; /* prototype IntEnable register */ 157 uint16_t sc_MacCtrl0; /* prototype MacCtrl0 register */ 158 uint8_t sc_ReceiveMode; /* prototype ReceiveMode register */ 159 }; 160 161 #define STE_CDTXADDR(sc, x) ((sc)->sc_cddma + STE_CDTXOFF((x))) 162 #define STE_CDRXADDR(sc, x) ((sc)->sc_cddma + STE_CDRXOFF((x))) 163 164 #define STE_CDTXSYNC(sc, x, ops) \ 165 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 166 STE_CDTXOFF((x)), sizeof(struct ste_tfd), (ops)) 167 168 #define STE_CDRXSYNC(sc, x, ops) \ 169 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 170 STE_CDRXOFF((x)), sizeof(struct ste_rfd), (ops)) 171 172 #define STE_INIT_RXDESC(sc, x) \ 173 do { \ 174 struct ste_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 175 struct ste_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 176 struct mbuf *__m = __ds->ds_mbuf; \ 177 \ 178 /* \ 179 * Note: We scoot the packet forward 2 bytes in the buffer \ 180 * so that the payload after the Ethernet header is aligned \ 181 * to a 4-byte boundary. \ 182 */ \ 183 __m->m_data = __m->m_ext.ext_buf + 2; \ 184 __rfd->rfd_frag.frag_addr = \ 185 htole32(__ds->ds_dmamap->dm_segs[0].ds_addr + 2); \ 186 __rfd->rfd_frag.frag_len = htole32((MCLBYTES - 2) | FRAG_LAST); \ 187 __rfd->rfd_next = htole32(STE_CDRXADDR((sc), STE_NEXTRX((x)))); \ 188 __rfd->rfd_status = 0; \ 189 STE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \ 190 } while (/*CONSTCOND*/0) 191 192 #define STE_TIMEOUT 1000 193 194 static void ste_start(struct ifnet *); 195 static void ste_watchdog(struct ifnet *); 196 static int ste_ioctl(struct ifnet *, u_long, void *); 197 static int ste_init(struct ifnet *); 198 static void ste_stop(struct ifnet *, int); 199 200 static bool ste_shutdown(device_t, int); 201 202 static void ste_reset(struct ste_softc *, uint32_t); 203 static void ste_setthresh(struct ste_softc *); 204 static void ste_txrestart(struct ste_softc *, uint8_t); 205 static void ste_rxdrain(struct ste_softc *); 206 static int ste_add_rxbuf(struct ste_softc *, int); 207 static void ste_read_eeprom(struct ste_softc *, int, uint16_t *); 208 static void ste_tick(void *); 209 210 static void ste_stats_update(struct ste_softc *); 211 212 static void ste_set_filter(struct ste_softc *); 213 214 static int ste_intr(void *); 215 static void ste_txintr(struct ste_softc *); 216 static void ste_rxintr(struct ste_softc *); 217 218 static int ste_mii_readreg(device_t, int, int, uint16_t *); 219 static int ste_mii_writereg(device_t, int, int, uint16_t); 220 static void ste_mii_statchg(struct ifnet *); 221 222 static int ste_match(device_t, cfdata_t, void *); 223 static void ste_attach(device_t, device_t, void *); 224 225 int ste_copy_small = 0; 226 227 CFATTACH_DECL_NEW(ste, sizeof(struct ste_softc), 228 ste_match, ste_attach, NULL, NULL); 229 230 static uint32_t ste_mii_bitbang_read(device_t); 231 static void ste_mii_bitbang_write(device_t, uint32_t); 232 233 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 234 ste_mii_bitbang_read, 235 ste_mii_bitbang_write, 236 { 237 PC_MgmtData, /* MII_BIT_MDO */ 238 PC_MgmtData, /* MII_BIT_MDI */ 239 PC_MgmtClk, /* MII_BIT_MDC */ 240 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 241 0, /* MII_BIT_DIR_PHY_HOST */ 242 } 243 }; 244 245 /* 246 * Devices supported by this driver. 247 */ 248 static const struct ste_product { 249 pci_vendor_id_t ste_vendor; 250 pci_product_id_t ste_product; 251 const char *ste_name; 252 } ste_products[] = { 253 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_IP100A, 254 "IC Plus Corp. IP00A 10/100 Fast Ethernet Adapter" }, 255 256 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST201, 257 "Sundance ST-201 10/100 Ethernet" }, 258 259 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL1002, 260 "D-Link DL-1002 10/100 Ethernet" }, 261 262 { 0, 0, 263 NULL }, 264 }; 265 266 static const struct ste_product * 267 ste_lookup(const struct pci_attach_args *pa) 268 { 269 const struct ste_product *sp; 270 271 for (sp = ste_products; sp->ste_name != NULL; sp++) { 272 if (PCI_VENDOR(pa->pa_id) == sp->ste_vendor && 273 PCI_PRODUCT(pa->pa_id) == sp->ste_product) 274 return (sp); 275 } 276 return (NULL); 277 } 278 279 static int 280 ste_match(device_t parent, cfdata_t cf, void *aux) 281 { 282 struct pci_attach_args *pa = aux; 283 284 if (ste_lookup(pa) != NULL) 285 return (1); 286 287 return (0); 288 } 289 290 static void 291 ste_attach(device_t parent, device_t self, void *aux) 292 { 293 struct ste_softc *sc = device_private(self); 294 struct pci_attach_args *pa = aux; 295 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 296 struct mii_data * const mii = &sc->sc_mii; 297 pci_chipset_tag_t pc = pa->pa_pc; 298 pci_intr_handle_t ih; 299 const char *intrstr = NULL; 300 bus_space_tag_t iot, memt; 301 bus_space_handle_t ioh, memh; 302 bus_dma_segment_t seg; 303 int ioh_valid, memh_valid; 304 int i, rseg, error; 305 const struct ste_product *sp; 306 uint8_t enaddr[ETHER_ADDR_LEN]; 307 uint16_t myea[ETHER_ADDR_LEN / 2]; 308 char intrbuf[PCI_INTRSTR_LEN]; 309 310 sc->sc_dev = self; 311 312 callout_init(&sc->sc_tick_ch, 0); 313 callout_setfunc(&sc->sc_tick_ch, ste_tick, sc); 314 315 sp = ste_lookup(pa); 316 if (sp == NULL) { 317 printf("\n"); 318 panic("ste_attach: impossible"); 319 } 320 321 printf(": %s\n", sp->ste_name); 322 323 /* 324 * Map the device. 325 */ 326 ioh_valid = (pci_mapreg_map(pa, STE_PCI_IOBA, 327 PCI_MAPREG_TYPE_IO, 0, 328 &iot, &ioh, NULL, NULL) == 0); 329 memh_valid = (pci_mapreg_map(pa, STE_PCI_MMBA, 330 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 331 &memt, &memh, NULL, NULL) == 0); 332 333 if (memh_valid) { 334 sc->sc_st = memt; 335 sc->sc_sh = memh; 336 } else if (ioh_valid) { 337 sc->sc_st = iot; 338 sc->sc_sh = ioh; 339 } else { 340 aprint_error_dev(self, "unable to map device registers\n"); 341 return; 342 } 343 344 sc->sc_dmat = pa->pa_dmat; 345 346 /* Enable bus mastering. */ 347 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 348 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 349 PCI_COMMAND_MASTER_ENABLE); 350 351 /* power up chip */ 352 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 353 NULL)) && error != EOPNOTSUPP) { 354 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 355 return; 356 } 357 358 /* 359 * Map and establish our interrupt. 360 */ 361 if (pci_intr_map(pa, &ih)) { 362 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 363 return; 364 } 365 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 366 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, ste_intr, sc, 367 device_xname(self)); 368 if (sc->sc_ih == NULL) { 369 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 370 if (intrstr != NULL) 371 aprint_error(" at %s", intrstr); 372 aprint_error("\n"); 373 return; 374 } 375 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 376 377 /* 378 * Allocate the control data structures, and create and load the 379 * DMA map for it. 380 */ 381 if ((error = bus_dmamem_alloc(sc->sc_dmat, 382 sizeof(struct ste_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 383 0)) != 0) { 384 aprint_error_dev(sc->sc_dev, 385 "unable to allocate control data, error = %d\n", error); 386 goto fail_0; 387 } 388 389 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 390 sizeof(struct ste_control_data), (void **)&sc->sc_control_data, 391 BUS_DMA_COHERENT)) != 0) { 392 aprint_error_dev(sc->sc_dev, 393 "unable to map control data, error = %d\n", error); 394 goto fail_1; 395 } 396 397 if ((error = bus_dmamap_create(sc->sc_dmat, 398 sizeof(struct ste_control_data), 1, 399 sizeof(struct ste_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 400 aprint_error_dev(sc->sc_dev, 401 "unable to create control data DMA map, error = %d\n", 402 error); 403 goto fail_2; 404 } 405 406 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 407 sc->sc_control_data, sizeof(struct ste_control_data), NULL, 408 0)) != 0) { 409 aprint_error_dev(sc->sc_dev, 410 "unable to load control data DMA map, error = %d\n", 411 error); 412 goto fail_3; 413 } 414 415 /* 416 * Create the transmit buffer DMA maps. 417 */ 418 for (i = 0; i < STE_NTXDESC; i++) { 419 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 420 STE_NTXFRAGS, MCLBYTES, 0, 0, 421 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 422 aprint_error_dev(sc->sc_dev, 423 "unable to create tx DMA map %d, error = %d\n", i, 424 error); 425 goto fail_4; 426 } 427 } 428 429 /* 430 * Create the receive buffer DMA maps. 431 */ 432 for (i = 0; i < STE_NRXDESC; i++) { 433 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 434 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 435 aprint_error_dev(sc->sc_dev, 436 "unable to create rx DMA map %d, error = %d\n", i, 437 error); 438 goto fail_5; 439 } 440 sc->sc_rxsoft[i].ds_mbuf = NULL; 441 } 442 443 /* 444 * Reset the chip to a known state. 445 */ 446 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 447 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 448 449 /* 450 * Read the Ethernet address from the EEPROM. 451 */ 452 for (i = 0; i < 3; i++) { 453 ste_read_eeprom(sc, STE_EEPROM_StationAddress0 + i, &myea[i]); 454 myea[i] = le16toh(myea[i]); 455 } 456 memcpy(enaddr, myea, sizeof(enaddr)); 457 458 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 459 ether_sprintf(enaddr)); 460 461 /* 462 * Initialize our media structures and probe the MII. 463 */ 464 mii->mii_ifp = ifp; 465 mii->mii_readreg = ste_mii_readreg; 466 mii->mii_writereg = ste_mii_writereg; 467 mii->mii_statchg = ste_mii_statchg; 468 sc->sc_ethercom.ec_mii = mii; 469 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 470 ether_mediastatus); 471 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 472 MII_OFFSET_ANY, 0); 473 if (LIST_FIRST(&mii->mii_phys) == NULL) { 474 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 475 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 476 } else 477 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 478 479 ifp = &sc->sc_ethercom.ec_if; 480 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 481 ifp->if_softc = sc; 482 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 483 ifp->if_ioctl = ste_ioctl; 484 ifp->if_start = ste_start; 485 ifp->if_watchdog = ste_watchdog; 486 ifp->if_init = ste_init; 487 ifp->if_stop = ste_stop; 488 IFQ_SET_READY(&ifp->if_snd); 489 490 /* 491 * Default the transmit threshold to 128 bytes. 492 */ 493 sc->sc_txthresh = 128; 494 495 /* 496 * Disable MWI if the PCI layer tells us to. 497 */ 498 sc->sc_DMACtrl = 0; 499 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 500 sc->sc_DMACtrl |= DC_MWIDisable; 501 502 /* 503 * We can support 802.1Q VLAN-sized frames. 504 */ 505 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 506 507 /* 508 * Attach the interface. 509 */ 510 if_attach(ifp); 511 if_deferred_start_init(ifp, NULL); 512 ether_ifattach(ifp, enaddr); 513 514 /* 515 * Make sure the interface is shutdown during reboot. 516 */ 517 if (pmf_device_register1(self, NULL, NULL, ste_shutdown)) 518 pmf_class_network_register(self, ifp); 519 else 520 aprint_error_dev(self, "couldn't establish power handler\n"); 521 522 return; 523 524 /* 525 * Free any resources we've allocated during the failed attach 526 * attempt. Do this in reverse order and fall through. 527 */ 528 fail_5: 529 for (i = 0; i < STE_NRXDESC; i++) { 530 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 531 bus_dmamap_destroy(sc->sc_dmat, 532 sc->sc_rxsoft[i].ds_dmamap); 533 } 534 fail_4: 535 for (i = 0; i < STE_NTXDESC; i++) { 536 if (sc->sc_txsoft[i].ds_dmamap != NULL) 537 bus_dmamap_destroy(sc->sc_dmat, 538 sc->sc_txsoft[i].ds_dmamap); 539 } 540 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 541 fail_3: 542 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 543 fail_2: 544 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 545 sizeof(struct ste_control_data)); 546 fail_1: 547 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 548 fail_0: 549 return; 550 } 551 552 /* 553 * ste_shutdown: 554 * 555 * Make sure the interface is stopped at reboot time. 556 */ 557 static bool 558 ste_shutdown(device_t self, int howto) 559 { 560 struct ste_softc *sc; 561 562 sc = device_private(self); 563 ste_stop(&sc->sc_ethercom.ec_if, 1); 564 565 return true; 566 } 567 568 static void 569 ste_dmahalt_wait(struct ste_softc *sc) 570 { 571 int i; 572 573 for (i = 0; i < STE_TIMEOUT; i++) { 574 delay(2); 575 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_DMACtrl) & 576 DC_DMAHaltBusy) == 0) 577 break; 578 } 579 580 if (i == STE_TIMEOUT) 581 printf("%s: DMA halt timed out\n", device_xname(sc->sc_dev)); 582 } 583 584 /* 585 * ste_start: [ifnet interface function] 586 * 587 * Start packet transmission on the interface. 588 */ 589 static void 590 ste_start(struct ifnet *ifp) 591 { 592 struct ste_softc *sc = ifp->if_softc; 593 struct mbuf *m0, *m; 594 struct ste_descsoft *ds; 595 struct ste_tfd *tfd; 596 bus_dmamap_t dmamap; 597 int error, olasttx, nexttx, opending, seg, totlen; 598 599 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 600 return; 601 602 /* 603 * Remember the previous number of pending transmissions 604 * and the current last descriptor in the list. 605 */ 606 opending = sc->sc_txpending; 607 olasttx = sc->sc_txlast; 608 609 /* 610 * Loop through the send queue, setting up transmit descriptors 611 * until we drain the queue, or use up all available transmit 612 * descriptors. 613 */ 614 while (sc->sc_txpending < STE_NTXDESC) { 615 /* 616 * Grab a packet off the queue. 617 */ 618 IFQ_POLL(&ifp->if_snd, m0); 619 if (m0 == NULL) 620 break; 621 m = NULL; 622 623 /* 624 * Get the last and next available transmit descriptor. 625 */ 626 nexttx = STE_NEXTTX(sc->sc_txlast); 627 tfd = &sc->sc_txdescs[nexttx]; 628 ds = &sc->sc_txsoft[nexttx]; 629 630 dmamap = ds->ds_dmamap; 631 632 /* 633 * Load the DMA map. If this fails, the packet either 634 * didn't fit in the alloted number of segments, or we 635 * were short on resources. In this case, we'll copy 636 * and try again. 637 */ 638 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 639 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 640 MGETHDR(m, M_DONTWAIT, MT_DATA); 641 if (m == NULL) { 642 printf("%s: unable to allocate Tx mbuf\n", 643 device_xname(sc->sc_dev)); 644 break; 645 } 646 if (m0->m_pkthdr.len > MHLEN) { 647 MCLGET(m, M_DONTWAIT); 648 if ((m->m_flags & M_EXT) == 0) { 649 printf("%s: unable to allocate Tx " 650 "cluster\n", 651 device_xname(sc->sc_dev)); 652 m_freem(m); 653 break; 654 } 655 } 656 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 657 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 658 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 659 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 660 if (error) { 661 printf("%s: unable to load Tx buffer, " 662 "error = %d\n", device_xname(sc->sc_dev), 663 error); 664 break; 665 } 666 } 667 668 IFQ_DEQUEUE(&ifp->if_snd, m0); 669 if (m != NULL) { 670 m_freem(m0); 671 m0 = m; 672 } 673 674 /* 675 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 676 */ 677 678 /* Sync the DMA map. */ 679 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 680 BUS_DMASYNC_PREWRITE); 681 682 /* Initialize the fragment list. */ 683 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 684 tfd->tfd_frags[seg].frag_addr = 685 htole32(dmamap->dm_segs[seg].ds_addr); 686 tfd->tfd_frags[seg].frag_len = 687 htole32(dmamap->dm_segs[seg].ds_len); 688 totlen += dmamap->dm_segs[seg].ds_len; 689 } 690 tfd->tfd_frags[seg - 1].frag_len |= htole32(FRAG_LAST); 691 692 /* Initialize the descriptor. */ 693 tfd->tfd_next = htole32(STE_CDTXADDR(sc, nexttx)); 694 tfd->tfd_control = htole32(TFD_FrameId(nexttx) | (totlen & 3)); 695 696 /* Sync the descriptor. */ 697 STE_CDTXSYNC(sc, nexttx, 698 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 699 700 /* 701 * Store a pointer to the packet so we can free it later, 702 * and remember what txdirty will be once the packet is 703 * done. 704 */ 705 ds->ds_mbuf = m0; 706 707 /* Advance the tx pointer. */ 708 sc->sc_txpending++; 709 sc->sc_txlast = nexttx; 710 711 /* 712 * Pass the packet to any BPF listeners. 713 */ 714 bpf_mtap(ifp, m0, BPF_D_OUT); 715 } 716 717 if (sc->sc_txpending == STE_NTXDESC) { 718 /* No more slots left; notify upper layer. */ 719 ifp->if_flags |= IFF_OACTIVE; 720 } 721 722 if (sc->sc_txpending != opending) { 723 /* 724 * We enqueued packets. If the transmitter was idle, 725 * reset the txdirty pointer. 726 */ 727 if (opending == 0) 728 sc->sc_txdirty = STE_NEXTTX(olasttx); 729 730 /* 731 * Cause a descriptor interrupt to happen on the 732 * last packet we enqueued, and also cause the 733 * DMA engine to wait after is has finished processing 734 * it. 735 */ 736 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; 737 sc->sc_txdescs[sc->sc_txlast].tfd_control |= 738 htole32(TFD_TxDMAIndicate); 739 STE_CDTXSYNC(sc, sc->sc_txlast, 740 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 741 742 /* 743 * Link up the new chain of descriptors to the 744 * last. 745 */ 746 sc->sc_txdescs[olasttx].tfd_next = 747 htole32(STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 748 STE_CDTXSYNC(sc, olasttx, 749 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 750 751 /* 752 * Kick the transmit DMA logic. Note that since we're 753 * using auto-polling, reading the Tx desc pointer will 754 * give it the nudge it needs to get going. 755 */ 756 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 757 STE_TxDMAListPtr) == 0) { 758 bus_space_write_4(sc->sc_st, sc->sc_sh, 759 STE_DMACtrl, DC_TxDMAHalt); 760 ste_dmahalt_wait(sc); 761 bus_space_write_4(sc->sc_st, sc->sc_sh, 762 STE_TxDMAListPtr, 763 STE_CDTXADDR(sc, STE_NEXTTX(olasttx))); 764 bus_space_write_4(sc->sc_st, sc->sc_sh, 765 STE_DMACtrl, DC_TxDMAResume); 766 } 767 768 /* Set a watchdog timer in case the chip flakes out. */ 769 ifp->if_timer = 5; 770 } 771 } 772 773 /* 774 * ste_watchdog: [ifnet interface function] 775 * 776 * Watchdog timer handler. 777 */ 778 static void 779 ste_watchdog(struct ifnet *ifp) 780 { 781 struct ste_softc *sc = ifp->if_softc; 782 783 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 784 if_statinc(ifp, if_oerrors); 785 786 ste_txintr(sc); 787 ste_rxintr(sc); 788 (void) ste_init(ifp); 789 790 /* Try to get more packets going. */ 791 ste_start(ifp); 792 } 793 794 /* 795 * ste_ioctl: [ifnet interface function] 796 * 797 * Handle control requests from the operator. 798 */ 799 static int 800 ste_ioctl(struct ifnet *ifp, u_long cmd, void *data) 801 { 802 struct ste_softc *sc = ifp->if_softc; 803 int s, error; 804 805 s = splnet(); 806 807 error = ether_ioctl(ifp, cmd, data); 808 if (error == ENETRESET) { 809 /* 810 * Multicast list has changed; set the hardware filter 811 * accordingly. 812 */ 813 if (ifp->if_flags & IFF_RUNNING) 814 ste_set_filter(sc); 815 error = 0; 816 } 817 818 /* Try to get more packets going. */ 819 ste_start(ifp); 820 821 splx(s); 822 return (error); 823 } 824 825 /* 826 * ste_intr: 827 * 828 * Interrupt service routine. 829 */ 830 static int 831 ste_intr(void *arg) 832 { 833 struct ste_softc *sc = arg; 834 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 835 uint16_t isr; 836 uint8_t txstat; 837 int wantinit; 838 839 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatus) & 840 IS_InterruptStatus) == 0) 841 return (0); 842 843 for (wantinit = 0; wantinit == 0;) { 844 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_IntStatusAck); 845 if ((isr & sc->sc_IntEnable) == 0) 846 break; 847 848 /* Receive interrupts. */ 849 if (isr & IE_RxDMAComplete) 850 ste_rxintr(sc); 851 852 /* Transmit interrupts. */ 853 if (isr & (IE_TxDMAComplete | IE_TxComplete)) 854 ste_txintr(sc); 855 856 /* Statistics overflow. */ 857 if (isr & IE_UpdateStats) 858 ste_stats_update(sc); 859 860 /* Transmission errors. */ 861 if (isr & IE_TxComplete) { 862 for (;;) { 863 txstat = bus_space_read_1(sc->sc_st, sc->sc_sh, 864 STE_TxStatus); 865 if ((txstat & TS_TxComplete) == 0) 866 break; 867 if (txstat & TS_TxUnderrun) { 868 sc->sc_txthresh += 32; 869 if (sc->sc_txthresh > 0x1ffc) 870 sc->sc_txthresh = 0x1ffc; 871 printf("%s: transmit underrun, new " 872 "threshold: %d bytes\n", 873 device_xname(sc->sc_dev), 874 sc->sc_txthresh); 875 ste_reset(sc, AC_TxReset | AC_DMA | 876 AC_FIFO | AC_Network); 877 ste_setthresh(sc); 878 bus_space_write_1(sc->sc_st, sc->sc_sh, 879 STE_TxDMAPollPeriod, 127); 880 ste_txrestart(sc, 881 bus_space_read_1(sc->sc_st, 882 sc->sc_sh, STE_TxFrameId)); 883 } 884 if (txstat & TS_TxReleaseError) { 885 printf("%s: Tx FIFO release error\n", 886 device_xname(sc->sc_dev)); 887 wantinit = 1; 888 } 889 if (txstat & TS_MaxCollisions) { 890 printf("%s: excessive collisions\n", 891 device_xname(sc->sc_dev)); 892 wantinit = 1; 893 } 894 if (txstat & TS_TxStatusOverflow) { 895 printf("%s: status overflow\n", 896 device_xname(sc->sc_dev)); 897 wantinit = 1; 898 } 899 bus_space_write_2(sc->sc_st, sc->sc_sh, 900 STE_TxStatus, 0); 901 } 902 } 903 904 /* Host interface errors. */ 905 if (isr & IE_HostError) { 906 printf("%s: Host interface error\n", 907 device_xname(sc->sc_dev)); 908 wantinit = 1; 909 } 910 } 911 912 if (wantinit) 913 ste_init(ifp); 914 915 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 916 sc->sc_IntEnable); 917 918 /* Try to get more packets going. */ 919 if_schedule_deferred_start(ifp); 920 921 return (1); 922 } 923 924 /* 925 * ste_txintr: 926 * 927 * Helper; handle transmit interrupts. 928 */ 929 static void 930 ste_txintr(struct ste_softc *sc) 931 { 932 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 933 struct ste_descsoft *ds; 934 uint32_t control; 935 int i; 936 937 ifp->if_flags &= ~IFF_OACTIVE; 938 939 /* 940 * Go through our Tx list and free mbufs for those 941 * frames which have been transmitted. 942 */ 943 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 944 i = STE_NEXTTX(i), sc->sc_txpending--) { 945 ds = &sc->sc_txsoft[i]; 946 947 STE_CDTXSYNC(sc, i, 948 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 949 950 control = le32toh(sc->sc_txdescs[i].tfd_control); 951 if ((control & TFD_TxDMAComplete) == 0) 952 break; 953 954 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 955 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 956 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 957 m_freem(ds->ds_mbuf); 958 ds->ds_mbuf = NULL; 959 } 960 961 /* Update the dirty transmit buffer pointer. */ 962 sc->sc_txdirty = i; 963 964 /* 965 * If there are no more pending transmissions, cancel the watchdog 966 * timer. 967 */ 968 if (sc->sc_txpending == 0) 969 ifp->if_timer = 0; 970 } 971 972 /* 973 * ste_rxintr: 974 * 975 * Helper; handle receive interrupts. 976 */ 977 static void 978 ste_rxintr(struct ste_softc *sc) 979 { 980 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 981 struct ste_descsoft *ds; 982 struct mbuf *m; 983 uint32_t status; 984 int i, len; 985 986 for (i = sc->sc_rxptr;; i = STE_NEXTRX(i)) { 987 ds = &sc->sc_rxsoft[i]; 988 989 STE_CDRXSYNC(sc, i, 990 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 991 992 status = le32toh(sc->sc_rxdescs[i].rfd_status); 993 994 if ((status & RFD_RxDMAComplete) == 0) 995 break; 996 997 /* 998 * If the packet had an error, simply recycle the 999 * buffer. Note, we count the error later in the 1000 * periodic stats update. 1001 */ 1002 if (status & RFD_RxFrameError) { 1003 STE_INIT_RXDESC(sc, i); 1004 continue; 1005 } 1006 1007 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1008 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1009 1010 /* 1011 * No errors; receive the packet. Note, we have 1012 * configured the chip to not include the CRC at 1013 * the end of the packet. 1014 */ 1015 len = RFD_RxDMAFrameLen(status); 1016 1017 /* 1018 * If the packet is small enough to fit in a 1019 * single header mbuf, allocate one and copy 1020 * the data into it. This greatly reduces 1021 * memory consumption when we receive lots 1022 * of small packets. 1023 * 1024 * Otherwise, we add a new buffer to the receive 1025 * chain. If this fails, we drop the packet and 1026 * recycle the old buffer. 1027 */ 1028 if (ste_copy_small != 0 && len <= (MHLEN - 2)) { 1029 MGETHDR(m, M_DONTWAIT, MT_DATA); 1030 if (m == NULL) 1031 goto dropit; 1032 m->m_data += 2; 1033 memcpy(mtod(m, void *), 1034 mtod(ds->ds_mbuf, void *), len); 1035 STE_INIT_RXDESC(sc, i); 1036 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1037 ds->ds_dmamap->dm_mapsize, 1038 BUS_DMASYNC_PREREAD); 1039 } else { 1040 m = ds->ds_mbuf; 1041 if (ste_add_rxbuf(sc, i) != 0) { 1042 dropit: 1043 if_statinc(ifp, if_ierrors); 1044 STE_INIT_RXDESC(sc, i); 1045 bus_dmamap_sync(sc->sc_dmat, 1046 ds->ds_dmamap, 0, 1047 ds->ds_dmamap->dm_mapsize, 1048 BUS_DMASYNC_PREREAD); 1049 continue; 1050 } 1051 } 1052 1053 m_set_rcvif(m, ifp); 1054 m->m_pkthdr.len = m->m_len = len; 1055 1056 /* Pass it on. */ 1057 if_percpuq_enqueue(ifp->if_percpuq, m); 1058 } 1059 1060 /* Update the receive pointer. */ 1061 sc->sc_rxptr = i; 1062 } 1063 1064 /* 1065 * ste_tick: 1066 * 1067 * One second timer, used to tick the MII. 1068 */ 1069 static void 1070 ste_tick(void *arg) 1071 { 1072 struct ste_softc *sc = arg; 1073 int s; 1074 1075 s = splnet(); 1076 mii_tick(&sc->sc_mii); 1077 ste_stats_update(sc); 1078 splx(s); 1079 1080 callout_schedule(&sc->sc_tick_ch, hz); 1081 } 1082 1083 /* 1084 * ste_stats_update: 1085 * 1086 * Read the ST-201 statistics counters. 1087 */ 1088 static void 1089 ste_stats_update(struct ste_softc *sc) 1090 { 1091 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1092 bus_space_tag_t st = sc->sc_st; 1093 bus_space_handle_t sh = sc->sc_sh; 1094 1095 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk0); 1096 (void) bus_space_read_2(st, sh, STE_OctetsReceivedOk1); 1097 1098 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk0); 1099 (void) bus_space_read_2(st, sh, STE_OctetsTransmittedOk1); 1100 1101 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1102 1103 if_statadd_ref(nsr, if_opackets, 1104 (u_int) bus_space_read_2(st, sh, STE_FramesTransmittedOK)); 1105 1106 (void) bus_space_read_2(st, sh, STE_FramesReceivedOK); 1107 1108 if_statadd_ref(nsr, if_collisions, 1109 (u_int) bus_space_read_1(st, sh, STE_LateCollisions) + 1110 (u_int) bus_space_read_1(st, sh, STE_MultipleColFrames) + 1111 (u_int) bus_space_read_1(st, sh, STE_SingleColFrames)); 1112 1113 (void) bus_space_read_1(st, sh, STE_FramesWDeferredXmt); 1114 1115 if_statadd_ref(nsr, if_ierrors, 1116 (u_int) bus_space_read_1(st, sh, STE_FramesLostRxErrors)); 1117 1118 if_statadd_ref(nsr, if_oerrors, 1119 (u_int) bus_space_read_1(st, sh, STE_FramesWExDeferral) + 1120 (u_int) bus_space_read_1(st, sh, STE_FramesXbortXSColls) + 1121 bus_space_read_1(st, sh, STE_CarrierSenseErrors)); 1122 1123 IF_STAT_PUTREF(ifp); 1124 1125 (void) bus_space_read_1(st, sh, STE_BcstFramesXmtdOk); 1126 (void) bus_space_read_1(st, sh, STE_BcstFramesRcvdOk); 1127 (void) bus_space_read_1(st, sh, STE_McstFramesXmtdOk); 1128 (void) bus_space_read_1(st, sh, STE_McstFramesRcvdOk); 1129 } 1130 1131 /* 1132 * ste_reset: 1133 * 1134 * Perform a soft reset on the ST-201. 1135 */ 1136 static void 1137 ste_reset(struct ste_softc *sc, uint32_t rstbits) 1138 { 1139 uint32_t ac; 1140 int i; 1141 1142 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl); 1143 1144 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl, ac | rstbits); 1145 1146 delay(50000); 1147 1148 for (i = 0; i < STE_TIMEOUT; i++) { 1149 delay(1000); 1150 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STE_AsicCtrl) & 1151 AC_ResetBusy) == 0) 1152 break; 1153 } 1154 1155 if (i == STE_TIMEOUT) 1156 printf("%s: reset failed to complete\n", 1157 device_xname(sc->sc_dev)); 1158 1159 delay(1000); 1160 } 1161 1162 /* 1163 * ste_setthresh: 1164 * 1165 * set the various transmit threshold registers 1166 */ 1167 static void 1168 ste_setthresh(struct ste_softc *sc) 1169 { 1170 /* set the TX threhold */ 1171 bus_space_write_2(sc->sc_st, sc->sc_sh, 1172 STE_TxStartThresh, sc->sc_txthresh); 1173 /* Urgent threshold: set to sc_txthresh / 2 */ 1174 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_TxDMAUrgentThresh, 1175 sc->sc_txthresh >> 6); 1176 /* Burst threshold: use default value (256 bytes) */ 1177 } 1178 1179 /* 1180 * restart TX at the given frame ID in the transmitter ring 1181 */ 1182 static void 1183 ste_txrestart(struct ste_softc *sc, uint8_t id) 1184 { 1185 uint32_t control; 1186 1187 STE_CDTXSYNC(sc, id, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1188 control = le32toh(sc->sc_txdescs[id].tfd_control); 1189 control &= ~TFD_TxDMAComplete; 1190 sc->sc_txdescs[id].tfd_control = htole32(control); 1191 STE_CDTXSYNC(sc, id, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1192 1193 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 0); 1194 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, MC1_TxEnable); 1195 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAHalt); 1196 ste_dmahalt_wait(sc); 1197 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_TxDMAListPtr, 1198 STE_CDTXADDR(sc, id)); 1199 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, DC_TxDMAResume); 1200 } 1201 1202 /* 1203 * ste_init: [ ifnet interface function ] 1204 * 1205 * Initialize the interface. Must be called at splnet(). 1206 */ 1207 static int 1208 ste_init(struct ifnet *ifp) 1209 { 1210 struct ste_softc *sc = ifp->if_softc; 1211 bus_space_tag_t st = sc->sc_st; 1212 bus_space_handle_t sh = sc->sc_sh; 1213 struct ste_descsoft *ds; 1214 int i, error = 0; 1215 1216 /* 1217 * Cancel any pending I/O. 1218 */ 1219 ste_stop(ifp, 0); 1220 1221 /* 1222 * Reset the chip to a known state. 1223 */ 1224 ste_reset(sc, AC_GlobalReset | AC_RxReset | AC_TxReset | AC_DMA | 1225 AC_FIFO | AC_Network | AC_Host | AC_AutoInit | AC_RstOut); 1226 1227 /* 1228 * Initialize the transmit descriptor ring. 1229 */ 1230 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1231 sc->sc_txpending = 0; 1232 sc->sc_txdirty = 0; 1233 sc->sc_txlast = STE_NTXDESC - 1; 1234 1235 /* 1236 * Initialize the receive descriptor and receive job 1237 * descriptor rings. 1238 */ 1239 for (i = 0; i < STE_NRXDESC; i++) { 1240 ds = &sc->sc_rxsoft[i]; 1241 if (ds->ds_mbuf == NULL) { 1242 if ((error = ste_add_rxbuf(sc, i)) != 0) { 1243 printf("%s: unable to allocate or map rx " 1244 "buffer %d, error = %d\n", 1245 device_xname(sc->sc_dev), i, error); 1246 /* 1247 * XXX Should attempt to run with fewer receive 1248 * XXX buffers instead of just failing. 1249 */ 1250 ste_rxdrain(sc); 1251 goto out; 1252 } 1253 } else 1254 STE_INIT_RXDESC(sc, i); 1255 } 1256 sc->sc_rxptr = 0; 1257 1258 /* Set the station address. */ 1259 for (i = 0; i < ETHER_ADDR_LEN; i++) 1260 bus_space_write_1(st, sh, STE_StationAddress0 + 1, 1261 CLLADDR(ifp->if_sadl)[i]); 1262 1263 /* Set up the receive filter. */ 1264 ste_set_filter(sc); 1265 1266 /* 1267 * Give the receive ring to the chip. 1268 */ 1269 bus_space_write_4(st, sh, STE_RxDMAListPtr, 1270 STE_CDRXADDR(sc, sc->sc_rxptr)); 1271 1272 /* 1273 * We defer giving the transmit ring to the chip until we 1274 * transmit the first packet. 1275 */ 1276 1277 /* 1278 * Initialize the Tx auto-poll period. It's OK to make this number 1279 * large (127 is the max) -- we explicitly kick the transmit engine 1280 * when there's actually a packet. We are using auto-polling only 1281 * to make the interface to the transmit engine not suck. 1282 */ 1283 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_TxDMAPollPeriod, 127); 1284 1285 /* ..and the Rx auto-poll period. */ 1286 bus_space_write_1(st, sh, STE_RxDMAPollPeriod, 64); 1287 1288 /* Initialize the Tx start threshold. */ 1289 ste_setthresh(sc); 1290 1291 /* Set the FIFO release threshold to 512 bytes. */ 1292 bus_space_write_1(st, sh, STE_TxReleaseThresh, 512 >> 4); 1293 1294 /* Set maximum packet size for VLAN. */ 1295 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1296 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN + 4); 1297 else 1298 bus_space_write_2(st, sh, STE_MaxFrameSize, ETHER_MAX_LEN); 1299 1300 /* 1301 * Initialize the interrupt mask. 1302 */ 1303 sc->sc_IntEnable = IE_HostError | IE_TxComplete | IE_UpdateStats | 1304 IE_TxDMAComplete | IE_RxDMAComplete; 1305 1306 bus_space_write_2(st, sh, STE_IntStatus, 0xffff); 1307 bus_space_write_2(st, sh, STE_IntEnable, sc->sc_IntEnable); 1308 1309 /* 1310 * Start the receive DMA engine. 1311 */ 1312 bus_space_write_4(st, sh, STE_DMACtrl, sc->sc_DMACtrl | DC_RxDMAResume); 1313 1314 /* 1315 * Initialize MacCtrl0 -- do it before setting the media, 1316 * as setting the media will actually program the register. 1317 */ 1318 sc->sc_MacCtrl0 = MC0_IFSSelect(0); 1319 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1320 sc->sc_MacCtrl0 |= MC0_RcvLargeFrames; 1321 1322 /* 1323 * Set the current media. 1324 */ 1325 if ((error = ether_mediachange(ifp)) != 0) 1326 goto out; 1327 1328 /* 1329 * Start the MAC. 1330 */ 1331 bus_space_write_2(st, sh, STE_MacCtrl1, 1332 MC1_StatisticsEnable | MC1_TxEnable | MC1_RxEnable); 1333 1334 /* 1335 * Start the one second MII clock. 1336 */ 1337 callout_schedule(&sc->sc_tick_ch, hz); 1338 1339 /* 1340 * ...all done! 1341 */ 1342 ifp->if_flags |= IFF_RUNNING; 1343 ifp->if_flags &= ~IFF_OACTIVE; 1344 1345 out: 1346 if (error) 1347 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1348 return (error); 1349 } 1350 1351 /* 1352 * ste_drain: 1353 * 1354 * Drain the receive queue. 1355 */ 1356 static void 1357 ste_rxdrain(struct ste_softc *sc) 1358 { 1359 struct ste_descsoft *ds; 1360 int i; 1361 1362 for (i = 0; i < STE_NRXDESC; i++) { 1363 ds = &sc->sc_rxsoft[i]; 1364 if (ds->ds_mbuf != NULL) { 1365 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1366 m_freem(ds->ds_mbuf); 1367 ds->ds_mbuf = NULL; 1368 } 1369 } 1370 } 1371 1372 /* 1373 * ste_stop: [ ifnet interface function ] 1374 * 1375 * Stop transmission on the interface. 1376 */ 1377 static void 1378 ste_stop(struct ifnet *ifp, int disable) 1379 { 1380 struct ste_softc *sc = ifp->if_softc; 1381 struct ste_descsoft *ds; 1382 int i; 1383 1384 /* 1385 * Stop the one second clock. 1386 */ 1387 callout_stop(&sc->sc_tick_ch); 1388 1389 /* Down the MII. */ 1390 mii_down(&sc->sc_mii); 1391 1392 /* 1393 * Disable interrupts. 1394 */ 1395 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_IntEnable, 0); 1396 1397 /* 1398 * Stop receiver, transmitter, and stats update. 1399 */ 1400 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl1, 1401 MC1_StatisticsDisable | MC1_TxDisable | MC1_RxDisable); 1402 1403 /* 1404 * Stop the transmit and receive DMA. 1405 */ 1406 bus_space_write_4(sc->sc_st, sc->sc_sh, STE_DMACtrl, 1407 DC_RxDMAHalt | DC_TxDMAHalt); 1408 ste_dmahalt_wait(sc); 1409 1410 /* 1411 * Release any queued transmit buffers. 1412 */ 1413 for (i = 0; i < STE_NTXDESC; i++) { 1414 ds = &sc->sc_txsoft[i]; 1415 if (ds->ds_mbuf != NULL) { 1416 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1417 m_freem(ds->ds_mbuf); 1418 ds->ds_mbuf = NULL; 1419 } 1420 } 1421 1422 /* 1423 * Mark the interface down and cancel the watchdog timer. 1424 */ 1425 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1426 ifp->if_timer = 0; 1427 1428 if (disable) 1429 ste_rxdrain(sc); 1430 } 1431 1432 static int 1433 ste_eeprom_wait(struct ste_softc *sc) 1434 { 1435 int i; 1436 1437 for (i = 0; i < STE_TIMEOUT; i++) { 1438 delay(1000); 1439 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl) & 1440 EC_EepromBusy) == 0) 1441 return (0); 1442 } 1443 return (1); 1444 } 1445 1446 /* 1447 * ste_read_eeprom: 1448 * 1449 * Read data from the serial EEPROM. 1450 */ 1451 static void 1452 ste_read_eeprom(struct ste_softc *sc, int offset, uint16_t *data) 1453 { 1454 1455 if (ste_eeprom_wait(sc)) 1456 printf("%s: EEPROM failed to come ready\n", 1457 device_xname(sc->sc_dev)); 1458 1459 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_EepromCtrl, 1460 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_R)); 1461 if (ste_eeprom_wait(sc)) 1462 printf("%s: EEPROM read timed out\n", 1463 device_xname(sc->sc_dev)); 1464 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STE_EepromData); 1465 } 1466 1467 /* 1468 * ste_add_rxbuf: 1469 * 1470 * Add a receive buffer to the indicated descriptor. 1471 */ 1472 static int 1473 ste_add_rxbuf(struct ste_softc *sc, int idx) 1474 { 1475 struct ste_descsoft *ds = &sc->sc_rxsoft[idx]; 1476 struct mbuf *m; 1477 int error; 1478 1479 MGETHDR(m, M_DONTWAIT, MT_DATA); 1480 if (m == NULL) 1481 return (ENOBUFS); 1482 1483 MCLGET(m, M_DONTWAIT); 1484 if ((m->m_flags & M_EXT) == 0) { 1485 m_freem(m); 1486 return (ENOBUFS); 1487 } 1488 1489 if (ds->ds_mbuf != NULL) 1490 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1491 1492 ds->ds_mbuf = m; 1493 1494 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1495 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1496 BUS_DMA_READ | BUS_DMA_NOWAIT); 1497 if (error) { 1498 printf("%s: can't load rx DMA map %d, error = %d\n", 1499 device_xname(sc->sc_dev), idx, error); 1500 panic("ste_add_rxbuf"); /* XXX */ 1501 } 1502 1503 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1504 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1505 1506 STE_INIT_RXDESC(sc, idx); 1507 1508 return (0); 1509 } 1510 1511 /* 1512 * ste_set_filter: 1513 * 1514 * Set up the receive filter. 1515 */ 1516 static void 1517 ste_set_filter(struct ste_softc *sc) 1518 { 1519 struct ethercom *ec = &sc->sc_ethercom; 1520 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1521 struct ether_multi *enm; 1522 struct ether_multistep step; 1523 uint32_t crc; 1524 uint16_t mchash[4]; 1525 1526 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1527 if (ifp->if_flags & IFF_BROADCAST) 1528 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1529 1530 if (ifp->if_flags & IFF_PROMISC) { 1531 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1532 goto allmulti; 1533 } 1534 1535 /* 1536 * Set up the multicast address filter by passing all multicast 1537 * addresses through a CRC generator, and then using the low-order 1538 * 6 bits as an index into the 64 bit multicast hash table. The 1539 * high order bits select the register, while the rest of the bits 1540 * select the bit within the register. 1541 */ 1542 1543 memset(mchash, 0, sizeof(mchash)); 1544 1545 ETHER_LOCK(ec); 1546 ETHER_FIRST_MULTI(step, ec, enm); 1547 if (enm == NULL) { 1548 ETHER_UNLOCK(ec); 1549 goto done; 1550 } 1551 1552 while (enm != NULL) { 1553 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1554 /* 1555 * We must listen to a range of multicast addresses. 1556 * For now, just accept all multicasts, rather than 1557 * trying to set only those filter bits needed to match 1558 * the range. (At this time, the only use of address 1559 * ranges is for IP multicast routing, for which the 1560 * range is big enough to require all bits set.) 1561 */ 1562 ETHER_UNLOCK(ec); 1563 goto allmulti; 1564 } 1565 1566 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1567 1568 /* Just want the 6 least significant bits. */ 1569 crc &= 0x3f; 1570 1571 /* Set the corresponding bit in the hash table. */ 1572 mchash[crc >> 4] |= 1 << (crc & 0xf); 1573 1574 ETHER_NEXT_MULTI(step, enm); 1575 } 1576 ETHER_UNLOCK(ec); 1577 1578 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1579 1580 ifp->if_flags &= ~IFF_ALLMULTI; 1581 goto done; 1582 1583 allmulti: 1584 ifp->if_flags |= IFF_ALLMULTI; 1585 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1586 1587 done: 1588 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1589 /* 1590 * Program the multicast hash table. 1591 */ 1592 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable0, 1593 mchash[0]); 1594 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable1, 1595 mchash[1]); 1596 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable2, 1597 mchash[2]); 1598 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_HashTable3, 1599 mchash[3]); 1600 } 1601 1602 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_ReceiveMode, 1603 sc->sc_ReceiveMode); 1604 } 1605 1606 /* 1607 * ste_mii_readreg: [mii interface function] 1608 * 1609 * Read a PHY register on the MII of the ST-201. 1610 */ 1611 static int 1612 ste_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1613 { 1614 1615 return mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg, val); 1616 } 1617 1618 /* 1619 * ste_mii_writereg: [mii interface function] 1620 * 1621 * Write a PHY register on the MII of the ST-201. 1622 */ 1623 static int 1624 ste_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1625 { 1626 1627 return mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val); 1628 } 1629 1630 /* 1631 * ste_mii_statchg: [mii interface function] 1632 * 1633 * Callback from MII layer when media changes. 1634 */ 1635 static void 1636 ste_mii_statchg(struct ifnet *ifp) 1637 { 1638 struct ste_softc *sc = ifp->if_softc; 1639 1640 if (sc->sc_mii.mii_media_active & IFM_FDX) 1641 sc->sc_MacCtrl0 |= MC0_FullDuplexEnable; 1642 else 1643 sc->sc_MacCtrl0 &= ~MC0_FullDuplexEnable; 1644 1645 /* XXX 802.1x flow-control? */ 1646 1647 bus_space_write_2(sc->sc_st, sc->sc_sh, STE_MacCtrl0, sc->sc_MacCtrl0); 1648 } 1649 1650 /* 1651 * ste_mii_bitbang_read: [mii bit-bang interface function] 1652 * 1653 * Read the MII serial port for the MII bit-bang module. 1654 */ 1655 static uint32_t 1656 ste_mii_bitbang_read(device_t self) 1657 { 1658 struct ste_softc *sc = device_private(self); 1659 1660 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl)); 1661 } 1662 1663 /* 1664 * ste_mii_bitbang_write: [mii big-bang interface function] 1665 * 1666 * Write the MII serial port for the MII bit-bang module. 1667 */ 1668 static void 1669 ste_mii_bitbang_write(device_t self, uint32_t val) 1670 { 1671 struct ste_softc *sc = device_private(self); 1672 1673 bus_space_write_1(sc->sc_st, sc->sc_sh, STE_PhyCtrl, val); 1674 } 1675
Indexes created Thu Oct 02 01:09:59 GMT 2025