if_stge.c revision 1.22
1 /* $NetBSD: if_stge.c,v 1.22 2004/10/30 18:09:22 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the Sundance Tech. TC9021 10/100/1000 41 * Ethernet controller. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.22 2004/10/30 18:09:22 thorpej Exp $"); 46 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/callout.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 #include <sys/queue.h> 60 61 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <machine/bus.h> 73 #include <machine/intr.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 #include <dev/mii/mii_bitbang.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <dev/pci/if_stgereg.h> 84 85 /* #define STGE_CU_BUG 1 */ 86 #define STGE_VLAN_UNTAG 1 87 /* #define STGE_VLAN_CFI 1 */ 88 89 /* 90 * Transmit descriptor list size. 91 */ 92 #define STGE_NTXDESC 256 93 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 94 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 95 96 /* 97 * Receive descriptor list size. 98 */ 99 #define STGE_NRXDESC 256 100 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 101 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 102 103 /* 104 * Only interrupt every N frames. Must be a power-of-two. 105 */ 106 #define STGE_TXINTR_SPACING 16 107 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 108 109 /* 110 * Control structures are DMA'd to the TC9021 chip. We allocate them in 111 * a single clump that maps to a single DMA segment to make several things 112 * easier. 113 */ 114 struct stge_control_data { 115 /* 116 * The transmit descriptors. 117 */ 118 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 119 120 /* 121 * The receive descriptors. 122 */ 123 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 124 }; 125 126 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 127 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 128 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 129 130 /* 131 * Software state for transmit and receive jobs. 132 */ 133 struct stge_descsoft { 134 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 135 bus_dmamap_t ds_dmamap; /* our DMA map */ 136 }; 137 138 /* 139 * Software state per device. 140 */ 141 struct stge_softc { 142 struct device sc_dev; /* generic device information */ 143 bus_space_tag_t sc_st; /* bus space tag */ 144 bus_space_handle_t sc_sh; /* bus space handle */ 145 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 146 struct ethercom sc_ethercom; /* ethernet common data */ 147 void *sc_sdhook; /* shutdown hook */ 148 int sc_rev; /* silicon revision */ 149 150 void *sc_ih; /* interrupt cookie */ 151 152 struct mii_data sc_mii; /* MII/media information */ 153 154 struct callout sc_tick_ch; /* tick callout */ 155 156 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 157 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 158 159 /* 160 * Software state for transmit and receive descriptors. 161 */ 162 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 163 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 164 165 /* 166 * Control data structures. 167 */ 168 struct stge_control_data *sc_control_data; 169 #define sc_txdescs sc_control_data->scd_txdescs 170 #define sc_rxdescs sc_control_data->scd_rxdescs 171 172 #ifdef STGE_EVENT_COUNTERS 173 /* 174 * Event counters. 175 */ 176 struct evcnt sc_ev_txstall; /* Tx stalled */ 177 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 178 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 179 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 180 181 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 182 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 183 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 184 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 185 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 186 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 187 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 188 189 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 190 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 191 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 192 193 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 194 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 195 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 196 #endif /* STGE_EVENT_COUNTERS */ 197 198 int sc_txpending; /* number of Tx requests pending */ 199 int sc_txdirty; /* first dirty Tx descriptor */ 200 int sc_txlast; /* last used Tx descriptor */ 201 202 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 203 int sc_rxdiscard; 204 int sc_rxlen; 205 struct mbuf *sc_rxhead; 206 struct mbuf *sc_rxtail; 207 struct mbuf **sc_rxtailp; 208 209 int sc_txthresh; /* Tx threshold */ 210 int sc_usefiber; /* if we're fiber */ 211 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 212 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 213 uint16_t sc_IntEnable; /* prototype IntEnable register */ 214 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 215 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 216 }; 217 218 #define STGE_RXCHAIN_RESET(sc) \ 219 do { \ 220 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 221 *(sc)->sc_rxtailp = NULL; \ 222 (sc)->sc_rxlen = 0; \ 223 } while (/*CONSTCOND*/0) 224 225 #define STGE_RXCHAIN_LINK(sc, m) \ 226 do { \ 227 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 228 (sc)->sc_rxtailp = &(m)->m_next; \ 229 } while (/*CONSTCOND*/0) 230 231 #ifdef STGE_EVENT_COUNTERS 232 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 233 #else 234 #define STGE_EVCNT_INCR(ev) /* nothing */ 235 #endif 236 237 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 238 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 239 240 #define STGE_CDTXSYNC(sc, x, ops) \ 241 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 242 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 243 244 #define STGE_CDRXSYNC(sc, x, ops) \ 245 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 246 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 247 248 #define STGE_INIT_RXDESC(sc, x) \ 249 do { \ 250 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 251 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 252 \ 253 /* \ 254 * Note: We scoot the packet forward 2 bytes in the buffer \ 255 * so that the payload after the Ethernet header is aligned \ 256 * to a 4-byte boundary. \ 257 */ \ 258 __rfd->rfd_frag.frag_word0 = \ 259 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 260 FRAG_LEN(MCLBYTES - 2)); \ 261 __rfd->rfd_next = \ 262 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 263 __rfd->rfd_status = 0; \ 264 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 265 } while (/*CONSTCOND*/0) 266 267 #define STGE_TIMEOUT 1000 268 269 static void stge_start(struct ifnet *); 270 static void stge_watchdog(struct ifnet *); 271 static int stge_ioctl(struct ifnet *, u_long, caddr_t); 272 static int stge_init(struct ifnet *); 273 static void stge_stop(struct ifnet *, int); 274 275 static void stge_shutdown(void *); 276 277 static void stge_reset(struct stge_softc *); 278 static void stge_rxdrain(struct stge_softc *); 279 static int stge_add_rxbuf(struct stge_softc *, int); 280 #if 0 281 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 282 #endif 283 static void stge_tick(void *); 284 285 static void stge_stats_update(struct stge_softc *); 286 287 static void stge_set_filter(struct stge_softc *); 288 289 static int stge_intr(void *); 290 static void stge_txintr(struct stge_softc *); 291 static void stge_rxintr(struct stge_softc *); 292 293 static int stge_mii_readreg(struct device *, int, int); 294 static void stge_mii_writereg(struct device *, int, int, int); 295 static void stge_mii_statchg(struct device *); 296 297 static int stge_mediachange(struct ifnet *); 298 static void stge_mediastatus(struct ifnet *, struct ifmediareq *); 299 300 static int stge_match(struct device *, struct cfdata *, void *); 301 static void stge_attach(struct device *, struct device *, void *); 302 303 int stge_copy_small = 0; 304 305 CFATTACH_DECL(stge, sizeof(struct stge_softc), 306 stge_match, stge_attach, NULL, NULL); 307 308 static uint32_t stge_mii_bitbang_read(struct device *); 309 static void stge_mii_bitbang_write(struct device *, uint32_t); 310 311 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 312 stge_mii_bitbang_read, 313 stge_mii_bitbang_write, 314 { 315 PC_MgmtData, /* MII_BIT_MDO */ 316 PC_MgmtData, /* MII_BIT_MDI */ 317 PC_MgmtClk, /* MII_BIT_MDC */ 318 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 319 0, /* MII_BIT_DIR_PHY_HOST */ 320 } 321 }; 322 323 /* 324 * Devices supported by this driver. 325 */ 326 static const struct stge_product { 327 pci_vendor_id_t stge_vendor; 328 pci_product_id_t stge_product; 329 const char *stge_name; 330 } stge_products[] = { 331 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 332 "Sundance ST-2021 Gigabit Ethernet" }, 333 334 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 335 "Tamarack TC9021 Gigabit Ethernet" }, 336 337 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 338 "Tamarack TC9021 Gigabit Ethernet" }, 339 340 /* 341 * The Sundance sample boards use the Sundance vendor ID, 342 * but the Tamarack product ID. 343 */ 344 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 345 "Sundance TC9021 Gigabit Ethernet" }, 346 347 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 348 "Sundance TC9021 Gigabit Ethernet" }, 349 350 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 351 "D-Link DL-4000 Gigabit Ethernet" }, 352 353 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 354 "Antares Gigabit Ethernet" }, 355 356 { 0, 0, 357 NULL }, 358 }; 359 360 static const struct stge_product * 361 stge_lookup(const struct pci_attach_args *pa) 362 { 363 const struct stge_product *sp; 364 365 for (sp = stge_products; sp->stge_name != NULL; sp++) { 366 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 367 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 368 return (sp); 369 } 370 return (NULL); 371 } 372 373 static int 374 stge_match(struct device *parent, struct cfdata *cf, void *aux) 375 { 376 struct pci_attach_args *pa = aux; 377 378 if (stge_lookup(pa) != NULL) 379 return (1); 380 381 return (0); 382 } 383 384 static void 385 stge_attach(struct device *parent, struct device *self, void *aux) 386 { 387 struct stge_softc *sc = (struct stge_softc *) self; 388 struct pci_attach_args *pa = aux; 389 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 390 pci_chipset_tag_t pc = pa->pa_pc; 391 pci_intr_handle_t ih; 392 const char *intrstr = NULL; 393 bus_space_tag_t iot, memt; 394 bus_space_handle_t ioh, memh; 395 bus_dma_segment_t seg; 396 int ioh_valid, memh_valid; 397 int i, rseg, error; 398 const struct stge_product *sp; 399 pcireg_t pmode; 400 uint8_t enaddr[ETHER_ADDR_LEN]; 401 int pmreg; 402 403 callout_init(&sc->sc_tick_ch); 404 405 sp = stge_lookup(pa); 406 if (sp == NULL) { 407 printf("\n"); 408 panic("ste_attach: impossible"); 409 } 410 411 sc->sc_rev = PCI_REVISION(pa->pa_class); 412 413 printf(": %s, rev. %d\n", sp->stge_name, sc->sc_rev); 414 415 /* 416 * Map the device. 417 */ 418 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 419 PCI_MAPREG_TYPE_IO, 0, 420 &iot, &ioh, NULL, NULL) == 0); 421 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 422 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 423 &memt, &memh, NULL, NULL) == 0); 424 425 if (memh_valid) { 426 sc->sc_st = memt; 427 sc->sc_sh = memh; 428 } else if (ioh_valid) { 429 sc->sc_st = iot; 430 sc->sc_sh = ioh; 431 } else { 432 printf("%s: unable to map device registers\n", 433 sc->sc_dev.dv_xname); 434 return; 435 } 436 437 sc->sc_dmat = pa->pa_dmat; 438 439 /* Enable bus mastering. */ 440 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 441 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 442 PCI_COMMAND_MASTER_ENABLE); 443 444 /* Get it out of power save mode if needed. */ 445 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 446 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 447 PCI_PMCSR_STATE_MASK; 448 if (pmode == PCI_PMCSR_STATE_D3) { 449 /* 450 * The card has lost all configuration data in 451 * this state, so punt. 452 */ 453 printf("%s: unable to wake up from power state D3\n", 454 sc->sc_dev.dv_xname); 455 return; 456 } 457 if (pmode != 0) { 458 printf("%s: waking up from power state D%d\n", 459 sc->sc_dev.dv_xname, pmode); 460 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 461 PCI_PMCSR_STATE_D0); 462 } 463 } 464 465 /* 466 * Map and establish our interrupt. 467 */ 468 if (pci_intr_map(pa, &ih)) { 469 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 470 return; 471 } 472 intrstr = pci_intr_string(pc, ih); 473 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc); 474 if (sc->sc_ih == NULL) { 475 printf("%s: unable to establish interrupt", 476 sc->sc_dev.dv_xname); 477 if (intrstr != NULL) 478 printf(" at %s", intrstr); 479 printf("\n"); 480 return; 481 } 482 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 483 484 /* 485 * Allocate the control data structures, and create and load the 486 * DMA map for it. 487 */ 488 if ((error = bus_dmamem_alloc(sc->sc_dmat, 489 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 490 0)) != 0) { 491 printf("%s: unable to allocate control data, error = %d\n", 492 sc->sc_dev.dv_xname, error); 493 goto fail_0; 494 } 495 496 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 497 sizeof(struct stge_control_data), (caddr_t *)&sc->sc_control_data, 498 BUS_DMA_COHERENT)) != 0) { 499 printf("%s: unable to map control data, error = %d\n", 500 sc->sc_dev.dv_xname, error); 501 goto fail_1; 502 } 503 504 if ((error = bus_dmamap_create(sc->sc_dmat, 505 sizeof(struct stge_control_data), 1, 506 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 507 printf("%s: unable to create control data DMA map, " 508 "error = %d\n", sc->sc_dev.dv_xname, error); 509 goto fail_2; 510 } 511 512 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 513 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 514 0)) != 0) { 515 printf("%s: unable to load control data DMA map, error = %d\n", 516 sc->sc_dev.dv_xname, error); 517 goto fail_3; 518 } 519 520 /* 521 * Create the transmit buffer DMA maps. Note that rev B.3 522 * and earlier seem to have a bug regarding multi-fragment 523 * packets. We need to limit the number of Tx segments on 524 * such chips to 1. 525 */ 526 for (i = 0; i < STGE_NTXDESC; i++) { 527 if ((error = bus_dmamap_create(sc->sc_dmat, 528 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 529 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 530 printf("%s: unable to create tx DMA map %d, " 531 "error = %d\n", sc->sc_dev.dv_xname, i, error); 532 goto fail_4; 533 } 534 } 535 536 /* 537 * Create the receive buffer DMA maps. 538 */ 539 for (i = 0; i < STGE_NRXDESC; i++) { 540 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 541 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 542 printf("%s: unable to create rx DMA map %d, " 543 "error = %d\n", sc->sc_dev.dv_xname, i, error); 544 goto fail_5; 545 } 546 sc->sc_rxsoft[i].ds_mbuf = NULL; 547 } 548 549 /* 550 * Determine if we're copper or fiber. It affects how we 551 * reset the card. 552 */ 553 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 554 AC_PhyMedia) 555 sc->sc_usefiber = 1; 556 else 557 sc->sc_usefiber = 0; 558 559 /* 560 * Reset the chip to a known state. 561 */ 562 stge_reset(sc); 563 564 /* 565 * Reading the station address from the EEPROM doesn't seem 566 * to work, at least on my sample boards. Instread, since 567 * the reset sequence does AutoInit, read it from the station 568 * address registers. 569 */ 570 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 571 STGE_StationAddress0) & 0xff; 572 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 573 STGE_StationAddress0) >> 8; 574 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 575 STGE_StationAddress1) & 0xff; 576 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 577 STGE_StationAddress1) >> 8; 578 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 579 STGE_StationAddress2) & 0xff; 580 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 581 STGE_StationAddress2) >> 8; 582 583 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 584 ether_sprintf(enaddr)); 585 586 /* 587 * Read some important bits from the PhyCtrl register. 588 */ 589 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 590 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 591 592 /* 593 * Initialize our media structures and probe the MII. 594 */ 595 sc->sc_mii.mii_ifp = ifp; 596 sc->sc_mii.mii_readreg = stge_mii_readreg; 597 sc->sc_mii.mii_writereg = stge_mii_writereg; 598 sc->sc_mii.mii_statchg = stge_mii_statchg; 599 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, stge_mediachange, 600 stge_mediastatus); 601 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 602 MII_OFFSET_ANY, MIIF_DOPAUSE); 603 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 604 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 605 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 606 } else 607 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 608 609 ifp = &sc->sc_ethercom.ec_if; 610 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 611 ifp->if_softc = sc; 612 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 613 ifp->if_ioctl = stge_ioctl; 614 ifp->if_start = stge_start; 615 ifp->if_watchdog = stge_watchdog; 616 ifp->if_init = stge_init; 617 ifp->if_stop = stge_stop; 618 IFQ_SET_READY(&ifp->if_snd); 619 620 /* 621 * The manual recommends disabling early transmit, so we 622 * do. It's disabled anyway, if using IP checksumming, 623 * since the entire packet must be in the FIFO in order 624 * for the chip to perform the checksum. 625 */ 626 sc->sc_txthresh = 0x0fff; 627 628 /* 629 * Disable MWI if the PCI layer tells us to. 630 */ 631 sc->sc_DMACtrl = 0; 632 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 633 sc->sc_DMACtrl |= DMAC_MWIDisable; 634 635 /* 636 * We can support 802.1Q VLAN-sized frames and jumbo 637 * Ethernet frames. 638 * 639 * XXX Figure out how to do hw-assisted VLAN tagging in 640 * XXX a reasonable way on this chip. 641 */ 642 sc->sc_ethercom.ec_capabilities |= 643 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 644 ETHERCAP_VLAN_HWTAGGING; 645 646 /* 647 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 648 */ 649 sc->sc_ethercom.ec_if.if_capabilities |= IFCAP_CSUM_IPv4 | 650 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 651 652 /* 653 * Attach the interface. 654 */ 655 if_attach(ifp); 656 ether_ifattach(ifp, enaddr); 657 658 #ifdef STGE_EVENT_COUNTERS 659 /* 660 * Attach event counters. 661 */ 662 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 663 NULL, sc->sc_dev.dv_xname, "txstall"); 664 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 665 NULL, sc->sc_dev.dv_xname, "txdmaintr"); 666 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 667 NULL, sc->sc_dev.dv_xname, "txindintr"); 668 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 669 NULL, sc->sc_dev.dv_xname, "rxintr"); 670 671 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 672 NULL, sc->sc_dev.dv_xname, "txseg1"); 673 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 674 NULL, sc->sc_dev.dv_xname, "txseg2"); 675 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 676 NULL, sc->sc_dev.dv_xname, "txseg3"); 677 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 678 NULL, sc->sc_dev.dv_xname, "txseg4"); 679 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 680 NULL, sc->sc_dev.dv_xname, "txseg5"); 681 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 682 NULL, sc->sc_dev.dv_xname, "txsegmore"); 683 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 684 NULL, sc->sc_dev.dv_xname, "txcopy"); 685 686 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 687 NULL, sc->sc_dev.dv_xname, "rxipsum"); 688 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 689 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 690 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 691 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 692 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 693 NULL, sc->sc_dev.dv_xname, "txipsum"); 694 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 695 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 696 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 697 NULL, sc->sc_dev.dv_xname, "txudpsum"); 698 #endif /* STGE_EVENT_COUNTERS */ 699 700 /* 701 * Make sure the interface is shutdown during reboot. 702 */ 703 sc->sc_sdhook = shutdownhook_establish(stge_shutdown, sc); 704 if (sc->sc_sdhook == NULL) 705 printf("%s: WARNING: unable to establish shutdown hook\n", 706 sc->sc_dev.dv_xname); 707 return; 708 709 /* 710 * Free any resources we've allocated during the failed attach 711 * attempt. Do this in reverse order and fall through. 712 */ 713 fail_5: 714 for (i = 0; i < STGE_NRXDESC; i++) { 715 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 716 bus_dmamap_destroy(sc->sc_dmat, 717 sc->sc_rxsoft[i].ds_dmamap); 718 } 719 fail_4: 720 for (i = 0; i < STGE_NTXDESC; i++) { 721 if (sc->sc_txsoft[i].ds_dmamap != NULL) 722 bus_dmamap_destroy(sc->sc_dmat, 723 sc->sc_txsoft[i].ds_dmamap); 724 } 725 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 726 fail_3: 727 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 728 fail_2: 729 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 730 sizeof(struct stge_control_data)); 731 fail_1: 732 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 733 fail_0: 734 return; 735 } 736 737 /* 738 * stge_shutdown: 739 * 740 * Make sure the interface is stopped at reboot time. 741 */ 742 static void 743 stge_shutdown(void *arg) 744 { 745 struct stge_softc *sc = arg; 746 747 stge_stop(&sc->sc_ethercom.ec_if, 1); 748 } 749 750 static void 751 stge_dma_wait(struct stge_softc *sc) 752 { 753 int i; 754 755 for (i = 0; i < STGE_TIMEOUT; i++) { 756 delay(2); 757 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 758 DMAC_TxDMAInProg) == 0) 759 break; 760 } 761 762 if (i == STGE_TIMEOUT) 763 printf("%s: DMA wait timed out\n", sc->sc_dev.dv_xname); 764 } 765 766 /* 767 * stge_start: [ifnet interface function] 768 * 769 * Start packet transmission on the interface. 770 */ 771 static void 772 stge_start(struct ifnet *ifp) 773 { 774 struct stge_softc *sc = ifp->if_softc; 775 struct mbuf *m0; 776 struct stge_descsoft *ds; 777 struct stge_tfd *tfd; 778 bus_dmamap_t dmamap; 779 int error, firsttx, nexttx, opending, seg, totlen; 780 uint64_t csum_flags; 781 782 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 783 return; 784 785 /* 786 * Remember the previous number of pending transmissions 787 * and the first descriptor we will use. 788 */ 789 opending = sc->sc_txpending; 790 firsttx = STGE_NEXTTX(sc->sc_txlast); 791 792 /* 793 * Loop through the send queue, setting up transmit descriptors 794 * until we drain the queue, or use up all available transmit 795 * descriptors. 796 */ 797 for (;;) { 798 struct m_tag *mtag; 799 uint64_t tfc; 800 801 /* 802 * Grab a packet off the queue. 803 */ 804 IFQ_POLL(&ifp->if_snd, m0); 805 if (m0 == NULL) 806 break; 807 808 /* 809 * Leave one unused descriptor at the end of the 810 * list to prevent wrapping completely around. 811 */ 812 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 813 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 814 break; 815 } 816 817 /* 818 * See if we have any VLAN stuff. 819 */ 820 mtag = sc->sc_ethercom.ec_nvlans ? 821 m_tag_find(m0, PACKET_TAG_VLAN, NULL) : NULL; 822 823 /* 824 * Get the last and next available transmit descriptor. 825 */ 826 nexttx = STGE_NEXTTX(sc->sc_txlast); 827 tfd = &sc->sc_txdescs[nexttx]; 828 ds = &sc->sc_txsoft[nexttx]; 829 830 dmamap = ds->ds_dmamap; 831 832 /* 833 * Load the DMA map. If this fails, the packet either 834 * didn't fit in the alloted number of segments, or we 835 * were short on resources. For the too-many-segments 836 * case, we simply report an error and drop the packet, 837 * since we can't sanely copy a jumbo packet to a single 838 * buffer. 839 */ 840 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 841 BUS_DMA_NOWAIT); 842 if (error) { 843 if (error == EFBIG) { 844 printf("%s: Tx packet consumes too many " 845 "DMA segments, dropping...\n", 846 sc->sc_dev.dv_xname); 847 IFQ_DEQUEUE(&ifp->if_snd, m0); 848 m_freem(m0); 849 continue; 850 } 851 /* 852 * Short on resources, just stop for now. 853 */ 854 break; 855 } 856 857 IFQ_DEQUEUE(&ifp->if_snd, m0); 858 859 /* 860 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 861 */ 862 863 /* Sync the DMA map. */ 864 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 865 BUS_DMASYNC_PREWRITE); 866 867 /* Initialize the fragment list. */ 868 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 869 tfd->tfd_frags[seg].frag_word0 = 870 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 871 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 872 totlen += dmamap->dm_segs[seg].ds_len; 873 } 874 875 #ifdef STGE_EVENT_COUNTERS 876 switch (dmamap->dm_nsegs) { 877 case 1: 878 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 879 break; 880 case 2: 881 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 882 break; 883 case 3: 884 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 885 break; 886 case 4: 887 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 888 break; 889 case 5: 890 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 891 break; 892 default: 893 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 894 break; 895 } 896 #endif /* STGE_EVENT_COUNTERS */ 897 898 /* 899 * Initialize checksumming flags in the descriptor. 900 * Byte-swap constants so the compiler can optimize. 901 */ 902 csum_flags = 0; 903 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 904 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 905 csum_flags |= htole64(TFD_IPChecksumEnable); 906 } 907 908 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 909 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 910 csum_flags |= htole64(TFD_TCPChecksumEnable); 911 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 912 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 913 csum_flags |= htole64(TFD_UDPChecksumEnable); 914 } 915 916 /* 917 * Initialize the descriptor and give it to the chip. 918 * Check to see if we have a VLAN tag to insert. 919 */ 920 921 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 922 TFD_FragCount(seg) | csum_flags | 923 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 924 TFD_TxDMAIndicate : 0); 925 if (mtag) { 926 #if 0 927 struct ether_header *eh = 928 mtod(m0, struct ether_header *); 929 u_int16_t etype = ntohs(eh->ether_type); 930 printf("%s: xmit (tag %d) etype %x\n", 931 ifp->if_xname, *mtod(n, int *), etype); 932 #endif 933 tfc |= TFD_VLANTagInsert | 934 #ifdef STGE_VLAN_CFI 935 TFD_CFI | 936 #endif 937 TFD_VID((*(u_int *)(mtag + 1))); 938 } 939 tfd->tfd_control = htole64(tfc); 940 941 /* Sync the descriptor. */ 942 STGE_CDTXSYNC(sc, nexttx, 943 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 944 945 /* 946 * Kick the transmit DMA logic. 947 */ 948 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 949 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 950 951 /* 952 * Store a pointer to the packet so we can free it later. 953 */ 954 ds->ds_mbuf = m0; 955 956 /* Advance the tx pointer. */ 957 sc->sc_txpending++; 958 sc->sc_txlast = nexttx; 959 960 #if NBPFILTER > 0 961 /* 962 * Pass the packet to any BPF listeners. 963 */ 964 if (ifp->if_bpf) 965 bpf_mtap(ifp->if_bpf, m0); 966 #endif /* NBPFILTER > 0 */ 967 } 968 969 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 970 /* No more slots left; notify upper layer. */ 971 ifp->if_flags |= IFF_OACTIVE; 972 } 973 974 if (sc->sc_txpending != opending) { 975 /* 976 * We enqueued packets. If the transmitter was idle, 977 * reset the txdirty pointer. 978 */ 979 if (opending == 0) 980 sc->sc_txdirty = firsttx; 981 982 /* Set a watchdog timer in case the chip flakes out. */ 983 ifp->if_timer = 5; 984 } 985 } 986 987 /* 988 * stge_watchdog: [ifnet interface function] 989 * 990 * Watchdog timer handler. 991 */ 992 static void 993 stge_watchdog(struct ifnet *ifp) 994 { 995 struct stge_softc *sc = ifp->if_softc; 996 997 /* 998 * Sweep up first, since we don't interrupt every frame. 999 */ 1000 stge_txintr(sc); 1001 if (sc->sc_txpending != 0) { 1002 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1003 ifp->if_oerrors++; 1004 1005 (void) stge_init(ifp); 1006 1007 /* Try to get more packets going. */ 1008 stge_start(ifp); 1009 } 1010 } 1011 1012 /* 1013 * stge_ioctl: [ifnet interface function] 1014 * 1015 * Handle control requests from the operator. 1016 */ 1017 static int 1018 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1019 { 1020 struct stge_softc *sc = ifp->if_softc; 1021 struct ifreq *ifr = (struct ifreq *)data; 1022 int s, error; 1023 1024 s = splnet(); 1025 1026 switch (cmd) { 1027 case SIOCSIFMEDIA: 1028 case SIOCGIFMEDIA: 1029 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1030 break; 1031 1032 default: 1033 error = ether_ioctl(ifp, cmd, data); 1034 if (error == ENETRESET) { 1035 /* 1036 * Multicast list has changed; set the hardware filter 1037 * accordingly. 1038 */ 1039 if (ifp->if_flags & IFF_RUNNING) 1040 stge_set_filter(sc); 1041 error = 0; 1042 } 1043 break; 1044 } 1045 1046 /* Try to get more packets going. */ 1047 stge_start(ifp); 1048 1049 splx(s); 1050 return (error); 1051 } 1052 1053 /* 1054 * stge_intr: 1055 * 1056 * Interrupt service routine. 1057 */ 1058 static int 1059 stge_intr(void *arg) 1060 { 1061 struct stge_softc *sc = arg; 1062 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1063 uint32_t txstat; 1064 int wantinit; 1065 uint16_t isr; 1066 1067 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1068 IS_InterruptStatus) == 0) 1069 return (0); 1070 1071 for (wantinit = 0; wantinit == 0;) { 1072 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1073 if ((isr & sc->sc_IntEnable) == 0) 1074 break; 1075 1076 /* Host interface errors. */ 1077 if (isr & IS_HostError) { 1078 printf("%s: Host interface error\n", 1079 sc->sc_dev.dv_xname); 1080 wantinit = 1; 1081 continue; 1082 } 1083 1084 /* Receive interrupts. */ 1085 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) { 1086 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1087 stge_rxintr(sc); 1088 if (isr & IS_RFDListEnd) { 1089 printf("%s: receive ring overflow\n", 1090 sc->sc_dev.dv_xname); 1091 /* 1092 * XXX Should try to recover from this 1093 * XXX more gracefully. 1094 */ 1095 wantinit = 1; 1096 } 1097 } 1098 1099 /* Transmit interrupts. */ 1100 if (isr & (IS_TxDMAComplete|IS_TxComplete)) { 1101 #ifdef STGE_EVENT_COUNTERS 1102 if (isr & IS_TxDMAComplete) 1103 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1104 #endif 1105 stge_txintr(sc); 1106 } 1107 1108 /* Statistics overflow. */ 1109 if (isr & IS_UpdateStats) 1110 stge_stats_update(sc); 1111 1112 /* Transmission errors. */ 1113 if (isr & IS_TxComplete) { 1114 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1115 for (;;) { 1116 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1117 STGE_TxStatus); 1118 if ((txstat & TS_TxComplete) == 0) 1119 break; 1120 if (txstat & TS_TxUnderrun) { 1121 sc->sc_txthresh++; 1122 if (sc->sc_txthresh > 0x0fff) 1123 sc->sc_txthresh = 0x0fff; 1124 printf("%s: transmit underrun, new " 1125 "threshold: %d bytes\n", 1126 sc->sc_dev.dv_xname, 1127 sc->sc_txthresh << 5); 1128 } 1129 if (txstat & TS_MaxCollisions) 1130 printf("%s: excessive collisions\n", 1131 sc->sc_dev.dv_xname); 1132 } 1133 wantinit = 1; 1134 } 1135 1136 } 1137 1138 if (wantinit) 1139 stge_init(ifp); 1140 1141 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1142 sc->sc_IntEnable); 1143 1144 /* Try to get more packets going. */ 1145 stge_start(ifp); 1146 1147 return (1); 1148 } 1149 1150 /* 1151 * stge_txintr: 1152 * 1153 * Helper; handle transmit interrupts. 1154 */ 1155 static void 1156 stge_txintr(struct stge_softc *sc) 1157 { 1158 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1159 struct stge_descsoft *ds; 1160 uint64_t control; 1161 int i; 1162 1163 ifp->if_flags &= ~IFF_OACTIVE; 1164 1165 /* 1166 * Go through our Tx list and free mbufs for those 1167 * frames which have been transmitted. 1168 */ 1169 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1170 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1171 ds = &sc->sc_txsoft[i]; 1172 1173 STGE_CDTXSYNC(sc, i, 1174 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1175 1176 control = le64toh(sc->sc_txdescs[i].tfd_control); 1177 if ((control & TFD_TFDDone) == 0) 1178 break; 1179 1180 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1181 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1182 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1183 m_freem(ds->ds_mbuf); 1184 ds->ds_mbuf = NULL; 1185 } 1186 1187 /* Update the dirty transmit buffer pointer. */ 1188 sc->sc_txdirty = i; 1189 1190 /* 1191 * If there are no more pending transmissions, cancel the watchdog 1192 * timer. 1193 */ 1194 if (sc->sc_txpending == 0) 1195 ifp->if_timer = 0; 1196 } 1197 1198 /* 1199 * stge_rxintr: 1200 * 1201 * Helper; handle receive interrupts. 1202 */ 1203 static void 1204 stge_rxintr(struct stge_softc *sc) 1205 { 1206 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1207 struct stge_descsoft *ds; 1208 struct mbuf *m, *tailm; 1209 uint64_t status; 1210 int i, len; 1211 1212 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1213 ds = &sc->sc_rxsoft[i]; 1214 1215 STGE_CDRXSYNC(sc, i, 1216 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1217 1218 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1219 1220 if ((status & RFD_RFDDone) == 0) 1221 break; 1222 1223 if (__predict_false(sc->sc_rxdiscard)) { 1224 STGE_INIT_RXDESC(sc, i); 1225 if (status & RFD_FrameEnd) { 1226 /* Reset our state. */ 1227 sc->sc_rxdiscard = 0; 1228 } 1229 continue; 1230 } 1231 1232 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1233 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1234 1235 m = ds->ds_mbuf; 1236 1237 /* 1238 * Add a new receive buffer to the ring. 1239 */ 1240 if (stge_add_rxbuf(sc, i) != 0) { 1241 /* 1242 * Failed, throw away what we've done so 1243 * far, and discard the rest of the packet. 1244 */ 1245 ifp->if_ierrors++; 1246 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1247 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1248 STGE_INIT_RXDESC(sc, i); 1249 if ((status & RFD_FrameEnd) == 0) 1250 sc->sc_rxdiscard = 1; 1251 if (sc->sc_rxhead != NULL) 1252 m_freem(sc->sc_rxhead); 1253 STGE_RXCHAIN_RESET(sc); 1254 continue; 1255 } 1256 1257 #ifdef DIAGNOSTIC 1258 if (status & RFD_FrameStart) { 1259 KASSERT(sc->sc_rxhead == NULL); 1260 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1261 } 1262 #endif 1263 1264 STGE_RXCHAIN_LINK(sc, m); 1265 1266 /* 1267 * If this is not the end of the packet, keep 1268 * looking. 1269 */ 1270 if ((status & RFD_FrameEnd) == 0) { 1271 sc->sc_rxlen += m->m_len; 1272 continue; 1273 } 1274 1275 /* 1276 * Okay, we have the entire packet now... 1277 */ 1278 *sc->sc_rxtailp = NULL; 1279 m = sc->sc_rxhead; 1280 tailm = sc->sc_rxtail; 1281 1282 STGE_RXCHAIN_RESET(sc); 1283 1284 /* 1285 * If the packet had an error, drop it. Note we 1286 * count the error later in the periodic stats update. 1287 */ 1288 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1289 RFD_RxAlignmentError | RFD_RxFCSError | 1290 RFD_RxLengthError)) { 1291 m_freem(m); 1292 continue; 1293 } 1294 1295 /* 1296 * No errors. 1297 * 1298 * Note we have configured the chip to not include 1299 * the CRC at the end of the packet. 1300 */ 1301 len = RFD_RxDMAFrameLen(status); 1302 tailm->m_len = len - sc->sc_rxlen; 1303 1304 /* 1305 * If the packet is small enough to fit in a 1306 * single header mbuf, allocate one and copy 1307 * the data into it. This greatly reduces 1308 * memory consumption when we receive lots 1309 * of small packets. 1310 */ 1311 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1312 struct mbuf *nm; 1313 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1314 if (nm == NULL) { 1315 ifp->if_ierrors++; 1316 m_freem(m); 1317 continue; 1318 } 1319 nm->m_data += 2; 1320 nm->m_pkthdr.len = nm->m_len = len; 1321 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1322 m_freem(m); 1323 m = nm; 1324 } 1325 1326 /* 1327 * Set the incoming checksum information for the packet. 1328 */ 1329 if (status & RFD_IPDetected) { 1330 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1331 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1332 if (status & RFD_IPError) 1333 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1334 if (status & RFD_TCPDetected) { 1335 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1336 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1337 if (status & RFD_TCPError) 1338 m->m_pkthdr.csum_flags |= 1339 M_CSUM_TCP_UDP_BAD; 1340 } else if (status & RFD_UDPDetected) { 1341 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1342 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1343 if (status & RFD_UDPError) 1344 m->m_pkthdr.csum_flags |= 1345 M_CSUM_TCP_UDP_BAD; 1346 } 1347 } 1348 1349 m->m_pkthdr.rcvif = ifp; 1350 m->m_pkthdr.len = len; 1351 1352 #if NBPFILTER > 0 1353 /* 1354 * Pass this up to any BPF listeners, but only 1355 * pass if up the stack if it's for us. 1356 */ 1357 if (ifp->if_bpf) 1358 bpf_mtap(ifp->if_bpf, m); 1359 #endif /* NBPFILTER > 0 */ 1360 #ifdef STGE_VLAN_UNTAG 1361 /* 1362 * Check for VLAN tagged packets 1363 */ 1364 if (status & RFD_VLANDetected) { 1365 struct m_tag *mtag = 1366 m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1367 if (mtag == NULL) { 1368 printf("%s: no mbuf for VLAN tag\n", 1369 ifp->if_xname); 1370 m_freem(m); 1371 continue; 1372 } 1373 *(u_int *)(mtag + 1) = RFD_TCI(status); 1374 m_tag_prepend(m, mtag); 1375 } 1376 #endif 1377 #if 0 1378 if (status & RFD_VLANDetected) { 1379 struct ether_header *eh; 1380 u_int16_t etype; 1381 1382 eh = mtod(m, struct ether_header *); 1383 etype = ntohs(eh->ether_type); 1384 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1385 ifp->if_xname, (u_int16_t) RFD_TCI(status), 1386 etype); 1387 } 1388 #endif 1389 /* Pass it on. */ 1390 (*ifp->if_input)(ifp, m); 1391 } 1392 1393 /* Update the receive pointer. */ 1394 sc->sc_rxptr = i; 1395 } 1396 1397 /* 1398 * stge_tick: 1399 * 1400 * One second timer, used to tick the MII. 1401 */ 1402 static void 1403 stge_tick(void *arg) 1404 { 1405 struct stge_softc *sc = arg; 1406 int s; 1407 1408 s = splnet(); 1409 mii_tick(&sc->sc_mii); 1410 stge_stats_update(sc); 1411 splx(s); 1412 1413 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1414 } 1415 1416 /* 1417 * stge_stats_update: 1418 * 1419 * Read the TC9021 statistics counters. 1420 */ 1421 static void 1422 stge_stats_update(struct stge_softc *sc) 1423 { 1424 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1425 bus_space_tag_t st = sc->sc_st; 1426 bus_space_handle_t sh = sc->sc_sh; 1427 1428 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1429 1430 ifp->if_ipackets += 1431 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1432 1433 ifp->if_ierrors += 1434 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1435 1436 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1437 1438 ifp->if_opackets += 1439 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1440 1441 ifp->if_collisions += 1442 bus_space_read_4(st, sh, STGE_LateCollisions) + 1443 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1444 bus_space_read_4(st, sh, STGE_SingleColFrames); 1445 1446 ifp->if_oerrors += 1447 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1448 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1449 } 1450 1451 /* 1452 * stge_reset: 1453 * 1454 * Perform a soft reset on the TC9021. 1455 */ 1456 static void 1457 stge_reset(struct stge_softc *sc) 1458 { 1459 uint32_t ac; 1460 int i; 1461 1462 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1463 1464 /* 1465 * Only assert RstOut if we're fiber. We need GMII clocks 1466 * to be present in order for the reset to complete on fiber 1467 * cards. 1468 */ 1469 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1470 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1471 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1472 (sc->sc_usefiber ? AC_RstOut : 0)); 1473 1474 delay(50000); 1475 1476 for (i = 0; i < STGE_TIMEOUT; i++) { 1477 delay(5000); 1478 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1479 AC_ResetBusy) == 0) 1480 break; 1481 } 1482 1483 if (i == STGE_TIMEOUT) 1484 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1485 1486 delay(1000); 1487 } 1488 1489 /* 1490 * stge_init: [ ifnet interface function ] 1491 * 1492 * Initialize the interface. Must be called at splnet(). 1493 */ 1494 static int 1495 stge_init(struct ifnet *ifp) 1496 { 1497 struct stge_softc *sc = ifp->if_softc; 1498 bus_space_tag_t st = sc->sc_st; 1499 bus_space_handle_t sh = sc->sc_sh; 1500 struct stge_descsoft *ds; 1501 int i, error = 0; 1502 1503 /* 1504 * Cancel any pending I/O. 1505 */ 1506 stge_stop(ifp, 0); 1507 1508 /* 1509 * Reset the chip to a known state. 1510 */ 1511 stge_reset(sc); 1512 1513 /* 1514 * Initialize the transmit descriptor ring. 1515 */ 1516 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1517 for (i = 0; i < STGE_NTXDESC; i++) { 1518 sc->sc_txdescs[i].tfd_next = 1519 (uint64_t) STGE_CDTXADDR(sc, STGE_NEXTTX(i)); 1520 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1521 } 1522 sc->sc_txpending = 0; 1523 sc->sc_txdirty = 0; 1524 sc->sc_txlast = STGE_NTXDESC - 1; 1525 1526 /* 1527 * Initialize the receive descriptor and receive job 1528 * descriptor rings. 1529 */ 1530 for (i = 0; i < STGE_NRXDESC; i++) { 1531 ds = &sc->sc_rxsoft[i]; 1532 if (ds->ds_mbuf == NULL) { 1533 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1534 printf("%s: unable to allocate or map rx " 1535 "buffer %d, error = %d\n", 1536 sc->sc_dev.dv_xname, i, error); 1537 /* 1538 * XXX Should attempt to run with fewer receive 1539 * XXX buffers instead of just failing. 1540 */ 1541 stge_rxdrain(sc); 1542 goto out; 1543 } 1544 } else 1545 STGE_INIT_RXDESC(sc, i); 1546 } 1547 sc->sc_rxptr = 0; 1548 sc->sc_rxdiscard = 0; 1549 STGE_RXCHAIN_RESET(sc); 1550 1551 /* Set the station address. */ 1552 bus_space_write_2(st, sh, STGE_StationAddress0, 1553 LLADDR(ifp->if_sadl)[0] | (LLADDR(ifp->if_sadl)[1] << 8)); 1554 bus_space_write_2(st, sh, STGE_StationAddress1, 1555 LLADDR(ifp->if_sadl)[2] | (LLADDR(ifp->if_sadl)[3] << 8)); 1556 bus_space_write_2(st, sh, STGE_StationAddress2, 1557 LLADDR(ifp->if_sadl)[4] | (LLADDR(ifp->if_sadl)[5] << 8)); 1558 1559 /* 1560 * Set the statistics masks. Disable all the RMON stats, 1561 * and disable selected stats in the non-RMON stats registers. 1562 */ 1563 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1564 bus_space_write_4(st, sh, STGE_StatisticsMask, 1565 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1566 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1567 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1568 (1U << 21)); 1569 1570 /* Set up the receive filter. */ 1571 stge_set_filter(sc); 1572 1573 /* 1574 * Give the transmit and receive ring to the chip. 1575 */ 1576 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1577 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1578 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1579 1580 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1581 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1582 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1583 1584 /* 1585 * Initialize the Tx auto-poll period. It's OK to make this number 1586 * large (255 is the max, but we use 127) -- we explicitly kick the 1587 * transmit engine when there's actually a packet. 1588 */ 1589 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1590 1591 /* ..and the Rx auto-poll period. */ 1592 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1593 1594 /* Initialize the Tx start threshold. */ 1595 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1596 1597 /* 1598 * Initialize the Rx DMA interrupt control register. We 1599 * request an interrupt after every incoming packet, but 1600 * defer it for 32us (64 * 512 ns). When the number of 1601 * interrupts pending reaches 8, we stop deferring the 1602 * interrupt, and signal it immediately. 1603 */ 1604 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1605 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1606 1607 /* 1608 * Initialize the interrupt mask. 1609 */ 1610 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1611 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1612 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1613 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1614 1615 /* 1616 * Configure the DMA engine. 1617 * XXX Should auto-tune TxBurstLimit. 1618 */ 1619 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1620 DMAC_TxBurstLimit(3)); 1621 1622 /* 1623 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1624 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1625 * empty again. 1626 */ 1627 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1628 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1629 1630 /* 1631 * Set the maximum frame size. 1632 */ 1633 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1634 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1635 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1636 ETHER_VLAN_ENCAP_LEN : 0)); 1637 1638 /* 1639 * Initialize MacCtrl -- do it before setting the media, 1640 * as setting the media will actually program the register. 1641 * 1642 * Note: We have to poke the IFS value before poking 1643 * anything else. 1644 */ 1645 sc->sc_MACCtrl = MC_IFSSelect(0); 1646 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1647 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1648 #ifdef STGE_VLAN_UNTAG 1649 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1650 #endif 1651 1652 if (sc->sc_rev >= 6) { /* >= B.2 */ 1653 /* Multi-frag frame bug work-around. */ 1654 bus_space_write_2(st, sh, STGE_DebugCtrl, 1655 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1656 1657 /* Tx Poll Now bug work-around. */ 1658 bus_space_write_2(st, sh, STGE_DebugCtrl, 1659 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1660 } 1661 1662 /* 1663 * Set the current media. 1664 */ 1665 mii_mediachg(&sc->sc_mii); 1666 1667 /* 1668 * Start the one second MII clock. 1669 */ 1670 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1671 1672 /* 1673 * ...all done! 1674 */ 1675 ifp->if_flags |= IFF_RUNNING; 1676 ifp->if_flags &= ~IFF_OACTIVE; 1677 1678 out: 1679 if (error) 1680 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1681 return (error); 1682 } 1683 1684 /* 1685 * stge_drain: 1686 * 1687 * Drain the receive queue. 1688 */ 1689 static void 1690 stge_rxdrain(struct stge_softc *sc) 1691 { 1692 struct stge_descsoft *ds; 1693 int i; 1694 1695 for (i = 0; i < STGE_NRXDESC; i++) { 1696 ds = &sc->sc_rxsoft[i]; 1697 if (ds->ds_mbuf != NULL) { 1698 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1699 ds->ds_mbuf->m_next = NULL; 1700 m_freem(ds->ds_mbuf); 1701 ds->ds_mbuf = NULL; 1702 } 1703 } 1704 } 1705 1706 /* 1707 * stge_stop: [ ifnet interface function ] 1708 * 1709 * Stop transmission on the interface. 1710 */ 1711 static void 1712 stge_stop(struct ifnet *ifp, int disable) 1713 { 1714 struct stge_softc *sc = ifp->if_softc; 1715 struct stge_descsoft *ds; 1716 int i; 1717 1718 /* 1719 * Stop the one second clock. 1720 */ 1721 callout_stop(&sc->sc_tick_ch); 1722 1723 /* Down the MII. */ 1724 mii_down(&sc->sc_mii); 1725 1726 /* 1727 * Disable interrupts. 1728 */ 1729 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1730 1731 /* 1732 * Stop receiver, transmitter, and stats update. 1733 */ 1734 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1735 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1736 1737 /* 1738 * Stop the transmit and receive DMA. 1739 */ 1740 stge_dma_wait(sc); 1741 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1742 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1743 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1744 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1745 1746 /* 1747 * Release any queued transmit buffers. 1748 */ 1749 for (i = 0; i < STGE_NTXDESC; i++) { 1750 ds = &sc->sc_txsoft[i]; 1751 if (ds->ds_mbuf != NULL) { 1752 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1753 m_freem(ds->ds_mbuf); 1754 ds->ds_mbuf = NULL; 1755 } 1756 } 1757 1758 if (disable) 1759 stge_rxdrain(sc); 1760 1761 /* 1762 * Mark the interface down and cancel the watchdog timer. 1763 */ 1764 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1765 ifp->if_timer = 0; 1766 } 1767 1768 #if 0 1769 static int 1770 stge_eeprom_wait(struct stge_softc *sc) 1771 { 1772 int i; 1773 1774 for (i = 0; i < STGE_TIMEOUT; i++) { 1775 delay(1000); 1776 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1777 EC_EepromBusy) == 0) 1778 return (0); 1779 } 1780 return (1); 1781 } 1782 1783 /* 1784 * stge_read_eeprom: 1785 * 1786 * Read data from the serial EEPROM. 1787 */ 1788 static void 1789 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1790 { 1791 1792 if (stge_eeprom_wait(sc)) 1793 printf("%s: EEPROM failed to come ready\n", 1794 sc->sc_dev.dv_xname); 1795 1796 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1797 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1798 if (stge_eeprom_wait(sc)) 1799 printf("%s: EEPROM read timed out\n", 1800 sc->sc_dev.dv_xname); 1801 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1802 } 1803 #endif /* 0 */ 1804 1805 /* 1806 * stge_add_rxbuf: 1807 * 1808 * Add a receive buffer to the indicated descriptor. 1809 */ 1810 static int 1811 stge_add_rxbuf(struct stge_softc *sc, int idx) 1812 { 1813 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1814 struct mbuf *m; 1815 int error; 1816 1817 MGETHDR(m, M_DONTWAIT, MT_DATA); 1818 if (m == NULL) 1819 return (ENOBUFS); 1820 1821 MCLGET(m, M_DONTWAIT); 1822 if ((m->m_flags & M_EXT) == 0) { 1823 m_freem(m); 1824 return (ENOBUFS); 1825 } 1826 1827 m->m_data = m->m_ext.ext_buf + 2; 1828 m->m_len = MCLBYTES - 2; 1829 1830 if (ds->ds_mbuf != NULL) 1831 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1832 1833 ds->ds_mbuf = m; 1834 1835 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1836 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1837 if (error) { 1838 printf("%s: can't load rx DMA map %d, error = %d\n", 1839 sc->sc_dev.dv_xname, idx, error); 1840 panic("stge_add_rxbuf"); /* XXX */ 1841 } 1842 1843 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1844 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1845 1846 STGE_INIT_RXDESC(sc, idx); 1847 1848 return (0); 1849 } 1850 1851 /* 1852 * stge_set_filter: 1853 * 1854 * Set up the receive filter. 1855 */ 1856 static void 1857 stge_set_filter(struct stge_softc *sc) 1858 { 1859 struct ethercom *ec = &sc->sc_ethercom; 1860 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1861 struct ether_multi *enm; 1862 struct ether_multistep step; 1863 uint32_t crc; 1864 uint32_t mchash[2]; 1865 1866 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1867 if (ifp->if_flags & IFF_BROADCAST) 1868 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1869 1870 #ifdef STGE_CU_BUG 1871 /* 1872 * Some cards (Sundance TI, copper) only seem to work 1873 * right now if we put them into promiscuous mode. It 1874 * probably is the Marvell PHY stuff that isn't quite 1875 * right. 1876 */ 1877 ifp->if_flags |= IFF_PROMISC; 1878 #endif 1879 1880 if (ifp->if_flags & IFF_PROMISC) { 1881 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1882 goto allmulti; 1883 } 1884 1885 /* 1886 * Set up the multicast address filter by passing all multicast 1887 * addresses through a CRC generator, and then using the low-order 1888 * 6 bits as an index into the 64 bit multicast hash table. The 1889 * high order bits select the register, while the rest of the bits 1890 * select the bit within the register. 1891 */ 1892 1893 memset(mchash, 0, sizeof(mchash)); 1894 1895 ETHER_FIRST_MULTI(step, ec, enm); 1896 if (enm == NULL) 1897 goto done; 1898 1899 while (enm != NULL) { 1900 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1901 /* 1902 * We must listen to a range of multicast addresses. 1903 * For now, just accept all multicasts, rather than 1904 * trying to set only those filter bits needed to match 1905 * the range. (At this time, the only use of address 1906 * ranges is for IP multicast routing, for which the 1907 * range is big enough to require all bits set.) 1908 */ 1909 goto allmulti; 1910 } 1911 1912 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1913 1914 /* Just want the 6 least significant bits. */ 1915 crc &= 0x3f; 1916 1917 /* Set the corresponding bit in the hash table. */ 1918 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1919 1920 ETHER_NEXT_MULTI(step, enm); 1921 } 1922 1923 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1924 1925 ifp->if_flags &= ~IFF_ALLMULTI; 1926 goto done; 1927 1928 allmulti: 1929 ifp->if_flags |= IFF_ALLMULTI; 1930 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1931 1932 done: 1933 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1934 /* 1935 * Program the multicast hash table. 1936 */ 1937 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1938 mchash[0]); 1939 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1940 mchash[1]); 1941 } 1942 1943 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1944 sc->sc_ReceiveMode); 1945 } 1946 1947 /* 1948 * stge_mii_readreg: [mii interface function] 1949 * 1950 * Read a PHY register on the MII of the TC9021. 1951 */ 1952 static int 1953 stge_mii_readreg(struct device *self, int phy, int reg) 1954 { 1955 1956 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1957 } 1958 1959 /* 1960 * stge_mii_writereg: [mii interface function] 1961 * 1962 * Write a PHY register on the MII of the TC9021. 1963 */ 1964 static void 1965 stge_mii_writereg(struct device *self, int phy, int reg, int val) 1966 { 1967 1968 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1969 } 1970 1971 /* 1972 * stge_mii_statchg: [mii interface function] 1973 * 1974 * Callback from MII layer when media changes. 1975 */ 1976 static void 1977 stge_mii_statchg(struct device *self) 1978 { 1979 struct stge_softc *sc = (struct stge_softc *) self; 1980 1981 if (sc->sc_mii.mii_media_active & IFM_FDX) 1982 sc->sc_MACCtrl |= MC_DuplexSelect; 1983 else 1984 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1985 1986 /* XXX 802.1x flow-control? */ 1987 1988 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1989 } 1990 1991 /* 1992 * sste_mii_bitbang_read: [mii bit-bang interface function] 1993 * 1994 * Read the MII serial port for the MII bit-bang module. 1995 */ 1996 static uint32_t 1997 stge_mii_bitbang_read(struct device *self) 1998 { 1999 struct stge_softc *sc = (void *) self; 2000 2001 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 2002 } 2003 2004 /* 2005 * stge_mii_bitbang_write: [mii big-bang interface function] 2006 * 2007 * Write the MII serial port for the MII bit-bang module. 2008 */ 2009 static void 2010 stge_mii_bitbang_write(struct device *self, uint32_t val) 2011 { 2012 struct stge_softc *sc = (void *) self; 2013 2014 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 2015 val | sc->sc_PhyCtrl); 2016 } 2017 2018 /* 2019 * stge_mediastatus: [ifmedia interface function] 2020 * 2021 * Get the current interface media status. 2022 */ 2023 static void 2024 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2025 { 2026 struct stge_softc *sc = ifp->if_softc; 2027 2028 mii_pollstat(&sc->sc_mii); 2029 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2030 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2031 } 2032 2033 /* 2034 * stge_mediachange: [ifmedia interface function] 2035 * 2036 * Set hardware to newly-selected media. 2037 */ 2038 static int 2039 stge_mediachange(struct ifnet *ifp) 2040 { 2041 struct stge_softc *sc = ifp->if_softc; 2042 2043 if (ifp->if_flags & IFF_UP) 2044 mii_mediachg(&sc->sc_mii); 2045 return (0); 2046 } 2047
Indexes created Tue Sep 30 17:09:57 GMT 2025