if_stge.c revision 1.41.6.1
1 /* $NetBSD: if_stge.c,v 1.41.6.1 2008/04/03 12:42:51 mjf Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the Sundance Tech. TC9021 10/100/1000 41 * Ethernet controller. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.41.6.1 2008/04/03 12:42:51 mjf Exp $"); 46 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/callout.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/socket.h> 56 #include <sys/ioctl.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 #include <sys/queue.h> 60 61 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <sys/bus.h> 73 #include <sys/intr.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 #include <dev/mii/mii_bitbang.h> 78 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pcidevs.h> 82 83 #include <dev/pci/if_stgereg.h> 84 85 /* #define STGE_CU_BUG 1 */ 86 #define STGE_VLAN_UNTAG 1 87 /* #define STGE_VLAN_CFI 1 */ 88 89 /* 90 * Transmit descriptor list size. 91 */ 92 #define STGE_NTXDESC 256 93 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 94 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 95 96 /* 97 * Receive descriptor list size. 98 */ 99 #define STGE_NRXDESC 256 100 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 101 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 102 103 /* 104 * Only interrupt every N frames. Must be a power-of-two. 105 */ 106 #define STGE_TXINTR_SPACING 16 107 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 108 109 /* 110 * Control structures are DMA'd to the TC9021 chip. We allocate them in 111 * a single clump that maps to a single DMA segment to make several things 112 * easier. 113 */ 114 struct stge_control_data { 115 /* 116 * The transmit descriptors. 117 */ 118 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 119 120 /* 121 * The receive descriptors. 122 */ 123 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 124 }; 125 126 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 127 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 128 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 129 130 /* 131 * Software state for transmit and receive jobs. 132 */ 133 struct stge_descsoft { 134 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 135 bus_dmamap_t ds_dmamap; /* our DMA map */ 136 }; 137 138 /* 139 * Software state per device. 140 */ 141 struct stge_softc { 142 struct device sc_dev; /* generic device information */ 143 bus_space_tag_t sc_st; /* bus space tag */ 144 bus_space_handle_t sc_sh; /* bus space handle */ 145 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 146 struct ethercom sc_ethercom; /* ethernet common data */ 147 void *sc_sdhook; /* shutdown hook */ 148 int sc_rev; /* silicon revision */ 149 150 void *sc_ih; /* interrupt cookie */ 151 152 struct mii_data sc_mii; /* MII/media information */ 153 154 callout_t sc_tick_ch; /* tick callout */ 155 156 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 157 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 158 159 /* 160 * Software state for transmit and receive descriptors. 161 */ 162 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 163 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 164 165 /* 166 * Control data structures. 167 */ 168 struct stge_control_data *sc_control_data; 169 #define sc_txdescs sc_control_data->scd_txdescs 170 #define sc_rxdescs sc_control_data->scd_rxdescs 171 172 #ifdef STGE_EVENT_COUNTERS 173 /* 174 * Event counters. 175 */ 176 struct evcnt sc_ev_txstall; /* Tx stalled */ 177 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 178 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 179 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 180 181 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 182 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 183 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 184 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 185 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 186 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 187 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 188 189 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 190 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 191 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 192 193 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 194 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 195 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 196 #endif /* STGE_EVENT_COUNTERS */ 197 198 int sc_txpending; /* number of Tx requests pending */ 199 int sc_txdirty; /* first dirty Tx descriptor */ 200 int sc_txlast; /* last used Tx descriptor */ 201 202 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 203 int sc_rxdiscard; 204 int sc_rxlen; 205 struct mbuf *sc_rxhead; 206 struct mbuf *sc_rxtail; 207 struct mbuf **sc_rxtailp; 208 209 int sc_txthresh; /* Tx threshold */ 210 uint32_t sc_usefiber:1; /* if we're fiber */ 211 uint32_t sc_stge1023:1; /* are we a 1023 */ 212 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 213 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 214 uint16_t sc_IntEnable; /* prototype IntEnable register */ 215 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 216 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 217 }; 218 219 #define STGE_RXCHAIN_RESET(sc) \ 220 do { \ 221 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 222 *(sc)->sc_rxtailp = NULL; \ 223 (sc)->sc_rxlen = 0; \ 224 } while (/*CONSTCOND*/0) 225 226 #define STGE_RXCHAIN_LINK(sc, m) \ 227 do { \ 228 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 229 (sc)->sc_rxtailp = &(m)->m_next; \ 230 } while (/*CONSTCOND*/0) 231 232 #ifdef STGE_EVENT_COUNTERS 233 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 234 #else 235 #define STGE_EVCNT_INCR(ev) /* nothing */ 236 #endif 237 238 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 239 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 240 241 #define STGE_CDTXSYNC(sc, x, ops) \ 242 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 243 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 244 245 #define STGE_CDRXSYNC(sc, x, ops) \ 246 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 247 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 248 249 #define STGE_INIT_RXDESC(sc, x) \ 250 do { \ 251 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 252 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 253 \ 254 /* \ 255 * Note: We scoot the packet forward 2 bytes in the buffer \ 256 * so that the payload after the Ethernet header is aligned \ 257 * to a 4-byte boundary. \ 258 */ \ 259 __rfd->rfd_frag.frag_word0 = \ 260 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 261 FRAG_LEN(MCLBYTES - 2)); \ 262 __rfd->rfd_next = \ 263 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 264 __rfd->rfd_status = 0; \ 265 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 266 } while (/*CONSTCOND*/0) 267 268 #define STGE_TIMEOUT 1000 269 270 static void stge_start(struct ifnet *); 271 static void stge_watchdog(struct ifnet *); 272 static int stge_ioctl(struct ifnet *, u_long, void *); 273 static int stge_init(struct ifnet *); 274 static void stge_stop(struct ifnet *, int); 275 276 static void stge_shutdown(void *); 277 278 static void stge_reset(struct stge_softc *); 279 static void stge_rxdrain(struct stge_softc *); 280 static int stge_add_rxbuf(struct stge_softc *, int); 281 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 282 static void stge_tick(void *); 283 284 static void stge_stats_update(struct stge_softc *); 285 286 static void stge_set_filter(struct stge_softc *); 287 288 static int stge_intr(void *); 289 static void stge_txintr(struct stge_softc *); 290 static void stge_rxintr(struct stge_softc *); 291 292 static int stge_mii_readreg(device_t, int, int); 293 static void stge_mii_writereg(device_t, int, int, int); 294 static void stge_mii_statchg(device_t); 295 296 static int stge_match(device_t, struct cfdata *, void *); 297 static void stge_attach(device_t, device_t, void *); 298 299 int stge_copy_small = 0; 300 301 CFATTACH_DECL(stge, sizeof(struct stge_softc), 302 stge_match, stge_attach, NULL, NULL); 303 304 static uint32_t stge_mii_bitbang_read(device_t); 305 static void stge_mii_bitbang_write(device_t, uint32_t); 306 307 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 308 stge_mii_bitbang_read, 309 stge_mii_bitbang_write, 310 { 311 PC_MgmtData, /* MII_BIT_MDO */ 312 PC_MgmtData, /* MII_BIT_MDI */ 313 PC_MgmtClk, /* MII_BIT_MDC */ 314 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 315 0, /* MII_BIT_DIR_PHY_HOST */ 316 } 317 }; 318 319 /* 320 * Devices supported by this driver. 321 */ 322 static const struct stge_product { 323 pci_vendor_id_t stge_vendor; 324 pci_product_id_t stge_product; 325 const char *stge_name; 326 } stge_products[] = { 327 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023, 328 "Sundance ST-1023 Gigabit Ethernet" }, 329 330 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 331 "Sundance ST-2021 Gigabit Ethernet" }, 332 333 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 334 "Tamarack TC9021 Gigabit Ethernet" }, 335 336 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 337 "Tamarack TC9021 Gigabit Ethernet" }, 338 339 /* 340 * The Sundance sample boards use the Sundance vendor ID, 341 * but the Tamarack product ID. 342 */ 343 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 344 "Sundance TC9021 Gigabit Ethernet" }, 345 346 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 347 "Sundance TC9021 Gigabit Ethernet" }, 348 349 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 350 "D-Link DL-4000 Gigabit Ethernet" }, 351 352 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 353 "Antares Gigabit Ethernet" }, 354 355 { 0, 0, 356 NULL }, 357 }; 358 359 static const struct stge_product * 360 stge_lookup(const struct pci_attach_args *pa) 361 { 362 const struct stge_product *sp; 363 364 for (sp = stge_products; sp->stge_name != NULL; sp++) { 365 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 366 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 367 return (sp); 368 } 369 return (NULL); 370 } 371 372 static int 373 stge_match(device_t parent, struct cfdata *cf, void *aux) 374 { 375 struct pci_attach_args *pa = aux; 376 377 if (stge_lookup(pa) != NULL) 378 return (1); 379 380 return (0); 381 } 382 383 static void 384 stge_attach(device_t parent, device_t self, void *aux) 385 { 386 struct stge_softc *sc = device_private(self); 387 struct pci_attach_args *pa = aux; 388 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 389 pci_chipset_tag_t pc = pa->pa_pc; 390 pci_intr_handle_t ih; 391 const char *intrstr = NULL; 392 bus_space_tag_t iot, memt; 393 bus_space_handle_t ioh, memh; 394 bus_dma_segment_t seg; 395 int ioh_valid, memh_valid; 396 int i, rseg, error; 397 const struct stge_product *sp; 398 uint8_t enaddr[ETHER_ADDR_LEN]; 399 400 callout_init(&sc->sc_tick_ch, 0); 401 402 sp = stge_lookup(pa); 403 if (sp == NULL) { 404 printf("\n"); 405 panic("ste_attach: impossible"); 406 } 407 408 sc->sc_rev = PCI_REVISION(pa->pa_class); 409 410 printf(": %s, rev. %d\n", sp->stge_name, sc->sc_rev); 411 412 /* 413 * Map the device. 414 */ 415 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 416 PCI_MAPREG_TYPE_IO, 0, 417 &iot, &ioh, NULL, NULL) == 0); 418 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 419 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 420 &memt, &memh, NULL, NULL) == 0); 421 422 if (memh_valid) { 423 sc->sc_st = memt; 424 sc->sc_sh = memh; 425 } else if (ioh_valid) { 426 sc->sc_st = iot; 427 sc->sc_sh = ioh; 428 } else { 429 printf("%s: unable to map device registers\n", 430 sc->sc_dev.dv_xname); 431 return; 432 } 433 434 sc->sc_dmat = pa->pa_dmat; 435 436 /* Enable bus mastering. */ 437 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 438 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 439 PCI_COMMAND_MASTER_ENABLE); 440 441 /* power up chip */ 442 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 443 error != EOPNOTSUPP) { 444 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 445 error); 446 return; 447 } 448 /* 449 * Map and establish our interrupt. 450 */ 451 if (pci_intr_map(pa, &ih)) { 452 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 453 return; 454 } 455 intrstr = pci_intr_string(pc, ih); 456 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc); 457 if (sc->sc_ih == NULL) { 458 printf("%s: unable to establish interrupt", 459 sc->sc_dev.dv_xname); 460 if (intrstr != NULL) 461 printf(" at %s", intrstr); 462 printf("\n"); 463 return; 464 } 465 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 466 467 /* 468 * Allocate the control data structures, and create and load the 469 * DMA map for it. 470 */ 471 if ((error = bus_dmamem_alloc(sc->sc_dmat, 472 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 473 0)) != 0) { 474 printf("%s: unable to allocate control data, error = %d\n", 475 sc->sc_dev.dv_xname, error); 476 goto fail_0; 477 } 478 479 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 480 sizeof(struct stge_control_data), (void **)&sc->sc_control_data, 481 BUS_DMA_COHERENT)) != 0) { 482 printf("%s: unable to map control data, error = %d\n", 483 sc->sc_dev.dv_xname, error); 484 goto fail_1; 485 } 486 487 if ((error = bus_dmamap_create(sc->sc_dmat, 488 sizeof(struct stge_control_data), 1, 489 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 490 printf("%s: unable to create control data DMA map, " 491 "error = %d\n", sc->sc_dev.dv_xname, error); 492 goto fail_2; 493 } 494 495 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 496 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 497 0)) != 0) { 498 printf("%s: unable to load control data DMA map, error = %d\n", 499 sc->sc_dev.dv_xname, error); 500 goto fail_3; 501 } 502 503 /* 504 * Create the transmit buffer DMA maps. Note that rev B.3 505 * and earlier seem to have a bug regarding multi-fragment 506 * packets. We need to limit the number of Tx segments on 507 * such chips to 1. 508 */ 509 for (i = 0; i < STGE_NTXDESC; i++) { 510 if ((error = bus_dmamap_create(sc->sc_dmat, 511 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 512 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 513 printf("%s: unable to create tx DMA map %d, " 514 "error = %d\n", sc->sc_dev.dv_xname, i, error); 515 goto fail_4; 516 } 517 } 518 519 /* 520 * Create the receive buffer DMA maps. 521 */ 522 for (i = 0; i < STGE_NRXDESC; i++) { 523 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 524 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 525 printf("%s: unable to create rx DMA map %d, " 526 "error = %d\n", sc->sc_dev.dv_xname, i, error); 527 goto fail_5; 528 } 529 sc->sc_rxsoft[i].ds_mbuf = NULL; 530 } 531 532 /* 533 * Determine if we're copper or fiber. It affects how we 534 * reset the card. 535 */ 536 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 537 AC_PhyMedia) 538 sc->sc_usefiber = 1; 539 else 540 sc->sc_usefiber = 0; 541 542 /* 543 * Reset the chip to a known state. 544 */ 545 stge_reset(sc); 546 547 /* 548 * Reading the station address from the EEPROM doesn't seem 549 * to work, at least on my sample boards. Instead, since 550 * the reset sequence does AutoInit, read it from the station 551 * address registers. For Sundance 1023 you can only read it 552 * from EEPROM. 553 */ 554 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) { 555 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 556 STGE_StationAddress0) & 0xff; 557 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 558 STGE_StationAddress0) >> 8; 559 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 560 STGE_StationAddress1) & 0xff; 561 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 562 STGE_StationAddress1) >> 8; 563 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 564 STGE_StationAddress2) & 0xff; 565 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 566 STGE_StationAddress2) >> 8; 567 sc->sc_stge1023 = 0; 568 } else { 569 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 570 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 571 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 572 &myaddr[i]); 573 myaddr[i] = le16toh(myaddr[i]); 574 } 575 (void)memcpy(enaddr, myaddr, sizeof(enaddr)); 576 sc->sc_stge1023 = 1; 577 } 578 579 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 580 ether_sprintf(enaddr)); 581 582 /* 583 * Read some important bits from the PhyCtrl register. 584 */ 585 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 586 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 587 588 /* 589 * Initialize our media structures and probe the MII. 590 */ 591 sc->sc_mii.mii_ifp = ifp; 592 sc->sc_mii.mii_readreg = stge_mii_readreg; 593 sc->sc_mii.mii_writereg = stge_mii_writereg; 594 sc->sc_mii.mii_statchg = stge_mii_statchg; 595 sc->sc_ethercom.ec_mii = &sc->sc_mii; 596 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 597 ether_mediastatus); 598 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 599 MII_OFFSET_ANY, MIIF_DOPAUSE); 600 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 601 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 602 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 603 } else 604 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 605 606 ifp = &sc->sc_ethercom.ec_if; 607 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 608 ifp->if_softc = sc; 609 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 610 ifp->if_ioctl = stge_ioctl; 611 ifp->if_start = stge_start; 612 ifp->if_watchdog = stge_watchdog; 613 ifp->if_init = stge_init; 614 ifp->if_stop = stge_stop; 615 IFQ_SET_READY(&ifp->if_snd); 616 617 /* 618 * The manual recommends disabling early transmit, so we 619 * do. It's disabled anyway, if using IP checksumming, 620 * since the entire packet must be in the FIFO in order 621 * for the chip to perform the checksum. 622 */ 623 sc->sc_txthresh = 0x0fff; 624 625 /* 626 * Disable MWI if the PCI layer tells us to. 627 */ 628 sc->sc_DMACtrl = 0; 629 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 630 sc->sc_DMACtrl |= DMAC_MWIDisable; 631 632 /* 633 * We can support 802.1Q VLAN-sized frames and jumbo 634 * Ethernet frames. 635 * 636 * XXX Figure out how to do hw-assisted VLAN tagging in 637 * XXX a reasonable way on this chip. 638 */ 639 sc->sc_ethercom.ec_capabilities |= 640 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 641 ETHERCAP_VLAN_HWTAGGING; 642 643 /* 644 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 645 */ 646 sc->sc_ethercom.ec_if.if_capabilities |= 647 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 648 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 649 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 650 651 /* 652 * Attach the interface. 653 */ 654 if_attach(ifp); 655 ether_ifattach(ifp, enaddr); 656 657 #ifdef STGE_EVENT_COUNTERS 658 /* 659 * Attach event counters. 660 */ 661 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 662 NULL, sc->sc_dev.dv_xname, "txstall"); 663 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 664 NULL, sc->sc_dev.dv_xname, "txdmaintr"); 665 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 666 NULL, sc->sc_dev.dv_xname, "txindintr"); 667 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 668 NULL, sc->sc_dev.dv_xname, "rxintr"); 669 670 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 671 NULL, sc->sc_dev.dv_xname, "txseg1"); 672 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 673 NULL, sc->sc_dev.dv_xname, "txseg2"); 674 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 675 NULL, sc->sc_dev.dv_xname, "txseg3"); 676 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 677 NULL, sc->sc_dev.dv_xname, "txseg4"); 678 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 679 NULL, sc->sc_dev.dv_xname, "txseg5"); 680 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 681 NULL, sc->sc_dev.dv_xname, "txsegmore"); 682 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 683 NULL, sc->sc_dev.dv_xname, "txcopy"); 684 685 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 686 NULL, sc->sc_dev.dv_xname, "rxipsum"); 687 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 688 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 689 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 690 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 691 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 692 NULL, sc->sc_dev.dv_xname, "txipsum"); 693 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 694 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 695 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 696 NULL, sc->sc_dev.dv_xname, "txudpsum"); 697 #endif /* STGE_EVENT_COUNTERS */ 698 699 /* 700 * Make sure the interface is shutdown during reboot. 701 */ 702 sc->sc_sdhook = shutdownhook_establish(stge_shutdown, sc); 703 if (sc->sc_sdhook == NULL) 704 printf("%s: WARNING: unable to establish shutdown hook\n", 705 sc->sc_dev.dv_xname); 706 return; 707 708 /* 709 * Free any resources we've allocated during the failed attach 710 * attempt. Do this in reverse order and fall through. 711 */ 712 fail_5: 713 for (i = 0; i < STGE_NRXDESC; i++) { 714 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 715 bus_dmamap_destroy(sc->sc_dmat, 716 sc->sc_rxsoft[i].ds_dmamap); 717 } 718 fail_4: 719 for (i = 0; i < STGE_NTXDESC; i++) { 720 if (sc->sc_txsoft[i].ds_dmamap != NULL) 721 bus_dmamap_destroy(sc->sc_dmat, 722 sc->sc_txsoft[i].ds_dmamap); 723 } 724 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 725 fail_3: 726 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 727 fail_2: 728 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 729 sizeof(struct stge_control_data)); 730 fail_1: 731 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 732 fail_0: 733 return; 734 } 735 736 /* 737 * stge_shutdown: 738 * 739 * Make sure the interface is stopped at reboot time. 740 */ 741 static void 742 stge_shutdown(void *arg) 743 { 744 struct stge_softc *sc = arg; 745 746 stge_stop(&sc->sc_ethercom.ec_if, 1); 747 } 748 749 static void 750 stge_dma_wait(struct stge_softc *sc) 751 { 752 int i; 753 754 for (i = 0; i < STGE_TIMEOUT; i++) { 755 delay(2); 756 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 757 DMAC_TxDMAInProg) == 0) 758 break; 759 } 760 761 if (i == STGE_TIMEOUT) 762 printf("%s: DMA wait timed out\n", sc->sc_dev.dv_xname); 763 } 764 765 /* 766 * stge_start: [ifnet interface function] 767 * 768 * Start packet transmission on the interface. 769 */ 770 static void 771 stge_start(struct ifnet *ifp) 772 { 773 struct stge_softc *sc = ifp->if_softc; 774 struct mbuf *m0; 775 struct stge_descsoft *ds; 776 struct stge_tfd *tfd; 777 bus_dmamap_t dmamap; 778 int error, firsttx, nexttx, opending, seg, totlen; 779 uint64_t csum_flags; 780 781 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 782 return; 783 784 /* 785 * Remember the previous number of pending transmissions 786 * and the first descriptor we will use. 787 */ 788 opending = sc->sc_txpending; 789 firsttx = STGE_NEXTTX(sc->sc_txlast); 790 791 /* 792 * Loop through the send queue, setting up transmit descriptors 793 * until we drain the queue, or use up all available transmit 794 * descriptors. 795 */ 796 for (;;) { 797 struct m_tag *mtag; 798 uint64_t tfc; 799 800 /* 801 * Grab a packet off the queue. 802 */ 803 IFQ_POLL(&ifp->if_snd, m0); 804 if (m0 == NULL) 805 break; 806 807 /* 808 * Leave one unused descriptor at the end of the 809 * list to prevent wrapping completely around. 810 */ 811 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 812 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 813 break; 814 } 815 816 /* 817 * See if we have any VLAN stuff. 818 */ 819 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 820 821 /* 822 * Get the last and next available transmit descriptor. 823 */ 824 nexttx = STGE_NEXTTX(sc->sc_txlast); 825 tfd = &sc->sc_txdescs[nexttx]; 826 ds = &sc->sc_txsoft[nexttx]; 827 828 dmamap = ds->ds_dmamap; 829 830 /* 831 * Load the DMA map. If this fails, the packet either 832 * didn't fit in the alloted number of segments, or we 833 * were short on resources. For the too-many-segments 834 * case, we simply report an error and drop the packet, 835 * since we can't sanely copy a jumbo packet to a single 836 * buffer. 837 */ 838 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 839 BUS_DMA_NOWAIT); 840 if (error) { 841 if (error == EFBIG) { 842 printf("%s: Tx packet consumes too many " 843 "DMA segments, dropping...\n", 844 sc->sc_dev.dv_xname); 845 IFQ_DEQUEUE(&ifp->if_snd, m0); 846 m_freem(m0); 847 continue; 848 } 849 /* 850 * Short on resources, just stop for now. 851 */ 852 break; 853 } 854 855 IFQ_DEQUEUE(&ifp->if_snd, m0); 856 857 /* 858 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 859 */ 860 861 /* Sync the DMA map. */ 862 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 863 BUS_DMASYNC_PREWRITE); 864 865 /* Initialize the fragment list. */ 866 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 867 tfd->tfd_frags[seg].frag_word0 = 868 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 869 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 870 totlen += dmamap->dm_segs[seg].ds_len; 871 } 872 873 #ifdef STGE_EVENT_COUNTERS 874 switch (dmamap->dm_nsegs) { 875 case 1: 876 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 877 break; 878 case 2: 879 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 880 break; 881 case 3: 882 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 883 break; 884 case 4: 885 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 886 break; 887 case 5: 888 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 889 break; 890 default: 891 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 892 break; 893 } 894 #endif /* STGE_EVENT_COUNTERS */ 895 896 /* 897 * Initialize checksumming flags in the descriptor. 898 * Byte-swap constants so the compiler can optimize. 899 */ 900 csum_flags = 0; 901 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 902 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 903 csum_flags |= TFD_IPChecksumEnable; 904 } 905 906 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 907 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 908 csum_flags |= TFD_TCPChecksumEnable; 909 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 910 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 911 csum_flags |= TFD_UDPChecksumEnable; 912 } 913 914 /* 915 * Initialize the descriptor and give it to the chip. 916 * Check to see if we have a VLAN tag to insert. 917 */ 918 919 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 920 TFD_FragCount(seg) | csum_flags | 921 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 922 TFD_TxDMAIndicate : 0); 923 if (mtag) { 924 #if 0 925 struct ether_header *eh = 926 mtod(m0, struct ether_header *); 927 u_int16_t etype = ntohs(eh->ether_type); 928 printf("%s: xmit (tag %d) etype %x\n", 929 ifp->if_xname, *mtod(n, int *), etype); 930 #endif 931 tfc |= TFD_VLANTagInsert | 932 #ifdef STGE_VLAN_CFI 933 TFD_CFI | 934 #endif 935 TFD_VID(VLAN_TAG_VALUE(mtag)); 936 } 937 tfd->tfd_control = htole64(tfc); 938 939 /* Sync the descriptor. */ 940 STGE_CDTXSYNC(sc, nexttx, 941 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 942 943 /* 944 * Kick the transmit DMA logic. 945 */ 946 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 947 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 948 949 /* 950 * Store a pointer to the packet so we can free it later. 951 */ 952 ds->ds_mbuf = m0; 953 954 /* Advance the tx pointer. */ 955 sc->sc_txpending++; 956 sc->sc_txlast = nexttx; 957 958 #if NBPFILTER > 0 959 /* 960 * Pass the packet to any BPF listeners. 961 */ 962 if (ifp->if_bpf) 963 bpf_mtap(ifp->if_bpf, m0); 964 #endif /* NBPFILTER > 0 */ 965 } 966 967 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 968 /* No more slots left; notify upper layer. */ 969 ifp->if_flags |= IFF_OACTIVE; 970 } 971 972 if (sc->sc_txpending != opending) { 973 /* 974 * We enqueued packets. If the transmitter was idle, 975 * reset the txdirty pointer. 976 */ 977 if (opending == 0) 978 sc->sc_txdirty = firsttx; 979 980 /* Set a watchdog timer in case the chip flakes out. */ 981 ifp->if_timer = 5; 982 } 983 } 984 985 /* 986 * stge_watchdog: [ifnet interface function] 987 * 988 * Watchdog timer handler. 989 */ 990 static void 991 stge_watchdog(struct ifnet *ifp) 992 { 993 struct stge_softc *sc = ifp->if_softc; 994 995 /* 996 * Sweep up first, since we don't interrupt every frame. 997 */ 998 stge_txintr(sc); 999 if (sc->sc_txpending != 0) { 1000 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1001 ifp->if_oerrors++; 1002 1003 (void) stge_init(ifp); 1004 1005 /* Try to get more packets going. */ 1006 stge_start(ifp); 1007 } 1008 } 1009 1010 /* 1011 * stge_ioctl: [ifnet interface function] 1012 * 1013 * Handle control requests from the operator. 1014 */ 1015 static int 1016 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1017 { 1018 struct stge_softc *sc = ifp->if_softc; 1019 int s, error; 1020 1021 s = splnet(); 1022 1023 error = ether_ioctl(ifp, cmd, data); 1024 if (error == ENETRESET) { 1025 error = 0; 1026 1027 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1028 ; 1029 else if (ifp->if_flags & IFF_RUNNING) { 1030 /* 1031 * Multicast list has changed; set the hardware filter 1032 * accordingly. 1033 */ 1034 stge_set_filter(sc); 1035 } 1036 } 1037 1038 /* Try to get more packets going. */ 1039 stge_start(ifp); 1040 1041 splx(s); 1042 return (error); 1043 } 1044 1045 /* 1046 * stge_intr: 1047 * 1048 * Interrupt service routine. 1049 */ 1050 static int 1051 stge_intr(void *arg) 1052 { 1053 struct stge_softc *sc = arg; 1054 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1055 uint32_t txstat; 1056 int wantinit; 1057 uint16_t isr; 1058 1059 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1060 IS_InterruptStatus) == 0) 1061 return (0); 1062 1063 for (wantinit = 0; wantinit == 0;) { 1064 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1065 if ((isr & sc->sc_IntEnable) == 0) 1066 break; 1067 1068 /* Host interface errors. */ 1069 if (isr & IS_HostError) { 1070 printf("%s: Host interface error\n", 1071 sc->sc_dev.dv_xname); 1072 wantinit = 1; 1073 continue; 1074 } 1075 1076 /* Receive interrupts. */ 1077 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) { 1078 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1079 stge_rxintr(sc); 1080 if (isr & IS_RFDListEnd) { 1081 printf("%s: receive ring overflow\n", 1082 sc->sc_dev.dv_xname); 1083 /* 1084 * XXX Should try to recover from this 1085 * XXX more gracefully. 1086 */ 1087 wantinit = 1; 1088 } 1089 } 1090 1091 /* Transmit interrupts. */ 1092 if (isr & (IS_TxDMAComplete|IS_TxComplete)) { 1093 #ifdef STGE_EVENT_COUNTERS 1094 if (isr & IS_TxDMAComplete) 1095 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1096 #endif 1097 stge_txintr(sc); 1098 } 1099 1100 /* Statistics overflow. */ 1101 if (isr & IS_UpdateStats) 1102 stge_stats_update(sc); 1103 1104 /* Transmission errors. */ 1105 if (isr & IS_TxComplete) { 1106 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1107 for (;;) { 1108 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1109 STGE_TxStatus); 1110 if ((txstat & TS_TxComplete) == 0) 1111 break; 1112 if (txstat & TS_TxUnderrun) { 1113 sc->sc_txthresh++; 1114 if (sc->sc_txthresh > 0x0fff) 1115 sc->sc_txthresh = 0x0fff; 1116 printf("%s: transmit underrun, new " 1117 "threshold: %d bytes\n", 1118 sc->sc_dev.dv_xname, 1119 sc->sc_txthresh << 5); 1120 } 1121 if (txstat & TS_MaxCollisions) 1122 printf("%s: excessive collisions\n", 1123 sc->sc_dev.dv_xname); 1124 } 1125 wantinit = 1; 1126 } 1127 1128 } 1129 1130 if (wantinit) 1131 stge_init(ifp); 1132 1133 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1134 sc->sc_IntEnable); 1135 1136 /* Try to get more packets going. */ 1137 stge_start(ifp); 1138 1139 return (1); 1140 } 1141 1142 /* 1143 * stge_txintr: 1144 * 1145 * Helper; handle transmit interrupts. 1146 */ 1147 static void 1148 stge_txintr(struct stge_softc *sc) 1149 { 1150 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1151 struct stge_descsoft *ds; 1152 uint64_t control; 1153 int i; 1154 1155 ifp->if_flags &= ~IFF_OACTIVE; 1156 1157 /* 1158 * Go through our Tx list and free mbufs for those 1159 * frames which have been transmitted. 1160 */ 1161 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1162 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1163 ds = &sc->sc_txsoft[i]; 1164 1165 STGE_CDTXSYNC(sc, i, 1166 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1167 1168 control = le64toh(sc->sc_txdescs[i].tfd_control); 1169 if ((control & TFD_TFDDone) == 0) 1170 break; 1171 1172 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1173 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1174 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1175 m_freem(ds->ds_mbuf); 1176 ds->ds_mbuf = NULL; 1177 } 1178 1179 /* Update the dirty transmit buffer pointer. */ 1180 sc->sc_txdirty = i; 1181 1182 /* 1183 * If there are no more pending transmissions, cancel the watchdog 1184 * timer. 1185 */ 1186 if (sc->sc_txpending == 0) 1187 ifp->if_timer = 0; 1188 } 1189 1190 /* 1191 * stge_rxintr: 1192 * 1193 * Helper; handle receive interrupts. 1194 */ 1195 static void 1196 stge_rxintr(struct stge_softc *sc) 1197 { 1198 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1199 struct stge_descsoft *ds; 1200 struct mbuf *m, *tailm; 1201 uint64_t status; 1202 int i, len; 1203 1204 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1205 ds = &sc->sc_rxsoft[i]; 1206 1207 STGE_CDRXSYNC(sc, i, 1208 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1209 1210 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1211 1212 if ((status & RFD_RFDDone) == 0) 1213 break; 1214 1215 if (__predict_false(sc->sc_rxdiscard)) { 1216 STGE_INIT_RXDESC(sc, i); 1217 if (status & RFD_FrameEnd) { 1218 /* Reset our state. */ 1219 sc->sc_rxdiscard = 0; 1220 } 1221 continue; 1222 } 1223 1224 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1225 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1226 1227 m = ds->ds_mbuf; 1228 1229 /* 1230 * Add a new receive buffer to the ring. 1231 */ 1232 if (stge_add_rxbuf(sc, i) != 0) { 1233 /* 1234 * Failed, throw away what we've done so 1235 * far, and discard the rest of the packet. 1236 */ 1237 ifp->if_ierrors++; 1238 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1239 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1240 STGE_INIT_RXDESC(sc, i); 1241 if ((status & RFD_FrameEnd) == 0) 1242 sc->sc_rxdiscard = 1; 1243 if (sc->sc_rxhead != NULL) 1244 m_freem(sc->sc_rxhead); 1245 STGE_RXCHAIN_RESET(sc); 1246 continue; 1247 } 1248 1249 #ifdef DIAGNOSTIC 1250 if (status & RFD_FrameStart) { 1251 KASSERT(sc->sc_rxhead == NULL); 1252 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1253 } 1254 #endif 1255 1256 STGE_RXCHAIN_LINK(sc, m); 1257 1258 /* 1259 * If this is not the end of the packet, keep 1260 * looking. 1261 */ 1262 if ((status & RFD_FrameEnd) == 0) { 1263 sc->sc_rxlen += m->m_len; 1264 continue; 1265 } 1266 1267 /* 1268 * Okay, we have the entire packet now... 1269 */ 1270 *sc->sc_rxtailp = NULL; 1271 m = sc->sc_rxhead; 1272 tailm = sc->sc_rxtail; 1273 1274 STGE_RXCHAIN_RESET(sc); 1275 1276 /* 1277 * If the packet had an error, drop it. Note we 1278 * count the error later in the periodic stats update. 1279 */ 1280 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1281 RFD_RxAlignmentError | RFD_RxFCSError | 1282 RFD_RxLengthError)) { 1283 m_freem(m); 1284 continue; 1285 } 1286 1287 /* 1288 * No errors. 1289 * 1290 * Note we have configured the chip to not include 1291 * the CRC at the end of the packet. 1292 */ 1293 len = RFD_RxDMAFrameLen(status); 1294 tailm->m_len = len - sc->sc_rxlen; 1295 1296 /* 1297 * If the packet is small enough to fit in a 1298 * single header mbuf, allocate one and copy 1299 * the data into it. This greatly reduces 1300 * memory consumption when we receive lots 1301 * of small packets. 1302 */ 1303 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1304 struct mbuf *nm; 1305 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1306 if (nm == NULL) { 1307 ifp->if_ierrors++; 1308 m_freem(m); 1309 continue; 1310 } 1311 nm->m_data += 2; 1312 nm->m_pkthdr.len = nm->m_len = len; 1313 m_copydata(m, 0, len, mtod(nm, void *)); 1314 m_freem(m); 1315 m = nm; 1316 } 1317 1318 /* 1319 * Set the incoming checksum information for the packet. 1320 */ 1321 if (status & RFD_IPDetected) { 1322 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1323 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1324 if (status & RFD_IPError) 1325 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1326 if (status & RFD_TCPDetected) { 1327 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1328 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1329 if (status & RFD_TCPError) 1330 m->m_pkthdr.csum_flags |= 1331 M_CSUM_TCP_UDP_BAD; 1332 } else if (status & RFD_UDPDetected) { 1333 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1334 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1335 if (status & RFD_UDPError) 1336 m->m_pkthdr.csum_flags |= 1337 M_CSUM_TCP_UDP_BAD; 1338 } 1339 } 1340 1341 m->m_pkthdr.rcvif = ifp; 1342 m->m_pkthdr.len = len; 1343 1344 #if NBPFILTER > 0 1345 /* 1346 * Pass this up to any BPF listeners, but only 1347 * pass if up the stack if it's for us. 1348 */ 1349 if (ifp->if_bpf) 1350 bpf_mtap(ifp->if_bpf, m); 1351 #endif /* NBPFILTER > 0 */ 1352 #ifdef STGE_VLAN_UNTAG 1353 /* 1354 * Check for VLAN tagged packets 1355 */ 1356 if (status & RFD_VLANDetected) 1357 VLAN_INPUT_TAG(ifp, m, RFD_TCI(status), continue); 1358 1359 #endif 1360 #if 0 1361 if (status & RFD_VLANDetected) { 1362 struct ether_header *eh; 1363 u_int16_t etype; 1364 1365 eh = mtod(m, struct ether_header *); 1366 etype = ntohs(eh->ether_type); 1367 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1368 ifp->if_xname, (u_int16_t) RFD_TCI(status), 1369 etype); 1370 } 1371 #endif 1372 /* Pass it on. */ 1373 (*ifp->if_input)(ifp, m); 1374 } 1375 1376 /* Update the receive pointer. */ 1377 sc->sc_rxptr = i; 1378 } 1379 1380 /* 1381 * stge_tick: 1382 * 1383 * One second timer, used to tick the MII. 1384 */ 1385 static void 1386 stge_tick(void *arg) 1387 { 1388 struct stge_softc *sc = arg; 1389 int s; 1390 1391 s = splnet(); 1392 mii_tick(&sc->sc_mii); 1393 stge_stats_update(sc); 1394 splx(s); 1395 1396 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1397 } 1398 1399 /* 1400 * stge_stats_update: 1401 * 1402 * Read the TC9021 statistics counters. 1403 */ 1404 static void 1405 stge_stats_update(struct stge_softc *sc) 1406 { 1407 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1408 bus_space_tag_t st = sc->sc_st; 1409 bus_space_handle_t sh = sc->sc_sh; 1410 1411 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1412 1413 ifp->if_ipackets += 1414 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1415 1416 ifp->if_ierrors += 1417 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1418 1419 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1420 1421 ifp->if_opackets += 1422 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1423 1424 ifp->if_collisions += 1425 bus_space_read_4(st, sh, STGE_LateCollisions) + 1426 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1427 bus_space_read_4(st, sh, STGE_SingleColFrames); 1428 1429 ifp->if_oerrors += 1430 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1431 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1432 } 1433 1434 /* 1435 * stge_reset: 1436 * 1437 * Perform a soft reset on the TC9021. 1438 */ 1439 static void 1440 stge_reset(struct stge_softc *sc) 1441 { 1442 uint32_t ac; 1443 int i; 1444 1445 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1446 1447 /* 1448 * Only assert RstOut if we're fiber. We need GMII clocks 1449 * to be present in order for the reset to complete on fiber 1450 * cards. 1451 */ 1452 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1453 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1454 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1455 (sc->sc_usefiber ? AC_RstOut : 0)); 1456 1457 delay(50000); 1458 1459 for (i = 0; i < STGE_TIMEOUT; i++) { 1460 delay(5000); 1461 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1462 AC_ResetBusy) == 0) 1463 break; 1464 } 1465 1466 if (i == STGE_TIMEOUT) 1467 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1468 1469 delay(1000); 1470 } 1471 1472 /* 1473 * stge_init: [ ifnet interface function ] 1474 * 1475 * Initialize the interface. Must be called at splnet(). 1476 */ 1477 static int 1478 stge_init(struct ifnet *ifp) 1479 { 1480 struct stge_softc *sc = ifp->if_softc; 1481 bus_space_tag_t st = sc->sc_st; 1482 bus_space_handle_t sh = sc->sc_sh; 1483 struct stge_descsoft *ds; 1484 int i, error = 0; 1485 1486 /* 1487 * Cancel any pending I/O. 1488 */ 1489 stge_stop(ifp, 0); 1490 1491 /* 1492 * Reset the chip to a known state. 1493 */ 1494 stge_reset(sc); 1495 1496 /* 1497 * Initialize the transmit descriptor ring. 1498 */ 1499 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1500 for (i = 0; i < STGE_NTXDESC; i++) { 1501 sc->sc_txdescs[i].tfd_next = htole64( 1502 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1503 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1504 } 1505 sc->sc_txpending = 0; 1506 sc->sc_txdirty = 0; 1507 sc->sc_txlast = STGE_NTXDESC - 1; 1508 1509 /* 1510 * Initialize the receive descriptor and receive job 1511 * descriptor rings. 1512 */ 1513 for (i = 0; i < STGE_NRXDESC; i++) { 1514 ds = &sc->sc_rxsoft[i]; 1515 if (ds->ds_mbuf == NULL) { 1516 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1517 printf("%s: unable to allocate or map rx " 1518 "buffer %d, error = %d\n", 1519 sc->sc_dev.dv_xname, i, error); 1520 /* 1521 * XXX Should attempt to run with fewer receive 1522 * XXX buffers instead of just failing. 1523 */ 1524 stge_rxdrain(sc); 1525 goto out; 1526 } 1527 } else 1528 STGE_INIT_RXDESC(sc, i); 1529 } 1530 sc->sc_rxptr = 0; 1531 sc->sc_rxdiscard = 0; 1532 STGE_RXCHAIN_RESET(sc); 1533 1534 /* Set the station address. */ 1535 for (i = 0; i < 6; i++) 1536 bus_space_write_1(st, sh, STGE_StationAddress0 + i, 1537 CLLADDR(ifp->if_sadl)[i]); 1538 1539 /* 1540 * Set the statistics masks. Disable all the RMON stats, 1541 * and disable selected stats in the non-RMON stats registers. 1542 */ 1543 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1544 bus_space_write_4(st, sh, STGE_StatisticsMask, 1545 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1546 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1547 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1548 (1U << 21)); 1549 1550 /* Set up the receive filter. */ 1551 stge_set_filter(sc); 1552 1553 /* 1554 * Give the transmit and receive ring to the chip. 1555 */ 1556 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1557 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1558 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1559 1560 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1561 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1562 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1563 1564 /* 1565 * Initialize the Tx auto-poll period. It's OK to make this number 1566 * large (255 is the max, but we use 127) -- we explicitly kick the 1567 * transmit engine when there's actually a packet. 1568 */ 1569 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1570 1571 /* ..and the Rx auto-poll period. */ 1572 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1573 1574 /* Initialize the Tx start threshold. */ 1575 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1576 1577 /* RX DMA thresholds, from linux */ 1578 bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30); 1579 bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30); 1580 1581 /* 1582 * Initialize the Rx DMA interrupt control register. We 1583 * request an interrupt after every incoming packet, but 1584 * defer it for 32us (64 * 512 ns). When the number of 1585 * interrupts pending reaches 8, we stop deferring the 1586 * interrupt, and signal it immediately. 1587 */ 1588 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1589 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1590 1591 /* 1592 * Initialize the interrupt mask. 1593 */ 1594 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1595 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1596 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1597 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1598 1599 /* 1600 * Configure the DMA engine. 1601 * XXX Should auto-tune TxBurstLimit. 1602 */ 1603 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1604 DMAC_TxBurstLimit(3)); 1605 1606 /* 1607 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1608 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1609 * empty again. 1610 */ 1611 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1612 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1613 1614 /* 1615 * Set the maximum frame size. 1616 */ 1617 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1618 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1619 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1620 ETHER_VLAN_ENCAP_LEN : 0)); 1621 1622 /* 1623 * Initialize MacCtrl -- do it before setting the media, 1624 * as setting the media will actually program the register. 1625 * 1626 * Note: We have to poke the IFS value before poking 1627 * anything else. 1628 */ 1629 sc->sc_MACCtrl = MC_IFSSelect(0); 1630 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1631 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1632 #ifdef STGE_VLAN_UNTAG 1633 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1634 #endif 1635 1636 if (sc->sc_rev >= 6) { /* >= B.2 */ 1637 /* Multi-frag frame bug work-around. */ 1638 bus_space_write_2(st, sh, STGE_DebugCtrl, 1639 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1640 1641 /* Tx Poll Now bug work-around. */ 1642 bus_space_write_2(st, sh, STGE_DebugCtrl, 1643 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1644 /* XXX ? from linux */ 1645 bus_space_write_2(st, sh, STGE_DebugCtrl, 1646 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0020); 1647 } 1648 1649 /* 1650 * Set the current media. 1651 */ 1652 if ((error = ether_mediachange(ifp)) != 0) 1653 goto out; 1654 1655 /* 1656 * Start the one second MII clock. 1657 */ 1658 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1659 1660 /* 1661 * ...all done! 1662 */ 1663 ifp->if_flags |= IFF_RUNNING; 1664 ifp->if_flags &= ~IFF_OACTIVE; 1665 1666 out: 1667 if (error) 1668 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1669 return (error); 1670 } 1671 1672 /* 1673 * stge_drain: 1674 * 1675 * Drain the receive queue. 1676 */ 1677 static void 1678 stge_rxdrain(struct stge_softc *sc) 1679 { 1680 struct stge_descsoft *ds; 1681 int i; 1682 1683 for (i = 0; i < STGE_NRXDESC; i++) { 1684 ds = &sc->sc_rxsoft[i]; 1685 if (ds->ds_mbuf != NULL) { 1686 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1687 ds->ds_mbuf->m_next = NULL; 1688 m_freem(ds->ds_mbuf); 1689 ds->ds_mbuf = NULL; 1690 } 1691 } 1692 } 1693 1694 /* 1695 * stge_stop: [ ifnet interface function ] 1696 * 1697 * Stop transmission on the interface. 1698 */ 1699 static void 1700 stge_stop(struct ifnet *ifp, int disable) 1701 { 1702 struct stge_softc *sc = ifp->if_softc; 1703 struct stge_descsoft *ds; 1704 int i; 1705 1706 /* 1707 * Stop the one second clock. 1708 */ 1709 callout_stop(&sc->sc_tick_ch); 1710 1711 /* Down the MII. */ 1712 mii_down(&sc->sc_mii); 1713 1714 /* 1715 * Disable interrupts. 1716 */ 1717 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1718 1719 /* 1720 * Stop receiver, transmitter, and stats update. 1721 */ 1722 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1723 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1724 1725 /* 1726 * Stop the transmit and receive DMA. 1727 */ 1728 stge_dma_wait(sc); 1729 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1730 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1731 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1732 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1733 1734 /* 1735 * Release any queued transmit buffers. 1736 */ 1737 for (i = 0; i < STGE_NTXDESC; i++) { 1738 ds = &sc->sc_txsoft[i]; 1739 if (ds->ds_mbuf != NULL) { 1740 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1741 m_freem(ds->ds_mbuf); 1742 ds->ds_mbuf = NULL; 1743 } 1744 } 1745 1746 /* 1747 * Mark the interface down and cancel the watchdog timer. 1748 */ 1749 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1750 ifp->if_timer = 0; 1751 1752 if (disable) 1753 stge_rxdrain(sc); 1754 } 1755 1756 static int 1757 stge_eeprom_wait(struct stge_softc *sc) 1758 { 1759 int i; 1760 1761 for (i = 0; i < STGE_TIMEOUT; i++) { 1762 delay(1000); 1763 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1764 EC_EepromBusy) == 0) 1765 return (0); 1766 } 1767 return (1); 1768 } 1769 1770 /* 1771 * stge_read_eeprom: 1772 * 1773 * Read data from the serial EEPROM. 1774 */ 1775 static void 1776 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1777 { 1778 1779 if (stge_eeprom_wait(sc)) 1780 printf("%s: EEPROM failed to come ready\n", 1781 sc->sc_dev.dv_xname); 1782 1783 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1784 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1785 if (stge_eeprom_wait(sc)) 1786 printf("%s: EEPROM read timed out\n", 1787 sc->sc_dev.dv_xname); 1788 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1789 } 1790 1791 /* 1792 * stge_add_rxbuf: 1793 * 1794 * Add a receive buffer to the indicated descriptor. 1795 */ 1796 static int 1797 stge_add_rxbuf(struct stge_softc *sc, int idx) 1798 { 1799 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1800 struct mbuf *m; 1801 int error; 1802 1803 MGETHDR(m, M_DONTWAIT, MT_DATA); 1804 if (m == NULL) 1805 return (ENOBUFS); 1806 1807 MCLGET(m, M_DONTWAIT); 1808 if ((m->m_flags & M_EXT) == 0) { 1809 m_freem(m); 1810 return (ENOBUFS); 1811 } 1812 1813 m->m_data = m->m_ext.ext_buf + 2; 1814 m->m_len = MCLBYTES - 2; 1815 1816 if (ds->ds_mbuf != NULL) 1817 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1818 1819 ds->ds_mbuf = m; 1820 1821 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1822 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1823 if (error) { 1824 printf("%s: can't load rx DMA map %d, error = %d\n", 1825 sc->sc_dev.dv_xname, idx, error); 1826 panic("stge_add_rxbuf"); /* XXX */ 1827 } 1828 1829 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1830 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1831 1832 STGE_INIT_RXDESC(sc, idx); 1833 1834 return (0); 1835 } 1836 1837 /* 1838 * stge_set_filter: 1839 * 1840 * Set up the receive filter. 1841 */ 1842 static void 1843 stge_set_filter(struct stge_softc *sc) 1844 { 1845 struct ethercom *ec = &sc->sc_ethercom; 1846 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1847 struct ether_multi *enm; 1848 struct ether_multistep step; 1849 uint32_t crc; 1850 uint32_t mchash[2]; 1851 1852 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1853 if (ifp->if_flags & IFF_BROADCAST) 1854 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1855 1856 /* XXX: ST1023 only works in promiscuous mode */ 1857 if (sc->sc_stge1023) 1858 ifp->if_flags |= IFF_PROMISC; 1859 1860 if (ifp->if_flags & IFF_PROMISC) { 1861 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1862 goto allmulti; 1863 } 1864 1865 /* 1866 * Set up the multicast address filter by passing all multicast 1867 * addresses through a CRC generator, and then using the low-order 1868 * 6 bits as an index into the 64 bit multicast hash table. The 1869 * high order bits select the register, while the rest of the bits 1870 * select the bit within the register. 1871 */ 1872 1873 memset(mchash, 0, sizeof(mchash)); 1874 1875 ETHER_FIRST_MULTI(step, ec, enm); 1876 if (enm == NULL) 1877 goto done; 1878 1879 while (enm != NULL) { 1880 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1881 /* 1882 * We must listen to a range of multicast addresses. 1883 * For now, just accept all multicasts, rather than 1884 * trying to set only those filter bits needed to match 1885 * the range. (At this time, the only use of address 1886 * ranges is for IP multicast routing, for which the 1887 * range is big enough to require all bits set.) 1888 */ 1889 goto allmulti; 1890 } 1891 1892 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1893 1894 /* Just want the 6 least significant bits. */ 1895 crc &= 0x3f; 1896 1897 /* Set the corresponding bit in the hash table. */ 1898 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1899 1900 ETHER_NEXT_MULTI(step, enm); 1901 } 1902 1903 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1904 1905 ifp->if_flags &= ~IFF_ALLMULTI; 1906 goto done; 1907 1908 allmulti: 1909 ifp->if_flags |= IFF_ALLMULTI; 1910 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1911 1912 done: 1913 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1914 /* 1915 * Program the multicast hash table. 1916 */ 1917 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1918 mchash[0]); 1919 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1920 mchash[1]); 1921 } 1922 1923 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1924 sc->sc_ReceiveMode); 1925 } 1926 1927 /* 1928 * stge_mii_readreg: [mii interface function] 1929 * 1930 * Read a PHY register on the MII of the TC9021. 1931 */ 1932 static int 1933 stge_mii_readreg(device_t self, int phy, int reg) 1934 { 1935 1936 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1937 } 1938 1939 /* 1940 * stge_mii_writereg: [mii interface function] 1941 * 1942 * Write a PHY register on the MII of the TC9021. 1943 */ 1944 static void 1945 stge_mii_writereg(device_t self, int phy, int reg, int val) 1946 { 1947 1948 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1949 } 1950 1951 /* 1952 * stge_mii_statchg: [mii interface function] 1953 * 1954 * Callback from MII layer when media changes. 1955 */ 1956 static void 1957 stge_mii_statchg(device_t self) 1958 { 1959 struct stge_softc *sc = device_private(self); 1960 1961 if (sc->sc_mii.mii_media_active & IFM_FDX) 1962 sc->sc_MACCtrl |= MC_DuplexSelect; 1963 else 1964 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1965 1966 /* XXX 802.1x flow-control? */ 1967 1968 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1969 } 1970 1971 /* 1972 * sste_mii_bitbang_read: [mii bit-bang interface function] 1973 * 1974 * Read the MII serial port for the MII bit-bang module. 1975 */ 1976 static uint32_t 1977 stge_mii_bitbang_read(device_t self) 1978 { 1979 struct stge_softc *sc = device_private(self); 1980 1981 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 1982 } 1983 1984 /* 1985 * stge_mii_bitbang_write: [mii big-bang interface function] 1986 * 1987 * Write the MII serial port for the MII bit-bang module. 1988 */ 1989 static void 1990 stge_mii_bitbang_write(device_t self, uint32_t val) 1991 { 1992 struct stge_softc *sc = device_private(self); 1993 1994 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 1995 val | sc->sc_PhyCtrl); 1996 } 1997
Indexes created Fri Oct 03 02:09:57 GMT 2025