if_stge.c revision 1.49.4.2
1 /* $NetBSD: if_stge.c,v 1.49.4.2 2011/03/05 20:53:44 rmind Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. TC9021 10/100/1000 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.49.4.2 2011/03/05 20:53:44 rmind Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/mii_bitbang.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_stgereg.h> 72 73 /* #define STGE_CU_BUG 1 */ 74 #define STGE_VLAN_UNTAG 1 75 /* #define STGE_VLAN_CFI 1 */ 76 77 /* 78 * Transmit descriptor list size. 79 */ 80 #define STGE_NTXDESC 256 81 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 82 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 83 84 /* 85 * Receive descriptor list size. 86 */ 87 #define STGE_NRXDESC 256 88 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 89 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 90 91 /* 92 * Only interrupt every N frames. Must be a power-of-two. 93 */ 94 #define STGE_TXINTR_SPACING 16 95 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 96 97 /* 98 * Control structures are DMA'd to the TC9021 chip. We allocate them in 99 * a single clump that maps to a single DMA segment to make several things 100 * easier. 101 */ 102 struct stge_control_data { 103 /* 104 * The transmit descriptors. 105 */ 106 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 107 108 /* 109 * The receive descriptors. 110 */ 111 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 112 }; 113 114 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 115 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 116 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 117 118 /* 119 * Software state for transmit and receive jobs. 120 */ 121 struct stge_descsoft { 122 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 123 bus_dmamap_t ds_dmamap; /* our DMA map */ 124 }; 125 126 /* 127 * Software state per device. 128 */ 129 struct stge_softc { 130 device_t sc_dev; /* generic device information */ 131 bus_space_tag_t sc_st; /* bus space tag */ 132 bus_space_handle_t sc_sh; /* bus space handle */ 133 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 134 struct ethercom sc_ethercom; /* ethernet common data */ 135 int sc_rev; /* silicon revision */ 136 137 void *sc_ih; /* interrupt cookie */ 138 139 struct mii_data sc_mii; /* MII/media information */ 140 141 callout_t sc_tick_ch; /* tick callout */ 142 143 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 144 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 145 146 /* 147 * Software state for transmit and receive descriptors. 148 */ 149 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 150 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 151 152 /* 153 * Control data structures. 154 */ 155 struct stge_control_data *sc_control_data; 156 #define sc_txdescs sc_control_data->scd_txdescs 157 #define sc_rxdescs sc_control_data->scd_rxdescs 158 159 #ifdef STGE_EVENT_COUNTERS 160 /* 161 * Event counters. 162 */ 163 struct evcnt sc_ev_txstall; /* Tx stalled */ 164 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 165 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 166 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 167 168 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 169 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 170 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 171 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 172 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 173 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 174 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 175 176 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 177 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 178 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 179 180 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 181 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 182 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 183 #endif /* STGE_EVENT_COUNTERS */ 184 185 int sc_txpending; /* number of Tx requests pending */ 186 int sc_txdirty; /* first dirty Tx descriptor */ 187 int sc_txlast; /* last used Tx descriptor */ 188 189 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 190 int sc_rxdiscard; 191 int sc_rxlen; 192 struct mbuf *sc_rxhead; 193 struct mbuf *sc_rxtail; 194 struct mbuf **sc_rxtailp; 195 196 int sc_txthresh; /* Tx threshold */ 197 uint32_t sc_usefiber:1; /* if we're fiber */ 198 uint32_t sc_stge1023:1; /* are we a 1023 */ 199 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 200 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 201 uint16_t sc_IntEnable; /* prototype IntEnable register */ 202 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 203 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 204 }; 205 206 #define STGE_RXCHAIN_RESET(sc) \ 207 do { \ 208 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 209 *(sc)->sc_rxtailp = NULL; \ 210 (sc)->sc_rxlen = 0; \ 211 } while (/*CONSTCOND*/0) 212 213 #define STGE_RXCHAIN_LINK(sc, m) \ 214 do { \ 215 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 216 (sc)->sc_rxtailp = &(m)->m_next; \ 217 } while (/*CONSTCOND*/0) 218 219 #ifdef STGE_EVENT_COUNTERS 220 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 221 #else 222 #define STGE_EVCNT_INCR(ev) /* nothing */ 223 #endif 224 225 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 226 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 227 228 #define STGE_CDTXSYNC(sc, x, ops) \ 229 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 230 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 231 232 #define STGE_CDRXSYNC(sc, x, ops) \ 233 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 234 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 235 236 #define STGE_INIT_RXDESC(sc, x) \ 237 do { \ 238 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 239 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 240 \ 241 /* \ 242 * Note: We scoot the packet forward 2 bytes in the buffer \ 243 * so that the payload after the Ethernet header is aligned \ 244 * to a 4-byte boundary. \ 245 */ \ 246 __rfd->rfd_frag.frag_word0 = \ 247 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 248 FRAG_LEN(MCLBYTES - 2)); \ 249 __rfd->rfd_next = \ 250 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 251 __rfd->rfd_status = 0; \ 252 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 253 } while (/*CONSTCOND*/0) 254 255 #define STGE_TIMEOUT 1000 256 257 static void stge_start(struct ifnet *); 258 static void stge_watchdog(struct ifnet *); 259 static int stge_ioctl(struct ifnet *, u_long, void *); 260 static int stge_init(struct ifnet *); 261 static void stge_stop(struct ifnet *, int); 262 263 static bool stge_shutdown(device_t, int); 264 265 static void stge_reset(struct stge_softc *); 266 static void stge_rxdrain(struct stge_softc *); 267 static int stge_add_rxbuf(struct stge_softc *, int); 268 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 269 static void stge_tick(void *); 270 271 static void stge_stats_update(struct stge_softc *); 272 273 static void stge_set_filter(struct stge_softc *); 274 275 static int stge_intr(void *); 276 static void stge_txintr(struct stge_softc *); 277 static void stge_rxintr(struct stge_softc *); 278 279 static int stge_mii_readreg(device_t, int, int); 280 static void stge_mii_writereg(device_t, int, int, int); 281 static void stge_mii_statchg(device_t); 282 283 static int stge_match(device_t, cfdata_t, void *); 284 static void stge_attach(device_t, device_t, void *); 285 286 int stge_copy_small = 0; 287 288 CFATTACH_DECL_NEW(stge, sizeof(struct stge_softc), 289 stge_match, stge_attach, NULL, NULL); 290 291 static uint32_t stge_mii_bitbang_read(device_t); 292 static void stge_mii_bitbang_write(device_t, uint32_t); 293 294 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 295 stge_mii_bitbang_read, 296 stge_mii_bitbang_write, 297 { 298 PC_MgmtData, /* MII_BIT_MDO */ 299 PC_MgmtData, /* MII_BIT_MDI */ 300 PC_MgmtClk, /* MII_BIT_MDC */ 301 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 302 0, /* MII_BIT_DIR_PHY_HOST */ 303 } 304 }; 305 306 /* 307 * Devices supported by this driver. 308 */ 309 static const struct stge_product { 310 pci_vendor_id_t stge_vendor; 311 pci_product_id_t stge_product; 312 const char *stge_name; 313 } stge_products[] = { 314 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023, 315 "Sundance ST-1023 Gigabit Ethernet" }, 316 317 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 318 "Sundance ST-2021 Gigabit Ethernet" }, 319 320 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 321 "Tamarack TC9021 Gigabit Ethernet" }, 322 323 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 324 "Tamarack TC9021 Gigabit Ethernet" }, 325 326 /* 327 * The Sundance sample boards use the Sundance vendor ID, 328 * but the Tamarack product ID. 329 */ 330 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 331 "Sundance TC9021 Gigabit Ethernet" }, 332 333 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 334 "Sundance TC9021 Gigabit Ethernet" }, 335 336 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 337 "D-Link DL-4000 Gigabit Ethernet" }, 338 339 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 340 "Antares Gigabit Ethernet" }, 341 342 { 0, 0, 343 NULL }, 344 }; 345 346 static const struct stge_product * 347 stge_lookup(const struct pci_attach_args *pa) 348 { 349 const struct stge_product *sp; 350 351 for (sp = stge_products; sp->stge_name != NULL; sp++) { 352 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 353 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 354 return (sp); 355 } 356 return (NULL); 357 } 358 359 static int 360 stge_match(device_t parent, cfdata_t cf, void *aux) 361 { 362 struct pci_attach_args *pa = aux; 363 364 if (stge_lookup(pa) != NULL) 365 return (1); 366 367 return (0); 368 } 369 370 static void 371 stge_attach(device_t parent, device_t self, void *aux) 372 { 373 struct stge_softc *sc = device_private(self); 374 struct pci_attach_args *pa = aux; 375 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 376 pci_chipset_tag_t pc = pa->pa_pc; 377 pci_intr_handle_t ih; 378 const char *intrstr = NULL; 379 bus_space_tag_t iot, memt; 380 bus_space_handle_t ioh, memh; 381 bus_dma_segment_t seg; 382 int ioh_valid, memh_valid; 383 int i, rseg, error; 384 const struct stge_product *sp; 385 uint8_t enaddr[ETHER_ADDR_LEN]; 386 387 callout_init(&sc->sc_tick_ch, 0); 388 389 sp = stge_lookup(pa); 390 if (sp == NULL) { 391 printf("\n"); 392 panic("ste_attach: impossible"); 393 } 394 395 sc->sc_rev = PCI_REVISION(pa->pa_class); 396 397 aprint_normal(": %s, rev. %d\n", sp->stge_name, sc->sc_rev); 398 399 /* 400 * Map the device. 401 */ 402 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 403 PCI_MAPREG_TYPE_IO, 0, 404 &iot, &ioh, NULL, NULL) == 0); 405 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 406 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 407 &memt, &memh, NULL, NULL) == 0); 408 409 if (memh_valid) { 410 sc->sc_st = memt; 411 sc->sc_sh = memh; 412 } else if (ioh_valid) { 413 sc->sc_st = iot; 414 sc->sc_sh = ioh; 415 } else { 416 aprint_error_dev(self, "unable to map device registers\n"); 417 return; 418 } 419 420 sc->sc_dmat = pa->pa_dmat; 421 422 /* Enable bus mastering. */ 423 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 424 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 425 PCI_COMMAND_MASTER_ENABLE); 426 427 /* power up chip */ 428 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 429 error != EOPNOTSUPP) { 430 aprint_error_dev(self, "cannot activate %d\n", 431 error); 432 return; 433 } 434 /* 435 * Map and establish our interrupt. 436 */ 437 if (pci_intr_map(pa, &ih)) { 438 aprint_error_dev(self, "unable to map interrupt\n"); 439 return; 440 } 441 intrstr = pci_intr_string(pc, ih); 442 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc); 443 if (sc->sc_ih == NULL) { 444 aprint_error_dev(self, "unable to establish interrupt"); 445 if (intrstr != NULL) 446 aprint_error(" at %s", intrstr); 447 aprint_error("\n"); 448 return; 449 } 450 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 451 452 /* 453 * Allocate the control data structures, and create and load the 454 * DMA map for it. 455 */ 456 if ((error = bus_dmamem_alloc(sc->sc_dmat, 457 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 458 0)) != 0) { 459 aprint_error_dev(self, 460 "unable to allocate control data, error = %d\n", 461 error); 462 goto fail_0; 463 } 464 465 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 466 sizeof(struct stge_control_data), (void **)&sc->sc_control_data, 467 BUS_DMA_COHERENT)) != 0) { 468 aprint_error_dev(self, 469 "unable to map control data, error = %d\n", 470 error); 471 goto fail_1; 472 } 473 474 if ((error = bus_dmamap_create(sc->sc_dmat, 475 sizeof(struct stge_control_data), 1, 476 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 477 aprint_error_dev(self, 478 "unable to create control data DMA map, error = %d\n", 479 error); 480 goto fail_2; 481 } 482 483 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 484 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 485 0)) != 0) { 486 aprint_error_dev(self, 487 "unable to load control data DMA map, error = %d\n", 488 error); 489 goto fail_3; 490 } 491 492 /* 493 * Create the transmit buffer DMA maps. Note that rev B.3 494 * and earlier seem to have a bug regarding multi-fragment 495 * packets. We need to limit the number of Tx segments on 496 * such chips to 1. 497 */ 498 for (i = 0; i < STGE_NTXDESC; i++) { 499 if ((error = bus_dmamap_create(sc->sc_dmat, 500 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 501 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 502 aprint_error_dev(self, 503 "unable to create tx DMA map %d, error = %d\n", 504 i, error); 505 goto fail_4; 506 } 507 } 508 509 /* 510 * Create the receive buffer DMA maps. 511 */ 512 for (i = 0; i < STGE_NRXDESC; i++) { 513 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 514 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 515 aprint_error_dev(self, 516 "unable to create rx DMA map %d, error = %d\n", 517 i, error); 518 goto fail_5; 519 } 520 sc->sc_rxsoft[i].ds_mbuf = NULL; 521 } 522 523 /* 524 * Determine if we're copper or fiber. It affects how we 525 * reset the card. 526 */ 527 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 528 AC_PhyMedia) 529 sc->sc_usefiber = 1; 530 else 531 sc->sc_usefiber = 0; 532 533 /* 534 * Reset the chip to a known state. 535 */ 536 stge_reset(sc); 537 538 /* 539 * Reading the station address from the EEPROM doesn't seem 540 * to work, at least on my sample boards. Instead, since 541 * the reset sequence does AutoInit, read it from the station 542 * address registers. For Sundance 1023 you can only read it 543 * from EEPROM. 544 */ 545 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) { 546 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh, 547 STGE_StationAddress0) & 0xff; 548 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh, 549 STGE_StationAddress0) >> 8; 550 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh, 551 STGE_StationAddress1) & 0xff; 552 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh, 553 STGE_StationAddress1) >> 8; 554 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh, 555 STGE_StationAddress2) & 0xff; 556 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh, 557 STGE_StationAddress2) >> 8; 558 sc->sc_stge1023 = 0; 559 } else { 560 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 561 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 562 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 563 &myaddr[i]); 564 myaddr[i] = le16toh(myaddr[i]); 565 } 566 (void)memcpy(enaddr, myaddr, sizeof(enaddr)); 567 sc->sc_stge1023 = 1; 568 } 569 570 aprint_normal_dev(self, "Ethernet address %s\n", 571 ether_sprintf(enaddr)); 572 573 /* 574 * Read some important bits from the PhyCtrl register. 575 */ 576 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh, 577 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 578 579 /* 580 * Initialize our media structures and probe the MII. 581 */ 582 sc->sc_mii.mii_ifp = ifp; 583 sc->sc_mii.mii_readreg = stge_mii_readreg; 584 sc->sc_mii.mii_writereg = stge_mii_writereg; 585 sc->sc_mii.mii_statchg = stge_mii_statchg; 586 sc->sc_ethercom.ec_mii = &sc->sc_mii; 587 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 588 ether_mediastatus); 589 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 590 MII_OFFSET_ANY, MIIF_DOPAUSE); 591 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 592 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 593 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 594 } else 595 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 596 597 ifp = &sc->sc_ethercom.ec_if; 598 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 599 ifp->if_softc = sc; 600 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 601 ifp->if_ioctl = stge_ioctl; 602 ifp->if_start = stge_start; 603 ifp->if_watchdog = stge_watchdog; 604 ifp->if_init = stge_init; 605 ifp->if_stop = stge_stop; 606 IFQ_SET_READY(&ifp->if_snd); 607 608 /* 609 * The manual recommends disabling early transmit, so we 610 * do. It's disabled anyway, if using IP checksumming, 611 * since the entire packet must be in the FIFO in order 612 * for the chip to perform the checksum. 613 */ 614 sc->sc_txthresh = 0x0fff; 615 616 /* 617 * Disable MWI if the PCI layer tells us to. 618 */ 619 sc->sc_DMACtrl = 0; 620 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 621 sc->sc_DMACtrl |= DMAC_MWIDisable; 622 623 /* 624 * We can support 802.1Q VLAN-sized frames and jumbo 625 * Ethernet frames. 626 * 627 * XXX Figure out how to do hw-assisted VLAN tagging in 628 * XXX a reasonable way on this chip. 629 */ 630 sc->sc_ethercom.ec_capabilities |= 631 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 632 ETHERCAP_VLAN_HWTAGGING; 633 634 /* 635 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 636 */ 637 sc->sc_ethercom.ec_if.if_capabilities |= 638 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 639 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 640 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 641 642 /* 643 * Attach the interface. 644 */ 645 if_attach(ifp); 646 ether_ifattach(ifp, enaddr); 647 648 #ifdef STGE_EVENT_COUNTERS 649 /* 650 * Attach event counters. 651 */ 652 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 653 NULL, device_xname(self), "txstall"); 654 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 655 NULL, device_xname(self), "txdmaintr"); 656 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 657 NULL, device_xname(self), "txindintr"); 658 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 659 NULL, device_xname(self), "rxintr"); 660 661 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 662 NULL, device_xname(self), "txseg1"); 663 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 664 NULL, device_xname(self), "txseg2"); 665 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 666 NULL, device_xname(self), "txseg3"); 667 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 668 NULL, device_xname(self), "txseg4"); 669 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 670 NULL, device_xname(self), "txseg5"); 671 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 672 NULL, device_xname(self), "txsegmore"); 673 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 674 NULL, device_xname(self), "txcopy"); 675 676 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 677 NULL, device_xname(self), "rxipsum"); 678 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 679 NULL, device_xname(self), "rxtcpsum"); 680 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 681 NULL, device_xname(self), "rxudpsum"); 682 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 683 NULL, device_xname(self), "txipsum"); 684 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 685 NULL, device_xname(self), "txtcpsum"); 686 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 687 NULL, device_xname(self), "txudpsum"); 688 #endif /* STGE_EVENT_COUNTERS */ 689 690 /* 691 * Make sure the interface is shutdown during reboot. 692 */ 693 if (pmf_device_register1(self, NULL, NULL, stge_shutdown)) 694 pmf_class_network_register(self, ifp); 695 else 696 aprint_error_dev(self, "couldn't establish power handler\n"); 697 698 return; 699 700 /* 701 * Free any resources we've allocated during the failed attach 702 * attempt. Do this in reverse order and fall through. 703 */ 704 fail_5: 705 for (i = 0; i < STGE_NRXDESC; i++) { 706 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 707 bus_dmamap_destroy(sc->sc_dmat, 708 sc->sc_rxsoft[i].ds_dmamap); 709 } 710 fail_4: 711 for (i = 0; i < STGE_NTXDESC; i++) { 712 if (sc->sc_txsoft[i].ds_dmamap != NULL) 713 bus_dmamap_destroy(sc->sc_dmat, 714 sc->sc_txsoft[i].ds_dmamap); 715 } 716 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 717 fail_3: 718 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 719 fail_2: 720 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 721 sizeof(struct stge_control_data)); 722 fail_1: 723 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 724 fail_0: 725 return; 726 } 727 728 /* 729 * stge_shutdown: 730 * 731 * Make sure the interface is stopped at reboot time. 732 */ 733 static bool 734 stge_shutdown(device_t self, int howto) 735 { 736 struct stge_softc *sc = device_private(self); 737 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 738 739 stge_stop(ifp, 1); 740 741 return true; 742 } 743 744 static void 745 stge_dma_wait(struct stge_softc *sc) 746 { 747 int i; 748 749 for (i = 0; i < STGE_TIMEOUT; i++) { 750 delay(2); 751 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) & 752 DMAC_TxDMAInProg) == 0) 753 break; 754 } 755 756 if (i == STGE_TIMEOUT) 757 printf("%s: DMA wait timed out\n", device_xname(sc->sc_dev)); 758 } 759 760 /* 761 * stge_start: [ifnet interface function] 762 * 763 * Start packet transmission on the interface. 764 */ 765 static void 766 stge_start(struct ifnet *ifp) 767 { 768 struct stge_softc *sc = ifp->if_softc; 769 struct mbuf *m0; 770 struct stge_descsoft *ds; 771 struct stge_tfd *tfd; 772 bus_dmamap_t dmamap; 773 int error, firsttx, nexttx, opending, seg, totlen; 774 uint64_t csum_flags; 775 776 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 777 return; 778 779 /* 780 * Remember the previous number of pending transmissions 781 * and the first descriptor we will use. 782 */ 783 opending = sc->sc_txpending; 784 firsttx = STGE_NEXTTX(sc->sc_txlast); 785 786 /* 787 * Loop through the send queue, setting up transmit descriptors 788 * until we drain the queue, or use up all available transmit 789 * descriptors. 790 */ 791 for (;;) { 792 struct m_tag *mtag; 793 uint64_t tfc; 794 795 /* 796 * Grab a packet off the queue. 797 */ 798 IFQ_POLL(&ifp->if_snd, m0); 799 if (m0 == NULL) 800 break; 801 802 /* 803 * Leave one unused descriptor at the end of the 804 * list to prevent wrapping completely around. 805 */ 806 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 807 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 808 break; 809 } 810 811 /* 812 * See if we have any VLAN stuff. 813 */ 814 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 815 816 /* 817 * Get the last and next available transmit descriptor. 818 */ 819 nexttx = STGE_NEXTTX(sc->sc_txlast); 820 tfd = &sc->sc_txdescs[nexttx]; 821 ds = &sc->sc_txsoft[nexttx]; 822 823 dmamap = ds->ds_dmamap; 824 825 /* 826 * Load the DMA map. If this fails, the packet either 827 * didn't fit in the alloted number of segments, or we 828 * were short on resources. For the too-many-segments 829 * case, we simply report an error and drop the packet, 830 * since we can't sanely copy a jumbo packet to a single 831 * buffer. 832 */ 833 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 834 BUS_DMA_NOWAIT); 835 if (error) { 836 if (error == EFBIG) { 837 printf("%s: Tx packet consumes too many " 838 "DMA segments, dropping...\n", 839 device_xname(sc->sc_dev)); 840 IFQ_DEQUEUE(&ifp->if_snd, m0); 841 m_freem(m0); 842 continue; 843 } 844 /* 845 * Short on resources, just stop for now. 846 */ 847 break; 848 } 849 850 IFQ_DEQUEUE(&ifp->if_snd, m0); 851 852 /* 853 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 854 */ 855 856 /* Sync the DMA map. */ 857 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 858 BUS_DMASYNC_PREWRITE); 859 860 /* Initialize the fragment list. */ 861 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 862 tfd->tfd_frags[seg].frag_word0 = 863 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 864 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 865 totlen += dmamap->dm_segs[seg].ds_len; 866 } 867 868 #ifdef STGE_EVENT_COUNTERS 869 switch (dmamap->dm_nsegs) { 870 case 1: 871 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 872 break; 873 case 2: 874 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 875 break; 876 case 3: 877 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 878 break; 879 case 4: 880 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 881 break; 882 case 5: 883 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 884 break; 885 default: 886 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 887 break; 888 } 889 #endif /* STGE_EVENT_COUNTERS */ 890 891 /* 892 * Initialize checksumming flags in the descriptor. 893 * Byte-swap constants so the compiler can optimize. 894 */ 895 csum_flags = 0; 896 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 897 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 898 csum_flags |= TFD_IPChecksumEnable; 899 } 900 901 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 902 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 903 csum_flags |= TFD_TCPChecksumEnable; 904 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 905 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 906 csum_flags |= TFD_UDPChecksumEnable; 907 } 908 909 /* 910 * Initialize the descriptor and give it to the chip. 911 * Check to see if we have a VLAN tag to insert. 912 */ 913 914 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 915 TFD_FragCount(seg) | csum_flags | 916 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 917 TFD_TxDMAIndicate : 0); 918 if (mtag) { 919 #if 0 920 struct ether_header *eh = 921 mtod(m0, struct ether_header *); 922 u_int16_t etype = ntohs(eh->ether_type); 923 printf("%s: xmit (tag %d) etype %x\n", 924 ifp->if_xname, *mtod(n, int *), etype); 925 #endif 926 tfc |= TFD_VLANTagInsert | 927 #ifdef STGE_VLAN_CFI 928 TFD_CFI | 929 #endif 930 TFD_VID(VLAN_TAG_VALUE(mtag)); 931 } 932 tfd->tfd_control = htole64(tfc); 933 934 /* Sync the descriptor. */ 935 STGE_CDTXSYNC(sc, nexttx, 936 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 937 938 /* 939 * Kick the transmit DMA logic. 940 */ 941 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl, 942 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 943 944 /* 945 * Store a pointer to the packet so we can free it later. 946 */ 947 ds->ds_mbuf = m0; 948 949 /* Advance the tx pointer. */ 950 sc->sc_txpending++; 951 sc->sc_txlast = nexttx; 952 953 /* 954 * Pass the packet to any BPF listeners. 955 */ 956 bpf_mtap(ifp, m0); 957 } 958 959 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 960 /* No more slots left; notify upper layer. */ 961 ifp->if_flags |= IFF_OACTIVE; 962 } 963 964 if (sc->sc_txpending != opending) { 965 /* 966 * We enqueued packets. If the transmitter was idle, 967 * reset the txdirty pointer. 968 */ 969 if (opending == 0) 970 sc->sc_txdirty = firsttx; 971 972 /* Set a watchdog timer in case the chip flakes out. */ 973 ifp->if_timer = 5; 974 } 975 } 976 977 /* 978 * stge_watchdog: [ifnet interface function] 979 * 980 * Watchdog timer handler. 981 */ 982 static void 983 stge_watchdog(struct ifnet *ifp) 984 { 985 struct stge_softc *sc = ifp->if_softc; 986 987 /* 988 * Sweep up first, since we don't interrupt every frame. 989 */ 990 stge_txintr(sc); 991 if (sc->sc_txpending != 0) { 992 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 993 ifp->if_oerrors++; 994 995 (void) stge_init(ifp); 996 997 /* Try to get more packets going. */ 998 stge_start(ifp); 999 } 1000 } 1001 1002 /* 1003 * stge_ioctl: [ifnet interface function] 1004 * 1005 * Handle control requests from the operator. 1006 */ 1007 static int 1008 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1009 { 1010 struct stge_softc *sc = ifp->if_softc; 1011 int s, error; 1012 1013 s = splnet(); 1014 1015 error = ether_ioctl(ifp, cmd, data); 1016 if (error == ENETRESET) { 1017 error = 0; 1018 1019 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1020 ; 1021 else if (ifp->if_flags & IFF_RUNNING) { 1022 /* 1023 * Multicast list has changed; set the hardware filter 1024 * accordingly. 1025 */ 1026 stge_set_filter(sc); 1027 } 1028 } 1029 1030 /* Try to get more packets going. */ 1031 stge_start(ifp); 1032 1033 splx(s); 1034 return (error); 1035 } 1036 1037 /* 1038 * stge_intr: 1039 * 1040 * Interrupt service routine. 1041 */ 1042 static int 1043 stge_intr(void *arg) 1044 { 1045 struct stge_softc *sc = arg; 1046 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1047 uint32_t txstat; 1048 int wantinit; 1049 uint16_t isr; 1050 1051 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) & 1052 IS_InterruptStatus) == 0) 1053 return (0); 1054 1055 for (wantinit = 0; wantinit == 0;) { 1056 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck); 1057 if ((isr & sc->sc_IntEnable) == 0) 1058 break; 1059 1060 /* Host interface errors. */ 1061 if (isr & IS_HostError) { 1062 printf("%s: Host interface error\n", 1063 device_xname(sc->sc_dev)); 1064 wantinit = 1; 1065 continue; 1066 } 1067 1068 /* Receive interrupts. */ 1069 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) { 1070 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1071 stge_rxintr(sc); 1072 if (isr & IS_RFDListEnd) { 1073 printf("%s: receive ring overflow\n", 1074 device_xname(sc->sc_dev)); 1075 /* 1076 * XXX Should try to recover from this 1077 * XXX more gracefully. 1078 */ 1079 wantinit = 1; 1080 } 1081 } 1082 1083 /* Transmit interrupts. */ 1084 if (isr & (IS_TxDMAComplete|IS_TxComplete)) { 1085 #ifdef STGE_EVENT_COUNTERS 1086 if (isr & IS_TxDMAComplete) 1087 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1088 #endif 1089 stge_txintr(sc); 1090 } 1091 1092 /* Statistics overflow. */ 1093 if (isr & IS_UpdateStats) 1094 stge_stats_update(sc); 1095 1096 /* Transmission errors. */ 1097 if (isr & IS_TxComplete) { 1098 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1099 for (;;) { 1100 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh, 1101 STGE_TxStatus); 1102 if ((txstat & TS_TxComplete) == 0) 1103 break; 1104 if (txstat & TS_TxUnderrun) { 1105 sc->sc_txthresh++; 1106 if (sc->sc_txthresh > 0x0fff) 1107 sc->sc_txthresh = 0x0fff; 1108 printf("%s: transmit underrun, new " 1109 "threshold: %d bytes\n", 1110 device_xname(sc->sc_dev), 1111 sc->sc_txthresh << 5); 1112 } 1113 if (txstat & TS_MaxCollisions) 1114 printf("%s: excessive collisions\n", 1115 device_xname(sc->sc_dev)); 1116 } 1117 wantinit = 1; 1118 } 1119 1120 } 1121 1122 if (wantinit) 1123 stge_init(ifp); 1124 1125 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 1126 sc->sc_IntEnable); 1127 1128 /* Try to get more packets going. */ 1129 stge_start(ifp); 1130 1131 return (1); 1132 } 1133 1134 /* 1135 * stge_txintr: 1136 * 1137 * Helper; handle transmit interrupts. 1138 */ 1139 static void 1140 stge_txintr(struct stge_softc *sc) 1141 { 1142 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1143 struct stge_descsoft *ds; 1144 uint64_t control; 1145 int i; 1146 1147 ifp->if_flags &= ~IFF_OACTIVE; 1148 1149 /* 1150 * Go through our Tx list and free mbufs for those 1151 * frames which have been transmitted. 1152 */ 1153 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1154 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1155 ds = &sc->sc_txsoft[i]; 1156 1157 STGE_CDTXSYNC(sc, i, 1158 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1159 1160 control = le64toh(sc->sc_txdescs[i].tfd_control); 1161 if ((control & TFD_TFDDone) == 0) 1162 break; 1163 1164 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1165 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1166 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1167 m_freem(ds->ds_mbuf); 1168 ds->ds_mbuf = NULL; 1169 } 1170 1171 /* Update the dirty transmit buffer pointer. */ 1172 sc->sc_txdirty = i; 1173 1174 /* 1175 * If there are no more pending transmissions, cancel the watchdog 1176 * timer. 1177 */ 1178 if (sc->sc_txpending == 0) 1179 ifp->if_timer = 0; 1180 } 1181 1182 /* 1183 * stge_rxintr: 1184 * 1185 * Helper; handle receive interrupts. 1186 */ 1187 static void 1188 stge_rxintr(struct stge_softc *sc) 1189 { 1190 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1191 struct stge_descsoft *ds; 1192 struct mbuf *m, *tailm; 1193 uint64_t status; 1194 int i, len; 1195 1196 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1197 ds = &sc->sc_rxsoft[i]; 1198 1199 STGE_CDRXSYNC(sc, i, 1200 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1201 1202 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1203 1204 if ((status & RFD_RFDDone) == 0) 1205 break; 1206 1207 if (__predict_false(sc->sc_rxdiscard)) { 1208 STGE_INIT_RXDESC(sc, i); 1209 if (status & RFD_FrameEnd) { 1210 /* Reset our state. */ 1211 sc->sc_rxdiscard = 0; 1212 } 1213 continue; 1214 } 1215 1216 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1217 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1218 1219 m = ds->ds_mbuf; 1220 1221 /* 1222 * Add a new receive buffer to the ring. 1223 */ 1224 if (stge_add_rxbuf(sc, i) != 0) { 1225 /* 1226 * Failed, throw away what we've done so 1227 * far, and discard the rest of the packet. 1228 */ 1229 ifp->if_ierrors++; 1230 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1231 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1232 STGE_INIT_RXDESC(sc, i); 1233 if ((status & RFD_FrameEnd) == 0) 1234 sc->sc_rxdiscard = 1; 1235 if (sc->sc_rxhead != NULL) 1236 m_freem(sc->sc_rxhead); 1237 STGE_RXCHAIN_RESET(sc); 1238 continue; 1239 } 1240 1241 #ifdef DIAGNOSTIC 1242 if (status & RFD_FrameStart) { 1243 KASSERT(sc->sc_rxhead == NULL); 1244 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1245 } 1246 #endif 1247 1248 STGE_RXCHAIN_LINK(sc, m); 1249 1250 /* 1251 * If this is not the end of the packet, keep 1252 * looking. 1253 */ 1254 if ((status & RFD_FrameEnd) == 0) { 1255 sc->sc_rxlen += m->m_len; 1256 continue; 1257 } 1258 1259 /* 1260 * Okay, we have the entire packet now... 1261 */ 1262 *sc->sc_rxtailp = NULL; 1263 m = sc->sc_rxhead; 1264 tailm = sc->sc_rxtail; 1265 1266 STGE_RXCHAIN_RESET(sc); 1267 1268 /* 1269 * If the packet had an error, drop it. Note we 1270 * count the error later in the periodic stats update. 1271 */ 1272 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1273 RFD_RxAlignmentError | RFD_RxFCSError | 1274 RFD_RxLengthError)) { 1275 m_freem(m); 1276 continue; 1277 } 1278 1279 /* 1280 * No errors. 1281 * 1282 * Note we have configured the chip to not include 1283 * the CRC at the end of the packet. 1284 */ 1285 len = RFD_RxDMAFrameLen(status); 1286 tailm->m_len = len - sc->sc_rxlen; 1287 1288 /* 1289 * If the packet is small enough to fit in a 1290 * single header mbuf, allocate one and copy 1291 * the data into it. This greatly reduces 1292 * memory consumption when we receive lots 1293 * of small packets. 1294 */ 1295 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1296 struct mbuf *nm; 1297 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1298 if (nm == NULL) { 1299 ifp->if_ierrors++; 1300 m_freem(m); 1301 continue; 1302 } 1303 nm->m_data += 2; 1304 nm->m_pkthdr.len = nm->m_len = len; 1305 m_copydata(m, 0, len, mtod(nm, void *)); 1306 m_freem(m); 1307 m = nm; 1308 } 1309 1310 /* 1311 * Set the incoming checksum information for the packet. 1312 */ 1313 if (status & RFD_IPDetected) { 1314 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1315 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1316 if (status & RFD_IPError) 1317 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1318 if (status & RFD_TCPDetected) { 1319 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1320 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1321 if (status & RFD_TCPError) 1322 m->m_pkthdr.csum_flags |= 1323 M_CSUM_TCP_UDP_BAD; 1324 } else if (status & RFD_UDPDetected) { 1325 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1326 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1327 if (status & RFD_UDPError) 1328 m->m_pkthdr.csum_flags |= 1329 M_CSUM_TCP_UDP_BAD; 1330 } 1331 } 1332 1333 m->m_pkthdr.rcvif = ifp; 1334 m->m_pkthdr.len = len; 1335 1336 /* 1337 * Pass this up to any BPF listeners, but only 1338 * pass if up the stack if it's for us. 1339 */ 1340 bpf_mtap(ifp, m); 1341 #ifdef STGE_VLAN_UNTAG 1342 /* 1343 * Check for VLAN tagged packets 1344 */ 1345 if (status & RFD_VLANDetected) 1346 VLAN_INPUT_TAG(ifp, m, RFD_TCI(status), continue); 1347 1348 #endif 1349 #if 0 1350 if (status & RFD_VLANDetected) { 1351 struct ether_header *eh; 1352 u_int16_t etype; 1353 1354 eh = mtod(m, struct ether_header *); 1355 etype = ntohs(eh->ether_type); 1356 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1357 ifp->if_xname, (u_int16_t) RFD_TCI(status), 1358 etype); 1359 } 1360 #endif 1361 /* Pass it on. */ 1362 (*ifp->if_input)(ifp, m); 1363 } 1364 1365 /* Update the receive pointer. */ 1366 sc->sc_rxptr = i; 1367 } 1368 1369 /* 1370 * stge_tick: 1371 * 1372 * One second timer, used to tick the MII. 1373 */ 1374 static void 1375 stge_tick(void *arg) 1376 { 1377 struct stge_softc *sc = arg; 1378 int s; 1379 1380 s = splnet(); 1381 mii_tick(&sc->sc_mii); 1382 stge_stats_update(sc); 1383 splx(s); 1384 1385 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1386 } 1387 1388 /* 1389 * stge_stats_update: 1390 * 1391 * Read the TC9021 statistics counters. 1392 */ 1393 static void 1394 stge_stats_update(struct stge_softc *sc) 1395 { 1396 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1397 bus_space_tag_t st = sc->sc_st; 1398 bus_space_handle_t sh = sc->sc_sh; 1399 1400 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk); 1401 1402 ifp->if_ipackets += 1403 bus_space_read_4(st, sh, STGE_FramesRcvdOk); 1404 1405 ifp->if_ierrors += 1406 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors); 1407 1408 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk); 1409 1410 ifp->if_opackets += 1411 bus_space_read_4(st, sh, STGE_FramesXmtdOk); 1412 1413 ifp->if_collisions += 1414 bus_space_read_4(st, sh, STGE_LateCollisions) + 1415 bus_space_read_4(st, sh, STGE_MultiColFrames) + 1416 bus_space_read_4(st, sh, STGE_SingleColFrames); 1417 1418 ifp->if_oerrors += 1419 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) + 1420 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal); 1421 } 1422 1423 /* 1424 * stge_reset: 1425 * 1426 * Perform a soft reset on the TC9021. 1427 */ 1428 static void 1429 stge_reset(struct stge_softc *sc) 1430 { 1431 uint32_t ac; 1432 int i; 1433 1434 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl); 1435 1436 /* 1437 * Only assert RstOut if we're fiber. We need GMII clocks 1438 * to be present in order for the reset to complete on fiber 1439 * cards. 1440 */ 1441 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl, 1442 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1443 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1444 (sc->sc_usefiber ? AC_RstOut : 0)); 1445 1446 delay(50000); 1447 1448 for (i = 0; i < STGE_TIMEOUT; i++) { 1449 delay(5000); 1450 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) & 1451 AC_ResetBusy) == 0) 1452 break; 1453 } 1454 1455 if (i == STGE_TIMEOUT) 1456 printf("%s: reset failed to complete\n", 1457 device_xname(sc->sc_dev)); 1458 1459 delay(1000); 1460 } 1461 1462 /* 1463 * stge_init: [ ifnet interface function ] 1464 * 1465 * Initialize the interface. Must be called at splnet(). 1466 */ 1467 static int 1468 stge_init(struct ifnet *ifp) 1469 { 1470 struct stge_softc *sc = ifp->if_softc; 1471 bus_space_tag_t st = sc->sc_st; 1472 bus_space_handle_t sh = sc->sc_sh; 1473 struct stge_descsoft *ds; 1474 int i, error = 0; 1475 1476 /* 1477 * Cancel any pending I/O. 1478 */ 1479 stge_stop(ifp, 0); 1480 1481 /* 1482 * Reset the chip to a known state. 1483 */ 1484 stge_reset(sc); 1485 1486 /* 1487 * Initialize the transmit descriptor ring. 1488 */ 1489 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1490 for (i = 0; i < STGE_NTXDESC; i++) { 1491 sc->sc_txdescs[i].tfd_next = htole64( 1492 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1493 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1494 } 1495 sc->sc_txpending = 0; 1496 sc->sc_txdirty = 0; 1497 sc->sc_txlast = STGE_NTXDESC - 1; 1498 1499 /* 1500 * Initialize the receive descriptor and receive job 1501 * descriptor rings. 1502 */ 1503 for (i = 0; i < STGE_NRXDESC; i++) { 1504 ds = &sc->sc_rxsoft[i]; 1505 if (ds->ds_mbuf == NULL) { 1506 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1507 printf("%s: unable to allocate or map rx " 1508 "buffer %d, error = %d\n", 1509 device_xname(sc->sc_dev), i, error); 1510 /* 1511 * XXX Should attempt to run with fewer receive 1512 * XXX buffers instead of just failing. 1513 */ 1514 stge_rxdrain(sc); 1515 goto out; 1516 } 1517 } else 1518 STGE_INIT_RXDESC(sc, i); 1519 } 1520 sc->sc_rxptr = 0; 1521 sc->sc_rxdiscard = 0; 1522 STGE_RXCHAIN_RESET(sc); 1523 1524 /* Set the station address. */ 1525 for (i = 0; i < 6; i++) 1526 bus_space_write_1(st, sh, STGE_StationAddress0 + i, 1527 CLLADDR(ifp->if_sadl)[i]); 1528 1529 /* 1530 * Set the statistics masks. Disable all the RMON stats, 1531 * and disable selected stats in the non-RMON stats registers. 1532 */ 1533 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff); 1534 bus_space_write_4(st, sh, STGE_StatisticsMask, 1535 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1536 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1537 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1538 (1U << 21)); 1539 1540 /* Set up the receive filter. */ 1541 stge_set_filter(sc); 1542 1543 /* 1544 * Give the transmit and receive ring to the chip. 1545 */ 1546 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1547 bus_space_write_4(st, sh, STGE_TFDListPtrLo, 1548 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1549 1550 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1551 bus_space_write_4(st, sh, STGE_RFDListPtrLo, 1552 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1553 1554 /* 1555 * Initialize the Tx auto-poll period. It's OK to make this number 1556 * large (255 is the max, but we use 127) -- we explicitly kick the 1557 * transmit engine when there's actually a packet. 1558 */ 1559 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127); 1560 1561 /* ..and the Rx auto-poll period. */ 1562 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64); 1563 1564 /* Initialize the Tx start threshold. */ 1565 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh); 1566 1567 /* RX DMA thresholds, from linux */ 1568 bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30); 1569 bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30); 1570 1571 /* 1572 * Initialize the Rx DMA interrupt control register. We 1573 * request an interrupt after every incoming packet, but 1574 * defer it for 32us (64 * 512 ns). When the number of 1575 * interrupts pending reaches 8, we stop deferring the 1576 * interrupt, and signal it immediately. 1577 */ 1578 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl, 1579 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1580 1581 /* 1582 * Initialize the interrupt mask. 1583 */ 1584 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1585 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1586 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff); 1587 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable); 1588 1589 /* 1590 * Configure the DMA engine. 1591 * XXX Should auto-tune TxBurstLimit. 1592 */ 1593 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl | 1594 DMAC_TxBurstLimit(3)); 1595 1596 /* 1597 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1598 * FIFO, and send an un-PAUSE frame when the FIFO is totally 1599 * empty again. 1600 */ 1601 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16); 1602 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0); 1603 1604 /* 1605 * Set the maximum frame size. 1606 */ 1607 bus_space_write_2(st, sh, STGE_MaxFrameSize, 1608 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1609 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1610 ETHER_VLAN_ENCAP_LEN : 0)); 1611 1612 /* 1613 * Initialize MacCtrl -- do it before setting the media, 1614 * as setting the media will actually program the register. 1615 * 1616 * Note: We have to poke the IFS value before poking 1617 * anything else. 1618 */ 1619 sc->sc_MACCtrl = MC_IFSSelect(0); 1620 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl); 1621 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1622 #ifdef STGE_VLAN_UNTAG 1623 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1624 #endif 1625 1626 if (sc->sc_rev >= 6) { /* >= B.2 */ 1627 /* Multi-frag frame bug work-around. */ 1628 bus_space_write_2(st, sh, STGE_DebugCtrl, 1629 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200); 1630 1631 /* Tx Poll Now bug work-around. */ 1632 bus_space_write_2(st, sh, STGE_DebugCtrl, 1633 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010); 1634 /* XXX ? from linux */ 1635 bus_space_write_2(st, sh, STGE_DebugCtrl, 1636 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0020); 1637 } 1638 1639 /* 1640 * Set the current media. 1641 */ 1642 if ((error = ether_mediachange(ifp)) != 0) 1643 goto out; 1644 1645 /* 1646 * Start the one second MII clock. 1647 */ 1648 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1649 1650 /* 1651 * ...all done! 1652 */ 1653 ifp->if_flags |= IFF_RUNNING; 1654 ifp->if_flags &= ~IFF_OACTIVE; 1655 1656 out: 1657 if (error) 1658 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1659 return (error); 1660 } 1661 1662 /* 1663 * stge_drain: 1664 * 1665 * Drain the receive queue. 1666 */ 1667 static void 1668 stge_rxdrain(struct stge_softc *sc) 1669 { 1670 struct stge_descsoft *ds; 1671 int i; 1672 1673 for (i = 0; i < STGE_NRXDESC; i++) { 1674 ds = &sc->sc_rxsoft[i]; 1675 if (ds->ds_mbuf != NULL) { 1676 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1677 ds->ds_mbuf->m_next = NULL; 1678 m_freem(ds->ds_mbuf); 1679 ds->ds_mbuf = NULL; 1680 } 1681 } 1682 } 1683 1684 /* 1685 * stge_stop: [ ifnet interface function ] 1686 * 1687 * Stop transmission on the interface. 1688 */ 1689 static void 1690 stge_stop(struct ifnet *ifp, int disable) 1691 { 1692 struct stge_softc *sc = ifp->if_softc; 1693 struct stge_descsoft *ds; 1694 int i; 1695 1696 /* 1697 * Stop the one second clock. 1698 */ 1699 callout_stop(&sc->sc_tick_ch); 1700 1701 /* Down the MII. */ 1702 mii_down(&sc->sc_mii); 1703 1704 /* 1705 * Disable interrupts. 1706 */ 1707 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0); 1708 1709 /* 1710 * Stop receiver, transmitter, and stats update. 1711 */ 1712 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, 1713 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1714 1715 /* 1716 * Stop the transmit and receive DMA. 1717 */ 1718 stge_dma_wait(sc); 1719 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0); 1720 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0); 1721 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0); 1722 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0); 1723 1724 /* 1725 * Release any queued transmit buffers. 1726 */ 1727 for (i = 0; i < STGE_NTXDESC; i++) { 1728 ds = &sc->sc_txsoft[i]; 1729 if (ds->ds_mbuf != NULL) { 1730 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1731 m_freem(ds->ds_mbuf); 1732 ds->ds_mbuf = NULL; 1733 } 1734 } 1735 1736 /* 1737 * Mark the interface down and cancel the watchdog timer. 1738 */ 1739 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1740 ifp->if_timer = 0; 1741 1742 if (disable) 1743 stge_rxdrain(sc); 1744 } 1745 1746 static int 1747 stge_eeprom_wait(struct stge_softc *sc) 1748 { 1749 int i; 1750 1751 for (i = 0; i < STGE_TIMEOUT; i++) { 1752 delay(1000); 1753 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) & 1754 EC_EepromBusy) == 0) 1755 return (0); 1756 } 1757 return (1); 1758 } 1759 1760 /* 1761 * stge_read_eeprom: 1762 * 1763 * Read data from the serial EEPROM. 1764 */ 1765 static void 1766 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1767 { 1768 1769 if (stge_eeprom_wait(sc)) 1770 printf("%s: EEPROM failed to come ready\n", 1771 device_xname(sc->sc_dev)); 1772 1773 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl, 1774 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1775 if (stge_eeprom_wait(sc)) 1776 printf("%s: EEPROM read timed out\n", 1777 device_xname(sc->sc_dev)); 1778 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData); 1779 } 1780 1781 /* 1782 * stge_add_rxbuf: 1783 * 1784 * Add a receive buffer to the indicated descriptor. 1785 */ 1786 static int 1787 stge_add_rxbuf(struct stge_softc *sc, int idx) 1788 { 1789 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1790 struct mbuf *m; 1791 int error; 1792 1793 MGETHDR(m, M_DONTWAIT, MT_DATA); 1794 if (m == NULL) 1795 return (ENOBUFS); 1796 1797 MCLGET(m, M_DONTWAIT); 1798 if ((m->m_flags & M_EXT) == 0) { 1799 m_freem(m); 1800 return (ENOBUFS); 1801 } 1802 1803 m->m_data = m->m_ext.ext_buf + 2; 1804 m->m_len = MCLBYTES - 2; 1805 1806 if (ds->ds_mbuf != NULL) 1807 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1808 1809 ds->ds_mbuf = m; 1810 1811 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1812 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1813 if (error) { 1814 printf("%s: can't load rx DMA map %d, error = %d\n", 1815 device_xname(sc->sc_dev), idx, error); 1816 panic("stge_add_rxbuf"); /* XXX */ 1817 } 1818 1819 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1820 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1821 1822 STGE_INIT_RXDESC(sc, idx); 1823 1824 return (0); 1825 } 1826 1827 /* 1828 * stge_set_filter: 1829 * 1830 * Set up the receive filter. 1831 */ 1832 static void 1833 stge_set_filter(struct stge_softc *sc) 1834 { 1835 struct ethercom *ec = &sc->sc_ethercom; 1836 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1837 struct ether_multi *enm; 1838 struct ether_multistep step; 1839 uint32_t crc; 1840 uint32_t mchash[2]; 1841 1842 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1843 if (ifp->if_flags & IFF_BROADCAST) 1844 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1845 1846 /* XXX: ST1023 only works in promiscuous mode */ 1847 if (sc->sc_stge1023) 1848 ifp->if_flags |= IFF_PROMISC; 1849 1850 if (ifp->if_flags & IFF_PROMISC) { 1851 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1852 goto allmulti; 1853 } 1854 1855 /* 1856 * Set up the multicast address filter by passing all multicast 1857 * addresses through a CRC generator, and then using the low-order 1858 * 6 bits as an index into the 64 bit multicast hash table. The 1859 * high order bits select the register, while the rest of the bits 1860 * select the bit within the register. 1861 */ 1862 1863 memset(mchash, 0, sizeof(mchash)); 1864 1865 ETHER_FIRST_MULTI(step, ec, enm); 1866 if (enm == NULL) 1867 goto done; 1868 1869 while (enm != NULL) { 1870 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1871 /* 1872 * We must listen to a range of multicast addresses. 1873 * For now, just accept all multicasts, rather than 1874 * trying to set only those filter bits needed to match 1875 * the range. (At this time, the only use of address 1876 * ranges is for IP multicast routing, for which the 1877 * range is big enough to require all bits set.) 1878 */ 1879 goto allmulti; 1880 } 1881 1882 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1883 1884 /* Just want the 6 least significant bits. */ 1885 crc &= 0x3f; 1886 1887 /* Set the corresponding bit in the hash table. */ 1888 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1889 1890 ETHER_NEXT_MULTI(step, enm); 1891 } 1892 1893 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1894 1895 ifp->if_flags &= ~IFF_ALLMULTI; 1896 goto done; 1897 1898 allmulti: 1899 ifp->if_flags |= IFF_ALLMULTI; 1900 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1901 1902 done: 1903 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1904 /* 1905 * Program the multicast hash table. 1906 */ 1907 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0, 1908 mchash[0]); 1909 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1, 1910 mchash[1]); 1911 } 1912 1913 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode, 1914 sc->sc_ReceiveMode); 1915 } 1916 1917 /* 1918 * stge_mii_readreg: [mii interface function] 1919 * 1920 * Read a PHY register on the MII of the TC9021. 1921 */ 1922 static int 1923 stge_mii_readreg(device_t self, int phy, int reg) 1924 { 1925 1926 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg)); 1927 } 1928 1929 /* 1930 * stge_mii_writereg: [mii interface function] 1931 * 1932 * Write a PHY register on the MII of the TC9021. 1933 */ 1934 static void 1935 stge_mii_writereg(device_t self, int phy, int reg, int val) 1936 { 1937 1938 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val); 1939 } 1940 1941 /* 1942 * stge_mii_statchg: [mii interface function] 1943 * 1944 * Callback from MII layer when media changes. 1945 */ 1946 static void 1947 stge_mii_statchg(device_t self) 1948 { 1949 struct stge_softc *sc = device_private(self); 1950 1951 if (sc->sc_mii.mii_media_active & IFM_FDX) 1952 sc->sc_MACCtrl |= MC_DuplexSelect; 1953 else 1954 sc->sc_MACCtrl &= ~MC_DuplexSelect; 1955 1956 /* XXX 802.1x flow-control? */ 1957 1958 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl); 1959 } 1960 1961 /* 1962 * sste_mii_bitbang_read: [mii bit-bang interface function] 1963 * 1964 * Read the MII serial port for the MII bit-bang module. 1965 */ 1966 static uint32_t 1967 stge_mii_bitbang_read(device_t self) 1968 { 1969 struct stge_softc *sc = device_private(self); 1970 1971 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl)); 1972 } 1973 1974 /* 1975 * stge_mii_bitbang_write: [mii big-bang interface function] 1976 * 1977 * Write the MII serial port for the MII bit-bang module. 1978 */ 1979 static void 1980 stge_mii_bitbang_write(device_t self, uint32_t val) 1981 { 1982 struct stge_softc *sc = device_private(self); 1983 1984 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl, 1985 val | sc->sc_PhyCtrl); 1986 } 1987
Indexes created Fri Oct 03 02:09:57 GMT 2025