if_stge.c revision 1.77
1 /* $NetBSD: if_stge.c,v 1.77 2020/01/14 09:49:26 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. TC9021 10/100/1000 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.77 2020/01/14 09:49:26 msaitoh Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/mii_bitbang.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_stgereg.h> 72 73 #include <prop/proplib.h> 74 75 /* #define STGE_CU_BUG 1 */ 76 #define STGE_VLAN_UNTAG 1 77 /* #define STGE_VLAN_CFI 1 */ 78 79 /* 80 * Transmit descriptor list size. 81 */ 82 #define STGE_NTXDESC 256 83 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 84 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 85 86 /* 87 * Receive descriptor list size. 88 */ 89 #define STGE_NRXDESC 256 90 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 91 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 92 93 /* 94 * Only interrupt every N frames. Must be a power-of-two. 95 */ 96 #define STGE_TXINTR_SPACING 16 97 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 98 99 /* 100 * Control structures are DMA'd to the TC9021 chip. We allocate them in 101 * a single clump that maps to a single DMA segment to make several things 102 * easier. 103 */ 104 struct stge_control_data { 105 /* 106 * The transmit descriptors. 107 */ 108 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 109 110 /* 111 * The receive descriptors. 112 */ 113 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 114 }; 115 116 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 117 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 118 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 119 120 /* 121 * Software state for transmit and receive jobs. 122 */ 123 struct stge_descsoft { 124 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 125 bus_dmamap_t ds_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct stge_softc { 132 device_t sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 int sc_rev; /* silicon revision */ 138 139 void *sc_ih; /* interrupt cookie */ 140 141 struct mii_data sc_mii; /* MII/media information */ 142 143 callout_t sc_tick_ch; /* tick callout */ 144 145 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* 149 * Software state for transmit and receive descriptors. 150 */ 151 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 152 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 153 154 /* 155 * Control data structures. 156 */ 157 struct stge_control_data *sc_control_data; 158 #define sc_txdescs sc_control_data->scd_txdescs 159 #define sc_rxdescs sc_control_data->scd_rxdescs 160 161 #ifdef STGE_EVENT_COUNTERS 162 /* 163 * Event counters. 164 */ 165 struct evcnt sc_ev_txstall; /* Tx stalled */ 166 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 167 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 168 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 169 170 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 171 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 172 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 173 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 174 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 175 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 176 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 177 178 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 179 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 180 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 181 182 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 183 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 184 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 185 #endif /* STGE_EVENT_COUNTERS */ 186 187 int sc_txpending; /* number of Tx requests pending */ 188 int sc_txdirty; /* first dirty Tx descriptor */ 189 int sc_txlast; /* last used Tx descriptor */ 190 191 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 192 int sc_rxdiscard; 193 int sc_rxlen; 194 struct mbuf *sc_rxhead; 195 struct mbuf *sc_rxtail; 196 struct mbuf **sc_rxtailp; 197 198 int sc_txthresh; /* Tx threshold */ 199 uint32_t sc_usefiber:1; /* if we're fiber */ 200 uint32_t sc_stge1023:1; /* are we a 1023 */ 201 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 202 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 203 uint16_t sc_IntEnable; /* prototype IntEnable register */ 204 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 205 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 206 }; 207 208 #define STGE_RXCHAIN_RESET(sc) \ 209 do { \ 210 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 211 *(sc)->sc_rxtailp = NULL; \ 212 (sc)->sc_rxlen = 0; \ 213 } while (/*CONSTCOND*/0) 214 215 #define STGE_RXCHAIN_LINK(sc, m) \ 216 do { \ 217 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 218 (sc)->sc_rxtailp = &(m)->m_next; \ 219 } while (/*CONSTCOND*/0) 220 221 /* 222 * Register access macros 223 */ 224 #define CSR_WRITE_4(_sc, reg, val) \ 225 bus_space_write_4((_sc)->sc_st, (_sc)->sc_sh, (reg), (val)) 226 #define CSR_WRITE_2(_sc, reg, val) \ 227 bus_space_write_2((_sc)->sc_st, (_sc)->sc_sh, (reg), (val)) 228 #define CSR_WRITE_1(_sc, reg, val) \ 229 bus_space_write_1((_sc)->sc_st, (_sc)->sc_sh, (reg), (val)) 230 231 #define CSR_READ_4(_sc, reg) \ 232 bus_space_read_4((_sc)->sc_st, (_sc)->sc_sh, (reg)) 233 #define CSR_READ_2(_sc, reg) \ 234 bus_space_read_2((_sc)->sc_st, (_sc)->sc_sh, (reg)) 235 #define CSR_READ_1(_sc, reg) \ 236 bus_space_read_1((_sc)->sc_st, (_sc)->sc_sh, (reg)) 237 238 #define STGE_TIMEOUT 1000 239 240 #ifdef STGE_EVENT_COUNTERS 241 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 242 #else 243 #define STGE_EVCNT_INCR(ev) /* nothing */ 244 #endif 245 246 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 247 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 248 249 #define STGE_CDTXSYNC(sc, x, ops) \ 250 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 251 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 252 253 #define STGE_CDRXSYNC(sc, x, ops) \ 254 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 255 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 256 257 #define STGE_INIT_RXDESC(sc, x) \ 258 do { \ 259 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 260 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 261 \ 262 /* \ 263 * Note: We scoot the packet forward 2 bytes in the buffer \ 264 * so that the payload after the Ethernet header is aligned \ 265 * to a 4-byte boundary. \ 266 */ \ 267 __rfd->rfd_frag.frag_word0 = \ 268 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 269 FRAG_LEN(MCLBYTES - 2)); \ 270 __rfd->rfd_next = \ 271 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 272 __rfd->rfd_status = 0; \ 273 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \ 274 } while (/*CONSTCOND*/0) 275 276 static void stge_start(struct ifnet *); 277 static void stge_watchdog(struct ifnet *); 278 static int stge_ioctl(struct ifnet *, u_long, void *); 279 static int stge_init(struct ifnet *); 280 static void stge_stop(struct ifnet *, int); 281 282 static bool stge_shutdown(device_t, int); 283 284 static void stge_reset(struct stge_softc *); 285 static void stge_rxdrain(struct stge_softc *); 286 static int stge_add_rxbuf(struct stge_softc *, int); 287 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 288 static void stge_tick(void *); 289 290 static void stge_stats_update(struct stge_softc *); 291 292 static void stge_set_filter(struct stge_softc *); 293 294 static int stge_intr(void *); 295 static void stge_txintr(struct stge_softc *); 296 static void stge_rxintr(struct stge_softc *); 297 298 static int stge_mii_readreg(device_t, int, int, uint16_t *); 299 static int stge_mii_writereg(device_t, int, int, uint16_t); 300 static void stge_mii_statchg(struct ifnet *); 301 302 static int stge_match(device_t, cfdata_t, void *); 303 static void stge_attach(device_t, device_t, void *); 304 305 int stge_copy_small = 0; 306 307 CFATTACH_DECL_NEW(stge, sizeof(struct stge_softc), 308 stge_match, stge_attach, NULL, NULL); 309 310 static uint32_t stge_mii_bitbang_read(device_t); 311 static void stge_mii_bitbang_write(device_t, uint32_t); 312 313 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 314 stge_mii_bitbang_read, 315 stge_mii_bitbang_write, 316 { 317 PC_MgmtData, /* MII_BIT_MDO */ 318 PC_MgmtData, /* MII_BIT_MDI */ 319 PC_MgmtClk, /* MII_BIT_MDC */ 320 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 321 0, /* MII_BIT_DIR_PHY_HOST */ 322 } 323 }; 324 325 /* 326 * Devices supported by this driver. 327 */ 328 static const struct stge_product { 329 pci_vendor_id_t stge_vendor; 330 pci_product_id_t stge_product; 331 const char *stge_name; 332 } stge_products[] = { 333 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023, 334 "Sundance ST-1023 Gigabit Ethernet" }, 335 336 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 337 "Sundance ST-2021 Gigabit Ethernet" }, 338 339 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 340 "Tamarack TC9021 Gigabit Ethernet" }, 341 342 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 343 "Tamarack TC9021 Gigabit Ethernet" }, 344 345 /* 346 * The Sundance sample boards use the Sundance vendor ID, 347 * but the Tamarack product ID. 348 */ 349 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 350 "Sundance TC9021 Gigabit Ethernet" }, 351 352 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 353 "Sundance TC9021 Gigabit Ethernet" }, 354 355 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 356 "D-Link DL-4000 Gigabit Ethernet" }, 357 358 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 359 "Antares Gigabit Ethernet" }, 360 361 { 0, 0, 362 NULL }, 363 }; 364 365 static const struct stge_product * 366 stge_lookup(const struct pci_attach_args *pa) 367 { 368 const struct stge_product *sp; 369 370 for (sp = stge_products; sp->stge_name != NULL; sp++) { 371 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 372 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 373 return (sp); 374 } 375 return (NULL); 376 } 377 378 static int 379 stge_match(device_t parent, cfdata_t cf, void *aux) 380 { 381 struct pci_attach_args *pa = aux; 382 383 if (stge_lookup(pa) != NULL) 384 return (1); 385 386 return (0); 387 } 388 389 static void 390 stge_attach(device_t parent, device_t self, void *aux) 391 { 392 struct stge_softc *sc = device_private(self); 393 struct pci_attach_args *pa = aux; 394 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 395 struct mii_data * const mii = &sc->sc_mii; 396 pci_chipset_tag_t pc = pa->pa_pc; 397 pci_intr_handle_t ih; 398 const char *intrstr = NULL; 399 bus_space_tag_t iot, memt; 400 bus_space_handle_t ioh, memh; 401 bus_dma_segment_t seg; 402 prop_dictionary_t dict; 403 prop_data_t data; 404 int ioh_valid, memh_valid; 405 int i, rseg, error; 406 const struct stge_product *sp; 407 uint8_t enaddr[ETHER_ADDR_LEN]; 408 char intrbuf[PCI_INTRSTR_LEN]; 409 410 sc->sc_dev = self; 411 callout_init(&sc->sc_tick_ch, 0); 412 413 sp = stge_lookup(pa); 414 if (sp == NULL) { 415 printf("\n"); 416 panic("ste_attach: impossible"); 417 } 418 419 sc->sc_rev = PCI_REVISION(pa->pa_class); 420 421 pci_aprint_devinfo_fancy(pa, NULL, sp->stge_name, 1); 422 423 /* 424 * Map the device. 425 */ 426 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 427 PCI_MAPREG_TYPE_IO, 0, 428 &iot, &ioh, NULL, NULL) == 0); 429 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 430 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 431 &memt, &memh, NULL, NULL) == 0); 432 433 if (memh_valid) { 434 sc->sc_st = memt; 435 sc->sc_sh = memh; 436 } else if (ioh_valid) { 437 sc->sc_st = iot; 438 sc->sc_sh = ioh; 439 } else { 440 aprint_error_dev(self, "unable to map device registers\n"); 441 return; 442 } 443 444 sc->sc_dmat = pa->pa_dmat; 445 446 /* Enable bus mastering. */ 447 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 448 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 449 PCI_COMMAND_MASTER_ENABLE); 450 451 /* power up chip */ 452 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 453 error != EOPNOTSUPP) { 454 aprint_error_dev(self, "cannot activate %d\n", error); 455 return; 456 } 457 /* 458 * Map and establish our interrupt. 459 */ 460 if (pci_intr_map(pa, &ih)) { 461 aprint_error_dev(self, "unable to map interrupt\n"); 462 return; 463 } 464 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 465 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, stge_intr, sc, 466 device_xname(self)); 467 if (sc->sc_ih == NULL) { 468 aprint_error_dev(self, "unable to establish interrupt"); 469 if (intrstr != NULL) 470 aprint_error(" at %s", intrstr); 471 aprint_error("\n"); 472 return; 473 } 474 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 475 476 /* 477 * Allocate the control data structures, and create and load the 478 * DMA map for it. 479 */ 480 if ((error = bus_dmamem_alloc(sc->sc_dmat, 481 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 482 0)) != 0) { 483 aprint_error_dev(self, 484 "unable to allocate control data, error = %d\n", error); 485 goto fail_0; 486 } 487 488 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 489 sizeof(struct stge_control_data), (void **)&sc->sc_control_data, 490 BUS_DMA_COHERENT)) != 0) { 491 aprint_error_dev(self, 492 "unable to map control data, error = %d\n", error); 493 goto fail_1; 494 } 495 496 if ((error = bus_dmamap_create(sc->sc_dmat, 497 sizeof(struct stge_control_data), 1, 498 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 499 aprint_error_dev(self, 500 "unable to create control data DMA map, error = %d\n", 501 error); 502 goto fail_2; 503 } 504 505 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 506 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 507 0)) != 0) { 508 aprint_error_dev(self, 509 "unable to load control data DMA map, error = %d\n", 510 error); 511 goto fail_3; 512 } 513 514 /* 515 * Create the transmit buffer DMA maps. Note that rev B.3 516 * and earlier seem to have a bug regarding multi-fragment 517 * packets. We need to limit the number of Tx segments on 518 * such chips to 1. 519 */ 520 for (i = 0; i < STGE_NTXDESC; i++) { 521 if ((error = bus_dmamap_create(sc->sc_dmat, 522 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 523 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 524 aprint_error_dev(self, 525 "unable to create tx DMA map %d, error = %d\n", 526 i, error); 527 goto fail_4; 528 } 529 } 530 531 /* 532 * Create the receive buffer DMA maps. 533 */ 534 for (i = 0; i < STGE_NRXDESC; i++) { 535 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 536 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 537 aprint_error_dev(self, 538 "unable to create rx DMA map %d, error = %d\n", 539 i, error); 540 goto fail_5; 541 } 542 sc->sc_rxsoft[i].ds_mbuf = NULL; 543 } 544 545 /* 546 * Determine if we're copper or fiber. It affects how we 547 * reset the card. 548 */ 549 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) 550 sc->sc_usefiber = 1; 551 else 552 sc->sc_usefiber = 0; 553 554 /* 555 * Reset the chip to a known state. 556 */ 557 stge_reset(sc); 558 559 /* 560 * Reading the station address from the EEPROM doesn't seem 561 * to work, at least on my sample boards. Instead, since 562 * the reset sequence does AutoInit, read it from the station 563 * address registers. For Sundance 1023 you can only read it 564 * from EEPROM. 565 */ 566 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) { 567 enaddr[0] = CSR_READ_2(sc, STGE_StationAddress0) & 0xff; 568 enaddr[1] = CSR_READ_2(sc, STGE_StationAddress0) >> 8; 569 enaddr[2] = CSR_READ_2(sc, STGE_StationAddress1) & 0xff; 570 enaddr[3] = CSR_READ_2(sc, STGE_StationAddress1) >> 8; 571 enaddr[4] = CSR_READ_2(sc, STGE_StationAddress2) & 0xff; 572 enaddr[5] = CSR_READ_2(sc, STGE_StationAddress2) >> 8; 573 sc->sc_stge1023 = 0; 574 } else { 575 data = prop_dictionary_get(device_properties(self), 576 "mac-address"); 577 if (data != NULL) { 578 /* 579 * Try to get the station address from device 580 * properties first, in case the EEPROM is missing. 581 */ 582 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 583 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 584 (void)memcpy(enaddr, prop_data_data_nocopy(data), 585 ETHER_ADDR_LEN); 586 } else { 587 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 588 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 589 stge_read_eeprom(sc, 590 STGE_EEPROM_StationAddress0 + i, 591 &myaddr[i]); 592 myaddr[i] = le16toh(myaddr[i]); 593 } 594 (void)memcpy(enaddr, myaddr, sizeof(enaddr)); 595 } 596 sc->sc_stge1023 = 1; 597 } 598 599 /* Set need_loaddspcode before mii_attach() */ 600 dict = device_properties(self); 601 prop_dictionary_set_bool(dict, "need_loaddspcode", 602 ((sc->sc_rev >= 0x40) && (sc->sc_rev <= 0x4e)) ? true : false); 603 604 aprint_normal_dev(self, "Ethernet address %s\n", 605 ether_sprintf(enaddr)); 606 607 /* 608 * Read some important bits from the PhyCtrl register. 609 */ 610 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & 611 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 612 613 /* 614 * Initialize our media structures and probe the MII. 615 */ 616 mii->mii_ifp = ifp; 617 mii->mii_readreg = stge_mii_readreg; 618 mii->mii_writereg = stge_mii_writereg; 619 mii->mii_statchg = stge_mii_statchg; 620 sc->sc_ethercom.ec_mii = mii; 621 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 622 ether_mediastatus); 623 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 624 MII_OFFSET_ANY, MIIF_DOPAUSE); 625 if (LIST_FIRST(&mii->mii_phys) == NULL) { 626 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 627 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 628 } else 629 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 630 631 ifp = &sc->sc_ethercom.ec_if; 632 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 633 ifp->if_softc = sc; 634 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 635 ifp->if_ioctl = stge_ioctl; 636 ifp->if_start = stge_start; 637 ifp->if_watchdog = stge_watchdog; 638 ifp->if_init = stge_init; 639 ifp->if_stop = stge_stop; 640 IFQ_SET_READY(&ifp->if_snd); 641 642 /* 643 * The manual recommends disabling early transmit, so we 644 * do. It's disabled anyway, if using IP checksumming, 645 * since the entire packet must be in the FIFO in order 646 * for the chip to perform the checksum. 647 */ 648 sc->sc_txthresh = 0x0fff; 649 650 /* 651 * Disable MWI if the PCI layer tells us to. 652 */ 653 sc->sc_DMACtrl = 0; 654 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 655 sc->sc_DMACtrl |= DMAC_MWIDisable; 656 657 /* 658 * We can support 802.1Q VLAN-sized frames and jumbo 659 * Ethernet frames. 660 * 661 * XXX Figure out how to do hw-assisted VLAN tagging in 662 * XXX a reasonable way on this chip. 663 */ 664 sc->sc_ethercom.ec_capabilities |= 665 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 666 ETHERCAP_VLAN_HWTAGGING; 667 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 668 669 /* 670 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 671 */ 672 sc->sc_ethercom.ec_if.if_capabilities |= 673 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 674 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 675 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 676 677 /* 678 * Attach the interface. 679 */ 680 if_attach(ifp); 681 if_deferred_start_init(ifp, NULL); 682 ether_ifattach(ifp, enaddr); 683 684 #ifdef STGE_EVENT_COUNTERS 685 /* 686 * Attach event counters. 687 */ 688 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 689 NULL, device_xname(self), "txstall"); 690 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 691 NULL, device_xname(self), "txdmaintr"); 692 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 693 NULL, device_xname(self), "txindintr"); 694 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 695 NULL, device_xname(self), "rxintr"); 696 697 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 698 NULL, device_xname(self), "txseg1"); 699 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 700 NULL, device_xname(self), "txseg2"); 701 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 702 NULL, device_xname(self), "txseg3"); 703 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 704 NULL, device_xname(self), "txseg4"); 705 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 706 NULL, device_xname(self), "txseg5"); 707 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 708 NULL, device_xname(self), "txsegmore"); 709 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 710 NULL, device_xname(self), "txcopy"); 711 712 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 713 NULL, device_xname(self), "rxipsum"); 714 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 715 NULL, device_xname(self), "rxtcpsum"); 716 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 717 NULL, device_xname(self), "rxudpsum"); 718 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 719 NULL, device_xname(self), "txipsum"); 720 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 721 NULL, device_xname(self), "txtcpsum"); 722 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 723 NULL, device_xname(self), "txudpsum"); 724 #endif /* STGE_EVENT_COUNTERS */ 725 726 /* 727 * Make sure the interface is shutdown during reboot. 728 */ 729 if (pmf_device_register1(self, NULL, NULL, stge_shutdown)) 730 pmf_class_network_register(self, ifp); 731 else 732 aprint_error_dev(self, "couldn't establish power handler\n"); 733 734 return; 735 736 /* 737 * Free any resources we've allocated during the failed attach 738 * attempt. Do this in reverse order and fall through. 739 */ 740 fail_5: 741 for (i = 0; i < STGE_NRXDESC; i++) { 742 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 743 bus_dmamap_destroy(sc->sc_dmat, 744 sc->sc_rxsoft[i].ds_dmamap); 745 } 746 fail_4: 747 for (i = 0; i < STGE_NTXDESC; i++) { 748 if (sc->sc_txsoft[i].ds_dmamap != NULL) 749 bus_dmamap_destroy(sc->sc_dmat, 750 sc->sc_txsoft[i].ds_dmamap); 751 } 752 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 753 fail_3: 754 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 755 fail_2: 756 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 757 sizeof(struct stge_control_data)); 758 fail_1: 759 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 760 fail_0: 761 return; 762 } 763 764 /* 765 * stge_shutdown: 766 * 767 * Make sure the interface is stopped at reboot time. 768 */ 769 static bool 770 stge_shutdown(device_t self, int howto) 771 { 772 struct stge_softc *sc = device_private(self); 773 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 774 775 stge_stop(ifp, 1); 776 stge_reset(sc); 777 return true; 778 } 779 780 static void 781 stge_dma_wait(struct stge_softc *sc) 782 { 783 int i; 784 785 for (i = 0; i < STGE_TIMEOUT; i++) { 786 delay(2); 787 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) 788 break; 789 } 790 791 if (i == STGE_TIMEOUT) 792 printf("%s: DMA wait timed out\n", device_xname(sc->sc_dev)); 793 } 794 795 /* 796 * stge_start: [ifnet interface function] 797 * 798 * Start packet transmission on the interface. 799 */ 800 static void 801 stge_start(struct ifnet *ifp) 802 { 803 struct stge_softc *sc = ifp->if_softc; 804 struct mbuf *m0; 805 struct stge_descsoft *ds; 806 struct stge_tfd *tfd; 807 bus_dmamap_t dmamap; 808 int error, firsttx, nexttx, opending, seg, totlen; 809 uint64_t csum_flags; 810 811 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 812 return; 813 814 /* 815 * Remember the previous number of pending transmissions 816 * and the first descriptor we will use. 817 */ 818 opending = sc->sc_txpending; 819 firsttx = STGE_NEXTTX(sc->sc_txlast); 820 821 /* 822 * Loop through the send queue, setting up transmit descriptors 823 * until we drain the queue, or use up all available transmit 824 * descriptors. 825 */ 826 for (;;) { 827 uint64_t tfc; 828 bool have_vtag; 829 uint16_t vtag; 830 831 /* 832 * Grab a packet off the queue. 833 */ 834 IFQ_POLL(&ifp->if_snd, m0); 835 if (m0 == NULL) 836 break; 837 838 /* 839 * Leave one unused descriptor at the end of the 840 * list to prevent wrapping completely around. 841 */ 842 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 843 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 844 break; 845 } 846 847 /* 848 * See if we have any VLAN stuff. 849 */ 850 have_vtag = vlan_has_tag(m0); 851 if (have_vtag) 852 vtag = vlan_get_tag(m0); 853 854 /* 855 * Get the last and next available transmit descriptor. 856 */ 857 nexttx = STGE_NEXTTX(sc->sc_txlast); 858 tfd = &sc->sc_txdescs[nexttx]; 859 ds = &sc->sc_txsoft[nexttx]; 860 861 dmamap = ds->ds_dmamap; 862 863 /* 864 * Load the DMA map. If this fails, the packet either 865 * didn't fit in the alloted number of segments, or we 866 * were short on resources. For the too-many-segments 867 * case, we simply report an error and drop the packet, 868 * since we can't sanely copy a jumbo packet to a single 869 * buffer. 870 */ 871 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 872 BUS_DMA_NOWAIT); 873 if (error) { 874 if (error == EFBIG) { 875 printf("%s: Tx packet consumes too many " 876 "DMA segments, dropping...\n", 877 device_xname(sc->sc_dev)); 878 IFQ_DEQUEUE(&ifp->if_snd, m0); 879 m_freem(m0); 880 continue; 881 } 882 /* 883 * Short on resources, just stop for now. 884 */ 885 break; 886 } 887 888 IFQ_DEQUEUE(&ifp->if_snd, m0); 889 890 /* 891 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 892 */ 893 894 /* Sync the DMA map. */ 895 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 896 BUS_DMASYNC_PREWRITE); 897 898 /* Initialize the fragment list. */ 899 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 900 tfd->tfd_frags[seg].frag_word0 = 901 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 902 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 903 totlen += dmamap->dm_segs[seg].ds_len; 904 } 905 906 #ifdef STGE_EVENT_COUNTERS 907 switch (dmamap->dm_nsegs) { 908 case 1: 909 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 910 break; 911 case 2: 912 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 913 break; 914 case 3: 915 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 916 break; 917 case 4: 918 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 919 break; 920 case 5: 921 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 922 break; 923 default: 924 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 925 break; 926 } 927 #endif /* STGE_EVENT_COUNTERS */ 928 929 /* 930 * Initialize checksumming flags in the descriptor. 931 * Byte-swap constants so the compiler can optimize. 932 */ 933 csum_flags = 0; 934 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 935 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 936 csum_flags |= TFD_IPChecksumEnable; 937 } 938 939 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 940 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 941 csum_flags |= TFD_TCPChecksumEnable; 942 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 943 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 944 csum_flags |= TFD_UDPChecksumEnable; 945 } 946 947 /* 948 * Initialize the descriptor and give it to the chip. 949 * Check to see if we have a VLAN tag to insert. 950 */ 951 952 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 953 TFD_FragCount(seg) | csum_flags | 954 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 955 TFD_TxDMAIndicate : 0); 956 if (have_vtag) { 957 #if 0 958 struct ether_header *eh = 959 mtod(m0, struct ether_header *); 960 uint16_t etype = ntohs(eh->ether_type); 961 printf("%s: xmit (tag %d) etype %x\n", 962 ifp->if_xname, *mtod(n, int *), etype); 963 #endif 964 tfc |= TFD_VLANTagInsert | 965 #ifdef STGE_VLAN_CFI 966 TFD_CFI | 967 #endif 968 TFD_VID(vtag); 969 } 970 tfd->tfd_control = htole64(tfc); 971 972 /* Sync the descriptor. */ 973 STGE_CDTXSYNC(sc, nexttx, 974 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 975 976 /* 977 * Kick the transmit DMA logic. 978 */ 979 CSR_WRITE_4(sc, STGE_DMACtrl, 980 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 981 982 /* 983 * Store a pointer to the packet so we can free it later. 984 */ 985 ds->ds_mbuf = m0; 986 987 /* Advance the tx pointer. */ 988 sc->sc_txpending++; 989 sc->sc_txlast = nexttx; 990 991 /* 992 * Pass the packet to any BPF listeners. 993 */ 994 bpf_mtap(ifp, m0, BPF_D_OUT); 995 } 996 997 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 998 /* No more slots left; notify upper layer. */ 999 ifp->if_flags |= IFF_OACTIVE; 1000 } 1001 1002 if (sc->sc_txpending != opending) { 1003 /* 1004 * We enqueued packets. If the transmitter was idle, 1005 * reset the txdirty pointer. 1006 */ 1007 if (opending == 0) 1008 sc->sc_txdirty = firsttx; 1009 1010 /* Set a watchdog timer in case the chip flakes out. */ 1011 ifp->if_timer = 5; 1012 } 1013 } 1014 1015 /* 1016 * stge_watchdog: [ifnet interface function] 1017 * 1018 * Watchdog timer handler. 1019 */ 1020 static void 1021 stge_watchdog(struct ifnet *ifp) 1022 { 1023 struct stge_softc *sc = ifp->if_softc; 1024 1025 /* 1026 * Sweep up first, since we don't interrupt every frame. 1027 */ 1028 stge_txintr(sc); 1029 if (sc->sc_txpending != 0) { 1030 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1031 ifp->if_oerrors++; 1032 1033 (void) stge_init(ifp); 1034 1035 /* Try to get more packets going. */ 1036 stge_start(ifp); 1037 } 1038 } 1039 1040 /* 1041 * stge_ioctl: [ifnet interface function] 1042 * 1043 * Handle control requests from the operator. 1044 */ 1045 static int 1046 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1047 { 1048 struct stge_softc *sc = ifp->if_softc; 1049 int s, error; 1050 1051 s = splnet(); 1052 1053 error = ether_ioctl(ifp, cmd, data); 1054 if (error == ENETRESET) { 1055 error = 0; 1056 1057 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1058 ; 1059 else if (ifp->if_flags & IFF_RUNNING) { 1060 /* 1061 * Multicast list has changed; set the hardware filter 1062 * accordingly. 1063 */ 1064 stge_set_filter(sc); 1065 } 1066 } 1067 1068 /* Try to get more packets going. */ 1069 stge_start(ifp); 1070 1071 splx(s); 1072 return (error); 1073 } 1074 1075 /* 1076 * stge_intr: 1077 * 1078 * Interrupt service routine. 1079 */ 1080 static int 1081 stge_intr(void *arg) 1082 { 1083 struct stge_softc *sc = arg; 1084 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1085 uint32_t txstat; 1086 int wantinit; 1087 uint16_t isr; 1088 1089 if ((CSR_READ_2(sc, STGE_IntStatus) & IS_InterruptStatus) == 0) 1090 return (0); 1091 1092 for (wantinit = 0; wantinit == 0;) { 1093 isr = CSR_READ_2(sc, STGE_IntStatusAck); 1094 if ((isr & sc->sc_IntEnable) == 0) 1095 break; 1096 1097 /* Host interface errors. */ 1098 if (isr & IS_HostError) { 1099 printf("%s: Host interface error\n", 1100 device_xname(sc->sc_dev)); 1101 wantinit = 1; 1102 continue; 1103 } 1104 1105 /* Receive interrupts. */ 1106 if (isr & (IS_RxDMAComplete | IS_RFDListEnd)) { 1107 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1108 stge_rxintr(sc); 1109 if (isr & IS_RFDListEnd) { 1110 printf("%s: receive ring overflow\n", 1111 device_xname(sc->sc_dev)); 1112 /* 1113 * XXX Should try to recover from this 1114 * XXX more gracefully. 1115 */ 1116 wantinit = 1; 1117 } 1118 } 1119 1120 /* Transmit interrupts. */ 1121 if (isr & (IS_TxDMAComplete | IS_TxComplete)) { 1122 #ifdef STGE_EVENT_COUNTERS 1123 if (isr & IS_TxDMAComplete) 1124 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1125 #endif 1126 stge_txintr(sc); 1127 } 1128 1129 /* Statistics overflow. */ 1130 if (isr & IS_UpdateStats) 1131 stge_stats_update(sc); 1132 1133 /* Transmission errors. */ 1134 if (isr & IS_TxComplete) { 1135 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1136 for (;;) { 1137 txstat = CSR_READ_4(sc, STGE_TxStatus); 1138 if ((txstat & TS_TxComplete) == 0) 1139 break; 1140 if (txstat & TS_TxUnderrun) { 1141 sc->sc_txthresh++; 1142 if (sc->sc_txthresh > 0x0fff) 1143 sc->sc_txthresh = 0x0fff; 1144 printf("%s: transmit underrun, new " 1145 "threshold: %d bytes\n", 1146 device_xname(sc->sc_dev), 1147 sc->sc_txthresh << 5); 1148 } 1149 if (txstat & TS_MaxCollisions) 1150 printf("%s: excessive collisions\n", 1151 device_xname(sc->sc_dev)); 1152 } 1153 wantinit = 1; 1154 } 1155 1156 } 1157 1158 if (wantinit) 1159 stge_init(ifp); 1160 1161 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1162 1163 /* Try to get more packets going. */ 1164 if_schedule_deferred_start(ifp); 1165 1166 return (1); 1167 } 1168 1169 /* 1170 * stge_txintr: 1171 * 1172 * Helper; handle transmit interrupts. 1173 */ 1174 static void 1175 stge_txintr(struct stge_softc *sc) 1176 { 1177 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1178 struct stge_descsoft *ds; 1179 uint64_t control; 1180 int i; 1181 1182 ifp->if_flags &= ~IFF_OACTIVE; 1183 1184 /* 1185 * Go through our Tx list and free mbufs for those 1186 * frames which have been transmitted. 1187 */ 1188 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1189 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1190 ds = &sc->sc_txsoft[i]; 1191 1192 STGE_CDTXSYNC(sc, i, 1193 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1194 1195 control = le64toh(sc->sc_txdescs[i].tfd_control); 1196 if ((control & TFD_TFDDone) == 0) 1197 break; 1198 1199 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1200 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1201 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1202 m_freem(ds->ds_mbuf); 1203 ds->ds_mbuf = NULL; 1204 } 1205 1206 /* Update the dirty transmit buffer pointer. */ 1207 sc->sc_txdirty = i; 1208 1209 /* 1210 * If there are no more pending transmissions, cancel the watchdog 1211 * timer. 1212 */ 1213 if (sc->sc_txpending == 0) 1214 ifp->if_timer = 0; 1215 } 1216 1217 /* 1218 * stge_rxintr: 1219 * 1220 * Helper; handle receive interrupts. 1221 */ 1222 static void 1223 stge_rxintr(struct stge_softc *sc) 1224 { 1225 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1226 struct stge_descsoft *ds; 1227 struct mbuf *m, *tailm; 1228 uint64_t status; 1229 int i, len; 1230 1231 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1232 ds = &sc->sc_rxsoft[i]; 1233 1234 STGE_CDRXSYNC(sc, i, 1235 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1236 1237 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1238 1239 if ((status & RFD_RFDDone) == 0) 1240 break; 1241 1242 if (__predict_false(sc->sc_rxdiscard)) { 1243 STGE_INIT_RXDESC(sc, i); 1244 if (status & RFD_FrameEnd) { 1245 /* Reset our state. */ 1246 sc->sc_rxdiscard = 0; 1247 } 1248 continue; 1249 } 1250 1251 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1252 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1253 1254 m = ds->ds_mbuf; 1255 1256 /* 1257 * Add a new receive buffer to the ring. 1258 */ 1259 if (stge_add_rxbuf(sc, i) != 0) { 1260 /* 1261 * Failed, throw away what we've done so 1262 * far, and discard the rest of the packet. 1263 */ 1264 ifp->if_ierrors++; 1265 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1266 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1267 STGE_INIT_RXDESC(sc, i); 1268 if ((status & RFD_FrameEnd) == 0) 1269 sc->sc_rxdiscard = 1; 1270 if (sc->sc_rxhead != NULL) 1271 m_freem(sc->sc_rxhead); 1272 STGE_RXCHAIN_RESET(sc); 1273 continue; 1274 } 1275 1276 #ifdef DIAGNOSTIC 1277 if (status & RFD_FrameStart) { 1278 KASSERT(sc->sc_rxhead == NULL); 1279 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1280 } 1281 #endif 1282 1283 STGE_RXCHAIN_LINK(sc, m); 1284 1285 /* 1286 * If this is not the end of the packet, keep 1287 * looking. 1288 */ 1289 if ((status & RFD_FrameEnd) == 0) { 1290 sc->sc_rxlen += m->m_len; 1291 continue; 1292 } 1293 1294 /* 1295 * Okay, we have the entire packet now... 1296 */ 1297 *sc->sc_rxtailp = NULL; 1298 m = sc->sc_rxhead; 1299 tailm = sc->sc_rxtail; 1300 1301 STGE_RXCHAIN_RESET(sc); 1302 1303 /* 1304 * If the packet had an error, drop it. Note we 1305 * count the error later in the periodic stats update. 1306 */ 1307 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1308 RFD_RxAlignmentError | RFD_RxFCSError | 1309 RFD_RxLengthError)) { 1310 m_freem(m); 1311 continue; 1312 } 1313 1314 /* 1315 * No errors. 1316 * 1317 * Note we have configured the chip to not include 1318 * the CRC at the end of the packet. 1319 */ 1320 len = RFD_RxDMAFrameLen(status); 1321 tailm->m_len = len - sc->sc_rxlen; 1322 1323 /* 1324 * If the packet is small enough to fit in a 1325 * single header mbuf, allocate one and copy 1326 * the data into it. This greatly reduces 1327 * memory consumption when we receive lots 1328 * of small packets. 1329 */ 1330 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1331 struct mbuf *nm; 1332 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1333 if (nm == NULL) { 1334 ifp->if_ierrors++; 1335 m_freem(m); 1336 continue; 1337 } 1338 nm->m_data += 2; 1339 nm->m_pkthdr.len = nm->m_len = len; 1340 m_copydata(m, 0, len, mtod(nm, void *)); 1341 m_freem(m); 1342 m = nm; 1343 } 1344 1345 /* 1346 * Set the incoming checksum information for the packet. 1347 */ 1348 if (status & RFD_IPDetected) { 1349 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1350 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1351 if (status & RFD_IPError) 1352 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1353 if (status & RFD_TCPDetected) { 1354 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1355 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1356 if (status & RFD_TCPError) 1357 m->m_pkthdr.csum_flags |= 1358 M_CSUM_TCP_UDP_BAD; 1359 } else if (status & RFD_UDPDetected) { 1360 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1361 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1362 if (status & RFD_UDPError) 1363 m->m_pkthdr.csum_flags |= 1364 M_CSUM_TCP_UDP_BAD; 1365 } 1366 } 1367 1368 m_set_rcvif(m, ifp); 1369 m->m_pkthdr.len = len; 1370 1371 /* 1372 * Pass this up to any BPF listeners, but only 1373 * pass if up the stack if it's for us. 1374 */ 1375 #ifdef STGE_VLAN_UNTAG 1376 /* 1377 * Check for VLAN tagged packets 1378 */ 1379 if (status & RFD_VLANDetected) 1380 vlan_set_tag(m, RFD_TCI(status)); 1381 1382 #endif 1383 #if 0 1384 if (status & RFD_VLANDetected) { 1385 struct ether_header *eh; 1386 uint16_t etype; 1387 1388 eh = mtod(m, struct ether_header *); 1389 etype = ntohs(eh->ether_type); 1390 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1391 ifp->if_xname, (uint16_t) RFD_TCI(status), 1392 etype); 1393 } 1394 #endif 1395 /* Pass it on. */ 1396 if_percpuq_enqueue(ifp->if_percpuq, m); 1397 } 1398 1399 /* Update the receive pointer. */ 1400 sc->sc_rxptr = i; 1401 } 1402 1403 /* 1404 * stge_tick: 1405 * 1406 * One second timer, used to tick the MII. 1407 */ 1408 static void 1409 stge_tick(void *arg) 1410 { 1411 struct stge_softc *sc = arg; 1412 int s; 1413 1414 s = splnet(); 1415 mii_tick(&sc->sc_mii); 1416 stge_stats_update(sc); 1417 splx(s); 1418 1419 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1420 } 1421 1422 /* 1423 * stge_stats_update: 1424 * 1425 * Read the TC9021 statistics counters. 1426 */ 1427 static void 1428 stge_stats_update(struct stge_softc *sc) 1429 { 1430 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1431 1432 (void) CSR_READ_4(sc, STGE_OctetRcvOk); 1433 1434 (void) CSR_READ_4(sc, STGE_FramesRcvdOk); 1435 1436 ifp->if_ierrors += 1437 (u_int) CSR_READ_2(sc, STGE_FramesLostRxErrors); 1438 1439 (void) CSR_READ_4(sc, STGE_OctetXmtdOk); 1440 1441 ifp->if_opackets += 1442 CSR_READ_4(sc, STGE_FramesXmtdOk); 1443 1444 ifp->if_collisions += 1445 CSR_READ_4(sc, STGE_LateCollisions) + 1446 CSR_READ_4(sc, STGE_MultiColFrames) + 1447 CSR_READ_4(sc, STGE_SingleColFrames); 1448 1449 ifp->if_oerrors += 1450 (u_int) CSR_READ_2(sc, STGE_FramesAbortXSColls) + 1451 (u_int) CSR_READ_2(sc, STGE_FramesWEXDeferal); 1452 } 1453 1454 /* 1455 * stge_reset: 1456 * 1457 * Perform a soft reset on the TC9021. 1458 */ 1459 static void 1460 stge_reset(struct stge_softc *sc) 1461 { 1462 uint32_t ac; 1463 int i; 1464 1465 ac = CSR_READ_4(sc, STGE_AsicCtrl); 1466 1467 /* 1468 * Only assert RstOut if we're fiber. We need GMII clocks 1469 * to be present in order for the reset to complete on fiber 1470 * cards. 1471 */ 1472 CSR_WRITE_4(sc, STGE_AsicCtrl, 1473 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1474 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1475 (sc->sc_usefiber ? AC_RstOut : 0)); 1476 1477 delay(50000); 1478 1479 for (i = 0; i < STGE_TIMEOUT; i++) { 1480 delay(5000); 1481 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1482 break; 1483 } 1484 1485 if (i == STGE_TIMEOUT) 1486 printf("%s: reset failed to complete\n", 1487 device_xname(sc->sc_dev)); 1488 1489 delay(1000); 1490 } 1491 1492 /* 1493 * stge_init: [ ifnet interface function ] 1494 * 1495 * Initialize the interface. Must be called at splnet(). 1496 */ 1497 static int 1498 stge_init(struct ifnet *ifp) 1499 { 1500 struct stge_softc *sc = ifp->if_softc; 1501 struct stge_descsoft *ds; 1502 int i, error = 0; 1503 1504 /* 1505 * Cancel any pending I/O. 1506 */ 1507 stge_stop(ifp, 0); 1508 1509 /* 1510 * Reset the chip to a known state. 1511 */ 1512 stge_reset(sc); 1513 1514 /* 1515 * Initialize the transmit descriptor ring. 1516 */ 1517 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1518 for (i = 0; i < STGE_NTXDESC; i++) { 1519 sc->sc_txdescs[i].tfd_next = htole64( 1520 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1521 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1522 } 1523 sc->sc_txpending = 0; 1524 sc->sc_txdirty = 0; 1525 sc->sc_txlast = STGE_NTXDESC - 1; 1526 1527 /* 1528 * Initialize the receive descriptor and receive job 1529 * descriptor rings. 1530 */ 1531 for (i = 0; i < STGE_NRXDESC; i++) { 1532 ds = &sc->sc_rxsoft[i]; 1533 if (ds->ds_mbuf == NULL) { 1534 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1535 printf("%s: unable to allocate or map rx " 1536 "buffer %d, error = %d\n", 1537 device_xname(sc->sc_dev), i, error); 1538 /* 1539 * XXX Should attempt to run with fewer receive 1540 * XXX buffers instead of just failing. 1541 */ 1542 stge_rxdrain(sc); 1543 goto out; 1544 } 1545 } else 1546 STGE_INIT_RXDESC(sc, i); 1547 } 1548 sc->sc_rxptr = 0; 1549 sc->sc_rxdiscard = 0; 1550 STGE_RXCHAIN_RESET(sc); 1551 1552 /* Set the station address. */ 1553 for (i = 0; i < 6; i++) 1554 CSR_WRITE_1(sc, STGE_StationAddress0 + i, 1555 CLLADDR(ifp->if_sadl)[i]); 1556 1557 /* 1558 * Set the statistics masks. Disable all the RMON stats, 1559 * and disable selected stats in the non-RMON stats registers. 1560 */ 1561 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); 1562 CSR_WRITE_4(sc, STGE_StatisticsMask, 1563 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1564 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1565 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1566 (1U << 21)); 1567 1568 /* Set up the receive filter. */ 1569 stge_set_filter(sc); 1570 1571 /* 1572 * Give the transmit and receive ring to the chip. 1573 */ 1574 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1575 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 1576 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1577 1578 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */ 1579 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 1580 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1581 1582 /* 1583 * Initialize the Tx auto-poll period. It's OK to make this number 1584 * large (255 is the max, but we use 127) -- we explicitly kick the 1585 * transmit engine when there's actually a packet. 1586 */ 1587 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 1588 1589 /* ..and the Rx auto-poll period. */ 1590 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 64); 1591 1592 /* Initialize the Tx start threshold. */ 1593 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); 1594 1595 /* RX DMA thresholds, from linux */ 1596 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); 1597 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); 1598 1599 /* Rx early threhold, from Linux */ 1600 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); 1601 1602 /* Tx DMA thresholds, from Linux */ 1603 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); 1604 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); 1605 1606 /* 1607 * Initialize the Rx DMA interrupt control register. We 1608 * request an interrupt after every incoming packet, but 1609 * defer it for 32us (64 * 512 ns). When the number of 1610 * interrupts pending reaches 8, we stop deferring the 1611 * interrupt, and signal it immediately. 1612 */ 1613 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl, 1614 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1615 1616 /* 1617 * Initialize the interrupt mask. 1618 */ 1619 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1620 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1621 CSR_WRITE_2(sc, STGE_IntStatus, 0xffff); 1622 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1623 1624 /* 1625 * Configure the DMA engine. 1626 * XXX Should auto-tune TxBurstLimit. 1627 */ 1628 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | 1629 DMAC_TxBurstLimit(3)); 1630 1631 /* 1632 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1633 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes 1634 * in the Rx FIFO. 1635 */ 1636 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16); 1637 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16); 1638 1639 /* 1640 * Set the maximum frame size. 1641 */ 1642 CSR_WRITE_2(sc, STGE_MaxFrameSize, 1643 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1644 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1645 ETHER_VLAN_ENCAP_LEN : 0)); 1646 1647 /* 1648 * Initialize MacCtrl -- do it before setting the media, 1649 * as setting the media will actually program the register. 1650 * 1651 * Note: We have to poke the IFS value before poking 1652 * anything else. 1653 */ 1654 sc->sc_MACCtrl = MC_IFSSelect(0); 1655 CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl); 1656 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1657 #ifdef STGE_VLAN_UNTAG 1658 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1659 #endif 1660 1661 if (sc->sc_rev >= 6) { /* >= B.2 */ 1662 /* Multi-frag frame bug work-around. */ 1663 CSR_WRITE_2(sc, STGE_DebugCtrl, 1664 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200); 1665 1666 /* Tx Poll Now bug work-around. */ 1667 CSR_WRITE_2(sc, STGE_DebugCtrl, 1668 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010); 1669 /* XXX ? from linux */ 1670 CSR_WRITE_2(sc, STGE_DebugCtrl, 1671 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020); 1672 } 1673 1674 /* 1675 * Set the current media. 1676 */ 1677 if ((error = ether_mediachange(ifp)) != 0) 1678 goto out; 1679 1680 /* 1681 * Start the one second MII clock. 1682 */ 1683 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1684 1685 /* 1686 * ...all done! 1687 */ 1688 ifp->if_flags |= IFF_RUNNING; 1689 ifp->if_flags &= ~IFF_OACTIVE; 1690 1691 out: 1692 if (error) 1693 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1694 return (error); 1695 } 1696 1697 /* 1698 * stge_drain: 1699 * 1700 * Drain the receive queue. 1701 */ 1702 static void 1703 stge_rxdrain(struct stge_softc *sc) 1704 { 1705 struct stge_descsoft *ds; 1706 int i; 1707 1708 for (i = 0; i < STGE_NRXDESC; i++) { 1709 ds = &sc->sc_rxsoft[i]; 1710 if (ds->ds_mbuf != NULL) { 1711 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1712 ds->ds_mbuf->m_next = NULL; 1713 m_freem(ds->ds_mbuf); 1714 ds->ds_mbuf = NULL; 1715 } 1716 } 1717 } 1718 1719 /* 1720 * stge_stop: [ ifnet interface function ] 1721 * 1722 * Stop transmission on the interface. 1723 */ 1724 static void 1725 stge_stop(struct ifnet *ifp, int disable) 1726 { 1727 struct stge_softc *sc = ifp->if_softc; 1728 struct stge_descsoft *ds; 1729 int i; 1730 1731 /* 1732 * Stop the one second clock. 1733 */ 1734 callout_stop(&sc->sc_tick_ch); 1735 1736 /* Down the MII. */ 1737 mii_down(&sc->sc_mii); 1738 1739 /* 1740 * Disable interrupts. 1741 */ 1742 CSR_WRITE_2(sc, STGE_IntEnable, 0); 1743 1744 /* 1745 * Stop receiver, transmitter, and stats update. 1746 */ 1747 CSR_WRITE_4(sc, STGE_MACCtrl, 1748 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1749 1750 /* 1751 * Stop the transmit and receive DMA. 1752 */ 1753 stge_dma_wait(sc); 1754 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); 1755 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0); 1756 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); 1757 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0); 1758 1759 /* 1760 * Release any queued transmit buffers. 1761 */ 1762 for (i = 0; i < STGE_NTXDESC; i++) { 1763 ds = &sc->sc_txsoft[i]; 1764 if (ds->ds_mbuf != NULL) { 1765 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1766 m_freem(ds->ds_mbuf); 1767 ds->ds_mbuf = NULL; 1768 } 1769 } 1770 1771 /* 1772 * Mark the interface down and cancel the watchdog timer. 1773 */ 1774 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1775 ifp->if_timer = 0; 1776 1777 if (disable) 1778 stge_rxdrain(sc); 1779 } 1780 1781 static int 1782 stge_eeprom_wait(struct stge_softc *sc) 1783 { 1784 int i; 1785 1786 for (i = 0; i < STGE_TIMEOUT; i++) { 1787 delay(1000); 1788 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0) 1789 return (0); 1790 } 1791 return (1); 1792 } 1793 1794 /* 1795 * stge_read_eeprom: 1796 * 1797 * Read data from the serial EEPROM. 1798 */ 1799 static void 1800 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1801 { 1802 1803 if (stge_eeprom_wait(sc)) 1804 printf("%s: EEPROM failed to come ready\n", 1805 device_xname(sc->sc_dev)); 1806 1807 CSR_WRITE_2(sc, STGE_EepromCtrl, 1808 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1809 if (stge_eeprom_wait(sc)) 1810 printf("%s: EEPROM read timed out\n", 1811 device_xname(sc->sc_dev)); 1812 *data = CSR_READ_2(sc, STGE_EepromData); 1813 } 1814 1815 /* 1816 * stge_add_rxbuf: 1817 * 1818 * Add a receive buffer to the indicated descriptor. 1819 */ 1820 static int 1821 stge_add_rxbuf(struct stge_softc *sc, int idx) 1822 { 1823 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1824 struct mbuf *m; 1825 int error; 1826 1827 MGETHDR(m, M_DONTWAIT, MT_DATA); 1828 if (m == NULL) 1829 return (ENOBUFS); 1830 1831 MCLGET(m, M_DONTWAIT); 1832 if ((m->m_flags & M_EXT) == 0) { 1833 m_freem(m); 1834 return (ENOBUFS); 1835 } 1836 1837 m->m_data = m->m_ext.ext_buf + 2; 1838 m->m_len = MCLBYTES - 2; 1839 1840 if (ds->ds_mbuf != NULL) 1841 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1842 1843 ds->ds_mbuf = m; 1844 1845 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1846 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1847 if (error) { 1848 printf("%s: can't load rx DMA map %d, error = %d\n", 1849 device_xname(sc->sc_dev), idx, error); 1850 panic("stge_add_rxbuf"); /* XXX */ 1851 } 1852 1853 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1854 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1855 1856 STGE_INIT_RXDESC(sc, idx); 1857 1858 return (0); 1859 } 1860 1861 /* 1862 * stge_set_filter: 1863 * 1864 * Set up the receive filter. 1865 */ 1866 static void 1867 stge_set_filter(struct stge_softc *sc) 1868 { 1869 struct ethercom *ec = &sc->sc_ethercom; 1870 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1871 struct ether_multi *enm; 1872 struct ether_multistep step; 1873 uint32_t crc; 1874 uint32_t mchash[2]; 1875 1876 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1877 if (ifp->if_flags & IFF_BROADCAST) 1878 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1879 1880 /* XXX: ST1023 only works in promiscuous mode */ 1881 if (sc->sc_stge1023) 1882 ifp->if_flags |= IFF_PROMISC; 1883 1884 if (ifp->if_flags & IFF_PROMISC) { 1885 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1886 goto allmulti; 1887 } 1888 1889 /* 1890 * Set up the multicast address filter by passing all multicast 1891 * addresses through a CRC generator, and then using the low-order 1892 * 6 bits as an index into the 64 bit multicast hash table. The 1893 * high order bits select the register, while the rest of the bits 1894 * select the bit within the register. 1895 */ 1896 1897 memset(mchash, 0, sizeof(mchash)); 1898 1899 ETHER_LOCK(ec); 1900 ETHER_FIRST_MULTI(step, ec, enm); 1901 if (enm == NULL) { 1902 ETHER_UNLOCK(ec); 1903 goto done; 1904 } 1905 1906 while (enm != NULL) { 1907 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1908 /* 1909 * We must listen to a range of multicast addresses. 1910 * For now, just accept all multicasts, rather than 1911 * trying to set only those filter bits needed to match 1912 * the range. (At this time, the only use of address 1913 * ranges is for IP multicast routing, for which the 1914 * range is big enough to require all bits set.) 1915 */ 1916 ETHER_UNLOCK(ec); 1917 goto allmulti; 1918 } 1919 1920 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1921 1922 /* Just want the 6 least significant bits. */ 1923 crc &= 0x3f; 1924 1925 /* Set the corresponding bit in the hash table. */ 1926 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1927 1928 ETHER_NEXT_MULTI(step, enm); 1929 } 1930 ETHER_UNLOCK(ec); 1931 1932 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1933 1934 ifp->if_flags &= ~IFF_ALLMULTI; 1935 goto done; 1936 1937 allmulti: 1938 ifp->if_flags |= IFF_ALLMULTI; 1939 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1940 1941 done: 1942 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1943 /* 1944 * Program the multicast hash table. 1945 */ 1946 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]); 1947 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]); 1948 } 1949 1950 CSR_WRITE_2(sc, STGE_ReceiveMode, sc->sc_ReceiveMode); 1951 } 1952 1953 /* 1954 * stge_mii_readreg: [mii interface function] 1955 * 1956 * Read a PHY register on the MII of the TC9021. 1957 */ 1958 static int 1959 stge_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1960 { 1961 1962 return mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg, val); 1963 } 1964 1965 /* 1966 * stge_mii_writereg: [mii interface function] 1967 * 1968 * Write a PHY register on the MII of the TC9021. 1969 */ 1970 static int 1971 stge_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1972 { 1973 1974 return mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, 1975 val); 1976 } 1977 1978 /* 1979 * stge_mii_statchg: [mii interface function] 1980 * 1981 * Callback from MII layer when media changes. 1982 */ 1983 static void 1984 stge_mii_statchg(struct ifnet *ifp) 1985 { 1986 struct stge_softc *sc = ifp->if_softc; 1987 1988 sc->sc_MACCtrl &= ~(MC_DuplexSelect | MC_RxFlowControlEnable | 1989 MC_TxFlowControlEnable); 1990 1991 if (sc->sc_mii.mii_media_active & IFM_FDX) 1992 sc->sc_MACCtrl |= MC_DuplexSelect; 1993 if ((sc->sc_mii.mii_media_active & IFM_ETH_RXPAUSE) != 0) 1994 sc->sc_MACCtrl |= MC_RxFlowControlEnable; 1995 if ((sc->sc_mii.mii_media_active & IFM_ETH_TXPAUSE) != 0) 1996 sc->sc_MACCtrl |= MC_TxFlowControlEnable; 1997 1998 CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl); 1999 } 2000 2001 /* 2002 * sste_mii_bitbang_read: [mii bit-bang interface function] 2003 * 2004 * Read the MII serial port for the MII bit-bang module. 2005 */ 2006 static uint32_t 2007 stge_mii_bitbang_read(device_t self) 2008 { 2009 struct stge_softc *sc = device_private(self); 2010 2011 return (CSR_READ_1(sc, STGE_PhyCtrl)); 2012 } 2013 2014 /* 2015 * stge_mii_bitbang_write: [mii big-bang interface function] 2016 * 2017 * Write the MII serial port for the MII bit-bang module. 2018 */ 2019 static void 2020 stge_mii_bitbang_write(device_t self, uint32_t val) 2021 { 2022 struct stge_softc *sc = device_private(self); 2023 2024 CSR_WRITE_1(sc, STGE_PhyCtrl, val | sc->sc_PhyCtrl); 2025 } 2026
Indexes created Tue Sep 30 20:09:53 GMT 2025