if_stge.c revision 1.87
1 /* $NetBSD: if_stge.c,v 1.87 2020/07/02 09:02:04 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. TC9021 10/100/1000 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.87 2020/07/02 09:02:04 msaitoh Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 #include <sys/queue.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <net/bpf.h> 59 60 #include <sys/bus.h> 61 #include <sys/intr.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 #include <dev/mii/mii_bitbang.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_stgereg.h> 72 73 #include <prop/proplib.h> 74 75 /* #define STGE_CU_BUG 1 */ 76 #define STGE_VLAN_UNTAG 1 77 /* #define STGE_VLAN_CFI 1 */ 78 79 /* 80 * Transmit descriptor list size. 81 */ 82 #define STGE_NTXDESC 256 83 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 84 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 85 86 /* 87 * Receive descriptor list size. 88 */ 89 #define STGE_NRXDESC 256 90 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 91 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 92 93 /* 94 * Only interrupt every N frames. Must be a power-of-two. 95 */ 96 #define STGE_TXINTR_SPACING 16 97 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 98 99 /* 100 * Control structures are DMA'd to the TC9021 chip. We allocate them in 101 * a single clump that maps to a single DMA segment to make several things 102 * easier. 103 */ 104 struct stge_control_data { 105 /* 106 * The transmit descriptors. 107 */ 108 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 109 110 /* 111 * The receive descriptors. 112 */ 113 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 114 }; 115 116 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 117 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 118 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 119 120 /* 121 * Software state for transmit and receive jobs. 122 */ 123 struct stge_descsoft { 124 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 125 bus_dmamap_t ds_dmamap; /* our DMA map */ 126 }; 127 128 /* 129 * Software state per device. 130 */ 131 struct stge_softc { 132 device_t sc_dev; /* generic device information */ 133 bus_space_tag_t sc_st; /* bus space tag */ 134 bus_space_handle_t sc_sh; /* bus space handle */ 135 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 136 struct ethercom sc_ethercom; /* ethernet common data */ 137 int sc_rev; /* silicon revision */ 138 139 void *sc_ih; /* interrupt cookie */ 140 141 struct mii_data sc_mii; /* MII/media information */ 142 143 callout_t sc_tick_ch; /* tick callout */ 144 145 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 147 148 /* 149 * Software state for transmit and receive descriptors. 150 */ 151 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 152 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 153 154 /* 155 * Control data structures. 156 */ 157 struct stge_control_data *sc_control_data; 158 #define sc_txdescs sc_control_data->scd_txdescs 159 #define sc_rxdescs sc_control_data->scd_rxdescs 160 161 #ifdef STGE_EVENT_COUNTERS 162 /* 163 * Event counters. 164 */ 165 struct evcnt sc_ev_txstall; /* Tx stalled */ 166 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 167 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 168 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 169 170 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 171 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 172 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 173 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 174 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 175 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 176 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 177 178 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 179 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 180 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 181 182 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 183 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 184 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 185 #endif /* STGE_EVENT_COUNTERS */ 186 187 int sc_txpending; /* number of Tx requests pending */ 188 int sc_txdirty; /* first dirty Tx descriptor */ 189 int sc_txlast; /* last used Tx descriptor */ 190 191 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 192 int sc_rxdiscard; 193 int sc_rxlen; 194 struct mbuf *sc_rxhead; 195 struct mbuf *sc_rxtail; 196 struct mbuf **sc_rxtailp; 197 198 int sc_txthresh; /* Tx threshold */ 199 uint32_t sc_usefiber:1; /* if we're fiber */ 200 uint32_t sc_stge1023:1; /* are we a 1023 */ 201 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 202 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 203 uint16_t sc_IntEnable; /* prototype IntEnable register */ 204 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 205 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 206 }; 207 208 #define STGE_RXCHAIN_RESET(sc) \ 209 do { \ 210 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 211 *(sc)->sc_rxtailp = NULL; \ 212 (sc)->sc_rxlen = 0; \ 213 } while (/*CONSTCOND*/0) 214 215 #define STGE_RXCHAIN_LINK(sc, m) \ 216 do { \ 217 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 218 (sc)->sc_rxtailp = &(m)->m_next; \ 219 } while (/*CONSTCOND*/0) 220 221 /* 222 * Register access macros 223 */ 224 #define CSR_WRITE_4(_sc, reg, val) \ 225 bus_space_write_4((_sc)->sc_st, (_sc)->sc_sh, (reg), (val)) 226 #define CSR_WRITE_2(_sc, reg, val) \ 227 bus_space_write_2((_sc)->sc_st, (_sc)->sc_sh, (reg), (val)) 228 #define CSR_WRITE_1(_sc, reg, val) \ 229 bus_space_write_1((_sc)->sc_st, (_sc)->sc_sh, (reg), (val)) 230 231 #define CSR_READ_4(_sc, reg) \ 232 bus_space_read_4((_sc)->sc_st, (_sc)->sc_sh, (reg)) 233 #define CSR_READ_2(_sc, reg) \ 234 bus_space_read_2((_sc)->sc_st, (_sc)->sc_sh, (reg)) 235 #define CSR_READ_1(_sc, reg) \ 236 bus_space_read_1((_sc)->sc_st, (_sc)->sc_sh, (reg)) 237 238 #define STGE_TIMEOUT 1000 239 240 #ifdef STGE_EVENT_COUNTERS 241 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 242 #else 243 #define STGE_EVCNT_INCR(ev) /* nothing */ 244 #endif 245 246 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 247 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 248 249 #define STGE_CDTXSYNC(sc, x, ops) \ 250 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 251 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 252 253 #define STGE_CDRXSYNC(sc, x, ops) \ 254 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 255 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 256 257 #define STGE_INIT_RXDESC(sc, x) \ 258 do { \ 259 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 260 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 261 \ 262 /* \ 263 * Note: We scoot the packet forward 2 bytes in the buffer \ 264 * so that the payload after the Ethernet header is aligned \ 265 * to a 4-byte boundary. \ 266 */ \ 267 __rfd->rfd_frag.frag_word0 = \ 268 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 269 FRAG_LEN(MCLBYTES - 2)); \ 270 __rfd->rfd_next = \ 271 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 272 __rfd->rfd_status = 0; \ 273 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \ 274 } while (/*CONSTCOND*/0) 275 276 static void stge_start(struct ifnet *); 277 static void stge_watchdog(struct ifnet *); 278 static int stge_ioctl(struct ifnet *, u_long, void *); 279 static int stge_init(struct ifnet *); 280 static void stge_stop(struct ifnet *, int); 281 282 static bool stge_shutdown(device_t, int); 283 284 static void stge_reset(struct stge_softc *); 285 static void stge_rxdrain(struct stge_softc *); 286 static int stge_add_rxbuf(struct stge_softc *, int); 287 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 288 static void stge_tick(void *); 289 290 static void stge_stats_update(struct stge_softc *); 291 292 static void stge_set_filter(struct stge_softc *); 293 294 static int stge_intr(void *); 295 static void stge_txintr(struct stge_softc *); 296 static void stge_rxintr(struct stge_softc *); 297 298 static int stge_mii_readreg(device_t, int, int, uint16_t *); 299 static int stge_mii_writereg(device_t, int, int, uint16_t); 300 static void stge_mii_statchg(struct ifnet *); 301 302 static int stge_match(device_t, cfdata_t, void *); 303 static void stge_attach(device_t, device_t, void *); 304 305 int stge_copy_small = 0; 306 307 CFATTACH_DECL_NEW(stge, sizeof(struct stge_softc), 308 stge_match, stge_attach, NULL, NULL); 309 310 static uint32_t stge_mii_bitbang_read(device_t); 311 static void stge_mii_bitbang_write(device_t, uint32_t); 312 313 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 314 stge_mii_bitbang_read, 315 stge_mii_bitbang_write, 316 { 317 PC_MgmtData, /* MII_BIT_MDO */ 318 PC_MgmtData, /* MII_BIT_MDI */ 319 PC_MgmtClk, /* MII_BIT_MDC */ 320 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 321 0, /* MII_BIT_DIR_PHY_HOST */ 322 } 323 }; 324 325 /* 326 * Devices supported by this driver. 327 */ 328 static const struct stge_product { 329 pci_vendor_id_t stge_vendor; 330 pci_product_id_t stge_product; 331 const char *stge_name; 332 } stge_products[] = { 333 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023, 334 "Sundance ST-1023 Gigabit Ethernet" }, 335 336 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 337 "Sundance ST-2021 Gigabit Ethernet" }, 338 339 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 340 "Tamarack TC9021 Gigabit Ethernet" }, 341 342 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 343 "Tamarack TC9021 Gigabit Ethernet" }, 344 345 /* 346 * The Sundance sample boards use the Sundance vendor ID, 347 * but the Tamarack product ID. 348 */ 349 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 350 "Sundance TC9021 Gigabit Ethernet" }, 351 352 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 353 "Sundance TC9021 Gigabit Ethernet" }, 354 355 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 356 "D-Link DL-4000 Gigabit Ethernet" }, 357 358 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 359 "Antares Gigabit Ethernet" }, 360 361 { 0, 0, 362 NULL }, 363 }; 364 365 static const struct stge_product * 366 stge_lookup(const struct pci_attach_args *pa) 367 { 368 const struct stge_product *sp; 369 370 for (sp = stge_products; sp->stge_name != NULL; sp++) { 371 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 372 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 373 return (sp); 374 } 375 return (NULL); 376 } 377 378 static int 379 stge_match(device_t parent, cfdata_t cf, void *aux) 380 { 381 struct pci_attach_args *pa = aux; 382 383 if (stge_lookup(pa) != NULL) 384 return (1); 385 386 return (0); 387 } 388 389 static void 390 stge_attach(device_t parent, device_t self, void *aux) 391 { 392 struct stge_softc *sc = device_private(self); 393 struct pci_attach_args *pa = aux; 394 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 395 struct mii_data * const mii = &sc->sc_mii; 396 pci_chipset_tag_t pc = pa->pa_pc; 397 pci_intr_handle_t ih; 398 const char *intrstr = NULL; 399 bus_space_tag_t iot, memt; 400 bus_space_handle_t ioh, memh; 401 bus_dma_segment_t seg; 402 prop_dictionary_t dict; 403 prop_data_t data; 404 int ioh_valid, memh_valid; 405 int i, rseg, error; 406 const struct stge_product *sp; 407 uint8_t enaddr[ETHER_ADDR_LEN]; 408 char intrbuf[PCI_INTRSTR_LEN]; 409 410 sc->sc_dev = self; 411 callout_init(&sc->sc_tick_ch, 0); 412 callout_setfunc(&sc->sc_tick_ch, stge_tick, sc); 413 414 sp = stge_lookup(pa); 415 if (sp == NULL) { 416 printf("\n"); 417 panic("ste_attach: impossible"); 418 } 419 420 sc->sc_rev = PCI_REVISION(pa->pa_class); 421 422 pci_aprint_devinfo_fancy(pa, NULL, sp->stge_name, 1); 423 424 /* 425 * Map the device. 426 */ 427 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 428 PCI_MAPREG_TYPE_IO, 0, 429 &iot, &ioh, NULL, NULL) == 0); 430 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 431 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 432 &memt, &memh, NULL, NULL) == 0); 433 434 if (memh_valid) { 435 sc->sc_st = memt; 436 sc->sc_sh = memh; 437 } else if (ioh_valid) { 438 sc->sc_st = iot; 439 sc->sc_sh = ioh; 440 } else { 441 aprint_error_dev(self, "unable to map device registers\n"); 442 return; 443 } 444 445 /* 446 * We have a 40-bit limit on our DMA addresses. This isn't an 447 * issue if we're only using a 32-bit DMA tag, but we have to 448 * account for it if the 64-bit DMA tag is available. 449 */ 450 if (pci_dma64_available(pa)) { 451 if (bus_dmatag_subregion(pa->pa_dmat64, 452 0, 453 (bus_addr_t)(FRAG_ADDR_MASK + 1ULL), 454 &sc->sc_dmat, 455 BUS_DMA_WAITOK) != 0) { 456 aprint_error_dev(self, 457 "WARNING: failed to restrict dma range," 458 " falling back to parent bus dma range\n"); 459 sc->sc_dmat = pa->pa_dmat64; 460 } 461 } else { 462 sc->sc_dmat = pa->pa_dmat; 463 } 464 465 /* Enable bus mastering. */ 466 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 467 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 468 PCI_COMMAND_MASTER_ENABLE); 469 470 /* power up chip */ 471 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 472 error != EOPNOTSUPP) { 473 aprint_error_dev(self, "cannot activate %d\n", error); 474 return; 475 } 476 /* 477 * Map and establish our interrupt. 478 */ 479 if (pci_intr_map(pa, &ih)) { 480 aprint_error_dev(self, "unable to map interrupt\n"); 481 return; 482 } 483 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 484 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, stge_intr, sc, 485 device_xname(self)); 486 if (sc->sc_ih == NULL) { 487 aprint_error_dev(self, "unable to establish interrupt"); 488 if (intrstr != NULL) 489 aprint_error(" at %s", intrstr); 490 aprint_error("\n"); 491 return; 492 } 493 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 494 495 /* 496 * Allocate the control data structures, and create and load the 497 * DMA map for it. 498 */ 499 if ((error = bus_dmamem_alloc(sc->sc_dmat, 500 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 501 0)) != 0) { 502 aprint_error_dev(self, 503 "unable to allocate control data, error = %d\n", error); 504 goto fail_0; 505 } 506 507 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 508 sizeof(struct stge_control_data), (void **)&sc->sc_control_data, 509 BUS_DMA_COHERENT)) != 0) { 510 aprint_error_dev(self, 511 "unable to map control data, error = %d\n", error); 512 goto fail_1; 513 } 514 515 if ((error = bus_dmamap_create(sc->sc_dmat, 516 sizeof(struct stge_control_data), 1, 517 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 518 aprint_error_dev(self, 519 "unable to create control data DMA map, error = %d\n", 520 error); 521 goto fail_2; 522 } 523 524 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 525 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 526 0)) != 0) { 527 aprint_error_dev(self, 528 "unable to load control data DMA map, error = %d\n", 529 error); 530 goto fail_3; 531 } 532 533 /* 534 * Create the transmit buffer DMA maps. Note that rev B.3 535 * and earlier seem to have a bug regarding multi-fragment 536 * packets. We need to limit the number of Tx segments on 537 * such chips to 1. 538 */ 539 for (i = 0; i < STGE_NTXDESC; i++) { 540 if ((error = bus_dmamap_create(sc->sc_dmat, 541 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 542 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 543 aprint_error_dev(self, 544 "unable to create tx DMA map %d, error = %d\n", 545 i, error); 546 goto fail_4; 547 } 548 } 549 550 /* 551 * Create the receive buffer DMA maps. 552 */ 553 for (i = 0; i < STGE_NRXDESC; i++) { 554 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 555 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 556 aprint_error_dev(self, 557 "unable to create rx DMA map %d, error = %d\n", 558 i, error); 559 goto fail_5; 560 } 561 sc->sc_rxsoft[i].ds_mbuf = NULL; 562 } 563 564 /* 565 * Determine if we're copper or fiber. It affects how we 566 * reset the card. 567 */ 568 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) 569 sc->sc_usefiber = 1; 570 else 571 sc->sc_usefiber = 0; 572 573 /* 574 * Reset the chip to a known state. 575 */ 576 stge_reset(sc); 577 578 /* 579 * Reading the station address from the EEPROM doesn't seem 580 * to work, at least on my sample boards. Instead, since 581 * the reset sequence does AutoInit, read it from the station 582 * address registers. For Sundance 1023 you can only read it 583 * from EEPROM. 584 */ 585 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) { 586 enaddr[0] = CSR_READ_2(sc, STGE_StationAddress0) & 0xff; 587 enaddr[1] = CSR_READ_2(sc, STGE_StationAddress0) >> 8; 588 enaddr[2] = CSR_READ_2(sc, STGE_StationAddress1) & 0xff; 589 enaddr[3] = CSR_READ_2(sc, STGE_StationAddress1) >> 8; 590 enaddr[4] = CSR_READ_2(sc, STGE_StationAddress2) & 0xff; 591 enaddr[5] = CSR_READ_2(sc, STGE_StationAddress2) >> 8; 592 sc->sc_stge1023 = 0; 593 } else { 594 data = prop_dictionary_get(device_properties(self), 595 "mac-address"); 596 if (data != NULL) { 597 /* 598 * Try to get the station address from device 599 * properties first, in case the EEPROM is missing. 600 */ 601 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 602 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 603 (void)memcpy(enaddr, prop_data_value(data), 604 ETHER_ADDR_LEN); 605 } else { 606 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 607 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 608 stge_read_eeprom(sc, 609 STGE_EEPROM_StationAddress0 + i, 610 &myaddr[i]); 611 myaddr[i] = le16toh(myaddr[i]); 612 } 613 (void)memcpy(enaddr, myaddr, sizeof(enaddr)); 614 } 615 sc->sc_stge1023 = 1; 616 } 617 618 /* Set need_loaddspcode before mii_attach() */ 619 dict = device_properties(self); 620 prop_dictionary_set_bool(dict, "need_loaddspcode", 621 ((sc->sc_rev >= 0x40) && (sc->sc_rev <= 0x4e)) ? true : false); 622 623 aprint_normal_dev(self, "Ethernet address %s\n", 624 ether_sprintf(enaddr)); 625 626 /* 627 * Read some important bits from the PhyCtrl register. 628 */ 629 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & 630 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 631 632 /* 633 * Initialize our media structures and probe the MII. 634 */ 635 mii->mii_ifp = ifp; 636 mii->mii_readreg = stge_mii_readreg; 637 mii->mii_writereg = stge_mii_writereg; 638 mii->mii_statchg = stge_mii_statchg; 639 sc->sc_ethercom.ec_mii = mii; 640 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 641 ether_mediastatus); 642 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 643 MII_OFFSET_ANY, MIIF_DOPAUSE); 644 if (LIST_FIRST(&mii->mii_phys) == NULL) { 645 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 646 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 647 } else 648 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 649 650 ifp = &sc->sc_ethercom.ec_if; 651 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 652 ifp->if_softc = sc; 653 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 654 ifp->if_ioctl = stge_ioctl; 655 ifp->if_start = stge_start; 656 ifp->if_watchdog = stge_watchdog; 657 ifp->if_init = stge_init; 658 ifp->if_stop = stge_stop; 659 IFQ_SET_READY(&ifp->if_snd); 660 661 /* 662 * The manual recommends disabling early transmit, so we 663 * do. It's disabled anyway, if using IP checksumming, 664 * since the entire packet must be in the FIFO in order 665 * for the chip to perform the checksum. 666 */ 667 sc->sc_txthresh = 0x0fff; 668 669 /* 670 * Disable MWI if the PCI layer tells us to. 671 */ 672 sc->sc_DMACtrl = 0; 673 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 674 sc->sc_DMACtrl |= DMAC_MWIDisable; 675 676 /* 677 * We can support 802.1Q VLAN-sized frames and jumbo 678 * Ethernet frames. 679 * 680 * XXX Figure out how to do hw-assisted VLAN tagging in 681 * XXX a reasonable way on this chip. 682 */ 683 sc->sc_ethercom.ec_capabilities |= 684 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 685 ETHERCAP_VLAN_HWTAGGING; 686 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 687 688 /* 689 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 690 */ 691 sc->sc_ethercom.ec_if.if_capabilities |= 692 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 693 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 694 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 695 696 /* 697 * Attach the interface. 698 */ 699 if_attach(ifp); 700 if_deferred_start_init(ifp, NULL); 701 ether_ifattach(ifp, enaddr); 702 703 #ifdef STGE_EVENT_COUNTERS 704 /* 705 * Attach event counters. 706 */ 707 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 708 NULL, device_xname(self), "txstall"); 709 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 710 NULL, device_xname(self), "txdmaintr"); 711 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 712 NULL, device_xname(self), "txindintr"); 713 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 714 NULL, device_xname(self), "rxintr"); 715 716 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 717 NULL, device_xname(self), "txseg1"); 718 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 719 NULL, device_xname(self), "txseg2"); 720 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 721 NULL, device_xname(self), "txseg3"); 722 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 723 NULL, device_xname(self), "txseg4"); 724 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 725 NULL, device_xname(self), "txseg5"); 726 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 727 NULL, device_xname(self), "txsegmore"); 728 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 729 NULL, device_xname(self), "txcopy"); 730 731 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 732 NULL, device_xname(self), "rxipsum"); 733 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 734 NULL, device_xname(self), "rxtcpsum"); 735 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 736 NULL, device_xname(self), "rxudpsum"); 737 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 738 NULL, device_xname(self), "txipsum"); 739 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 740 NULL, device_xname(self), "txtcpsum"); 741 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 742 NULL, device_xname(self), "txudpsum"); 743 #endif /* STGE_EVENT_COUNTERS */ 744 745 /* 746 * Make sure the interface is shutdown during reboot. 747 */ 748 if (pmf_device_register1(self, NULL, NULL, stge_shutdown)) 749 pmf_class_network_register(self, ifp); 750 else 751 aprint_error_dev(self, "couldn't establish power handler\n"); 752 753 return; 754 755 /* 756 * Free any resources we've allocated during the failed attach 757 * attempt. Do this in reverse order and fall through. 758 */ 759 fail_5: 760 for (i = 0; i < STGE_NRXDESC; i++) { 761 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 762 bus_dmamap_destroy(sc->sc_dmat, 763 sc->sc_rxsoft[i].ds_dmamap); 764 } 765 fail_4: 766 for (i = 0; i < STGE_NTXDESC; i++) { 767 if (sc->sc_txsoft[i].ds_dmamap != NULL) 768 bus_dmamap_destroy(sc->sc_dmat, 769 sc->sc_txsoft[i].ds_dmamap); 770 } 771 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 772 fail_3: 773 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 774 fail_2: 775 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 776 sizeof(struct stge_control_data)); 777 fail_1: 778 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 779 fail_0: 780 return; 781 } 782 783 /* 784 * stge_shutdown: 785 * 786 * Make sure the interface is stopped at reboot time. 787 */ 788 static bool 789 stge_shutdown(device_t self, int howto) 790 { 791 struct stge_softc *sc = device_private(self); 792 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 793 794 stge_stop(ifp, 1); 795 stge_reset(sc); 796 return true; 797 } 798 799 static void 800 stge_dma_wait(struct stge_softc *sc) 801 { 802 int i; 803 804 for (i = 0; i < STGE_TIMEOUT; i++) { 805 delay(2); 806 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) 807 break; 808 } 809 810 if (i == STGE_TIMEOUT) 811 printf("%s: DMA wait timed out\n", device_xname(sc->sc_dev)); 812 } 813 814 /* 815 * stge_start: [ifnet interface function] 816 * 817 * Start packet transmission on the interface. 818 */ 819 static void 820 stge_start(struct ifnet *ifp) 821 { 822 struct stge_softc *sc = ifp->if_softc; 823 struct mbuf *m0; 824 struct stge_descsoft *ds; 825 struct stge_tfd *tfd; 826 bus_dmamap_t dmamap; 827 int error, firsttx, nexttx, opending, seg, totlen; 828 uint64_t csum_flags; 829 830 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING) 831 return; 832 833 /* 834 * Remember the previous number of pending transmissions 835 * and the first descriptor we will use. 836 */ 837 opending = sc->sc_txpending; 838 firsttx = STGE_NEXTTX(sc->sc_txlast); 839 840 /* 841 * Loop through the send queue, setting up transmit descriptors 842 * until we drain the queue, or use up all available transmit 843 * descriptors. 844 */ 845 for (;;) { 846 uint64_t tfc; 847 bool have_vtag; 848 uint16_t vtag; 849 850 /* 851 * Grab a packet off the queue. 852 */ 853 IFQ_POLL(&ifp->if_snd, m0); 854 if (m0 == NULL) 855 break; 856 857 /* 858 * Leave one unused descriptor at the end of the 859 * list to prevent wrapping completely around. 860 */ 861 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 862 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 863 break; 864 } 865 866 /* 867 * See if we have any VLAN stuff. 868 */ 869 have_vtag = vlan_has_tag(m0); 870 if (have_vtag) 871 vtag = vlan_get_tag(m0); 872 873 /* 874 * Get the last and next available transmit descriptor. 875 */ 876 nexttx = STGE_NEXTTX(sc->sc_txlast); 877 tfd = &sc->sc_txdescs[nexttx]; 878 ds = &sc->sc_txsoft[nexttx]; 879 880 dmamap = ds->ds_dmamap; 881 882 /* 883 * Load the DMA map. If this fails, the packet either 884 * didn't fit in the alloted number of segments, or we 885 * were short on resources. For the too-many-segments 886 * case, we simply report an error and drop the packet, 887 * since we can't sanely copy a jumbo packet to a single 888 * buffer. 889 */ 890 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 891 BUS_DMA_NOWAIT); 892 if (error) { 893 if (error == EFBIG) { 894 printf("%s: Tx packet consumes too many " 895 "DMA segments, dropping...\n", 896 device_xname(sc->sc_dev)); 897 IFQ_DEQUEUE(&ifp->if_snd, m0); 898 m_freem(m0); 899 continue; 900 } 901 /* 902 * Short on resources, just stop for now. 903 */ 904 break; 905 } 906 907 IFQ_DEQUEUE(&ifp->if_snd, m0); 908 909 /* 910 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 911 */ 912 913 /* Sync the DMA map. */ 914 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 915 BUS_DMASYNC_PREWRITE); 916 917 /* Initialize the fragment list. */ 918 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 919 tfd->tfd_frags[seg].frag_word0 = 920 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 921 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 922 totlen += dmamap->dm_segs[seg].ds_len; 923 } 924 925 #ifdef STGE_EVENT_COUNTERS 926 switch (dmamap->dm_nsegs) { 927 case 1: 928 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 929 break; 930 case 2: 931 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 932 break; 933 case 3: 934 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 935 break; 936 case 4: 937 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 938 break; 939 case 5: 940 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 941 break; 942 default: 943 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 944 break; 945 } 946 #endif /* STGE_EVENT_COUNTERS */ 947 948 /* 949 * Initialize checksumming flags in the descriptor. 950 * Byte-swap constants so the compiler can optimize. 951 */ 952 csum_flags = 0; 953 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 954 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 955 csum_flags |= TFD_IPChecksumEnable; 956 } 957 958 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 959 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 960 csum_flags |= TFD_TCPChecksumEnable; 961 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 962 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 963 csum_flags |= TFD_UDPChecksumEnable; 964 } 965 966 /* 967 * Initialize the descriptor and give it to the chip. 968 * Check to see if we have a VLAN tag to insert. 969 */ 970 971 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 972 TFD_FragCount(seg) | csum_flags | 973 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 974 TFD_TxDMAIndicate : 0); 975 if (have_vtag) { 976 #if 0 977 struct ether_header *eh = 978 mtod(m0, struct ether_header *); 979 uint16_t etype = ntohs(eh->ether_type); 980 printf("%s: xmit (tag %d) etype %x\n", 981 ifp->if_xname, *mtod(n, int *), etype); 982 #endif 983 tfc |= TFD_VLANTagInsert | 984 #ifdef STGE_VLAN_CFI 985 TFD_CFI | 986 #endif 987 TFD_VID(vtag); 988 } 989 tfd->tfd_control = htole64(tfc); 990 991 /* Sync the descriptor. */ 992 STGE_CDTXSYNC(sc, nexttx, 993 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 994 995 /* 996 * Kick the transmit DMA logic. 997 */ 998 CSR_WRITE_4(sc, STGE_DMACtrl, 999 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 1000 1001 /* 1002 * Store a pointer to the packet so we can free it later. 1003 */ 1004 ds->ds_mbuf = m0; 1005 1006 /* Advance the tx pointer. */ 1007 sc->sc_txpending++; 1008 sc->sc_txlast = nexttx; 1009 1010 /* 1011 * Pass the packet to any BPF listeners. 1012 */ 1013 bpf_mtap(ifp, m0, BPF_D_OUT); 1014 } 1015 1016 if (sc->sc_txpending != opending) { 1017 /* 1018 * We enqueued packets. If the transmitter was idle, 1019 * reset the txdirty pointer. 1020 */ 1021 if (opending == 0) 1022 sc->sc_txdirty = firsttx; 1023 1024 /* Set a watchdog timer in case the chip flakes out. */ 1025 ifp->if_timer = 5; 1026 } 1027 } 1028 1029 /* 1030 * stge_watchdog: [ifnet interface function] 1031 * 1032 * Watchdog timer handler. 1033 */ 1034 static void 1035 stge_watchdog(struct ifnet *ifp) 1036 { 1037 struct stge_softc *sc = ifp->if_softc; 1038 1039 /* 1040 * Sweep up first, since we don't interrupt every frame. 1041 */ 1042 stge_txintr(sc); 1043 if (sc->sc_txpending != 0) { 1044 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1045 if_statinc(ifp, if_oerrors); 1046 1047 (void) stge_init(ifp); 1048 1049 /* Try to get more packets going. */ 1050 stge_start(ifp); 1051 } 1052 } 1053 1054 /* 1055 * stge_ioctl: [ifnet interface function] 1056 * 1057 * Handle control requests from the operator. 1058 */ 1059 static int 1060 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1061 { 1062 struct stge_softc *sc = ifp->if_softc; 1063 int s, error; 1064 1065 s = splnet(); 1066 1067 error = ether_ioctl(ifp, cmd, data); 1068 if (error == ENETRESET) { 1069 error = 0; 1070 1071 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1072 ; 1073 else if (ifp->if_flags & IFF_RUNNING) { 1074 /* 1075 * Multicast list has changed; set the hardware filter 1076 * accordingly. 1077 */ 1078 stge_set_filter(sc); 1079 } 1080 } 1081 1082 /* Try to get more packets going. */ 1083 stge_start(ifp); 1084 1085 splx(s); 1086 return (error); 1087 } 1088 1089 /* 1090 * stge_intr: 1091 * 1092 * Interrupt service routine. 1093 */ 1094 static int 1095 stge_intr(void *arg) 1096 { 1097 struct stge_softc *sc = arg; 1098 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1099 uint32_t txstat; 1100 int wantinit; 1101 uint16_t isr; 1102 1103 if ((CSR_READ_2(sc, STGE_IntStatus) & IS_InterruptStatus) == 0) 1104 return (0); 1105 1106 for (wantinit = 0; wantinit == 0;) { 1107 isr = CSR_READ_2(sc, STGE_IntStatusAck); 1108 if ((isr & sc->sc_IntEnable) == 0) 1109 break; 1110 1111 /* Host interface errors. */ 1112 if (isr & IS_HostError) { 1113 printf("%s: Host interface error\n", 1114 device_xname(sc->sc_dev)); 1115 wantinit = 1; 1116 continue; 1117 } 1118 1119 /* Receive interrupts. */ 1120 if (isr & (IS_RxDMAComplete | IS_RFDListEnd)) { 1121 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1122 stge_rxintr(sc); 1123 if (isr & IS_RFDListEnd) { 1124 printf("%s: receive ring overflow\n", 1125 device_xname(sc->sc_dev)); 1126 /* 1127 * XXX Should try to recover from this 1128 * XXX more gracefully. 1129 */ 1130 wantinit = 1; 1131 } 1132 } 1133 1134 /* Transmit interrupts. */ 1135 if (isr & (IS_TxDMAComplete | IS_TxComplete)) { 1136 #ifdef STGE_EVENT_COUNTERS 1137 if (isr & IS_TxDMAComplete) 1138 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1139 #endif 1140 stge_txintr(sc); 1141 } 1142 1143 /* Statistics overflow. */ 1144 if (isr & IS_UpdateStats) 1145 stge_stats_update(sc); 1146 1147 /* Transmission errors. */ 1148 if (isr & IS_TxComplete) { 1149 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1150 for (;;) { 1151 txstat = CSR_READ_4(sc, STGE_TxStatus); 1152 if ((txstat & TS_TxComplete) == 0) 1153 break; 1154 if (txstat & TS_TxUnderrun) { 1155 sc->sc_txthresh++; 1156 if (sc->sc_txthresh > 0x0fff) 1157 sc->sc_txthresh = 0x0fff; 1158 printf("%s: transmit underrun, new " 1159 "threshold: %d bytes\n", 1160 device_xname(sc->sc_dev), 1161 sc->sc_txthresh << 5); 1162 } 1163 if (txstat & TS_MaxCollisions) 1164 printf("%s: excessive collisions\n", 1165 device_xname(sc->sc_dev)); 1166 } 1167 wantinit = 1; 1168 } 1169 1170 } 1171 1172 if (wantinit) 1173 stge_init(ifp); 1174 1175 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1176 1177 /* Try to get more packets going. */ 1178 if_schedule_deferred_start(ifp); 1179 1180 return (1); 1181 } 1182 1183 /* 1184 * stge_txintr: 1185 * 1186 * Helper; handle transmit interrupts. 1187 */ 1188 static void 1189 stge_txintr(struct stge_softc *sc) 1190 { 1191 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1192 struct stge_descsoft *ds; 1193 uint64_t control; 1194 int i; 1195 1196 /* 1197 * Go through our Tx list and free mbufs for those 1198 * frames which have been transmitted. 1199 */ 1200 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1201 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1202 ds = &sc->sc_txsoft[i]; 1203 1204 STGE_CDTXSYNC(sc, i, 1205 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1206 1207 control = le64toh(sc->sc_txdescs[i].tfd_control); 1208 if ((control & TFD_TFDDone) == 0) 1209 break; 1210 1211 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1212 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1213 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1214 m_freem(ds->ds_mbuf); 1215 ds->ds_mbuf = NULL; 1216 } 1217 1218 /* Update the dirty transmit buffer pointer. */ 1219 sc->sc_txdirty = i; 1220 1221 /* 1222 * If there are no more pending transmissions, cancel the watchdog 1223 * timer. 1224 */ 1225 if (sc->sc_txpending == 0) 1226 ifp->if_timer = 0; 1227 } 1228 1229 /* 1230 * stge_rxintr: 1231 * 1232 * Helper; handle receive interrupts. 1233 */ 1234 static void 1235 stge_rxintr(struct stge_softc *sc) 1236 { 1237 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1238 struct stge_descsoft *ds; 1239 struct mbuf *m, *tailm; 1240 uint64_t status; 1241 int i, len; 1242 1243 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1244 ds = &sc->sc_rxsoft[i]; 1245 1246 STGE_CDRXSYNC(sc, i, 1247 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1248 1249 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1250 1251 if ((status & RFD_RFDDone) == 0) 1252 break; 1253 1254 if (__predict_false(sc->sc_rxdiscard)) { 1255 STGE_INIT_RXDESC(sc, i); 1256 if (status & RFD_FrameEnd) { 1257 /* Reset our state. */ 1258 sc->sc_rxdiscard = 0; 1259 } 1260 continue; 1261 } 1262 1263 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1264 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1265 1266 m = ds->ds_mbuf; 1267 1268 /* 1269 * Add a new receive buffer to the ring. 1270 */ 1271 if (stge_add_rxbuf(sc, i) != 0) { 1272 /* 1273 * Failed, throw away what we've done so 1274 * far, and discard the rest of the packet. 1275 */ 1276 if_statinc(ifp, if_ierrors); 1277 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1278 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1279 STGE_INIT_RXDESC(sc, i); 1280 if ((status & RFD_FrameEnd) == 0) 1281 sc->sc_rxdiscard = 1; 1282 if (sc->sc_rxhead != NULL) 1283 m_freem(sc->sc_rxhead); 1284 STGE_RXCHAIN_RESET(sc); 1285 continue; 1286 } 1287 1288 #ifdef DIAGNOSTIC 1289 if (status & RFD_FrameStart) { 1290 KASSERT(sc->sc_rxhead == NULL); 1291 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1292 } 1293 #endif 1294 1295 STGE_RXCHAIN_LINK(sc, m); 1296 1297 /* 1298 * If this is not the end of the packet, keep 1299 * looking. 1300 */ 1301 if ((status & RFD_FrameEnd) == 0) { 1302 sc->sc_rxlen += m->m_len; 1303 continue; 1304 } 1305 1306 /* 1307 * Okay, we have the entire packet now... 1308 */ 1309 *sc->sc_rxtailp = NULL; 1310 m = sc->sc_rxhead; 1311 tailm = sc->sc_rxtail; 1312 1313 STGE_RXCHAIN_RESET(sc); 1314 1315 /* 1316 * If the packet had an error, drop it. Note we 1317 * count the error later in the periodic stats update. 1318 */ 1319 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1320 RFD_RxAlignmentError | RFD_RxFCSError | 1321 RFD_RxLengthError)) { 1322 m_freem(m); 1323 continue; 1324 } 1325 1326 /* 1327 * No errors. 1328 * 1329 * Note we have configured the chip to not include 1330 * the CRC at the end of the packet. 1331 */ 1332 len = RFD_RxDMAFrameLen(status); 1333 tailm->m_len = len - sc->sc_rxlen; 1334 1335 /* 1336 * If the packet is small enough to fit in a 1337 * single header mbuf, allocate one and copy 1338 * the data into it. This greatly reduces 1339 * memory consumption when we receive lots 1340 * of small packets. 1341 */ 1342 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1343 struct mbuf *nm; 1344 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1345 if (nm == NULL) { 1346 if_statinc(ifp, if_ierrors); 1347 m_freem(m); 1348 continue; 1349 } 1350 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1351 nm->m_data += 2; 1352 nm->m_pkthdr.len = nm->m_len = len; 1353 m_copydata(m, 0, len, mtod(nm, void *)); 1354 m_freem(m); 1355 m = nm; 1356 } 1357 1358 /* 1359 * Set the incoming checksum information for the packet. 1360 */ 1361 if (status & RFD_IPDetected) { 1362 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1363 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1364 if (status & RFD_IPError) 1365 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1366 if (status & RFD_TCPDetected) { 1367 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1368 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1369 if (status & RFD_TCPError) 1370 m->m_pkthdr.csum_flags |= 1371 M_CSUM_TCP_UDP_BAD; 1372 } else if (status & RFD_UDPDetected) { 1373 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1374 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1375 if (status & RFD_UDPError) 1376 m->m_pkthdr.csum_flags |= 1377 M_CSUM_TCP_UDP_BAD; 1378 } 1379 } 1380 1381 m_set_rcvif(m, ifp); 1382 m->m_pkthdr.len = len; 1383 1384 /* 1385 * Pass this up to any BPF listeners, but only 1386 * pass if up the stack if it's for us. 1387 */ 1388 #ifdef STGE_VLAN_UNTAG 1389 /* 1390 * Check for VLAN tagged packets 1391 */ 1392 if (status & RFD_VLANDetected) 1393 vlan_set_tag(m, RFD_TCI(status)); 1394 1395 #endif 1396 #if 0 1397 if (status & RFD_VLANDetected) { 1398 struct ether_header *eh; 1399 uint16_t etype; 1400 1401 eh = mtod(m, struct ether_header *); 1402 etype = ntohs(eh->ether_type); 1403 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1404 ifp->if_xname, (uint16_t) RFD_TCI(status), 1405 etype); 1406 } 1407 #endif 1408 /* Pass it on. */ 1409 if_percpuq_enqueue(ifp->if_percpuq, m); 1410 } 1411 1412 /* Update the receive pointer. */ 1413 sc->sc_rxptr = i; 1414 } 1415 1416 /* 1417 * stge_tick: 1418 * 1419 * One second timer, used to tick the MII. 1420 */ 1421 static void 1422 stge_tick(void *arg) 1423 { 1424 struct stge_softc *sc = arg; 1425 int s; 1426 1427 s = splnet(); 1428 mii_tick(&sc->sc_mii); 1429 stge_stats_update(sc); 1430 splx(s); 1431 1432 callout_schedule(&sc->sc_tick_ch, hz); 1433 } 1434 1435 /* 1436 * stge_stats_update: 1437 * 1438 * Read the TC9021 statistics counters. 1439 */ 1440 static void 1441 stge_stats_update(struct stge_softc *sc) 1442 { 1443 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1444 1445 (void) CSR_READ_4(sc, STGE_OctetRcvOk); 1446 1447 (void) CSR_READ_4(sc, STGE_FramesRcvdOk); 1448 1449 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1450 1451 if_statadd_ref(nsr, if_ierrors, 1452 (u_int) CSR_READ_2(sc, STGE_FramesLostRxErrors)); 1453 1454 (void) CSR_READ_4(sc, STGE_OctetXmtdOk); 1455 1456 if_statadd_ref(nsr, if_opackets, 1457 CSR_READ_4(sc, STGE_FramesXmtdOk)); 1458 1459 if_statadd_ref(nsr, if_collisions, 1460 CSR_READ_4(sc, STGE_LateCollisions) + 1461 CSR_READ_4(sc, STGE_MultiColFrames) + 1462 CSR_READ_4(sc, STGE_SingleColFrames)); 1463 1464 if_statadd_ref(nsr, if_oerrors, 1465 (u_int) CSR_READ_2(sc, STGE_FramesAbortXSColls) + 1466 (u_int) CSR_READ_2(sc, STGE_FramesWEXDeferal)); 1467 1468 IF_STAT_PUTREF(ifp); 1469 } 1470 1471 /* 1472 * stge_reset: 1473 * 1474 * Perform a soft reset on the TC9021. 1475 */ 1476 static void 1477 stge_reset(struct stge_softc *sc) 1478 { 1479 uint32_t ac; 1480 int i; 1481 1482 ac = CSR_READ_4(sc, STGE_AsicCtrl); 1483 1484 /* 1485 * Only assert RstOut if we're fiber. We need GMII clocks 1486 * to be present in order for the reset to complete on fiber 1487 * cards. 1488 */ 1489 CSR_WRITE_4(sc, STGE_AsicCtrl, 1490 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1491 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1492 (sc->sc_usefiber ? AC_RstOut : 0)); 1493 1494 delay(50000); 1495 1496 for (i = 0; i < STGE_TIMEOUT; i++) { 1497 delay(5000); 1498 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1499 break; 1500 } 1501 1502 if (i == STGE_TIMEOUT) 1503 printf("%s: reset failed to complete\n", 1504 device_xname(sc->sc_dev)); 1505 1506 delay(1000); 1507 } 1508 1509 /* 1510 * stge_init: [ ifnet interface function ] 1511 * 1512 * Initialize the interface. Must be called at splnet(). 1513 */ 1514 static int 1515 stge_init(struct ifnet *ifp) 1516 { 1517 struct stge_softc *sc = ifp->if_softc; 1518 struct stge_descsoft *ds; 1519 int i, error = 0; 1520 1521 /* 1522 * Cancel any pending I/O. 1523 */ 1524 stge_stop(ifp, 0); 1525 1526 /* 1527 * Reset the chip to a known state. 1528 */ 1529 stge_reset(sc); 1530 1531 /* 1532 * Initialize the transmit descriptor ring. 1533 */ 1534 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1535 for (i = 0; i < STGE_NTXDESC; i++) { 1536 sc->sc_txdescs[i].tfd_next = htole64( 1537 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1538 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1539 } 1540 sc->sc_txpending = 0; 1541 sc->sc_txdirty = 0; 1542 sc->sc_txlast = STGE_NTXDESC - 1; 1543 1544 /* 1545 * Initialize the receive descriptor and receive job 1546 * descriptor rings. 1547 */ 1548 for (i = 0; i < STGE_NRXDESC; i++) { 1549 ds = &sc->sc_rxsoft[i]; 1550 if (ds->ds_mbuf == NULL) { 1551 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1552 printf("%s: unable to allocate or map rx " 1553 "buffer %d, error = %d\n", 1554 device_xname(sc->sc_dev), i, error); 1555 /* 1556 * XXX Should attempt to run with fewer receive 1557 * XXX buffers instead of just failing. 1558 */ 1559 stge_rxdrain(sc); 1560 goto out; 1561 } 1562 } else 1563 STGE_INIT_RXDESC(sc, i); 1564 } 1565 sc->sc_rxptr = 0; 1566 sc->sc_rxdiscard = 0; 1567 STGE_RXCHAIN_RESET(sc); 1568 1569 /* Set the station address. */ 1570 for (i = 0; i < 6; i++) 1571 CSR_WRITE_1(sc, STGE_StationAddress0 + i, 1572 CLLADDR(ifp->if_sadl)[i]); 1573 1574 /* 1575 * Set the statistics masks. Disable all the RMON stats, 1576 * and disable selected stats in the non-RMON stats registers. 1577 */ 1578 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); 1579 CSR_WRITE_4(sc, STGE_StatisticsMask, 1580 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1581 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1582 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1583 (1U << 21)); 1584 1585 /* Set up the receive filter. */ 1586 stge_set_filter(sc); 1587 1588 /* 1589 * Give the transmit and receive ring to the chip. 1590 */ 1591 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 1592 ((uint64_t)STGE_CDTXADDR(sc, sc->sc_txdirty)) >> 32); 1593 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 1594 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1595 1596 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 1597 ((uint64_t)STGE_CDRXADDR(sc, sc->sc_rxptr)) >> 32); 1598 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 1599 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1600 1601 /* 1602 * Initialize the Tx auto-poll period. It's OK to make this number 1603 * large (255 is the max, but we use 127) -- we explicitly kick the 1604 * transmit engine when there's actually a packet. 1605 */ 1606 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 1607 1608 /* ..and the Rx auto-poll period. */ 1609 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 64); 1610 1611 /* Initialize the Tx start threshold. */ 1612 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); 1613 1614 /* RX DMA thresholds, from linux */ 1615 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); 1616 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); 1617 1618 /* Rx early threhold, from Linux */ 1619 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); 1620 1621 /* Tx DMA thresholds, from Linux */ 1622 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); 1623 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); 1624 1625 /* 1626 * Initialize the Rx DMA interrupt control register. We 1627 * request an interrupt after every incoming packet, but 1628 * defer it for 32us (64 * 512 ns). When the number of 1629 * interrupts pending reaches 8, we stop deferring the 1630 * interrupt, and signal it immediately. 1631 */ 1632 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl, 1633 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1634 1635 /* 1636 * Initialize the interrupt mask. 1637 */ 1638 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1639 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1640 CSR_WRITE_2(sc, STGE_IntStatus, 0xffff); 1641 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1642 1643 /* 1644 * Configure the DMA engine. 1645 * XXX Should auto-tune TxBurstLimit. 1646 */ 1647 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | 1648 DMAC_TxBurstLimit(3)); 1649 1650 /* 1651 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1652 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes 1653 * in the Rx FIFO. 1654 */ 1655 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16); 1656 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16); 1657 1658 /* 1659 * Set the maximum frame size. 1660 */ 1661 CSR_WRITE_2(sc, STGE_MaxFrameSize, 1662 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1663 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1664 ETHER_VLAN_ENCAP_LEN : 0)); 1665 1666 /* 1667 * Initialize MacCtrl -- do it before setting the media, 1668 * as setting the media will actually program the register. 1669 * 1670 * Note: We have to poke the IFS value before poking 1671 * anything else. 1672 */ 1673 sc->sc_MACCtrl = MC_IFSSelect(0); 1674 CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl); 1675 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1676 #ifdef STGE_VLAN_UNTAG 1677 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1678 #endif 1679 1680 if (sc->sc_rev >= 6) { /* >= B.2 */ 1681 /* Multi-frag frame bug work-around. */ 1682 CSR_WRITE_2(sc, STGE_DebugCtrl, 1683 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200); 1684 1685 /* Tx Poll Now bug work-around. */ 1686 CSR_WRITE_2(sc, STGE_DebugCtrl, 1687 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010); 1688 /* XXX ? from linux */ 1689 CSR_WRITE_2(sc, STGE_DebugCtrl, 1690 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020); 1691 } 1692 1693 /* 1694 * Set the current media. 1695 */ 1696 if ((error = ether_mediachange(ifp)) != 0) 1697 goto out; 1698 1699 /* 1700 * Start the one second MII clock. 1701 */ 1702 callout_schedule(&sc->sc_tick_ch, hz); 1703 1704 /* 1705 * ...all done! 1706 */ 1707 ifp->if_flags |= IFF_RUNNING; 1708 1709 out: 1710 if (error) 1711 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1712 return (error); 1713 } 1714 1715 /* 1716 * stge_drain: 1717 * 1718 * Drain the receive queue. 1719 */ 1720 static void 1721 stge_rxdrain(struct stge_softc *sc) 1722 { 1723 struct stge_descsoft *ds; 1724 int i; 1725 1726 for (i = 0; i < STGE_NRXDESC; i++) { 1727 ds = &sc->sc_rxsoft[i]; 1728 if (ds->ds_mbuf != NULL) { 1729 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1730 ds->ds_mbuf->m_next = NULL; 1731 m_freem(ds->ds_mbuf); 1732 ds->ds_mbuf = NULL; 1733 } 1734 } 1735 } 1736 1737 /* 1738 * stge_stop: [ ifnet interface function ] 1739 * 1740 * Stop transmission on the interface. 1741 */ 1742 static void 1743 stge_stop(struct ifnet *ifp, int disable) 1744 { 1745 struct stge_softc *sc = ifp->if_softc; 1746 struct stge_descsoft *ds; 1747 int i; 1748 1749 /* 1750 * Stop the one second clock. 1751 */ 1752 callout_stop(&sc->sc_tick_ch); 1753 1754 /* Down the MII. */ 1755 mii_down(&sc->sc_mii); 1756 1757 /* 1758 * Disable interrupts. 1759 */ 1760 CSR_WRITE_2(sc, STGE_IntEnable, 0); 1761 1762 /* 1763 * Stop receiver, transmitter, and stats update. 1764 */ 1765 CSR_WRITE_4(sc, STGE_MACCtrl, 1766 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1767 1768 /* 1769 * Stop the transmit and receive DMA. 1770 */ 1771 stge_dma_wait(sc); 1772 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); 1773 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0); 1774 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); 1775 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0); 1776 1777 /* 1778 * Release any queued transmit buffers. 1779 */ 1780 for (i = 0; i < STGE_NTXDESC; i++) { 1781 ds = &sc->sc_txsoft[i]; 1782 if (ds->ds_mbuf != NULL) { 1783 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1784 m_freem(ds->ds_mbuf); 1785 ds->ds_mbuf = NULL; 1786 } 1787 } 1788 1789 /* 1790 * Mark the interface down and cancel the watchdog timer. 1791 */ 1792 ifp->if_flags &= ~IFF_RUNNING; 1793 ifp->if_timer = 0; 1794 1795 if (disable) 1796 stge_rxdrain(sc); 1797 } 1798 1799 static int 1800 stge_eeprom_wait(struct stge_softc *sc) 1801 { 1802 int i; 1803 1804 for (i = 0; i < STGE_TIMEOUT; i++) { 1805 delay(1000); 1806 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0) 1807 return (0); 1808 } 1809 return (1); 1810 } 1811 1812 /* 1813 * stge_read_eeprom: 1814 * 1815 * Read data from the serial EEPROM. 1816 */ 1817 static void 1818 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1819 { 1820 1821 if (stge_eeprom_wait(sc)) 1822 printf("%s: EEPROM failed to come ready\n", 1823 device_xname(sc->sc_dev)); 1824 1825 CSR_WRITE_2(sc, STGE_EepromCtrl, 1826 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1827 if (stge_eeprom_wait(sc)) 1828 printf("%s: EEPROM read timed out\n", 1829 device_xname(sc->sc_dev)); 1830 *data = CSR_READ_2(sc, STGE_EepromData); 1831 } 1832 1833 /* 1834 * stge_add_rxbuf: 1835 * 1836 * Add a receive buffer to the indicated descriptor. 1837 */ 1838 static int 1839 stge_add_rxbuf(struct stge_softc *sc, int idx) 1840 { 1841 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1842 struct mbuf *m; 1843 int error; 1844 1845 MGETHDR(m, M_DONTWAIT, MT_DATA); 1846 if (m == NULL) 1847 return (ENOBUFS); 1848 1849 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1850 MCLGET(m, M_DONTWAIT); 1851 if ((m->m_flags & M_EXT) == 0) { 1852 m_freem(m); 1853 return (ENOBUFS); 1854 } 1855 1856 m->m_data = m->m_ext.ext_buf + 2; 1857 m->m_len = MCLBYTES - 2; 1858 1859 if (ds->ds_mbuf != NULL) 1860 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1861 1862 ds->ds_mbuf = m; 1863 1864 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1865 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1866 if (error) { 1867 printf("%s: can't load rx DMA map %d, error = %d\n", 1868 device_xname(sc->sc_dev), idx, error); 1869 panic("stge_add_rxbuf"); /* XXX */ 1870 } 1871 1872 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1873 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1874 1875 STGE_INIT_RXDESC(sc, idx); 1876 1877 return (0); 1878 } 1879 1880 /* 1881 * stge_set_filter: 1882 * 1883 * Set up the receive filter. 1884 */ 1885 static void 1886 stge_set_filter(struct stge_softc *sc) 1887 { 1888 struct ethercom *ec = &sc->sc_ethercom; 1889 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1890 struct ether_multi *enm; 1891 struct ether_multistep step; 1892 uint32_t crc; 1893 uint32_t mchash[2]; 1894 1895 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1896 if (ifp->if_flags & IFF_BROADCAST) 1897 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1898 1899 /* XXX: ST1023 only works in promiscuous mode */ 1900 if (sc->sc_stge1023) 1901 ifp->if_flags |= IFF_PROMISC; 1902 1903 if (ifp->if_flags & IFF_PROMISC) { 1904 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1905 goto allmulti; 1906 } 1907 1908 /* 1909 * Set up the multicast address filter by passing all multicast 1910 * addresses through a CRC generator, and then using the low-order 1911 * 6 bits as an index into the 64 bit multicast hash table. The 1912 * high order bits select the register, while the rest of the bits 1913 * select the bit within the register. 1914 */ 1915 1916 memset(mchash, 0, sizeof(mchash)); 1917 1918 ETHER_LOCK(ec); 1919 ETHER_FIRST_MULTI(step, ec, enm); 1920 if (enm == NULL) { 1921 ETHER_UNLOCK(ec); 1922 goto done; 1923 } 1924 1925 while (enm != NULL) { 1926 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1927 /* 1928 * We must listen to a range of multicast addresses. 1929 * For now, just accept all multicasts, rather than 1930 * trying to set only those filter bits needed to match 1931 * the range. (At this time, the only use of address 1932 * ranges is for IP multicast routing, for which the 1933 * range is big enough to require all bits set.) 1934 */ 1935 ETHER_UNLOCK(ec); 1936 goto allmulti; 1937 } 1938 1939 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1940 1941 /* Just want the 6 least significant bits. */ 1942 crc &= 0x3f; 1943 1944 /* Set the corresponding bit in the hash table. */ 1945 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1946 1947 ETHER_NEXT_MULTI(step, enm); 1948 } 1949 ETHER_UNLOCK(ec); 1950 1951 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1952 1953 ifp->if_flags &= ~IFF_ALLMULTI; 1954 goto done; 1955 1956 allmulti: 1957 ifp->if_flags |= IFF_ALLMULTI; 1958 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1959 1960 done: 1961 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1962 /* 1963 * Program the multicast hash table. 1964 */ 1965 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]); 1966 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]); 1967 } 1968 1969 CSR_WRITE_2(sc, STGE_ReceiveMode, sc->sc_ReceiveMode); 1970 } 1971 1972 /* 1973 * stge_mii_readreg: [mii interface function] 1974 * 1975 * Read a PHY register on the MII of the TC9021. 1976 */ 1977 static int 1978 stge_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1979 { 1980 1981 return mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg, val); 1982 } 1983 1984 /* 1985 * stge_mii_writereg: [mii interface function] 1986 * 1987 * Write a PHY register on the MII of the TC9021. 1988 */ 1989 static int 1990 stge_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1991 { 1992 1993 return mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, 1994 val); 1995 } 1996 1997 /* 1998 * stge_mii_statchg: [mii interface function] 1999 * 2000 * Callback from MII layer when media changes. 2001 */ 2002 static void 2003 stge_mii_statchg(struct ifnet *ifp) 2004 { 2005 struct stge_softc *sc = ifp->if_softc; 2006 2007 sc->sc_MACCtrl &= ~(MC_DuplexSelect | MC_RxFlowControlEnable | 2008 MC_TxFlowControlEnable); 2009 2010 if (sc->sc_mii.mii_media_active & IFM_FDX) 2011 sc->sc_MACCtrl |= MC_DuplexSelect; 2012 if ((sc->sc_mii.mii_media_active & IFM_ETH_RXPAUSE) != 0) 2013 sc->sc_MACCtrl |= MC_RxFlowControlEnable; 2014 if ((sc->sc_mii.mii_media_active & IFM_ETH_TXPAUSE) != 0) 2015 sc->sc_MACCtrl |= MC_TxFlowControlEnable; 2016 2017 CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl); 2018 } 2019 2020 /* 2021 * sste_mii_bitbang_read: [mii bit-bang interface function] 2022 * 2023 * Read the MII serial port for the MII bit-bang module. 2024 */ 2025 static uint32_t 2026 stge_mii_bitbang_read(device_t self) 2027 { 2028 struct stge_softc *sc = device_private(self); 2029 2030 return (CSR_READ_1(sc, STGE_PhyCtrl)); 2031 } 2032 2033 /* 2034 * stge_mii_bitbang_write: [mii big-bang interface function] 2035 * 2036 * Write the MII serial port for the MII bit-bang module. 2037 */ 2038 static void 2039 stge_mii_bitbang_write(device_t self, uint32_t val) 2040 { 2041 struct stge_softc *sc = device_private(self); 2042 2043 CSR_WRITE_1(sc, STGE_PhyCtrl, val | sc->sc_PhyCtrl); 2044 } 2045
Indexes created Tue Sep 30 20:09:53 GMT 2025