if_ti.c revision 1.111
1 /* $NetBSD: if_ti.c,v 1.111 2019/05/29 10:07:29 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.111 2019/05/29 10:07:29 msaitoh Exp $"); 85 86 #include "opt_inet.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/queue.h> 96 #include <sys/device.h> 97 #include <sys/reboot.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/if_ether.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #include <netinet/in_systm.h> 111 #include <netinet/ip.h> 112 #endif 113 114 115 #include <sys/bus.h> 116 117 #include <dev/pci/pcireg.h> 118 #include <dev/pci/pcivar.h> 119 #include <dev/pci/pcidevs.h> 120 121 #include <dev/pci/if_tireg.h> 122 123 #include <dev/microcode/tigon/ti_fw.h> 124 #include <dev/microcode/tigon/ti_fw2.h> 125 126 /* 127 * Various supported device vendors/types and their names. 128 */ 129 130 static const struct ti_type ti_devs[] = { 131 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 132 "Alteon AceNIC 1000BASE-SX Ethernet" }, 133 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 134 "Alteon AceNIC 1000BASE-T Ethernet" }, 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 136 "3Com 3c985-SX Gigabit Ethernet" }, 137 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 138 "Netgear GA620 1000BASE-SX Ethernet" }, 139 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 140 "Netgear GA620 1000BASE-T Ethernet" }, 141 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 142 "Silicon Graphics Gigabit Ethernet" }, 143 { 0, 0, NULL } 144 }; 145 146 static const struct ti_type *ti_type_match(struct pci_attach_args *); 147 static int ti_probe(device_t, cfdata_t, void *); 148 static void ti_attach(device_t, device_t, void *); 149 static bool ti_shutdown(device_t, int); 150 static void ti_txeof_tigon1(struct ti_softc *); 151 static void ti_txeof_tigon2(struct ti_softc *); 152 static void ti_rxeof(struct ti_softc *); 153 154 static void ti_stats_update(struct ti_softc *); 155 static int ti_encap_tigon1(struct ti_softc *, struct mbuf *, uint32_t *); 156 static int ti_encap_tigon2(struct ti_softc *, struct mbuf *, uint32_t *); 157 158 static int ti_intr(void *); 159 static void ti_start(struct ifnet *); 160 static int ti_ioctl(struct ifnet *, u_long, void *); 161 static void ti_init(void *); 162 static void ti_init2(struct ti_softc *); 163 static void ti_stop(struct ti_softc *); 164 static void ti_watchdog(struct ifnet *); 165 static int ti_ifmedia_upd(struct ifnet *); 166 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 167 168 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 169 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 170 static int ti_read_eeprom(struct ti_softc *, void *, int, int); 171 172 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 173 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 174 static void ti_setmulti(struct ti_softc *); 175 176 static void ti_mem(struct ti_softc *, uint32_t, uint32_t, const void *); 177 static void ti_loadfw(struct ti_softc *); 178 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 179 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, void *, int); 180 static void ti_handle_events(struct ti_softc *); 181 static int ti_alloc_jumbo_mem(struct ti_softc *); 182 static void *ti_jalloc(struct ti_softc *); 183 static void ti_jfree(struct mbuf *, void *, size_t, void *); 184 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 185 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 186 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 187 static int ti_init_rx_ring_std(struct ti_softc *); 188 static void ti_free_rx_ring_std(struct ti_softc *); 189 static int ti_init_rx_ring_jumbo(struct ti_softc *); 190 static void ti_free_rx_ring_jumbo(struct ti_softc *); 191 static int ti_init_rx_ring_mini(struct ti_softc *); 192 static void ti_free_rx_ring_mini(struct ti_softc *); 193 static void ti_free_tx_ring(struct ti_softc *); 194 static int ti_init_tx_ring(struct ti_softc *); 195 196 static int ti_64bitslot_war(struct ti_softc *); 197 static int ti_chipinit(struct ti_softc *); 198 static int ti_gibinit(struct ti_softc *); 199 200 static int ti_ether_ioctl(struct ifnet *, u_long, void *); 201 202 CFATTACH_DECL_NEW(ti, sizeof(struct ti_softc), 203 ti_probe, ti_attach, NULL, NULL); 204 205 /* 206 * Send an instruction or address to the EEPROM, check for ACK. 207 */ 208 static uint32_t 209 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 210 { 211 int i, ack = 0; 212 213 /* 214 * Make sure we're in TX mode. 215 */ 216 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 217 218 /* 219 * Feed in each bit and stobe the clock. 220 */ 221 for (i = 0x80; i; i >>= 1) { 222 if (byte & i) { 223 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 224 } else { 225 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 226 } 227 DELAY(1); 228 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 229 DELAY(1); 230 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 231 } 232 233 /* 234 * Turn off TX mode. 235 */ 236 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 237 238 /* 239 * Check for ack. 240 */ 241 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 242 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 243 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 244 245 return (ack); 246 } 247 248 /* 249 * Read a byte of data stored in the EEPROM at address 'addr.' 250 * We have to send two address bytes since the EEPROM can hold 251 * more than 256 bytes of data. 252 */ 253 static uint8_t 254 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 255 { 256 int i; 257 uint8_t byte = 0; 258 259 EEPROM_START(); 260 261 /* 262 * Send write control code to EEPROM. 263 */ 264 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 265 printf("%s: failed to send write command, status: %x\n", 266 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 267 return (1); 268 } 269 270 /* 271 * Send first byte of address of byte we want to read. 272 */ 273 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 274 printf("%s: failed to send address, status: %x\n", 275 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 276 return (1); 277 } 278 /* 279 * Send second byte address of byte we want to read. 280 */ 281 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 282 printf("%s: failed to send address, status: %x\n", 283 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 284 return (1); 285 } 286 287 EEPROM_STOP(); 288 EEPROM_START(); 289 /* 290 * Send read control code to EEPROM. 291 */ 292 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 293 printf("%s: failed to send read command, status: %x\n", 294 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 295 return (1); 296 } 297 298 /* 299 * Start reading bits from EEPROM. 300 */ 301 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 302 for (i = 0x80; i; i >>= 1) { 303 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 304 DELAY(1); 305 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 306 byte |= i; 307 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 308 DELAY(1); 309 } 310 311 EEPROM_STOP(); 312 313 /* 314 * No ACK generated for read, so just return byte. 315 */ 316 317 *dest = byte; 318 319 return (0); 320 } 321 322 /* 323 * Read a sequence of bytes from the EEPROM. 324 */ 325 static int 326 ti_read_eeprom(struct ti_softc *sc, void *destv, int off, int cnt) 327 { 328 char *dest = destv; 329 int err = 0, i; 330 uint8_t byte = 0; 331 332 for (i = 0; i < cnt; i++) { 333 err = ti_eeprom_getbyte(sc, off + i, &byte); 334 if (err) 335 break; 336 *(dest + i) = byte; 337 } 338 339 return (err ? 1 : 0); 340 } 341 342 /* 343 * NIC memory access function. Can be used to either clear a section 344 * of NIC local memory or (if tbuf is non-NULL) copy data into it. 345 */ 346 static void 347 ti_mem(struct ti_softc *sc, uint32_t addr, uint32_t len, const void *xbuf) 348 { 349 int segptr, segsize, cnt; 350 const void *ptr; 351 352 segptr = addr; 353 cnt = len; 354 ptr = xbuf; 355 356 while (cnt) { 357 if (cnt < TI_WINLEN) 358 segsize = cnt; 359 else 360 segsize = TI_WINLEN - (segptr % TI_WINLEN); 361 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 362 if (xbuf == NULL) { 363 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 364 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 365 segsize / 4); 366 } else { 367 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 368 bus_space_write_region_stream_4(sc->ti_btag, 369 sc->ti_bhandle, 370 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 371 (const uint32_t *)ptr, segsize / 4); 372 #else 373 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 374 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 375 (const uint32_t *)ptr, segsize / 4); 376 #endif 377 ptr = (const char *)ptr + segsize; 378 } 379 segptr += segsize; 380 cnt -= segsize; 381 } 382 383 return; 384 } 385 386 /* 387 * Load firmware image into the NIC. Check that the firmware revision 388 * is acceptable and see if we want the firmware for the Tigon 1 or 389 * Tigon 2. 390 */ 391 static void 392 ti_loadfw(struct ti_softc *sc) 393 { 394 switch (sc->ti_hwrev) { 395 case TI_HWREV_TIGON: 396 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 397 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 398 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 399 printf("%s: firmware revision mismatch; want " 400 "%d.%d.%d, got %d.%d.%d\n", device_xname(sc->sc_dev), 401 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 402 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 403 tigonFwReleaseMinor, tigonFwReleaseFix); 404 return; 405 } 406 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 407 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 408 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, tigonFwRodata); 409 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 410 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 411 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 412 break; 413 case TI_HWREV_TIGON_II: 414 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 415 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 416 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 417 printf("%s: firmware revision mismatch; want " 418 "%d.%d.%d, got %d.%d.%d\n", device_xname(sc->sc_dev), 419 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 420 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 421 tigon2FwReleaseMinor, tigon2FwReleaseFix); 422 return; 423 } 424 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, tigon2FwText); 425 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, tigon2FwData); 426 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 427 tigon2FwRodata); 428 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 429 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 430 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 431 break; 432 default: 433 printf("%s: can't load firmware: unknown hardware rev\n", 434 device_xname(sc->sc_dev)); 435 break; 436 } 437 438 return; 439 } 440 441 /* 442 * Send the NIC a command via the command ring. 443 */ 444 static void 445 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 446 { 447 uint32_t index; 448 449 index = sc->ti_cmd_saved_prodidx; 450 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 451 TI_INC(index, TI_CMD_RING_CNT); 452 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 453 sc->ti_cmd_saved_prodidx = index; 454 } 455 456 /* 457 * Send the NIC an extended command. The 'len' parameter specifies the 458 * number of command slots to include after the initial command. 459 */ 460 static void 461 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, void *argv, int len) 462 { 463 char *arg = argv; 464 uint32_t index; 465 int i; 466 467 index = sc->ti_cmd_saved_prodidx; 468 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 469 TI_INC(index, TI_CMD_RING_CNT); 470 for (i = 0; i < len; i++) { 471 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 472 *(uint32_t *)(&arg[i * 4])); 473 TI_INC(index, TI_CMD_RING_CNT); 474 } 475 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 476 sc->ti_cmd_saved_prodidx = index; 477 } 478 479 /* 480 * Handle events that have triggered interrupts. 481 */ 482 static void 483 ti_handle_events(struct ti_softc *sc) 484 { 485 struct ti_event_desc *e; 486 487 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 488 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 489 switch (TI_EVENT_EVENT(e)) { 490 case TI_EV_LINKSTAT_CHANGED: 491 sc->ti_linkstat = TI_EVENT_CODE(e); 492 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) 493 printf("%s: 10/100 link up\n", 494 device_xname(sc->sc_dev)); 495 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 496 printf("%s: gigabit link up\n", 497 device_xname(sc->sc_dev)); 498 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 499 printf("%s: link down\n", 500 device_xname(sc->sc_dev)); 501 break; 502 case TI_EV_ERROR: 503 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 504 printf("%s: invalid command\n", 505 device_xname(sc->sc_dev)); 506 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 507 printf("%s: unknown command\n", 508 device_xname(sc->sc_dev)); 509 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 510 printf("%s: bad config data\n", 511 device_xname(sc->sc_dev)); 512 break; 513 case TI_EV_FIRMWARE_UP: 514 ti_init2(sc); 515 break; 516 case TI_EV_STATS_UPDATED: 517 ti_stats_update(sc); 518 break; 519 case TI_EV_RESET_JUMBO_RING: 520 case TI_EV_MCAST_UPDATED: 521 /* Who cares. */ 522 break; 523 default: 524 printf("%s: unknown event: %d\n", 525 device_xname(sc->sc_dev), TI_EVENT_EVENT(e)); 526 break; 527 } 528 /* Advance the consumer index. */ 529 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 530 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 531 } 532 533 return; 534 } 535 536 /* 537 * Memory management for the jumbo receive ring is a pain in the 538 * butt. We need to allocate at least 9018 bytes of space per frame, 539 * _and_ it has to be contiguous (unless you use the extended 540 * jumbo descriptor format). Using malloc() all the time won't 541 * work: malloc() allocates memory in powers of two, which means we 542 * would end up wasting a considerable amount of space by allocating 543 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 544 * to do our own memory management. 545 * 546 * The driver needs to allocate a contiguous chunk of memory at boot 547 * time. We then chop this up ourselves into 9K pieces and use them 548 * as external mbuf storage. 549 * 550 * One issue here is how much memory to allocate. The jumbo ring has 551 * 256 slots in it, but at 9K per slot than can consume over 2MB of 552 * RAM. This is a bit much, especially considering we also need 553 * RAM for the standard ring and mini ring (on the Tigon 2). To 554 * save space, we only actually allocate enough memory for 64 slots 555 * by default, which works out to between 500 and 600K. This can 556 * be tuned by changing a #define in if_tireg.h. 557 */ 558 559 static int 560 ti_alloc_jumbo_mem(struct ti_softc *sc) 561 { 562 char *ptr; 563 int i; 564 struct ti_jpool_entry *entry; 565 bus_dma_segment_t dmaseg; 566 int error, dmanseg; 567 568 /* Grab a big chunk o' storage. */ 569 if ((error = bus_dmamem_alloc(sc->sc_dmat, 570 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 571 BUS_DMA_NOWAIT)) != 0) { 572 aprint_error_dev(sc->sc_dev, 573 "can't allocate jumbo buffer, error = %d\n", error); 574 return (error); 575 } 576 577 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 578 TI_JMEM, (void **)&sc->ti_cdata.ti_jumbo_buf, 579 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 580 aprint_error_dev(sc->sc_dev, 581 "can't map jumbo buffer, error = %d\n", error); 582 return (error); 583 } 584 585 if ((error = bus_dmamap_create(sc->sc_dmat, 586 TI_JMEM, 1, 587 TI_JMEM, 0, BUS_DMA_NOWAIT, 588 &sc->jumbo_dmamap)) != 0) { 589 aprint_error_dev(sc->sc_dev, 590 "can't create jumbo buffer DMA map, error = %d\n", error); 591 return (error); 592 } 593 594 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 595 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 596 BUS_DMA_NOWAIT)) != 0) { 597 aprint_error_dev(sc->sc_dev, 598 "can't load jumbo buffer DMA map, error = %d\n", error); 599 return (error); 600 } 601 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 602 603 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 604 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 605 606 /* 607 * Now divide it up into 9K pieces and save the addresses 608 * in an array. 609 */ 610 ptr = sc->ti_cdata.ti_jumbo_buf; 611 for (i = 0; i < TI_JSLOTS; i++) { 612 sc->ti_cdata.ti_jslots[i] = ptr; 613 ptr += TI_JLEN; 614 entry = malloc(sizeof(struct ti_jpool_entry), 615 M_DEVBUF, M_NOWAIT); 616 if (entry == NULL) { 617 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 618 sc->ti_cdata.ti_jumbo_buf = NULL; 619 printf("%s: no memory for jumbo " 620 "buffer queue!\n", device_xname(sc->sc_dev)); 621 return (ENOBUFS); 622 } 623 entry->slot = i; 624 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 625 jpool_entries); 626 } 627 628 return (0); 629 } 630 631 /* 632 * Allocate a jumbo buffer. 633 */ 634 static void * 635 ti_jalloc(struct ti_softc *sc) 636 { 637 struct ti_jpool_entry *entry; 638 639 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 640 641 if (entry == NULL) { 642 printf("%s: no free jumbo buffers\n", device_xname(sc->sc_dev)); 643 return (NULL); 644 } 645 646 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 647 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 648 649 return (sc->ti_cdata.ti_jslots[entry->slot]); 650 } 651 652 /* 653 * Release a jumbo buffer. 654 */ 655 static void 656 ti_jfree(struct mbuf *m, void *tbuf, size_t size, void *arg) 657 { 658 struct ti_softc *sc; 659 int i, s; 660 struct ti_jpool_entry *entry; 661 662 /* Extract the softc struct pointer. */ 663 sc = (struct ti_softc *)arg; 664 665 if (sc == NULL) 666 panic("ti_jfree: didn't get softc pointer!"); 667 668 /* calculate the slot this buffer belongs to */ 669 670 i = ((char *)tbuf 671 - (char *)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 672 673 if ((i < 0) || (i >= TI_JSLOTS)) 674 panic("ti_jfree: asked to free buffer that we don't manage!"); 675 676 s = splvm(); 677 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 678 if (entry == NULL) 679 panic("ti_jfree: buffer not in use!"); 680 entry->slot = i; 681 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 682 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 683 684 if (__predict_true(m != NULL)) 685 pool_cache_put(mb_cache, m); 686 splx(s); 687 } 688 689 690 /* 691 * Initialize a standard receive ring descriptor. 692 */ 693 static int 694 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 695 { 696 struct mbuf *m_new = NULL; 697 struct ti_rx_desc *r; 698 int error; 699 700 if (dmamap == NULL) { 701 /* if (m) panic() */ 702 703 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 704 MCLBYTES, 0, BUS_DMA_NOWAIT, 705 &dmamap)) != 0) { 706 aprint_error_dev(sc->sc_dev, 707 "can't create recv map, error = %d\n", error); 708 return (ENOMEM); 709 } 710 } 711 sc->std_dmamap[i] = dmamap; 712 713 if (m == NULL) { 714 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 715 if (m_new == NULL) { 716 aprint_error_dev(sc->sc_dev, 717 "mbuf allocation failed -- packet dropped!\n"); 718 return (ENOBUFS); 719 } 720 721 MCLGET(m_new, M_DONTWAIT); 722 if (!(m_new->m_flags & M_EXT)) { 723 aprint_error_dev(sc->sc_dev, 724 "cluster allocation failed -- packet dropped!\n"); 725 m_freem(m_new); 726 return (ENOBUFS); 727 } 728 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 729 m_adj(m_new, ETHER_ALIGN); 730 731 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 732 mtod(m_new, void *), m_new->m_len, NULL, 733 BUS_DMA_READ | BUS_DMA_NOWAIT)) != 0) { 734 aprint_error_dev(sc->sc_dev, 735 "can't load recv map, error = %d\n", error); 736 m_freem(m_new); 737 return (ENOMEM); 738 } 739 } else { 740 m_new = m; 741 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 742 m_new->m_data = m_new->m_ext.ext_buf; 743 m_adj(m_new, ETHER_ALIGN); 744 745 /* reuse the dmamap */ 746 } 747 748 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 749 r = &sc->ti_rdata->ti_rx_std_ring[i]; 750 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 751 r->ti_type = TI_BDTYPE_RECV_BD; 752 r->ti_flags = 0; 753 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 754 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 755 if (sc->ethercom.ec_if.if_capenable & 756 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 757 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 758 r->ti_len = m_new->m_len; /* == ds_len */ 759 r->ti_idx = i; 760 761 return (0); 762 } 763 764 /* 765 * Intialize a mini receive ring descriptor. This only applies to 766 * the Tigon 2. 767 */ 768 static int 769 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 770 { 771 struct mbuf *m_new = NULL; 772 struct ti_rx_desc *r; 773 int error; 774 775 if (dmamap == NULL) { 776 /* if (m) panic() */ 777 778 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 779 MHLEN, 0, BUS_DMA_NOWAIT, 780 &dmamap)) != 0) { 781 aprint_error_dev(sc->sc_dev, 782 "can't create recv map, error = %d\n", error); 783 return (ENOMEM); 784 } 785 } 786 sc->mini_dmamap[i] = dmamap; 787 788 if (m == NULL) { 789 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 790 if (m_new == NULL) { 791 aprint_error_dev(sc->sc_dev, 792 "mbuf allocation failed -- packet dropped!\n"); 793 return (ENOBUFS); 794 } 795 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 796 m_adj(m_new, ETHER_ALIGN); 797 798 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 799 mtod(m_new, void *), m_new->m_len, NULL, 800 BUS_DMA_READ | BUS_DMA_NOWAIT)) != 0) { 801 aprint_error_dev(sc->sc_dev, 802 "can't load recv map, error = %d\n", error); 803 m_freem(m_new); 804 return (ENOMEM); 805 } 806 } else { 807 m_new = m; 808 m_new->m_data = m_new->m_pktdat; 809 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 810 m_adj(m_new, ETHER_ALIGN); 811 812 /* reuse the dmamap */ 813 } 814 815 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 816 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 817 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 818 r->ti_type = TI_BDTYPE_RECV_BD; 819 r->ti_flags = TI_BDFLAG_MINI_RING; 820 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 821 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 822 if (sc->ethercom.ec_if.if_capenable & 823 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 824 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 825 r->ti_len = m_new->m_len; /* == ds_len */ 826 r->ti_idx = i; 827 828 return (0); 829 } 830 831 /* 832 * Initialize a jumbo receive ring descriptor. This allocates 833 * a jumbo buffer from the pool managed internally by the driver. 834 */ 835 static int 836 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m) 837 { 838 struct mbuf *m_new = NULL; 839 struct ti_rx_desc *r; 840 841 if (m == NULL) { 842 void * tbuf = NULL; 843 844 /* Allocate the mbuf. */ 845 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 846 if (m_new == NULL) { 847 aprint_error_dev(sc->sc_dev, 848 "mbuf allocation failed -- packet dropped!\n"); 849 return (ENOBUFS); 850 } 851 852 /* Allocate the jumbo buffer */ 853 tbuf = ti_jalloc(sc); 854 if (tbuf == NULL) { 855 m_freem(m_new); 856 aprint_error_dev(sc->sc_dev, 857 "jumbo allocation failed -- packet dropped!\n"); 858 return (ENOBUFS); 859 } 860 861 /* Attach the buffer to the mbuf. */ 862 MEXTADD(m_new, tbuf, ETHER_MAX_LEN_JUMBO, 863 M_DEVBUF, ti_jfree, sc); 864 m_new->m_flags |= M_EXT_RW; 865 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 866 } else { 867 m_new = m; 868 m_new->m_data = m_new->m_ext.ext_buf; 869 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 870 } 871 872 m_adj(m_new, ETHER_ALIGN); 873 /* Set up the descriptor. */ 874 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 875 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 876 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 877 (mtod(m_new, char *) - (char *)sc->ti_cdata.ti_jumbo_buf); 878 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 879 r->ti_flags = TI_BDFLAG_JUMBO_RING; 880 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 881 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 882 if (sc->ethercom.ec_if.if_capenable & 883 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 884 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 885 r->ti_len = m_new->m_len; 886 r->ti_idx = i; 887 888 return (0); 889 } 890 891 /* 892 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 893 * that's 1MB or memory, which is a lot. For now, we fill only the first 894 * 256 ring entries and hope that our CPU is fast enough to keep up with 895 * the NIC. 896 */ 897 static int 898 ti_init_rx_ring_std(struct ti_softc *sc) 899 { 900 int i; 901 struct ti_cmd_desc cmd; 902 903 for (i = 0; i < TI_SSLOTS; i++) { 904 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 905 return (ENOBUFS); 906 }; 907 908 TI_UPDATE_STDPROD(sc, i - 1); 909 sc->ti_std = i - 1; 910 911 return (0); 912 } 913 914 static void 915 ti_free_rx_ring_std(struct ti_softc *sc) 916 { 917 int i; 918 919 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 920 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 921 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 922 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 923 924 /* if (sc->std_dmamap[i] == 0) panic() */ 925 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 926 sc->std_dmamap[i] = 0; 927 } 928 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 929 sizeof(struct ti_rx_desc)); 930 } 931 932 return; 933 } 934 935 static int 936 ti_init_rx_ring_jumbo(struct ti_softc *sc) 937 { 938 int i; 939 struct ti_cmd_desc cmd; 940 941 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 942 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 943 return (ENOBUFS); 944 }; 945 946 TI_UPDATE_JUMBOPROD(sc, i - 1); 947 sc->ti_jumbo = i - 1; 948 949 return (0); 950 } 951 952 static void 953 ti_free_rx_ring_jumbo(struct ti_softc *sc) 954 { 955 int i; 956 957 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 958 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 959 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 960 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 961 } 962 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 963 sizeof(struct ti_rx_desc)); 964 } 965 966 return; 967 } 968 969 static int 970 ti_init_rx_ring_mini(struct ti_softc *sc) 971 { 972 int i; 973 974 for (i = 0; i < TI_MSLOTS; i++) { 975 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 976 return (ENOBUFS); 977 }; 978 979 TI_UPDATE_MINIPROD(sc, i - 1); 980 sc->ti_mini = i - 1; 981 982 return (0); 983 } 984 985 static void 986 ti_free_rx_ring_mini(struct ti_softc *sc) 987 { 988 int i; 989 990 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 991 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 992 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 993 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 994 995 /* if (sc->mini_dmamap[i] == 0) panic() */ 996 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 997 sc->mini_dmamap[i] = 0; 998 } 999 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1000 sizeof(struct ti_rx_desc)); 1001 } 1002 1003 return; 1004 } 1005 1006 static void 1007 ti_free_tx_ring(struct ti_softc *sc) 1008 { 1009 int i; 1010 struct txdmamap_pool_entry *dma; 1011 1012 for (i = 0; i < TI_TX_RING_CNT; i++) { 1013 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1014 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1015 sc->ti_cdata.ti_tx_chain[i] = NULL; 1016 1017 /* if (sc->txdma[i] == 0) panic() */ 1018 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1019 link); 1020 sc->txdma[i] = 0; 1021 } 1022 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1023 sizeof(struct ti_tx_desc)); 1024 } 1025 1026 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1027 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1028 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1029 free(dma, M_DEVBUF); 1030 } 1031 1032 return; 1033 } 1034 1035 static int 1036 ti_init_tx_ring(struct ti_softc *sc) 1037 { 1038 int i, error; 1039 bus_dmamap_t dmamap; 1040 struct txdmamap_pool_entry *dma; 1041 1042 sc->ti_txcnt = 0; 1043 sc->ti_tx_saved_considx = 0; 1044 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1045 1046 SIMPLEQ_INIT(&sc->txdma_list); 1047 for (i = 0; i < TI_RSLOTS; i++) { 1048 /* I've seen mbufs with 30 fragments. */ 1049 if ((error = bus_dmamap_create(sc->sc_dmat, 1050 ETHER_MAX_LEN_JUMBO, 40, ETHER_MAX_LEN_JUMBO, 0, 1051 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1052 aprint_error_dev(sc->sc_dev, 1053 "can't create tx map, error = %d\n", error); 1054 return (ENOMEM); 1055 } 1056 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1057 if (!dma) { 1058 aprint_error_dev(sc->sc_dev, 1059 "can't alloc txdmamap_pool_entry\n"); 1060 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1061 return (ENOMEM); 1062 } 1063 dma->dmamap = dmamap; 1064 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1065 } 1066 1067 return (0); 1068 } 1069 1070 /* 1071 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1072 * but we have to support the old way too so that Tigon 1 cards will 1073 * work. 1074 */ 1075 static void 1076 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1077 { 1078 struct ti_cmd_desc cmd; 1079 uint16_t *m; 1080 uint32_t ext[2] = {0, 0}; 1081 1082 m = (uint16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1083 1084 switch (sc->ti_hwrev) { 1085 case TI_HWREV_TIGON: 1086 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1087 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1088 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1089 break; 1090 case TI_HWREV_TIGON_II: 1091 ext[0] = htons(m[0]); 1092 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1093 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (void *)&ext, 2); 1094 break; 1095 default: 1096 printf("%s: unknown hwrev\n", device_xname(sc->sc_dev)); 1097 break; 1098 } 1099 1100 return; 1101 } 1102 1103 static void 1104 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1105 { 1106 struct ti_cmd_desc cmd; 1107 uint16_t *m; 1108 uint32_t ext[2] = {0, 0}; 1109 1110 m = (uint16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1111 1112 switch (sc->ti_hwrev) { 1113 case TI_HWREV_TIGON: 1114 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1115 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1116 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1117 break; 1118 case TI_HWREV_TIGON_II: 1119 ext[0] = htons(m[0]); 1120 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1121 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (void *)&ext, 2); 1122 break; 1123 default: 1124 printf("%s: unknown hwrev\n", device_xname(sc->sc_dev)); 1125 break; 1126 } 1127 1128 return; 1129 } 1130 1131 /* 1132 * Configure the Tigon's multicast address filter. 1133 * 1134 * The actual multicast table management is a bit of a pain, thanks to 1135 * slight brain damage on the part of both Alteon and us. With our 1136 * multicast code, we are only alerted when the multicast address table 1137 * changes and at that point we only have the current list of addresses: 1138 * we only know the current state, not the previous state, so we don't 1139 * actually know what addresses were removed or added. The firmware has 1140 * state, but we can't get our grubby mits on it, and there is no 'delete 1141 * all multicast addresses' command. Hence, we have to maintain our own 1142 * state so we know what addresses have been programmed into the NIC at 1143 * any given time. 1144 */ 1145 static void 1146 ti_setmulti(struct ti_softc *sc) 1147 { 1148 struct ethercom *ec = &sc->ethercom; 1149 struct ifnet *ifp = &ec->ec_if; 1150 struct ti_cmd_desc cmd; 1151 struct ti_mc_entry *mc; 1152 uint32_t intrs; 1153 struct ether_multi *enm; 1154 struct ether_multistep step; 1155 1156 /* Disable interrupts. */ 1157 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1158 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1159 1160 /* First, zot all the existing filters. */ 1161 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1162 ti_del_mcast(sc, &mc->mc_addr); 1163 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1164 free(mc, M_DEVBUF); 1165 } 1166 1167 /* 1168 * Remember all multicast addresses so that we can delete them 1169 * later. Punt if there is a range of addresses or memory shortage. 1170 */ 1171 ETHER_LOCK(ec); 1172 ETHER_FIRST_MULTI(step, ec, enm); 1173 while (enm != NULL) { 1174 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1175 ETHER_ADDR_LEN) != 0) { 1176 ETHER_UNLOCK(ec); 1177 goto allmulti; 1178 } 1179 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1180 M_NOWAIT)) == NULL) { 1181 ETHER_UNLOCK(ec); 1182 goto allmulti; 1183 } 1184 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1185 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1186 ETHER_NEXT_MULTI(step, enm); 1187 } 1188 ETHER_UNLOCK(ec); 1189 1190 /* Accept only programmed multicast addresses */ 1191 ifp->if_flags &= ~IFF_ALLMULTI; 1192 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1193 1194 /* Now program new ones. */ 1195 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1196 ti_add_mcast(sc, &mc->mc_addr); 1197 1198 /* Re-enable interrupts. */ 1199 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1200 1201 return; 1202 1203 allmulti: 1204 /* No need to keep individual multicast addresses */ 1205 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1206 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1207 free(mc, M_DEVBUF); 1208 } 1209 1210 /* Accept all multicast addresses */ 1211 ifp->if_flags |= IFF_ALLMULTI; 1212 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1213 1214 /* Re-enable interrupts. */ 1215 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1216 } 1217 1218 /* 1219 * Check to see if the BIOS has configured us for a 64 bit slot when 1220 * we aren't actually in one. If we detect this condition, we can work 1221 * around it on the Tigon 2 by setting a bit in the PCI state register, 1222 * but for the Tigon 1 we must give up and abort the interface attach. 1223 */ 1224 static int 1225 ti_64bitslot_war(struct ti_softc *sc) 1226 { 1227 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1228 CSR_WRITE_4(sc, 0x600, 0); 1229 CSR_WRITE_4(sc, 0x604, 0); 1230 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1231 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1232 if (sc->ti_hwrev == TI_HWREV_TIGON) 1233 return (EINVAL); 1234 else { 1235 TI_SETBIT(sc, TI_PCI_STATE, 1236 TI_PCISTATE_32BIT_BUS); 1237 return (0); 1238 } 1239 } 1240 } 1241 1242 return (0); 1243 } 1244 1245 /* 1246 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1247 * self-test results. 1248 */ 1249 static int 1250 ti_chipinit(struct ti_softc *sc) 1251 { 1252 uint32_t cacheline; 1253 uint32_t pci_writemax = 0; 1254 uint32_t rev; 1255 1256 /* Initialize link to down state. */ 1257 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1258 1259 /* Set endianness before we access any non-PCI registers. */ 1260 #if BYTE_ORDER == BIG_ENDIAN 1261 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1262 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1263 #else 1264 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1265 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1266 #endif 1267 1268 /* Check the ROM failed bit to see if self-tests passed. */ 1269 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1270 printf("%s: board self-diagnostics failed!\n", 1271 device_xname(sc->sc_dev)); 1272 return (ENODEV); 1273 } 1274 1275 /* Halt the CPU. */ 1276 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1277 1278 /* Figure out the hardware revision. */ 1279 rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK; 1280 switch (rev) { 1281 case TI_REV_TIGON_I: 1282 sc->ti_hwrev = TI_HWREV_TIGON; 1283 break; 1284 case TI_REV_TIGON_II: 1285 sc->ti_hwrev = TI_HWREV_TIGON_II; 1286 break; 1287 default: 1288 printf("%s: unsupported chip revision 0x%x\n", 1289 device_xname(sc->sc_dev), rev); 1290 return (ENODEV); 1291 } 1292 1293 /* Do special setup for Tigon 2. */ 1294 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1295 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1296 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1297 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1298 } 1299 1300 /* Set up the PCI state register. */ 1301 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD | TI_PCI_WRITE_CMD); 1302 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1303 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1304 } 1305 1306 /* Clear the read/write max DMA parameters. */ 1307 TI_CLRBIT(sc, TI_PCI_STATE, 1308 (TI_PCISTATE_WRITE_MAXDMA | TI_PCISTATE_READ_MAXDMA)); 1309 1310 /* Get cache line size. */ 1311 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1312 1313 /* 1314 * If the system has set enabled the PCI memory write 1315 * and invalidate command in the command register, set 1316 * the write max parameter accordingly. This is necessary 1317 * to use MWI with the Tigon 2. 1318 */ 1319 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1320 & PCI_COMMAND_INVALIDATE_ENABLE) { 1321 switch (cacheline) { 1322 case 1: 1323 case 4: 1324 case 8: 1325 case 16: 1326 case 32: 1327 case 64: 1328 break; 1329 default: 1330 /* Disable PCI memory write and invalidate. */ 1331 if (bootverbose) 1332 printf("%s: cache line size %d not " 1333 "supported; disabling PCI MWI\n", 1334 device_xname(sc->sc_dev), cacheline); 1335 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1336 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1337 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1338 break; 1339 } 1340 } 1341 1342 #ifdef __brokenalpha__ 1343 /* 1344 * From the Alteon sample driver: 1345 * Must insure that we do not cross an 8K (bytes) boundary 1346 * for DMA reads. Our highest limit is 1K bytes. This is a 1347 * restriction on some ALPHA platforms with early revision 1348 * 21174 PCI chipsets, such as the AlphaPC 164lx 1349 */ 1350 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax | TI_PCI_READMAX_1024); 1351 #else 1352 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1353 #endif 1354 1355 /* This sets the min dma param all the way up (0xff). */ 1356 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1357 1358 /* Configure DMA variables. */ 1359 #if BYTE_ORDER == BIG_ENDIAN 1360 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1361 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1362 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1363 TI_OPMODE_DONT_FRAG_JUMBO); 1364 #else 1365 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA | 1366 TI_OPMODE_WORDSWAP_BD | TI_OPMODE_DONT_FRAG_JUMBO | 1367 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB); 1368 #endif 1369 1370 /* 1371 * Only allow 1 DMA channel to be active at a time. 1372 * I don't think this is a good idea, but without it 1373 * the firmware racks up lots of nicDmaReadRingFull 1374 * errors. 1375 * Incompatible with hardware assisted checksums. 1376 */ 1377 if ((sc->ethercom.ec_if.if_capenable & 1378 (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1379 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1380 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx)) == 0) 1381 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1382 1383 /* Recommended settings from Tigon manual. */ 1384 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1385 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1386 1387 if (ti_64bitslot_war(sc)) { 1388 printf("%s: bios thinks we're in a 64 bit slot, " 1389 "but we aren't", device_xname(sc->sc_dev)); 1390 return (EINVAL); 1391 } 1392 1393 return (0); 1394 } 1395 1396 /* 1397 * Initialize the general information block and firmware, and 1398 * start the CPU(s) running. 1399 */ 1400 static int 1401 ti_gibinit(struct ti_softc *sc) 1402 { 1403 struct ti_rcb *rcb; 1404 int i; 1405 struct ifnet *ifp; 1406 1407 ifp = &sc->ethercom.ec_if; 1408 1409 /* Disable interrupts for now. */ 1410 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1411 1412 /* Tell the chip where to find the general information block. */ 1413 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1414 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1415 1416 /* Load the firmware into SRAM. */ 1417 ti_loadfw(sc); 1418 1419 /* Set up the contents of the general info and ring control blocks. */ 1420 1421 /* Set up the event ring and producer pointer. */ 1422 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1423 1424 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1425 rcb->ti_flags = 0; 1426 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1427 TI_CDEVPRODADDR(sc); 1428 1429 sc->ti_ev_prodidx.ti_idx = 0; 1430 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1431 sc->ti_ev_saved_considx = 0; 1432 1433 /* Set up the command ring and producer mailbox. */ 1434 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1435 1436 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1437 rcb->ti_flags = 0; 1438 rcb->ti_max_len = 0; 1439 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1440 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1441 } 1442 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1443 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1444 sc->ti_cmd_saved_prodidx = 0; 1445 1446 /* 1447 * Assign the address of the stats refresh buffer. 1448 * We re-use the current stats buffer for this to 1449 * conserve memory. 1450 */ 1451 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1452 TI_CDSTATSADDR(sc); 1453 1454 /* Set up the standard receive ring. */ 1455 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1456 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1457 rcb->ti_max_len = ETHER_MAX_LEN; 1458 rcb->ti_flags = 0; 1459 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1460 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1461 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1462 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1463 if (VLAN_ATTACHED(&sc->ethercom)) 1464 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1465 1466 /* Set up the jumbo receive ring. */ 1467 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1468 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1469 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1470 rcb->ti_flags = 0; 1471 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1472 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1473 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1474 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1475 if (VLAN_ATTACHED(&sc->ethercom)) 1476 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1477 1478 /* 1479 * Set up the mini ring. Only activated on the 1480 * Tigon 2 but the slot in the config block is 1481 * still there on the Tigon 1. 1482 */ 1483 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1484 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1485 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1486 if (sc->ti_hwrev == TI_HWREV_TIGON) 1487 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1488 else 1489 rcb->ti_flags = 0; 1490 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1491 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1492 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1493 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1494 if (VLAN_ATTACHED(&sc->ethercom)) 1495 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1496 1497 /* 1498 * Set up the receive return ring. 1499 */ 1500 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1501 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1502 rcb->ti_flags = 0; 1503 rcb->ti_max_len = TI_RETURN_RING_CNT; 1504 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1505 TI_CDRTNPRODADDR(sc); 1506 1507 /* 1508 * Set up the tx ring. Note: for the Tigon 2, we have the option 1509 * of putting the transmit ring in the host's address space and 1510 * letting the chip DMA it instead of leaving the ring in the NIC's 1511 * memory and accessing it through the shared memory region. We 1512 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1513 * so we have to revert to the shared memory scheme if we detect 1514 * a Tigon 1 chip. 1515 */ 1516 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1517 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1518 sc->ti_tx_ring_nic = 1519 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1520 } 1521 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1522 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1523 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1524 if (sc->ti_hwrev == TI_HWREV_TIGON) 1525 rcb->ti_flags = 0; 1526 else 1527 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1528 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) 1529 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1530 /* 1531 * When we get the packet, there is a pseudo-header seed already 1532 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1533 * compute the pseudo-header checksum again! 1534 */ 1535 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx)) 1536 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1537 TI_RCB_FLAG_NO_PHDR_CKSUM; 1538 if (VLAN_ATTACHED(&sc->ethercom)) 1539 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1540 rcb->ti_max_len = TI_TX_RING_CNT; 1541 if (sc->ti_hwrev == TI_HWREV_TIGON) 1542 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1543 else 1544 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1545 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1546 TI_CDTXCONSADDR(sc); 1547 1548 /* 1549 * We're done frobbing the General Information Block. Sync 1550 * it. Note we take care of the first stats sync here, as 1551 * well. 1552 */ 1553 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1554 1555 /* Set up tuneables */ 1556 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1557 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1558 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1559 (sc->ti_rx_coal_ticks / 10)); 1560 else 1561 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1562 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1563 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1564 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1565 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1566 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1567 1568 /* Turn interrupts on. */ 1569 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1570 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1571 1572 /* Start CPU. */ 1573 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT | TI_CPUSTATE_STEP)); 1574 1575 return (0); 1576 } 1577 1578 /* 1579 * look for id in the device list, returning the first match 1580 */ 1581 static const struct ti_type * 1582 ti_type_match(struct pci_attach_args *pa) 1583 { 1584 const struct ti_type *t; 1585 1586 t = ti_devs; 1587 while (t->ti_name != NULL) { 1588 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1589 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1590 return (t); 1591 } 1592 t++; 1593 } 1594 1595 return (NULL); 1596 } 1597 1598 /* 1599 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1600 * against our list and return its name if we find a match. 1601 */ 1602 static int 1603 ti_probe(device_t parent, cfdata_t match, void *aux) 1604 { 1605 struct pci_attach_args *pa = aux; 1606 const struct ti_type *t; 1607 1608 t = ti_type_match(pa); 1609 1610 return ((t == NULL) ? 0 : 1); 1611 } 1612 1613 static void 1614 ti_attach(device_t parent, device_t self, void *aux) 1615 { 1616 uint32_t command; 1617 struct ifnet *ifp; 1618 struct ti_softc *sc; 1619 uint8_t eaddr[ETHER_ADDR_LEN]; 1620 struct pci_attach_args *pa = aux; 1621 pci_chipset_tag_t pc = pa->pa_pc; 1622 pci_intr_handle_t ih; 1623 const char *intrstr = NULL; 1624 bus_dma_segment_t dmaseg; 1625 int error, dmanseg, nolinear; 1626 const struct ti_type *t; 1627 char intrbuf[PCI_INTRSTR_LEN]; 1628 1629 t = ti_type_match(pa); 1630 if (t == NULL) { 1631 aprint_error("ti_attach: were did the card go ?\n"); 1632 return; 1633 } 1634 1635 aprint_normal(": %s (rev. 0x%02x)\n", t->ti_name, 1636 PCI_REVISION(pa->pa_class)); 1637 1638 sc = device_private(self); 1639 sc->sc_dev = self; 1640 1641 /* 1642 * Map control/status registers. 1643 */ 1644 nolinear = 0; 1645 if (pci_mapreg_map(pa, 0x10, 1646 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1647 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1648 NULL, NULL)) { 1649 nolinear = 1; 1650 if (pci_mapreg_map(pa, 0x10, 1651 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1652 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1653 aprint_error_dev(self, "can't map memory space\n"); 1654 return; 1655 } 1656 } 1657 if (nolinear == 0) 1658 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1659 else 1660 sc->ti_vhandle = NULL; 1661 1662 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1663 command |= PCI_COMMAND_MASTER_ENABLE; 1664 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1665 1666 /* Allocate interrupt */ 1667 if (pci_intr_map(pa, &ih)) { 1668 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 1669 return; 1670 } 1671 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1672 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, ti_intr, sc, 1673 device_xname(self)); 1674 if (sc->sc_ih == NULL) { 1675 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 1676 if (intrstr != NULL) 1677 aprint_error(" at %s", intrstr); 1678 aprint_error("\n"); 1679 return; 1680 } 1681 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1682 1683 if (ti_chipinit(sc)) { 1684 aprint_error_dev(self, "chip initialization failed\n"); 1685 goto fail2; 1686 } 1687 1688 /* 1689 * Deal with some chip diffrences. 1690 */ 1691 switch (sc->ti_hwrev) { 1692 case TI_HWREV_TIGON: 1693 sc->sc_tx_encap = ti_encap_tigon1; 1694 sc->sc_tx_eof = ti_txeof_tigon1; 1695 if (nolinear == 1) 1696 aprint_error_dev(self, 1697 "memory space not mapped linear\n"); 1698 break; 1699 1700 case TI_HWREV_TIGON_II: 1701 sc->sc_tx_encap = ti_encap_tigon2; 1702 sc->sc_tx_eof = ti_txeof_tigon2; 1703 break; 1704 1705 default: 1706 aprint_error_dev(self, "Unknown chip version: %d\n", 1707 sc->ti_hwrev); 1708 goto fail2; 1709 } 1710 1711 /* Zero out the NIC's on-board SRAM. */ 1712 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1713 1714 /* Init again -- zeroing memory may have clobbered some registers. */ 1715 if (ti_chipinit(sc)) { 1716 aprint_error_dev(self, "chip initialization failed\n"); 1717 goto fail2; 1718 } 1719 1720 /* 1721 * Get station address from the EEPROM. Note: the manual states 1722 * that the MAC address is at offset 0x8c, however the data is 1723 * stored as two longwords (since that's how it's loaded into 1724 * the NIC). This means the MAC address is actually preceded 1725 * by two zero bytes. We need to skip over those. 1726 */ 1727 if (ti_read_eeprom(sc, (void *)&eaddr, 1728 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1729 aprint_error_dev(self, "failed to read station address\n"); 1730 goto fail2; 1731 } 1732 1733 /* 1734 * A Tigon chip was detected. Inform the world. 1735 */ 1736 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr)); 1737 1738 sc->sc_dmat = pa->pa_dmat; 1739 1740 /* Allocate the general information block and ring buffers. */ 1741 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1742 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1743 BUS_DMA_NOWAIT)) != 0) { 1744 aprint_error_dev(self, 1745 "can't allocate ring buffer, error = %d\n", error); 1746 goto fail2; 1747 } 1748 1749 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1750 sizeof(struct ti_ring_data), (void **)&sc->ti_rdata, 1751 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 1752 aprint_error_dev(self, 1753 "can't map ring buffer, error = %d\n", error); 1754 goto fail2; 1755 } 1756 1757 if ((error = bus_dmamap_create(sc->sc_dmat, 1758 sizeof(struct ti_ring_data), 1, 1759 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1760 &sc->info_dmamap)) != 0) { 1761 aprint_error_dev(self, 1762 "can't create ring buffer DMA map, error = %d\n", error); 1763 goto fail2; 1764 } 1765 1766 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1767 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1768 BUS_DMA_NOWAIT)) != 0) { 1769 aprint_error_dev(self, 1770 "can't load ring buffer DMA map, error = %d\n", error); 1771 goto fail2; 1772 } 1773 1774 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1775 1776 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1777 1778 /* Try to allocate memory for jumbo buffers. */ 1779 if (ti_alloc_jumbo_mem(sc)) { 1780 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 1781 goto fail2; 1782 } 1783 1784 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1785 1786 /* 1787 * We really need a better way to tell a 1000baseT card 1788 * from a 1000baseSX one, since in theory there could be 1789 * OEMed 1000baseT cards from lame vendors who aren't 1790 * clever enough to change the PCI ID. For the moment 1791 * though, the AceNIC is the only copper card available. 1792 */ 1793 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1794 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1795 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1796 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1797 sc->ti_copper = 1; 1798 else 1799 sc->ti_copper = 0; 1800 1801 /* Set default tuneable values. */ 1802 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1803 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1804 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1805 sc->ti_rx_max_coal_bds = 64; 1806 sc->ti_tx_max_coal_bds = 128; 1807 sc->ti_tx_buf_ratio = 21; 1808 1809 /* Set up ifnet structure */ 1810 ifp = &sc->ethercom.ec_if; 1811 ifp->if_softc = sc; 1812 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1813 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1814 ifp->if_ioctl = ti_ioctl; 1815 ifp->if_start = ti_start; 1816 ifp->if_watchdog = ti_watchdog; 1817 IFQ_SET_READY(&ifp->if_snd); 1818 1819 #if 0 1820 /* 1821 * XXX This is not really correct -- we don't necessarily 1822 * XXX want to queue up as many as we can transmit at the 1823 * XXX upper layer like that. Someone with a board should 1824 * XXX check to see how this affects performance. 1825 */ 1826 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1827 #endif 1828 1829 /* 1830 * We can support 802.1Q VLAN-sized frames. 1831 */ 1832 sc->ethercom.ec_capabilities |= 1833 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1834 1835 /* 1836 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1837 */ 1838 ifp->if_capabilities |= 1839 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1840 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1841 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1842 1843 /* Set up ifmedia support. */ 1844 sc->ethercom.ec_ifmedia = &sc->ifmedia; 1845 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1846 if (sc->ti_copper) { 1847 /* 1848 * Copper cards allow manual 10/100 mode selection, 1849 * but not manual 1000baseT mode selection. Why? 1850 * Because currently there's no way to specify the 1851 * master/slave setting through the firmware interface, 1852 * so Alteon decided to just bag it and handle it 1853 * via autonegotiation. 1854 */ 1855 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 1856 ifmedia_add(&sc->ifmedia, 1857 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1858 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 1859 ifmedia_add(&sc->ifmedia, 1860 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1861 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 1862 ifmedia_add(&sc->ifmedia, 1863 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1864 } else { 1865 /* Fiber cards don't support 10/100 modes. */ 1866 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 1867 ifmedia_add(&sc->ifmedia, 1868 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 1869 } 1870 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1871 ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_AUTO); 1872 1873 /* 1874 * Call MI attach routines. 1875 */ 1876 if_attach(ifp); 1877 if_deferred_start_init(ifp, NULL); 1878 ether_ifattach(ifp, eaddr); 1879 1880 /* 1881 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1882 * doing do could allow DMA to corrupt kernel memory during the 1883 * reboot before the driver initializes. 1884 */ 1885 if (pmf_device_register1(self, NULL, NULL, ti_shutdown)) 1886 pmf_class_network_register(self, ifp); 1887 else 1888 aprint_error_dev(self, "couldn't establish power handler\n"); 1889 1890 return; 1891 fail2: 1892 pci_intr_disestablish(pc, sc->sc_ih); 1893 return; 1894 } 1895 1896 /* 1897 * Frame reception handling. This is called if there's a frame 1898 * on the receive return list. 1899 * 1900 * Note: we have to be able to handle three possibilities here: 1901 * 1) the frame is from the mini receive ring (can only happen) 1902 * on Tigon 2 boards) 1903 * 2) the frame is from the jumbo receive ring 1904 * 3) the frame is from the standard receive ring 1905 */ 1906 1907 static void 1908 ti_rxeof(struct ti_softc *sc) 1909 { 1910 struct ifnet *ifp; 1911 struct ti_cmd_desc cmd; 1912 1913 ifp = &sc->ethercom.ec_if; 1914 1915 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1916 struct ti_rx_desc *cur_rx; 1917 uint32_t rxidx; 1918 struct mbuf *m = NULL; 1919 struct ether_header *eh; 1920 bus_dmamap_t dmamap; 1921 1922 cur_rx = 1923 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1924 rxidx = cur_rx->ti_idx; 1925 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1926 1927 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1928 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1929 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1930 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1931 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1932 ifp->if_ierrors++; 1933 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1934 continue; 1935 } 1936 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1937 == ENOBUFS) { 1938 ifp->if_ierrors++; 1939 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1940 continue; 1941 } 1942 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1943 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1944 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1945 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1946 dmamap = sc->mini_dmamap[rxidx]; 1947 sc->mini_dmamap[rxidx] = 0; 1948 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1949 ifp->if_ierrors++; 1950 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1951 continue; 1952 } 1953 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1954 == ENOBUFS) { 1955 ifp->if_ierrors++; 1956 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1957 continue; 1958 } 1959 } else { 1960 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1961 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1962 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1963 dmamap = sc->std_dmamap[rxidx]; 1964 sc->std_dmamap[rxidx] = 0; 1965 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1966 ifp->if_ierrors++; 1967 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1968 continue; 1969 } 1970 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 1971 == ENOBUFS) { 1972 ifp->if_ierrors++; 1973 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1974 continue; 1975 } 1976 } 1977 1978 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1979 m_set_rcvif(m, ifp); 1980 1981 eh = mtod(m, struct ether_header *); 1982 switch (ntohs(eh->ether_type)) { 1983 #ifdef INET 1984 case ETHERTYPE_IP: 1985 { 1986 struct ip *ip = (struct ip *) (eh + 1); 1987 1988 /* 1989 * Note the Tigon firmware does not invert 1990 * the checksum for us, hence the XOR. 1991 */ 1992 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1993 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 1994 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1995 /* 1996 * ntohs() the constant so the compiler can 1997 * optimize... 1998 * 1999 * XXX Figure out a sane way to deal with 2000 * fragmented packets. 2001 */ 2002 if ((ip->ip_off & htons(IP_MF | IP_OFFMASK)) == 0) { 2003 switch (ip->ip_p) { 2004 case IPPROTO_TCP: 2005 m->m_pkthdr.csum_data = 2006 cur_rx->ti_tcp_udp_cksum; 2007 m->m_pkthdr.csum_flags |= 2008 M_CSUM_TCPv4 | M_CSUM_DATA; 2009 break; 2010 case IPPROTO_UDP: 2011 m->m_pkthdr.csum_data = 2012 cur_rx->ti_tcp_udp_cksum; 2013 m->m_pkthdr.csum_flags |= 2014 M_CSUM_UDPv4 | M_CSUM_DATA; 2015 break; 2016 default: 2017 /* Nothing */; 2018 } 2019 } 2020 break; 2021 } 2022 #endif 2023 default: 2024 /* Nothing. */ 2025 break; 2026 } 2027 2028 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2029 /* ti_vlan_tag also has the priority, trim it */ 2030 vlan_set_tag(m, cur_rx->ti_vlan_tag & 0x0fff); 2031 } 2032 2033 if_percpuq_enqueue(ifp->if_percpuq, m); 2034 } 2035 2036 /* Only necessary on the Tigon 1. */ 2037 if (sc->ti_hwrev == TI_HWREV_TIGON) 2038 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2039 sc->ti_rx_saved_considx); 2040 2041 TI_UPDATE_STDPROD(sc, sc->ti_std); 2042 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2043 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2044 } 2045 2046 static void 2047 ti_txeof_tigon1(struct ti_softc *sc) 2048 { 2049 struct ti_tx_desc *cur_tx = NULL; 2050 struct ifnet *ifp; 2051 struct txdmamap_pool_entry *dma; 2052 2053 ifp = &sc->ethercom.ec_if; 2054 2055 /* 2056 * Go through our tx ring and free mbufs for those 2057 * frames that have been sent. 2058 */ 2059 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2060 uint32_t idx = 0; 2061 2062 idx = sc->ti_tx_saved_considx; 2063 if (idx > 383) 2064 CSR_WRITE_4(sc, TI_WINBASE, 2065 TI_TX_RING_BASE + 6144); 2066 else if (idx > 255) 2067 CSR_WRITE_4(sc, TI_WINBASE, 2068 TI_TX_RING_BASE + 4096); 2069 else if (idx > 127) 2070 CSR_WRITE_4(sc, TI_WINBASE, 2071 TI_TX_RING_BASE + 2048); 2072 else 2073 CSR_WRITE_4(sc, TI_WINBASE, 2074 TI_TX_RING_BASE); 2075 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2076 if (cur_tx->ti_flags & TI_BDFLAG_END) 2077 ifp->if_opackets++; 2078 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2079 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2080 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2081 2082 dma = sc->txdma[idx]; 2083 KDASSERT(dma != NULL); 2084 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2085 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2086 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2087 2088 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2089 sc->txdma[idx] = NULL; 2090 } 2091 sc->ti_txcnt--; 2092 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2093 ifp->if_timer = 0; 2094 } 2095 2096 if (cur_tx != NULL) 2097 ifp->if_flags &= ~IFF_OACTIVE; 2098 } 2099 2100 static void 2101 ti_txeof_tigon2(struct ti_softc *sc) 2102 { 2103 struct ti_tx_desc *cur_tx = NULL; 2104 struct ifnet *ifp; 2105 struct txdmamap_pool_entry *dma; 2106 int firstidx, cnt; 2107 2108 ifp = &sc->ethercom.ec_if; 2109 2110 /* 2111 * Go through our tx ring and free mbufs for those 2112 * frames that have been sent. 2113 */ 2114 firstidx = sc->ti_tx_saved_considx; 2115 cnt = 0; 2116 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2117 uint32_t idx = 0; 2118 2119 idx = sc->ti_tx_saved_considx; 2120 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2121 if (cur_tx->ti_flags & TI_BDFLAG_END) 2122 ifp->if_opackets++; 2123 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2124 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2125 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2126 2127 dma = sc->txdma[idx]; 2128 KDASSERT(dma != NULL); 2129 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2130 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2131 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2132 2133 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2134 sc->txdma[idx] = NULL; 2135 } 2136 cnt++; 2137 sc->ti_txcnt--; 2138 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2139 ifp->if_timer = 0; 2140 } 2141 2142 if (cnt != 0) 2143 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2144 2145 if (cur_tx != NULL) 2146 ifp->if_flags &= ~IFF_OACTIVE; 2147 } 2148 2149 static int 2150 ti_intr(void *xsc) 2151 { 2152 struct ti_softc *sc; 2153 struct ifnet *ifp; 2154 2155 sc = xsc; 2156 ifp = &sc->ethercom.ec_if; 2157 2158 #ifdef notdef 2159 /* Avoid this for now -- checking this register is expensive. */ 2160 /* Make sure this is really our interrupt. */ 2161 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2162 return (0); 2163 #endif 2164 2165 /* Ack interrupt and stop others from occurring. */ 2166 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2167 2168 if (ifp->if_flags & IFF_RUNNING) { 2169 /* Check RX return ring producer/consumer */ 2170 ti_rxeof(sc); 2171 2172 /* Check TX ring producer/consumer */ 2173 (*sc->sc_tx_eof)(sc); 2174 } 2175 2176 ti_handle_events(sc); 2177 2178 /* Re-enable interrupts. */ 2179 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2180 2181 if ((ifp->if_flags & IFF_RUNNING) != 0) 2182 if_schedule_deferred_start(ifp); 2183 2184 return (1); 2185 } 2186 2187 static void 2188 ti_stats_update(struct ti_softc *sc) 2189 { 2190 struct ifnet *ifp; 2191 2192 ifp = &sc->ethercom.ec_if; 2193 2194 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2195 2196 ifp->if_collisions += 2197 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2198 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2199 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2200 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2201 ifp->if_collisions; 2202 2203 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2204 } 2205 2206 /* 2207 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2208 * pointers to descriptors. 2209 */ 2210 static int 2211 ti_encap_tigon1(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx) 2212 { 2213 struct ti_tx_desc *f = NULL; 2214 uint32_t frag, cur, cnt = 0; 2215 struct txdmamap_pool_entry *dma; 2216 bus_dmamap_t dmamap; 2217 int error, i; 2218 uint16_t csum_flags = 0; 2219 2220 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2221 if (dma == NULL) { 2222 return ENOMEM; 2223 } 2224 dmamap = dma->dmamap; 2225 2226 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2227 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2228 if (error) { 2229 struct mbuf *m; 2230 int j = 0; 2231 for (m = m_head; m; m = m->m_next) 2232 j++; 2233 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2234 "error %d\n", m_head->m_pkthdr.len, j, error); 2235 return (ENOMEM); 2236 } 2237 2238 cur = frag = *txidx; 2239 2240 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2241 /* IP header checksum field must be 0! */ 2242 csum_flags |= TI_BDFLAG_IP_CKSUM; 2243 } 2244 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 2245 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2246 2247 /* XXX fragmented packet checksum capability? */ 2248 2249 /* 2250 * Start packing the mbufs in this chain into 2251 * the fragment pointers. Stop when we run out 2252 * of fragments or hit the end of the mbuf chain. 2253 */ 2254 for (i = 0; i < dmamap->dm_nsegs; i++) { 2255 if (frag > 383) 2256 CSR_WRITE_4(sc, TI_WINBASE, 2257 TI_TX_RING_BASE + 6144); 2258 else if (frag > 255) 2259 CSR_WRITE_4(sc, TI_WINBASE, 2260 TI_TX_RING_BASE + 4096); 2261 else if (frag > 127) 2262 CSR_WRITE_4(sc, TI_WINBASE, 2263 TI_TX_RING_BASE + 2048); 2264 else 2265 CSR_WRITE_4(sc, TI_WINBASE, 2266 TI_TX_RING_BASE); 2267 f = &sc->ti_tx_ring_nic[frag % 128]; 2268 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2269 break; 2270 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2271 f->ti_len = dmamap->dm_segs[i].ds_len; 2272 f->ti_flags = csum_flags; 2273 if (vlan_has_tag(m_head)) { 2274 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2275 f->ti_vlan_tag = vlan_get_tag(m_head); 2276 } else { 2277 f->ti_vlan_tag = 0; 2278 } 2279 /* 2280 * Sanity check: avoid coming within 16 descriptors 2281 * of the end of the ring. 2282 */ 2283 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2284 return (ENOBUFS); 2285 cur = frag; 2286 TI_INC(frag, TI_TX_RING_CNT); 2287 cnt++; 2288 } 2289 2290 if (i < dmamap->dm_nsegs) 2291 return (ENOBUFS); 2292 2293 if (frag == sc->ti_tx_saved_considx) 2294 return (ENOBUFS); 2295 2296 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2297 TI_BDFLAG_END; 2298 2299 /* Sync the packet's DMA map. */ 2300 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2301 BUS_DMASYNC_PREWRITE); 2302 2303 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2304 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2305 sc->txdma[cur] = dma; 2306 sc->ti_txcnt += cnt; 2307 2308 *txidx = frag; 2309 2310 return (0); 2311 } 2312 2313 static int 2314 ti_encap_tigon2(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx) 2315 { 2316 struct ti_tx_desc *f = NULL; 2317 uint32_t frag, firstfrag, cur, cnt = 0; 2318 struct txdmamap_pool_entry *dma; 2319 bus_dmamap_t dmamap; 2320 int error, i; 2321 uint16_t csum_flags = 0; 2322 2323 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2324 if (dma == NULL) { 2325 return ENOMEM; 2326 } 2327 dmamap = dma->dmamap; 2328 2329 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2330 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2331 if (error) { 2332 struct mbuf *m; 2333 int j = 0; 2334 for (m = m_head; m; m = m->m_next) 2335 j++; 2336 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2337 "error %d\n", m_head->m_pkthdr.len, j, error); 2338 return (ENOMEM); 2339 } 2340 2341 cur = firstfrag = frag = *txidx; 2342 2343 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2344 /* IP header checksum field must be 0! */ 2345 csum_flags |= TI_BDFLAG_IP_CKSUM; 2346 } 2347 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 2348 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2349 2350 /* XXX fragmented packet checksum capability? */ 2351 2352 /* 2353 * Start packing the mbufs in this chain into 2354 * the fragment pointers. Stop when we run out 2355 * of fragments or hit the end of the mbuf chain. 2356 */ 2357 for (i = 0; i < dmamap->dm_nsegs; i++) { 2358 f = &sc->ti_rdata->ti_tx_ring[frag]; 2359 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2360 break; 2361 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2362 f->ti_len = dmamap->dm_segs[i].ds_len; 2363 f->ti_flags = csum_flags; 2364 if (vlan_has_tag(m_head)) { 2365 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2366 f->ti_vlan_tag = vlan_get_tag(m_head); 2367 } else { 2368 f->ti_vlan_tag = 0; 2369 } 2370 /* 2371 * Sanity check: avoid coming within 16 descriptors 2372 * of the end of the ring. 2373 */ 2374 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2375 return (ENOBUFS); 2376 cur = frag; 2377 TI_INC(frag, TI_TX_RING_CNT); 2378 cnt++; 2379 } 2380 2381 if (i < dmamap->dm_nsegs) 2382 return (ENOBUFS); 2383 2384 if (frag == sc->ti_tx_saved_considx) 2385 return (ENOBUFS); 2386 2387 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2388 2389 /* Sync the packet's DMA map. */ 2390 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2391 BUS_DMASYNC_PREWRITE); 2392 2393 /* Sync the descriptors we are using. */ 2394 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2395 2396 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2397 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2398 sc->txdma[cur] = dma; 2399 sc->ti_txcnt += cnt; 2400 2401 *txidx = frag; 2402 2403 return (0); 2404 } 2405 2406 /* 2407 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2408 * to the mbuf data regions directly in the transmit descriptors. 2409 */ 2410 static void 2411 ti_start(struct ifnet *ifp) 2412 { 2413 struct ti_softc *sc; 2414 struct mbuf *m_head = NULL; 2415 uint32_t prodidx = 0; 2416 2417 sc = ifp->if_softc; 2418 2419 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2420 2421 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2422 IFQ_POLL(&ifp->if_snd, m_head); 2423 if (m_head == NULL) 2424 break; 2425 2426 /* 2427 * Pack the data into the transmit ring. If we 2428 * don't have room, set the OACTIVE flag and wait 2429 * for the NIC to drain the ring. 2430 */ 2431 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2432 ifp->if_flags |= IFF_OACTIVE; 2433 break; 2434 } 2435 2436 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2437 2438 /* 2439 * If there's a BPF listener, bounce a copy of this frame 2440 * to him. 2441 */ 2442 bpf_mtap(ifp, m_head, BPF_D_OUT); 2443 } 2444 2445 /* Transmit */ 2446 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2447 2448 /* Set a timeout in case the chip goes out to lunch. */ 2449 ifp->if_timer = 5; 2450 } 2451 2452 static void 2453 ti_init(void *xsc) 2454 { 2455 struct ti_softc *sc = xsc; 2456 int s; 2457 2458 s = splnet(); 2459 2460 /* Cancel pending I/O and flush buffers. */ 2461 ti_stop(sc); 2462 2463 /* Init the gen info block, ring control blocks and firmware. */ 2464 if (ti_gibinit(sc)) { 2465 aprint_error_dev(sc->sc_dev, "initialization failure\n"); 2466 splx(s); 2467 return; 2468 } 2469 2470 splx(s); 2471 } 2472 2473 static void 2474 ti_init2(struct ti_softc *sc) 2475 { 2476 struct ti_cmd_desc cmd; 2477 struct ifnet *ifp; 2478 const uint8_t *m; 2479 struct ifmedia *ifm; 2480 int tmp; 2481 2482 ifp = &sc->ethercom.ec_if; 2483 2484 /* Specify MTU and interface index. */ 2485 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_unit(sc->sc_dev)); /* ??? */ 2486 2487 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2488 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2489 tmp += ETHER_VLAN_ENCAP_LEN; 2490 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2491 2492 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2493 2494 /* Load our MAC address. */ 2495 m = (const uint8_t *)CLLADDR(ifp->if_sadl); 2496 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2497 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2498 | (m[4] << 8) | m[5]); 2499 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2500 2501 /* Enable or disable promiscuous mode as needed. */ 2502 if (ifp->if_flags & IFF_PROMISC) { 2503 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2504 } else { 2505 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2506 } 2507 2508 /* Program multicast filter. */ 2509 ti_setmulti(sc); 2510 2511 /* 2512 * If this is a Tigon 1, we should tell the 2513 * firmware to use software packet filtering. 2514 */ 2515 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2516 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2517 } 2518 2519 /* Init RX ring. */ 2520 ti_init_rx_ring_std(sc); 2521 2522 /* Init jumbo RX ring. */ 2523 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2524 ti_init_rx_ring_jumbo(sc); 2525 2526 /* 2527 * If this is a Tigon 2, we can also configure the 2528 * mini ring. 2529 */ 2530 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2531 ti_init_rx_ring_mini(sc); 2532 2533 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2534 sc->ti_rx_saved_considx = 0; 2535 2536 /* Init TX ring. */ 2537 ti_init_tx_ring(sc); 2538 2539 /* Tell firmware we're alive. */ 2540 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2541 2542 /* Enable host interrupts. */ 2543 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2544 2545 ifp->if_flags |= IFF_RUNNING; 2546 ifp->if_flags &= ~IFF_OACTIVE; 2547 2548 /* 2549 * Make sure to set media properly. We have to do this 2550 * here since we have to issue commands in order to set 2551 * the link negotiation and we can't issue commands until 2552 * the firmware is running. 2553 */ 2554 ifm = &sc->ifmedia; 2555 tmp = ifm->ifm_media; 2556 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2557 ti_ifmedia_upd(ifp); 2558 ifm->ifm_media = tmp; 2559 } 2560 2561 /* 2562 * Set media options. 2563 */ 2564 static int 2565 ti_ifmedia_upd(struct ifnet *ifp) 2566 { 2567 struct ti_softc *sc; 2568 struct ifmedia *ifm; 2569 struct ti_cmd_desc cmd; 2570 2571 sc = ifp->if_softc; 2572 ifm = &sc->ifmedia; 2573 2574 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2575 return (EINVAL); 2576 2577 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2578 case IFM_AUTO: 2579 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF | TI_GLNK_1000MB | 2580 TI_GLNK_FULL_DUPLEX | TI_GLNK_RX_FLOWCTL_Y | 2581 TI_GLNK_AUTONEGENB | TI_GLNK_ENB); 2582 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB | TI_LNK_10MB | 2583 TI_LNK_FULL_DUPLEX | TI_LNK_HALF_DUPLEX | 2584 TI_LNK_AUTONEGENB | TI_LNK_ENB); 2585 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2586 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2587 break; 2588 case IFM_1000_SX: 2589 case IFM_1000_T: 2590 if ((ifm->ifm_media & IFM_FDX) != 0) { 2591 CSR_WRITE_4(sc, TI_GCR_GLINK, 2592 TI_GLNK_PREF | TI_GLNK_1000MB | TI_GLNK_FULL_DUPLEX 2593 | TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB); 2594 } else { 2595 CSR_WRITE_4(sc, TI_GCR_GLINK, 2596 TI_GLNK_PREF | TI_GLNK_1000MB | 2597 TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB); 2598 } 2599 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2600 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2601 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2602 break; 2603 case IFM_100_FX: 2604 case IFM_10_FL: 2605 case IFM_100_TX: 2606 case IFM_10_T: 2607 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2608 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB | TI_LNK_PREF); 2609 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2610 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2611 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2612 } else { 2613 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2614 } 2615 if ((ifm->ifm_media & IFM_FDX) != 0) { 2616 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2617 } else { 2618 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2619 } 2620 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2621 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2622 break; 2623 } 2624 2625 sc->ethercom.ec_if.if_baudrate = 2626 ifmedia_baudrate(ifm->ifm_media); 2627 2628 return (0); 2629 } 2630 2631 /* 2632 * Report current media status. 2633 */ 2634 static void 2635 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2636 { 2637 struct ti_softc *sc; 2638 uint32_t media = 0; 2639 2640 sc = ifp->if_softc; 2641 2642 ifmr->ifm_status = IFM_AVALID; 2643 ifmr->ifm_active = IFM_ETHER; 2644 2645 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2646 return; 2647 2648 ifmr->ifm_status |= IFM_ACTIVE; 2649 2650 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2651 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2652 if (sc->ti_copper) 2653 ifmr->ifm_active |= IFM_1000_T; 2654 else 2655 ifmr->ifm_active |= IFM_1000_SX; 2656 if (media & TI_GLNK_FULL_DUPLEX) 2657 ifmr->ifm_active |= IFM_FDX; 2658 else 2659 ifmr->ifm_active |= IFM_HDX; 2660 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2661 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2662 if (sc->ti_copper) { 2663 if (media & TI_LNK_100MB) 2664 ifmr->ifm_active |= IFM_100_TX; 2665 if (media & TI_LNK_10MB) 2666 ifmr->ifm_active |= IFM_10_T; 2667 } else { 2668 if (media & TI_LNK_100MB) 2669 ifmr->ifm_active |= IFM_100_FX; 2670 if (media & TI_LNK_10MB) 2671 ifmr->ifm_active |= IFM_10_FL; 2672 } 2673 if (media & TI_LNK_FULL_DUPLEX) 2674 ifmr->ifm_active |= IFM_FDX; 2675 if (media & TI_LNK_HALF_DUPLEX) 2676 ifmr->ifm_active |= IFM_HDX; 2677 } 2678 2679 sc->ethercom.ec_if.if_baudrate = 2680 ifmedia_baudrate(sc->ifmedia.ifm_media); 2681 } 2682 2683 static int 2684 ti_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2685 { 2686 struct ifaddr *ifa = (struct ifaddr *) data; 2687 struct ti_softc *sc = ifp->if_softc; 2688 2689 if ((ifp->if_flags & IFF_UP) == 0) { 2690 ifp->if_flags |= IFF_UP; 2691 ti_init(sc); 2692 } 2693 2694 switch (cmd) { 2695 case SIOCINITIFADDR: 2696 2697 switch (ifa->ifa_addr->sa_family) { 2698 #ifdef INET 2699 case AF_INET: 2700 arp_ifinit(ifp, ifa); 2701 break; 2702 #endif 2703 default: 2704 break; 2705 } 2706 break; 2707 2708 default: 2709 return (EINVAL); 2710 } 2711 2712 return (0); 2713 } 2714 2715 static int 2716 ti_ioctl(struct ifnet *ifp, u_long command, void *data) 2717 { 2718 struct ti_softc *sc = ifp->if_softc; 2719 struct ifreq *ifr = (struct ifreq *) data; 2720 int s, error = 0; 2721 struct ti_cmd_desc cmd; 2722 2723 s = splnet(); 2724 2725 switch (command) { 2726 case SIOCINITIFADDR: 2727 error = ti_ether_ioctl(ifp, command, data); 2728 break; 2729 case SIOCSIFMTU: 2730 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 2731 error = EINVAL; 2732 else if ((error = ifioctl_common(ifp, command, data)) 2733 == ENETRESET) { 2734 ti_init(sc); 2735 error = 0; 2736 } 2737 break; 2738 case SIOCSIFFLAGS: 2739 if ((error = ifioctl_common(ifp, command, data)) != 0) 2740 break; 2741 if (ifp->if_flags & IFF_UP) { 2742 /* 2743 * If only the state of the PROMISC flag changed, 2744 * then just use the 'set promisc mode' command 2745 * instead of reinitializing the entire NIC. Doing 2746 * a full re-init means reloading the firmware and 2747 * waiting for it to start up, which may take a 2748 * second or two. 2749 */ 2750 if (ifp->if_flags & IFF_RUNNING && 2751 ifp->if_flags & IFF_PROMISC && 2752 !(sc->ti_if_flags & IFF_PROMISC)) { 2753 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2754 TI_CMD_CODE_PROMISC_ENB, 0); 2755 } else if (ifp->if_flags & IFF_RUNNING && 2756 !(ifp->if_flags & IFF_PROMISC) && 2757 sc->ti_if_flags & IFF_PROMISC) { 2758 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2759 TI_CMD_CODE_PROMISC_DIS, 0); 2760 } else 2761 ti_init(sc); 2762 } else { 2763 if (ifp->if_flags & IFF_RUNNING) { 2764 ti_stop(sc); 2765 } 2766 } 2767 sc->ti_if_flags = ifp->if_flags; 2768 error = 0; 2769 break; 2770 default: 2771 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 2772 break; 2773 2774 error = 0; 2775 2776 if (command == SIOCSIFCAP) 2777 ti_init(sc); 2778 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 2779 ; 2780 else if (ifp->if_flags & IFF_RUNNING) 2781 ti_setmulti(sc); 2782 break; 2783 } 2784 2785 (void)splx(s); 2786 2787 return (error); 2788 } 2789 2790 static void 2791 ti_watchdog(struct ifnet *ifp) 2792 { 2793 struct ti_softc *sc; 2794 2795 sc = ifp->if_softc; 2796 2797 aprint_error_dev(sc->sc_dev, "watchdog timeout -- resetting\n"); 2798 ti_stop(sc); 2799 ti_init(sc); 2800 2801 ifp->if_oerrors++; 2802 } 2803 2804 /* 2805 * Stop the adapter and free any mbufs allocated to the 2806 * RX and TX lists. 2807 */ 2808 static void 2809 ti_stop(struct ti_softc *sc) 2810 { 2811 struct ifnet *ifp; 2812 struct ti_cmd_desc cmd; 2813 2814 ifp = &sc->ethercom.ec_if; 2815 2816 /* Disable host interrupts. */ 2817 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2818 /* 2819 * Tell firmware we're shutting down. 2820 */ 2821 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2822 2823 /* Halt and reinitialize. */ 2824 ti_chipinit(sc); 2825 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2826 ti_chipinit(sc); 2827 2828 /* Free the RX lists. */ 2829 ti_free_rx_ring_std(sc); 2830 2831 /* Free jumbo RX list. */ 2832 ti_free_rx_ring_jumbo(sc); 2833 2834 /* Free mini RX list. */ 2835 ti_free_rx_ring_mini(sc); 2836 2837 /* Free TX buffers. */ 2838 ti_free_tx_ring(sc); 2839 2840 sc->ti_ev_prodidx.ti_idx = 0; 2841 sc->ti_return_prodidx.ti_idx = 0; 2842 sc->ti_tx_considx.ti_idx = 0; 2843 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2844 2845 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2846 } 2847 2848 /* 2849 * Stop all chip I/O so that the kernel's probe routines don't 2850 * get confused by errant DMAs when rebooting. 2851 */ 2852 static bool 2853 ti_shutdown(device_t self, int howto) 2854 { 2855 struct ti_softc *sc; 2856 2857 sc = device_private(self); 2858 ti_chipinit(sc); 2859 2860 return true; 2861 } 2862
Indexes created Fri Sep 26 20:09:58 GMT 2025