if_ti.c revision 1.115
1 /* $NetBSD: if_ti.c,v 1.115 2020/02/29 18:49:53 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.115 2020/02/29 18:49:53 thorpej Exp $"); 85 86 #include "opt_inet.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/queue.h> 96 #include <sys/device.h> 97 #include <sys/reboot.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/if_ether.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #include <netinet/in_systm.h> 111 #include <netinet/ip.h> 112 #endif 113 114 115 #include <sys/bus.h> 116 117 #include <dev/pci/pcireg.h> 118 #include <dev/pci/pcivar.h> 119 #include <dev/pci/pcidevs.h> 120 121 #include <dev/pci/if_tireg.h> 122 123 #include <dev/microcode/tigon/ti_fw.h> 124 #include <dev/microcode/tigon/ti_fw2.h> 125 126 #define TI_HOSTADDR(x, y) \ 127 do { \ 128 (x).ti_addr_lo = (uint32_t)(y); \ 129 if (sizeof(bus_addr_t) == 8) \ 130 (x).ti_addr_hi = \ 131 (uint32_t)(((uint64_t)(y) >> 32)); \ 132 else \ 133 (x).ti_addr_hi = 0; \ 134 } while (/*CONSTCOND*/0) 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 140 static const struct ti_type ti_devs[] = { 141 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 142 "Alteon AceNIC 1000BASE-SX Ethernet" }, 143 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 144 "Alteon AceNIC 1000BASE-T Ethernet" }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 146 "3Com 3c985-SX Gigabit Ethernet" }, 147 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 148 "Netgear GA620 1000BASE-SX Ethernet" }, 149 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 150 "Netgear GA620 1000BASE-T Ethernet" }, 151 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 152 "Silicon Graphics Gigabit Ethernet" }, 153 { 0, 0, NULL } 154 }; 155 156 static const struct ti_type *ti_type_match(struct pci_attach_args *); 157 static int ti_probe(device_t, cfdata_t, void *); 158 static void ti_attach(device_t, device_t, void *); 159 static bool ti_shutdown(device_t, int); 160 static void ti_txeof_tigon1(struct ti_softc *); 161 static void ti_txeof_tigon2(struct ti_softc *); 162 static void ti_rxeof(struct ti_softc *); 163 164 static void ti_stats_update(struct ti_softc *); 165 static int ti_encap_tigon1(struct ti_softc *, struct mbuf *, uint32_t *); 166 static int ti_encap_tigon2(struct ti_softc *, struct mbuf *, uint32_t *); 167 168 static int ti_intr(void *); 169 static void ti_start(struct ifnet *); 170 static int ti_ioctl(struct ifnet *, u_long, void *); 171 static void ti_init(void *); 172 static void ti_init2(struct ti_softc *); 173 static void ti_stop(struct ti_softc *); 174 static void ti_watchdog(struct ifnet *); 175 static int ti_ifmedia_upd(struct ifnet *); 176 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 177 178 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 179 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 180 static int ti_read_eeprom(struct ti_softc *, void *, int, int); 181 182 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 183 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 184 static void ti_setmulti(struct ti_softc *); 185 186 static void ti_mem(struct ti_softc *, uint32_t, uint32_t, const void *); 187 static void ti_loadfw(struct ti_softc *); 188 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 189 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, void *, int); 190 static void ti_handle_events(struct ti_softc *); 191 static int ti_alloc_jumbo_mem(struct ti_softc *); 192 static void *ti_jalloc(struct ti_softc *); 193 static void ti_jfree(struct mbuf *, void *, size_t, void *); 194 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 195 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 196 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 197 static int ti_init_rx_ring_std(struct ti_softc *); 198 static void ti_free_rx_ring_std(struct ti_softc *); 199 static int ti_init_rx_ring_jumbo(struct ti_softc *); 200 static void ti_free_rx_ring_jumbo(struct ti_softc *); 201 static int ti_init_rx_ring_mini(struct ti_softc *); 202 static void ti_free_rx_ring_mini(struct ti_softc *); 203 static void ti_free_tx_ring(struct ti_softc *); 204 static int ti_init_tx_ring(struct ti_softc *); 205 206 static int ti_64bitslot_war(struct ti_softc *); 207 static int ti_chipinit(struct ti_softc *); 208 static int ti_gibinit(struct ti_softc *); 209 210 static int ti_ether_ioctl(struct ifnet *, u_long, void *); 211 212 CFATTACH_DECL_NEW(ti, sizeof(struct ti_softc), 213 ti_probe, ti_attach, NULL, NULL); 214 215 /* 216 * Send an instruction or address to the EEPROM, check for ACK. 217 */ 218 static uint32_t 219 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 220 { 221 int i, ack = 0; 222 223 /* 224 * Make sure we're in TX mode. 225 */ 226 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 227 228 /* 229 * Feed in each bit and stobe the clock. 230 */ 231 for (i = 0x80; i; i >>= 1) { 232 if (byte & i) { 233 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 234 } else { 235 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 236 } 237 DELAY(1); 238 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 239 DELAY(1); 240 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 241 } 242 243 /* 244 * Turn off TX mode. 245 */ 246 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 247 248 /* 249 * Check for ack. 250 */ 251 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 252 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 253 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 254 255 return (ack); 256 } 257 258 /* 259 * Read a byte of data stored in the EEPROM at address 'addr.' 260 * We have to send two address bytes since the EEPROM can hold 261 * more than 256 bytes of data. 262 */ 263 static uint8_t 264 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 265 { 266 int i; 267 uint8_t byte = 0; 268 269 EEPROM_START(); 270 271 /* 272 * Send write control code to EEPROM. 273 */ 274 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 275 printf("%s: failed to send write command, status: %x\n", 276 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 277 return (1); 278 } 279 280 /* 281 * Send first byte of address of byte we want to read. 282 */ 283 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 284 printf("%s: failed to send address, status: %x\n", 285 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 286 return (1); 287 } 288 /* 289 * Send second byte address of byte we want to read. 290 */ 291 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 292 printf("%s: failed to send address, status: %x\n", 293 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 294 return (1); 295 } 296 297 EEPROM_STOP(); 298 EEPROM_START(); 299 /* 300 * Send read control code to EEPROM. 301 */ 302 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 303 printf("%s: failed to send read command, status: %x\n", 304 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 305 return (1); 306 } 307 308 /* 309 * Start reading bits from EEPROM. 310 */ 311 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 312 for (i = 0x80; i; i >>= 1) { 313 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 314 DELAY(1); 315 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 316 byte |= i; 317 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 318 DELAY(1); 319 } 320 321 EEPROM_STOP(); 322 323 /* 324 * No ACK generated for read, so just return byte. 325 */ 326 327 *dest = byte; 328 329 return (0); 330 } 331 332 /* 333 * Read a sequence of bytes from the EEPROM. 334 */ 335 static int 336 ti_read_eeprom(struct ti_softc *sc, void *destv, int off, int cnt) 337 { 338 char *dest = destv; 339 int err = 0, i; 340 uint8_t byte = 0; 341 342 for (i = 0; i < cnt; i++) { 343 err = ti_eeprom_getbyte(sc, off + i, &byte); 344 if (err) 345 break; 346 *(dest + i) = byte; 347 } 348 349 return (err ? 1 : 0); 350 } 351 352 /* 353 * NIC memory access function. Can be used to either clear a section 354 * of NIC local memory or (if tbuf is non-NULL) copy data into it. 355 */ 356 static void 357 ti_mem(struct ti_softc *sc, uint32_t addr, uint32_t len, const void *xbuf) 358 { 359 int segptr, segsize, cnt; 360 const void *ptr; 361 362 segptr = addr; 363 cnt = len; 364 ptr = xbuf; 365 366 while (cnt) { 367 if (cnt < TI_WINLEN) 368 segsize = cnt; 369 else 370 segsize = TI_WINLEN - (segptr % TI_WINLEN); 371 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 372 if (xbuf == NULL) { 373 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 374 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 375 segsize / 4); 376 } else { 377 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 378 bus_space_write_region_stream_4(sc->ti_btag, 379 sc->ti_bhandle, 380 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 381 (const uint32_t *)ptr, segsize / 4); 382 #else 383 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 384 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 385 (const uint32_t *)ptr, segsize / 4); 386 #endif 387 ptr = (const char *)ptr + segsize; 388 } 389 segptr += segsize; 390 cnt -= segsize; 391 } 392 393 return; 394 } 395 396 /* 397 * Load firmware image into the NIC. Check that the firmware revision 398 * is acceptable and see if we want the firmware for the Tigon 1 or 399 * Tigon 2. 400 */ 401 static void 402 ti_loadfw(struct ti_softc *sc) 403 { 404 switch (sc->ti_hwrev) { 405 case TI_HWREV_TIGON: 406 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 407 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 408 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 409 printf("%s: firmware revision mismatch; want " 410 "%d.%d.%d, got %d.%d.%d\n", device_xname(sc->sc_dev), 411 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 412 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 413 tigonFwReleaseMinor, tigonFwReleaseFix); 414 return; 415 } 416 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 417 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 418 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, tigonFwRodata); 419 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 420 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 421 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 422 break; 423 case TI_HWREV_TIGON_II: 424 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 425 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 426 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 427 printf("%s: firmware revision mismatch; want " 428 "%d.%d.%d, got %d.%d.%d\n", device_xname(sc->sc_dev), 429 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 430 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 431 tigon2FwReleaseMinor, tigon2FwReleaseFix); 432 return; 433 } 434 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, tigon2FwText); 435 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, tigon2FwData); 436 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 437 tigon2FwRodata); 438 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 439 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 440 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 441 break; 442 default: 443 printf("%s: can't load firmware: unknown hardware rev\n", 444 device_xname(sc->sc_dev)); 445 break; 446 } 447 448 return; 449 } 450 451 /* 452 * Send the NIC a command via the command ring. 453 */ 454 static void 455 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 456 { 457 uint32_t index; 458 459 index = sc->ti_cmd_saved_prodidx; 460 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 461 TI_INC(index, TI_CMD_RING_CNT); 462 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 463 sc->ti_cmd_saved_prodidx = index; 464 } 465 466 /* 467 * Send the NIC an extended command. The 'len' parameter specifies the 468 * number of command slots to include after the initial command. 469 */ 470 static void 471 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, void *argv, int len) 472 { 473 char *arg = argv; 474 uint32_t index; 475 int i; 476 477 index = sc->ti_cmd_saved_prodidx; 478 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 479 TI_INC(index, TI_CMD_RING_CNT); 480 for (i = 0; i < len; i++) { 481 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 482 *(uint32_t *)(&arg[i * 4])); 483 TI_INC(index, TI_CMD_RING_CNT); 484 } 485 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 486 sc->ti_cmd_saved_prodidx = index; 487 } 488 489 /* 490 * Handle events that have triggered interrupts. 491 */ 492 static void 493 ti_handle_events(struct ti_softc *sc) 494 { 495 struct ti_event_desc *e; 496 497 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 498 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 499 switch (TI_EVENT_EVENT(e)) { 500 case TI_EV_LINKSTAT_CHANGED: 501 sc->ti_linkstat = TI_EVENT_CODE(e); 502 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) 503 printf("%s: 10/100 link up\n", 504 device_xname(sc->sc_dev)); 505 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 506 printf("%s: gigabit link up\n", 507 device_xname(sc->sc_dev)); 508 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 509 printf("%s: link down\n", 510 device_xname(sc->sc_dev)); 511 break; 512 case TI_EV_ERROR: 513 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 514 printf("%s: invalid command\n", 515 device_xname(sc->sc_dev)); 516 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 517 printf("%s: unknown command\n", 518 device_xname(sc->sc_dev)); 519 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 520 printf("%s: bad config data\n", 521 device_xname(sc->sc_dev)); 522 break; 523 case TI_EV_FIRMWARE_UP: 524 ti_init2(sc); 525 break; 526 case TI_EV_STATS_UPDATED: 527 ti_stats_update(sc); 528 break; 529 case TI_EV_RESET_JUMBO_RING: 530 case TI_EV_MCAST_UPDATED: 531 /* Who cares. */ 532 break; 533 default: 534 printf("%s: unknown event: %d\n", 535 device_xname(sc->sc_dev), TI_EVENT_EVENT(e)); 536 break; 537 } 538 /* Advance the consumer index. */ 539 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 540 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 541 } 542 543 return; 544 } 545 546 /* 547 * Memory management for the jumbo receive ring is a pain in the 548 * butt. We need to allocate at least 9018 bytes of space per frame, 549 * _and_ it has to be contiguous (unless you use the extended 550 * jumbo descriptor format). Using malloc() all the time won't 551 * work: malloc() allocates memory in powers of two, which means we 552 * would end up wasting a considerable amount of space by allocating 553 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 554 * to do our own memory management. 555 * 556 * The driver needs to allocate a contiguous chunk of memory at boot 557 * time. We then chop this up ourselves into 9K pieces and use them 558 * as external mbuf storage. 559 * 560 * One issue here is how much memory to allocate. The jumbo ring has 561 * 256 slots in it, but at 9K per slot than can consume over 2MB of 562 * RAM. This is a bit much, especially considering we also need 563 * RAM for the standard ring and mini ring (on the Tigon 2). To 564 * save space, we only actually allocate enough memory for 64 slots 565 * by default, which works out to between 500 and 600K. This can 566 * be tuned by changing a #define in if_tireg.h. 567 */ 568 569 static int 570 ti_alloc_jumbo_mem(struct ti_softc *sc) 571 { 572 char *ptr; 573 int i; 574 struct ti_jpool_entry *entry; 575 bus_dma_segment_t dmaseg; 576 int error, dmanseg; 577 578 /* Grab a big chunk o' storage. */ 579 if ((error = bus_dmamem_alloc(sc->sc_dmat, 580 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 581 BUS_DMA_NOWAIT)) != 0) { 582 aprint_error_dev(sc->sc_dev, 583 "can't allocate jumbo buffer, error = %d\n", error); 584 return (error); 585 } 586 587 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 588 TI_JMEM, (void **)&sc->ti_cdata.ti_jumbo_buf, 589 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 590 aprint_error_dev(sc->sc_dev, 591 "can't map jumbo buffer, error = %d\n", error); 592 return (error); 593 } 594 595 if ((error = bus_dmamap_create(sc->sc_dmat, 596 TI_JMEM, 1, 597 TI_JMEM, 0, BUS_DMA_NOWAIT, 598 &sc->jumbo_dmamap)) != 0) { 599 aprint_error_dev(sc->sc_dev, 600 "can't create jumbo buffer DMA map, error = %d\n", error); 601 return (error); 602 } 603 604 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 605 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 606 BUS_DMA_NOWAIT)) != 0) { 607 aprint_error_dev(sc->sc_dev, 608 "can't load jumbo buffer DMA map, error = %d\n", error); 609 return (error); 610 } 611 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 612 613 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 614 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 615 616 /* 617 * Now divide it up into 9K pieces and save the addresses 618 * in an array. 619 */ 620 ptr = sc->ti_cdata.ti_jumbo_buf; 621 for (i = 0; i < TI_JSLOTS; i++) { 622 sc->ti_cdata.ti_jslots[i] = ptr; 623 ptr += TI_JLEN; 624 entry = malloc(sizeof(struct ti_jpool_entry), 625 M_DEVBUF, M_WAITOK); 626 entry->slot = i; 627 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 628 jpool_entries); 629 } 630 631 return (0); 632 } 633 634 /* 635 * Allocate a jumbo buffer. 636 */ 637 static void * 638 ti_jalloc(struct ti_softc *sc) 639 { 640 struct ti_jpool_entry *entry; 641 642 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 643 644 if (entry == NULL) { 645 printf("%s: no free jumbo buffers\n", device_xname(sc->sc_dev)); 646 return (NULL); 647 } 648 649 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 650 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 651 652 return (sc->ti_cdata.ti_jslots[entry->slot]); 653 } 654 655 /* 656 * Release a jumbo buffer. 657 */ 658 static void 659 ti_jfree(struct mbuf *m, void *tbuf, size_t size, void *arg) 660 { 661 struct ti_softc *sc; 662 int i, s; 663 struct ti_jpool_entry *entry; 664 665 /* Extract the softc struct pointer. */ 666 sc = (struct ti_softc *)arg; 667 668 if (sc == NULL) 669 panic("ti_jfree: didn't get softc pointer!"); 670 671 /* calculate the slot this buffer belongs to */ 672 673 i = ((char *)tbuf 674 - (char *)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 675 676 if ((i < 0) || (i >= TI_JSLOTS)) 677 panic("ti_jfree: asked to free buffer that we don't manage!"); 678 679 s = splvm(); 680 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 681 if (entry == NULL) 682 panic("ti_jfree: buffer not in use!"); 683 entry->slot = i; 684 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 685 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 686 687 if (__predict_true(m != NULL)) 688 pool_cache_put(mb_cache, m); 689 splx(s); 690 } 691 692 693 /* 694 * Initialize a standard receive ring descriptor. 695 */ 696 static int 697 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 698 { 699 struct mbuf *m_new = NULL; 700 struct ti_rx_desc *r; 701 int error; 702 703 if (dmamap == NULL) { 704 /* if (m) panic() */ 705 706 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 707 MCLBYTES, 0, BUS_DMA_NOWAIT, 708 &dmamap)) != 0) { 709 aprint_error_dev(sc->sc_dev, 710 "can't create recv map, error = %d\n", error); 711 return (ENOMEM); 712 } 713 } 714 sc->std_dmamap[i] = dmamap; 715 716 if (m == NULL) { 717 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 718 if (m_new == NULL) { 719 aprint_error_dev(sc->sc_dev, 720 "mbuf allocation failed -- packet dropped!\n"); 721 return (ENOBUFS); 722 } 723 724 MCLGET(m_new, M_DONTWAIT); 725 if (!(m_new->m_flags & M_EXT)) { 726 aprint_error_dev(sc->sc_dev, 727 "cluster allocation failed -- packet dropped!\n"); 728 m_freem(m_new); 729 return (ENOBUFS); 730 } 731 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 732 m_adj(m_new, ETHER_ALIGN); 733 734 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 735 mtod(m_new, void *), m_new->m_len, NULL, 736 BUS_DMA_READ | BUS_DMA_NOWAIT)) != 0) { 737 aprint_error_dev(sc->sc_dev, 738 "can't load recv map, error = %d\n", error); 739 m_freem(m_new); 740 return (ENOMEM); 741 } 742 } else { 743 m_new = m; 744 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 745 m_new->m_data = m_new->m_ext.ext_buf; 746 m_adj(m_new, ETHER_ALIGN); 747 748 /* reuse the dmamap */ 749 } 750 751 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 752 r = &sc->ti_rdata->ti_rx_std_ring[i]; 753 TI_HOSTADDR(r->ti_addr, dmamap->dm_segs[0].ds_addr); 754 r->ti_type = TI_BDTYPE_RECV_BD; 755 r->ti_flags = 0; 756 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 757 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 758 if (sc->ethercom.ec_if.if_capenable & 759 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 760 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 761 r->ti_len = m_new->m_len; /* == ds_len */ 762 r->ti_idx = i; 763 764 return (0); 765 } 766 767 /* 768 * Intialize a mini receive ring descriptor. This only applies to 769 * the Tigon 2. 770 */ 771 static int 772 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 773 { 774 struct mbuf *m_new = NULL; 775 struct ti_rx_desc *r; 776 int error; 777 778 if (dmamap == NULL) { 779 /* if (m) panic() */ 780 781 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 782 MHLEN, 0, BUS_DMA_NOWAIT, 783 &dmamap)) != 0) { 784 aprint_error_dev(sc->sc_dev, 785 "can't create recv map, error = %d\n", error); 786 return (ENOMEM); 787 } 788 } 789 sc->mini_dmamap[i] = dmamap; 790 791 if (m == NULL) { 792 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 793 if (m_new == NULL) { 794 aprint_error_dev(sc->sc_dev, 795 "mbuf allocation failed -- packet dropped!\n"); 796 return (ENOBUFS); 797 } 798 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 799 m_adj(m_new, ETHER_ALIGN); 800 801 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 802 mtod(m_new, void *), m_new->m_len, NULL, 803 BUS_DMA_READ | BUS_DMA_NOWAIT)) != 0) { 804 aprint_error_dev(sc->sc_dev, 805 "can't load recv map, error = %d\n", error); 806 m_freem(m_new); 807 return (ENOMEM); 808 } 809 } else { 810 m_new = m; 811 m_new->m_data = m_new->m_pktdat; 812 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 813 m_adj(m_new, ETHER_ALIGN); 814 815 /* reuse the dmamap */ 816 } 817 818 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 819 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 820 TI_HOSTADDR(r->ti_addr, dmamap->dm_segs[0].ds_addr); 821 r->ti_type = TI_BDTYPE_RECV_BD; 822 r->ti_flags = TI_BDFLAG_MINI_RING; 823 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 824 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 825 if (sc->ethercom.ec_if.if_capenable & 826 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 827 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 828 r->ti_len = m_new->m_len; /* == ds_len */ 829 r->ti_idx = i; 830 831 return (0); 832 } 833 834 /* 835 * Initialize a jumbo receive ring descriptor. This allocates 836 * a jumbo buffer from the pool managed internally by the driver. 837 */ 838 static int 839 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m) 840 { 841 struct mbuf *m_new = NULL; 842 struct ti_rx_desc *r; 843 844 if (m == NULL) { 845 void * tbuf = NULL; 846 847 /* Allocate the mbuf. */ 848 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 849 if (m_new == NULL) { 850 aprint_error_dev(sc->sc_dev, 851 "mbuf allocation failed -- packet dropped!\n"); 852 return (ENOBUFS); 853 } 854 855 /* Allocate the jumbo buffer */ 856 tbuf = ti_jalloc(sc); 857 if (tbuf == NULL) { 858 m_freem(m_new); 859 aprint_error_dev(sc->sc_dev, 860 "jumbo allocation failed -- packet dropped!\n"); 861 return (ENOBUFS); 862 } 863 864 /* Attach the buffer to the mbuf. */ 865 MEXTADD(m_new, tbuf, ETHER_MAX_LEN_JUMBO, 866 M_DEVBUF, ti_jfree, sc); 867 m_new->m_flags |= M_EXT_RW; 868 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 869 } else { 870 m_new = m; 871 m_new->m_data = m_new->m_ext.ext_buf; 872 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 873 } 874 875 m_adj(m_new, ETHER_ALIGN); 876 /* Set up the descriptor. */ 877 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 878 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 879 TI_HOSTADDR(r->ti_addr, sc->jumbo_dmaaddr + 880 (mtod(m_new, char *) - (char *)sc->ti_cdata.ti_jumbo_buf)); 881 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 882 r->ti_flags = TI_BDFLAG_JUMBO_RING; 883 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 884 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 885 if (sc->ethercom.ec_if.if_capenable & 886 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 887 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 888 r->ti_len = m_new->m_len; 889 r->ti_idx = i; 890 891 return (0); 892 } 893 894 /* 895 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 896 * that's 1MB or memory, which is a lot. For now, we fill only the first 897 * 256 ring entries and hope that our CPU is fast enough to keep up with 898 * the NIC. 899 */ 900 static int 901 ti_init_rx_ring_std(struct ti_softc *sc) 902 { 903 int i; 904 struct ti_cmd_desc cmd; 905 906 for (i = 0; i < TI_SSLOTS; i++) { 907 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 908 return (ENOBUFS); 909 }; 910 911 TI_UPDATE_STDPROD(sc, i - 1); 912 sc->ti_std = i - 1; 913 914 return (0); 915 } 916 917 static void 918 ti_free_rx_ring_std(struct ti_softc *sc) 919 { 920 int i; 921 922 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 923 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 924 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 925 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 926 927 /* if (sc->std_dmamap[i] == 0) panic() */ 928 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 929 sc->std_dmamap[i] = 0; 930 } 931 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 932 sizeof(struct ti_rx_desc)); 933 } 934 935 return; 936 } 937 938 static int 939 ti_init_rx_ring_jumbo(struct ti_softc *sc) 940 { 941 int i; 942 struct ti_cmd_desc cmd; 943 944 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 945 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 946 return (ENOBUFS); 947 }; 948 949 TI_UPDATE_JUMBOPROD(sc, i - 1); 950 sc->ti_jumbo = i - 1; 951 952 return (0); 953 } 954 955 static void 956 ti_free_rx_ring_jumbo(struct ti_softc *sc) 957 { 958 int i; 959 960 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 961 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 962 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 963 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 964 } 965 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 966 sizeof(struct ti_rx_desc)); 967 } 968 969 return; 970 } 971 972 static int 973 ti_init_rx_ring_mini(struct ti_softc *sc) 974 { 975 int i; 976 977 for (i = 0; i < TI_MSLOTS; i++) { 978 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 979 return (ENOBUFS); 980 }; 981 982 TI_UPDATE_MINIPROD(sc, i - 1); 983 sc->ti_mini = i - 1; 984 985 return (0); 986 } 987 988 static void 989 ti_free_rx_ring_mini(struct ti_softc *sc) 990 { 991 int i; 992 993 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 994 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 995 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 996 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 997 998 /* if (sc->mini_dmamap[i] == 0) panic() */ 999 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1000 sc->mini_dmamap[i] = 0; 1001 } 1002 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1003 sizeof(struct ti_rx_desc)); 1004 } 1005 1006 return; 1007 } 1008 1009 static void 1010 ti_free_tx_ring(struct ti_softc *sc) 1011 { 1012 int i; 1013 struct txdmamap_pool_entry *dma; 1014 1015 for (i = 0; i < TI_TX_RING_CNT; i++) { 1016 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1017 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1018 sc->ti_cdata.ti_tx_chain[i] = NULL; 1019 1020 /* if (sc->txdma[i] == 0) panic() */ 1021 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1022 link); 1023 sc->txdma[i] = 0; 1024 } 1025 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1026 sizeof(struct ti_tx_desc)); 1027 } 1028 1029 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1030 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1031 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1032 free(dma, M_DEVBUF); 1033 } 1034 1035 return; 1036 } 1037 1038 static int 1039 ti_init_tx_ring(struct ti_softc *sc) 1040 { 1041 int i, error; 1042 bus_dmamap_t dmamap; 1043 struct txdmamap_pool_entry *dma; 1044 1045 sc->ti_txcnt = 0; 1046 sc->ti_tx_saved_considx = 0; 1047 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1048 1049 SIMPLEQ_INIT(&sc->txdma_list); 1050 for (i = 0; i < TI_RSLOTS; i++) { 1051 /* I've seen mbufs with 30 fragments. */ 1052 if ((error = bus_dmamap_create(sc->sc_dmat, 1053 ETHER_MAX_LEN_JUMBO, 40, ETHER_MAX_LEN_JUMBO, 0, 1054 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1055 aprint_error_dev(sc->sc_dev, 1056 "can't create tx map, error = %d\n", error); 1057 return (ENOMEM); 1058 } 1059 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1060 if (!dma) { 1061 aprint_error_dev(sc->sc_dev, 1062 "can't alloc txdmamap_pool_entry\n"); 1063 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1064 return (ENOMEM); 1065 } 1066 dma->dmamap = dmamap; 1067 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1068 } 1069 1070 return (0); 1071 } 1072 1073 /* 1074 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1075 * but we have to support the old way too so that Tigon 1 cards will 1076 * work. 1077 */ 1078 static void 1079 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1080 { 1081 struct ti_cmd_desc cmd; 1082 uint16_t *m; 1083 uint32_t ext[2] = {0, 0}; 1084 1085 m = (uint16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1086 1087 switch (sc->ti_hwrev) { 1088 case TI_HWREV_TIGON: 1089 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1090 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1091 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1092 break; 1093 case TI_HWREV_TIGON_II: 1094 ext[0] = htons(m[0]); 1095 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1096 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (void *)&ext, 2); 1097 break; 1098 default: 1099 printf("%s: unknown hwrev\n", device_xname(sc->sc_dev)); 1100 break; 1101 } 1102 1103 return; 1104 } 1105 1106 static void 1107 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1108 { 1109 struct ti_cmd_desc cmd; 1110 uint16_t *m; 1111 uint32_t ext[2] = {0, 0}; 1112 1113 m = (uint16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1114 1115 switch (sc->ti_hwrev) { 1116 case TI_HWREV_TIGON: 1117 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1118 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1119 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1120 break; 1121 case TI_HWREV_TIGON_II: 1122 ext[0] = htons(m[0]); 1123 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1124 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (void *)&ext, 2); 1125 break; 1126 default: 1127 printf("%s: unknown hwrev\n", device_xname(sc->sc_dev)); 1128 break; 1129 } 1130 1131 return; 1132 } 1133 1134 /* 1135 * Configure the Tigon's multicast address filter. 1136 * 1137 * The actual multicast table management is a bit of a pain, thanks to 1138 * slight brain damage on the part of both Alteon and us. With our 1139 * multicast code, we are only alerted when the multicast address table 1140 * changes and at that point we only have the current list of addresses: 1141 * we only know the current state, not the previous state, so we don't 1142 * actually know what addresses were removed or added. The firmware has 1143 * state, but we can't get our grubby mits on it, and there is no 'delete 1144 * all multicast addresses' command. Hence, we have to maintain our own 1145 * state so we know what addresses have been programmed into the NIC at 1146 * any given time. 1147 */ 1148 static void 1149 ti_setmulti(struct ti_softc *sc) 1150 { 1151 struct ethercom *ec = &sc->ethercom; 1152 struct ifnet *ifp = &ec->ec_if; 1153 struct ti_cmd_desc cmd; 1154 struct ti_mc_entry *mc; 1155 uint32_t intrs; 1156 struct ether_multi *enm; 1157 struct ether_multistep step; 1158 1159 /* Disable interrupts. */ 1160 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1161 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1162 1163 /* First, zot all the existing filters. */ 1164 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1165 ti_del_mcast(sc, &mc->mc_addr); 1166 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1167 free(mc, M_DEVBUF); 1168 } 1169 1170 /* 1171 * Remember all multicast addresses so that we can delete them 1172 * later. Punt if there is a range of addresses or memory shortage. 1173 */ 1174 ETHER_LOCK(ec); 1175 ETHER_FIRST_MULTI(step, ec, enm); 1176 while (enm != NULL) { 1177 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1178 ETHER_ADDR_LEN) != 0) { 1179 ETHER_UNLOCK(ec); 1180 goto allmulti; 1181 } 1182 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1183 M_NOWAIT)) == NULL) { 1184 ETHER_UNLOCK(ec); 1185 goto allmulti; 1186 } 1187 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1188 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1189 ETHER_NEXT_MULTI(step, enm); 1190 } 1191 ETHER_UNLOCK(ec); 1192 1193 /* Accept only programmed multicast addresses */ 1194 ifp->if_flags &= ~IFF_ALLMULTI; 1195 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1196 1197 /* Now program new ones. */ 1198 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1199 ti_add_mcast(sc, &mc->mc_addr); 1200 1201 /* Re-enable interrupts. */ 1202 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1203 1204 return; 1205 1206 allmulti: 1207 /* No need to keep individual multicast addresses */ 1208 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1209 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1210 free(mc, M_DEVBUF); 1211 } 1212 1213 /* Accept all multicast addresses */ 1214 ifp->if_flags |= IFF_ALLMULTI; 1215 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1216 1217 /* Re-enable interrupts. */ 1218 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1219 } 1220 1221 /* 1222 * Check to see if the BIOS has configured us for a 64 bit slot when 1223 * we aren't actually in one. If we detect this condition, we can work 1224 * around it on the Tigon 2 by setting a bit in the PCI state register, 1225 * but for the Tigon 1 we must give up and abort the interface attach. 1226 */ 1227 static int 1228 ti_64bitslot_war(struct ti_softc *sc) 1229 { 1230 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1231 CSR_WRITE_4(sc, 0x600, 0); 1232 CSR_WRITE_4(sc, 0x604, 0); 1233 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1234 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1235 if (sc->ti_hwrev == TI_HWREV_TIGON) 1236 return (EINVAL); 1237 else { 1238 TI_SETBIT(sc, TI_PCI_STATE, 1239 TI_PCISTATE_32BIT_BUS); 1240 return (0); 1241 } 1242 } 1243 } 1244 1245 return (0); 1246 } 1247 1248 /* 1249 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1250 * self-test results. 1251 */ 1252 static int 1253 ti_chipinit(struct ti_softc *sc) 1254 { 1255 uint32_t cacheline; 1256 uint32_t pci_writemax = 0; 1257 uint32_t rev; 1258 1259 /* Initialize link to down state. */ 1260 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1261 1262 /* Set endianness before we access any non-PCI registers. */ 1263 #if BYTE_ORDER == BIG_ENDIAN 1264 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1265 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1266 #else 1267 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1268 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1269 #endif 1270 1271 /* Check the ROM failed bit to see if self-tests passed. */ 1272 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1273 printf("%s: board self-diagnostics failed!\n", 1274 device_xname(sc->sc_dev)); 1275 return (ENODEV); 1276 } 1277 1278 /* Halt the CPU. */ 1279 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1280 1281 /* Figure out the hardware revision. */ 1282 rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK; 1283 switch (rev) { 1284 case TI_REV_TIGON_I: 1285 sc->ti_hwrev = TI_HWREV_TIGON; 1286 break; 1287 case TI_REV_TIGON_II: 1288 sc->ti_hwrev = TI_HWREV_TIGON_II; 1289 break; 1290 default: 1291 printf("%s: unsupported chip revision 0x%x\n", 1292 device_xname(sc->sc_dev), rev); 1293 return (ENODEV); 1294 } 1295 1296 /* Do special setup for Tigon 2. */ 1297 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1298 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1299 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1300 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1301 } 1302 1303 /* Set up the PCI state register. */ 1304 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD | TI_PCI_WRITE_CMD); 1305 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1306 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1307 } 1308 1309 /* Clear the read/write max DMA parameters. */ 1310 TI_CLRBIT(sc, TI_PCI_STATE, 1311 (TI_PCISTATE_WRITE_MAXDMA | TI_PCISTATE_READ_MAXDMA)); 1312 1313 /* Get cache line size. */ 1314 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1315 1316 /* 1317 * If the system has set enabled the PCI memory write 1318 * and invalidate command in the command register, set 1319 * the write max parameter accordingly. This is necessary 1320 * to use MWI with the Tigon 2. 1321 */ 1322 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1323 & PCI_COMMAND_INVALIDATE_ENABLE) { 1324 switch (cacheline) { 1325 case 1: 1326 case 4: 1327 case 8: 1328 case 16: 1329 case 32: 1330 case 64: 1331 break; 1332 default: 1333 /* Disable PCI memory write and invalidate. */ 1334 if (bootverbose) 1335 printf("%s: cache line size %d not " 1336 "supported; disabling PCI MWI\n", 1337 device_xname(sc->sc_dev), cacheline); 1338 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1339 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1340 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1341 break; 1342 } 1343 } 1344 1345 #ifdef __brokenalpha__ 1346 /* 1347 * From the Alteon sample driver: 1348 * Must insure that we do not cross an 8K (bytes) boundary 1349 * for DMA reads. Our highest limit is 1K bytes. This is a 1350 * restriction on some ALPHA platforms with early revision 1351 * 21174 PCI chipsets, such as the AlphaPC 164lx 1352 */ 1353 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax | TI_PCI_READMAX_1024); 1354 #else 1355 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1356 #endif 1357 1358 /* This sets the min dma param all the way up (0xff). */ 1359 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1360 1361 /* Configure DMA variables. */ 1362 #if BYTE_ORDER == BIG_ENDIAN 1363 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1364 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1365 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1366 TI_OPMODE_DONT_FRAG_JUMBO); 1367 #else 1368 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA | 1369 TI_OPMODE_WORDSWAP_BD | TI_OPMODE_DONT_FRAG_JUMBO | 1370 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB); 1371 #endif 1372 1373 /* 1374 * Only allow 1 DMA channel to be active at a time. 1375 * I don't think this is a good idea, but without it 1376 * the firmware racks up lots of nicDmaReadRingFull 1377 * errors. 1378 * Incompatible with hardware assisted checksums. 1379 */ 1380 if ((sc->ethercom.ec_if.if_capenable & 1381 (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1382 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1383 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx)) == 0) 1384 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1385 1386 /* Recommended settings from Tigon manual. */ 1387 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1388 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1389 1390 if (ti_64bitslot_war(sc)) { 1391 printf("%s: bios thinks we're in a 64 bit slot, " 1392 "but we aren't", device_xname(sc->sc_dev)); 1393 return (EINVAL); 1394 } 1395 1396 return (0); 1397 } 1398 1399 /* 1400 * Initialize the general information block and firmware, and 1401 * start the CPU(s) running. 1402 */ 1403 static int 1404 ti_gibinit(struct ti_softc *sc) 1405 { 1406 struct ti_rcb *rcb; 1407 int i; 1408 struct ifnet *ifp; 1409 1410 ifp = &sc->ethercom.ec_if; 1411 1412 /* Disable interrupts for now. */ 1413 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1414 1415 /* Tell the chip where to find the general information block. */ 1416 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1417 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1418 1419 /* Load the firmware into SRAM. */ 1420 ti_loadfw(sc); 1421 1422 /* Set up the contents of the general info and ring control blocks. */ 1423 1424 /* Set up the event ring and producer pointer. */ 1425 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1426 1427 TI_HOSTADDR(rcb->ti_hostaddr, TI_CDEVENTADDR(sc, 0)); 1428 rcb->ti_flags = 0; 1429 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr, 1430 TI_CDEVPRODADDR(sc)); 1431 1432 sc->ti_ev_prodidx.ti_idx = 0; 1433 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1434 sc->ti_ev_saved_considx = 0; 1435 1436 /* Set up the command ring and producer mailbox. */ 1437 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1438 1439 TI_HOSTADDR(rcb->ti_hostaddr, TI_GCR_NIC_ADDR(TI_GCR_CMDRING)); 1440 rcb->ti_flags = 0; 1441 rcb->ti_max_len = 0; 1442 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1443 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1444 } 1445 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1446 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1447 sc->ti_cmd_saved_prodidx = 0; 1448 1449 /* 1450 * Assign the address of the stats refresh buffer. 1451 * We re-use the current stats buffer for this to 1452 * conserve memory. 1453 */ 1454 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr, 1455 TI_CDSTATSADDR(sc)); 1456 1457 /* Set up the standard receive ring. */ 1458 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1459 TI_HOSTADDR(rcb->ti_hostaddr, TI_CDRXSTDADDR(sc, 0)); 1460 rcb->ti_max_len = ETHER_MAX_LEN; 1461 rcb->ti_flags = 0; 1462 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1463 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1464 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1465 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1466 if (VLAN_ATTACHED(&sc->ethercom)) 1467 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1468 1469 /* Set up the jumbo receive ring. */ 1470 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1471 TI_HOSTADDR(rcb->ti_hostaddr, TI_CDRXJUMBOADDR(sc, 0)); 1472 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1473 rcb->ti_flags = 0; 1474 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1475 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1476 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1477 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1478 if (VLAN_ATTACHED(&sc->ethercom)) 1479 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1480 1481 /* 1482 * Set up the mini ring. Only activated on the 1483 * Tigon 2 but the slot in the config block is 1484 * still there on the Tigon 1. 1485 */ 1486 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1487 TI_HOSTADDR(rcb->ti_hostaddr, TI_CDRXMINIADDR(sc, 0)); 1488 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1489 if (sc->ti_hwrev == TI_HWREV_TIGON) 1490 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1491 else 1492 rcb->ti_flags = 0; 1493 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1494 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1495 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1496 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1497 if (VLAN_ATTACHED(&sc->ethercom)) 1498 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1499 1500 /* 1501 * Set up the receive return ring. 1502 */ 1503 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1504 TI_HOSTADDR(rcb->ti_hostaddr, TI_CDRXRTNADDR(sc, 0)); 1505 rcb->ti_flags = 0; 1506 rcb->ti_max_len = TI_RETURN_RING_CNT; 1507 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr, 1508 TI_CDRTNPRODADDR(sc)); 1509 1510 /* 1511 * Set up the tx ring. Note: for the Tigon 2, we have the option 1512 * of putting the transmit ring in the host's address space and 1513 * letting the chip DMA it instead of leaving the ring in the NIC's 1514 * memory and accessing it through the shared memory region. We 1515 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1516 * so we have to revert to the shared memory scheme if we detect 1517 * a Tigon 1 chip. 1518 */ 1519 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1520 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1521 sc->ti_tx_ring_nic = 1522 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1523 } 1524 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1525 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1526 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1527 if (sc->ti_hwrev == TI_HWREV_TIGON) 1528 rcb->ti_flags = 0; 1529 else 1530 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1531 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) 1532 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1533 /* 1534 * When we get the packet, there is a pseudo-header seed already 1535 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1536 * compute the pseudo-header checksum again! 1537 */ 1538 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx)) 1539 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1540 TI_RCB_FLAG_NO_PHDR_CKSUM; 1541 if (VLAN_ATTACHED(&sc->ethercom)) 1542 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1543 rcb->ti_max_len = TI_TX_RING_CNT; 1544 if (sc->ti_hwrev == TI_HWREV_TIGON) 1545 TI_HOSTADDR(rcb->ti_hostaddr, TI_TX_RING_BASE); 1546 else 1547 TI_HOSTADDR(rcb->ti_hostaddr, TI_CDTXADDR(sc, 0)); 1548 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr, 1549 TI_CDTXCONSADDR(sc)); 1550 1551 /* 1552 * We're done frobbing the General Information Block. Sync 1553 * it. Note we take care of the first stats sync here, as 1554 * well. 1555 */ 1556 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1557 1558 /* Set up tuneables */ 1559 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1560 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1561 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1562 (sc->ti_rx_coal_ticks / 10)); 1563 else 1564 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1565 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1566 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1567 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1568 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1569 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1570 1571 /* Turn interrupts on. */ 1572 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1573 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1574 1575 /* Start CPU. */ 1576 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT | TI_CPUSTATE_STEP)); 1577 1578 return (0); 1579 } 1580 1581 /* 1582 * look for id in the device list, returning the first match 1583 */ 1584 static const struct ti_type * 1585 ti_type_match(struct pci_attach_args *pa) 1586 { 1587 const struct ti_type *t; 1588 1589 t = ti_devs; 1590 while (t->ti_name != NULL) { 1591 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1592 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1593 return (t); 1594 } 1595 t++; 1596 } 1597 1598 return (NULL); 1599 } 1600 1601 /* 1602 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1603 * against our list and return its name if we find a match. 1604 */ 1605 static int 1606 ti_probe(device_t parent, cfdata_t match, void *aux) 1607 { 1608 struct pci_attach_args *pa = aux; 1609 const struct ti_type *t; 1610 1611 t = ti_type_match(pa); 1612 1613 return ((t == NULL) ? 0 : 1); 1614 } 1615 1616 static void 1617 ti_attach(device_t parent, device_t self, void *aux) 1618 { 1619 uint32_t command; 1620 struct ifnet *ifp; 1621 struct ti_softc *sc; 1622 uint8_t eaddr[ETHER_ADDR_LEN]; 1623 struct pci_attach_args *pa = aux; 1624 pci_chipset_tag_t pc = pa->pa_pc; 1625 pci_intr_handle_t ih; 1626 const char *intrstr = NULL; 1627 bus_dma_segment_t dmaseg; 1628 int error, dmanseg, nolinear; 1629 const struct ti_type *t; 1630 char intrbuf[PCI_INTRSTR_LEN]; 1631 1632 t = ti_type_match(pa); 1633 if (t == NULL) { 1634 aprint_error("ti_attach: were did the card go ?\n"); 1635 return; 1636 } 1637 1638 aprint_normal(": %s (rev. 0x%02x)\n", t->ti_name, 1639 PCI_REVISION(pa->pa_class)); 1640 1641 sc = device_private(self); 1642 sc->sc_dev = self; 1643 1644 /* 1645 * Map control/status registers. 1646 */ 1647 nolinear = 0; 1648 if (pci_mapreg_map(pa, 0x10, 1649 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1650 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1651 NULL, NULL)) { 1652 nolinear = 1; 1653 if (pci_mapreg_map(pa, 0x10, 1654 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1655 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1656 aprint_error_dev(self, "can't map memory space\n"); 1657 return; 1658 } 1659 } 1660 if (nolinear == 0) 1661 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1662 else 1663 sc->ti_vhandle = NULL; 1664 1665 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1666 command |= PCI_COMMAND_MASTER_ENABLE; 1667 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1668 1669 /* Allocate interrupt */ 1670 if (pci_intr_map(pa, &ih)) { 1671 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 1672 return; 1673 } 1674 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1675 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, ti_intr, sc, 1676 device_xname(self)); 1677 if (sc->sc_ih == NULL) { 1678 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 1679 if (intrstr != NULL) 1680 aprint_error(" at %s", intrstr); 1681 aprint_error("\n"); 1682 return; 1683 } 1684 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1685 1686 if (ti_chipinit(sc)) { 1687 aprint_error_dev(self, "chip initialization failed\n"); 1688 goto fail2; 1689 } 1690 1691 /* 1692 * Deal with some chip diffrences. 1693 */ 1694 switch (sc->ti_hwrev) { 1695 case TI_HWREV_TIGON: 1696 sc->sc_tx_encap = ti_encap_tigon1; 1697 sc->sc_tx_eof = ti_txeof_tigon1; 1698 if (nolinear == 1) 1699 aprint_error_dev(self, 1700 "memory space not mapped linear\n"); 1701 break; 1702 1703 case TI_HWREV_TIGON_II: 1704 sc->sc_tx_encap = ti_encap_tigon2; 1705 sc->sc_tx_eof = ti_txeof_tigon2; 1706 break; 1707 1708 default: 1709 aprint_error_dev(self, "Unknown chip version: %d\n", 1710 sc->ti_hwrev); 1711 goto fail2; 1712 } 1713 1714 /* Zero out the NIC's on-board SRAM. */ 1715 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1716 1717 /* Init again -- zeroing memory may have clobbered some registers. */ 1718 if (ti_chipinit(sc)) { 1719 aprint_error_dev(self, "chip initialization failed\n"); 1720 goto fail2; 1721 } 1722 1723 /* 1724 * Get station address from the EEPROM. Note: the manual states 1725 * that the MAC address is at offset 0x8c, however the data is 1726 * stored as two longwords (since that's how it's loaded into 1727 * the NIC). This means the MAC address is actually preceded 1728 * by two zero bytes. We need to skip over those. 1729 */ 1730 if (ti_read_eeprom(sc, (void *)&eaddr, 1731 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1732 aprint_error_dev(self, "failed to read station address\n"); 1733 goto fail2; 1734 } 1735 1736 /* 1737 * A Tigon chip was detected. Inform the world. 1738 */ 1739 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr)); 1740 1741 if (pci_dma64_available(pa)) 1742 sc->sc_dmat = pa->pa_dmat64; 1743 else 1744 sc->sc_dmat = pa->pa_dmat; 1745 1746 /* Allocate the general information block and ring buffers. */ 1747 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1748 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1749 BUS_DMA_NOWAIT)) != 0) { 1750 aprint_error_dev(self, 1751 "can't allocate ring buffer, error = %d\n", error); 1752 goto fail2; 1753 } 1754 1755 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1756 sizeof(struct ti_ring_data), (void **)&sc->ti_rdata, 1757 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 1758 aprint_error_dev(self, 1759 "can't map ring buffer, error = %d\n", error); 1760 goto fail2; 1761 } 1762 1763 if ((error = bus_dmamap_create(sc->sc_dmat, 1764 sizeof(struct ti_ring_data), 1, 1765 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1766 &sc->info_dmamap)) != 0) { 1767 aprint_error_dev(self, 1768 "can't create ring buffer DMA map, error = %d\n", error); 1769 goto fail2; 1770 } 1771 1772 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1773 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1774 BUS_DMA_NOWAIT)) != 0) { 1775 aprint_error_dev(self, 1776 "can't load ring buffer DMA map, error = %d\n", error); 1777 goto fail2; 1778 } 1779 1780 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1781 1782 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1783 1784 /* Try to allocate memory for jumbo buffers. */ 1785 if (ti_alloc_jumbo_mem(sc)) { 1786 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 1787 goto fail2; 1788 } 1789 1790 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1791 1792 /* 1793 * We really need a better way to tell a 1000baseT card 1794 * from a 1000baseSX one, since in theory there could be 1795 * OEMed 1000baseT cards from lame vendors who aren't 1796 * clever enough to change the PCI ID. For the moment 1797 * though, the AceNIC is the only copper card available. 1798 */ 1799 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1800 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1801 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1802 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1803 sc->ti_copper = 1; 1804 else 1805 sc->ti_copper = 0; 1806 1807 /* Set default tuneable values. */ 1808 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1809 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1810 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1811 sc->ti_rx_max_coal_bds = 64; 1812 sc->ti_tx_max_coal_bds = 128; 1813 sc->ti_tx_buf_ratio = 21; 1814 1815 /* Set up ifnet structure */ 1816 ifp = &sc->ethercom.ec_if; 1817 ifp->if_softc = sc; 1818 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1819 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1820 ifp->if_ioctl = ti_ioctl; 1821 ifp->if_start = ti_start; 1822 ifp->if_watchdog = ti_watchdog; 1823 IFQ_SET_READY(&ifp->if_snd); 1824 1825 #if 0 1826 /* 1827 * XXX This is not really correct -- we don't necessarily 1828 * XXX want to queue up as many as we can transmit at the 1829 * XXX upper layer like that. Someone with a board should 1830 * XXX check to see how this affects performance. 1831 */ 1832 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1833 #endif 1834 1835 /* 1836 * We can support 802.1Q VLAN-sized frames. 1837 */ 1838 sc->ethercom.ec_capabilities |= 1839 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1840 sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 1841 1842 /* 1843 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1844 */ 1845 ifp->if_capabilities |= 1846 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1847 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1848 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1849 1850 /* Set up ifmedia support. */ 1851 sc->ethercom.ec_ifmedia = &sc->ifmedia; 1852 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1853 if (sc->ti_copper) { 1854 /* 1855 * Copper cards allow manual 10/100 mode selection, 1856 * but not manual 1000baseT mode selection. Why? 1857 * Because currently there's no way to specify the 1858 * master/slave setting through the firmware interface, 1859 * so Alteon decided to just bag it and handle it 1860 * via autonegotiation. 1861 */ 1862 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 1863 ifmedia_add(&sc->ifmedia, 1864 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1865 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 1866 ifmedia_add(&sc->ifmedia, 1867 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1868 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 1869 ifmedia_add(&sc->ifmedia, 1870 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1871 } else { 1872 /* Fiber cards don't support 10/100 modes. */ 1873 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 1874 ifmedia_add(&sc->ifmedia, 1875 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 1876 } 1877 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1878 ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_AUTO); 1879 1880 /* 1881 * Call MI attach routines. 1882 */ 1883 if_attach(ifp); 1884 if_deferred_start_init(ifp, NULL); 1885 ether_ifattach(ifp, eaddr); 1886 1887 /* 1888 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1889 * doing do could allow DMA to corrupt kernel memory during the 1890 * reboot before the driver initializes. 1891 */ 1892 if (pmf_device_register1(self, NULL, NULL, ti_shutdown)) 1893 pmf_class_network_register(self, ifp); 1894 else 1895 aprint_error_dev(self, "couldn't establish power handler\n"); 1896 1897 return; 1898 fail2: 1899 pci_intr_disestablish(pc, sc->sc_ih); 1900 return; 1901 } 1902 1903 /* 1904 * Frame reception handling. This is called if there's a frame 1905 * on the receive return list. 1906 * 1907 * Note: we have to be able to handle three possibilities here: 1908 * 1) the frame is from the mini receive ring (can only happen) 1909 * on Tigon 2 boards) 1910 * 2) the frame is from the jumbo receive ring 1911 * 3) the frame is from the standard receive ring 1912 */ 1913 1914 static void 1915 ti_rxeof(struct ti_softc *sc) 1916 { 1917 struct ifnet *ifp; 1918 struct ti_cmd_desc cmd; 1919 1920 ifp = &sc->ethercom.ec_if; 1921 1922 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1923 struct ti_rx_desc *cur_rx; 1924 uint32_t rxidx; 1925 struct mbuf *m = NULL; 1926 struct ether_header *eh; 1927 bus_dmamap_t dmamap; 1928 1929 cur_rx = 1930 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1931 rxidx = cur_rx->ti_idx; 1932 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1933 1934 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1935 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1936 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1937 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1938 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1939 if_statinc(ifp, if_ierrors); 1940 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1941 continue; 1942 } 1943 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1944 == ENOBUFS) { 1945 if_statinc(ifp, if_ierrors); 1946 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1947 continue; 1948 } 1949 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1950 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1951 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1952 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1953 dmamap = sc->mini_dmamap[rxidx]; 1954 sc->mini_dmamap[rxidx] = 0; 1955 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1956 if_statinc(ifp, if_ierrors); 1957 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1958 continue; 1959 } 1960 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1961 == ENOBUFS) { 1962 if_statinc(ifp, if_ierrors); 1963 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1964 continue; 1965 } 1966 } else { 1967 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1968 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1969 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1970 dmamap = sc->std_dmamap[rxidx]; 1971 sc->std_dmamap[rxidx] = 0; 1972 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1973 if_statinc(ifp, if_ierrors); 1974 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1975 continue; 1976 } 1977 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 1978 == ENOBUFS) { 1979 if_statinc(ifp, if_ierrors); 1980 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1981 continue; 1982 } 1983 } 1984 1985 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1986 m_set_rcvif(m, ifp); 1987 1988 eh = mtod(m, struct ether_header *); 1989 switch (ntohs(eh->ether_type)) { 1990 #ifdef INET 1991 case ETHERTYPE_IP: 1992 { 1993 struct ip *ip = (struct ip *) (eh + 1); 1994 1995 /* 1996 * Note the Tigon firmware does not invert 1997 * the checksum for us, hence the XOR. 1998 */ 1999 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2000 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 2001 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2002 /* 2003 * ntohs() the constant so the compiler can 2004 * optimize... 2005 * 2006 * XXX Figure out a sane way to deal with 2007 * fragmented packets. 2008 */ 2009 if ((ip->ip_off & htons(IP_MF | IP_OFFMASK)) == 0) { 2010 switch (ip->ip_p) { 2011 case IPPROTO_TCP: 2012 m->m_pkthdr.csum_data = 2013 cur_rx->ti_tcp_udp_cksum; 2014 m->m_pkthdr.csum_flags |= 2015 M_CSUM_TCPv4 | M_CSUM_DATA; 2016 break; 2017 case IPPROTO_UDP: 2018 m->m_pkthdr.csum_data = 2019 cur_rx->ti_tcp_udp_cksum; 2020 m->m_pkthdr.csum_flags |= 2021 M_CSUM_UDPv4 | M_CSUM_DATA; 2022 break; 2023 default: 2024 /* Nothing */; 2025 } 2026 } 2027 break; 2028 } 2029 #endif 2030 default: 2031 /* Nothing. */ 2032 break; 2033 } 2034 2035 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2036 /* ti_vlan_tag also has the priority, trim it */ 2037 vlan_set_tag(m, cur_rx->ti_vlan_tag & 0x0fff); 2038 } 2039 2040 if_percpuq_enqueue(ifp->if_percpuq, m); 2041 } 2042 2043 /* Only necessary on the Tigon 1. */ 2044 if (sc->ti_hwrev == TI_HWREV_TIGON) 2045 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2046 sc->ti_rx_saved_considx); 2047 2048 TI_UPDATE_STDPROD(sc, sc->ti_std); 2049 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2050 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2051 } 2052 2053 static void 2054 ti_txeof_tigon1(struct ti_softc *sc) 2055 { 2056 struct ti_tx_desc *cur_tx = NULL; 2057 struct ifnet *ifp; 2058 struct txdmamap_pool_entry *dma; 2059 2060 ifp = &sc->ethercom.ec_if; 2061 2062 /* 2063 * Go through our tx ring and free mbufs for those 2064 * frames that have been sent. 2065 */ 2066 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2067 uint32_t idx = 0; 2068 2069 idx = sc->ti_tx_saved_considx; 2070 if (idx > 383) 2071 CSR_WRITE_4(sc, TI_WINBASE, 2072 TI_TX_RING_BASE + 6144); 2073 else if (idx > 255) 2074 CSR_WRITE_4(sc, TI_WINBASE, 2075 TI_TX_RING_BASE + 4096); 2076 else if (idx > 127) 2077 CSR_WRITE_4(sc, TI_WINBASE, 2078 TI_TX_RING_BASE + 2048); 2079 else 2080 CSR_WRITE_4(sc, TI_WINBASE, 2081 TI_TX_RING_BASE); 2082 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2083 if (cur_tx->ti_flags & TI_BDFLAG_END) 2084 if_statinc(ifp, if_opackets); 2085 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2086 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2087 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2088 2089 dma = sc->txdma[idx]; 2090 KDASSERT(dma != NULL); 2091 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2092 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2093 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2094 2095 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2096 sc->txdma[idx] = NULL; 2097 } 2098 sc->ti_txcnt--; 2099 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2100 ifp->if_timer = 0; 2101 } 2102 2103 if (cur_tx != NULL) 2104 ifp->if_flags &= ~IFF_OACTIVE; 2105 } 2106 2107 static void 2108 ti_txeof_tigon2(struct ti_softc *sc) 2109 { 2110 struct ti_tx_desc *cur_tx = NULL; 2111 struct ifnet *ifp; 2112 struct txdmamap_pool_entry *dma; 2113 int firstidx, cnt; 2114 2115 ifp = &sc->ethercom.ec_if; 2116 2117 /* 2118 * Go through our tx ring and free mbufs for those 2119 * frames that have been sent. 2120 */ 2121 firstidx = sc->ti_tx_saved_considx; 2122 cnt = 0; 2123 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2124 uint32_t idx = 0; 2125 2126 idx = sc->ti_tx_saved_considx; 2127 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2128 if (cur_tx->ti_flags & TI_BDFLAG_END) 2129 if_statinc(ifp, if_opackets); 2130 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2131 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2132 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2133 2134 dma = sc->txdma[idx]; 2135 KDASSERT(dma != NULL); 2136 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2137 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2138 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2139 2140 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2141 sc->txdma[idx] = NULL; 2142 } 2143 cnt++; 2144 sc->ti_txcnt--; 2145 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2146 ifp->if_timer = 0; 2147 } 2148 2149 if (cnt != 0) 2150 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2151 2152 if (cur_tx != NULL) 2153 ifp->if_flags &= ~IFF_OACTIVE; 2154 } 2155 2156 static int 2157 ti_intr(void *xsc) 2158 { 2159 struct ti_softc *sc; 2160 struct ifnet *ifp; 2161 2162 sc = xsc; 2163 ifp = &sc->ethercom.ec_if; 2164 2165 #ifdef notdef 2166 /* Avoid this for now -- checking this register is expensive. */ 2167 /* Make sure this is really our interrupt. */ 2168 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2169 return (0); 2170 #endif 2171 2172 /* Ack interrupt and stop others from occurring. */ 2173 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2174 2175 if (ifp->if_flags & IFF_RUNNING) { 2176 /* Check RX return ring producer/consumer */ 2177 ti_rxeof(sc); 2178 2179 /* Check TX ring producer/consumer */ 2180 (*sc->sc_tx_eof)(sc); 2181 } 2182 2183 ti_handle_events(sc); 2184 2185 /* Re-enable interrupts. */ 2186 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2187 2188 if ((ifp->if_flags & IFF_RUNNING) != 0) 2189 if_schedule_deferred_start(ifp); 2190 2191 return (1); 2192 } 2193 2194 static void 2195 ti_stats_update(struct ti_softc *sc) 2196 { 2197 struct ifnet *ifp = &sc->ethercom.ec_if; 2198 2199 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2200 2201 uint64_t collisions = 2202 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2203 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2204 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2205 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions); 2206 if_statadd(ifp, if_collisions, collisions - sc->ti_if_collisions); 2207 sc->ti_if_collisions = collisions; 2208 2209 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2210 } 2211 2212 /* 2213 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2214 * pointers to descriptors. 2215 */ 2216 static int 2217 ti_encap_tigon1(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx) 2218 { 2219 struct ti_tx_desc *f = NULL; 2220 uint32_t frag, cur, cnt = 0; 2221 struct txdmamap_pool_entry *dma; 2222 bus_dmamap_t dmamap; 2223 int error, i; 2224 uint16_t csum_flags = 0; 2225 2226 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2227 if (dma == NULL) { 2228 return ENOMEM; 2229 } 2230 dmamap = dma->dmamap; 2231 2232 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2233 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2234 if (error) { 2235 struct mbuf *m; 2236 int j = 0; 2237 for (m = m_head; m; m = m->m_next) 2238 j++; 2239 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2240 "error %d\n", m_head->m_pkthdr.len, j, error); 2241 return (ENOMEM); 2242 } 2243 2244 cur = frag = *txidx; 2245 2246 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2247 /* IP header checksum field must be 0! */ 2248 csum_flags |= TI_BDFLAG_IP_CKSUM; 2249 } 2250 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 2251 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2252 2253 /* XXX fragmented packet checksum capability? */ 2254 2255 /* 2256 * Start packing the mbufs in this chain into 2257 * the fragment pointers. Stop when we run out 2258 * of fragments or hit the end of the mbuf chain. 2259 */ 2260 for (i = 0; i < dmamap->dm_nsegs; i++) { 2261 if (frag > 383) 2262 CSR_WRITE_4(sc, TI_WINBASE, 2263 TI_TX_RING_BASE + 6144); 2264 else if (frag > 255) 2265 CSR_WRITE_4(sc, TI_WINBASE, 2266 TI_TX_RING_BASE + 4096); 2267 else if (frag > 127) 2268 CSR_WRITE_4(sc, TI_WINBASE, 2269 TI_TX_RING_BASE + 2048); 2270 else 2271 CSR_WRITE_4(sc, TI_WINBASE, 2272 TI_TX_RING_BASE); 2273 f = &sc->ti_tx_ring_nic[frag % 128]; 2274 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2275 break; 2276 TI_HOSTADDR(f->ti_addr, dmamap->dm_segs[i].ds_addr); 2277 f->ti_len = dmamap->dm_segs[i].ds_len; 2278 f->ti_flags = csum_flags; 2279 if (vlan_has_tag(m_head)) { 2280 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2281 f->ti_vlan_tag = vlan_get_tag(m_head); 2282 } else { 2283 f->ti_vlan_tag = 0; 2284 } 2285 /* 2286 * Sanity check: avoid coming within 16 descriptors 2287 * of the end of the ring. 2288 */ 2289 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2290 return (ENOBUFS); 2291 cur = frag; 2292 TI_INC(frag, TI_TX_RING_CNT); 2293 cnt++; 2294 } 2295 2296 if (i < dmamap->dm_nsegs) 2297 return (ENOBUFS); 2298 2299 if (frag == sc->ti_tx_saved_considx) 2300 return (ENOBUFS); 2301 2302 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2303 TI_BDFLAG_END; 2304 2305 /* Sync the packet's DMA map. */ 2306 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2307 BUS_DMASYNC_PREWRITE); 2308 2309 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2310 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2311 sc->txdma[cur] = dma; 2312 sc->ti_txcnt += cnt; 2313 2314 *txidx = frag; 2315 2316 return (0); 2317 } 2318 2319 static int 2320 ti_encap_tigon2(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx) 2321 { 2322 struct ti_tx_desc *f = NULL; 2323 uint32_t frag, firstfrag, cur, cnt = 0; 2324 struct txdmamap_pool_entry *dma; 2325 bus_dmamap_t dmamap; 2326 int error, i; 2327 uint16_t csum_flags = 0; 2328 2329 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2330 if (dma == NULL) { 2331 return ENOMEM; 2332 } 2333 dmamap = dma->dmamap; 2334 2335 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2336 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2337 if (error) { 2338 struct mbuf *m; 2339 int j = 0; 2340 for (m = m_head; m; m = m->m_next) 2341 j++; 2342 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2343 "error %d\n", m_head->m_pkthdr.len, j, error); 2344 return (ENOMEM); 2345 } 2346 2347 cur = firstfrag = frag = *txidx; 2348 2349 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2350 /* IP header checksum field must be 0! */ 2351 csum_flags |= TI_BDFLAG_IP_CKSUM; 2352 } 2353 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 2354 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2355 2356 /* XXX fragmented packet checksum capability? */ 2357 2358 /* 2359 * Start packing the mbufs in this chain into 2360 * the fragment pointers. Stop when we run out 2361 * of fragments or hit the end of the mbuf chain. 2362 */ 2363 for (i = 0; i < dmamap->dm_nsegs; i++) { 2364 f = &sc->ti_rdata->ti_tx_ring[frag]; 2365 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2366 break; 2367 TI_HOSTADDR(f->ti_addr, dmamap->dm_segs[i].ds_addr); 2368 f->ti_len = dmamap->dm_segs[i].ds_len; 2369 f->ti_flags = csum_flags; 2370 if (vlan_has_tag(m_head)) { 2371 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2372 f->ti_vlan_tag = vlan_get_tag(m_head); 2373 } else { 2374 f->ti_vlan_tag = 0; 2375 } 2376 /* 2377 * Sanity check: avoid coming within 16 descriptors 2378 * of the end of the ring. 2379 */ 2380 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2381 return (ENOBUFS); 2382 cur = frag; 2383 TI_INC(frag, TI_TX_RING_CNT); 2384 cnt++; 2385 } 2386 2387 if (i < dmamap->dm_nsegs) 2388 return (ENOBUFS); 2389 2390 if (frag == sc->ti_tx_saved_considx) 2391 return (ENOBUFS); 2392 2393 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2394 2395 /* Sync the packet's DMA map. */ 2396 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2397 BUS_DMASYNC_PREWRITE); 2398 2399 /* Sync the descriptors we are using. */ 2400 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2401 2402 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2403 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2404 sc->txdma[cur] = dma; 2405 sc->ti_txcnt += cnt; 2406 2407 *txidx = frag; 2408 2409 return (0); 2410 } 2411 2412 /* 2413 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2414 * to the mbuf data regions directly in the transmit descriptors. 2415 */ 2416 static void 2417 ti_start(struct ifnet *ifp) 2418 { 2419 struct ti_softc *sc; 2420 struct mbuf *m_head = NULL; 2421 uint32_t prodidx = 0; 2422 2423 sc = ifp->if_softc; 2424 2425 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2426 2427 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2428 IFQ_POLL(&ifp->if_snd, m_head); 2429 if (m_head == NULL) 2430 break; 2431 2432 /* 2433 * Pack the data into the transmit ring. If we 2434 * don't have room, set the OACTIVE flag and wait 2435 * for the NIC to drain the ring. 2436 */ 2437 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2438 ifp->if_flags |= IFF_OACTIVE; 2439 break; 2440 } 2441 2442 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2443 2444 /* 2445 * If there's a BPF listener, bounce a copy of this frame 2446 * to him. 2447 */ 2448 bpf_mtap(ifp, m_head, BPF_D_OUT); 2449 } 2450 2451 /* Transmit */ 2452 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2453 2454 /* Set a timeout in case the chip goes out to lunch. */ 2455 ifp->if_timer = 5; 2456 } 2457 2458 static void 2459 ti_init(void *xsc) 2460 { 2461 struct ti_softc *sc = xsc; 2462 int s; 2463 2464 s = splnet(); 2465 2466 /* Cancel pending I/O and flush buffers. */ 2467 ti_stop(sc); 2468 2469 /* Init the gen info block, ring control blocks and firmware. */ 2470 if (ti_gibinit(sc)) { 2471 aprint_error_dev(sc->sc_dev, "initialization failure\n"); 2472 splx(s); 2473 return; 2474 } 2475 2476 splx(s); 2477 } 2478 2479 static void 2480 ti_init2(struct ti_softc *sc) 2481 { 2482 struct ti_cmd_desc cmd; 2483 struct ifnet *ifp; 2484 const uint8_t *m; 2485 struct ifmedia *ifm; 2486 int tmp; 2487 2488 ifp = &sc->ethercom.ec_if; 2489 2490 /* Specify MTU and interface index. */ 2491 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_unit(sc->sc_dev)); /* ??? */ 2492 2493 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2494 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2495 tmp += ETHER_VLAN_ENCAP_LEN; 2496 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2497 2498 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2499 2500 /* Load our MAC address. */ 2501 m = (const uint8_t *)CLLADDR(ifp->if_sadl); 2502 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2503 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2504 | (m[4] << 8) | m[5]); 2505 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2506 2507 /* Enable or disable promiscuous mode as needed. */ 2508 if (ifp->if_flags & IFF_PROMISC) { 2509 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2510 } else { 2511 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2512 } 2513 2514 /* Program multicast filter. */ 2515 ti_setmulti(sc); 2516 2517 /* 2518 * If this is a Tigon 1, we should tell the 2519 * firmware to use software packet filtering. 2520 */ 2521 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2522 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2523 } 2524 2525 /* Init RX ring. */ 2526 ti_init_rx_ring_std(sc); 2527 2528 /* Init jumbo RX ring. */ 2529 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2530 ti_init_rx_ring_jumbo(sc); 2531 2532 /* 2533 * If this is a Tigon 2, we can also configure the 2534 * mini ring. 2535 */ 2536 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2537 ti_init_rx_ring_mini(sc); 2538 2539 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2540 sc->ti_rx_saved_considx = 0; 2541 2542 /* Init TX ring. */ 2543 ti_init_tx_ring(sc); 2544 2545 /* Tell firmware we're alive. */ 2546 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2547 2548 /* Enable host interrupts. */ 2549 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2550 2551 ifp->if_flags |= IFF_RUNNING; 2552 ifp->if_flags &= ~IFF_OACTIVE; 2553 2554 /* 2555 * Make sure to set media properly. We have to do this 2556 * here since we have to issue commands in order to set 2557 * the link negotiation and we can't issue commands until 2558 * the firmware is running. 2559 */ 2560 ifm = &sc->ifmedia; 2561 tmp = ifm->ifm_media; 2562 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2563 ti_ifmedia_upd(ifp); 2564 ifm->ifm_media = tmp; 2565 } 2566 2567 /* 2568 * Set media options. 2569 */ 2570 static int 2571 ti_ifmedia_upd(struct ifnet *ifp) 2572 { 2573 struct ti_softc *sc; 2574 struct ifmedia *ifm; 2575 struct ti_cmd_desc cmd; 2576 2577 sc = ifp->if_softc; 2578 ifm = &sc->ifmedia; 2579 2580 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2581 return (EINVAL); 2582 2583 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2584 case IFM_AUTO: 2585 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF | TI_GLNK_1000MB | 2586 TI_GLNK_FULL_DUPLEX | TI_GLNK_RX_FLOWCTL_Y | 2587 TI_GLNK_AUTONEGENB | TI_GLNK_ENB); 2588 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB | TI_LNK_10MB | 2589 TI_LNK_FULL_DUPLEX | TI_LNK_HALF_DUPLEX | 2590 TI_LNK_AUTONEGENB | TI_LNK_ENB); 2591 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2592 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2593 break; 2594 case IFM_1000_SX: 2595 case IFM_1000_T: 2596 if ((ifm->ifm_media & IFM_FDX) != 0) { 2597 CSR_WRITE_4(sc, TI_GCR_GLINK, 2598 TI_GLNK_PREF | TI_GLNK_1000MB | TI_GLNK_FULL_DUPLEX 2599 | TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB); 2600 } else { 2601 CSR_WRITE_4(sc, TI_GCR_GLINK, 2602 TI_GLNK_PREF | TI_GLNK_1000MB | 2603 TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB); 2604 } 2605 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2606 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2607 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2608 break; 2609 case IFM_100_FX: 2610 case IFM_10_FL: 2611 case IFM_100_TX: 2612 case IFM_10_T: 2613 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2614 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB | TI_LNK_PREF); 2615 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2616 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2617 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2618 } else { 2619 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2620 } 2621 if ((ifm->ifm_media & IFM_FDX) != 0) { 2622 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2623 } else { 2624 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2625 } 2626 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2627 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2628 break; 2629 } 2630 2631 sc->ethercom.ec_if.if_baudrate = 2632 ifmedia_baudrate(ifm->ifm_media); 2633 2634 return (0); 2635 } 2636 2637 /* 2638 * Report current media status. 2639 */ 2640 static void 2641 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2642 { 2643 struct ti_softc *sc; 2644 uint32_t media = 0; 2645 2646 sc = ifp->if_softc; 2647 2648 ifmr->ifm_status = IFM_AVALID; 2649 ifmr->ifm_active = IFM_ETHER; 2650 2651 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2652 return; 2653 2654 ifmr->ifm_status |= IFM_ACTIVE; 2655 2656 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2657 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2658 if (sc->ti_copper) 2659 ifmr->ifm_active |= IFM_1000_T; 2660 else 2661 ifmr->ifm_active |= IFM_1000_SX; 2662 if (media & TI_GLNK_FULL_DUPLEX) 2663 ifmr->ifm_active |= IFM_FDX; 2664 else 2665 ifmr->ifm_active |= IFM_HDX; 2666 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2667 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2668 if (sc->ti_copper) { 2669 if (media & TI_LNK_100MB) 2670 ifmr->ifm_active |= IFM_100_TX; 2671 if (media & TI_LNK_10MB) 2672 ifmr->ifm_active |= IFM_10_T; 2673 } else { 2674 if (media & TI_LNK_100MB) 2675 ifmr->ifm_active |= IFM_100_FX; 2676 if (media & TI_LNK_10MB) 2677 ifmr->ifm_active |= IFM_10_FL; 2678 } 2679 if (media & TI_LNK_FULL_DUPLEX) 2680 ifmr->ifm_active |= IFM_FDX; 2681 if (media & TI_LNK_HALF_DUPLEX) 2682 ifmr->ifm_active |= IFM_HDX; 2683 } 2684 2685 sc->ethercom.ec_if.if_baudrate = 2686 ifmedia_baudrate(sc->ifmedia.ifm_media); 2687 } 2688 2689 static int 2690 ti_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2691 { 2692 struct ifaddr *ifa = (struct ifaddr *) data; 2693 struct ti_softc *sc = ifp->if_softc; 2694 2695 if ((ifp->if_flags & IFF_UP) == 0) { 2696 ifp->if_flags |= IFF_UP; 2697 ti_init(sc); 2698 } 2699 2700 switch (cmd) { 2701 case SIOCINITIFADDR: 2702 2703 switch (ifa->ifa_addr->sa_family) { 2704 #ifdef INET 2705 case AF_INET: 2706 arp_ifinit(ifp, ifa); 2707 break; 2708 #endif 2709 default: 2710 break; 2711 } 2712 break; 2713 2714 default: 2715 return (EINVAL); 2716 } 2717 2718 return (0); 2719 } 2720 2721 static int 2722 ti_ioctl(struct ifnet *ifp, u_long command, void *data) 2723 { 2724 struct ti_softc *sc = ifp->if_softc; 2725 struct ifreq *ifr = (struct ifreq *) data; 2726 int s, error = 0; 2727 struct ti_cmd_desc cmd; 2728 2729 s = splnet(); 2730 2731 switch (command) { 2732 case SIOCINITIFADDR: 2733 error = ti_ether_ioctl(ifp, command, data); 2734 break; 2735 case SIOCSIFMTU: 2736 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 2737 error = EINVAL; 2738 else if ((error = ifioctl_common(ifp, command, data)) 2739 == ENETRESET) { 2740 ti_init(sc); 2741 error = 0; 2742 } 2743 break; 2744 case SIOCSIFFLAGS: 2745 if ((error = ifioctl_common(ifp, command, data)) != 0) 2746 break; 2747 if (ifp->if_flags & IFF_UP) { 2748 /* 2749 * If only the state of the PROMISC flag changed, 2750 * then just use the 'set promisc mode' command 2751 * instead of reinitializing the entire NIC. Doing 2752 * a full re-init means reloading the firmware and 2753 * waiting for it to start up, which may take a 2754 * second or two. 2755 */ 2756 if (ifp->if_flags & IFF_RUNNING && 2757 ifp->if_flags & IFF_PROMISC && 2758 !(sc->ti_if_flags & IFF_PROMISC)) { 2759 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2760 TI_CMD_CODE_PROMISC_ENB, 0); 2761 } else if (ifp->if_flags & IFF_RUNNING && 2762 !(ifp->if_flags & IFF_PROMISC) && 2763 sc->ti_if_flags & IFF_PROMISC) { 2764 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2765 TI_CMD_CODE_PROMISC_DIS, 0); 2766 } else 2767 ti_init(sc); 2768 } else { 2769 if (ifp->if_flags & IFF_RUNNING) { 2770 ti_stop(sc); 2771 } 2772 } 2773 sc->ti_if_flags = ifp->if_flags; 2774 error = 0; 2775 break; 2776 default: 2777 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 2778 break; 2779 2780 error = 0; 2781 2782 if (command == SIOCSIFCAP) 2783 ti_init(sc); 2784 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 2785 ; 2786 else if (ifp->if_flags & IFF_RUNNING) 2787 ti_setmulti(sc); 2788 break; 2789 } 2790 2791 (void)splx(s); 2792 2793 return (error); 2794 } 2795 2796 static void 2797 ti_watchdog(struct ifnet *ifp) 2798 { 2799 struct ti_softc *sc; 2800 2801 sc = ifp->if_softc; 2802 2803 aprint_error_dev(sc->sc_dev, "watchdog timeout -- resetting\n"); 2804 ti_stop(sc); 2805 ti_init(sc); 2806 2807 if_statinc(ifp, if_oerrors); 2808 } 2809 2810 /* 2811 * Stop the adapter and free any mbufs allocated to the 2812 * RX and TX lists. 2813 */ 2814 static void 2815 ti_stop(struct ti_softc *sc) 2816 { 2817 struct ifnet *ifp; 2818 struct ti_cmd_desc cmd; 2819 2820 ifp = &sc->ethercom.ec_if; 2821 2822 /* Disable host interrupts. */ 2823 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2824 /* 2825 * Tell firmware we're shutting down. 2826 */ 2827 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2828 2829 /* Halt and reinitialize. */ 2830 ti_chipinit(sc); 2831 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2832 ti_chipinit(sc); 2833 2834 /* Free the RX lists. */ 2835 ti_free_rx_ring_std(sc); 2836 2837 /* Free jumbo RX list. */ 2838 ti_free_rx_ring_jumbo(sc); 2839 2840 /* Free mini RX list. */ 2841 ti_free_rx_ring_mini(sc); 2842 2843 /* Free TX buffers. */ 2844 ti_free_tx_ring(sc); 2845 2846 sc->ti_ev_prodidx.ti_idx = 0; 2847 sc->ti_return_prodidx.ti_idx = 0; 2848 sc->ti_tx_considx.ti_idx = 0; 2849 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2850 2851 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2852 } 2853 2854 /* 2855 * Stop all chip I/O so that the kernel's probe routines don't 2856 * get confused by errant DMAs when rebooting. 2857 */ 2858 static bool 2859 ti_shutdown(device_t self, int howto) 2860 { 2861 struct ti_softc *sc; 2862 2863 sc = device_private(self); 2864 ti_chipinit(sc); 2865 2866 return true; 2867 } 2868
Indexes created Fri Sep 26 20:09:58 GMT 2025