if_ti.c revision 1.124
1 /* $NetBSD: if_ti.c,v 1.124 2024/07/05 04:31:51 rin Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring descriptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.124 2024/07/05 04:31:51 rin Exp $"); 85 86 #include "opt_inet.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/queue.h> 96 #include <sys/device.h> 97 #include <sys/reboot.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/if_ether.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #include <netinet/in_systm.h> 111 #include <netinet/ip.h> 112 #endif 113 114 115 #include <sys/bus.h> 116 117 #include <dev/pci/pcireg.h> 118 #include <dev/pci/pcivar.h> 119 #include <dev/pci/pcidevs.h> 120 121 #include <dev/pci/if_tireg.h> 122 123 #include <dev/microcode/tigon/ti_fw.h> 124 #include <dev/microcode/tigon/ti_fw2.h> 125 126 /* 127 * Various supported device vendors/types and their names. 128 */ 129 130 static const struct ti_type ti_devs[] = { 131 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 132 "Alteon AceNIC 1000BASE-SX Ethernet" }, 133 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 134 "Alteon AceNIC 1000BASE-T Ethernet" }, 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 136 "3Com 3c985-SX Gigabit Ethernet" }, 137 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 138 "Netgear GA620 1000BASE-SX Ethernet" }, 139 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 140 "Netgear GA620 1000BASE-T Ethernet" }, 141 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 142 "Silicon Graphics Gigabit Ethernet" }, 143 { PCI_VENDOR_DEC, PCI_PRODUCT_DEC_PN9000SX, 144 "Farallon PN9000SX Gigabit Ethernet" }, 145 { 0, 0, NULL } 146 }; 147 148 static const struct ti_type *ti_type_match(struct pci_attach_args *); 149 static int ti_probe(device_t, cfdata_t, void *); 150 static void ti_attach(device_t, device_t, void *); 151 static bool ti_shutdown(device_t, int); 152 static void ti_txeof_tigon1(struct ti_softc *); 153 static void ti_txeof_tigon2(struct ti_softc *); 154 static void ti_rxeof(struct ti_softc *); 155 156 static void ti_stats_update(struct ti_softc *); 157 static int ti_encap_tigon1(struct ti_softc *, struct mbuf *, uint32_t *); 158 static int ti_encap_tigon2(struct ti_softc *, struct mbuf *, uint32_t *); 159 160 static int ti_intr(void *); 161 static void ti_start(struct ifnet *); 162 static int ti_ioctl(struct ifnet *, u_long, void *); 163 static void ti_init(void *); 164 static void ti_init2(struct ti_softc *); 165 static void ti_stop(struct ti_softc *); 166 static void ti_watchdog(struct ifnet *); 167 static int ti_ifmedia_upd(struct ifnet *); 168 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 169 170 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 171 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 172 static int ti_read_eeprom(struct ti_softc *, void *, int, int); 173 174 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 175 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 176 static void ti_setmulti(struct ti_softc *); 177 178 static void ti_mem(struct ti_softc *, uint32_t, uint32_t, const void *); 179 static void ti_loadfw(struct ti_softc *); 180 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 181 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, void *, int); 182 static void ti_handle_events(struct ti_softc *); 183 static int ti_alloc_jumbo_mem(struct ti_softc *); 184 static void *ti_jalloc(struct ti_softc *); 185 static void ti_jfree(struct mbuf *, void *, size_t, void *); 186 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 187 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 188 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 189 static int ti_init_rx_ring_std(struct ti_softc *); 190 static void ti_free_rx_ring_std(struct ti_softc *); 191 static int ti_init_rx_ring_jumbo(struct ti_softc *); 192 static void ti_free_rx_ring_jumbo(struct ti_softc *); 193 static int ti_init_rx_ring_mini(struct ti_softc *); 194 static void ti_free_rx_ring_mini(struct ti_softc *); 195 static void ti_free_tx_ring(struct ti_softc *); 196 static int ti_init_tx_ring(struct ti_softc *); 197 198 static int ti_64bitslot_war(struct ti_softc *); 199 static int ti_chipinit(struct ti_softc *); 200 static int ti_gibinit(struct ti_softc *); 201 202 static int ti_ether_ioctl(struct ifnet *, u_long, void *); 203 204 CFATTACH_DECL_NEW(ti, sizeof(struct ti_softc), 205 ti_probe, ti_attach, NULL, NULL); 206 207 /* 208 * Send an instruction or address to the EEPROM, check for ACK. 209 */ 210 static uint32_t 211 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 212 { 213 int i, ack = 0; 214 215 /* 216 * Make sure we're in TX mode. 217 */ 218 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 219 220 /* 221 * Feed in each bit and strobe the clock. 222 */ 223 for (i = 0x80; i; i >>= 1) { 224 if (byte & i) { 225 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 226 } else { 227 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 228 } 229 DELAY(1); 230 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 231 DELAY(1); 232 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 233 } 234 235 /* 236 * Turn off TX mode. 237 */ 238 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 239 240 /* 241 * Check for ack. 242 */ 243 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 244 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 245 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 246 247 return (ack); 248 } 249 250 /* 251 * Read a byte of data stored in the EEPROM at address 'addr.' 252 * We have to send two address bytes since the EEPROM can hold 253 * more than 256 bytes of data. 254 */ 255 static uint8_t 256 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 257 { 258 int i; 259 uint8_t byte = 0; 260 261 EEPROM_START(); 262 263 /* 264 * Send write control code to EEPROM. 265 */ 266 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 267 printf("%s: failed to send write command, status: %x\n", 268 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 269 return (1); 270 } 271 272 /* 273 * Send first byte of address of byte we want to read. 274 */ 275 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 276 printf("%s: failed to send address, status: %x\n", 277 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 278 return (1); 279 } 280 /* 281 * Send second byte address of byte we want to read. 282 */ 283 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 284 printf("%s: failed to send address, status: %x\n", 285 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 286 return (1); 287 } 288 289 EEPROM_STOP(); 290 EEPROM_START(); 291 /* 292 * Send read control code to EEPROM. 293 */ 294 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 295 printf("%s: failed to send read command, status: %x\n", 296 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 297 return (1); 298 } 299 300 /* 301 * Start reading bits from EEPROM. 302 */ 303 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 304 for (i = 0x80; i; i >>= 1) { 305 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 306 DELAY(1); 307 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 308 byte |= i; 309 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 310 DELAY(1); 311 } 312 313 EEPROM_STOP(); 314 315 /* 316 * No ACK generated for read, so just return byte. 317 */ 318 319 *dest = byte; 320 321 return (0); 322 } 323 324 /* 325 * Read a sequence of bytes from the EEPROM. 326 */ 327 static int 328 ti_read_eeprom(struct ti_softc *sc, void *destv, int off, int cnt) 329 { 330 char *dest = destv; 331 int err = 0, i; 332 uint8_t byte = 0; 333 334 for (i = 0; i < cnt; i++) { 335 err = ti_eeprom_getbyte(sc, off + i, &byte); 336 if (err) 337 break; 338 *(dest + i) = byte; 339 } 340 341 return (err ? 1 : 0); 342 } 343 344 /* 345 * NIC memory access function. Can be used to either clear a section 346 * of NIC local memory or (if tbuf is non-NULL) copy data into it. 347 */ 348 static void 349 ti_mem(struct ti_softc *sc, uint32_t addr, uint32_t len, const void *xbuf) 350 { 351 int segptr, segsize, cnt; 352 const void *ptr; 353 354 segptr = addr; 355 cnt = len; 356 ptr = xbuf; 357 358 while (cnt) { 359 if (cnt < TI_WINLEN) 360 segsize = cnt; 361 else 362 segsize = TI_WINLEN - (segptr % TI_WINLEN); 363 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 364 if (xbuf == NULL) { 365 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 366 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 367 segsize / 4); 368 } else { 369 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 370 bus_space_write_region_stream_4(sc->ti_btag, 371 sc->ti_bhandle, 372 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 373 (const uint32_t *)ptr, segsize / 4); 374 #else 375 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 376 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 377 (const uint32_t *)ptr, segsize / 4); 378 #endif 379 ptr = (const char *)ptr + segsize; 380 } 381 segptr += segsize; 382 cnt -= segsize; 383 } 384 385 return; 386 } 387 388 /* 389 * Load firmware image into the NIC. Check that the firmware revision 390 * is acceptable and see if we want the firmware for the Tigon 1 or 391 * Tigon 2. 392 */ 393 static void 394 ti_loadfw(struct ti_softc *sc) 395 { 396 switch (sc->ti_hwrev) { 397 case TI_HWREV_TIGON: 398 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 399 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 400 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 401 printf("%s: firmware revision mismatch; want " 402 "%d.%d.%d, got %d.%d.%d\n", device_xname(sc->sc_dev), 403 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 404 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 405 tigonFwReleaseMinor, tigonFwReleaseFix); 406 return; 407 } 408 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 409 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 410 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, tigonFwRodata); 411 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 412 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 413 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 414 break; 415 case TI_HWREV_TIGON_II: 416 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 417 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 418 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 419 printf("%s: firmware revision mismatch; want " 420 "%d.%d.%d, got %d.%d.%d\n", device_xname(sc->sc_dev), 421 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 422 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 423 tigon2FwReleaseMinor, tigon2FwReleaseFix); 424 return; 425 } 426 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, tigon2FwText); 427 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, tigon2FwData); 428 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 429 tigon2FwRodata); 430 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 431 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 432 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 433 break; 434 default: 435 printf("%s: can't load firmware: unknown hardware rev\n", 436 device_xname(sc->sc_dev)); 437 break; 438 } 439 440 return; 441 } 442 443 /* 444 * Send the NIC a command via the command ring. 445 */ 446 static void 447 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 448 { 449 uint32_t index; 450 451 index = sc->ti_cmd_saved_prodidx; 452 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 453 TI_INC(index, TI_CMD_RING_CNT); 454 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 455 sc->ti_cmd_saved_prodidx = index; 456 } 457 458 /* 459 * Send the NIC an extended command. The 'len' parameter specifies the 460 * number of command slots to include after the initial command. 461 */ 462 static void 463 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, void *argv, int len) 464 { 465 char *arg = argv; 466 uint32_t index; 467 int i; 468 469 index = sc->ti_cmd_saved_prodidx; 470 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 471 TI_INC(index, TI_CMD_RING_CNT); 472 for (i = 0; i < len; i++) { 473 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 474 *(uint32_t *)(&arg[i * 4])); 475 TI_INC(index, TI_CMD_RING_CNT); 476 } 477 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 478 sc->ti_cmd_saved_prodidx = index; 479 } 480 481 /* 482 * Handle events that have triggered interrupts. 483 */ 484 static void 485 ti_handle_events(struct ti_softc *sc) 486 { 487 struct ti_event_desc *e; 488 489 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 490 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 491 switch (TI_EVENT_EVENT(e)) { 492 case TI_EV_LINKSTAT_CHANGED: 493 sc->ti_linkstat = TI_EVENT_CODE(e); 494 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) 495 printf("%s: 10/100 link up\n", 496 device_xname(sc->sc_dev)); 497 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 498 printf("%s: gigabit link up\n", 499 device_xname(sc->sc_dev)); 500 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 501 printf("%s: link down\n", 502 device_xname(sc->sc_dev)); 503 break; 504 case TI_EV_ERROR: 505 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 506 printf("%s: invalid command\n", 507 device_xname(sc->sc_dev)); 508 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 509 printf("%s: unknown command\n", 510 device_xname(sc->sc_dev)); 511 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 512 printf("%s: bad config data\n", 513 device_xname(sc->sc_dev)); 514 break; 515 case TI_EV_FIRMWARE_UP: 516 ti_init2(sc); 517 break; 518 case TI_EV_STATS_UPDATED: 519 ti_stats_update(sc); 520 break; 521 case TI_EV_RESET_JUMBO_RING: 522 case TI_EV_MCAST_UPDATED: 523 /* Who cares. */ 524 break; 525 default: 526 printf("%s: unknown event: %d\n", 527 device_xname(sc->sc_dev), TI_EVENT_EVENT(e)); 528 break; 529 } 530 /* Advance the consumer index. */ 531 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 532 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 533 } 534 535 return; 536 } 537 538 /* 539 * Memory management for the jumbo receive ring is a pain in the 540 * butt. We need to allocate at least 9018 bytes of space per frame, 541 * _and_ it has to be contiguous (unless you use the extended 542 * jumbo descriptor format). Using malloc() all the time won't 543 * work: malloc() allocates memory in powers of two, which means we 544 * would end up wasting a considerable amount of space by allocating 545 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 546 * to do our own memory management. 547 * 548 * The driver needs to allocate a contiguous chunk of memory at boot 549 * time. We then chop this up ourselves into 9K pieces and use them 550 * as external mbuf storage. 551 * 552 * One issue here is how much memory to allocate. The jumbo ring has 553 * 256 slots in it, but at 9K per slot than can consume over 2MB of 554 * RAM. This is a bit much, especially considering we also need 555 * RAM for the standard ring and mini ring (on the Tigon 2). To 556 * save space, we only actually allocate enough memory for 64 slots 557 * by default, which works out to between 500 and 600K. This can 558 * be tuned by changing a #define in if_tireg.h. 559 */ 560 561 static int 562 ti_alloc_jumbo_mem(struct ti_softc *sc) 563 { 564 char *ptr; 565 int i; 566 struct ti_jpool_entry *entry; 567 bus_dma_segment_t dmaseg; 568 int error, dmanseg; 569 570 /* Grab a big chunk o' storage. */ 571 if ((error = bus_dmamem_alloc(sc->sc_dmat, 572 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 573 BUS_DMA_NOWAIT)) != 0) { 574 aprint_error_dev(sc->sc_dev, 575 "can't allocate jumbo buffer, error = %d\n", error); 576 return (error); 577 } 578 579 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 580 TI_JMEM, (void **)&sc->ti_cdata.ti_jumbo_buf, 581 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 582 aprint_error_dev(sc->sc_dev, 583 "can't map jumbo buffer, error = %d\n", error); 584 return (error); 585 } 586 587 if ((error = bus_dmamap_create(sc->sc_dmat, 588 TI_JMEM, 1, 589 TI_JMEM, 0, BUS_DMA_NOWAIT, 590 &sc->jumbo_dmamap)) != 0) { 591 aprint_error_dev(sc->sc_dev, 592 "can't create jumbo buffer DMA map, error = %d\n", error); 593 return (error); 594 } 595 596 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 597 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 598 BUS_DMA_NOWAIT)) != 0) { 599 aprint_error_dev(sc->sc_dev, 600 "can't load jumbo buffer DMA map, error = %d\n", error); 601 return (error); 602 } 603 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 604 605 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 606 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 607 608 /* 609 * Now divide it up into 9K pieces and save the addresses 610 * in an array. 611 */ 612 ptr = sc->ti_cdata.ti_jumbo_buf; 613 for (i = 0; i < TI_JSLOTS; i++) { 614 sc->ti_cdata.ti_jslots[i] = ptr; 615 ptr += TI_JLEN; 616 entry = malloc(sizeof(struct ti_jpool_entry), 617 M_DEVBUF, M_WAITOK); 618 entry->slot = i; 619 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 620 jpool_entries); 621 } 622 623 return (0); 624 } 625 626 /* 627 * Allocate a jumbo buffer. 628 */ 629 static void * 630 ti_jalloc(struct ti_softc *sc) 631 { 632 struct ti_jpool_entry *entry; 633 634 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 635 636 if (entry == NULL) { 637 printf("%s: no free jumbo buffers\n", device_xname(sc->sc_dev)); 638 return (NULL); 639 } 640 641 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 642 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 643 644 return (sc->ti_cdata.ti_jslots[entry->slot]); 645 } 646 647 /* 648 * Release a jumbo buffer. 649 */ 650 static void 651 ti_jfree(struct mbuf *m, void *tbuf, size_t size, void *arg) 652 { 653 struct ti_softc *sc; 654 int i, s; 655 struct ti_jpool_entry *entry; 656 657 /* Extract the softc struct pointer. */ 658 sc = (struct ti_softc *)arg; 659 660 if (sc == NULL) 661 panic("ti_jfree: didn't get softc pointer!"); 662 663 /* calculate the slot this buffer belongs to */ 664 665 i = ((char *)tbuf 666 - (char *)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 667 668 if ((i < 0) || (i >= TI_JSLOTS)) 669 panic("ti_jfree: asked to free buffer that we don't manage!"); 670 671 s = splvm(); 672 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 673 if (entry == NULL) 674 panic("ti_jfree: buffer not in use!"); 675 entry->slot = i; 676 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 677 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 678 679 if (__predict_true(m != NULL)) 680 pool_cache_put(mb_cache, m); 681 splx(s); 682 } 683 684 685 /* 686 * Initialize a standard receive ring descriptor. 687 */ 688 static int 689 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 690 { 691 struct mbuf *m_new = NULL; 692 struct ti_rx_desc *r; 693 int error; 694 695 if (dmamap == NULL) { 696 /* if (m) panic() */ 697 698 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 699 MCLBYTES, 0, BUS_DMA_NOWAIT, 700 &dmamap)) != 0) { 701 aprint_error_dev(sc->sc_dev, 702 "can't create recv map, error = %d\n", error); 703 return (ENOMEM); 704 } 705 } 706 sc->std_dmamap[i] = dmamap; 707 708 if (m == NULL) { 709 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 710 if (m_new == NULL) { 711 aprint_error_dev(sc->sc_dev, 712 "mbuf allocation failed -- packet dropped!\n"); 713 return (ENOBUFS); 714 } 715 716 MCLGET(m_new, M_DONTWAIT); 717 if (!(m_new->m_flags & M_EXT)) { 718 aprint_error_dev(sc->sc_dev, 719 "cluster allocation failed -- packet dropped!\n"); 720 m_freem(m_new); 721 return (ENOBUFS); 722 } 723 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 724 m_adj(m_new, ETHER_ALIGN); 725 726 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 727 mtod(m_new, void *), m_new->m_len, NULL, 728 BUS_DMA_READ | BUS_DMA_NOWAIT)) != 0) { 729 aprint_error_dev(sc->sc_dev, 730 "can't load recv map, error = %d\n", error); 731 m_freem(m_new); 732 return (ENOMEM); 733 } 734 } else { 735 m_new = m; 736 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 737 m_new->m_data = m_new->m_ext.ext_buf; 738 m_adj(m_new, ETHER_ALIGN); 739 740 /* reuse the dmamap */ 741 } 742 743 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 744 r = &sc->ti_rdata->ti_rx_std_ring[i]; 745 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 746 r->ti_type = TI_BDTYPE_RECV_BD; 747 r->ti_flags = 0; 748 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 749 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 750 if (sc->ethercom.ec_if.if_capenable & 751 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 752 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 753 r->ti_len = m_new->m_len; /* == ds_len */ 754 r->ti_idx = i; 755 756 return (0); 757 } 758 759 /* 760 * Initialize a mini receive ring descriptor. This only applies to 761 * the Tigon 2. 762 */ 763 static int 764 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 765 { 766 struct mbuf *m_new = NULL; 767 struct ti_rx_desc *r; 768 int error; 769 770 if (dmamap == NULL) { 771 /* if (m) panic() */ 772 773 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 774 MHLEN, 0, BUS_DMA_NOWAIT, 775 &dmamap)) != 0) { 776 aprint_error_dev(sc->sc_dev, 777 "can't create recv map, error = %d\n", error); 778 return (ENOMEM); 779 } 780 } 781 sc->mini_dmamap[i] = dmamap; 782 783 if (m == NULL) { 784 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 785 if (m_new == NULL) { 786 aprint_error_dev(sc->sc_dev, 787 "mbuf allocation failed -- packet dropped!\n"); 788 return (ENOBUFS); 789 } 790 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 791 m_adj(m_new, ETHER_ALIGN); 792 793 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 794 mtod(m_new, void *), m_new->m_len, NULL, 795 BUS_DMA_READ | BUS_DMA_NOWAIT)) != 0) { 796 aprint_error_dev(sc->sc_dev, 797 "can't load recv map, error = %d\n", error); 798 m_freem(m_new); 799 return (ENOMEM); 800 } 801 } else { 802 m_new = m; 803 m_new->m_data = m_new->m_pktdat; 804 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 805 m_adj(m_new, ETHER_ALIGN); 806 807 /* reuse the dmamap */ 808 } 809 810 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 811 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 812 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 813 r->ti_type = TI_BDTYPE_RECV_BD; 814 r->ti_flags = TI_BDFLAG_MINI_RING; 815 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 816 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 817 if (sc->ethercom.ec_if.if_capenable & 818 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 819 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 820 r->ti_len = m_new->m_len; /* == ds_len */ 821 r->ti_idx = i; 822 823 return (0); 824 } 825 826 /* 827 * Initialize a jumbo receive ring descriptor. This allocates 828 * a jumbo buffer from the pool managed internally by the driver. 829 */ 830 static int 831 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m) 832 { 833 struct mbuf *m_new = NULL; 834 struct ti_rx_desc *r; 835 836 if (m == NULL) { 837 void * tbuf = NULL; 838 839 /* Allocate the mbuf. */ 840 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 841 if (m_new == NULL) { 842 aprint_error_dev(sc->sc_dev, 843 "mbuf allocation failed -- packet dropped!\n"); 844 return (ENOBUFS); 845 } 846 847 /* Allocate the jumbo buffer */ 848 tbuf = ti_jalloc(sc); 849 if (tbuf == NULL) { 850 m_freem(m_new); 851 aprint_error_dev(sc->sc_dev, 852 "jumbo allocation failed -- packet dropped!\n"); 853 return (ENOBUFS); 854 } 855 856 /* Attach the buffer to the mbuf. */ 857 MEXTADD(m_new, tbuf, ETHER_MAX_LEN_JUMBO, 858 M_DEVBUF, ti_jfree, sc); 859 m_new->m_flags |= M_EXT_RW; 860 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 861 } else { 862 m_new = m; 863 m_new->m_data = m_new->m_ext.ext_buf; 864 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 865 } 866 867 m_adj(m_new, ETHER_ALIGN); 868 /* Set up the descriptor. */ 869 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 870 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 871 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 872 (mtod(m_new, char *) - (char *)sc->ti_cdata.ti_jumbo_buf); 873 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 874 r->ti_flags = TI_BDFLAG_JUMBO_RING; 875 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 876 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 877 if (sc->ethercom.ec_if.if_capenable & 878 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 879 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 880 r->ti_len = m_new->m_len; 881 r->ti_idx = i; 882 883 return (0); 884 } 885 886 /* 887 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 888 * that's 1MB or memory, which is a lot. For now, we fill only the first 889 * 256 ring entries and hope that our CPU is fast enough to keep up with 890 * the NIC. 891 */ 892 static int 893 ti_init_rx_ring_std(struct ti_softc *sc) 894 { 895 int i; 896 struct ti_cmd_desc cmd; 897 898 for (i = 0; i < TI_SSLOTS; i++) { 899 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 900 return (ENOBUFS); 901 } 902 903 TI_UPDATE_STDPROD(sc, i - 1); 904 sc->ti_std = i - 1; 905 906 return (0); 907 } 908 909 static void 910 ti_free_rx_ring_std(struct ti_softc *sc) 911 { 912 int i; 913 914 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 915 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 916 /* if (sc->std_dmamap[i] == 0) panic() */ 917 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 918 sc->std_dmamap[i] = 0; 919 920 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 921 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 922 } 923 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 924 sizeof(struct ti_rx_desc)); 925 } 926 927 return; 928 } 929 930 static int 931 ti_init_rx_ring_jumbo(struct ti_softc *sc) 932 { 933 int i; 934 struct ti_cmd_desc cmd; 935 936 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 937 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 938 return (ENOBUFS); 939 } 940 941 TI_UPDATE_JUMBOPROD(sc, i - 1); 942 sc->ti_jumbo = i - 1; 943 944 return (0); 945 } 946 947 static void 948 ti_free_rx_ring_jumbo(struct ti_softc *sc) 949 { 950 int i; 951 952 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 953 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 954 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 955 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 956 sizeof(struct ti_rx_desc)); 957 } 958 959 return; 960 } 961 962 static int 963 ti_init_rx_ring_mini(struct ti_softc *sc) 964 { 965 int i; 966 967 for (i = 0; i < TI_MSLOTS; i++) { 968 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 969 return (ENOBUFS); 970 } 971 972 TI_UPDATE_MINIPROD(sc, i - 1); 973 sc->ti_mini = i - 1; 974 975 return (0); 976 } 977 978 static void 979 ti_free_rx_ring_mini(struct ti_softc *sc) 980 { 981 int i; 982 983 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 984 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 985 /* if (sc->mini_dmamap[i] == 0) panic() */ 986 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 987 sc->mini_dmamap[i] = 0; 988 989 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 990 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 991 } 992 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 993 sizeof(struct ti_rx_desc)); 994 } 995 996 return; 997 } 998 999 static void 1000 ti_free_tx_ring(struct ti_softc *sc) 1001 { 1002 int i; 1003 struct txdmamap_pool_entry *dma; 1004 1005 for (i = 0; i < TI_TX_RING_CNT; i++) { 1006 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1007 dma = sc->txdma[i]; 1008 KDASSERT(dma != NULL); 1009 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 1010 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1011 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 1012 1013 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1014 link); 1015 sc->txdma[i] = NULL; 1016 1017 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1018 sc->ti_cdata.ti_tx_chain[i] = NULL; 1019 } 1020 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1021 sizeof(struct ti_tx_desc)); 1022 } 1023 1024 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1025 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1026 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1027 free(dma, M_DEVBUF); 1028 } 1029 1030 return; 1031 } 1032 1033 static int 1034 ti_init_tx_ring(struct ti_softc *sc) 1035 { 1036 int i, error; 1037 bus_dmamap_t dmamap; 1038 struct txdmamap_pool_entry *dma; 1039 1040 sc->ti_txcnt = 0; 1041 sc->ti_tx_saved_considx = 0; 1042 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1043 1044 SIMPLEQ_INIT(&sc->txdma_list); 1045 for (i = 0; i < TI_RSLOTS; i++) { 1046 /* I've seen mbufs with 30 fragments. */ 1047 if ((error = bus_dmamap_create(sc->sc_dmat, 1048 ETHER_MAX_LEN_JUMBO, 40, ETHER_MAX_LEN_JUMBO, 0, 1049 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1050 aprint_error_dev(sc->sc_dev, 1051 "can't create tx map, error = %d\n", error); 1052 return (ENOMEM); 1053 } 1054 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1055 if (!dma) { 1056 aprint_error_dev(sc->sc_dev, 1057 "can't alloc txdmamap_pool_entry\n"); 1058 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1059 return (ENOMEM); 1060 } 1061 dma->dmamap = dmamap; 1062 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1063 } 1064 1065 return (0); 1066 } 1067 1068 /* 1069 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1070 * but we have to support the old way too so that Tigon 1 cards will 1071 * work. 1072 */ 1073 static void 1074 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1075 { 1076 struct ti_cmd_desc cmd; 1077 uint16_t *m; 1078 uint32_t ext[2] = {0, 0}; 1079 1080 m = (uint16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1081 1082 switch (sc->ti_hwrev) { 1083 case TI_HWREV_TIGON: 1084 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1085 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1086 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1087 break; 1088 case TI_HWREV_TIGON_II: 1089 ext[0] = htons(m[0]); 1090 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1091 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (void *)&ext, 2); 1092 break; 1093 default: 1094 printf("%s: unknown hwrev\n", device_xname(sc->sc_dev)); 1095 break; 1096 } 1097 1098 return; 1099 } 1100 1101 static void 1102 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1103 { 1104 struct ti_cmd_desc cmd; 1105 uint16_t *m; 1106 uint32_t ext[2] = {0, 0}; 1107 1108 m = (uint16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1109 1110 switch (sc->ti_hwrev) { 1111 case TI_HWREV_TIGON: 1112 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1113 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1114 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1115 break; 1116 case TI_HWREV_TIGON_II: 1117 ext[0] = htons(m[0]); 1118 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1119 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (void *)&ext, 2); 1120 break; 1121 default: 1122 printf("%s: unknown hwrev\n", device_xname(sc->sc_dev)); 1123 break; 1124 } 1125 1126 return; 1127 } 1128 1129 /* 1130 * Configure the Tigon's multicast address filter. 1131 * 1132 * The actual multicast table management is a bit of a pain, thanks to 1133 * slight brain damage on the part of both Alteon and us. With our 1134 * multicast code, we are only alerted when the multicast address table 1135 * changes and at that point we only have the current list of addresses: 1136 * we only know the current state, not the previous state, so we don't 1137 * actually know what addresses were removed or added. The firmware has 1138 * state, but we can't get our grubby mits on it, and there is no 'delete 1139 * all multicast addresses' command. Hence, we have to maintain our own 1140 * state so we know what addresses have been programmed into the NIC at 1141 * any given time. 1142 */ 1143 static void 1144 ti_setmulti(struct ti_softc *sc) 1145 { 1146 struct ethercom *ec = &sc->ethercom; 1147 struct ifnet *ifp = &ec->ec_if; 1148 struct ti_cmd_desc cmd; 1149 struct ti_mc_entry *mc; 1150 uint32_t intrs; 1151 struct ether_multi *enm; 1152 struct ether_multistep step; 1153 1154 /* Disable interrupts. */ 1155 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1156 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1157 1158 /* First, zot all the existing filters. */ 1159 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1160 ti_del_mcast(sc, &mc->mc_addr); 1161 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1162 free(mc, M_DEVBUF); 1163 } 1164 1165 /* 1166 * Remember all multicast addresses so that we can delete them 1167 * later. Punt if there is a range of addresses or memory shortage. 1168 */ 1169 ETHER_LOCK(ec); 1170 ETHER_FIRST_MULTI(step, ec, enm); 1171 while (enm != NULL) { 1172 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1173 ETHER_ADDR_LEN) != 0) { 1174 ETHER_UNLOCK(ec); 1175 goto allmulti; 1176 } 1177 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1178 M_NOWAIT)) == NULL) { 1179 ETHER_UNLOCK(ec); 1180 goto allmulti; 1181 } 1182 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1183 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1184 ETHER_NEXT_MULTI(step, enm); 1185 } 1186 ETHER_UNLOCK(ec); 1187 1188 /* Accept only programmed multicast addresses */ 1189 ifp->if_flags &= ~IFF_ALLMULTI; 1190 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1191 1192 /* Now program new ones. */ 1193 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1194 ti_add_mcast(sc, &mc->mc_addr); 1195 1196 /* Re-enable interrupts. */ 1197 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1198 1199 return; 1200 1201 allmulti: 1202 /* No need to keep individual multicast addresses */ 1203 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1204 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1205 free(mc, M_DEVBUF); 1206 } 1207 1208 /* Accept all multicast addresses */ 1209 ifp->if_flags |= IFF_ALLMULTI; 1210 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1211 1212 /* Re-enable interrupts. */ 1213 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1214 } 1215 1216 /* 1217 * Check to see if the BIOS has configured us for a 64 bit slot when 1218 * we aren't actually in one. If we detect this condition, we can work 1219 * around it on the Tigon 2 by setting a bit in the PCI state register, 1220 * but for the Tigon 1 we must give up and abort the interface attach. 1221 */ 1222 static int 1223 ti_64bitslot_war(struct ti_softc *sc) 1224 { 1225 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1226 CSR_WRITE_4(sc, 0x600, 0); 1227 CSR_WRITE_4(sc, 0x604, 0); 1228 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1229 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1230 if (sc->ti_hwrev == TI_HWREV_TIGON) 1231 return (EINVAL); 1232 else { 1233 TI_SETBIT(sc, TI_PCI_STATE, 1234 TI_PCISTATE_32BIT_BUS); 1235 return (0); 1236 } 1237 } 1238 } 1239 1240 return (0); 1241 } 1242 1243 /* 1244 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1245 * self-test results. 1246 */ 1247 static int 1248 ti_chipinit(struct ti_softc *sc) 1249 { 1250 uint32_t cacheline; 1251 uint32_t pci_writemax = 0; 1252 uint32_t rev; 1253 1254 /* Initialize link to down state. */ 1255 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1256 1257 /* Set endianness before we access any non-PCI registers. */ 1258 #if BYTE_ORDER == BIG_ENDIAN 1259 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1260 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1261 #else 1262 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1263 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1264 #endif 1265 1266 /* Check the ROM failed bit to see if self-tests passed. */ 1267 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1268 printf("%s: board self-diagnostics failed!\n", 1269 device_xname(sc->sc_dev)); 1270 return (ENODEV); 1271 } 1272 1273 /* Halt the CPU. */ 1274 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1275 1276 /* Figure out the hardware revision. */ 1277 rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK; 1278 switch (rev) { 1279 case TI_REV_TIGON_I: 1280 sc->ti_hwrev = TI_HWREV_TIGON; 1281 break; 1282 case TI_REV_TIGON_II: 1283 sc->ti_hwrev = TI_HWREV_TIGON_II; 1284 break; 1285 default: 1286 printf("%s: unsupported chip revision 0x%x\n", 1287 device_xname(sc->sc_dev), rev); 1288 return (ENODEV); 1289 } 1290 1291 /* Do special setup for Tigon 2. */ 1292 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1293 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1294 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1295 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1296 } 1297 1298 /* Set up the PCI state register. */ 1299 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD | TI_PCI_WRITE_CMD); 1300 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1301 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1302 } 1303 1304 /* Clear the read/write max DMA parameters. */ 1305 TI_CLRBIT(sc, TI_PCI_STATE, 1306 (TI_PCISTATE_WRITE_MAXDMA | TI_PCISTATE_READ_MAXDMA)); 1307 1308 /* Get cache line size. */ 1309 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1310 1311 /* 1312 * If the system has set enabled the PCI memory write 1313 * and invalidate command in the command register, set 1314 * the write max parameter accordingly. This is necessary 1315 * to use MWI with the Tigon 2. 1316 */ 1317 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1318 & PCI_COMMAND_INVALIDATE_ENABLE) { 1319 switch (cacheline) { 1320 case 1: 1321 case 4: 1322 case 8: 1323 case 16: 1324 case 32: 1325 case 64: 1326 break; 1327 default: 1328 /* Disable PCI memory write and invalidate. */ 1329 if (bootverbose) 1330 printf("%s: cache line size %d not " 1331 "supported; disabling PCI MWI\n", 1332 device_xname(sc->sc_dev), cacheline); 1333 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1334 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1335 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1336 break; 1337 } 1338 } 1339 1340 #ifdef __brokenalpha__ 1341 /* 1342 * From the Alteon sample driver: 1343 * Must insure that we do not cross an 8K (bytes) boundary 1344 * for DMA reads. Our highest limit is 1K bytes. This is a 1345 * restriction on some ALPHA platforms with early revision 1346 * 21174 PCI chipsets, such as the AlphaPC 164lx 1347 */ 1348 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax | TI_PCI_READMAX_1024); 1349 #else 1350 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1351 #endif 1352 1353 /* This sets the min dma param all the way up (0xff). */ 1354 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1355 1356 /* Configure DMA variables. */ 1357 #if BYTE_ORDER == BIG_ENDIAN 1358 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1359 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1360 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1361 TI_OPMODE_DONT_FRAG_JUMBO); 1362 #else 1363 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA | 1364 TI_OPMODE_WORDSWAP_BD | TI_OPMODE_DONT_FRAG_JUMBO | 1365 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB); 1366 #endif 1367 1368 /* 1369 * Only allow 1 DMA channel to be active at a time. 1370 * I don't think this is a good idea, but without it 1371 * the firmware racks up lots of nicDmaReadRingFull 1372 * errors. 1373 * Incompatible with hardware assisted checksums. 1374 */ 1375 if ((sc->ethercom.ec_if.if_capenable & 1376 (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1377 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1378 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx)) == 0) 1379 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1380 1381 /* Recommended settings from Tigon manual. */ 1382 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1383 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1384 1385 if (ti_64bitslot_war(sc)) { 1386 printf("%s: bios thinks we're in a 64 bit slot, " 1387 "but we aren't", device_xname(sc->sc_dev)); 1388 return (EINVAL); 1389 } 1390 1391 return (0); 1392 } 1393 1394 /* 1395 * Initialize the general information block and firmware, and 1396 * start the CPU(s) running. 1397 */ 1398 static int 1399 ti_gibinit(struct ti_softc *sc) 1400 { 1401 struct ti_rcb *rcb; 1402 int i; 1403 struct ifnet *ifp; 1404 1405 ifp = &sc->ethercom.ec_if; 1406 1407 /* Disable interrupts for now. */ 1408 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1409 1410 /* Tell the chip where to find the general information block. */ 1411 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1412 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1413 1414 /* Load the firmware into SRAM. */ 1415 ti_loadfw(sc); 1416 1417 /* Set up the contents of the general info and ring control blocks. */ 1418 1419 /* Set up the event ring and producer pointer. */ 1420 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1421 1422 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1423 rcb->ti_flags = 0; 1424 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1425 TI_CDEVPRODADDR(sc); 1426 1427 sc->ti_ev_prodidx.ti_idx = 0; 1428 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1429 sc->ti_ev_saved_considx = 0; 1430 1431 /* Set up the command ring and producer mailbox. */ 1432 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1433 1434 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1435 rcb->ti_flags = 0; 1436 rcb->ti_max_len = 0; 1437 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1438 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1439 } 1440 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1441 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1442 sc->ti_cmd_saved_prodidx = 0; 1443 1444 /* 1445 * Assign the address of the stats refresh buffer. 1446 * We re-use the current stats buffer for this to 1447 * conserve memory. 1448 */ 1449 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1450 TI_CDSTATSADDR(sc); 1451 1452 /* Set up the standard receive ring. */ 1453 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1454 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1455 rcb->ti_max_len = ETHER_MAX_LEN; 1456 rcb->ti_flags = 0; 1457 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1458 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1459 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1460 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1461 if (VLAN_ATTACHED(&sc->ethercom)) 1462 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1463 1464 /* Set up the jumbo receive ring. */ 1465 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1466 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1467 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1468 rcb->ti_flags = 0; 1469 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1470 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1471 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1472 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1473 if (VLAN_ATTACHED(&sc->ethercom)) 1474 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1475 1476 /* 1477 * Set up the mini ring. Only activated on the 1478 * Tigon 2 but the slot in the config block is 1479 * still there on the Tigon 1. 1480 */ 1481 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1482 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1483 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1484 if (sc->ti_hwrev == TI_HWREV_TIGON) 1485 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1486 else 1487 rcb->ti_flags = 0; 1488 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1489 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1490 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1491 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1492 if (VLAN_ATTACHED(&sc->ethercom)) 1493 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1494 1495 /* 1496 * Set up the receive return ring. 1497 */ 1498 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1499 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1500 rcb->ti_flags = 0; 1501 rcb->ti_max_len = TI_RETURN_RING_CNT; 1502 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1503 TI_CDRTNPRODADDR(sc); 1504 1505 /* 1506 * Set up the tx ring. Note: for the Tigon 2, we have the option 1507 * of putting the transmit ring in the host's address space and 1508 * letting the chip DMA it instead of leaving the ring in the NIC's 1509 * memory and accessing it through the shared memory region. We 1510 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1511 * so we have to revert to the shared memory scheme if we detect 1512 * a Tigon 1 chip. 1513 */ 1514 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1515 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1516 sc->ti_tx_ring_nic = 1517 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1518 } 1519 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1520 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1521 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1522 if (sc->ti_hwrev == TI_HWREV_TIGON) 1523 rcb->ti_flags = 0; 1524 else 1525 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1526 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) 1527 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1528 /* 1529 * When we get the packet, there is a pseudo-header seed already 1530 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1531 * compute the pseudo-header checksum again! 1532 */ 1533 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx)) 1534 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1535 TI_RCB_FLAG_NO_PHDR_CKSUM; 1536 if (VLAN_ATTACHED(&sc->ethercom)) 1537 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1538 rcb->ti_max_len = TI_TX_RING_CNT; 1539 if (sc->ti_hwrev == TI_HWREV_TIGON) 1540 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1541 else 1542 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1543 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1544 TI_CDTXCONSADDR(sc); 1545 1546 /* 1547 * We're done frobbing the General Information Block. Sync 1548 * it. Note we take care of the first stats sync here, as 1549 * well. 1550 */ 1551 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1552 1553 /* Set up tuneables */ 1554 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1555 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1556 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1557 (sc->ti_rx_coal_ticks / 10)); 1558 else 1559 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1560 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1561 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1562 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1563 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1564 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1565 1566 /* Turn interrupts on. */ 1567 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1568 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1569 1570 /* Start CPU. */ 1571 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT | TI_CPUSTATE_STEP)); 1572 1573 return (0); 1574 } 1575 1576 /* 1577 * look for id in the device list, returning the first match 1578 */ 1579 static const struct ti_type * 1580 ti_type_match(struct pci_attach_args *pa) 1581 { 1582 const struct ti_type *t; 1583 1584 t = ti_devs; 1585 while (t->ti_name != NULL) { 1586 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1587 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1588 return (t); 1589 } 1590 t++; 1591 } 1592 1593 return (NULL); 1594 } 1595 1596 /* 1597 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1598 * against our list and return its name if we find a match. 1599 */ 1600 static int 1601 ti_probe(device_t parent, cfdata_t match, void *aux) 1602 { 1603 struct pci_attach_args *pa = aux; 1604 const struct ti_type *t; 1605 1606 t = ti_type_match(pa); 1607 1608 return ((t == NULL) ? 0 : 1); 1609 } 1610 1611 static void 1612 ti_attach(device_t parent, device_t self, void *aux) 1613 { 1614 uint32_t command; 1615 struct ifnet *ifp; 1616 struct ti_softc *sc; 1617 uint8_t eaddr[ETHER_ADDR_LEN]; 1618 struct pci_attach_args *pa = aux; 1619 pci_chipset_tag_t pc = pa->pa_pc; 1620 pci_intr_handle_t ih; 1621 const char *intrstr = NULL; 1622 bus_dma_segment_t dmaseg; 1623 int error, dmanseg, nolinear; 1624 const struct ti_type *t; 1625 char intrbuf[PCI_INTRSTR_LEN]; 1626 1627 t = ti_type_match(pa); 1628 if (t == NULL) { 1629 aprint_error("ti_attach: were did the card go ?\n"); 1630 return; 1631 } 1632 1633 aprint_normal(": %s (rev. 0x%02x)\n", t->ti_name, 1634 PCI_REVISION(pa->pa_class)); 1635 1636 sc = device_private(self); 1637 sc->sc_dev = self; 1638 1639 /* 1640 * Map control/status registers. 1641 */ 1642 nolinear = 0; 1643 if (pci_mapreg_map(pa, 0x10, 1644 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1645 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1646 NULL, NULL)) { 1647 nolinear = 1; 1648 if (pci_mapreg_map(pa, 0x10, 1649 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1650 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1651 aprint_error_dev(self, "can't map memory space\n"); 1652 return; 1653 } 1654 } 1655 if (nolinear == 0) 1656 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1657 else 1658 sc->ti_vhandle = NULL; 1659 1660 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1661 command |= PCI_COMMAND_MASTER_ENABLE; 1662 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1663 1664 /* Allocate interrupt */ 1665 if (pci_intr_map(pa, &ih)) { 1666 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 1667 return; 1668 } 1669 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1670 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, ti_intr, sc, 1671 device_xname(self)); 1672 if (sc->sc_ih == NULL) { 1673 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 1674 if (intrstr != NULL) 1675 aprint_error(" at %s", intrstr); 1676 aprint_error("\n"); 1677 return; 1678 } 1679 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1680 1681 if (ti_chipinit(sc)) { 1682 aprint_error_dev(self, "chip initialization failed\n"); 1683 goto fail2; 1684 } 1685 1686 /* 1687 * Deal with some chip diffrences. 1688 */ 1689 switch (sc->ti_hwrev) { 1690 case TI_HWREV_TIGON: 1691 sc->sc_tx_encap = ti_encap_tigon1; 1692 sc->sc_tx_eof = ti_txeof_tigon1; 1693 if (nolinear == 1) 1694 aprint_error_dev(self, 1695 "memory space not mapped linear\n"); 1696 break; 1697 1698 case TI_HWREV_TIGON_II: 1699 sc->sc_tx_encap = ti_encap_tigon2; 1700 sc->sc_tx_eof = ti_txeof_tigon2; 1701 break; 1702 1703 default: 1704 aprint_error_dev(self, "Unknown chip version: %d\n", 1705 sc->ti_hwrev); 1706 goto fail2; 1707 } 1708 1709 /* Zero out the NIC's on-board SRAM. */ 1710 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1711 1712 /* Init again -- zeroing memory may have clobbered some registers. */ 1713 if (ti_chipinit(sc)) { 1714 aprint_error_dev(self, "chip initialization failed\n"); 1715 goto fail2; 1716 } 1717 1718 /* 1719 * Get station address from the EEPROM. Note: the manual states 1720 * that the MAC address is at offset 0x8c, however the data is 1721 * stored as two longwords (since that's how it's loaded into 1722 * the NIC). This means the MAC address is actually preceded 1723 * by two zero bytes. We need to skip over those. 1724 */ 1725 if (ti_read_eeprom(sc, (void *)&eaddr, 1726 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1727 aprint_error_dev(self, "failed to read station address\n"); 1728 goto fail2; 1729 } 1730 1731 /* 1732 * A Tigon chip was detected. Inform the world. 1733 */ 1734 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr)); 1735 1736 sc->sc_dmat = pa->pa_dmat; 1737 1738 /* Allocate the general information block and ring buffers. */ 1739 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1740 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1741 BUS_DMA_NOWAIT)) != 0) { 1742 aprint_error_dev(self, 1743 "can't allocate ring buffer, error = %d\n", error); 1744 goto fail2; 1745 } 1746 1747 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1748 sizeof(struct ti_ring_data), (void **)&sc->ti_rdata, 1749 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 1750 aprint_error_dev(self, 1751 "can't map ring buffer, error = %d\n", error); 1752 goto fail2; 1753 } 1754 1755 if ((error = bus_dmamap_create(sc->sc_dmat, 1756 sizeof(struct ti_ring_data), 1, 1757 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1758 &sc->info_dmamap)) != 0) { 1759 aprint_error_dev(self, 1760 "can't create ring buffer DMA map, error = %d\n", error); 1761 goto fail2; 1762 } 1763 1764 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1765 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1766 BUS_DMA_NOWAIT)) != 0) { 1767 aprint_error_dev(self, 1768 "can't load ring buffer DMA map, error = %d\n", error); 1769 goto fail2; 1770 } 1771 1772 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1773 1774 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1775 1776 /* Try to allocate memory for jumbo buffers. */ 1777 if (ti_alloc_jumbo_mem(sc)) { 1778 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 1779 goto fail2; 1780 } 1781 1782 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1783 1784 /* 1785 * We really need a better way to tell a 1000baseT card 1786 * from a 1000baseSX one, since in theory there could be 1787 * OEMed 1000baseT cards from lame vendors who aren't 1788 * clever enough to change the PCI ID. For the moment 1789 * though, the AceNIC is the only copper card available. 1790 */ 1791 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1792 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1793 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1794 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1795 sc->ti_copper = 1; 1796 else 1797 sc->ti_copper = 0; 1798 1799 /* Set default tuneable values. */ 1800 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1801 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1802 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1803 sc->ti_rx_max_coal_bds = 64; 1804 sc->ti_tx_max_coal_bds = 128; 1805 sc->ti_tx_buf_ratio = 21; 1806 1807 /* Set up ifnet structure */ 1808 ifp = &sc->ethercom.ec_if; 1809 ifp->if_softc = sc; 1810 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1811 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1812 ifp->if_ioctl = ti_ioctl; 1813 ifp->if_start = ti_start; 1814 ifp->if_watchdog = ti_watchdog; 1815 IFQ_SET_READY(&ifp->if_snd); 1816 1817 #if 0 1818 /* 1819 * XXX This is not really correct -- we don't necessarily 1820 * XXX want to queue up as many as we can transmit at the 1821 * XXX upper layer like that. Someone with a board should 1822 * XXX check to see how this affects performance. 1823 */ 1824 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1825 #endif 1826 1827 /* 1828 * We can support 802.1Q VLAN-sized frames. 1829 */ 1830 sc->ethercom.ec_capabilities |= 1831 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1832 sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 1833 1834 /* 1835 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1836 */ 1837 ifp->if_capabilities |= 1838 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1839 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1840 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1841 1842 /* Set up ifmedia support. */ 1843 sc->ethercom.ec_ifmedia = &sc->ifmedia; 1844 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1845 if (sc->ti_copper) { 1846 /* 1847 * Copper cards allow manual 10/100 mode selection, 1848 * but not manual 1000baseT mode selection. Why? 1849 * Because currently there's no way to specify the 1850 * master/slave setting through the firmware interface, 1851 * so Alteon decided to just bag it and handle it 1852 * via autonegotiation. 1853 */ 1854 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 1855 ifmedia_add(&sc->ifmedia, 1856 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1857 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 1858 ifmedia_add(&sc->ifmedia, 1859 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1860 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 1861 ifmedia_add(&sc->ifmedia, 1862 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1863 } else { 1864 /* Fiber cards don't support 10/100 modes. */ 1865 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 1866 ifmedia_add(&sc->ifmedia, 1867 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 1868 } 1869 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1870 ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_AUTO); 1871 1872 /* 1873 * Call MI attach routines. 1874 */ 1875 if_attach(ifp); 1876 if_deferred_start_init(ifp, NULL); 1877 ether_ifattach(ifp, eaddr); 1878 1879 /* 1880 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1881 * doing do could allow DMA to corrupt kernel memory during the 1882 * reboot before the driver initializes. 1883 */ 1884 if (pmf_device_register1(self, NULL, NULL, ti_shutdown)) 1885 pmf_class_network_register(self, ifp); 1886 else 1887 aprint_error_dev(self, "couldn't establish power handler\n"); 1888 1889 return; 1890 fail2: 1891 pci_intr_disestablish(pc, sc->sc_ih); 1892 return; 1893 } 1894 1895 /* 1896 * Frame reception handling. This is called if there's a frame 1897 * on the receive return list. 1898 * 1899 * Note: we have to be able to handle three possibilities here: 1900 * 1) the frame is from the mini receive ring (can only happen) 1901 * on Tigon 2 boards) 1902 * 2) the frame is from the jumbo receive ring 1903 * 3) the frame is from the standard receive ring 1904 */ 1905 1906 static void 1907 ti_rxeof(struct ti_softc *sc) 1908 { 1909 struct ifnet *ifp; 1910 struct ti_cmd_desc cmd; 1911 1912 ifp = &sc->ethercom.ec_if; 1913 1914 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1915 struct ti_rx_desc *cur_rx; 1916 uint32_t rxidx; 1917 struct mbuf *m = NULL; 1918 struct ether_header *eh; 1919 bus_dmamap_t dmamap; 1920 1921 cur_rx = 1922 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1923 rxidx = cur_rx->ti_idx; 1924 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1925 1926 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1927 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1928 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1929 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1930 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1931 if_statinc(ifp, if_ierrors); 1932 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1933 continue; 1934 } 1935 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1936 == ENOBUFS) { 1937 if_statinc(ifp, if_ierrors); 1938 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1939 continue; 1940 } 1941 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1942 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1943 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1944 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1945 dmamap = sc->mini_dmamap[rxidx]; 1946 sc->mini_dmamap[rxidx] = 0; 1947 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1948 if_statinc(ifp, if_ierrors); 1949 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1950 continue; 1951 } 1952 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1953 == ENOBUFS) { 1954 if_statinc(ifp, if_ierrors); 1955 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1956 continue; 1957 } 1958 } else { 1959 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1960 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1961 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1962 dmamap = sc->std_dmamap[rxidx]; 1963 sc->std_dmamap[rxidx] = 0; 1964 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1965 if_statinc(ifp, if_ierrors); 1966 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1967 continue; 1968 } 1969 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 1970 == ENOBUFS) { 1971 if_statinc(ifp, if_ierrors); 1972 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1973 continue; 1974 } 1975 } 1976 1977 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1978 m_set_rcvif(m, ifp); 1979 1980 eh = mtod(m, struct ether_header *); 1981 switch (ntohs(eh->ether_type)) { 1982 #ifdef INET 1983 case ETHERTYPE_IP: 1984 { 1985 struct ip *ip = (struct ip *) (eh + 1); 1986 1987 /* 1988 * Note the Tigon firmware does not invert 1989 * the checksum for us, hence the XOR. 1990 */ 1991 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1992 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 1993 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1994 /* 1995 * ntohs() the constant so the compiler can 1996 * optimize... 1997 * 1998 * XXX Figure out a sane way to deal with 1999 * fragmented packets. 2000 */ 2001 if ((ip->ip_off & htons(IP_MF | IP_OFFMASK)) == 0) { 2002 switch (ip->ip_p) { 2003 case IPPROTO_TCP: 2004 m->m_pkthdr.csum_data = 2005 cur_rx->ti_tcp_udp_cksum; 2006 m->m_pkthdr.csum_flags |= 2007 M_CSUM_TCPv4 | M_CSUM_DATA; 2008 break; 2009 case IPPROTO_UDP: 2010 m->m_pkthdr.csum_data = 2011 cur_rx->ti_tcp_udp_cksum; 2012 m->m_pkthdr.csum_flags |= 2013 M_CSUM_UDPv4 | M_CSUM_DATA; 2014 break; 2015 default: 2016 /* Nothing */; 2017 } 2018 } 2019 break; 2020 } 2021 #endif 2022 default: 2023 /* Nothing. */ 2024 break; 2025 } 2026 2027 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) 2028 vlan_set_tag(m, cur_rx->ti_vlan_tag); 2029 2030 if_percpuq_enqueue(ifp->if_percpuq, m); 2031 } 2032 2033 /* Only necessary on the Tigon 1. */ 2034 if (sc->ti_hwrev == TI_HWREV_TIGON) 2035 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2036 sc->ti_rx_saved_considx); 2037 2038 TI_UPDATE_STDPROD(sc, sc->ti_std); 2039 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2040 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2041 } 2042 2043 static void 2044 ti_txeof_tigon1(struct ti_softc *sc) 2045 { 2046 struct ti_tx_desc *cur_tx = NULL; 2047 struct ifnet *ifp; 2048 struct txdmamap_pool_entry *dma; 2049 2050 ifp = &sc->ethercom.ec_if; 2051 2052 /* 2053 * Go through our tx ring and free mbufs for those 2054 * frames that have been sent. 2055 */ 2056 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2057 uint32_t idx = 0; 2058 2059 idx = sc->ti_tx_saved_considx; 2060 if (idx > 383) 2061 CSR_WRITE_4(sc, TI_WINBASE, 2062 TI_TX_RING_BASE + 6144); 2063 else if (idx > 255) 2064 CSR_WRITE_4(sc, TI_WINBASE, 2065 TI_TX_RING_BASE + 4096); 2066 else if (idx > 127) 2067 CSR_WRITE_4(sc, TI_WINBASE, 2068 TI_TX_RING_BASE + 2048); 2069 else 2070 CSR_WRITE_4(sc, TI_WINBASE, 2071 TI_TX_RING_BASE); 2072 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2073 if (cur_tx->ti_flags & TI_BDFLAG_END) 2074 if_statinc(ifp, if_opackets); 2075 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2076 dma = sc->txdma[idx]; 2077 KDASSERT(dma != NULL); 2078 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2079 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2080 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2081 2082 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2083 sc->txdma[idx] = NULL; 2084 2085 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2086 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2087 } 2088 sc->ti_txcnt--; 2089 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2090 ifp->if_timer = 0; 2091 } 2092 2093 if (cur_tx != NULL) 2094 ifp->if_flags &= ~IFF_OACTIVE; 2095 } 2096 2097 static void 2098 ti_txeof_tigon2(struct ti_softc *sc) 2099 { 2100 struct ti_tx_desc *cur_tx = NULL; 2101 struct ifnet *ifp; 2102 struct txdmamap_pool_entry *dma; 2103 int firstidx, cnt; 2104 2105 ifp = &sc->ethercom.ec_if; 2106 2107 /* 2108 * Go through our tx ring and free mbufs for those 2109 * frames that have been sent. 2110 */ 2111 firstidx = sc->ti_tx_saved_considx; 2112 cnt = 0; 2113 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2114 uint32_t idx = 0; 2115 2116 idx = sc->ti_tx_saved_considx; 2117 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2118 if (cur_tx->ti_flags & TI_BDFLAG_END) 2119 if_statinc(ifp, if_opackets); 2120 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2121 dma = sc->txdma[idx]; 2122 KDASSERT(dma != NULL); 2123 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2124 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2125 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2126 2127 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2128 sc->txdma[idx] = NULL; 2129 2130 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2131 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2132 } 2133 cnt++; 2134 sc->ti_txcnt--; 2135 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2136 ifp->if_timer = 0; 2137 } 2138 2139 if (cnt != 0) 2140 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2141 2142 if (cur_tx != NULL) 2143 ifp->if_flags &= ~IFF_OACTIVE; 2144 } 2145 2146 static int 2147 ti_intr(void *xsc) 2148 { 2149 struct ti_softc *sc; 2150 struct ifnet *ifp; 2151 2152 sc = xsc; 2153 ifp = &sc->ethercom.ec_if; 2154 2155 #ifdef notdef 2156 /* Avoid this for now -- checking this register is expensive. */ 2157 /* Make sure this is really our interrupt. */ 2158 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2159 return (0); 2160 #endif 2161 2162 /* Ack interrupt and stop others from occurring. */ 2163 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2164 2165 if (ifp->if_flags & IFF_RUNNING) { 2166 /* Check RX return ring producer/consumer */ 2167 ti_rxeof(sc); 2168 2169 /* Check TX ring producer/consumer */ 2170 (*sc->sc_tx_eof)(sc); 2171 } 2172 2173 ti_handle_events(sc); 2174 2175 /* Re-enable interrupts. */ 2176 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2177 2178 if ((ifp->if_flags & IFF_RUNNING) != 0) 2179 if_schedule_deferred_start(ifp); 2180 2181 return (1); 2182 } 2183 2184 static void 2185 ti_stats_update(struct ti_softc *sc) 2186 { 2187 struct ifnet *ifp = &sc->ethercom.ec_if; 2188 2189 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2190 2191 uint64_t collisions = 2192 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2193 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2194 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2195 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions); 2196 if_statadd(ifp, if_collisions, collisions - sc->ti_if_collisions); 2197 sc->ti_if_collisions = collisions; 2198 2199 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2200 } 2201 2202 /* 2203 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2204 * pointers to descriptors. 2205 */ 2206 static int 2207 ti_encap_tigon1(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx) 2208 { 2209 struct ti_tx_desc *f = NULL; 2210 uint32_t frag, cur, cnt = 0; 2211 struct txdmamap_pool_entry *dma; 2212 bus_dmamap_t dmamap; 2213 int error, i; 2214 uint16_t csum_flags = 0; 2215 2216 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2217 if (dma == NULL) { 2218 return ENOMEM; 2219 } 2220 dmamap = dma->dmamap; 2221 2222 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2223 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2224 if (error) { 2225 struct mbuf *m; 2226 int j = 0; 2227 for (m = m_head; m; m = m->m_next) 2228 j++; 2229 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2230 "error %d\n", m_head->m_pkthdr.len, j, error); 2231 return (ENOMEM); 2232 } 2233 2234 cur = frag = *txidx; 2235 2236 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2237 /* IP header checksum field must be 0! */ 2238 csum_flags |= TI_BDFLAG_IP_CKSUM; 2239 } 2240 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 2241 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2242 2243 /* XXX fragmented packet checksum capability? */ 2244 2245 /* 2246 * Start packing the mbufs in this chain into 2247 * the fragment pointers. Stop when we run out 2248 * of fragments or hit the end of the mbuf chain. 2249 */ 2250 for (i = 0; i < dmamap->dm_nsegs; i++) { 2251 if (frag > 383) 2252 CSR_WRITE_4(sc, TI_WINBASE, 2253 TI_TX_RING_BASE + 6144); 2254 else if (frag > 255) 2255 CSR_WRITE_4(sc, TI_WINBASE, 2256 TI_TX_RING_BASE + 4096); 2257 else if (frag > 127) 2258 CSR_WRITE_4(sc, TI_WINBASE, 2259 TI_TX_RING_BASE + 2048); 2260 else 2261 CSR_WRITE_4(sc, TI_WINBASE, 2262 TI_TX_RING_BASE); 2263 f = &sc->ti_tx_ring_nic[frag % 128]; 2264 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2265 break; 2266 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2267 f->ti_len = dmamap->dm_segs[i].ds_len; 2268 f->ti_flags = csum_flags; 2269 if (vlan_has_tag(m_head)) { 2270 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2271 f->ti_vlan_tag = vlan_get_tag(m_head); 2272 } else { 2273 f->ti_vlan_tag = 0; 2274 } 2275 /* 2276 * Sanity check: avoid coming within 16 descriptors 2277 * of the end of the ring. 2278 */ 2279 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2280 return (ENOBUFS); 2281 cur = frag; 2282 TI_INC(frag, TI_TX_RING_CNT); 2283 cnt++; 2284 } 2285 2286 if (i < dmamap->dm_nsegs) 2287 return (ENOBUFS); 2288 2289 if (frag == sc->ti_tx_saved_considx) 2290 return (ENOBUFS); 2291 2292 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2293 TI_BDFLAG_END; 2294 2295 /* Sync the packet's DMA map. */ 2296 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2297 BUS_DMASYNC_PREWRITE); 2298 2299 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2300 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2301 sc->txdma[cur] = dma; 2302 sc->ti_txcnt += cnt; 2303 2304 *txidx = frag; 2305 2306 return (0); 2307 } 2308 2309 static int 2310 ti_encap_tigon2(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx) 2311 { 2312 struct ti_tx_desc *f = NULL; 2313 uint32_t frag, firstfrag, cur, cnt = 0; 2314 struct txdmamap_pool_entry *dma; 2315 bus_dmamap_t dmamap; 2316 int error, i; 2317 uint16_t csum_flags = 0; 2318 2319 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2320 if (dma == NULL) { 2321 return ENOMEM; 2322 } 2323 dmamap = dma->dmamap; 2324 2325 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2326 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2327 if (error) { 2328 struct mbuf *m; 2329 int j = 0; 2330 for (m = m_head; m; m = m->m_next) 2331 j++; 2332 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2333 "error %d\n", m_head->m_pkthdr.len, j, error); 2334 return (ENOMEM); 2335 } 2336 2337 cur = firstfrag = frag = *txidx; 2338 2339 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2340 /* IP header checksum field must be 0! */ 2341 csum_flags |= TI_BDFLAG_IP_CKSUM; 2342 } 2343 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 2344 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2345 2346 /* XXX fragmented packet checksum capability? */ 2347 2348 /* 2349 * Start packing the mbufs in this chain into 2350 * the fragment pointers. Stop when we run out 2351 * of fragments or hit the end of the mbuf chain. 2352 */ 2353 for (i = 0; i < dmamap->dm_nsegs; i++) { 2354 f = &sc->ti_rdata->ti_tx_ring[frag]; 2355 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2356 break; 2357 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2358 f->ti_len = dmamap->dm_segs[i].ds_len; 2359 f->ti_flags = csum_flags; 2360 if (vlan_has_tag(m_head)) { 2361 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2362 f->ti_vlan_tag = vlan_get_tag(m_head); 2363 } else { 2364 f->ti_vlan_tag = 0; 2365 } 2366 /* 2367 * Sanity check: avoid coming within 16 descriptors 2368 * of the end of the ring. 2369 */ 2370 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2371 return (ENOBUFS); 2372 cur = frag; 2373 TI_INC(frag, TI_TX_RING_CNT); 2374 cnt++; 2375 } 2376 2377 if (i < dmamap->dm_nsegs) 2378 return (ENOBUFS); 2379 2380 if (frag == sc->ti_tx_saved_considx) 2381 return (ENOBUFS); 2382 2383 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2384 2385 /* Sync the packet's DMA map. */ 2386 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2387 BUS_DMASYNC_PREWRITE); 2388 2389 /* Sync the descriptors we are using. */ 2390 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2391 2392 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2393 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2394 sc->txdma[cur] = dma; 2395 sc->ti_txcnt += cnt; 2396 2397 *txidx = frag; 2398 2399 return (0); 2400 } 2401 2402 /* 2403 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2404 * to the mbuf data regions directly in the transmit descriptors. 2405 */ 2406 static void 2407 ti_start(struct ifnet *ifp) 2408 { 2409 struct ti_softc *sc; 2410 struct mbuf *m_head = NULL; 2411 uint32_t prodidx = 0; 2412 2413 sc = ifp->if_softc; 2414 2415 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2416 2417 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2418 IFQ_POLL(&ifp->if_snd, m_head); 2419 if (m_head == NULL) 2420 break; 2421 2422 /* 2423 * Pack the data into the transmit ring. If we 2424 * don't have room, set the OACTIVE flag and wait 2425 * for the NIC to drain the ring. 2426 */ 2427 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2428 ifp->if_flags |= IFF_OACTIVE; 2429 break; 2430 } 2431 2432 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2433 2434 /* 2435 * If there's a BPF listener, bounce a copy of this frame 2436 * to him. 2437 */ 2438 bpf_mtap(ifp, m_head, BPF_D_OUT); 2439 } 2440 2441 /* Transmit */ 2442 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2443 2444 /* Set a timeout in case the chip goes out to lunch. */ 2445 ifp->if_timer = 5; 2446 } 2447 2448 static void 2449 ti_init(void *xsc) 2450 { 2451 struct ti_softc *sc = xsc; 2452 int s; 2453 2454 s = splnet(); 2455 2456 /* Cancel pending I/O and flush buffers. */ 2457 ti_stop(sc); 2458 2459 /* Init the gen info block, ring control blocks and firmware. */ 2460 if (ti_gibinit(sc)) { 2461 aprint_error_dev(sc->sc_dev, "initialization failure\n"); 2462 splx(s); 2463 return; 2464 } 2465 2466 splx(s); 2467 } 2468 2469 static void 2470 ti_init2(struct ti_softc *sc) 2471 { 2472 struct ti_cmd_desc cmd; 2473 struct ifnet *ifp; 2474 const uint8_t *m; 2475 struct ifmedia *ifm; 2476 int tmp; 2477 2478 ifp = &sc->ethercom.ec_if; 2479 2480 /* Specify MTU and interface index. */ 2481 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_unit(sc->sc_dev)); /* ??? */ 2482 2483 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2484 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2485 tmp += ETHER_VLAN_ENCAP_LEN; 2486 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2487 2488 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2489 2490 /* Load our MAC address. */ 2491 m = (const uint8_t *)CLLADDR(ifp->if_sadl); 2492 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2493 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2494 | (m[4] << 8) | m[5]); 2495 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2496 2497 /* Enable or disable promiscuous mode as needed. */ 2498 if (ifp->if_flags & IFF_PROMISC) { 2499 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2500 } else { 2501 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2502 } 2503 2504 /* Program multicast filter. */ 2505 ti_setmulti(sc); 2506 2507 /* 2508 * If this is a Tigon 1, we should tell the 2509 * firmware to use software packet filtering. 2510 */ 2511 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2512 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2513 } 2514 2515 /* Init RX ring. */ 2516 ti_init_rx_ring_std(sc); 2517 2518 /* Init jumbo RX ring. */ 2519 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2520 ti_init_rx_ring_jumbo(sc); 2521 2522 /* 2523 * If this is a Tigon 2, we can also configure the 2524 * mini ring. 2525 */ 2526 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2527 ti_init_rx_ring_mini(sc); 2528 2529 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2530 sc->ti_rx_saved_considx = 0; 2531 2532 /* Init TX ring. */ 2533 ti_init_tx_ring(sc); 2534 2535 /* Tell firmware we're alive. */ 2536 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2537 2538 /* Enable host interrupts. */ 2539 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2540 2541 ifp->if_flags |= IFF_RUNNING; 2542 ifp->if_flags &= ~IFF_OACTIVE; 2543 2544 /* 2545 * Make sure to set media properly. We have to do this 2546 * here since we have to issue commands in order to set 2547 * the link negotiation and we can't issue commands until 2548 * the firmware is running. 2549 */ 2550 ifm = &sc->ifmedia; 2551 tmp = ifm->ifm_media; 2552 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2553 ti_ifmedia_upd(ifp); 2554 ifm->ifm_media = tmp; 2555 } 2556 2557 /* 2558 * Set media options. 2559 */ 2560 static int 2561 ti_ifmedia_upd(struct ifnet *ifp) 2562 { 2563 struct ti_softc *sc; 2564 struct ifmedia *ifm; 2565 struct ti_cmd_desc cmd; 2566 2567 sc = ifp->if_softc; 2568 ifm = &sc->ifmedia; 2569 2570 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2571 return (EINVAL); 2572 2573 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2574 case IFM_AUTO: 2575 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF | TI_GLNK_1000MB | 2576 TI_GLNK_FULL_DUPLEX | TI_GLNK_RX_FLOWCTL_Y | 2577 TI_GLNK_AUTONEGENB | TI_GLNK_ENB); 2578 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB | TI_LNK_10MB | 2579 TI_LNK_FULL_DUPLEX | TI_LNK_HALF_DUPLEX | 2580 TI_LNK_AUTONEGENB | TI_LNK_ENB); 2581 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2582 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2583 break; 2584 case IFM_1000_SX: 2585 case IFM_1000_T: 2586 if ((ifm->ifm_media & IFM_FDX) != 0) { 2587 CSR_WRITE_4(sc, TI_GCR_GLINK, 2588 TI_GLNK_PREF | TI_GLNK_1000MB | TI_GLNK_FULL_DUPLEX 2589 | TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB); 2590 } else { 2591 CSR_WRITE_4(sc, TI_GCR_GLINK, 2592 TI_GLNK_PREF | TI_GLNK_1000MB | 2593 TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB); 2594 } 2595 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2596 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2597 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2598 break; 2599 case IFM_100_FX: 2600 case IFM_10_FL: 2601 case IFM_100_TX: 2602 case IFM_10_T: 2603 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2604 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB | TI_LNK_PREF); 2605 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2606 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2607 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2608 } else { 2609 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2610 } 2611 if ((ifm->ifm_media & IFM_FDX) != 0) { 2612 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2613 } else { 2614 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2615 } 2616 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2617 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2618 break; 2619 } 2620 2621 sc->ethercom.ec_if.if_baudrate = 2622 ifmedia_baudrate(ifm->ifm_media); 2623 2624 return (0); 2625 } 2626 2627 /* 2628 * Report current media status. 2629 */ 2630 static void 2631 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2632 { 2633 struct ti_softc *sc; 2634 uint32_t media = 0; 2635 2636 sc = ifp->if_softc; 2637 2638 ifmr->ifm_status = IFM_AVALID; 2639 ifmr->ifm_active = IFM_ETHER; 2640 2641 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2642 return; 2643 2644 ifmr->ifm_status |= IFM_ACTIVE; 2645 2646 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2647 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2648 if (sc->ti_copper) 2649 ifmr->ifm_active |= IFM_1000_T; 2650 else 2651 ifmr->ifm_active |= IFM_1000_SX; 2652 if (media & TI_GLNK_FULL_DUPLEX) 2653 ifmr->ifm_active |= IFM_FDX; 2654 else 2655 ifmr->ifm_active |= IFM_HDX; 2656 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2657 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2658 if (sc->ti_copper) { 2659 if (media & TI_LNK_100MB) 2660 ifmr->ifm_active |= IFM_100_TX; 2661 if (media & TI_LNK_10MB) 2662 ifmr->ifm_active |= IFM_10_T; 2663 } else { 2664 if (media & TI_LNK_100MB) 2665 ifmr->ifm_active |= IFM_100_FX; 2666 if (media & TI_LNK_10MB) 2667 ifmr->ifm_active |= IFM_10_FL; 2668 } 2669 if (media & TI_LNK_FULL_DUPLEX) 2670 ifmr->ifm_active |= IFM_FDX; 2671 if (media & TI_LNK_HALF_DUPLEX) 2672 ifmr->ifm_active |= IFM_HDX; 2673 } 2674 2675 sc->ethercom.ec_if.if_baudrate = 2676 ifmedia_baudrate(sc->ifmedia.ifm_media); 2677 } 2678 2679 static int 2680 ti_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2681 { 2682 struct ifaddr *ifa = (struct ifaddr *)data; 2683 struct ti_softc *sc = ifp->if_softc; 2684 2685 if ((ifp->if_flags & IFF_UP) == 0) { 2686 ifp->if_flags |= IFF_UP; 2687 ti_init(sc); 2688 } 2689 2690 switch (cmd) { 2691 case SIOCINITIFADDR: 2692 2693 switch (ifa->ifa_addr->sa_family) { 2694 #ifdef INET 2695 case AF_INET: 2696 arp_ifinit(ifp, ifa); 2697 break; 2698 #endif 2699 default: 2700 break; 2701 } 2702 break; 2703 2704 default: 2705 return (EINVAL); 2706 } 2707 2708 return (0); 2709 } 2710 2711 static int 2712 ti_ioctl(struct ifnet *ifp, u_long command, void *data) 2713 { 2714 struct ti_softc *sc = ifp->if_softc; 2715 struct ifreq *ifr = (struct ifreq *)data; 2716 int s, error = 0; 2717 struct ti_cmd_desc cmd; 2718 2719 s = splnet(); 2720 2721 switch (command) { 2722 case SIOCINITIFADDR: 2723 error = ti_ether_ioctl(ifp, command, data); 2724 break; 2725 case SIOCSIFMTU: 2726 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 2727 error = EINVAL; 2728 else if ((error = ifioctl_common(ifp, command, data)) 2729 == ENETRESET) { 2730 ti_init(sc); 2731 error = 0; 2732 } 2733 break; 2734 case SIOCSIFFLAGS: 2735 if ((error = ifioctl_common(ifp, command, data)) != 0) 2736 break; 2737 if (ifp->if_flags & IFF_UP) { 2738 /* 2739 * If only the state of the PROMISC flag changed, 2740 * then just use the 'set promisc mode' command 2741 * instead of reinitializing the entire NIC. Doing 2742 * a full re-init means reloading the firmware and 2743 * waiting for it to start up, which may take a 2744 * second or two. 2745 */ 2746 if (ifp->if_flags & IFF_RUNNING && 2747 ifp->if_flags & IFF_PROMISC && 2748 !(sc->ti_if_flags & IFF_PROMISC)) { 2749 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2750 TI_CMD_CODE_PROMISC_ENB, 0); 2751 } else if (ifp->if_flags & IFF_RUNNING && 2752 !(ifp->if_flags & IFF_PROMISC) && 2753 sc->ti_if_flags & IFF_PROMISC) { 2754 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2755 TI_CMD_CODE_PROMISC_DIS, 0); 2756 } else 2757 ti_init(sc); 2758 } else { 2759 if (ifp->if_flags & IFF_RUNNING) { 2760 ti_stop(sc); 2761 } 2762 } 2763 sc->ti_if_flags = ifp->if_flags; 2764 error = 0; 2765 break; 2766 default: 2767 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 2768 break; 2769 2770 error = 0; 2771 2772 if (command == SIOCSIFCAP) 2773 ti_init(sc); 2774 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 2775 ; 2776 else if (ifp->if_flags & IFF_RUNNING) 2777 ti_setmulti(sc); 2778 break; 2779 } 2780 2781 (void)splx(s); 2782 2783 return (error); 2784 } 2785 2786 static void 2787 ti_watchdog(struct ifnet *ifp) 2788 { 2789 struct ti_softc *sc; 2790 2791 sc = ifp->if_softc; 2792 2793 aprint_error_dev(sc->sc_dev, "watchdog timeout -- resetting\n"); 2794 ti_stop(sc); 2795 ti_init(sc); 2796 2797 if_statinc(ifp, if_oerrors); 2798 } 2799 2800 /* 2801 * Stop the adapter and free any mbufs allocated to the 2802 * RX and TX lists. 2803 */ 2804 static void 2805 ti_stop(struct ti_softc *sc) 2806 { 2807 struct ifnet *ifp; 2808 struct ti_cmd_desc cmd; 2809 2810 ifp = &sc->ethercom.ec_if; 2811 2812 /* Disable host interrupts. */ 2813 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2814 /* 2815 * Tell firmware we're shutting down. 2816 */ 2817 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2818 2819 /* Halt and reinitialize. */ 2820 ti_chipinit(sc); 2821 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2822 ti_chipinit(sc); 2823 2824 /* Free the RX lists. */ 2825 ti_free_rx_ring_std(sc); 2826 2827 /* Free jumbo RX list. */ 2828 ti_free_rx_ring_jumbo(sc); 2829 2830 /* Free mini RX list. */ 2831 ti_free_rx_ring_mini(sc); 2832 2833 /* Free TX buffers. */ 2834 ti_free_tx_ring(sc); 2835 2836 sc->ti_ev_prodidx.ti_idx = 0; 2837 sc->ti_return_prodidx.ti_idx = 0; 2838 sc->ti_tx_considx.ti_idx = 0; 2839 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2840 2841 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2842 } 2843 2844 /* 2845 * Stop all chip I/O so that the kernel's probe routines don't 2846 * get confused by errant DMAs when rebooting. 2847 */ 2848 static bool 2849 ti_shutdown(device_t self, int howto) 2850 { 2851 struct ti_softc *sc; 2852 2853 sc = device_private(self); 2854 ti_chipinit(sc); 2855 2856 return true; 2857 } 2858
Indexes created Fri Sep 26 20:09:58 GMT 2025