if_ti.c revision 1.3
1 /* $NetBSD: if_ti.c,v 1.3 2000/01/25 20:19:14 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include "bpfilter.h" 84 #if 0 85 #include "vlan.h" 86 #endif 87 #include "opt_inet.h" 88 #include "opt_ns.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/queue.h> 98 #include <sys/device.h> 99 100 #include <net/if.h> 101 #include <net/if_arp.h> 102 #include <net/if_ether.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 106 #if NBPFILTER > 0 107 #include <net/bpf.h> 108 #endif 109 110 #if 0 111 #if NVLAN > 0 112 #include <net/if_types.h> 113 #include <net/if_vlan_var.h> 114 #endif 115 #endif 116 117 #ifdef INET 118 #include <netinet/in.h> 119 #include <netinet/if_inarp.h> 120 #endif 121 122 #ifdef NS 123 #include <netns/ns.h> 124 #include <netns/ns_if.h> 125 #endif 126 127 #if 0 128 #include <vm/vm.h> /* for vtophys */ 129 #include <vm/pmap.h> /* for vtophys */ 130 #include <machine/clock.h> /* for DELAY */ 131 #endif 132 #include <machine/bus.h> 133 #if 0 134 #include <machine/resource.h> 135 #include <sys/bus.h> 136 #include <sys/rman.h> 137 #endif 138 139 #include <dev/pci/pcireg.h> 140 #include <dev/pci/pcivar.h> 141 #include <dev/pci/pcidevs.h> 142 143 #include <dev/pci/if_tireg.h> 144 #include <dev/pci/ti_fw.h> 145 #include <dev/pci/ti_fw2.h> 146 147 #ifdef M_HWCKSUM 148 /*#define TI_CSUM_OFFLOAD*/ 149 #endif 150 151 #define bootverbose 1 152 153 /* 154 * Various supported device vendors/types and their names. 155 */ 156 157 static struct ti_type ti_devs[] = { 158 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 159 "Alteon AceNIC Gigabit Ethernet" }, 160 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 161 "3Com 3c985-SX Gigabit Ethernet" }, 162 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 163 "Netgear GA620 Gigabit Ethernet" }, 164 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 165 "Silicon Graphics Gigabit Ethernet" }, 166 { 0, 0, NULL } 167 }; 168 169 static int ti_probe __P((struct device *, struct cfdata *, void *)); 170 static void ti_attach __P((struct device *, struct device *, void *)); 171 #if 0 172 static int ti_detach __P((device_t)); 173 #endif 174 static void ti_txeof __P((struct ti_softc *)); 175 static void ti_rxeof __P((struct ti_softc *)); 176 177 static void ti_stats_update __P((struct ti_softc *)); 178 static int ti_encap __P((struct ti_softc *, struct mbuf *, 179 u_int32_t *)); 180 181 static int ti_intr __P((void *)); 182 static void ti_start __P((struct ifnet *)); 183 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 184 static void ti_init __P((void *)); 185 static void ti_init2 __P((struct ti_softc *)); 186 static void ti_stop __P((struct ti_softc *)); 187 static void ti_watchdog __P((struct ifnet *)); 188 #if 0 189 static void ti_shutdown __P((device_t)); 190 #endif 191 static int ti_ifmedia_upd __P((struct ifnet *)); 192 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 193 194 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 195 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 196 int, u_int8_t *)); 197 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 198 199 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 200 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 201 static void ti_setmulti __P((struct ti_softc *)); 202 203 static void ti_mem __P((struct ti_softc *, u_int32_t, 204 u_int32_t, caddr_t)); 205 static void ti_loadfw __P((struct ti_softc *)); 206 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 207 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 208 caddr_t, int)); 209 static void ti_handle_events __P((struct ti_softc *)); 210 static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 211 static void *ti_jalloc __P((struct ti_softc *)); 212 static void ti_jfree __P((caddr_t, u_int, void *)); 213 #if 0 214 static void ti_jref __P((caddr_t, u_int)); 215 #endif 216 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 217 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 218 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 219 static int ti_init_rx_ring_std __P((struct ti_softc *)); 220 static void ti_free_rx_ring_std __P((struct ti_softc *)); 221 static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 222 static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 223 static int ti_init_rx_ring_mini __P((struct ti_softc *)); 224 static void ti_free_rx_ring_mini __P((struct ti_softc *)); 225 static void ti_free_tx_ring __P((struct ti_softc *)); 226 static int ti_init_tx_ring __P((struct ti_softc *)); 227 228 static int ti_64bitslot_war __P((struct ti_softc *)); 229 static int ti_chipinit __P((struct ti_softc *)); 230 static int ti_gibinit __P((struct ti_softc *)); 231 232 static int ti_ether_ioctl __P((struct ifnet *, u_long, caddr_t)); 233 234 struct cfattach ti_ca = { 235 sizeof(struct ti_softc), ti_probe, ti_attach 236 }; 237 238 /* 239 * Send an instruction or address to the EEPROM, check for ACK. 240 */ 241 static u_int32_t ti_eeprom_putbyte(sc, byte) 242 struct ti_softc *sc; 243 int byte; 244 { 245 register int i, ack = 0; 246 247 /* 248 * Make sure we're in TX mode. 249 */ 250 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 251 252 /* 253 * Feed in each bit and stobe the clock. 254 */ 255 for (i = 0x80; i; i >>= 1) { 256 if (byte & i) { 257 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 258 } else { 259 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 260 } 261 DELAY(1); 262 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 263 DELAY(1); 264 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 265 } 266 267 /* 268 * Turn off TX mode. 269 */ 270 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 271 272 /* 273 * Check for ack. 274 */ 275 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 276 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 277 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 278 279 return(ack); 280 } 281 282 /* 283 * Read a byte of data stored in the EEPROM at address 'addr.' 284 * We have to send two address bytes since the EEPROM can hold 285 * more than 256 bytes of data. 286 */ 287 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 288 struct ti_softc *sc; 289 int addr; 290 u_int8_t *dest; 291 { 292 register int i; 293 u_int8_t byte = 0; 294 295 EEPROM_START; 296 297 /* 298 * Send write control code to EEPROM. 299 */ 300 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 301 printf("%s: failed to send write command, status: %x\n", 302 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 303 return(1); 304 } 305 306 /* 307 * Send first byte of address of byte we want to read. 308 */ 309 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 310 printf("%s: failed to send address, status: %x\n", 311 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 312 return(1); 313 } 314 /* 315 * Send second byte address of byte we want to read. 316 */ 317 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 318 printf("%s: failed to send address, status: %x\n", 319 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 320 return(1); 321 } 322 323 EEPROM_STOP; 324 EEPROM_START; 325 /* 326 * Send read control code to EEPROM. 327 */ 328 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 329 printf("%s: failed to send read command, status: %x\n", 330 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 331 return(1); 332 } 333 334 /* 335 * Start reading bits from EEPROM. 336 */ 337 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 338 for (i = 0x80; i; i >>= 1) { 339 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 340 DELAY(1); 341 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 342 byte |= i; 343 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 344 DELAY(1); 345 } 346 347 EEPROM_STOP; 348 349 /* 350 * No ACK generated for read, so just return byte. 351 */ 352 353 *dest = byte; 354 355 return(0); 356 } 357 358 /* 359 * Read a sequence of bytes from the EEPROM. 360 */ 361 static int ti_read_eeprom(sc, dest, off, cnt) 362 struct ti_softc *sc; 363 caddr_t dest; 364 int off; 365 int cnt; 366 { 367 int err = 0, i; 368 u_int8_t byte = 0; 369 370 for (i = 0; i < cnt; i++) { 371 err = ti_eeprom_getbyte(sc, off + i, &byte); 372 if (err) 373 break; 374 *(dest + i) = byte; 375 } 376 377 return(err ? 1 : 0); 378 } 379 380 /* 381 * NIC memory access function. Can be used to either clear a section 382 * of NIC local memory or (if buf is non-NULL) copy data into it. 383 */ 384 static void ti_mem(sc, addr, len, buf) 385 struct ti_softc *sc; 386 u_int32_t addr, len; 387 caddr_t buf; 388 { 389 int segptr, segsize, cnt; 390 caddr_t ti_winbase, ptr; 391 392 segptr = addr; 393 cnt = len; 394 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 395 ptr = buf; 396 397 while(cnt) { 398 if (cnt < TI_WINLEN) 399 segsize = cnt; 400 else 401 segsize = TI_WINLEN - (segptr % TI_WINLEN); 402 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 403 if (buf == NULL) 404 bzero((char *)ti_winbase + (segptr & 405 (TI_WINLEN - 1)), segsize); 406 else { 407 bcopy((char *)ptr, (char *)ti_winbase + 408 (segptr & (TI_WINLEN - 1)), segsize); 409 ptr += segsize; 410 } 411 segptr += segsize; 412 cnt -= segsize; 413 } 414 415 return; 416 } 417 418 /* 419 * Load firmware image into the NIC. Check that the firmware revision 420 * is acceptable and see if we want the firmware for the Tigon 1 or 421 * Tigon 2. 422 */ 423 static void ti_loadfw(sc) 424 struct ti_softc *sc; 425 { 426 switch(sc->ti_hwrev) { 427 case TI_HWREV_TIGON: 428 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 429 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 430 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 431 printf("%s: firmware revision mismatch; want " 432 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 433 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 434 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 435 tigonFwReleaseMinor, tigonFwReleaseFix); 436 return; 437 } 438 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 439 (caddr_t)tigonFwText); 440 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 441 (caddr_t)tigonFwData); 442 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 443 (caddr_t)tigonFwRodata); 444 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 445 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 446 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 447 break; 448 case TI_HWREV_TIGON_II: 449 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 450 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 451 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 452 printf("%s: firmware revision mismatch; want " 453 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 454 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 455 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 456 tigon2FwReleaseMinor, tigon2FwReleaseFix); 457 return; 458 } 459 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 460 (caddr_t)tigon2FwText); 461 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 462 (caddr_t)tigon2FwData); 463 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 464 (caddr_t)tigon2FwRodata); 465 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 466 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 467 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 468 break; 469 default: 470 printf("%s: can't load firmware: unknown hardware rev\n", 471 sc->sc_dev.dv_xname); 472 break; 473 } 474 475 return; 476 } 477 478 /* 479 * Send the NIC a command via the command ring. 480 */ 481 static void ti_cmd(sc, cmd) 482 struct ti_softc *sc; 483 struct ti_cmd_desc *cmd; 484 { 485 u_int32_t index; 486 487 if (sc->ti_rdata->ti_cmd_ring == NULL) 488 return; 489 490 index = sc->ti_cmd_saved_prodidx; 491 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 492 TI_INC(index, TI_CMD_RING_CNT); 493 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 494 sc->ti_cmd_saved_prodidx = index; 495 496 return; 497 } 498 499 /* 500 * Send the NIC an extended command. The 'len' parameter specifies the 501 * number of command slots to include after the initial command. 502 */ 503 static void ti_cmd_ext(sc, cmd, arg, len) 504 struct ti_softc *sc; 505 struct ti_cmd_desc *cmd; 506 caddr_t arg; 507 int len; 508 { 509 u_int32_t index; 510 register int i; 511 512 if (sc->ti_rdata->ti_cmd_ring == NULL) 513 return; 514 515 index = sc->ti_cmd_saved_prodidx; 516 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 517 TI_INC(index, TI_CMD_RING_CNT); 518 for (i = 0; i < len; i++) { 519 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 520 *(u_int32_t *)(&arg[i * 4])); 521 TI_INC(index, TI_CMD_RING_CNT); 522 } 523 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 524 sc->ti_cmd_saved_prodidx = index; 525 526 return; 527 } 528 529 /* 530 * Handle events that have triggered interrupts. 531 */ 532 static void ti_handle_events(sc) 533 struct ti_softc *sc; 534 { 535 struct ti_event_desc *e; 536 537 if (sc->ti_rdata->ti_event_ring == NULL) 538 return; 539 540 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 541 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 542 switch(e->ti_event) { 543 case TI_EV_LINKSTAT_CHANGED: 544 sc->ti_linkstat = e->ti_code; 545 if (e->ti_code == TI_EV_CODE_LINK_UP) 546 printf("%s: 10/100 link up\n", 547 sc->sc_dev.dv_xname); 548 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 549 printf("%s: gigabit link up\n", 550 sc->sc_dev.dv_xname); 551 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 552 printf("%s: link down\n", 553 sc->sc_dev.dv_xname); 554 break; 555 case TI_EV_ERROR: 556 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 557 printf("%s: invalid command\n", 558 sc->sc_dev.dv_xname); 559 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 560 printf("%s: unknown command\n", 561 sc->sc_dev.dv_xname); 562 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 563 printf("%s: bad config data\n", 564 sc->sc_dev.dv_xname); 565 break; 566 case TI_EV_FIRMWARE_UP: 567 ti_init2(sc); 568 break; 569 case TI_EV_STATS_UPDATED: 570 ti_stats_update(sc); 571 break; 572 case TI_EV_RESET_JUMBO_RING: 573 case TI_EV_MCAST_UPDATED: 574 /* Who cares. */ 575 break; 576 default: 577 printf("%s: unknown event: %d\n", 578 sc->sc_dev.dv_xname, e->ti_event); 579 break; 580 } 581 /* Advance the consumer index. */ 582 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 583 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 584 } 585 586 return; 587 } 588 589 /* 590 * Memory management for the jumbo receive ring is a pain in the 591 * butt. We need to allocate at least 9018 bytes of space per frame, 592 * _and_ it has to be contiguous (unless you use the extended 593 * jumbo descriptor format). Using malloc() all the time won't 594 * work: malloc() allocates memory in powers of two, which means we 595 * would end up wasting a considerable amount of space by allocating 596 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 597 * to do our own memory management. 598 * 599 * The driver needs to allocate a contiguous chunk of memory at boot 600 * time. We then chop this up ourselves into 9K pieces and use them 601 * as external mbuf storage. 602 * 603 * One issue here is how much memory to allocate. The jumbo ring has 604 * 256 slots in it, but at 9K per slot than can consume over 2MB of 605 * RAM. This is a bit much, especially considering we also need 606 * RAM for the standard ring and mini ring (on the Tigon 2). To 607 * save space, we only actually allocate enough memory for 64 slots 608 * by default, which works out to between 500 and 600K. This can 609 * be tuned by changing a #define in if_tireg.h. 610 */ 611 612 static int ti_alloc_jumbo_mem(sc) 613 struct ti_softc *sc; 614 { 615 caddr_t ptr; 616 register int i; 617 struct ti_jpool_entry *entry; 618 bus_dma_segment_t dmaseg; 619 int error, dmanseg; 620 621 /* Grab a big chunk o' storage. */ 622 if ((error = bus_dmamem_alloc(sc->sc_dmat, 623 TI_JMEM, NBPG, 0, &dmaseg, 1, &dmanseg, 624 BUS_DMA_NOWAIT)) != 0) { 625 printf("%s: can't allocate jumbo buffer, error = %d\n", 626 sc->sc_dev.dv_xname, error); 627 return (error); 628 } 629 630 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 631 TI_JMEM, (caddr_t *)&sc->ti_cdata.ti_jumbo_buf, 632 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 633 printf("%s: can't map jumbo buffer, error = %d\n", 634 sc->sc_dev.dv_xname, error); 635 return (error); 636 } 637 638 if ((error = bus_dmamap_create(sc->sc_dmat, 639 TI_JMEM, 1, 640 TI_JMEM, 0, BUS_DMA_NOWAIT, 641 &sc->jumbo_dmamap)) != 0) { 642 printf("%s: can't create jumbo buffer DMA map, error = %d\n", 643 sc->sc_dev.dv_xname, error); 644 return (error); 645 } 646 647 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 648 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 649 BUS_DMA_NOWAIT)) != 0) { 650 printf("%s: can't load jumbo buffer DMA map, error = %d\n", 651 sc->sc_dev.dv_xname, error); 652 return (error); 653 } 654 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 655 656 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 657 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 658 659 /* 660 * Now divide it up into 9K pieces and save the addresses 661 * in an array. Note that we play an evil trick here by using 662 * the first few bytes in the buffer to hold the address 663 * of the softc structure for this interface. This is because 664 * ti_jfree() needs it, but it is called by the mbuf management 665 * code which will not pass it to us explicitly. 666 */ 667 ptr = sc->ti_cdata.ti_jumbo_buf; 668 for (i = 0; i < TI_JSLOTS; i++) { 669 u_int64_t **aptr; 670 aptr = (u_int64_t **)ptr; 671 aptr[0] = (u_int64_t *)sc; 672 ptr += sizeof(u_int64_t); 673 sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 674 sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 675 ptr += (TI_JLEN - sizeof(u_int64_t)); 676 entry = malloc(sizeof(struct ti_jpool_entry), 677 M_DEVBUF, M_NOWAIT); 678 if (entry == NULL) { 679 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 680 sc->ti_cdata.ti_jumbo_buf = NULL; 681 printf("%s: no memory for jumbo " 682 "buffer queue!\n", sc->sc_dev.dv_xname); 683 return(ENOBUFS); 684 } 685 entry->slot = i; 686 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 687 jpool_entries); 688 } 689 690 return(0); 691 } 692 693 /* 694 * Allocate a jumbo buffer. 695 */ 696 static void *ti_jalloc(sc) 697 struct ti_softc *sc; 698 { 699 struct ti_jpool_entry *entry; 700 701 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 702 703 if (entry == NULL) { 704 printf("%s: no free jumbo buffers\n", sc->sc_dev.dv_xname); 705 return(NULL); 706 } 707 708 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 709 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 710 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 711 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 712 } 713 714 #if 0 715 /* 716 * Adjust usage count on a jumbo buffer. In general this doesn't 717 * get used much because our jumbo buffers don't get passed around 718 * too much, but it's implemented for correctness. 719 */ 720 static void ti_jref(buf, size) 721 caddr_t buf; 722 u_int size; 723 { 724 struct ti_softc *sc; 725 u_int64_t **aptr; 726 register int i; 727 728 /* Extract the softc struct pointer. */ 729 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 730 sc = (struct ti_softc *)(aptr[0]); 731 732 if (sc == NULL) 733 panic("ti_jref: can't find softc pointer!"); 734 735 if (size != TI_JUMBO_FRAMELEN) 736 panic("ti_jref: adjusting refcount of buf of wrong size!"); 737 738 /* calculate the slot this buffer belongs to */ 739 740 i = ((caddr_t)aptr 741 - (caddr_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 742 743 if ((i < 0) || (i >= TI_JSLOTS)) 744 panic("ti_jref: asked to reference buffer " 745 "that we don't manage!"); 746 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 747 panic("ti_jref: buffer already free!"); 748 else 749 sc->ti_cdata.ti_jslots[i].ti_inuse++; 750 751 return; 752 } 753 #endif 754 755 /* 756 * Release a jumbo buffer. 757 */ 758 static void ti_jfree(buf, size, arg) 759 caddr_t buf; 760 u_int size; 761 void *arg; /* XXX NetBSD: we should really use it */ 762 { 763 struct ti_softc *sc; 764 u_int64_t **aptr; 765 int i; 766 struct ti_jpool_entry *entry; 767 768 /* Extract the softc struct pointer. */ 769 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 770 sc = (struct ti_softc *)(aptr[0]); 771 772 if (sc == NULL) 773 panic("ti_jfree: can't find softc pointer!"); 774 775 if (size != TI_JUMBO_FRAMELEN) 776 panic("ti_jfree: freeing buffer of wrong size!"); 777 778 /* calculate the slot this buffer belongs to */ 779 780 i = ((caddr_t)aptr 781 - (caddr_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 782 783 if ((i < 0) || (i >= TI_JSLOTS)) 784 panic("ti_jfree: asked to free buffer that we don't manage!"); 785 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 786 panic("ti_jfree: buffer already free!"); 787 else { 788 sc->ti_cdata.ti_jslots[i].ti_inuse--; 789 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 790 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 791 if (entry == NULL) 792 panic("ti_jfree: buffer not in use!"); 793 entry->slot = i; 794 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, 795 entry, jpool_entries); 796 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, 797 entry, jpool_entries); 798 } 799 } 800 801 return; 802 } 803 804 805 /* 806 * Intialize a standard receive ring descriptor. 807 */ 808 static int ti_newbuf_std(sc, i, m, dmamap) 809 struct ti_softc *sc; 810 int i; 811 struct mbuf *m; 812 bus_dmamap_t dmamap; /* required if (m != NULL) */ 813 { 814 struct mbuf *m_new = NULL; 815 struct ti_rx_desc *r; 816 int error; 817 818 if (dmamap == NULL) { 819 /* if (m) panic() */ 820 821 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 822 MCLBYTES, 0, BUS_DMA_NOWAIT, 823 &dmamap)) != 0) { 824 printf("%s: can't create recv map, error = %d\n", 825 sc->sc_dev.dv_xname, error); 826 return(ENOMEM); 827 } 828 } 829 sc->std_dmamap[i] = dmamap; 830 831 if (m == NULL) { 832 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 833 if (m_new == NULL) { 834 printf("%s: mbuf allocation failed " 835 "-- packet dropped!\n", sc->sc_dev.dv_xname); 836 return(ENOBUFS); 837 } 838 839 MCLGET(m_new, M_DONTWAIT); 840 if (!(m_new->m_flags & M_EXT)) { 841 printf("%s: cluster allocation failed " 842 "-- packet dropped!\n", sc->sc_dev.dv_xname); 843 m_freem(m_new); 844 return(ENOBUFS); 845 } 846 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 847 m_adj(m_new, ETHER_ALIGN); 848 849 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 850 mtod(m_new, caddr_t), m_new->m_len, NULL, 851 BUS_DMA_NOWAIT)) != 0) { 852 printf("%s: can't load recv map, error = %d\n", 853 sc->sc_dev.dv_xname, error); 854 return (ENOMEM); 855 } 856 } else { 857 m_new = m; 858 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 859 m_new->m_data = m_new->m_ext.ext_buf; 860 m_adj(m_new, ETHER_ALIGN); 861 862 /* reuse the dmamap */ 863 } 864 865 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 866 r = &sc->ti_rdata->ti_rx_std_ring[i]; 867 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 868 r->ti_type = TI_BDTYPE_RECV_BD; 869 #ifdef TI_CSUM_OFFLOAD 870 r->ti_flags = TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 871 #else 872 r->ti_flags = 0; 873 #endif 874 r->ti_len = m_new->m_len; /* == ds_len */ 875 r->ti_idx = i; 876 877 return(0); 878 } 879 880 /* 881 * Intialize a mini receive ring descriptor. This only applies to 882 * the Tigon 2. 883 */ 884 static int ti_newbuf_mini(sc, i, m, dmamap) 885 struct ti_softc *sc; 886 int i; 887 struct mbuf *m; 888 bus_dmamap_t dmamap; /* required if (m != NULL) */ 889 { 890 struct mbuf *m_new = NULL; 891 struct ti_rx_desc *r; 892 int error; 893 894 if (dmamap == NULL) { 895 /* if (m) panic() */ 896 897 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 898 MHLEN, 0, BUS_DMA_NOWAIT, 899 &dmamap)) != 0) { 900 printf("%s: can't create recv map, error = %d\n", 901 sc->sc_dev.dv_xname, error); 902 return(ENOMEM); 903 } 904 } 905 sc->mini_dmamap[i] = dmamap; 906 907 if (m == NULL) { 908 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 909 if (m_new == NULL) { 910 printf("%s: mbuf allocation failed " 911 "-- packet dropped!\n", sc->sc_dev.dv_xname); 912 return(ENOBUFS); 913 } 914 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 915 m_adj(m_new, ETHER_ALIGN); 916 917 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 918 mtod(m_new, caddr_t), m_new->m_len, NULL, 919 BUS_DMA_NOWAIT)) != 0) { 920 printf("%s: can't load recv map, error = %d\n", 921 sc->sc_dev.dv_xname, error); 922 return (ENOMEM); 923 } 924 } else { 925 m_new = m; 926 m_new->m_data = m_new->m_pktdat; 927 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 928 m_adj(m_new, ETHER_ALIGN); 929 930 /* reuse the dmamap */ 931 } 932 933 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 934 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 935 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 936 r->ti_type = TI_BDTYPE_RECV_BD; 937 r->ti_flags = TI_BDFLAG_MINI_RING; 938 #ifdef TI_CSUM_OFFLOAD 939 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 940 #endif 941 r->ti_len = m_new->m_len; /* == ds_len */ 942 r->ti_idx = i; 943 944 return(0); 945 } 946 947 /* 948 * Initialize a jumbo receive ring descriptor. This allocates 949 * a jumbo buffer from the pool managed internally by the driver. 950 */ 951 static int ti_newbuf_jumbo(sc, i, m) 952 struct ti_softc *sc; 953 int i; 954 struct mbuf *m; 955 { 956 struct mbuf *m_new = NULL; 957 struct ti_rx_desc *r; 958 959 if (m == NULL) { 960 caddr_t *buf = NULL; 961 962 /* Allocate the mbuf. */ 963 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 964 if (m_new == NULL) { 965 printf("%s: mbuf allocation failed " 966 "-- packet dropped!\n", sc->sc_dev.dv_xname); 967 return(ENOBUFS); 968 } 969 970 /* Allocate the jumbo buffer */ 971 buf = ti_jalloc(sc); 972 if (buf == NULL) { 973 m_freem(m_new); 974 printf("%s: jumbo allocation failed " 975 "-- packet dropped!\n", sc->sc_dev.dv_xname); 976 return(ENOBUFS); 977 } 978 979 /* Attach the buffer to the mbuf. */ 980 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 981 m_new->m_flags |= M_EXT; 982 m_new->m_len = m_new->m_pkthdr.len = 983 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 984 m_new->m_ext.ext_free = ti_jfree; 985 m_new->m_ext.ext_arg = sc; 986 #if 0 987 m_new->m_ext.ext_ref = ti_jref; 988 #endif 989 MCLINITREFERENCE(m_new); 990 } else { 991 m_new = m; 992 m_new->m_data = m_new->m_ext.ext_buf; 993 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 994 } 995 996 m_adj(m_new, ETHER_ALIGN); 997 /* Set up the descriptor. */ 998 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 999 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1000 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 1001 ((caddr_t)mtod(m_new, caddr_t) 1002 - (caddr_t)sc->ti_cdata.ti_jumbo_buf); 1003 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1004 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1005 #ifdef TI_CSUM_OFFLOAD 1006 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1007 #endif 1008 r->ti_len = m_new->m_len; 1009 r->ti_idx = i; 1010 1011 return(0); 1012 } 1013 1014 /* 1015 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1016 * that's 1MB or memory, which is a lot. For now, we fill only the first 1017 * 256 ring entries and hope that our CPU is fast enough to keep up with 1018 * the NIC. 1019 */ 1020 static int ti_init_rx_ring_std(sc) 1021 struct ti_softc *sc; 1022 { 1023 register int i; 1024 struct ti_cmd_desc cmd; 1025 1026 for (i = 0; i < TI_SSLOTS; i++) { 1027 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 1028 return(ENOBUFS); 1029 }; 1030 1031 TI_UPDATE_STDPROD(sc, i - 1); 1032 sc->ti_std = i - 1; 1033 1034 return(0); 1035 } 1036 1037 static void ti_free_rx_ring_std(sc) 1038 struct ti_softc *sc; 1039 { 1040 register int i; 1041 1042 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1043 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1044 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1045 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1046 1047 /* if (sc->std_dmamap[i] == 0) panic() */ 1048 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 1049 sc->std_dmamap[i] = 0; 1050 } 1051 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1052 sizeof(struct ti_rx_desc)); 1053 } 1054 1055 return; 1056 } 1057 1058 static int ti_init_rx_ring_jumbo(sc) 1059 struct ti_softc *sc; 1060 { 1061 register int i; 1062 struct ti_cmd_desc cmd; 1063 1064 for (i = 0; i < (TI_JSLOTS - 20); i++) { 1065 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1066 return(ENOBUFS); 1067 }; 1068 1069 TI_UPDATE_JUMBOPROD(sc, i - 1); 1070 sc->ti_jumbo = i - 1; 1071 1072 return(0); 1073 } 1074 1075 static void ti_free_rx_ring_jumbo(sc) 1076 struct ti_softc *sc; 1077 { 1078 register int i; 1079 1080 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1081 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1082 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1083 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1084 } 1085 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1086 sizeof(struct ti_rx_desc)); 1087 } 1088 1089 return; 1090 } 1091 1092 static int ti_init_rx_ring_mini(sc) 1093 struct ti_softc *sc; 1094 { 1095 register int i; 1096 1097 for (i = 0; i < TI_MSLOTS; i++) { 1098 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 1099 return(ENOBUFS); 1100 }; 1101 1102 TI_UPDATE_MINIPROD(sc, i - 1); 1103 sc->ti_mini = i - 1; 1104 1105 return(0); 1106 } 1107 1108 static void ti_free_rx_ring_mini(sc) 1109 struct ti_softc *sc; 1110 { 1111 register int i; 1112 1113 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1114 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1115 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1116 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1117 1118 /* if (sc->mini_dmamap[i] == 0) panic() */ 1119 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1120 sc->mini_dmamap[i] = 0; 1121 } 1122 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1123 sizeof(struct ti_rx_desc)); 1124 } 1125 1126 return; 1127 } 1128 1129 static void ti_free_tx_ring(sc) 1130 struct ti_softc *sc; 1131 { 1132 register int i; 1133 struct txdmamap_pool_entry *dma; 1134 1135 if (sc->ti_rdata->ti_tx_ring == NULL) 1136 return; 1137 1138 for (i = 0; i < TI_TX_RING_CNT; i++) { 1139 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1140 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1141 sc->ti_cdata.ti_tx_chain[i] = NULL; 1142 1143 /* if (sc->txdma[i] == 0) panic() */ 1144 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1145 link); 1146 sc->txdma[i] = 0; 1147 } 1148 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1149 sizeof(struct ti_tx_desc)); 1150 } 1151 1152 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1153 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, dma, link); 1154 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1155 free(dma, M_DEVBUF); 1156 } 1157 1158 return; 1159 } 1160 1161 static int ti_init_tx_ring(sc) 1162 struct ti_softc *sc; 1163 { 1164 int i, error; 1165 bus_dmamap_t dmamap; 1166 struct txdmamap_pool_entry *dma; 1167 1168 sc->ti_txcnt = 0; 1169 sc->ti_tx_saved_considx = 0; 1170 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1171 1172 SIMPLEQ_INIT(&sc->txdma_list); 1173 for (i = 0; i < TI_RSLOTS; i++) { 1174 /* I've seen mbufs with 30 fragments. */ 1175 if ((error = bus_dmamap_create(sc->sc_dmat, TI_JUMBO_FRAMELEN, 1176 40, TI_JUMBO_FRAMELEN, 0, 1177 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1178 printf("%s: can't create tx map, error = %d\n", 1179 sc->sc_dev.dv_xname, error); 1180 return(ENOMEM); 1181 } 1182 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1183 if (!dma) { 1184 printf("%s: can't alloc txdmamap_pool_entry\n", 1185 sc->sc_dev.dv_xname); 1186 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1187 return (ENOMEM); 1188 } 1189 dma->dmamap = dmamap; 1190 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1191 } 1192 1193 return(0); 1194 } 1195 1196 /* 1197 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1198 * but we have to support the old way too so that Tigon 1 cards will 1199 * work. 1200 */ 1201 void ti_add_mcast(sc, addr) 1202 struct ti_softc *sc; 1203 struct ether_addr *addr; 1204 { 1205 struct ti_cmd_desc cmd; 1206 u_int16_t *m; 1207 u_int32_t ext[2] = {0, 0}; 1208 1209 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1210 1211 switch(sc->ti_hwrev) { 1212 case TI_HWREV_TIGON: 1213 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1214 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1215 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1216 break; 1217 case TI_HWREV_TIGON_II: 1218 ext[0] = htons(m[0]); 1219 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1220 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1221 break; 1222 default: 1223 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1224 break; 1225 } 1226 1227 return; 1228 } 1229 1230 void ti_del_mcast(sc, addr) 1231 struct ti_softc *sc; 1232 struct ether_addr *addr; 1233 { 1234 struct ti_cmd_desc cmd; 1235 u_int16_t *m; 1236 u_int32_t ext[2] = {0, 0}; 1237 1238 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1239 1240 switch(sc->ti_hwrev) { 1241 case TI_HWREV_TIGON: 1242 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1243 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1244 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1245 break; 1246 case TI_HWREV_TIGON_II: 1247 ext[0] = htons(m[0]); 1248 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1249 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1250 break; 1251 default: 1252 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1253 break; 1254 } 1255 1256 return; 1257 } 1258 1259 /* 1260 * Configure the Tigon's multicast address filter. 1261 * 1262 * The actual multicast table management is a bit of a pain, thanks to 1263 * slight brain damage on the part of both Alteon and us. With our 1264 * multicast code, we are only alerted when the multicast address table 1265 * changes and at that point we only have the current list of addresses: 1266 * we only know the current state, not the previous state, so we don't 1267 * actually know what addresses were removed or added. The firmware has 1268 * state, but we can't get our grubby mits on it, and there is no 'delete 1269 * all multicast addresses' command. Hence, we have to maintain our own 1270 * state so we know what addresses have been programmed into the NIC at 1271 * any given time. 1272 */ 1273 static void ti_setmulti(sc) 1274 struct ti_softc *sc; 1275 { 1276 struct ifnet *ifp; 1277 struct ti_cmd_desc cmd; 1278 struct ti_mc_entry *mc; 1279 u_int32_t intrs; 1280 struct ether_multi *enm; 1281 struct ether_multistep step; 1282 1283 ifp = &sc->ethercom.ec_if; 1284 1285 if (ifp->if_flags & IFF_ALLMULTI) { 1286 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1287 return; 1288 } else { 1289 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1290 } 1291 1292 /* Disable interrupts. */ 1293 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1294 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1295 1296 /* First, zot all the existing filters. */ 1297 while (SIMPLEQ_FIRST(&sc->ti_mc_listhead) != NULL) { 1298 mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead); 1299 ti_del_mcast(sc, &mc->mc_addr); 1300 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1301 free(mc, M_DEVBUF); 1302 } 1303 1304 /* Now program new ones. */ 1305 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1306 while (enm != NULL) { 1307 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1308 bcopy(enm->enm_addrlo, 1309 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1310 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1311 ti_add_mcast(sc, &mc->mc_addr); 1312 ETHER_NEXT_MULTI(step, enm); 1313 } 1314 1315 /* Re-enable interrupts. */ 1316 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1317 1318 return; 1319 } 1320 1321 /* 1322 * Check to see if the BIOS has configured us for a 64 bit slot when 1323 * we aren't actually in one. If we detect this condition, we can work 1324 * around it on the Tigon 2 by setting a bit in the PCI state register, 1325 * but for the Tigon 1 we must give up and abort the interface attach. 1326 */ 1327 static int ti_64bitslot_war(sc) 1328 struct ti_softc *sc; 1329 { 1330 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1331 CSR_WRITE_4(sc, 0x600, 0); 1332 CSR_WRITE_4(sc, 0x604, 0); 1333 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1334 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1335 if (sc->ti_hwrev == TI_HWREV_TIGON) 1336 return(EINVAL); 1337 else { 1338 TI_SETBIT(sc, TI_PCI_STATE, 1339 TI_PCISTATE_32BIT_BUS); 1340 return(0); 1341 } 1342 } 1343 } 1344 1345 return(0); 1346 } 1347 1348 /* 1349 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1350 * self-test results. 1351 */ 1352 static int ti_chipinit(sc) 1353 struct ti_softc *sc; 1354 { 1355 u_int32_t cacheline; 1356 u_int32_t pci_writemax = 0; 1357 1358 /* Initialize link to down state. */ 1359 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1360 1361 /* Set endianness before we access any non-PCI registers. */ 1362 #if BYTE_ORDER == BIG_ENDIAN 1363 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1364 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1365 #else 1366 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1367 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1368 #endif 1369 1370 /* Check the ROM failed bit to see if self-tests passed. */ 1371 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1372 printf("%s: board self-diagnostics failed!\n", 1373 sc->sc_dev.dv_xname); 1374 return(ENODEV); 1375 } 1376 1377 /* Halt the CPU. */ 1378 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1379 1380 /* Figure out the hardware revision. */ 1381 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1382 case TI_REV_TIGON_I: 1383 sc->ti_hwrev = TI_HWREV_TIGON; 1384 break; 1385 case TI_REV_TIGON_II: 1386 sc->ti_hwrev = TI_HWREV_TIGON_II; 1387 break; 1388 default: 1389 printf("%s: unsupported chip revision\n", sc->sc_dev.dv_xname); 1390 return(ENODEV); 1391 } 1392 1393 /* Do special setup for Tigon 2. */ 1394 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1395 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1396 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1397 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1398 } 1399 1400 /* Set up the PCI state register. */ 1401 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1402 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1403 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1404 } 1405 1406 /* Clear the read/write max DMA parameters. */ 1407 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1408 TI_PCISTATE_READ_MAXDMA)); 1409 1410 /* Get cache line size. */ 1411 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1412 1413 /* 1414 * If the system has set enabled the PCI memory write 1415 * and invalidate command in the command register, set 1416 * the write max parameter accordingly. This is necessary 1417 * to use MWI with the Tigon 2. 1418 */ 1419 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1420 & PCI_COMMAND_INVALIDATE_ENABLE) { 1421 switch(cacheline) { 1422 case 1: 1423 case 4: 1424 case 8: 1425 case 16: 1426 case 32: 1427 case 64: 1428 break; 1429 default: 1430 /* Disable PCI memory write and invalidate. */ 1431 if (bootverbose) 1432 printf("%s: cache line size %d not " 1433 "supported; disabling PCI MWI\n", 1434 sc->sc_dev.dv_xname, cacheline); 1435 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1436 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1437 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1438 break; 1439 } 1440 } 1441 1442 #ifdef __brokenalpha__ 1443 /* 1444 * From the Alteon sample driver: 1445 * Must insure that we do not cross an 8K (bytes) boundary 1446 * for DMA reads. Our highest limit is 1K bytes. This is a 1447 * restriction on some ALPHA platforms with early revision 1448 * 21174 PCI chipsets, such as the AlphaPC 164lx 1449 */ 1450 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1451 #else 1452 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1453 #endif 1454 1455 /* This sets the min dma param all the way up (0xff). */ 1456 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1457 1458 /* Configure DMA variables. */ 1459 #if BYTE_ORDER == BIG_ENDIAN 1460 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1461 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1462 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1463 TI_OPMODE_DONT_FRAG_JUMBO); 1464 #else 1465 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1466 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1467 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1468 #endif 1469 1470 /* 1471 * Only allow 1 DMA channel to be active at a time. 1472 * I don't think this is a good idea, but without it 1473 * the firmware racks up lots of nicDmaReadRingFull 1474 * errors. 1475 */ 1476 #ifndef TI_CSUM_OFFLOAD 1477 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1478 #endif 1479 1480 /* Recommended settings from Tigon manual. */ 1481 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1482 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1483 1484 if (ti_64bitslot_war(sc)) { 1485 printf("%s: bios thinks we're in a 64 bit slot, " 1486 "but we aren't", sc->sc_dev.dv_xname); 1487 return(EINVAL); 1488 } 1489 1490 return(0); 1491 } 1492 1493 /* 1494 * Initialize the general information block and firmware, and 1495 * start the CPU(s) running. 1496 */ 1497 static int ti_gibinit(sc) 1498 struct ti_softc *sc; 1499 { 1500 struct ti_rcb *rcb; 1501 int i; 1502 struct ifnet *ifp; 1503 1504 ifp = &sc->ethercom.ec_if; 1505 1506 /* Disable interrupts for now. */ 1507 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1508 1509 /* Tell the chip where to find the general information block. */ 1510 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1511 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, sc->info_dmaaddr + 1512 ((caddr_t)&sc->ti_rdata->ti_info - (caddr_t)sc->ti_rdata)); 1513 1514 /* Load the firmware into SRAM. */ 1515 ti_loadfw(sc); 1516 1517 /* Set up the contents of the general info and ring control blocks. */ 1518 1519 /* Set up the event ring and producer pointer. */ 1520 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1521 1522 TI_HOSTADDR(rcb->ti_hostaddr) = sc->info_dmaaddr + 1523 ((caddr_t)&sc->ti_rdata->ti_event_ring - (caddr_t)sc->ti_rdata); 1524 rcb->ti_flags = 0; 1525 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1526 sc->info_dmaaddr + ((caddr_t)&sc->ti_rdata->ti_ev_prodidx_r 1527 - (caddr_t)sc->ti_rdata); 1528 sc->ti_ev_prodidx.ti_idx = 0; 1529 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1530 sc->ti_ev_saved_considx = 0; 1531 1532 /* Set up the command ring and producer mailbox. */ 1533 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1534 1535 sc->ti_rdata->ti_cmd_ring = 1536 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1537 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1538 rcb->ti_flags = 0; 1539 rcb->ti_max_len = 0; 1540 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1541 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1542 } 1543 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1544 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1545 sc->ti_cmd_saved_prodidx = 0; 1546 1547 /* 1548 * Assign the address of the stats refresh buffer. 1549 * We re-use the current stats buffer for this to 1550 * conserve memory. 1551 */ 1552 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1553 sc->info_dmaaddr + ((caddr_t)&sc->ti_rdata->ti_info.ti_stats 1554 - (caddr_t)sc->ti_rdata); 1555 1556 /* Set up the standard receive ring. */ 1557 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1558 TI_HOSTADDR(rcb->ti_hostaddr) = sc->info_dmaaddr + 1559 ((caddr_t)&sc->ti_rdata->ti_rx_std_ring 1560 - (caddr_t)sc->ti_rdata); 1561 rcb->ti_max_len = TI_FRAMELEN; 1562 rcb->ti_flags = 0; 1563 #ifdef TI_CSUM_OFFLOAD 1564 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1565 #endif 1566 #if NVLAN > 0 1567 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1568 #endif 1569 1570 /* Set up the jumbo receive ring. */ 1571 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1572 TI_HOSTADDR(rcb->ti_hostaddr) = sc->info_dmaaddr + 1573 ((caddr_t)&sc->ti_rdata->ti_rx_jumbo_ring - (caddr_t)sc->ti_rdata); 1574 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1575 rcb->ti_flags = 0; 1576 #ifdef TI_CSUM_OFFLOAD 1577 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1578 #endif 1579 #if NVLAN > 0 1580 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1581 #endif 1582 1583 /* 1584 * Set up the mini ring. Only activated on the 1585 * Tigon 2 but the slot in the config block is 1586 * still there on the Tigon 1. 1587 */ 1588 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1589 TI_HOSTADDR(rcb->ti_hostaddr) = sc->info_dmaaddr + 1590 ((caddr_t)&sc->ti_rdata->ti_rx_mini_ring - (caddr_t)sc->ti_rdata); 1591 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1592 if (sc->ti_hwrev == TI_HWREV_TIGON) 1593 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1594 else 1595 rcb->ti_flags = 0; 1596 #ifdef TI_CSUM_OFFLOAD 1597 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1598 #endif 1599 #if NVLAN > 0 1600 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1601 #endif 1602 1603 /* 1604 * Set up the receive return ring. 1605 */ 1606 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1607 TI_HOSTADDR(rcb->ti_hostaddr) = sc->info_dmaaddr + 1608 ((caddr_t)&sc->ti_rdata->ti_rx_return_ring - (caddr_t)sc->ti_rdata); 1609 rcb->ti_flags = 0; 1610 rcb->ti_max_len = TI_RETURN_RING_CNT; 1611 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1612 sc->info_dmaaddr + ((caddr_t)&sc->ti_rdata->ti_return_prodidx_r 1613 - (caddr_t)sc->ti_rdata); 1614 1615 /* 1616 * Set up the tx ring. Note: for the Tigon 2, we have the option 1617 * of putting the transmit ring in the host's address space and 1618 * letting the chip DMA it instead of leaving the ring in the NIC's 1619 * memory and accessing it through the shared memory region. We 1620 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1621 * so we have to revert to the shared memory scheme if we detect 1622 * a Tigon 1 chip. 1623 */ 1624 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1625 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1626 sc->ti_rdata->ti_tx_ring_nic = 1627 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1628 } 1629 bzero((char *)sc->ti_rdata->ti_tx_ring, 1630 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1631 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1632 if (sc->ti_hwrev == TI_HWREV_TIGON) 1633 rcb->ti_flags = 0; 1634 else 1635 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1636 #if NVLAN > 0 1637 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1638 #endif 1639 rcb->ti_max_len = TI_TX_RING_CNT; 1640 if (sc->ti_hwrev == TI_HWREV_TIGON) 1641 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1642 else 1643 TI_HOSTADDR(rcb->ti_hostaddr) = sc->info_dmaaddr + 1644 ((caddr_t)&sc->ti_rdata->ti_tx_ring 1645 - (caddr_t)sc->ti_rdata); 1646 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1647 sc->info_dmaaddr + ((caddr_t)&sc->ti_rdata->ti_tx_considx_r 1648 - (caddr_t)sc->ti_rdata); 1649 1650 /* Set up tuneables */ 1651 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1652 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1653 (sc->ti_rx_coal_ticks / 10)); 1654 else 1655 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1656 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1657 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1658 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1659 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1660 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1661 1662 /* Turn interrupts on. */ 1663 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1664 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1665 1666 /* Start CPU. */ 1667 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1668 1669 return(0); 1670 } 1671 1672 /* 1673 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1674 * against our list and return its name if we find a match. 1675 */ 1676 static int ti_probe(parent, match, aux) 1677 struct device *parent; 1678 struct cfdata *match; 1679 void *aux; 1680 { 1681 struct pci_attach_args *pa = aux; 1682 struct ti_type *t; 1683 1684 t = ti_devs; 1685 1686 while(t->ti_name != NULL) { 1687 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1688 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1689 return(1); 1690 } 1691 t++; 1692 } 1693 1694 return(0); 1695 } 1696 1697 static void ti_attach(parent, self, aux) 1698 struct device *parent, *self; 1699 void *aux; 1700 { 1701 int s; 1702 u_int32_t command; 1703 struct ifnet *ifp; 1704 struct ti_softc *sc; 1705 u_char eaddr[ETHER_ADDR_LEN]; 1706 struct pci_attach_args *pa = aux; 1707 pci_chipset_tag_t pc = pa->pa_pc; 1708 pci_intr_handle_t ih; 1709 const char *intrstr = NULL; 1710 bus_dma_segment_t dmaseg; 1711 int error, dmanseg; 1712 1713 s = splimp(); 1714 1715 sc = (struct ti_softc *)self; 1716 1717 /* 1718 * Map control/status registers. 1719 */ 1720 if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_MEM, BUS_SPACE_MAP_LINEAR, 1721 &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1722 printf(": can't map i/o space\n"); 1723 goto fail; 1724 } 1725 sc->ti_vhandle = (void *)(sc->ti_bhandle); /* XXX XXX XXX */ 1726 1727 printf("\n"); 1728 1729 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1730 command |= PCI_COMMAND_MASTER_ENABLE; 1731 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1732 1733 /* Allocate interrupt */ 1734 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 1735 pa->pa_intrline, &ih)) { 1736 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 1737 goto fail; 1738 } 1739 intrstr = pci_intr_string(pc, ih); 1740 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1741 if (sc->sc_ih == NULL) { 1742 printf("%s: couldn't establish interrupt", 1743 sc->sc_dev.dv_xname); 1744 if (intrstr != NULL) 1745 printf(" at %s", intrstr); 1746 printf("\n"); 1747 goto fail; 1748 } 1749 1750 if (ti_chipinit(sc)) { 1751 printf("%s: chip initialization failed\n", self->dv_xname); 1752 #if 0 1753 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1754 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1755 bus_release_resource(dev, SYS_RES_MEMORY, 1756 TI_PCI_LOMEM, sc->ti_res); 1757 #endif 1758 goto fail; 1759 } 1760 1761 /* Zero out the NIC's on-board SRAM. */ 1762 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1763 1764 /* Init again -- zeroing memory may have clobbered some registers. */ 1765 if (ti_chipinit(sc)) { 1766 printf("%s: chip initialization failed\n", self->dv_xname); 1767 #if 0 1768 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1769 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1770 bus_release_resource(dev, SYS_RES_MEMORY, 1771 TI_PCI_LOMEM, sc->ti_res); 1772 #endif 1773 goto fail; 1774 } 1775 1776 /* 1777 * Get station address from the EEPROM. Note: the manual states 1778 * that the MAC address is at offset 0x8c, however the data is 1779 * stored as two longwords (since that's how it's loaded into 1780 * the NIC). This means the MAC address is actually preceeded 1781 * by two zero bytes. We need to skip over those. 1782 */ 1783 if (ti_read_eeprom(sc, (caddr_t)&eaddr, 1784 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1785 printf("%s: failed to read station address\n", self->dv_xname); 1786 #if 0 1787 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1788 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1789 bus_release_resource(dev, SYS_RES_MEMORY, 1790 TI_PCI_LOMEM, sc->ti_res); 1791 #endif 1792 goto fail; 1793 } 1794 1795 /* 1796 * A Tigon chip was detected. Inform the world. 1797 */ 1798 printf("%s: Ethernet address: %s\n", self->dv_xname, 1799 ether_sprintf(eaddr)); 1800 1801 sc->sc_dmat = pa->pa_dmat; 1802 1803 /* Allocate the general information block and ring buffers. */ 1804 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1805 sizeof(struct ti_ring_data), NBPG, 0, &dmaseg, 1, &dmanseg, 1806 BUS_DMA_NOWAIT)) != 0) { 1807 printf("%s: can't allocate ring buffer, error = %d\n", 1808 sc->sc_dev.dv_xname, error); 1809 goto fail; 1810 } 1811 1812 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1813 sizeof(struct ti_ring_data), (caddr_t *)&sc->ti_rdata, 1814 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1815 printf("%s: can't map ring buffer, error = %d\n", 1816 sc->sc_dev.dv_xname, error); 1817 goto fail; 1818 } 1819 1820 if ((error = bus_dmamap_create(sc->sc_dmat, 1821 sizeof(struct ti_ring_data), 1, 1822 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1823 &sc->info_dmamap)) != 0) { 1824 printf("%s: can't create ring buffer DMA map, error = %d\n", 1825 sc->sc_dev.dv_xname, error); 1826 goto fail; 1827 } 1828 1829 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1830 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1831 BUS_DMA_NOWAIT)) != 0) { 1832 printf("%s: can't load ring buffer DMA map, error = %d\n", 1833 sc->sc_dev.dv_xname, error); 1834 goto fail; 1835 } 1836 1837 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1838 1839 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1840 1841 /* Try to allocate memory for jumbo buffers. */ 1842 if (ti_alloc_jumbo_mem(sc)) { 1843 printf("%s: jumbo buffer allocation failed\n", self->dv_xname); 1844 #if 0 1845 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1846 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1847 bus_release_resource(dev, SYS_RES_MEMORY, 1848 TI_PCI_LOMEM, sc->ti_res); 1849 free(sc->ti_rdata, M_DEVBUF); 1850 #endif 1851 goto fail; 1852 } 1853 1854 /* Set default tuneable values. */ 1855 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1856 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1857 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1858 sc->ti_rx_max_coal_bds = 64; 1859 sc->ti_tx_max_coal_bds = 128; 1860 sc->ti_tx_buf_ratio = 21; 1861 1862 /* Set up ifnet structure */ 1863 ifp = &sc->ethercom.ec_if; 1864 ifp->if_softc = sc; 1865 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1866 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1867 ifp->if_ioctl = ti_ioctl; 1868 #if 0 1869 ifp->if_output = ether_output; 1870 #endif 1871 ifp->if_start = ti_start; 1872 ifp->if_watchdog = ti_watchdog; 1873 ifp->if_baudrate = 10000000; 1874 #if 0 1875 ifp->if_init = ti_init; 1876 ifp->if_mtu = ETHERMTU; 1877 #endif 1878 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1879 1880 /* Set up ifmedia support. */ 1881 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1882 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1883 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1884 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1885 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL); 1886 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1887 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1888 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1889 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1890 1891 /* 1892 * Call MI attach routines. 1893 */ 1894 if_attach(ifp); 1895 ether_ifattach(ifp, eaddr); 1896 1897 #if NBPFILTER > 0 1898 bpfattach(&sc->ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 1899 sizeof(struct ether_header)); 1900 #endif 1901 1902 fail: 1903 splx(s); 1904 } 1905 1906 #if 0 1907 static int ti_detach(dev) 1908 device_t dev; 1909 { 1910 struct ti_softc *sc; 1911 struct ifnet *ifp; 1912 int s; 1913 1914 s = splimp(); 1915 1916 sc = device_get_softc(dev); 1917 ifp = &sc->arpcom.ac_if; 1918 1919 if_detach(ifp); 1920 ti_stop(sc); 1921 1922 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1923 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1924 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 1925 1926 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 1927 free(sc->ti_rdata, M_DEVBUF); 1928 ifmedia_removeall(&sc->ifmedia); 1929 1930 splx(s); 1931 1932 return(0); 1933 } 1934 #endif 1935 1936 /* 1937 * Frame reception handling. This is called if there's a frame 1938 * on the receive return list. 1939 * 1940 * Note: we have to be able to handle three possibilities here: 1941 * 1) the frame is from the mini receive ring (can only happen) 1942 * on Tigon 2 boards) 1943 * 2) the frame is from the jumbo recieve ring 1944 * 3) the frame is from the standard receive ring 1945 */ 1946 1947 static void ti_rxeof(sc) 1948 struct ti_softc *sc; 1949 { 1950 struct ifnet *ifp; 1951 struct ti_cmd_desc cmd; 1952 1953 ifp = &sc->ethercom.ec_if; 1954 1955 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1956 struct ti_rx_desc *cur_rx; 1957 u_int32_t rxidx; 1958 struct ether_header *eh; 1959 struct mbuf *m = NULL; 1960 #if NVLAN > 0 1961 u_int16_t vlan_tag = 0; 1962 int have_tag = 0; 1963 #endif 1964 #ifdef TI_CSUM_OFFLOAD 1965 struct ip *ip; 1966 #endif 1967 bus_dmamap_t dmamap; 1968 1969 cur_rx = 1970 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1971 rxidx = cur_rx->ti_idx; 1972 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1973 1974 #if NVLAN > 0 1975 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1976 have_tag = 1; 1977 vlan_tag = cur_rx->ti_vlan_tag; 1978 } 1979 #endif 1980 1981 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1982 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1983 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1984 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1985 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1986 ifp->if_ierrors++; 1987 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1988 continue; 1989 } 1990 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1991 == ENOBUFS) { 1992 ifp->if_ierrors++; 1993 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1994 continue; 1995 } 1996 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1997 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1998 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1999 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2000 dmamap = sc->mini_dmamap[rxidx]; 2001 sc->mini_dmamap[rxidx] = 0; 2002 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2003 ifp->if_ierrors++; 2004 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 2005 continue; 2006 } 2007 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 2008 == ENOBUFS) { 2009 ifp->if_ierrors++; 2010 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 2011 continue; 2012 } 2013 } else { 2014 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2015 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2016 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2017 dmamap = sc->std_dmamap[rxidx]; 2018 sc->std_dmamap[rxidx] = 0; 2019 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2020 ifp->if_ierrors++; 2021 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2022 continue; 2023 } 2024 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 2025 == ENOBUFS) { 2026 ifp->if_ierrors++; 2027 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2028 continue; 2029 } 2030 } 2031 2032 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 2033 ifp->if_ipackets++; 2034 eh = mtod(m, struct ether_header *); 2035 m->m_pkthdr.rcvif = ifp; 2036 2037 #if NBPFILTER > 0 2038 /* 2039 * Handle BPF listeners. Let the BPF user see the packet, but 2040 * don't pass it up to the ether_input() layer unless it's 2041 * a broadcast packet, multicast packet, matches our ethernet 2042 * address or the interface is in promiscuous mode. 2043 */ 2044 if (ifp->if_bpf) { 2045 bpf_mtap(ifp->if_bpf, m); 2046 if (ifp->if_flags & IFF_PROMISC && 2047 (bcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 2048 ETHER_ADDR_LEN) && 2049 (eh->ether_dhost[0] & 1) == 0)) { 2050 m_freem(m); 2051 continue; 2052 } 2053 } 2054 #endif 2055 2056 #ifdef TI_CSUM_OFFLOAD /* XXX NetBSD: broken because m points to ether pkt */ 2057 ip = mtod(m, struct ip *); 2058 if (!(cur_rx->ti_tcp_udp_cksum ^ 0xFFFF) && 2059 !(ip->ip_off & htons(IP_MF | IP_OFFMASK | IP_RF))) 2060 m->m_flags |= M_HWCKSUM; 2061 #endif 2062 2063 #if NVLAN > 0 /* XXX NetBSD: broken because m points to ether pkt */ 2064 /* 2065 * If we received a packet with a vlan tag, pass it 2066 * to vlan_input() instead of ether_input(). 2067 */ 2068 if (have_tag) { 2069 vlan_input_tag(eh, m, vlan_tag); 2070 have_tag = vlan_tag = 0; 2071 continue; 2072 } 2073 #endif 2074 (*ifp->if_input)(ifp, m); 2075 } 2076 2077 /* Only necessary on the Tigon 1. */ 2078 if (sc->ti_hwrev == TI_HWREV_TIGON) 2079 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2080 sc->ti_rx_saved_considx); 2081 2082 TI_UPDATE_STDPROD(sc, sc->ti_std); 2083 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2084 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2085 2086 return; 2087 } 2088 2089 static void ti_txeof(sc) 2090 struct ti_softc *sc; 2091 { 2092 struct ti_tx_desc *cur_tx = NULL; 2093 struct ifnet *ifp; 2094 2095 ifp = &sc->ethercom.ec_if; 2096 2097 /* 2098 * Go through our tx ring and free mbufs for those 2099 * frames that have been sent. 2100 */ 2101 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2102 u_int32_t idx = 0; 2103 2104 idx = sc->ti_tx_saved_considx; 2105 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2106 if (idx > 383) 2107 CSR_WRITE_4(sc, TI_WINBASE, 2108 TI_TX_RING_BASE + 6144); 2109 else if (idx > 255) 2110 CSR_WRITE_4(sc, TI_WINBASE, 2111 TI_TX_RING_BASE + 4096); 2112 else if (idx > 127) 2113 CSR_WRITE_4(sc, TI_WINBASE, 2114 TI_TX_RING_BASE + 2048); 2115 else 2116 CSR_WRITE_4(sc, TI_WINBASE, 2117 TI_TX_RING_BASE); 2118 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 2119 } else 2120 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2121 if (cur_tx->ti_flags & TI_BDFLAG_END) 2122 ifp->if_opackets++; 2123 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2124 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2125 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2126 2127 /* if (sc->txdma[idx] == 0) panic() */ 2128 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[idx], 2129 link); 2130 sc->txdma[idx] = 0; 2131 } 2132 sc->ti_txcnt--; 2133 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2134 ifp->if_timer = 0; 2135 } 2136 2137 if (cur_tx != NULL) 2138 ifp->if_flags &= ~IFF_OACTIVE; 2139 2140 return; 2141 } 2142 2143 static int ti_intr(xsc) 2144 void *xsc; 2145 { 2146 struct ti_softc *sc; 2147 struct ifnet *ifp; 2148 2149 sc = xsc; 2150 ifp = &sc->ethercom.ec_if; 2151 2152 #ifdef notdef 2153 /* Avoid this for now -- checking this register is expensive. */ 2154 /* Make sure this is really our interrupt. */ 2155 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2156 return (0); 2157 #endif 2158 2159 /* Ack interrupt and stop others from occuring. */ 2160 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2161 2162 if (ifp->if_flags & IFF_RUNNING) { 2163 /* Check RX return ring producer/consumer */ 2164 ti_rxeof(sc); 2165 2166 /* Check TX ring producer/consumer */ 2167 ti_txeof(sc); 2168 } 2169 2170 ti_handle_events(sc); 2171 2172 /* Re-enable interrupts. */ 2173 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2174 2175 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2176 ti_start(ifp); 2177 2178 return (1); 2179 } 2180 2181 static void ti_stats_update(sc) 2182 struct ti_softc *sc; 2183 { 2184 struct ifnet *ifp; 2185 2186 ifp = &sc->ethercom.ec_if; 2187 2188 ifp->if_collisions += 2189 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2190 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2191 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2192 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2193 ifp->if_collisions; 2194 2195 return; 2196 } 2197 2198 /* 2199 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2200 * pointers to descriptors. 2201 */ 2202 static int ti_encap(sc, m_head, txidx) 2203 struct ti_softc *sc; 2204 struct mbuf *m_head; 2205 u_int32_t *txidx; 2206 { 2207 struct ti_tx_desc *f = NULL; 2208 u_int32_t frag, cur, cnt = 0; 2209 struct txdmamap_pool_entry *dma; 2210 bus_dmamap_t dmamap; 2211 int error, i; 2212 #if NVLAN > 0 2213 struct ifvlan *ifv = NULL; 2214 2215 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2216 m_head->m_pkthdr.rcvif != NULL && 2217 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 2218 ifv = m_head->m_pkthdr.rcvif->if_softc; 2219 #endif 2220 2221 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2222 dmamap = dma->dmamap; 2223 2224 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 0); 2225 if (error) { 2226 struct mbuf *m; 2227 int i = 0; 2228 for (m = m_head; m; m = m->m_next) 2229 i++; 2230 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2231 "error %d\n", m_head->m_pkthdr.len, i, error); 2232 return (ENOMEM); 2233 } 2234 2235 cur = frag = *txidx; 2236 2237 /* 2238 * Start packing the mbufs in this chain into 2239 * the fragment pointers. Stop when we run out 2240 * of fragments or hit the end of the mbuf chain. 2241 */ 2242 for (i = 0; i < dmamap->dm_nsegs; i++) { 2243 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2244 if (frag > 383) 2245 CSR_WRITE_4(sc, TI_WINBASE, 2246 TI_TX_RING_BASE + 6144); 2247 else if (frag > 255) 2248 CSR_WRITE_4(sc, TI_WINBASE, 2249 TI_TX_RING_BASE + 4096); 2250 else if (frag > 127) 2251 CSR_WRITE_4(sc, TI_WINBASE, 2252 TI_TX_RING_BASE + 2048); 2253 else 2254 CSR_WRITE_4(sc, TI_WINBASE, 2255 TI_TX_RING_BASE); 2256 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2257 } else 2258 f = &sc->ti_rdata->ti_tx_ring[frag]; 2259 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2260 break; 2261 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2262 f->ti_len = dmamap->dm_segs[i].ds_len; 2263 f->ti_flags = 0; 2264 #if NVLAN > 0 2265 if (ifv != NULL) { 2266 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2267 f->ti_vlan_tag = ifv->ifv_tag; 2268 } else { 2269 f->ti_vlan_tag = 0; 2270 } 2271 #endif 2272 /* 2273 * Sanity check: avoid coming within 16 descriptors 2274 * of the end of the ring. 2275 */ 2276 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2277 return(ENOBUFS); 2278 cur = frag; 2279 TI_INC(frag, TI_TX_RING_CNT); 2280 cnt++; 2281 } 2282 2283 if (i < dmamap->dm_nsegs) 2284 return(ENOBUFS); 2285 2286 if (frag == sc->ti_tx_saved_considx) 2287 return(ENOBUFS); 2288 2289 if (sc->ti_hwrev == TI_HWREV_TIGON) 2290 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2291 TI_BDFLAG_END; 2292 else 2293 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2294 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2295 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, dma, link); 2296 sc->txdma[cur] = dma; 2297 sc->ti_txcnt += cnt; 2298 2299 *txidx = frag; 2300 2301 return(0); 2302 } 2303 2304 /* 2305 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2306 * to the mbuf data regions directly in the transmit descriptors. 2307 */ 2308 static void ti_start(ifp) 2309 struct ifnet *ifp; 2310 { 2311 struct ti_softc *sc; 2312 struct mbuf *m_head = NULL; 2313 u_int32_t prodidx = 0; 2314 2315 sc = ifp->if_softc; 2316 2317 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2318 2319 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2320 IF_DEQUEUE(&ifp->if_snd, m_head); 2321 if (m_head == NULL) 2322 break; 2323 2324 /* 2325 * Pack the data into the transmit ring. If we 2326 * don't have room, set the OACTIVE flag and wait 2327 * for the NIC to drain the ring. 2328 */ 2329 if (ti_encap(sc, m_head, &prodidx)) { 2330 IF_PREPEND(&ifp->if_snd, m_head); 2331 ifp->if_flags |= IFF_OACTIVE; 2332 break; 2333 } 2334 2335 /* 2336 * If there's a BPF listener, bounce a copy of this frame 2337 * to him. 2338 */ 2339 #if NBPFILTER > 0 2340 if (ifp->if_bpf) 2341 bpf_mtap(ifp->if_bpf, m_head); 2342 #endif 2343 } 2344 2345 /* Transmit */ 2346 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2347 2348 /* 2349 * Set a timeout in case the chip goes out to lunch. 2350 */ 2351 ifp->if_timer = 5; 2352 2353 return; 2354 } 2355 2356 static void ti_init(xsc) 2357 void *xsc; 2358 { 2359 struct ti_softc *sc = xsc; 2360 int s; 2361 2362 s = splimp(); 2363 2364 /* Cancel pending I/O and flush buffers. */ 2365 ti_stop(sc); 2366 2367 /* Init the gen info block, ring control blocks and firmware. */ 2368 if (ti_gibinit(sc)) { 2369 printf("%s: initialization failure\n", sc->sc_dev.dv_xname); 2370 splx(s); 2371 return; 2372 } 2373 2374 splx(s); 2375 2376 return; 2377 } 2378 2379 static void ti_init2(sc) 2380 struct ti_softc *sc; 2381 { 2382 struct ti_cmd_desc cmd; 2383 struct ifnet *ifp; 2384 u_int8_t *m; 2385 struct ifmedia *ifm; 2386 int tmp; 2387 2388 ifp = &sc->ethercom.ec_if; 2389 2390 /* Specify MTU and interface index. */ 2391 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->sc_dev.dv_unit); /* ??? */ 2392 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2393 ETHER_HDR_LEN + ETHER_CRC_LEN); 2394 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2395 2396 /* Load our MAC address. */ 2397 m = (u_int8_t *)LLADDR(ifp->if_sadl); 2398 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2399 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2400 | (m[4] << 8) | m[5]); 2401 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2402 2403 /* Enable or disable promiscuous mode as needed. */ 2404 if (ifp->if_flags & IFF_PROMISC) { 2405 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2406 } else { 2407 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2408 } 2409 2410 /* Program multicast filter. */ 2411 ti_setmulti(sc); 2412 2413 /* 2414 * If this is a Tigon 1, we should tell the 2415 * firmware to use software packet filtering. 2416 */ 2417 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2418 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2419 } 2420 2421 /* Init RX ring. */ 2422 ti_init_rx_ring_std(sc); 2423 2424 /* Init jumbo RX ring. */ 2425 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2426 ti_init_rx_ring_jumbo(sc); 2427 2428 /* 2429 * If this is a Tigon 2, we can also configure the 2430 * mini ring. 2431 */ 2432 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2433 ti_init_rx_ring_mini(sc); 2434 2435 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2436 sc->ti_rx_saved_considx = 0; 2437 2438 /* Init TX ring. */ 2439 ti_init_tx_ring(sc); 2440 2441 /* Tell firmware we're alive. */ 2442 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2443 2444 /* Enable host interrupts. */ 2445 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2446 2447 ifp->if_flags |= IFF_RUNNING; 2448 ifp->if_flags &= ~IFF_OACTIVE; 2449 2450 /* 2451 * Make sure to set media properly. We have to do this 2452 * here since we have to issue commands in order to set 2453 * the link negotiation and we can't issue commands until 2454 * the firmware is running. 2455 */ 2456 ifm = &sc->ifmedia; 2457 tmp = ifm->ifm_media; 2458 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2459 ti_ifmedia_upd(ifp); 2460 ifm->ifm_media = tmp; 2461 2462 return; 2463 } 2464 2465 /* 2466 * Set media options. 2467 */ 2468 static int ti_ifmedia_upd(ifp) 2469 struct ifnet *ifp; 2470 { 2471 struct ti_softc *sc; 2472 struct ifmedia *ifm; 2473 struct ti_cmd_desc cmd; 2474 2475 sc = ifp->if_softc; 2476 ifm = &sc->ifmedia; 2477 2478 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2479 return(EINVAL); 2480 2481 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2482 case IFM_AUTO: 2483 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2484 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2485 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2486 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2487 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2488 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2489 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2490 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2491 break; 2492 case IFM_1000_SX: 2493 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2494 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2495 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2496 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2497 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2498 break; 2499 case IFM_100_FX: 2500 case IFM_10_FL: 2501 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2502 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2503 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) { 2504 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2505 } else { 2506 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2507 } 2508 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2509 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2510 } else { 2511 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2512 } 2513 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2514 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2515 break; 2516 } 2517 2518 return(0); 2519 } 2520 2521 /* 2522 * Report current media status. 2523 */ 2524 static void ti_ifmedia_sts(ifp, ifmr) 2525 struct ifnet *ifp; 2526 struct ifmediareq *ifmr; 2527 { 2528 struct ti_softc *sc; 2529 2530 sc = ifp->if_softc; 2531 2532 ifmr->ifm_status = IFM_AVALID; 2533 ifmr->ifm_active = IFM_ETHER; 2534 2535 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2536 return; 2537 2538 ifmr->ifm_status |= IFM_ACTIVE; 2539 2540 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 2541 ifmr->ifm_active |= IFM_1000_SX|IFM_FDX; 2542 else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2543 u_int32_t media; 2544 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2545 if (media & TI_LNK_100MB) 2546 ifmr->ifm_active |= IFM_100_FX; 2547 if (media & TI_LNK_10MB) 2548 ifmr->ifm_active |= IFM_10_FL; 2549 if (media & TI_LNK_FULL_DUPLEX) 2550 ifmr->ifm_active |= IFM_FDX; 2551 if (media & TI_LNK_HALF_DUPLEX) 2552 ifmr->ifm_active |= IFM_HDX; 2553 } 2554 2555 return; 2556 } 2557 2558 static int 2559 ti_ether_ioctl(ifp, cmd, data) 2560 struct ifnet *ifp; 2561 u_long cmd; 2562 caddr_t data; 2563 { 2564 struct ifaddr *ifa = (struct ifaddr *) data; 2565 struct ti_softc *sc = ifp->if_softc; 2566 2567 switch (cmd) { 2568 case SIOCSIFADDR: 2569 ifp->if_flags |= IFF_UP; 2570 2571 switch (ifa->ifa_addr->sa_family) { 2572 #ifdef INET 2573 case AF_INET: 2574 ti_init(sc); 2575 arp_ifinit(ifp, ifa); 2576 break; 2577 #endif 2578 #ifdef NS 2579 case AF_NS: 2580 { 2581 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 2582 2583 if (ns_nullhost(*ina)) 2584 ina->x_host = *(union ns_host *) 2585 LLADDR(ifp->if_sadl); 2586 else 2587 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 2588 ifp->if_addrlen); 2589 /* Set new address. */ 2590 ti_init(sc); 2591 break; 2592 } 2593 #endif 2594 default: 2595 ti_init(sc); 2596 break; 2597 } 2598 break; 2599 2600 default: 2601 return (EINVAL); 2602 } 2603 2604 return (0); 2605 } 2606 2607 static int ti_ioctl(ifp, command, data) 2608 struct ifnet *ifp; 2609 u_long command; 2610 caddr_t data; 2611 { 2612 struct ti_softc *sc = ifp->if_softc; 2613 struct ifreq *ifr = (struct ifreq *) data; 2614 int s, error = 0; 2615 struct ti_cmd_desc cmd; 2616 2617 s = splimp(); 2618 2619 switch(command) { 2620 case SIOCSIFADDR: 2621 case SIOCGIFADDR: 2622 error = ti_ether_ioctl(ifp, command, data); 2623 break; 2624 case SIOCSIFMTU: 2625 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2626 error = EINVAL; 2627 else { 2628 ifp->if_mtu = ifr->ifr_mtu; 2629 ti_init(sc); 2630 } 2631 break; 2632 case SIOCSIFFLAGS: 2633 if (ifp->if_flags & IFF_UP) { 2634 /* 2635 * If only the state of the PROMISC flag changed, 2636 * then just use the 'set promisc mode' command 2637 * instead of reinitializing the entire NIC. Doing 2638 * a full re-init means reloading the firmware and 2639 * waiting for it to start up, which may take a 2640 * second or two. 2641 */ 2642 if (ifp->if_flags & IFF_RUNNING && 2643 ifp->if_flags & IFF_PROMISC && 2644 !(sc->ti_if_flags & IFF_PROMISC)) { 2645 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2646 TI_CMD_CODE_PROMISC_ENB, 0); 2647 } else if (ifp->if_flags & IFF_RUNNING && 2648 !(ifp->if_flags & IFF_PROMISC) && 2649 sc->ti_if_flags & IFF_PROMISC) { 2650 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2651 TI_CMD_CODE_PROMISC_DIS, 0); 2652 } else 2653 ti_init(sc); 2654 } else { 2655 if (ifp->if_flags & IFF_RUNNING) { 2656 ti_stop(sc); 2657 } 2658 } 2659 sc->ti_if_flags = ifp->if_flags; 2660 error = 0; 2661 break; 2662 case SIOCADDMULTI: 2663 case SIOCDELMULTI: 2664 if (ifp->if_flags & IFF_RUNNING) { 2665 ti_setmulti(sc); 2666 error = 0; 2667 } 2668 break; 2669 case SIOCSIFMEDIA: 2670 case SIOCGIFMEDIA: 2671 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2672 break; 2673 default: 2674 error = EINVAL; 2675 break; 2676 } 2677 2678 (void)splx(s); 2679 2680 return(error); 2681 } 2682 2683 static void ti_watchdog(ifp) 2684 struct ifnet *ifp; 2685 { 2686 struct ti_softc *sc; 2687 2688 sc = ifp->if_softc; 2689 2690 printf("%s: watchdog timeout -- resetting\n", sc->sc_dev.dv_xname); 2691 ti_stop(sc); 2692 ti_init(sc); 2693 2694 ifp->if_oerrors++; 2695 2696 return; 2697 } 2698 2699 /* 2700 * Stop the adapter and free any mbufs allocated to the 2701 * RX and TX lists. 2702 */ 2703 static void ti_stop(sc) 2704 struct ti_softc *sc; 2705 { 2706 struct ifnet *ifp; 2707 struct ti_cmd_desc cmd; 2708 2709 ifp = &sc->ethercom.ec_if; 2710 2711 /* Disable host interrupts. */ 2712 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2713 /* 2714 * Tell firmware we're shutting down. 2715 */ 2716 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2717 2718 /* Halt and reinitialize. */ 2719 ti_chipinit(sc); 2720 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2721 ti_chipinit(sc); 2722 2723 /* Free the RX lists. */ 2724 ti_free_rx_ring_std(sc); 2725 2726 /* Free jumbo RX list. */ 2727 ti_free_rx_ring_jumbo(sc); 2728 2729 /* Free mini RX list. */ 2730 ti_free_rx_ring_mini(sc); 2731 2732 /* Free TX buffers. */ 2733 ti_free_tx_ring(sc); 2734 2735 sc->ti_ev_prodidx.ti_idx = 0; 2736 sc->ti_return_prodidx.ti_idx = 0; 2737 sc->ti_tx_considx.ti_idx = 0; 2738 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2739 2740 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2741 2742 return; 2743 } 2744 2745 #if 0 2746 /* 2747 * Stop all chip I/O so that the kernel's probe routines don't 2748 * get confused by errant DMAs when rebooting. 2749 */ 2750 static void ti_shutdown(dev) 2751 device_t dev; 2752 { 2753 struct ti_softc *sc; 2754 2755 sc = device_get_softc(dev); 2756 2757 ti_chipinit(sc); 2758 2759 return; 2760 } 2761 #endif 2762
Indexes created Fri Sep 26 20:09:58 GMT 2025