if_ti.c revision 1.41
1 /* $NetBSD: if_ti.c,v 1.41 2001/08/14 11:55:38 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include "bpfilter.h" 84 #include "opt_inet.h" 85 #include "opt_ns.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/socket.h> 94 #include <sys/queue.h> 95 #include <sys/device.h> 96 #include <sys/reboot.h> 97 98 #include <uvm/uvm_extern.h> 99 100 #include <net/if.h> 101 #include <net/if_arp.h> 102 #include <net/if_ether.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 106 #if NBPFILTER > 0 107 #include <net/bpf.h> 108 #endif 109 110 #ifdef INET 111 #include <netinet/in.h> 112 #include <netinet/if_inarp.h> 113 #include <netinet/in_systm.h> 114 #include <netinet/ip.h> 115 #endif 116 117 #ifdef NS 118 #include <netns/ns.h> 119 #include <netns/ns_if.h> 120 #endif 121 122 #include <machine/bus.h> 123 124 #include <dev/pci/pcireg.h> 125 #include <dev/pci/pcivar.h> 126 #include <dev/pci/pcidevs.h> 127 128 #include <dev/pci/if_tireg.h> 129 130 #include <dev/microcode/tigon/ti_fw.h> 131 #include <dev/microcode/tigon/ti_fw2.h> 132 133 /* 134 * Various supported device vendors/types and their names. 135 */ 136 137 static const struct ti_type ti_devs[] = { 138 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 139 "Alteon AceNIC 1000BASE-SX Ethernet" }, 140 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 141 "Alteon AceNIC 1000BASE-T Ethernet" }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 143 "3Com 3c985-SX Gigabit Ethernet" }, 144 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 145 "Netgear GA620 1000BASE-SX Ethernet" }, 146 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 147 "Netgear GA620 1000BASE-T Ethernet" }, 148 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 149 "Silicon Graphics Gigabit Ethernet" }, 150 { 0, 0, NULL } 151 }; 152 153 static const struct ti_type *ti_type_match __P((struct pci_attach_args *)); 154 static int ti_probe __P((struct device *, struct cfdata *, void *)); 155 static void ti_attach __P((struct device *, struct device *, void *)); 156 static void ti_shutdown __P((void *)); 157 static void ti_txeof_tigon1 __P((struct ti_softc *)); 158 static void ti_txeof_tigon2 __P((struct ti_softc *)); 159 static void ti_rxeof __P((struct ti_softc *)); 160 161 static void ti_stats_update __P((struct ti_softc *)); 162 static int ti_encap_tigon1 __P((struct ti_softc *, struct mbuf *, 163 u_int32_t *)); 164 static int ti_encap_tigon2 __P((struct ti_softc *, struct mbuf *, 165 u_int32_t *)); 166 167 static int ti_intr __P((void *)); 168 static void ti_start __P((struct ifnet *)); 169 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 170 static void ti_init __P((void *)); 171 static void ti_init2 __P((struct ti_softc *)); 172 static void ti_stop __P((struct ti_softc *)); 173 static void ti_watchdog __P((struct ifnet *)); 174 static int ti_ifmedia_upd __P((struct ifnet *)); 175 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 176 177 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 178 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 179 int, u_int8_t *)); 180 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 181 182 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 183 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 184 static void ti_setmulti __P((struct ti_softc *)); 185 186 static void ti_mem __P((struct ti_softc *, u_int32_t, 187 u_int32_t, caddr_t)); 188 static void ti_loadfw __P((struct ti_softc *)); 189 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 190 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 191 caddr_t, int)); 192 static void ti_handle_events __P((struct ti_softc *)); 193 static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 194 static void *ti_jalloc __P((struct ti_softc *)); 195 static void ti_jfree __P((caddr_t, u_int, void *)); 196 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 197 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 198 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 199 static int ti_init_rx_ring_std __P((struct ti_softc *)); 200 static void ti_free_rx_ring_std __P((struct ti_softc *)); 201 static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 202 static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 203 static int ti_init_rx_ring_mini __P((struct ti_softc *)); 204 static void ti_free_rx_ring_mini __P((struct ti_softc *)); 205 static void ti_free_tx_ring __P((struct ti_softc *)); 206 static int ti_init_tx_ring __P((struct ti_softc *)); 207 208 static int ti_64bitslot_war __P((struct ti_softc *)); 209 static int ti_chipinit __P((struct ti_softc *)); 210 static int ti_gibinit __P((struct ti_softc *)); 211 212 static int ti_ether_ioctl __P((struct ifnet *, u_long, caddr_t)); 213 214 struct cfattach ti_ca = { 215 sizeof(struct ti_softc), ti_probe, ti_attach 216 }; 217 218 /* 219 * Send an instruction or address to the EEPROM, check for ACK. 220 */ 221 static u_int32_t ti_eeprom_putbyte(sc, byte) 222 struct ti_softc *sc; 223 int byte; 224 { 225 int i, ack = 0; 226 227 /* 228 * Make sure we're in TX mode. 229 */ 230 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 231 232 /* 233 * Feed in each bit and stobe the clock. 234 */ 235 for (i = 0x80; i; i >>= 1) { 236 if (byte & i) { 237 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 238 } else { 239 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 240 } 241 DELAY(1); 242 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 243 DELAY(1); 244 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 245 } 246 247 /* 248 * Turn off TX mode. 249 */ 250 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 251 252 /* 253 * Check for ack. 254 */ 255 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 256 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 257 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 258 259 return(ack); 260 } 261 262 /* 263 * Read a byte of data stored in the EEPROM at address 'addr.' 264 * We have to send two address bytes since the EEPROM can hold 265 * more than 256 bytes of data. 266 */ 267 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 268 struct ti_softc *sc; 269 int addr; 270 u_int8_t *dest; 271 { 272 int i; 273 u_int8_t byte = 0; 274 275 EEPROM_START; 276 277 /* 278 * Send write control code to EEPROM. 279 */ 280 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 281 printf("%s: failed to send write command, status: %x\n", 282 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 283 return(1); 284 } 285 286 /* 287 * Send first byte of address of byte we want to read. 288 */ 289 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 290 printf("%s: failed to send address, status: %x\n", 291 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 292 return(1); 293 } 294 /* 295 * Send second byte address of byte we want to read. 296 */ 297 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 298 printf("%s: failed to send address, status: %x\n", 299 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 300 return(1); 301 } 302 303 EEPROM_STOP; 304 EEPROM_START; 305 /* 306 * Send read control code to EEPROM. 307 */ 308 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 309 printf("%s: failed to send read command, status: %x\n", 310 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 311 return(1); 312 } 313 314 /* 315 * Start reading bits from EEPROM. 316 */ 317 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 318 for (i = 0x80; i; i >>= 1) { 319 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 320 DELAY(1); 321 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 322 byte |= i; 323 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 324 DELAY(1); 325 } 326 327 EEPROM_STOP; 328 329 /* 330 * No ACK generated for read, so just return byte. 331 */ 332 333 *dest = byte; 334 335 return(0); 336 } 337 338 /* 339 * Read a sequence of bytes from the EEPROM. 340 */ 341 static int ti_read_eeprom(sc, dest, off, cnt) 342 struct ti_softc *sc; 343 caddr_t dest; 344 int off; 345 int cnt; 346 { 347 int err = 0, i; 348 u_int8_t byte = 0; 349 350 for (i = 0; i < cnt; i++) { 351 err = ti_eeprom_getbyte(sc, off + i, &byte); 352 if (err) 353 break; 354 *(dest + i) = byte; 355 } 356 357 return(err ? 1 : 0); 358 } 359 360 /* 361 * NIC memory access function. Can be used to either clear a section 362 * of NIC local memory or (if buf is non-NULL) copy data into it. 363 */ 364 static void ti_mem(sc, addr, len, buf) 365 struct ti_softc *sc; 366 u_int32_t addr, len; 367 caddr_t buf; 368 { 369 int segptr, segsize, cnt; 370 caddr_t ptr; 371 372 segptr = addr; 373 cnt = len; 374 ptr = buf; 375 376 while(cnt) { 377 if (cnt < TI_WINLEN) 378 segsize = cnt; 379 else 380 segsize = TI_WINLEN - (segptr % TI_WINLEN); 381 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 382 if (buf == NULL) { 383 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 384 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 385 segsize / 4); 386 } else { 387 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 388 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 389 (u_int32_t *)ptr, segsize / 4); 390 ptr += segsize; 391 } 392 segptr += segsize; 393 cnt -= segsize; 394 } 395 396 return; 397 } 398 399 /* 400 * Load firmware image into the NIC. Check that the firmware revision 401 * is acceptable and see if we want the firmware for the Tigon 1 or 402 * Tigon 2. 403 */ 404 static void ti_loadfw(sc) 405 struct ti_softc *sc; 406 { 407 switch(sc->ti_hwrev) { 408 case TI_HWREV_TIGON: 409 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 410 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 411 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 412 printf("%s: firmware revision mismatch; want " 413 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 414 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 415 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 416 tigonFwReleaseMinor, tigonFwReleaseFix); 417 return; 418 } 419 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 420 (caddr_t)tigonFwText); 421 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 422 (caddr_t)tigonFwData); 423 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 424 (caddr_t)tigonFwRodata); 425 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 426 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 427 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 428 break; 429 case TI_HWREV_TIGON_II: 430 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 431 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 432 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 433 printf("%s: firmware revision mismatch; want " 434 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 435 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 436 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 437 tigon2FwReleaseMinor, tigon2FwReleaseFix); 438 return; 439 } 440 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 441 (caddr_t)tigon2FwText); 442 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 443 (caddr_t)tigon2FwData); 444 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 445 (caddr_t)tigon2FwRodata); 446 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 447 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 448 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 449 break; 450 default: 451 printf("%s: can't load firmware: unknown hardware rev\n", 452 sc->sc_dev.dv_xname); 453 break; 454 } 455 456 return; 457 } 458 459 /* 460 * Send the NIC a command via the command ring. 461 */ 462 static void ti_cmd(sc, cmd) 463 struct ti_softc *sc; 464 struct ti_cmd_desc *cmd; 465 { 466 u_int32_t index; 467 468 index = sc->ti_cmd_saved_prodidx; 469 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 470 TI_INC(index, TI_CMD_RING_CNT); 471 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 472 sc->ti_cmd_saved_prodidx = index; 473 474 return; 475 } 476 477 /* 478 * Send the NIC an extended command. The 'len' parameter specifies the 479 * number of command slots to include after the initial command. 480 */ 481 static void ti_cmd_ext(sc, cmd, arg, len) 482 struct ti_softc *sc; 483 struct ti_cmd_desc *cmd; 484 caddr_t arg; 485 int len; 486 { 487 u_int32_t index; 488 int i; 489 490 index = sc->ti_cmd_saved_prodidx; 491 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 492 TI_INC(index, TI_CMD_RING_CNT); 493 for (i = 0; i < len; i++) { 494 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 495 *(u_int32_t *)(&arg[i * 4])); 496 TI_INC(index, TI_CMD_RING_CNT); 497 } 498 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 499 sc->ti_cmd_saved_prodidx = index; 500 501 return; 502 } 503 504 /* 505 * Handle events that have triggered interrupts. 506 */ 507 static void ti_handle_events(sc) 508 struct ti_softc *sc; 509 { 510 struct ti_event_desc *e; 511 512 if (sc->ti_rdata->ti_event_ring == NULL) 513 return; 514 515 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 516 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 517 switch(e->ti_event) { 518 case TI_EV_LINKSTAT_CHANGED: 519 sc->ti_linkstat = e->ti_code; 520 if (e->ti_code == TI_EV_CODE_LINK_UP) 521 printf("%s: 10/100 link up\n", 522 sc->sc_dev.dv_xname); 523 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 524 printf("%s: gigabit link up\n", 525 sc->sc_dev.dv_xname); 526 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 527 printf("%s: link down\n", 528 sc->sc_dev.dv_xname); 529 break; 530 case TI_EV_ERROR: 531 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 532 printf("%s: invalid command\n", 533 sc->sc_dev.dv_xname); 534 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 535 printf("%s: unknown command\n", 536 sc->sc_dev.dv_xname); 537 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 538 printf("%s: bad config data\n", 539 sc->sc_dev.dv_xname); 540 break; 541 case TI_EV_FIRMWARE_UP: 542 ti_init2(sc); 543 break; 544 case TI_EV_STATS_UPDATED: 545 ti_stats_update(sc); 546 break; 547 case TI_EV_RESET_JUMBO_RING: 548 case TI_EV_MCAST_UPDATED: 549 /* Who cares. */ 550 break; 551 default: 552 printf("%s: unknown event: %d\n", 553 sc->sc_dev.dv_xname, e->ti_event); 554 break; 555 } 556 /* Advance the consumer index. */ 557 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 558 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 559 } 560 561 return; 562 } 563 564 /* 565 * Memory management for the jumbo receive ring is a pain in the 566 * butt. We need to allocate at least 9018 bytes of space per frame, 567 * _and_ it has to be contiguous (unless you use the extended 568 * jumbo descriptor format). Using malloc() all the time won't 569 * work: malloc() allocates memory in powers of two, which means we 570 * would end up wasting a considerable amount of space by allocating 571 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 572 * to do our own memory management. 573 * 574 * The driver needs to allocate a contiguous chunk of memory at boot 575 * time. We then chop this up ourselves into 9K pieces and use them 576 * as external mbuf storage. 577 * 578 * One issue here is how much memory to allocate. The jumbo ring has 579 * 256 slots in it, but at 9K per slot than can consume over 2MB of 580 * RAM. This is a bit much, especially considering we also need 581 * RAM for the standard ring and mini ring (on the Tigon 2). To 582 * save space, we only actually allocate enough memory for 64 slots 583 * by default, which works out to between 500 and 600K. This can 584 * be tuned by changing a #define in if_tireg.h. 585 */ 586 587 static int ti_alloc_jumbo_mem(sc) 588 struct ti_softc *sc; 589 { 590 caddr_t ptr; 591 int i; 592 struct ti_jpool_entry *entry; 593 bus_dma_segment_t dmaseg; 594 int error, dmanseg; 595 596 /* Grab a big chunk o' storage. */ 597 if ((error = bus_dmamem_alloc(sc->sc_dmat, 598 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 599 BUS_DMA_NOWAIT)) != 0) { 600 printf("%s: can't allocate jumbo buffer, error = %d\n", 601 sc->sc_dev.dv_xname, error); 602 return (error); 603 } 604 605 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 606 TI_JMEM, (caddr_t *)&sc->ti_cdata.ti_jumbo_buf, 607 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 608 printf("%s: can't map jumbo buffer, error = %d\n", 609 sc->sc_dev.dv_xname, error); 610 return (error); 611 } 612 613 if ((error = bus_dmamap_create(sc->sc_dmat, 614 TI_JMEM, 1, 615 TI_JMEM, 0, BUS_DMA_NOWAIT, 616 &sc->jumbo_dmamap)) != 0) { 617 printf("%s: can't create jumbo buffer DMA map, error = %d\n", 618 sc->sc_dev.dv_xname, error); 619 return (error); 620 } 621 622 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 623 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 624 BUS_DMA_NOWAIT)) != 0) { 625 printf("%s: can't load jumbo buffer DMA map, error = %d\n", 626 sc->sc_dev.dv_xname, error); 627 return (error); 628 } 629 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 630 631 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 632 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 633 634 /* 635 * Now divide it up into 9K pieces and save the addresses 636 * in an array. 637 */ 638 ptr = sc->ti_cdata.ti_jumbo_buf; 639 for (i = 0; i < TI_JSLOTS; i++) { 640 sc->ti_cdata.ti_jslots[i] = ptr; 641 ptr += TI_JLEN; 642 entry = malloc(sizeof(struct ti_jpool_entry), 643 M_DEVBUF, M_NOWAIT); 644 if (entry == NULL) { 645 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 646 sc->ti_cdata.ti_jumbo_buf = NULL; 647 printf("%s: no memory for jumbo " 648 "buffer queue!\n", sc->sc_dev.dv_xname); 649 return(ENOBUFS); 650 } 651 entry->slot = i; 652 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 653 jpool_entries); 654 } 655 656 return(0); 657 } 658 659 /* 660 * Allocate a jumbo buffer. 661 */ 662 static void *ti_jalloc(sc) 663 struct ti_softc *sc; 664 { 665 struct ti_jpool_entry *entry; 666 667 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 668 669 if (entry == NULL) { 670 printf("%s: no free jumbo buffers\n", sc->sc_dev.dv_xname); 671 return(NULL); 672 } 673 674 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 675 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 676 return(sc->ti_cdata.ti_jslots[entry->slot]); 677 } 678 679 /* 680 * Release a jumbo buffer. 681 */ 682 static void ti_jfree(buf, size, arg) 683 caddr_t buf; 684 u_int size; 685 void *arg; 686 { 687 struct ti_softc *sc; 688 int i; 689 struct ti_jpool_entry *entry; 690 691 /* Extract the softc struct pointer. */ 692 sc = (struct ti_softc *)arg; 693 694 if (sc == NULL) 695 panic("ti_jfree: didn't get softc pointer!"); 696 697 /* calculate the slot this buffer belongs to */ 698 699 i = ((caddr_t)buf 700 - (caddr_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 701 702 if ((i < 0) || (i >= TI_JSLOTS)) 703 panic("ti_jfree: asked to free buffer that we don't manage!"); 704 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 705 if (entry == NULL) 706 panic("ti_jfree: buffer not in use!"); 707 entry->slot = i; 708 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, 709 entry, jpool_entries); 710 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, 711 entry, jpool_entries); 712 713 return; 714 } 715 716 717 /* 718 * Intialize a standard receive ring descriptor. 719 */ 720 static int ti_newbuf_std(sc, i, m, dmamap) 721 struct ti_softc *sc; 722 int i; 723 struct mbuf *m; 724 bus_dmamap_t dmamap; /* required if (m != NULL) */ 725 { 726 struct mbuf *m_new = NULL; 727 struct ti_rx_desc *r; 728 int error; 729 730 if (dmamap == NULL) { 731 /* if (m) panic() */ 732 733 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 734 MCLBYTES, 0, BUS_DMA_NOWAIT, 735 &dmamap)) != 0) { 736 printf("%s: can't create recv map, error = %d\n", 737 sc->sc_dev.dv_xname, error); 738 return(ENOMEM); 739 } 740 } 741 sc->std_dmamap[i] = dmamap; 742 743 if (m == NULL) { 744 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 745 if (m_new == NULL) { 746 printf("%s: mbuf allocation failed " 747 "-- packet dropped!\n", sc->sc_dev.dv_xname); 748 return(ENOBUFS); 749 } 750 751 MCLGET(m_new, M_DONTWAIT); 752 if (!(m_new->m_flags & M_EXT)) { 753 printf("%s: cluster allocation failed " 754 "-- packet dropped!\n", sc->sc_dev.dv_xname); 755 m_freem(m_new); 756 return(ENOBUFS); 757 } 758 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 759 m_adj(m_new, ETHER_ALIGN); 760 761 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 762 mtod(m_new, caddr_t), m_new->m_len, NULL, 763 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 764 printf("%s: can't load recv map, error = %d\n", 765 sc->sc_dev.dv_xname, error); 766 return (ENOMEM); 767 } 768 } else { 769 m_new = m; 770 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 771 m_new->m_data = m_new->m_ext.ext_buf; 772 m_adj(m_new, ETHER_ALIGN); 773 774 /* reuse the dmamap */ 775 } 776 777 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 778 r = &sc->ti_rdata->ti_rx_std_ring[i]; 779 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 780 r->ti_type = TI_BDTYPE_RECV_BD; 781 r->ti_flags = 0; 782 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 783 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 784 if (sc->ethercom.ec_if.if_capenable & 785 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 786 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 787 r->ti_len = m_new->m_len; /* == ds_len */ 788 r->ti_idx = i; 789 790 return(0); 791 } 792 793 /* 794 * Intialize a mini receive ring descriptor. This only applies to 795 * the Tigon 2. 796 */ 797 static int ti_newbuf_mini(sc, i, m, dmamap) 798 struct ti_softc *sc; 799 int i; 800 struct mbuf *m; 801 bus_dmamap_t dmamap; /* required if (m != NULL) */ 802 { 803 struct mbuf *m_new = NULL; 804 struct ti_rx_desc *r; 805 int error; 806 807 if (dmamap == NULL) { 808 /* if (m) panic() */ 809 810 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 811 MHLEN, 0, BUS_DMA_NOWAIT, 812 &dmamap)) != 0) { 813 printf("%s: can't create recv map, error = %d\n", 814 sc->sc_dev.dv_xname, error); 815 return(ENOMEM); 816 } 817 } 818 sc->mini_dmamap[i] = dmamap; 819 820 if (m == NULL) { 821 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 822 if (m_new == NULL) { 823 printf("%s: mbuf allocation failed " 824 "-- packet dropped!\n", sc->sc_dev.dv_xname); 825 return(ENOBUFS); 826 } 827 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 828 m_adj(m_new, ETHER_ALIGN); 829 830 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 831 mtod(m_new, caddr_t), m_new->m_len, NULL, 832 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 833 printf("%s: can't load recv map, error = %d\n", 834 sc->sc_dev.dv_xname, error); 835 return (ENOMEM); 836 } 837 } else { 838 m_new = m; 839 m_new->m_data = m_new->m_pktdat; 840 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 841 m_adj(m_new, ETHER_ALIGN); 842 843 /* reuse the dmamap */ 844 } 845 846 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 847 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 848 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 849 r->ti_type = TI_BDTYPE_RECV_BD; 850 r->ti_flags = TI_BDFLAG_MINI_RING; 851 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 852 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 853 if (sc->ethercom.ec_if.if_capenable & 854 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 855 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 856 r->ti_len = m_new->m_len; /* == ds_len */ 857 r->ti_idx = i; 858 859 return(0); 860 } 861 862 /* 863 * Initialize a jumbo receive ring descriptor. This allocates 864 * a jumbo buffer from the pool managed internally by the driver. 865 */ 866 static int ti_newbuf_jumbo(sc, i, m) 867 struct ti_softc *sc; 868 int i; 869 struct mbuf *m; 870 { 871 struct mbuf *m_new = NULL; 872 struct ti_rx_desc *r; 873 874 if (m == NULL) { 875 caddr_t *buf = NULL; 876 877 /* Allocate the mbuf. */ 878 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 879 if (m_new == NULL) { 880 printf("%s: mbuf allocation failed " 881 "-- packet dropped!\n", sc->sc_dev.dv_xname); 882 return(ENOBUFS); 883 } 884 885 /* Allocate the jumbo buffer */ 886 buf = ti_jalloc(sc); 887 if (buf == NULL) { 888 m_freem(m_new); 889 printf("%s: jumbo allocation failed " 890 "-- packet dropped!\n", sc->sc_dev.dv_xname); 891 return(ENOBUFS); 892 } 893 894 /* Attach the buffer to the mbuf. */ 895 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 896 m_new->m_flags |= M_EXT; 897 m_new->m_len = m_new->m_pkthdr.len = 898 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 899 m_new->m_ext.ext_free = ti_jfree; 900 m_new->m_ext.ext_arg = sc; 901 MCLINITREFERENCE(m_new); 902 } else { 903 m_new = m; 904 m_new->m_data = m_new->m_ext.ext_buf; 905 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 906 } 907 908 m_adj(m_new, ETHER_ALIGN); 909 /* Set up the descriptor. */ 910 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 911 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 912 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 913 ((caddr_t)mtod(m_new, caddr_t) 914 - (caddr_t)sc->ti_cdata.ti_jumbo_buf); 915 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 916 r->ti_flags = TI_BDFLAG_JUMBO_RING; 917 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 918 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 919 if (sc->ethercom.ec_if.if_capenable & 920 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 921 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 922 r->ti_len = m_new->m_len; 923 r->ti_idx = i; 924 925 return(0); 926 } 927 928 /* 929 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 930 * that's 1MB or memory, which is a lot. For now, we fill only the first 931 * 256 ring entries and hope that our CPU is fast enough to keep up with 932 * the NIC. 933 */ 934 static int ti_init_rx_ring_std(sc) 935 struct ti_softc *sc; 936 { 937 int i; 938 struct ti_cmd_desc cmd; 939 940 for (i = 0; i < TI_SSLOTS; i++) { 941 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 942 return(ENOBUFS); 943 }; 944 945 TI_UPDATE_STDPROD(sc, i - 1); 946 sc->ti_std = i - 1; 947 948 return(0); 949 } 950 951 static void ti_free_rx_ring_std(sc) 952 struct ti_softc *sc; 953 { 954 int i; 955 956 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 957 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 958 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 959 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 960 961 /* if (sc->std_dmamap[i] == 0) panic() */ 962 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 963 sc->std_dmamap[i] = 0; 964 } 965 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 966 sizeof(struct ti_rx_desc)); 967 } 968 969 return; 970 } 971 972 static int ti_init_rx_ring_jumbo(sc) 973 struct ti_softc *sc; 974 { 975 int i; 976 struct ti_cmd_desc cmd; 977 978 for (i = 0; i < (TI_JSLOTS - 20); i++) { 979 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 980 return(ENOBUFS); 981 }; 982 983 TI_UPDATE_JUMBOPROD(sc, i - 1); 984 sc->ti_jumbo = i - 1; 985 986 return(0); 987 } 988 989 static void ti_free_rx_ring_jumbo(sc) 990 struct ti_softc *sc; 991 { 992 int i; 993 994 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 995 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 996 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 997 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 998 } 999 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 1000 sizeof(struct ti_rx_desc)); 1001 } 1002 1003 return; 1004 } 1005 1006 static int ti_init_rx_ring_mini(sc) 1007 struct ti_softc *sc; 1008 { 1009 int i; 1010 1011 for (i = 0; i < TI_MSLOTS; i++) { 1012 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 1013 return(ENOBUFS); 1014 }; 1015 1016 TI_UPDATE_MINIPROD(sc, i - 1); 1017 sc->ti_mini = i - 1; 1018 1019 return(0); 1020 } 1021 1022 static void ti_free_rx_ring_mini(sc) 1023 struct ti_softc *sc; 1024 { 1025 int i; 1026 1027 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1028 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1029 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1030 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1031 1032 /* if (sc->mini_dmamap[i] == 0) panic() */ 1033 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1034 sc->mini_dmamap[i] = 0; 1035 } 1036 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1037 sizeof(struct ti_rx_desc)); 1038 } 1039 1040 return; 1041 } 1042 1043 static void ti_free_tx_ring(sc) 1044 struct ti_softc *sc; 1045 { 1046 int i; 1047 struct txdmamap_pool_entry *dma; 1048 1049 if (sc->ti_rdata->ti_tx_ring == NULL) 1050 return; 1051 1052 for (i = 0; i < TI_TX_RING_CNT; i++) { 1053 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1054 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1055 sc->ti_cdata.ti_tx_chain[i] = NULL; 1056 1057 /* if (sc->txdma[i] == 0) panic() */ 1058 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1059 link); 1060 sc->txdma[i] = 0; 1061 } 1062 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1063 sizeof(struct ti_tx_desc)); 1064 } 1065 1066 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1067 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, dma, link); 1068 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1069 free(dma, M_DEVBUF); 1070 } 1071 1072 return; 1073 } 1074 1075 static int ti_init_tx_ring(sc) 1076 struct ti_softc *sc; 1077 { 1078 int i, error; 1079 bus_dmamap_t dmamap; 1080 struct txdmamap_pool_entry *dma; 1081 1082 sc->ti_txcnt = 0; 1083 sc->ti_tx_saved_considx = 0; 1084 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1085 1086 SIMPLEQ_INIT(&sc->txdma_list); 1087 for (i = 0; i < TI_RSLOTS; i++) { 1088 /* I've seen mbufs with 30 fragments. */ 1089 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 1090 40, ETHER_MAX_LEN_JUMBO, 0, 1091 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1092 printf("%s: can't create tx map, error = %d\n", 1093 sc->sc_dev.dv_xname, error); 1094 return(ENOMEM); 1095 } 1096 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1097 if (!dma) { 1098 printf("%s: can't alloc txdmamap_pool_entry\n", 1099 sc->sc_dev.dv_xname); 1100 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1101 return (ENOMEM); 1102 } 1103 dma->dmamap = dmamap; 1104 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1105 } 1106 1107 return(0); 1108 } 1109 1110 /* 1111 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1112 * but we have to support the old way too so that Tigon 1 cards will 1113 * work. 1114 */ 1115 void ti_add_mcast(sc, addr) 1116 struct ti_softc *sc; 1117 struct ether_addr *addr; 1118 { 1119 struct ti_cmd_desc cmd; 1120 u_int16_t *m; 1121 u_int32_t ext[2] = {0, 0}; 1122 1123 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1124 1125 switch(sc->ti_hwrev) { 1126 case TI_HWREV_TIGON: 1127 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1128 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1129 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1130 break; 1131 case TI_HWREV_TIGON_II: 1132 ext[0] = htons(m[0]); 1133 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1134 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1135 break; 1136 default: 1137 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1138 break; 1139 } 1140 1141 return; 1142 } 1143 1144 void ti_del_mcast(sc, addr) 1145 struct ti_softc *sc; 1146 struct ether_addr *addr; 1147 { 1148 struct ti_cmd_desc cmd; 1149 u_int16_t *m; 1150 u_int32_t ext[2] = {0, 0}; 1151 1152 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1153 1154 switch(sc->ti_hwrev) { 1155 case TI_HWREV_TIGON: 1156 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1157 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1158 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1159 break; 1160 case TI_HWREV_TIGON_II: 1161 ext[0] = htons(m[0]); 1162 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1163 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1164 break; 1165 default: 1166 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1167 break; 1168 } 1169 1170 return; 1171 } 1172 1173 /* 1174 * Configure the Tigon's multicast address filter. 1175 * 1176 * The actual multicast table management is a bit of a pain, thanks to 1177 * slight brain damage on the part of both Alteon and us. With our 1178 * multicast code, we are only alerted when the multicast address table 1179 * changes and at that point we only have the current list of addresses: 1180 * we only know the current state, not the previous state, so we don't 1181 * actually know what addresses were removed or added. The firmware has 1182 * state, but we can't get our grubby mits on it, and there is no 'delete 1183 * all multicast addresses' command. Hence, we have to maintain our own 1184 * state so we know what addresses have been programmed into the NIC at 1185 * any given time. 1186 */ 1187 static void ti_setmulti(sc) 1188 struct ti_softc *sc; 1189 { 1190 struct ifnet *ifp; 1191 struct ti_cmd_desc cmd; 1192 struct ti_mc_entry *mc; 1193 u_int32_t intrs; 1194 struct ether_multi *enm; 1195 struct ether_multistep step; 1196 1197 ifp = &sc->ethercom.ec_if; 1198 1199 /* Disable interrupts. */ 1200 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1201 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1202 1203 /* First, zot all the existing filters. */ 1204 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1205 ti_del_mcast(sc, &mc->mc_addr); 1206 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1207 free(mc, M_DEVBUF); 1208 } 1209 1210 /* 1211 * Remember all multicast addresses so that we can delete them 1212 * later. Punt if there is a range of addresses or memory shortage. 1213 */ 1214 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1215 while (enm != NULL) { 1216 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1217 ETHER_ADDR_LEN) != 0) 1218 goto allmulti; 1219 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1220 M_NOWAIT)) == NULL) 1221 goto allmulti; 1222 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1223 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1224 ETHER_NEXT_MULTI(step, enm); 1225 } 1226 1227 /* Accept only programmed multicast addresses */ 1228 ifp->if_flags &= ~IFF_ALLMULTI; 1229 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1230 1231 /* Now program new ones. */ 1232 for (mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead); mc != NULL; 1233 mc = SIMPLEQ_NEXT(mc, mc_entries)) 1234 ti_add_mcast(sc, &mc->mc_addr); 1235 1236 /* Re-enable interrupts. */ 1237 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1238 1239 return; 1240 1241 allmulti: 1242 /* No need to keep individual multicast addresses */ 1243 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1244 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc, 1245 mc_entries); 1246 free(mc, M_DEVBUF); 1247 } 1248 1249 /* Accept all multicast addresses */ 1250 ifp->if_flags |= IFF_ALLMULTI; 1251 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1252 1253 /* Re-enable interrupts. */ 1254 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1255 } 1256 1257 /* 1258 * Check to see if the BIOS has configured us for a 64 bit slot when 1259 * we aren't actually in one. If we detect this condition, we can work 1260 * around it on the Tigon 2 by setting a bit in the PCI state register, 1261 * but for the Tigon 1 we must give up and abort the interface attach. 1262 */ 1263 static int ti_64bitslot_war(sc) 1264 struct ti_softc *sc; 1265 { 1266 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1267 CSR_WRITE_4(sc, 0x600, 0); 1268 CSR_WRITE_4(sc, 0x604, 0); 1269 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1270 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1271 if (sc->ti_hwrev == TI_HWREV_TIGON) 1272 return(EINVAL); 1273 else { 1274 TI_SETBIT(sc, TI_PCI_STATE, 1275 TI_PCISTATE_32BIT_BUS); 1276 return(0); 1277 } 1278 } 1279 } 1280 1281 return(0); 1282 } 1283 1284 /* 1285 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1286 * self-test results. 1287 */ 1288 static int ti_chipinit(sc) 1289 struct ti_softc *sc; 1290 { 1291 u_int32_t cacheline; 1292 u_int32_t pci_writemax = 0; 1293 1294 /* Initialize link to down state. */ 1295 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1296 1297 /* Set endianness before we access any non-PCI registers. */ 1298 #if BYTE_ORDER == BIG_ENDIAN 1299 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1300 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1301 #else 1302 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1303 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1304 #endif 1305 1306 /* Check the ROM failed bit to see if self-tests passed. */ 1307 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1308 printf("%s: board self-diagnostics failed!\n", 1309 sc->sc_dev.dv_xname); 1310 return(ENODEV); 1311 } 1312 1313 /* Halt the CPU. */ 1314 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1315 1316 /* Figure out the hardware revision. */ 1317 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1318 case TI_REV_TIGON_I: 1319 sc->ti_hwrev = TI_HWREV_TIGON; 1320 break; 1321 case TI_REV_TIGON_II: 1322 sc->ti_hwrev = TI_HWREV_TIGON_II; 1323 break; 1324 default: 1325 printf("%s: unsupported chip revision\n", sc->sc_dev.dv_xname); 1326 return(ENODEV); 1327 } 1328 1329 /* Do special setup for Tigon 2. */ 1330 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1331 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1332 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1333 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1334 } 1335 1336 /* Set up the PCI state register. */ 1337 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1338 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1339 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1340 } 1341 1342 /* Clear the read/write max DMA parameters. */ 1343 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1344 TI_PCISTATE_READ_MAXDMA)); 1345 1346 /* Get cache line size. */ 1347 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1348 1349 /* 1350 * If the system has set enabled the PCI memory write 1351 * and invalidate command in the command register, set 1352 * the write max parameter accordingly. This is necessary 1353 * to use MWI with the Tigon 2. 1354 */ 1355 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1356 & PCI_COMMAND_INVALIDATE_ENABLE) { 1357 switch(cacheline) { 1358 case 1: 1359 case 4: 1360 case 8: 1361 case 16: 1362 case 32: 1363 case 64: 1364 break; 1365 default: 1366 /* Disable PCI memory write and invalidate. */ 1367 if (bootverbose) 1368 printf("%s: cache line size %d not " 1369 "supported; disabling PCI MWI\n", 1370 sc->sc_dev.dv_xname, cacheline); 1371 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1372 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1373 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1374 break; 1375 } 1376 } 1377 1378 #ifdef __brokenalpha__ 1379 /* 1380 * From the Alteon sample driver: 1381 * Must insure that we do not cross an 8K (bytes) boundary 1382 * for DMA reads. Our highest limit is 1K bytes. This is a 1383 * restriction on some ALPHA platforms with early revision 1384 * 21174 PCI chipsets, such as the AlphaPC 164lx 1385 */ 1386 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1387 #else 1388 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1389 #endif 1390 1391 /* This sets the min dma param all the way up (0xff). */ 1392 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1393 1394 /* Configure DMA variables. */ 1395 #if BYTE_ORDER == BIG_ENDIAN 1396 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1397 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1398 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1399 TI_OPMODE_DONT_FRAG_JUMBO); 1400 #else 1401 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1402 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1403 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1404 #endif 1405 1406 /* 1407 * Only allow 1 DMA channel to be active at a time. 1408 * I don't think this is a good idea, but without it 1409 * the firmware racks up lots of nicDmaReadRingFull 1410 * errors. 1411 * Incompatible with hardware assisted checksums. 1412 */ 1413 if ((sc->ethercom.ec_if.if_capenable & 1414 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4|IFCAP_CSUM_IPv4)) == 0) 1415 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1416 1417 /* Recommended settings from Tigon manual. */ 1418 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1419 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1420 1421 if (ti_64bitslot_war(sc)) { 1422 printf("%s: bios thinks we're in a 64 bit slot, " 1423 "but we aren't", sc->sc_dev.dv_xname); 1424 return(EINVAL); 1425 } 1426 1427 return(0); 1428 } 1429 1430 /* 1431 * Initialize the general information block and firmware, and 1432 * start the CPU(s) running. 1433 */ 1434 static int ti_gibinit(sc) 1435 struct ti_softc *sc; 1436 { 1437 struct ti_rcb *rcb; 1438 int i; 1439 struct ifnet *ifp; 1440 1441 ifp = &sc->ethercom.ec_if; 1442 1443 /* Disable interrupts for now. */ 1444 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1445 1446 /* Tell the chip where to find the general information block. */ 1447 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1448 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1449 1450 /* Load the firmware into SRAM. */ 1451 ti_loadfw(sc); 1452 1453 /* Set up the contents of the general info and ring control blocks. */ 1454 1455 /* Set up the event ring and producer pointer. */ 1456 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1457 1458 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1459 rcb->ti_flags = 0; 1460 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1461 TI_CDEVPRODADDR(sc); 1462 1463 sc->ti_ev_prodidx.ti_idx = 0; 1464 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1465 sc->ti_ev_saved_considx = 0; 1466 1467 /* Set up the command ring and producer mailbox. */ 1468 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1469 1470 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1471 rcb->ti_flags = 0; 1472 rcb->ti_max_len = 0; 1473 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1474 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1475 } 1476 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1477 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1478 sc->ti_cmd_saved_prodidx = 0; 1479 1480 /* 1481 * Assign the address of the stats refresh buffer. 1482 * We re-use the current stats buffer for this to 1483 * conserve memory. 1484 */ 1485 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1486 TI_CDSTATSADDR(sc); 1487 1488 /* Set up the standard receive ring. */ 1489 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1490 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1491 rcb->ti_max_len = ETHER_MAX_LEN; 1492 rcb->ti_flags = 0; 1493 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1494 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1495 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1496 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1497 if (sc->ethercom.ec_nvlans != 0) 1498 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1499 1500 /* Set up the jumbo receive ring. */ 1501 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1502 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1503 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1504 rcb->ti_flags = 0; 1505 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1506 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1507 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1508 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1509 if (sc->ethercom.ec_nvlans != 0) 1510 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1511 1512 /* 1513 * Set up the mini ring. Only activated on the 1514 * Tigon 2 but the slot in the config block is 1515 * still there on the Tigon 1. 1516 */ 1517 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1518 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1519 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1520 if (sc->ti_hwrev == TI_HWREV_TIGON) 1521 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1522 else 1523 rcb->ti_flags = 0; 1524 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1525 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1526 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1527 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1528 if (sc->ethercom.ec_nvlans != 0) 1529 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1530 1531 /* 1532 * Set up the receive return ring. 1533 */ 1534 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1535 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1536 rcb->ti_flags = 0; 1537 rcb->ti_max_len = TI_RETURN_RING_CNT; 1538 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1539 TI_CDRTNPRODADDR(sc); 1540 1541 /* 1542 * Set up the tx ring. Note: for the Tigon 2, we have the option 1543 * of putting the transmit ring in the host's address space and 1544 * letting the chip DMA it instead of leaving the ring in the NIC's 1545 * memory and accessing it through the shared memory region. We 1546 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1547 * so we have to revert to the shared memory scheme if we detect 1548 * a Tigon 1 chip. 1549 */ 1550 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1551 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1552 sc->ti_tx_ring_nic = 1553 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1554 } 1555 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1556 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1557 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1558 if (sc->ti_hwrev == TI_HWREV_TIGON) 1559 rcb->ti_flags = 0; 1560 else 1561 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1562 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1563 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1564 /* 1565 * When we get the packet, there is a pseudo-header seed already 1566 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1567 * compute the pseudo-header checksum again! 1568 */ 1569 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1570 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM| 1571 TI_RCB_FLAG_NO_PHDR_CKSUM; 1572 if (sc->ethercom.ec_nvlans != 0) 1573 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1574 rcb->ti_max_len = TI_TX_RING_CNT; 1575 if (sc->ti_hwrev == TI_HWREV_TIGON) 1576 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1577 else 1578 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1579 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1580 TI_CDTXCONSADDR(sc); 1581 1582 /* 1583 * We're done frobbing the General Information Block. Sync 1584 * it. Note we take care of the first stats sync here, as 1585 * well. 1586 */ 1587 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1588 1589 /* Set up tuneables */ 1590 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1591 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1592 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1593 (sc->ti_rx_coal_ticks / 10)); 1594 else 1595 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1596 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1597 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1598 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1599 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1600 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1601 1602 /* Turn interrupts on. */ 1603 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1604 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1605 1606 /* Start CPU. */ 1607 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1608 1609 return(0); 1610 } 1611 1612 /* 1613 * look for id in the device list, returning the first match 1614 */ 1615 static const struct ti_type * 1616 ti_type_match(pa) 1617 struct pci_attach_args *pa; 1618 { 1619 const struct ti_type *t; 1620 1621 t = ti_devs; 1622 while(t->ti_name != NULL) { 1623 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1624 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1625 return (t); 1626 } 1627 t++; 1628 } 1629 1630 return(NULL); 1631 } 1632 1633 /* 1634 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1635 * against our list and return its name if we find a match. 1636 */ 1637 static int ti_probe(parent, match, aux) 1638 struct device *parent; 1639 struct cfdata *match; 1640 void *aux; 1641 { 1642 struct pci_attach_args *pa = aux; 1643 const struct ti_type *t; 1644 1645 t = ti_type_match(pa); 1646 1647 return((t == NULL) ? 0 : 1); 1648 } 1649 1650 static void ti_attach(parent, self, aux) 1651 struct device *parent, *self; 1652 void *aux; 1653 { 1654 u_int32_t command; 1655 struct ifnet *ifp; 1656 struct ti_softc *sc; 1657 u_char eaddr[ETHER_ADDR_LEN]; 1658 struct pci_attach_args *pa = aux; 1659 pci_chipset_tag_t pc = pa->pa_pc; 1660 pci_intr_handle_t ih; 1661 const char *intrstr = NULL; 1662 bus_dma_segment_t dmaseg; 1663 int error, dmanseg, nolinear; 1664 const struct ti_type *t; 1665 1666 t = ti_type_match(pa); 1667 if (t == NULL) { 1668 printf("ti_attach: were did the card go ?\n"); 1669 return; 1670 } 1671 1672 printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class)); 1673 1674 sc = (struct ti_softc *)self; 1675 1676 /* 1677 * Map control/status registers. 1678 */ 1679 nolinear = 0; 1680 if (pci_mapreg_map(pa, 0x10, 1681 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1682 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1683 NULL, NULL)) { 1684 nolinear = 1; 1685 if (pci_mapreg_map(pa, 0x10, 1686 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1687 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1688 printf(": can't map memory space\n"); 1689 return; 1690 } 1691 } 1692 if (nolinear == 0) 1693 sc->ti_vhandle = (void *)(u_long)(sc->ti_bhandle); /* XXX XXX XXX */ 1694 else 1695 sc->ti_vhandle = NULL; 1696 1697 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1698 command |= PCI_COMMAND_MASTER_ENABLE; 1699 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1700 1701 /* Allocate interrupt */ 1702 if (pci_intr_map(pa, &ih)) { 1703 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 1704 return;; 1705 } 1706 intrstr = pci_intr_string(pc, ih); 1707 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1708 if (sc->sc_ih == NULL) { 1709 printf("%s: couldn't establish interrupt", 1710 sc->sc_dev.dv_xname); 1711 if (intrstr != NULL) 1712 printf(" at %s", intrstr); 1713 printf("\n"); 1714 return;; 1715 } 1716 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1717 /* 1718 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1719 * doing do could allow DMA to corrupt kernel memory during the 1720 * reboot before the driver initializes. 1721 */ 1722 (void) shutdownhook_establish(ti_shutdown, sc); 1723 1724 if (ti_chipinit(sc)) { 1725 printf("%s: chip initialization failed\n", self->dv_xname); 1726 goto fail2; 1727 } 1728 1729 /* 1730 * Deal with some chip diffrences. 1731 */ 1732 switch (sc->ti_hwrev) { 1733 case TI_HWREV_TIGON: 1734 sc->sc_tx_encap = ti_encap_tigon1; 1735 sc->sc_tx_eof = ti_txeof_tigon1; 1736 if (nolinear == 1) 1737 printf("%s: memory space not mapped linear\n", 1738 self->dv_xname); 1739 break; 1740 1741 case TI_HWREV_TIGON_II: 1742 sc->sc_tx_encap = ti_encap_tigon2; 1743 sc->sc_tx_eof = ti_txeof_tigon2; 1744 break; 1745 1746 default: 1747 printf("%s: Unknown chip version: %d\n", self->dv_xname, 1748 sc->ti_hwrev); 1749 goto fail2; 1750 } 1751 1752 /* Zero out the NIC's on-board SRAM. */ 1753 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1754 1755 /* Init again -- zeroing memory may have clobbered some registers. */ 1756 if (ti_chipinit(sc)) { 1757 printf("%s: chip initialization failed\n", self->dv_xname); 1758 goto fail2; 1759 } 1760 1761 /* 1762 * Get station address from the EEPROM. Note: the manual states 1763 * that the MAC address is at offset 0x8c, however the data is 1764 * stored as two longwords (since that's how it's loaded into 1765 * the NIC). This means the MAC address is actually preceeded 1766 * by two zero bytes. We need to skip over those. 1767 */ 1768 if (ti_read_eeprom(sc, (caddr_t)&eaddr, 1769 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1770 printf("%s: failed to read station address\n", self->dv_xname); 1771 goto fail2; 1772 } 1773 1774 /* 1775 * A Tigon chip was detected. Inform the world. 1776 */ 1777 printf("%s: Ethernet address: %s\n", self->dv_xname, 1778 ether_sprintf(eaddr)); 1779 1780 sc->sc_dmat = pa->pa_dmat; 1781 1782 /* Allocate the general information block and ring buffers. */ 1783 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1784 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1785 BUS_DMA_NOWAIT)) != 0) { 1786 printf("%s: can't allocate ring buffer, error = %d\n", 1787 sc->sc_dev.dv_xname, error); 1788 goto fail2; 1789 } 1790 1791 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1792 sizeof(struct ti_ring_data), (caddr_t *)&sc->ti_rdata, 1793 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1794 printf("%s: can't map ring buffer, error = %d\n", 1795 sc->sc_dev.dv_xname, error); 1796 goto fail2; 1797 } 1798 1799 if ((error = bus_dmamap_create(sc->sc_dmat, 1800 sizeof(struct ti_ring_data), 1, 1801 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1802 &sc->info_dmamap)) != 0) { 1803 printf("%s: can't create ring buffer DMA map, error = %d\n", 1804 sc->sc_dev.dv_xname, error); 1805 goto fail2; 1806 } 1807 1808 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1809 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1810 BUS_DMA_NOWAIT)) != 0) { 1811 printf("%s: can't load ring buffer DMA map, error = %d\n", 1812 sc->sc_dev.dv_xname, error); 1813 goto fail2; 1814 } 1815 1816 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1817 1818 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1819 1820 /* Try to allocate memory for jumbo buffers. */ 1821 if (ti_alloc_jumbo_mem(sc)) { 1822 printf("%s: jumbo buffer allocation failed\n", self->dv_xname); 1823 goto fail2; 1824 } 1825 1826 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1827 1828 /* 1829 * We really need a better way to tell a 1000baseT card 1830 * from a 1000baseSX one, since in theory there could be 1831 * OEMed 1000baseT cards from lame vendors who aren't 1832 * clever enough to change the PCI ID. For the moment 1833 * though, the AceNIC is the only copper card available. 1834 */ 1835 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1836 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1837 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1838 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1839 sc->ti_copper = 1; 1840 else 1841 sc->ti_copper = 0; 1842 1843 /* Set default tuneable values. */ 1844 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1845 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1846 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1847 sc->ti_rx_max_coal_bds = 64; 1848 sc->ti_tx_max_coal_bds = 128; 1849 sc->ti_tx_buf_ratio = 21; 1850 1851 /* Set up ifnet structure */ 1852 ifp = &sc->ethercom.ec_if; 1853 ifp->if_softc = sc; 1854 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1855 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1856 ifp->if_ioctl = ti_ioctl; 1857 ifp->if_start = ti_start; 1858 ifp->if_watchdog = ti_watchdog; 1859 IFQ_SET_READY(&ifp->if_snd); 1860 1861 #if 0 1862 /* 1863 * XXX This is not really correct -- we don't necessarily 1864 * XXX want to queue up as many as we can transmit at the 1865 * XXX upper layer like that. Someone with a board should 1866 * XXX check to see how this affects performance. 1867 */ 1868 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1869 #endif 1870 1871 /* 1872 * We can support 802.1Q VLAN-sized frames. 1873 */ 1874 sc->ethercom.ec_capabilities |= 1875 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1876 1877 /* 1878 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1879 */ 1880 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1881 IFCAP_CSUM_UDPv4; 1882 1883 /* Set up ifmedia support. */ 1884 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1885 if (sc->ti_copper) { 1886 /* 1887 * Copper cards allow manual 10/100 mode selection, 1888 * but not manual 1000baseT mode selection. Why? 1889 * Becuase currently there's no way to specify the 1890 * master/slave setting through the firmware interface, 1891 * so Alteon decided to just bag it and handle it 1892 * via autonegotiation. 1893 */ 1894 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1895 ifmedia_add(&sc->ifmedia, 1896 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1897 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1898 ifmedia_add(&sc->ifmedia, 1899 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1900 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 1901 ifmedia_add(&sc->ifmedia, 1902 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 1903 } else { 1904 /* Fiber cards don't support 10/100 modes. */ 1905 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1906 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1907 } 1908 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1909 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1910 1911 /* 1912 * Call MI attach routines. 1913 */ 1914 if_attach(ifp); 1915 ether_ifattach(ifp, eaddr); 1916 1917 return; 1918 fail2: 1919 pci_intr_disestablish(pc, sc->sc_ih); 1920 return; 1921 } 1922 1923 /* 1924 * Frame reception handling. This is called if there's a frame 1925 * on the receive return list. 1926 * 1927 * Note: we have to be able to handle three possibilities here: 1928 * 1) the frame is from the mini receive ring (can only happen) 1929 * on Tigon 2 boards) 1930 * 2) the frame is from the jumbo receive ring 1931 * 3) the frame is from the standard receive ring 1932 */ 1933 1934 static void ti_rxeof(sc) 1935 struct ti_softc *sc; 1936 { 1937 struct ifnet *ifp; 1938 struct ti_cmd_desc cmd; 1939 1940 ifp = &sc->ethercom.ec_if; 1941 1942 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1943 struct ti_rx_desc *cur_rx; 1944 u_int32_t rxidx; 1945 struct mbuf *m = NULL; 1946 u_int16_t vlan_tag = 0; 1947 int have_tag = 0; 1948 struct ether_header *eh; 1949 bus_dmamap_t dmamap; 1950 1951 cur_rx = 1952 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1953 rxidx = cur_rx->ti_idx; 1954 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1955 1956 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1957 have_tag = 1; 1958 vlan_tag = cur_rx->ti_vlan_tag; 1959 } 1960 1961 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1962 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1963 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1964 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1965 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1966 ifp->if_ierrors++; 1967 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1968 continue; 1969 } 1970 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1971 == ENOBUFS) { 1972 ifp->if_ierrors++; 1973 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1974 continue; 1975 } 1976 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1977 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1978 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1979 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1980 dmamap = sc->mini_dmamap[rxidx]; 1981 sc->mini_dmamap[rxidx] = 0; 1982 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1983 ifp->if_ierrors++; 1984 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1985 continue; 1986 } 1987 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1988 == ENOBUFS) { 1989 ifp->if_ierrors++; 1990 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1991 continue; 1992 } 1993 } else { 1994 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1995 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1996 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1997 dmamap = sc->std_dmamap[rxidx]; 1998 sc->std_dmamap[rxidx] = 0; 1999 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2000 ifp->if_ierrors++; 2001 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2002 continue; 2003 } 2004 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 2005 == ENOBUFS) { 2006 ifp->if_ierrors++; 2007 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2008 continue; 2009 } 2010 } 2011 2012 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 2013 ifp->if_ipackets++; 2014 m->m_pkthdr.rcvif = ifp; 2015 2016 #if NBPFILTER > 0 2017 /* 2018 * Handle BPF listeners. Let the BPF user see the packet, but 2019 * don't pass it up to the ether_input() layer unless it's 2020 * a broadcast packet, multicast packet, matches our ethernet 2021 * address or the interface is in promiscuous mode. 2022 */ 2023 if (ifp->if_bpf) 2024 bpf_mtap(ifp->if_bpf, m); 2025 #endif 2026 2027 eh = mtod(m, struct ether_header *); 2028 switch (ntohs(eh->ether_type)) { 2029 case ETHERTYPE_IP: 2030 { 2031 struct ip *ip = (struct ip *) (eh + 1); 2032 2033 /* 2034 * Note the Tigon firmware does not invert 2035 * the checksum for us, hence the XOR. 2036 */ 2037 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2038 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 2039 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2040 /* 2041 * ntohs() the constant so the compiler can 2042 * optimize... 2043 * 2044 * XXX Figure out a sane way to deal with 2045 * fragmented packets. 2046 */ 2047 if ((ip->ip_off & htons(IP_MF|IP_OFFMASK)) == 0) { 2048 switch (ip->ip_p) { 2049 case IPPROTO_TCP: 2050 m->m_pkthdr.csum_data = 2051 cur_rx->ti_tcp_udp_cksum; 2052 m->m_pkthdr.csum_flags |= 2053 M_CSUM_TCPv4|M_CSUM_DATA; 2054 break; 2055 case IPPROTO_UDP: 2056 m->m_pkthdr.csum_data = 2057 cur_rx->ti_tcp_udp_cksum; 2058 m->m_pkthdr.csum_flags |= 2059 M_CSUM_UDPv4|M_CSUM_DATA; 2060 break; 2061 default: 2062 /* Nothing */; 2063 } 2064 } 2065 break; 2066 } 2067 default: 2068 /* Nothing. */ 2069 break; 2070 } 2071 2072 if (have_tag) { 2073 struct mbuf *n; 2074 n = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 2075 if (n) { 2076 *mtod(n, int *) = vlan_tag; 2077 n->m_len = sizeof(int); 2078 } else { 2079 printf("%s: no mbuf for tag\n", ifp->if_xname); 2080 m_freem(m); 2081 continue; 2082 } 2083 have_tag = vlan_tag = 0; 2084 } 2085 (*ifp->if_input)(ifp, m); 2086 } 2087 2088 /* Only necessary on the Tigon 1. */ 2089 if (sc->ti_hwrev == TI_HWREV_TIGON) 2090 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2091 sc->ti_rx_saved_considx); 2092 2093 TI_UPDATE_STDPROD(sc, sc->ti_std); 2094 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2095 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2096 2097 return; 2098 } 2099 2100 static void ti_txeof_tigon1(sc) 2101 struct ti_softc *sc; 2102 { 2103 struct ti_tx_desc *cur_tx = NULL; 2104 struct ifnet *ifp; 2105 struct txdmamap_pool_entry *dma; 2106 2107 ifp = &sc->ethercom.ec_if; 2108 2109 /* 2110 * Go through our tx ring and free mbufs for those 2111 * frames that have been sent. 2112 */ 2113 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2114 u_int32_t idx = 0; 2115 2116 idx = sc->ti_tx_saved_considx; 2117 if (idx > 383) 2118 CSR_WRITE_4(sc, TI_WINBASE, 2119 TI_TX_RING_BASE + 6144); 2120 else if (idx > 255) 2121 CSR_WRITE_4(sc, TI_WINBASE, 2122 TI_TX_RING_BASE + 4096); 2123 else if (idx > 127) 2124 CSR_WRITE_4(sc, TI_WINBASE, 2125 TI_TX_RING_BASE + 2048); 2126 else 2127 CSR_WRITE_4(sc, TI_WINBASE, 2128 TI_TX_RING_BASE); 2129 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2130 if (cur_tx->ti_flags & TI_BDFLAG_END) 2131 ifp->if_opackets++; 2132 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2133 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2134 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2135 2136 dma = sc->txdma[idx]; 2137 KDASSERT(dma != NULL); 2138 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2139 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2140 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2141 2142 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2143 sc->txdma[idx] = NULL; 2144 } 2145 sc->ti_txcnt--; 2146 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2147 ifp->if_timer = 0; 2148 } 2149 2150 if (cur_tx != NULL) 2151 ifp->if_flags &= ~IFF_OACTIVE; 2152 2153 return; 2154 } 2155 2156 static void ti_txeof_tigon2(sc) 2157 struct ti_softc *sc; 2158 { 2159 struct ti_tx_desc *cur_tx = NULL; 2160 struct ifnet *ifp; 2161 struct txdmamap_pool_entry *dma; 2162 int firstidx, cnt; 2163 2164 ifp = &sc->ethercom.ec_if; 2165 2166 /* 2167 * Go through our tx ring and free mbufs for those 2168 * frames that have been sent. 2169 */ 2170 firstidx = sc->ti_tx_saved_considx; 2171 cnt = 0; 2172 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2173 u_int32_t idx = 0; 2174 2175 idx = sc->ti_tx_saved_considx; 2176 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2177 if (cur_tx->ti_flags & TI_BDFLAG_END) 2178 ifp->if_opackets++; 2179 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2180 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2181 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2182 2183 dma = sc->txdma[idx]; 2184 KDASSERT(dma != NULL); 2185 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2186 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2187 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2188 2189 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2190 sc->txdma[idx] = NULL; 2191 } 2192 cnt++; 2193 sc->ti_txcnt--; 2194 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2195 ifp->if_timer = 0; 2196 } 2197 2198 if (cnt != 0) 2199 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2200 2201 if (cur_tx != NULL) 2202 ifp->if_flags &= ~IFF_OACTIVE; 2203 2204 return; 2205 } 2206 2207 static int ti_intr(xsc) 2208 void *xsc; 2209 { 2210 struct ti_softc *sc; 2211 struct ifnet *ifp; 2212 2213 sc = xsc; 2214 ifp = &sc->ethercom.ec_if; 2215 2216 #ifdef notdef 2217 /* Avoid this for now -- checking this register is expensive. */ 2218 /* Make sure this is really our interrupt. */ 2219 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2220 return (0); 2221 #endif 2222 2223 /* Ack interrupt and stop others from occuring. */ 2224 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2225 2226 if (ifp->if_flags & IFF_RUNNING) { 2227 /* Check RX return ring producer/consumer */ 2228 ti_rxeof(sc); 2229 2230 /* Check TX ring producer/consumer */ 2231 (*sc->sc_tx_eof)(sc); 2232 } 2233 2234 ti_handle_events(sc); 2235 2236 /* Re-enable interrupts. */ 2237 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2238 2239 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2240 IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2241 ti_start(ifp); 2242 2243 return (1); 2244 } 2245 2246 static void ti_stats_update(sc) 2247 struct ti_softc *sc; 2248 { 2249 struct ifnet *ifp; 2250 2251 ifp = &sc->ethercom.ec_if; 2252 2253 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2254 2255 ifp->if_collisions += 2256 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2257 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2258 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2259 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2260 ifp->if_collisions; 2261 2262 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2263 } 2264 2265 /* 2266 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2267 * pointers to descriptors. 2268 */ 2269 static int ti_encap_tigon1(sc, m_head, txidx) 2270 struct ti_softc *sc; 2271 struct mbuf *m_head; 2272 u_int32_t *txidx; 2273 { 2274 struct ti_tx_desc *f = NULL; 2275 u_int32_t frag, cur, cnt = 0; 2276 struct txdmamap_pool_entry *dma; 2277 bus_dmamap_t dmamap; 2278 int error, i; 2279 struct mbuf *n; 2280 u_int16_t csum_flags = 0; 2281 2282 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2283 if (dma == NULL) { 2284 return ENOMEM; 2285 } 2286 dmamap = dma->dmamap; 2287 2288 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2289 BUS_DMA_WRITE); 2290 if (error) { 2291 struct mbuf *m; 2292 int i = 0; 2293 for (m = m_head; m; m = m->m_next) 2294 i++; 2295 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2296 "error %d\n", m_head->m_pkthdr.len, i, error); 2297 return (ENOMEM); 2298 } 2299 2300 cur = frag = *txidx; 2301 2302 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2303 /* IP header checksum field must be 0! */ 2304 csum_flags |= TI_BDFLAG_IP_CKSUM; 2305 } 2306 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2307 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2308 2309 /* XXX fragmented packet checksum capability? */ 2310 2311 /* 2312 * Start packing the mbufs in this chain into 2313 * the fragment pointers. Stop when we run out 2314 * of fragments or hit the end of the mbuf chain. 2315 */ 2316 for (i = 0; i < dmamap->dm_nsegs; i++) { 2317 if (frag > 383) 2318 CSR_WRITE_4(sc, TI_WINBASE, 2319 TI_TX_RING_BASE + 6144); 2320 else if (frag > 255) 2321 CSR_WRITE_4(sc, TI_WINBASE, 2322 TI_TX_RING_BASE + 4096); 2323 else if (frag > 127) 2324 CSR_WRITE_4(sc, TI_WINBASE, 2325 TI_TX_RING_BASE + 2048); 2326 else 2327 CSR_WRITE_4(sc, TI_WINBASE, 2328 TI_TX_RING_BASE); 2329 f = &sc->ti_tx_ring_nic[frag % 128]; 2330 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2331 break; 2332 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2333 f->ti_len = dmamap->dm_segs[i].ds_len; 2334 f->ti_flags = csum_flags; 2335 n = m_aux_find(m_head, AF_LINK, ETHERTYPE_VLAN); 2336 if (n) { 2337 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2338 f->ti_vlan_tag = *mtod(n, int *); 2339 } else { 2340 f->ti_vlan_tag = 0; 2341 } 2342 /* 2343 * Sanity check: avoid coming within 16 descriptors 2344 * of the end of the ring. 2345 */ 2346 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2347 return(ENOBUFS); 2348 cur = frag; 2349 TI_INC(frag, TI_TX_RING_CNT); 2350 cnt++; 2351 } 2352 2353 if (i < dmamap->dm_nsegs) 2354 return(ENOBUFS); 2355 2356 if (frag == sc->ti_tx_saved_considx) 2357 return(ENOBUFS); 2358 2359 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2360 TI_BDFLAG_END; 2361 2362 /* Sync the packet's DMA map. */ 2363 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2364 BUS_DMASYNC_PREWRITE); 2365 2366 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2367 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, dma, link); 2368 sc->txdma[cur] = dma; 2369 sc->ti_txcnt += cnt; 2370 2371 *txidx = frag; 2372 2373 return(0); 2374 } 2375 2376 static int ti_encap_tigon2(sc, m_head, txidx) 2377 struct ti_softc *sc; 2378 struct mbuf *m_head; 2379 u_int32_t *txidx; 2380 { 2381 struct ti_tx_desc *f = NULL; 2382 u_int32_t frag, firstfrag, cur, cnt = 0; 2383 struct txdmamap_pool_entry *dma; 2384 bus_dmamap_t dmamap; 2385 int error, i; 2386 struct mbuf *n; 2387 u_int16_t csum_flags = 0; 2388 2389 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2390 if (dma == NULL) { 2391 return ENOMEM; 2392 } 2393 dmamap = dma->dmamap; 2394 2395 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2396 BUS_DMA_WRITE); 2397 if (error) { 2398 struct mbuf *m; 2399 int i = 0; 2400 for (m = m_head; m; m = m->m_next) 2401 i++; 2402 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2403 "error %d\n", m_head->m_pkthdr.len, i, error); 2404 return (ENOMEM); 2405 } 2406 2407 cur = firstfrag = frag = *txidx; 2408 2409 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2410 /* IP header checksum field must be 0! */ 2411 csum_flags |= TI_BDFLAG_IP_CKSUM; 2412 } 2413 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2414 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2415 2416 /* XXX fragmented packet checksum capability? */ 2417 2418 /* 2419 * Start packing the mbufs in this chain into 2420 * the fragment pointers. Stop when we run out 2421 * of fragments or hit the end of the mbuf chain. 2422 */ 2423 for (i = 0; i < dmamap->dm_nsegs; i++) { 2424 f = &sc->ti_rdata->ti_tx_ring[frag]; 2425 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2426 break; 2427 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2428 f->ti_len = dmamap->dm_segs[i].ds_len; 2429 f->ti_flags = csum_flags; 2430 n = m_aux_find(m_head, AF_LINK, ETHERTYPE_VLAN); 2431 if (n) { 2432 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2433 f->ti_vlan_tag = *mtod(n, int *); 2434 } else { 2435 f->ti_vlan_tag = 0; 2436 } 2437 /* 2438 * Sanity check: avoid coming within 16 descriptors 2439 * of the end of the ring. 2440 */ 2441 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2442 return(ENOBUFS); 2443 cur = frag; 2444 TI_INC(frag, TI_TX_RING_CNT); 2445 cnt++; 2446 } 2447 2448 if (i < dmamap->dm_nsegs) 2449 return(ENOBUFS); 2450 2451 if (frag == sc->ti_tx_saved_considx) 2452 return(ENOBUFS); 2453 2454 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2455 2456 /* Sync the packet's DMA map. */ 2457 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2458 BUS_DMASYNC_PREWRITE); 2459 2460 /* Sync the descriptors we are using. */ 2461 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2462 2463 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2464 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, dma, link); 2465 sc->txdma[cur] = dma; 2466 sc->ti_txcnt += cnt; 2467 2468 *txidx = frag; 2469 2470 return(0); 2471 } 2472 2473 /* 2474 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2475 * to the mbuf data regions directly in the transmit descriptors. 2476 */ 2477 static void ti_start(ifp) 2478 struct ifnet *ifp; 2479 { 2480 struct ti_softc *sc; 2481 struct mbuf *m_head = NULL; 2482 u_int32_t prodidx = 0; 2483 2484 sc = ifp->if_softc; 2485 2486 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2487 2488 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2489 IFQ_POLL(&ifp->if_snd, m_head); 2490 if (m_head == NULL) 2491 break; 2492 2493 /* 2494 * Pack the data into the transmit ring. If we 2495 * don't have room, set the OACTIVE flag and wait 2496 * for the NIC to drain the ring. 2497 */ 2498 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2499 ifp->if_flags |= IFF_OACTIVE; 2500 break; 2501 } 2502 2503 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2504 2505 /* 2506 * If there's a BPF listener, bounce a copy of this frame 2507 * to him. 2508 */ 2509 #if NBPFILTER > 0 2510 if (ifp->if_bpf) 2511 bpf_mtap(ifp->if_bpf, m_head); 2512 #endif 2513 } 2514 2515 /* Transmit */ 2516 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2517 2518 /* 2519 * Set a timeout in case the chip goes out to lunch. 2520 */ 2521 ifp->if_timer = 5; 2522 2523 return; 2524 } 2525 2526 static void ti_init(xsc) 2527 void *xsc; 2528 { 2529 struct ti_softc *sc = xsc; 2530 int s; 2531 2532 s = splnet(); 2533 2534 /* Cancel pending I/O and flush buffers. */ 2535 ti_stop(sc); 2536 2537 /* Init the gen info block, ring control blocks and firmware. */ 2538 if (ti_gibinit(sc)) { 2539 printf("%s: initialization failure\n", sc->sc_dev.dv_xname); 2540 splx(s); 2541 return; 2542 } 2543 2544 splx(s); 2545 2546 return; 2547 } 2548 2549 static void ti_init2(sc) 2550 struct ti_softc *sc; 2551 { 2552 struct ti_cmd_desc cmd; 2553 struct ifnet *ifp; 2554 u_int8_t *m; 2555 struct ifmedia *ifm; 2556 int tmp; 2557 2558 ifp = &sc->ethercom.ec_if; 2559 2560 /* Specify MTU and interface index. */ 2561 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->sc_dev.dv_unit); /* ??? */ 2562 2563 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2564 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2565 tmp += ETHER_VLAN_ENCAP_LEN; 2566 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2567 2568 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2569 2570 /* Load our MAC address. */ 2571 m = (u_int8_t *)LLADDR(ifp->if_sadl); 2572 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2573 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2574 | (m[4] << 8) | m[5]); 2575 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2576 2577 /* Enable or disable promiscuous mode as needed. */ 2578 if (ifp->if_flags & IFF_PROMISC) { 2579 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2580 } else { 2581 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2582 } 2583 2584 /* Program multicast filter. */ 2585 ti_setmulti(sc); 2586 2587 /* 2588 * If this is a Tigon 1, we should tell the 2589 * firmware to use software packet filtering. 2590 */ 2591 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2592 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2593 } 2594 2595 /* Init RX ring. */ 2596 ti_init_rx_ring_std(sc); 2597 2598 /* Init jumbo RX ring. */ 2599 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2600 ti_init_rx_ring_jumbo(sc); 2601 2602 /* 2603 * If this is a Tigon 2, we can also configure the 2604 * mini ring. 2605 */ 2606 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2607 ti_init_rx_ring_mini(sc); 2608 2609 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2610 sc->ti_rx_saved_considx = 0; 2611 2612 /* Init TX ring. */ 2613 ti_init_tx_ring(sc); 2614 2615 /* Tell firmware we're alive. */ 2616 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2617 2618 /* Enable host interrupts. */ 2619 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2620 2621 ifp->if_flags |= IFF_RUNNING; 2622 ifp->if_flags &= ~IFF_OACTIVE; 2623 2624 /* 2625 * Make sure to set media properly. We have to do this 2626 * here since we have to issue commands in order to set 2627 * the link negotiation and we can't issue commands until 2628 * the firmware is running. 2629 */ 2630 ifm = &sc->ifmedia; 2631 tmp = ifm->ifm_media; 2632 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2633 ti_ifmedia_upd(ifp); 2634 ifm->ifm_media = tmp; 2635 2636 return; 2637 } 2638 2639 /* 2640 * Set media options. 2641 */ 2642 static int ti_ifmedia_upd(ifp) 2643 struct ifnet *ifp; 2644 { 2645 struct ti_softc *sc; 2646 struct ifmedia *ifm; 2647 struct ti_cmd_desc cmd; 2648 2649 sc = ifp->if_softc; 2650 ifm = &sc->ifmedia; 2651 2652 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2653 return(EINVAL); 2654 2655 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2656 case IFM_AUTO: 2657 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2658 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2659 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2660 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2661 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2662 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2663 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2664 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2665 break; 2666 case IFM_1000_SX: 2667 case IFM_1000_T: 2668 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2669 CSR_WRITE_4(sc, TI_GCR_GLINK, 2670 TI_GLNK_PREF|TI_GLNK_1000MB|TI_GLNK_FULL_DUPLEX| 2671 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2672 } else { 2673 CSR_WRITE_4(sc, TI_GCR_GLINK, 2674 TI_GLNK_PREF|TI_GLNK_1000MB| 2675 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2676 } 2677 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2678 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2679 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2680 break; 2681 case IFM_100_FX: 2682 case IFM_10_FL: 2683 case IFM_100_TX: 2684 case IFM_10_T: 2685 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2686 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2687 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2688 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2689 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2690 } else { 2691 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2692 } 2693 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2694 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2695 } else { 2696 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2697 } 2698 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2699 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2700 break; 2701 } 2702 2703 sc->ethercom.ec_if.if_baudrate = 2704 ifmedia_baudrate(ifm->ifm_media); 2705 2706 return(0); 2707 } 2708 2709 /* 2710 * Report current media status. 2711 */ 2712 static void ti_ifmedia_sts(ifp, ifmr) 2713 struct ifnet *ifp; 2714 struct ifmediareq *ifmr; 2715 { 2716 struct ti_softc *sc; 2717 u_int32_t media = 0; 2718 2719 sc = ifp->if_softc; 2720 2721 ifmr->ifm_status = IFM_AVALID; 2722 ifmr->ifm_active = IFM_ETHER; 2723 2724 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2725 return; 2726 2727 ifmr->ifm_status |= IFM_ACTIVE; 2728 2729 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2730 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2731 if (sc->ti_copper) 2732 ifmr->ifm_active |= IFM_1000_T; 2733 else 2734 ifmr->ifm_active |= IFM_1000_SX; 2735 if (media & TI_GLNK_FULL_DUPLEX) 2736 ifmr->ifm_active |= IFM_FDX; 2737 else 2738 ifmr->ifm_active |= IFM_HDX; 2739 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2740 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2741 if (sc->ti_copper) { 2742 if (media & TI_LNK_100MB) 2743 ifmr->ifm_active |= IFM_100_TX; 2744 if (media & TI_LNK_10MB) 2745 ifmr->ifm_active |= IFM_10_T; 2746 } else { 2747 if (media & TI_LNK_100MB) 2748 ifmr->ifm_active |= IFM_100_FX; 2749 if (media & TI_LNK_10MB) 2750 ifmr->ifm_active |= IFM_10_FL; 2751 } 2752 if (media & TI_LNK_FULL_DUPLEX) 2753 ifmr->ifm_active |= IFM_FDX; 2754 if (media & TI_LNK_HALF_DUPLEX) 2755 ifmr->ifm_active |= IFM_HDX; 2756 } 2757 2758 sc->ethercom.ec_if.if_baudrate = 2759 ifmedia_baudrate(sc->ifmedia.ifm_media); 2760 2761 return; 2762 } 2763 2764 static int 2765 ti_ether_ioctl(ifp, cmd, data) 2766 struct ifnet *ifp; 2767 u_long cmd; 2768 caddr_t data; 2769 { 2770 struct ifaddr *ifa = (struct ifaddr *) data; 2771 struct ti_softc *sc = ifp->if_softc; 2772 2773 if ((ifp->if_flags & IFF_UP) == 0) { 2774 ifp->if_flags |= IFF_UP; 2775 ti_init(sc); 2776 } 2777 2778 switch (cmd) { 2779 case SIOCSIFADDR: 2780 2781 switch (ifa->ifa_addr->sa_family) { 2782 #ifdef INET 2783 case AF_INET: 2784 arp_ifinit(ifp, ifa); 2785 break; 2786 #endif 2787 #ifdef NS 2788 case AF_NS: 2789 { 2790 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 2791 2792 if (ns_nullhost(*ina)) 2793 ina->x_host = *(union ns_host *) 2794 LLADDR(ifp->if_sadl); 2795 else 2796 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 2797 ifp->if_addrlen); 2798 break; 2799 } 2800 #endif 2801 default: 2802 break; 2803 } 2804 break; 2805 2806 default: 2807 return (EINVAL); 2808 } 2809 2810 return (0); 2811 } 2812 2813 static int ti_ioctl(ifp, command, data) 2814 struct ifnet *ifp; 2815 u_long command; 2816 caddr_t data; 2817 { 2818 struct ti_softc *sc = ifp->if_softc; 2819 struct ifreq *ifr = (struct ifreq *) data; 2820 int s, error = 0; 2821 struct ti_cmd_desc cmd; 2822 2823 s = splnet(); 2824 2825 switch(command) { 2826 case SIOCSIFADDR: 2827 case SIOCGIFADDR: 2828 error = ti_ether_ioctl(ifp, command, data); 2829 break; 2830 case SIOCSIFMTU: 2831 if (ifr->ifr_mtu > ETHERMTU_JUMBO) 2832 error = EINVAL; 2833 else { 2834 ifp->if_mtu = ifr->ifr_mtu; 2835 ti_init(sc); 2836 } 2837 break; 2838 case SIOCSIFFLAGS: 2839 if (ifp->if_flags & IFF_UP) { 2840 /* 2841 * If only the state of the PROMISC flag changed, 2842 * then just use the 'set promisc mode' command 2843 * instead of reinitializing the entire NIC. Doing 2844 * a full re-init means reloading the firmware and 2845 * waiting for it to start up, which may take a 2846 * second or two. 2847 */ 2848 if (ifp->if_flags & IFF_RUNNING && 2849 ifp->if_flags & IFF_PROMISC && 2850 !(sc->ti_if_flags & IFF_PROMISC)) { 2851 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2852 TI_CMD_CODE_PROMISC_ENB, 0); 2853 } else if (ifp->if_flags & IFF_RUNNING && 2854 !(ifp->if_flags & IFF_PROMISC) && 2855 sc->ti_if_flags & IFF_PROMISC) { 2856 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2857 TI_CMD_CODE_PROMISC_DIS, 0); 2858 } else 2859 ti_init(sc); 2860 } else { 2861 if (ifp->if_flags & IFF_RUNNING) { 2862 ti_stop(sc); 2863 } 2864 } 2865 sc->ti_if_flags = ifp->if_flags; 2866 error = 0; 2867 break; 2868 case SIOCADDMULTI: 2869 case SIOCDELMULTI: 2870 error = (command == SIOCADDMULTI) ? 2871 ether_addmulti(ifr, &sc->ethercom) : 2872 ether_delmulti(ifr, &sc->ethercom); 2873 if (error == ENETRESET) { 2874 if (ifp->if_flags & IFF_RUNNING) 2875 ti_setmulti(sc); 2876 error = 0; 2877 } 2878 break; 2879 case SIOCSIFMEDIA: 2880 case SIOCGIFMEDIA: 2881 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2882 break; 2883 default: 2884 error = EINVAL; 2885 break; 2886 } 2887 2888 (void)splx(s); 2889 2890 return(error); 2891 } 2892 2893 static void ti_watchdog(ifp) 2894 struct ifnet *ifp; 2895 { 2896 struct ti_softc *sc; 2897 2898 sc = ifp->if_softc; 2899 2900 printf("%s: watchdog timeout -- resetting\n", sc->sc_dev.dv_xname); 2901 ti_stop(sc); 2902 ti_init(sc); 2903 2904 ifp->if_oerrors++; 2905 2906 return; 2907 } 2908 2909 /* 2910 * Stop the adapter and free any mbufs allocated to the 2911 * RX and TX lists. 2912 */ 2913 static void ti_stop(sc) 2914 struct ti_softc *sc; 2915 { 2916 struct ifnet *ifp; 2917 struct ti_cmd_desc cmd; 2918 2919 ifp = &sc->ethercom.ec_if; 2920 2921 /* Disable host interrupts. */ 2922 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2923 /* 2924 * Tell firmware we're shutting down. 2925 */ 2926 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2927 2928 /* Halt and reinitialize. */ 2929 ti_chipinit(sc); 2930 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2931 ti_chipinit(sc); 2932 2933 /* Free the RX lists. */ 2934 ti_free_rx_ring_std(sc); 2935 2936 /* Free jumbo RX list. */ 2937 ti_free_rx_ring_jumbo(sc); 2938 2939 /* Free mini RX list. */ 2940 ti_free_rx_ring_mini(sc); 2941 2942 /* Free TX buffers. */ 2943 ti_free_tx_ring(sc); 2944 2945 sc->ti_ev_prodidx.ti_idx = 0; 2946 sc->ti_return_prodidx.ti_idx = 0; 2947 sc->ti_tx_considx.ti_idx = 0; 2948 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2949 2950 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2951 2952 return; 2953 } 2954 2955 /* 2956 * Stop all chip I/O so that the kernel's probe routines don't 2957 * get confused by errant DMAs when rebooting. 2958 */ 2959 static void ti_shutdown(v) 2960 void *v; 2961 { 2962 struct ti_softc *sc = v; 2963 2964 ti_chipinit(sc); 2965 2966 return; 2967 } 2968
Indexes created Fri Sep 26 20:09:58 GMT 2025