if_ti.c revision 1.49
1 /* $NetBSD: if_ti.c,v 1.49 2002/07/16 20:20:01 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.49 2002/07/16 20:20:01 bouyer Exp $"); 85 86 #include "bpfilter.h" 87 #include "opt_inet.h" 88 #include "opt_ns.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/queue.h> 98 #include <sys/device.h> 99 #include <sys/reboot.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #ifdef INET 114 #include <netinet/in.h> 115 #include <netinet/if_inarp.h> 116 #include <netinet/in_systm.h> 117 #include <netinet/ip.h> 118 #endif 119 120 #ifdef NS 121 #include <netns/ns.h> 122 #include <netns/ns_if.h> 123 #endif 124 125 #include <machine/bus.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/pcidevs.h> 130 131 #include <dev/pci/if_tireg.h> 132 133 #include <dev/microcode/tigon/ti_fw.h> 134 #include <dev/microcode/tigon/ti_fw2.h> 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 140 static const struct ti_type ti_devs[] = { 141 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 142 "Alteon AceNIC 1000BASE-SX Ethernet" }, 143 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 144 "Alteon AceNIC 1000BASE-T Ethernet" }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 146 "3Com 3c985-SX Gigabit Ethernet" }, 147 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 148 "Netgear GA620 1000BASE-SX Ethernet" }, 149 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 150 "Netgear GA620 1000BASE-T Ethernet" }, 151 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 152 "Silicon Graphics Gigabit Ethernet" }, 153 { 0, 0, NULL } 154 }; 155 156 static const struct ti_type *ti_type_match __P((struct pci_attach_args *)); 157 static int ti_probe __P((struct device *, struct cfdata *, void *)); 158 static void ti_attach __P((struct device *, struct device *, void *)); 159 static void ti_shutdown __P((void *)); 160 static void ti_txeof_tigon1 __P((struct ti_softc *)); 161 static void ti_txeof_tigon2 __P((struct ti_softc *)); 162 static void ti_rxeof __P((struct ti_softc *)); 163 164 static void ti_stats_update __P((struct ti_softc *)); 165 static int ti_encap_tigon1 __P((struct ti_softc *, struct mbuf *, 166 u_int32_t *)); 167 static int ti_encap_tigon2 __P((struct ti_softc *, struct mbuf *, 168 u_int32_t *)); 169 170 static int ti_intr __P((void *)); 171 static void ti_start __P((struct ifnet *)); 172 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 173 static void ti_init __P((void *)); 174 static void ti_init2 __P((struct ti_softc *)); 175 static void ti_stop __P((struct ti_softc *)); 176 static void ti_watchdog __P((struct ifnet *)); 177 static int ti_ifmedia_upd __P((struct ifnet *)); 178 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 179 180 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 181 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 182 int, u_int8_t *)); 183 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 184 185 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 186 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 187 static void ti_setmulti __P((struct ti_softc *)); 188 189 static void ti_mem __P((struct ti_softc *, u_int32_t, 190 u_int32_t, caddr_t)); 191 static void ti_loadfw __P((struct ti_softc *)); 192 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 193 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 194 caddr_t, int)); 195 static void ti_handle_events __P((struct ti_softc *)); 196 static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 197 static void *ti_jalloc __P((struct ti_softc *)); 198 static void ti_jfree __P((struct mbuf *, caddr_t, u_int, void *)); 199 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 200 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 201 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 202 static int ti_init_rx_ring_std __P((struct ti_softc *)); 203 static void ti_free_rx_ring_std __P((struct ti_softc *)); 204 static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 205 static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 206 static int ti_init_rx_ring_mini __P((struct ti_softc *)); 207 static void ti_free_rx_ring_mini __P((struct ti_softc *)); 208 static void ti_free_tx_ring __P((struct ti_softc *)); 209 static int ti_init_tx_ring __P((struct ti_softc *)); 210 211 static int ti_64bitslot_war __P((struct ti_softc *)); 212 static int ti_chipinit __P((struct ti_softc *)); 213 static int ti_gibinit __P((struct ti_softc *)); 214 215 static int ti_ether_ioctl __P((struct ifnet *, u_long, caddr_t)); 216 217 struct cfattach ti_ca = { 218 sizeof(struct ti_softc), ti_probe, ti_attach 219 }; 220 221 /* 222 * Send an instruction or address to the EEPROM, check for ACK. 223 */ 224 static u_int32_t ti_eeprom_putbyte(sc, byte) 225 struct ti_softc *sc; 226 int byte; 227 { 228 int i, ack = 0; 229 230 /* 231 * Make sure we're in TX mode. 232 */ 233 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 234 235 /* 236 * Feed in each bit and stobe the clock. 237 */ 238 for (i = 0x80; i; i >>= 1) { 239 if (byte & i) { 240 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 241 } else { 242 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 243 } 244 DELAY(1); 245 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 246 DELAY(1); 247 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 248 } 249 250 /* 251 * Turn off TX mode. 252 */ 253 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 254 255 /* 256 * Check for ack. 257 */ 258 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 259 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 260 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 261 262 return(ack); 263 } 264 265 /* 266 * Read a byte of data stored in the EEPROM at address 'addr.' 267 * We have to send two address bytes since the EEPROM can hold 268 * more than 256 bytes of data. 269 */ 270 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 271 struct ti_softc *sc; 272 int addr; 273 u_int8_t *dest; 274 { 275 int i; 276 u_int8_t byte = 0; 277 278 EEPROM_START; 279 280 /* 281 * Send write control code to EEPROM. 282 */ 283 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 284 printf("%s: failed to send write command, status: %x\n", 285 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 286 return(1); 287 } 288 289 /* 290 * Send first byte of address of byte we want to read. 291 */ 292 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 293 printf("%s: failed to send address, status: %x\n", 294 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 295 return(1); 296 } 297 /* 298 * Send second byte address of byte we want to read. 299 */ 300 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 301 printf("%s: failed to send address, status: %x\n", 302 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 303 return(1); 304 } 305 306 EEPROM_STOP; 307 EEPROM_START; 308 /* 309 * Send read control code to EEPROM. 310 */ 311 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 312 printf("%s: failed to send read command, status: %x\n", 313 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 314 return(1); 315 } 316 317 /* 318 * Start reading bits from EEPROM. 319 */ 320 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 321 for (i = 0x80; i; i >>= 1) { 322 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 323 DELAY(1); 324 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 325 byte |= i; 326 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 327 DELAY(1); 328 } 329 330 EEPROM_STOP; 331 332 /* 333 * No ACK generated for read, so just return byte. 334 */ 335 336 *dest = byte; 337 338 return(0); 339 } 340 341 /* 342 * Read a sequence of bytes from the EEPROM. 343 */ 344 static int ti_read_eeprom(sc, dest, off, cnt) 345 struct ti_softc *sc; 346 caddr_t dest; 347 int off; 348 int cnt; 349 { 350 int err = 0, i; 351 u_int8_t byte = 0; 352 353 for (i = 0; i < cnt; i++) { 354 err = ti_eeprom_getbyte(sc, off + i, &byte); 355 if (err) 356 break; 357 *(dest + i) = byte; 358 } 359 360 return(err ? 1 : 0); 361 } 362 363 /* 364 * NIC memory access function. Can be used to either clear a section 365 * of NIC local memory or (if buf is non-NULL) copy data into it. 366 */ 367 static void ti_mem(sc, addr, len, buf) 368 struct ti_softc *sc; 369 u_int32_t addr, len; 370 caddr_t buf; 371 { 372 int segptr, segsize, cnt; 373 caddr_t ptr; 374 375 segptr = addr; 376 cnt = len; 377 ptr = buf; 378 379 while(cnt) { 380 if (cnt < TI_WINLEN) 381 segsize = cnt; 382 else 383 segsize = TI_WINLEN - (segptr % TI_WINLEN); 384 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 385 if (buf == NULL) { 386 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 387 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 388 segsize / 4); 389 } else { 390 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 391 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 392 (u_int32_t *)ptr, segsize / 4); 393 ptr += segsize; 394 } 395 segptr += segsize; 396 cnt -= segsize; 397 } 398 399 return; 400 } 401 402 /* 403 * Load firmware image into the NIC. Check that the firmware revision 404 * is acceptable and see if we want the firmware for the Tigon 1 or 405 * Tigon 2. 406 */ 407 static void ti_loadfw(sc) 408 struct ti_softc *sc; 409 { 410 switch(sc->ti_hwrev) { 411 case TI_HWREV_TIGON: 412 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 413 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 414 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 415 printf("%s: firmware revision mismatch; want " 416 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 417 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 418 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 419 tigonFwReleaseMinor, tigonFwReleaseFix); 420 return; 421 } 422 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 423 (caddr_t)tigonFwText); 424 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 425 (caddr_t)tigonFwData); 426 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 427 (caddr_t)tigonFwRodata); 428 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 429 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 430 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 431 break; 432 case TI_HWREV_TIGON_II: 433 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 434 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 435 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 436 printf("%s: firmware revision mismatch; want " 437 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 438 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 439 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 440 tigon2FwReleaseMinor, tigon2FwReleaseFix); 441 return; 442 } 443 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 444 (caddr_t)tigon2FwText); 445 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 446 (caddr_t)tigon2FwData); 447 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 448 (caddr_t)tigon2FwRodata); 449 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 450 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 451 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 452 break; 453 default: 454 printf("%s: can't load firmware: unknown hardware rev\n", 455 sc->sc_dev.dv_xname); 456 break; 457 } 458 459 return; 460 } 461 462 /* 463 * Send the NIC a command via the command ring. 464 */ 465 static void ti_cmd(sc, cmd) 466 struct ti_softc *sc; 467 struct ti_cmd_desc *cmd; 468 { 469 u_int32_t index; 470 471 index = sc->ti_cmd_saved_prodidx; 472 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 473 TI_INC(index, TI_CMD_RING_CNT); 474 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 475 sc->ti_cmd_saved_prodidx = index; 476 477 return; 478 } 479 480 /* 481 * Send the NIC an extended command. The 'len' parameter specifies the 482 * number of command slots to include after the initial command. 483 */ 484 static void ti_cmd_ext(sc, cmd, arg, len) 485 struct ti_softc *sc; 486 struct ti_cmd_desc *cmd; 487 caddr_t arg; 488 int len; 489 { 490 u_int32_t index; 491 int i; 492 493 index = sc->ti_cmd_saved_prodidx; 494 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 495 TI_INC(index, TI_CMD_RING_CNT); 496 for (i = 0; i < len; i++) { 497 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 498 *(u_int32_t *)(&arg[i * 4])); 499 TI_INC(index, TI_CMD_RING_CNT); 500 } 501 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 502 sc->ti_cmd_saved_prodidx = index; 503 504 return; 505 } 506 507 /* 508 * Handle events that have triggered interrupts. 509 */ 510 static void ti_handle_events(sc) 511 struct ti_softc *sc; 512 { 513 struct ti_event_desc *e; 514 515 if (sc->ti_rdata->ti_event_ring == NULL) 516 return; 517 518 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 519 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 520 switch(e->ti_event) { 521 case TI_EV_LINKSTAT_CHANGED: 522 sc->ti_linkstat = e->ti_code; 523 if (e->ti_code == TI_EV_CODE_LINK_UP) 524 printf("%s: 10/100 link up\n", 525 sc->sc_dev.dv_xname); 526 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 527 printf("%s: gigabit link up\n", 528 sc->sc_dev.dv_xname); 529 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 530 printf("%s: link down\n", 531 sc->sc_dev.dv_xname); 532 break; 533 case TI_EV_ERROR: 534 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 535 printf("%s: invalid command\n", 536 sc->sc_dev.dv_xname); 537 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 538 printf("%s: unknown command\n", 539 sc->sc_dev.dv_xname); 540 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 541 printf("%s: bad config data\n", 542 sc->sc_dev.dv_xname); 543 break; 544 case TI_EV_FIRMWARE_UP: 545 ti_init2(sc); 546 break; 547 case TI_EV_STATS_UPDATED: 548 ti_stats_update(sc); 549 break; 550 case TI_EV_RESET_JUMBO_RING: 551 case TI_EV_MCAST_UPDATED: 552 /* Who cares. */ 553 break; 554 default: 555 printf("%s: unknown event: %d\n", 556 sc->sc_dev.dv_xname, e->ti_event); 557 break; 558 } 559 /* Advance the consumer index. */ 560 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 561 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 562 } 563 564 return; 565 } 566 567 /* 568 * Memory management for the jumbo receive ring is a pain in the 569 * butt. We need to allocate at least 9018 bytes of space per frame, 570 * _and_ it has to be contiguous (unless you use the extended 571 * jumbo descriptor format). Using malloc() all the time won't 572 * work: malloc() allocates memory in powers of two, which means we 573 * would end up wasting a considerable amount of space by allocating 574 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 575 * to do our own memory management. 576 * 577 * The driver needs to allocate a contiguous chunk of memory at boot 578 * time. We then chop this up ourselves into 9K pieces and use them 579 * as external mbuf storage. 580 * 581 * One issue here is how much memory to allocate. The jumbo ring has 582 * 256 slots in it, but at 9K per slot than can consume over 2MB of 583 * RAM. This is a bit much, especially considering we also need 584 * RAM for the standard ring and mini ring (on the Tigon 2). To 585 * save space, we only actually allocate enough memory for 64 slots 586 * by default, which works out to between 500 and 600K. This can 587 * be tuned by changing a #define in if_tireg.h. 588 */ 589 590 static int ti_alloc_jumbo_mem(sc) 591 struct ti_softc *sc; 592 { 593 caddr_t ptr; 594 int i; 595 struct ti_jpool_entry *entry; 596 bus_dma_segment_t dmaseg; 597 int error, dmanseg; 598 599 /* Grab a big chunk o' storage. */ 600 if ((error = bus_dmamem_alloc(sc->sc_dmat, 601 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 602 BUS_DMA_NOWAIT)) != 0) { 603 printf("%s: can't allocate jumbo buffer, error = %d\n", 604 sc->sc_dev.dv_xname, error); 605 return (error); 606 } 607 608 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 609 TI_JMEM, (caddr_t *)&sc->ti_cdata.ti_jumbo_buf, 610 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 611 printf("%s: can't map jumbo buffer, error = %d\n", 612 sc->sc_dev.dv_xname, error); 613 return (error); 614 } 615 616 if ((error = bus_dmamap_create(sc->sc_dmat, 617 TI_JMEM, 1, 618 TI_JMEM, 0, BUS_DMA_NOWAIT, 619 &sc->jumbo_dmamap)) != 0) { 620 printf("%s: can't create jumbo buffer DMA map, error = %d\n", 621 sc->sc_dev.dv_xname, error); 622 return (error); 623 } 624 625 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 626 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 627 BUS_DMA_NOWAIT)) != 0) { 628 printf("%s: can't load jumbo buffer DMA map, error = %d\n", 629 sc->sc_dev.dv_xname, error); 630 return (error); 631 } 632 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 633 634 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 635 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 636 637 /* 638 * Now divide it up into 9K pieces and save the addresses 639 * in an array. 640 */ 641 ptr = sc->ti_cdata.ti_jumbo_buf; 642 for (i = 0; i < TI_JSLOTS; i++) { 643 sc->ti_cdata.ti_jslots[i] = ptr; 644 ptr += TI_JLEN; 645 entry = malloc(sizeof(struct ti_jpool_entry), 646 M_DEVBUF, M_NOWAIT); 647 if (entry == NULL) { 648 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 649 sc->ti_cdata.ti_jumbo_buf = NULL; 650 printf("%s: no memory for jumbo " 651 "buffer queue!\n", sc->sc_dev.dv_xname); 652 return(ENOBUFS); 653 } 654 entry->slot = i; 655 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 656 jpool_entries); 657 } 658 659 return(0); 660 } 661 662 /* 663 * Allocate a jumbo buffer. 664 */ 665 static void *ti_jalloc(sc) 666 struct ti_softc *sc; 667 { 668 struct ti_jpool_entry *entry; 669 670 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 671 672 if (entry == NULL) { 673 printf("%s: no free jumbo buffers\n", sc->sc_dev.dv_xname); 674 return(NULL); 675 } 676 677 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 678 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 679 return(sc->ti_cdata.ti_jslots[entry->slot]); 680 } 681 682 /* 683 * Release a jumbo buffer. 684 */ 685 static void ti_jfree(m, buf, size, arg) 686 struct mbuf *m; 687 caddr_t buf; 688 u_int size; 689 void *arg; 690 { 691 struct ti_softc *sc; 692 int i, s; 693 struct ti_jpool_entry *entry; 694 695 /* Extract the softc struct pointer. */ 696 sc = (struct ti_softc *)arg; 697 698 if (sc == NULL) 699 panic("ti_jfree: didn't get softc pointer!"); 700 701 /* calculate the slot this buffer belongs to */ 702 703 i = ((caddr_t)buf 704 - (caddr_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 705 706 if ((i < 0) || (i >= TI_JSLOTS)) 707 panic("ti_jfree: asked to free buffer that we don't manage!"); 708 709 s = splvm(); 710 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 711 if (entry == NULL) 712 panic("ti_jfree: buffer not in use!"); 713 entry->slot = i; 714 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 715 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 716 717 if (__predict_true(m != NULL)) 718 pool_cache_put(&mbpool_cache, m); 719 splx(s); 720 } 721 722 723 /* 724 * Intialize a standard receive ring descriptor. 725 */ 726 static int ti_newbuf_std(sc, i, m, dmamap) 727 struct ti_softc *sc; 728 int i; 729 struct mbuf *m; 730 bus_dmamap_t dmamap; /* required if (m != NULL) */ 731 { 732 struct mbuf *m_new = NULL; 733 struct ti_rx_desc *r; 734 int error; 735 736 if (dmamap == NULL) { 737 /* if (m) panic() */ 738 739 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 740 MCLBYTES, 0, BUS_DMA_NOWAIT, 741 &dmamap)) != 0) { 742 printf("%s: can't create recv map, error = %d\n", 743 sc->sc_dev.dv_xname, error); 744 return(ENOMEM); 745 } 746 } 747 sc->std_dmamap[i] = dmamap; 748 749 if (m == NULL) { 750 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 751 if (m_new == NULL) { 752 printf("%s: mbuf allocation failed " 753 "-- packet dropped!\n", sc->sc_dev.dv_xname); 754 return(ENOBUFS); 755 } 756 757 MCLGET(m_new, M_DONTWAIT); 758 if (!(m_new->m_flags & M_EXT)) { 759 printf("%s: cluster allocation failed " 760 "-- packet dropped!\n", sc->sc_dev.dv_xname); 761 m_freem(m_new); 762 return(ENOBUFS); 763 } 764 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 765 m_adj(m_new, ETHER_ALIGN); 766 767 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 768 mtod(m_new, caddr_t), m_new->m_len, NULL, 769 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 770 printf("%s: can't load recv map, error = %d\n", 771 sc->sc_dev.dv_xname, error); 772 return (ENOMEM); 773 } 774 } else { 775 m_new = m; 776 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 777 m_new->m_data = m_new->m_ext.ext_buf; 778 m_adj(m_new, ETHER_ALIGN); 779 780 /* reuse the dmamap */ 781 } 782 783 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 784 r = &sc->ti_rdata->ti_rx_std_ring[i]; 785 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 786 r->ti_type = TI_BDTYPE_RECV_BD; 787 r->ti_flags = 0; 788 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 789 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 790 if (sc->ethercom.ec_if.if_capenable & 791 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 792 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 793 r->ti_len = m_new->m_len; /* == ds_len */ 794 r->ti_idx = i; 795 796 return(0); 797 } 798 799 /* 800 * Intialize a mini receive ring descriptor. This only applies to 801 * the Tigon 2. 802 */ 803 static int ti_newbuf_mini(sc, i, m, dmamap) 804 struct ti_softc *sc; 805 int i; 806 struct mbuf *m; 807 bus_dmamap_t dmamap; /* required if (m != NULL) */ 808 { 809 struct mbuf *m_new = NULL; 810 struct ti_rx_desc *r; 811 int error; 812 813 if (dmamap == NULL) { 814 /* if (m) panic() */ 815 816 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 817 MHLEN, 0, BUS_DMA_NOWAIT, 818 &dmamap)) != 0) { 819 printf("%s: can't create recv map, error = %d\n", 820 sc->sc_dev.dv_xname, error); 821 return(ENOMEM); 822 } 823 } 824 sc->mini_dmamap[i] = dmamap; 825 826 if (m == NULL) { 827 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 828 if (m_new == NULL) { 829 printf("%s: mbuf allocation failed " 830 "-- packet dropped!\n", sc->sc_dev.dv_xname); 831 return(ENOBUFS); 832 } 833 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 834 m_adj(m_new, ETHER_ALIGN); 835 836 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 837 mtod(m_new, caddr_t), m_new->m_len, NULL, 838 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 839 printf("%s: can't load recv map, error = %d\n", 840 sc->sc_dev.dv_xname, error); 841 return (ENOMEM); 842 } 843 } else { 844 m_new = m; 845 m_new->m_data = m_new->m_pktdat; 846 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 847 m_adj(m_new, ETHER_ALIGN); 848 849 /* reuse the dmamap */ 850 } 851 852 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 853 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 854 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 855 r->ti_type = TI_BDTYPE_RECV_BD; 856 r->ti_flags = TI_BDFLAG_MINI_RING; 857 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 858 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 859 if (sc->ethercom.ec_if.if_capenable & 860 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 861 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 862 r->ti_len = m_new->m_len; /* == ds_len */ 863 r->ti_idx = i; 864 865 return(0); 866 } 867 868 /* 869 * Initialize a jumbo receive ring descriptor. This allocates 870 * a jumbo buffer from the pool managed internally by the driver. 871 */ 872 static int ti_newbuf_jumbo(sc, i, m) 873 struct ti_softc *sc; 874 int i; 875 struct mbuf *m; 876 { 877 struct mbuf *m_new = NULL; 878 struct ti_rx_desc *r; 879 880 if (m == NULL) { 881 caddr_t *buf = NULL; 882 883 /* Allocate the mbuf. */ 884 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 885 if (m_new == NULL) { 886 printf("%s: mbuf allocation failed " 887 "-- packet dropped!\n", sc->sc_dev.dv_xname); 888 return(ENOBUFS); 889 } 890 891 /* Allocate the jumbo buffer */ 892 buf = ti_jalloc(sc); 893 if (buf == NULL) { 894 m_freem(m_new); 895 printf("%s: jumbo allocation failed " 896 "-- packet dropped!\n", sc->sc_dev.dv_xname); 897 return(ENOBUFS); 898 } 899 900 /* Attach the buffer to the mbuf. */ 901 MEXTADD(m_new, (void *)buf, ETHER_MAX_LEN_JUMBO, 902 M_DEVBUF, ti_jfree, sc); 903 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 904 } else { 905 m_new = m; 906 m_new->m_data = m_new->m_ext.ext_buf; 907 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 908 } 909 910 m_adj(m_new, ETHER_ALIGN); 911 /* Set up the descriptor. */ 912 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 913 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 914 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 915 ((caddr_t)mtod(m_new, caddr_t) 916 - (caddr_t)sc->ti_cdata.ti_jumbo_buf); 917 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 918 r->ti_flags = TI_BDFLAG_JUMBO_RING; 919 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 920 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 921 if (sc->ethercom.ec_if.if_capenable & 922 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 923 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 924 r->ti_len = m_new->m_len; 925 r->ti_idx = i; 926 927 return(0); 928 } 929 930 /* 931 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 932 * that's 1MB or memory, which is a lot. For now, we fill only the first 933 * 256 ring entries and hope that our CPU is fast enough to keep up with 934 * the NIC. 935 */ 936 static int ti_init_rx_ring_std(sc) 937 struct ti_softc *sc; 938 { 939 int i; 940 struct ti_cmd_desc cmd; 941 942 for (i = 0; i < TI_SSLOTS; i++) { 943 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 944 return(ENOBUFS); 945 }; 946 947 TI_UPDATE_STDPROD(sc, i - 1); 948 sc->ti_std = i - 1; 949 950 return(0); 951 } 952 953 static void ti_free_rx_ring_std(sc) 954 struct ti_softc *sc; 955 { 956 int i; 957 958 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 959 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 960 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 961 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 962 963 /* if (sc->std_dmamap[i] == 0) panic() */ 964 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 965 sc->std_dmamap[i] = 0; 966 } 967 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 968 sizeof(struct ti_rx_desc)); 969 } 970 971 return; 972 } 973 974 static int ti_init_rx_ring_jumbo(sc) 975 struct ti_softc *sc; 976 { 977 int i; 978 struct ti_cmd_desc cmd; 979 980 for (i = 0; i < (TI_JSLOTS - 20); i++) { 981 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 982 return(ENOBUFS); 983 }; 984 985 TI_UPDATE_JUMBOPROD(sc, i - 1); 986 sc->ti_jumbo = i - 1; 987 988 return(0); 989 } 990 991 static void ti_free_rx_ring_jumbo(sc) 992 struct ti_softc *sc; 993 { 994 int i; 995 996 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 997 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 998 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 999 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1000 } 1001 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 1002 sizeof(struct ti_rx_desc)); 1003 } 1004 1005 return; 1006 } 1007 1008 static int ti_init_rx_ring_mini(sc) 1009 struct ti_softc *sc; 1010 { 1011 int i; 1012 1013 for (i = 0; i < TI_MSLOTS; i++) { 1014 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 1015 return(ENOBUFS); 1016 }; 1017 1018 TI_UPDATE_MINIPROD(sc, i - 1); 1019 sc->ti_mini = i - 1; 1020 1021 return(0); 1022 } 1023 1024 static void ti_free_rx_ring_mini(sc) 1025 struct ti_softc *sc; 1026 { 1027 int i; 1028 1029 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1030 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1031 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1032 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1033 1034 /* if (sc->mini_dmamap[i] == 0) panic() */ 1035 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1036 sc->mini_dmamap[i] = 0; 1037 } 1038 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1039 sizeof(struct ti_rx_desc)); 1040 } 1041 1042 return; 1043 } 1044 1045 static void ti_free_tx_ring(sc) 1046 struct ti_softc *sc; 1047 { 1048 int i; 1049 struct txdmamap_pool_entry *dma; 1050 1051 if (sc->ti_rdata->ti_tx_ring == NULL) 1052 return; 1053 1054 for (i = 0; i < TI_TX_RING_CNT; i++) { 1055 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1056 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1057 sc->ti_cdata.ti_tx_chain[i] = NULL; 1058 1059 /* if (sc->txdma[i] == 0) panic() */ 1060 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1061 link); 1062 sc->txdma[i] = 0; 1063 } 1064 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1065 sizeof(struct ti_tx_desc)); 1066 } 1067 1068 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1069 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1070 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1071 free(dma, M_DEVBUF); 1072 } 1073 1074 return; 1075 } 1076 1077 static int ti_init_tx_ring(sc) 1078 struct ti_softc *sc; 1079 { 1080 int i, error; 1081 bus_dmamap_t dmamap; 1082 struct txdmamap_pool_entry *dma; 1083 1084 sc->ti_txcnt = 0; 1085 sc->ti_tx_saved_considx = 0; 1086 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1087 1088 SIMPLEQ_INIT(&sc->txdma_list); 1089 for (i = 0; i < TI_RSLOTS; i++) { 1090 /* I've seen mbufs with 30 fragments. */ 1091 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 1092 40, ETHER_MAX_LEN_JUMBO, 0, 1093 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1094 printf("%s: can't create tx map, error = %d\n", 1095 sc->sc_dev.dv_xname, error); 1096 return(ENOMEM); 1097 } 1098 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1099 if (!dma) { 1100 printf("%s: can't alloc txdmamap_pool_entry\n", 1101 sc->sc_dev.dv_xname); 1102 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1103 return (ENOMEM); 1104 } 1105 dma->dmamap = dmamap; 1106 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1107 } 1108 1109 return(0); 1110 } 1111 1112 /* 1113 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1114 * but we have to support the old way too so that Tigon 1 cards will 1115 * work. 1116 */ 1117 void ti_add_mcast(sc, addr) 1118 struct ti_softc *sc; 1119 struct ether_addr *addr; 1120 { 1121 struct ti_cmd_desc cmd; 1122 u_int16_t *m; 1123 u_int32_t ext[2] = {0, 0}; 1124 1125 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1126 1127 switch(sc->ti_hwrev) { 1128 case TI_HWREV_TIGON: 1129 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1130 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1131 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1132 break; 1133 case TI_HWREV_TIGON_II: 1134 ext[0] = htons(m[0]); 1135 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1136 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1137 break; 1138 default: 1139 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1140 break; 1141 } 1142 1143 return; 1144 } 1145 1146 void ti_del_mcast(sc, addr) 1147 struct ti_softc *sc; 1148 struct ether_addr *addr; 1149 { 1150 struct ti_cmd_desc cmd; 1151 u_int16_t *m; 1152 u_int32_t ext[2] = {0, 0}; 1153 1154 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1155 1156 switch(sc->ti_hwrev) { 1157 case TI_HWREV_TIGON: 1158 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1159 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1160 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1161 break; 1162 case TI_HWREV_TIGON_II: 1163 ext[0] = htons(m[0]); 1164 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1165 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1166 break; 1167 default: 1168 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1169 break; 1170 } 1171 1172 return; 1173 } 1174 1175 /* 1176 * Configure the Tigon's multicast address filter. 1177 * 1178 * The actual multicast table management is a bit of a pain, thanks to 1179 * slight brain damage on the part of both Alteon and us. With our 1180 * multicast code, we are only alerted when the multicast address table 1181 * changes and at that point we only have the current list of addresses: 1182 * we only know the current state, not the previous state, so we don't 1183 * actually know what addresses were removed or added. The firmware has 1184 * state, but we can't get our grubby mits on it, and there is no 'delete 1185 * all multicast addresses' command. Hence, we have to maintain our own 1186 * state so we know what addresses have been programmed into the NIC at 1187 * any given time. 1188 */ 1189 static void ti_setmulti(sc) 1190 struct ti_softc *sc; 1191 { 1192 struct ifnet *ifp; 1193 struct ti_cmd_desc cmd; 1194 struct ti_mc_entry *mc; 1195 u_int32_t intrs; 1196 struct ether_multi *enm; 1197 struct ether_multistep step; 1198 1199 ifp = &sc->ethercom.ec_if; 1200 1201 /* Disable interrupts. */ 1202 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1203 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1204 1205 /* First, zot all the existing filters. */ 1206 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1207 ti_del_mcast(sc, &mc->mc_addr); 1208 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1209 free(mc, M_DEVBUF); 1210 } 1211 1212 /* 1213 * Remember all multicast addresses so that we can delete them 1214 * later. Punt if there is a range of addresses or memory shortage. 1215 */ 1216 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1217 while (enm != NULL) { 1218 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1219 ETHER_ADDR_LEN) != 0) 1220 goto allmulti; 1221 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1222 M_NOWAIT)) == NULL) 1223 goto allmulti; 1224 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1225 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1226 ETHER_NEXT_MULTI(step, enm); 1227 } 1228 1229 /* Accept only programmed multicast addresses */ 1230 ifp->if_flags &= ~IFF_ALLMULTI; 1231 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1232 1233 /* Now program new ones. */ 1234 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1235 ti_add_mcast(sc, &mc->mc_addr); 1236 1237 /* Re-enable interrupts. */ 1238 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1239 1240 return; 1241 1242 allmulti: 1243 /* No need to keep individual multicast addresses */ 1244 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1245 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1246 free(mc, M_DEVBUF); 1247 } 1248 1249 /* Accept all multicast addresses */ 1250 ifp->if_flags |= IFF_ALLMULTI; 1251 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1252 1253 /* Re-enable interrupts. */ 1254 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1255 } 1256 1257 /* 1258 * Check to see if the BIOS has configured us for a 64 bit slot when 1259 * we aren't actually in one. If we detect this condition, we can work 1260 * around it on the Tigon 2 by setting a bit in the PCI state register, 1261 * but for the Tigon 1 we must give up and abort the interface attach. 1262 */ 1263 static int ti_64bitslot_war(sc) 1264 struct ti_softc *sc; 1265 { 1266 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1267 CSR_WRITE_4(sc, 0x600, 0); 1268 CSR_WRITE_4(sc, 0x604, 0); 1269 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1270 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1271 if (sc->ti_hwrev == TI_HWREV_TIGON) 1272 return(EINVAL); 1273 else { 1274 TI_SETBIT(sc, TI_PCI_STATE, 1275 TI_PCISTATE_32BIT_BUS); 1276 return(0); 1277 } 1278 } 1279 } 1280 1281 return(0); 1282 } 1283 1284 /* 1285 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1286 * self-test results. 1287 */ 1288 static int ti_chipinit(sc) 1289 struct ti_softc *sc; 1290 { 1291 u_int32_t cacheline; 1292 u_int32_t pci_writemax = 0; 1293 1294 /* Initialize link to down state. */ 1295 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1296 1297 /* Set endianness before we access any non-PCI registers. */ 1298 #if BYTE_ORDER == BIG_ENDIAN 1299 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1300 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1301 #else 1302 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1303 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1304 #endif 1305 1306 /* Check the ROM failed bit to see if self-tests passed. */ 1307 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1308 printf("%s: board self-diagnostics failed!\n", 1309 sc->sc_dev.dv_xname); 1310 return(ENODEV); 1311 } 1312 1313 /* Halt the CPU. */ 1314 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1315 1316 /* Figure out the hardware revision. */ 1317 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1318 case TI_REV_TIGON_I: 1319 sc->ti_hwrev = TI_HWREV_TIGON; 1320 break; 1321 case TI_REV_TIGON_II: 1322 sc->ti_hwrev = TI_HWREV_TIGON_II; 1323 break; 1324 default: 1325 printf("%s: unsupported chip revision\n", sc->sc_dev.dv_xname); 1326 return(ENODEV); 1327 } 1328 1329 /* Do special setup for Tigon 2. */ 1330 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1331 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1332 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1333 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1334 } 1335 1336 /* Set up the PCI state register. */ 1337 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1338 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1339 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1340 } 1341 1342 /* Clear the read/write max DMA parameters. */ 1343 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1344 TI_PCISTATE_READ_MAXDMA)); 1345 1346 /* Get cache line size. */ 1347 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1348 1349 /* 1350 * If the system has set enabled the PCI memory write 1351 * and invalidate command in the command register, set 1352 * the write max parameter accordingly. This is necessary 1353 * to use MWI with the Tigon 2. 1354 */ 1355 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1356 & PCI_COMMAND_INVALIDATE_ENABLE) { 1357 switch(cacheline) { 1358 case 1: 1359 case 4: 1360 case 8: 1361 case 16: 1362 case 32: 1363 case 64: 1364 break; 1365 default: 1366 /* Disable PCI memory write and invalidate. */ 1367 if (bootverbose) 1368 printf("%s: cache line size %d not " 1369 "supported; disabling PCI MWI\n", 1370 sc->sc_dev.dv_xname, cacheline); 1371 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1372 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1373 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1374 break; 1375 } 1376 } 1377 1378 #ifdef __brokenalpha__ 1379 /* 1380 * From the Alteon sample driver: 1381 * Must insure that we do not cross an 8K (bytes) boundary 1382 * for DMA reads. Our highest limit is 1K bytes. This is a 1383 * restriction on some ALPHA platforms with early revision 1384 * 21174 PCI chipsets, such as the AlphaPC 164lx 1385 */ 1386 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1387 #else 1388 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1389 #endif 1390 1391 /* This sets the min dma param all the way up (0xff). */ 1392 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1393 1394 /* Configure DMA variables. */ 1395 #if BYTE_ORDER == BIG_ENDIAN 1396 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1397 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1398 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1399 TI_OPMODE_DONT_FRAG_JUMBO); 1400 #else 1401 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1402 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1403 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1404 #endif 1405 1406 /* 1407 * Only allow 1 DMA channel to be active at a time. 1408 * I don't think this is a good idea, but without it 1409 * the firmware racks up lots of nicDmaReadRingFull 1410 * errors. 1411 * Incompatible with hardware assisted checksums. 1412 */ 1413 if ((sc->ethercom.ec_if.if_capenable & 1414 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4|IFCAP_CSUM_IPv4)) == 0) 1415 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1416 1417 /* Recommended settings from Tigon manual. */ 1418 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1419 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1420 1421 if (ti_64bitslot_war(sc)) { 1422 printf("%s: bios thinks we're in a 64 bit slot, " 1423 "but we aren't", sc->sc_dev.dv_xname); 1424 return(EINVAL); 1425 } 1426 1427 return(0); 1428 } 1429 1430 /* 1431 * Initialize the general information block and firmware, and 1432 * start the CPU(s) running. 1433 */ 1434 static int ti_gibinit(sc) 1435 struct ti_softc *sc; 1436 { 1437 struct ti_rcb *rcb; 1438 int i; 1439 struct ifnet *ifp; 1440 1441 ifp = &sc->ethercom.ec_if; 1442 1443 /* Disable interrupts for now. */ 1444 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1445 1446 /* Tell the chip where to find the general information block. */ 1447 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1448 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1449 1450 /* Load the firmware into SRAM. */ 1451 ti_loadfw(sc); 1452 1453 /* Set up the contents of the general info and ring control blocks. */ 1454 1455 /* Set up the event ring and producer pointer. */ 1456 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1457 1458 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1459 rcb->ti_flags = 0; 1460 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1461 TI_CDEVPRODADDR(sc); 1462 1463 sc->ti_ev_prodidx.ti_idx = 0; 1464 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1465 sc->ti_ev_saved_considx = 0; 1466 1467 /* Set up the command ring and producer mailbox. */ 1468 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1469 1470 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1471 rcb->ti_flags = 0; 1472 rcb->ti_max_len = 0; 1473 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1474 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1475 } 1476 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1477 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1478 sc->ti_cmd_saved_prodidx = 0; 1479 1480 /* 1481 * Assign the address of the stats refresh buffer. 1482 * We re-use the current stats buffer for this to 1483 * conserve memory. 1484 */ 1485 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1486 TI_CDSTATSADDR(sc); 1487 1488 /* Set up the standard receive ring. */ 1489 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1490 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1491 rcb->ti_max_len = ETHER_MAX_LEN; 1492 rcb->ti_flags = 0; 1493 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1494 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1495 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1496 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1497 if (sc->ethercom.ec_nvlans != 0) 1498 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1499 1500 /* Set up the jumbo receive ring. */ 1501 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1502 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1503 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1504 rcb->ti_flags = 0; 1505 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1506 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1507 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1508 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1509 if (sc->ethercom.ec_nvlans != 0) 1510 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1511 1512 /* 1513 * Set up the mini ring. Only activated on the 1514 * Tigon 2 but the slot in the config block is 1515 * still there on the Tigon 1. 1516 */ 1517 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1518 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1519 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1520 if (sc->ti_hwrev == TI_HWREV_TIGON) 1521 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1522 else 1523 rcb->ti_flags = 0; 1524 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1525 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1526 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1527 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1528 if (sc->ethercom.ec_nvlans != 0) 1529 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1530 1531 /* 1532 * Set up the receive return ring. 1533 */ 1534 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1535 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1536 rcb->ti_flags = 0; 1537 rcb->ti_max_len = TI_RETURN_RING_CNT; 1538 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1539 TI_CDRTNPRODADDR(sc); 1540 1541 /* 1542 * Set up the tx ring. Note: for the Tigon 2, we have the option 1543 * of putting the transmit ring in the host's address space and 1544 * letting the chip DMA it instead of leaving the ring in the NIC's 1545 * memory and accessing it through the shared memory region. We 1546 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1547 * so we have to revert to the shared memory scheme if we detect 1548 * a Tigon 1 chip. 1549 */ 1550 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1551 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1552 sc->ti_tx_ring_nic = 1553 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1554 } 1555 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1556 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1557 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1558 if (sc->ti_hwrev == TI_HWREV_TIGON) 1559 rcb->ti_flags = 0; 1560 else 1561 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1562 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1563 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1564 /* 1565 * When we get the packet, there is a pseudo-header seed already 1566 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1567 * compute the pseudo-header checksum again! 1568 */ 1569 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1570 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM| 1571 TI_RCB_FLAG_NO_PHDR_CKSUM; 1572 if (sc->ethercom.ec_nvlans != 0) 1573 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1574 rcb->ti_max_len = TI_TX_RING_CNT; 1575 if (sc->ti_hwrev == TI_HWREV_TIGON) 1576 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1577 else 1578 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1579 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1580 TI_CDTXCONSADDR(sc); 1581 1582 /* 1583 * We're done frobbing the General Information Block. Sync 1584 * it. Note we take care of the first stats sync here, as 1585 * well. 1586 */ 1587 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1588 1589 /* Set up tuneables */ 1590 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1591 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1592 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1593 (sc->ti_rx_coal_ticks / 10)); 1594 else 1595 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1596 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1597 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1598 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1599 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1600 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1601 1602 /* Turn interrupts on. */ 1603 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1604 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1605 1606 /* Start CPU. */ 1607 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1608 1609 return(0); 1610 } 1611 1612 /* 1613 * look for id in the device list, returning the first match 1614 */ 1615 static const struct ti_type * 1616 ti_type_match(pa) 1617 struct pci_attach_args *pa; 1618 { 1619 const struct ti_type *t; 1620 1621 t = ti_devs; 1622 while(t->ti_name != NULL) { 1623 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1624 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1625 return (t); 1626 } 1627 t++; 1628 } 1629 1630 return(NULL); 1631 } 1632 1633 /* 1634 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1635 * against our list and return its name if we find a match. 1636 */ 1637 static int ti_probe(parent, match, aux) 1638 struct device *parent; 1639 struct cfdata *match; 1640 void *aux; 1641 { 1642 struct pci_attach_args *pa = aux; 1643 const struct ti_type *t; 1644 1645 t = ti_type_match(pa); 1646 1647 return((t == NULL) ? 0 : 1); 1648 } 1649 1650 static void ti_attach(parent, self, aux) 1651 struct device *parent, *self; 1652 void *aux; 1653 { 1654 u_int32_t command; 1655 struct ifnet *ifp; 1656 struct ti_softc *sc; 1657 u_char eaddr[ETHER_ADDR_LEN]; 1658 struct pci_attach_args *pa = aux; 1659 pci_chipset_tag_t pc = pa->pa_pc; 1660 pci_intr_handle_t ih; 1661 const char *intrstr = NULL; 1662 bus_dma_segment_t dmaseg; 1663 int error, dmanseg, nolinear; 1664 const struct ti_type *t; 1665 1666 t = ti_type_match(pa); 1667 if (t == NULL) { 1668 printf("ti_attach: were did the card go ?\n"); 1669 return; 1670 } 1671 1672 printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class)); 1673 1674 sc = (struct ti_softc *)self; 1675 1676 /* 1677 * Map control/status registers. 1678 */ 1679 nolinear = 0; 1680 if (pci_mapreg_map(pa, 0x10, 1681 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1682 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1683 NULL, NULL)) { 1684 nolinear = 1; 1685 if (pci_mapreg_map(pa, 0x10, 1686 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1687 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1688 printf(": can't map memory space\n"); 1689 return; 1690 } 1691 } 1692 if (nolinear == 0) 1693 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1694 else 1695 sc->ti_vhandle = NULL; 1696 1697 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1698 command |= PCI_COMMAND_MASTER_ENABLE; 1699 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1700 1701 /* Allocate interrupt */ 1702 if (pci_intr_map(pa, &ih)) { 1703 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 1704 return;; 1705 } 1706 intrstr = pci_intr_string(pc, ih); 1707 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1708 if (sc->sc_ih == NULL) { 1709 printf("%s: couldn't establish interrupt", 1710 sc->sc_dev.dv_xname); 1711 if (intrstr != NULL) 1712 printf(" at %s", intrstr); 1713 printf("\n"); 1714 return;; 1715 } 1716 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1717 /* 1718 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1719 * doing do could allow DMA to corrupt kernel memory during the 1720 * reboot before the driver initializes. 1721 */ 1722 (void) shutdownhook_establish(ti_shutdown, sc); 1723 1724 if (ti_chipinit(sc)) { 1725 printf("%s: chip initialization failed\n", self->dv_xname); 1726 goto fail2; 1727 } 1728 1729 /* 1730 * Deal with some chip diffrences. 1731 */ 1732 switch (sc->ti_hwrev) { 1733 case TI_HWREV_TIGON: 1734 sc->sc_tx_encap = ti_encap_tigon1; 1735 sc->sc_tx_eof = ti_txeof_tigon1; 1736 if (nolinear == 1) 1737 printf("%s: memory space not mapped linear\n", 1738 self->dv_xname); 1739 break; 1740 1741 case TI_HWREV_TIGON_II: 1742 sc->sc_tx_encap = ti_encap_tigon2; 1743 sc->sc_tx_eof = ti_txeof_tigon2; 1744 break; 1745 1746 default: 1747 printf("%s: Unknown chip version: %d\n", self->dv_xname, 1748 sc->ti_hwrev); 1749 goto fail2; 1750 } 1751 1752 /* Zero out the NIC's on-board SRAM. */ 1753 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1754 1755 /* Init again -- zeroing memory may have clobbered some registers. */ 1756 if (ti_chipinit(sc)) { 1757 printf("%s: chip initialization failed\n", self->dv_xname); 1758 goto fail2; 1759 } 1760 1761 /* 1762 * Get station address from the EEPROM. Note: the manual states 1763 * that the MAC address is at offset 0x8c, however the data is 1764 * stored as two longwords (since that's how it's loaded into 1765 * the NIC). This means the MAC address is actually preceded 1766 * by two zero bytes. We need to skip over those. 1767 */ 1768 if (ti_read_eeprom(sc, (caddr_t)&eaddr, 1769 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1770 printf("%s: failed to read station address\n", self->dv_xname); 1771 goto fail2; 1772 } 1773 1774 /* 1775 * A Tigon chip was detected. Inform the world. 1776 */ 1777 printf("%s: Ethernet address: %s\n", self->dv_xname, 1778 ether_sprintf(eaddr)); 1779 1780 sc->sc_dmat = pa->pa_dmat; 1781 1782 /* Allocate the general information block and ring buffers. */ 1783 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1784 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1785 BUS_DMA_NOWAIT)) != 0) { 1786 printf("%s: can't allocate ring buffer, error = %d\n", 1787 sc->sc_dev.dv_xname, error); 1788 goto fail2; 1789 } 1790 1791 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1792 sizeof(struct ti_ring_data), (caddr_t *)&sc->ti_rdata, 1793 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1794 printf("%s: can't map ring buffer, error = %d\n", 1795 sc->sc_dev.dv_xname, error); 1796 goto fail2; 1797 } 1798 1799 if ((error = bus_dmamap_create(sc->sc_dmat, 1800 sizeof(struct ti_ring_data), 1, 1801 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1802 &sc->info_dmamap)) != 0) { 1803 printf("%s: can't create ring buffer DMA map, error = %d\n", 1804 sc->sc_dev.dv_xname, error); 1805 goto fail2; 1806 } 1807 1808 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1809 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1810 BUS_DMA_NOWAIT)) != 0) { 1811 printf("%s: can't load ring buffer DMA map, error = %d\n", 1812 sc->sc_dev.dv_xname, error); 1813 goto fail2; 1814 } 1815 1816 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1817 1818 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1819 1820 /* Try to allocate memory for jumbo buffers. */ 1821 if (ti_alloc_jumbo_mem(sc)) { 1822 printf("%s: jumbo buffer allocation failed\n", self->dv_xname); 1823 goto fail2; 1824 } 1825 1826 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1827 1828 /* 1829 * We really need a better way to tell a 1000baseT card 1830 * from a 1000baseSX one, since in theory there could be 1831 * OEMed 1000baseT cards from lame vendors who aren't 1832 * clever enough to change the PCI ID. For the moment 1833 * though, the AceNIC is the only copper card available. 1834 */ 1835 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1836 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1837 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1838 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1839 sc->ti_copper = 1; 1840 else 1841 sc->ti_copper = 0; 1842 1843 /* Set default tuneable values. */ 1844 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1845 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1846 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1847 sc->ti_rx_max_coal_bds = 64; 1848 sc->ti_tx_max_coal_bds = 128; 1849 sc->ti_tx_buf_ratio = 21; 1850 1851 /* Set up ifnet structure */ 1852 ifp = &sc->ethercom.ec_if; 1853 ifp->if_softc = sc; 1854 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1855 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1856 ifp->if_ioctl = ti_ioctl; 1857 ifp->if_start = ti_start; 1858 ifp->if_watchdog = ti_watchdog; 1859 IFQ_SET_READY(&ifp->if_snd); 1860 1861 #if 0 1862 /* 1863 * XXX This is not really correct -- we don't necessarily 1864 * XXX want to queue up as many as we can transmit at the 1865 * XXX upper layer like that. Someone with a board should 1866 * XXX check to see how this affects performance. 1867 */ 1868 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1869 #endif 1870 1871 /* 1872 * We can support 802.1Q VLAN-sized frames. 1873 */ 1874 sc->ethercom.ec_capabilities |= 1875 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1876 1877 /* 1878 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1879 */ 1880 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1881 IFCAP_CSUM_UDPv4; 1882 1883 /* Set up ifmedia support. */ 1884 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1885 if (sc->ti_copper) { 1886 /* 1887 * Copper cards allow manual 10/100 mode selection, 1888 * but not manual 1000baseT mode selection. Why? 1889 * Becuase currently there's no way to specify the 1890 * master/slave setting through the firmware interface, 1891 * so Alteon decided to just bag it and handle it 1892 * via autonegotiation. 1893 */ 1894 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1895 ifmedia_add(&sc->ifmedia, 1896 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1897 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1898 ifmedia_add(&sc->ifmedia, 1899 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1900 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 1901 ifmedia_add(&sc->ifmedia, 1902 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 1903 } else { 1904 /* Fiber cards don't support 10/100 modes. */ 1905 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1906 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1907 } 1908 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1909 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1910 1911 /* 1912 * Call MI attach routines. 1913 */ 1914 if_attach(ifp); 1915 ether_ifattach(ifp, eaddr); 1916 1917 return; 1918 fail2: 1919 pci_intr_disestablish(pc, sc->sc_ih); 1920 return; 1921 } 1922 1923 /* 1924 * Frame reception handling. This is called if there's a frame 1925 * on the receive return list. 1926 * 1927 * Note: we have to be able to handle three possibilities here: 1928 * 1) the frame is from the mini receive ring (can only happen) 1929 * on Tigon 2 boards) 1930 * 2) the frame is from the jumbo receive ring 1931 * 3) the frame is from the standard receive ring 1932 */ 1933 1934 static void ti_rxeof(sc) 1935 struct ti_softc *sc; 1936 { 1937 struct ifnet *ifp; 1938 struct ti_cmd_desc cmd; 1939 1940 ifp = &sc->ethercom.ec_if; 1941 1942 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1943 struct ti_rx_desc *cur_rx; 1944 u_int32_t rxidx; 1945 struct mbuf *m = NULL; 1946 u_int16_t vlan_tag = 0; 1947 int have_tag = 0; 1948 struct ether_header *eh; 1949 bus_dmamap_t dmamap; 1950 1951 cur_rx = 1952 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1953 rxidx = cur_rx->ti_idx; 1954 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1955 1956 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1957 have_tag = 1; 1958 vlan_tag = cur_rx->ti_vlan_tag; 1959 } 1960 1961 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1962 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1963 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1964 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1965 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1966 ifp->if_ierrors++; 1967 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1968 continue; 1969 } 1970 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1971 == ENOBUFS) { 1972 ifp->if_ierrors++; 1973 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1974 continue; 1975 } 1976 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1977 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1978 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1979 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1980 dmamap = sc->mini_dmamap[rxidx]; 1981 sc->mini_dmamap[rxidx] = 0; 1982 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1983 ifp->if_ierrors++; 1984 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1985 continue; 1986 } 1987 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1988 == ENOBUFS) { 1989 ifp->if_ierrors++; 1990 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1991 continue; 1992 } 1993 } else { 1994 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1995 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1996 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1997 dmamap = sc->std_dmamap[rxidx]; 1998 sc->std_dmamap[rxidx] = 0; 1999 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2000 ifp->if_ierrors++; 2001 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2002 continue; 2003 } 2004 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 2005 == ENOBUFS) { 2006 ifp->if_ierrors++; 2007 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2008 continue; 2009 } 2010 } 2011 2012 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 2013 ifp->if_ipackets++; 2014 m->m_pkthdr.rcvif = ifp; 2015 2016 #if NBPFILTER > 0 2017 /* 2018 * Handle BPF listeners. Let the BPF user see the packet, but 2019 * don't pass it up to the ether_input() layer unless it's 2020 * a broadcast packet, multicast packet, matches our ethernet 2021 * address or the interface is in promiscuous mode. 2022 */ 2023 if (ifp->if_bpf) 2024 bpf_mtap(ifp->if_bpf, m); 2025 #endif 2026 2027 eh = mtod(m, struct ether_header *); 2028 switch (ntohs(eh->ether_type)) { 2029 #ifdef INET 2030 case ETHERTYPE_IP: 2031 { 2032 struct ip *ip = (struct ip *) (eh + 1); 2033 2034 /* 2035 * Note the Tigon firmware does not invert 2036 * the checksum for us, hence the XOR. 2037 */ 2038 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2039 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 2040 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2041 /* 2042 * ntohs() the constant so the compiler can 2043 * optimize... 2044 * 2045 * XXX Figure out a sane way to deal with 2046 * fragmented packets. 2047 */ 2048 if ((ip->ip_off & htons(IP_MF|IP_OFFMASK)) == 0) { 2049 switch (ip->ip_p) { 2050 case IPPROTO_TCP: 2051 m->m_pkthdr.csum_data = 2052 cur_rx->ti_tcp_udp_cksum; 2053 m->m_pkthdr.csum_flags |= 2054 M_CSUM_TCPv4|M_CSUM_DATA; 2055 break; 2056 case IPPROTO_UDP: 2057 m->m_pkthdr.csum_data = 2058 cur_rx->ti_tcp_udp_cksum; 2059 m->m_pkthdr.csum_flags |= 2060 M_CSUM_UDPv4|M_CSUM_DATA; 2061 break; 2062 default: 2063 /* Nothing */; 2064 } 2065 } 2066 break; 2067 } 2068 #endif 2069 default: 2070 /* Nothing. */ 2071 break; 2072 } 2073 2074 if (have_tag) { 2075 struct mbuf *n; 2076 n = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 2077 if (n) { 2078 *mtod(n, int *) = vlan_tag; 2079 n->m_len = sizeof(int); 2080 } else { 2081 printf("%s: no mbuf for tag\n", ifp->if_xname); 2082 m_freem(m); 2083 continue; 2084 } 2085 have_tag = vlan_tag = 0; 2086 } 2087 (*ifp->if_input)(ifp, m); 2088 } 2089 2090 /* Only necessary on the Tigon 1. */ 2091 if (sc->ti_hwrev == TI_HWREV_TIGON) 2092 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2093 sc->ti_rx_saved_considx); 2094 2095 TI_UPDATE_STDPROD(sc, sc->ti_std); 2096 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2097 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2098 2099 return; 2100 } 2101 2102 static void ti_txeof_tigon1(sc) 2103 struct ti_softc *sc; 2104 { 2105 struct ti_tx_desc *cur_tx = NULL; 2106 struct ifnet *ifp; 2107 struct txdmamap_pool_entry *dma; 2108 2109 ifp = &sc->ethercom.ec_if; 2110 2111 /* 2112 * Go through our tx ring and free mbufs for those 2113 * frames that have been sent. 2114 */ 2115 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2116 u_int32_t idx = 0; 2117 2118 idx = sc->ti_tx_saved_considx; 2119 if (idx > 383) 2120 CSR_WRITE_4(sc, TI_WINBASE, 2121 TI_TX_RING_BASE + 6144); 2122 else if (idx > 255) 2123 CSR_WRITE_4(sc, TI_WINBASE, 2124 TI_TX_RING_BASE + 4096); 2125 else if (idx > 127) 2126 CSR_WRITE_4(sc, TI_WINBASE, 2127 TI_TX_RING_BASE + 2048); 2128 else 2129 CSR_WRITE_4(sc, TI_WINBASE, 2130 TI_TX_RING_BASE); 2131 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2132 if (cur_tx->ti_flags & TI_BDFLAG_END) 2133 ifp->if_opackets++; 2134 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2135 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2136 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2137 2138 dma = sc->txdma[idx]; 2139 KDASSERT(dma != NULL); 2140 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2141 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2142 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2143 2144 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2145 sc->txdma[idx] = NULL; 2146 } 2147 sc->ti_txcnt--; 2148 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2149 ifp->if_timer = 0; 2150 } 2151 2152 if (cur_tx != NULL) 2153 ifp->if_flags &= ~IFF_OACTIVE; 2154 2155 return; 2156 } 2157 2158 static void ti_txeof_tigon2(sc) 2159 struct ti_softc *sc; 2160 { 2161 struct ti_tx_desc *cur_tx = NULL; 2162 struct ifnet *ifp; 2163 struct txdmamap_pool_entry *dma; 2164 int firstidx, cnt; 2165 2166 ifp = &sc->ethercom.ec_if; 2167 2168 /* 2169 * Go through our tx ring and free mbufs for those 2170 * frames that have been sent. 2171 */ 2172 firstidx = sc->ti_tx_saved_considx; 2173 cnt = 0; 2174 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2175 u_int32_t idx = 0; 2176 2177 idx = sc->ti_tx_saved_considx; 2178 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2179 if (cur_tx->ti_flags & TI_BDFLAG_END) 2180 ifp->if_opackets++; 2181 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2182 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2183 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2184 2185 dma = sc->txdma[idx]; 2186 KDASSERT(dma != NULL); 2187 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2188 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2189 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2190 2191 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2192 sc->txdma[idx] = NULL; 2193 } 2194 cnt++; 2195 sc->ti_txcnt--; 2196 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2197 ifp->if_timer = 0; 2198 } 2199 2200 if (cnt != 0) 2201 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2202 2203 if (cur_tx != NULL) 2204 ifp->if_flags &= ~IFF_OACTIVE; 2205 2206 return; 2207 } 2208 2209 static int ti_intr(xsc) 2210 void *xsc; 2211 { 2212 struct ti_softc *sc; 2213 struct ifnet *ifp; 2214 2215 sc = xsc; 2216 ifp = &sc->ethercom.ec_if; 2217 2218 #ifdef notdef 2219 /* Avoid this for now -- checking this register is expensive. */ 2220 /* Make sure this is really our interrupt. */ 2221 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2222 return (0); 2223 #endif 2224 2225 /* Ack interrupt and stop others from occuring. */ 2226 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2227 2228 if (ifp->if_flags & IFF_RUNNING) { 2229 /* Check RX return ring producer/consumer */ 2230 ti_rxeof(sc); 2231 2232 /* Check TX ring producer/consumer */ 2233 (*sc->sc_tx_eof)(sc); 2234 } 2235 2236 ti_handle_events(sc); 2237 2238 /* Re-enable interrupts. */ 2239 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2240 2241 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2242 IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2243 ti_start(ifp); 2244 2245 return (1); 2246 } 2247 2248 static void ti_stats_update(sc) 2249 struct ti_softc *sc; 2250 { 2251 struct ifnet *ifp; 2252 2253 ifp = &sc->ethercom.ec_if; 2254 2255 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2256 2257 ifp->if_collisions += 2258 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2259 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2260 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2261 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2262 ifp->if_collisions; 2263 2264 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2265 } 2266 2267 /* 2268 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2269 * pointers to descriptors. 2270 */ 2271 static int ti_encap_tigon1(sc, m_head, txidx) 2272 struct ti_softc *sc; 2273 struct mbuf *m_head; 2274 u_int32_t *txidx; 2275 { 2276 struct ti_tx_desc *f = NULL; 2277 u_int32_t frag, cur, cnt = 0; 2278 struct txdmamap_pool_entry *dma; 2279 bus_dmamap_t dmamap; 2280 int error, i; 2281 struct mbuf *n; 2282 u_int16_t csum_flags = 0; 2283 2284 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2285 if (dma == NULL) { 2286 return ENOMEM; 2287 } 2288 dmamap = dma->dmamap; 2289 2290 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2291 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2292 if (error) { 2293 struct mbuf *m; 2294 int i = 0; 2295 for (m = m_head; m; m = m->m_next) 2296 i++; 2297 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2298 "error %d\n", m_head->m_pkthdr.len, i, error); 2299 return (ENOMEM); 2300 } 2301 2302 cur = frag = *txidx; 2303 2304 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2305 /* IP header checksum field must be 0! */ 2306 csum_flags |= TI_BDFLAG_IP_CKSUM; 2307 } 2308 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2309 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2310 2311 /* XXX fragmented packet checksum capability? */ 2312 2313 /* 2314 * Start packing the mbufs in this chain into 2315 * the fragment pointers. Stop when we run out 2316 * of fragments or hit the end of the mbuf chain. 2317 */ 2318 for (i = 0; i < dmamap->dm_nsegs; i++) { 2319 if (frag > 383) 2320 CSR_WRITE_4(sc, TI_WINBASE, 2321 TI_TX_RING_BASE + 6144); 2322 else if (frag > 255) 2323 CSR_WRITE_4(sc, TI_WINBASE, 2324 TI_TX_RING_BASE + 4096); 2325 else if (frag > 127) 2326 CSR_WRITE_4(sc, TI_WINBASE, 2327 TI_TX_RING_BASE + 2048); 2328 else 2329 CSR_WRITE_4(sc, TI_WINBASE, 2330 TI_TX_RING_BASE); 2331 f = &sc->ti_tx_ring_nic[frag % 128]; 2332 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2333 break; 2334 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2335 f->ti_len = dmamap->dm_segs[i].ds_len; 2336 f->ti_flags = csum_flags; 2337 n = m_aux_find(m_head, AF_LINK, ETHERTYPE_VLAN); 2338 if (n) { 2339 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2340 f->ti_vlan_tag = *mtod(n, int *); 2341 } else { 2342 f->ti_vlan_tag = 0; 2343 } 2344 /* 2345 * Sanity check: avoid coming within 16 descriptors 2346 * of the end of the ring. 2347 */ 2348 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2349 return(ENOBUFS); 2350 cur = frag; 2351 TI_INC(frag, TI_TX_RING_CNT); 2352 cnt++; 2353 } 2354 2355 if (i < dmamap->dm_nsegs) 2356 return(ENOBUFS); 2357 2358 if (frag == sc->ti_tx_saved_considx) 2359 return(ENOBUFS); 2360 2361 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2362 TI_BDFLAG_END; 2363 2364 /* Sync the packet's DMA map. */ 2365 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2366 BUS_DMASYNC_PREWRITE); 2367 2368 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2369 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2370 sc->txdma[cur] = dma; 2371 sc->ti_txcnt += cnt; 2372 2373 *txidx = frag; 2374 2375 return(0); 2376 } 2377 2378 static int ti_encap_tigon2(sc, m_head, txidx) 2379 struct ti_softc *sc; 2380 struct mbuf *m_head; 2381 u_int32_t *txidx; 2382 { 2383 struct ti_tx_desc *f = NULL; 2384 u_int32_t frag, firstfrag, cur, cnt = 0; 2385 struct txdmamap_pool_entry *dma; 2386 bus_dmamap_t dmamap; 2387 int error, i; 2388 struct mbuf *n; 2389 u_int16_t csum_flags = 0; 2390 2391 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2392 if (dma == NULL) { 2393 return ENOMEM; 2394 } 2395 dmamap = dma->dmamap; 2396 2397 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2398 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2399 if (error) { 2400 struct mbuf *m; 2401 int i = 0; 2402 for (m = m_head; m; m = m->m_next) 2403 i++; 2404 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2405 "error %d\n", m_head->m_pkthdr.len, i, error); 2406 return (ENOMEM); 2407 } 2408 2409 cur = firstfrag = frag = *txidx; 2410 2411 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2412 /* IP header checksum field must be 0! */ 2413 csum_flags |= TI_BDFLAG_IP_CKSUM; 2414 } 2415 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2416 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2417 2418 /* XXX fragmented packet checksum capability? */ 2419 2420 /* 2421 * Start packing the mbufs in this chain into 2422 * the fragment pointers. Stop when we run out 2423 * of fragments or hit the end of the mbuf chain. 2424 */ 2425 for (i = 0; i < dmamap->dm_nsegs; i++) { 2426 f = &sc->ti_rdata->ti_tx_ring[frag]; 2427 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2428 break; 2429 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2430 f->ti_len = dmamap->dm_segs[i].ds_len; 2431 f->ti_flags = csum_flags; 2432 n = m_aux_find(m_head, AF_LINK, ETHERTYPE_VLAN); 2433 if (n) { 2434 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2435 f->ti_vlan_tag = *mtod(n, int *); 2436 } else { 2437 f->ti_vlan_tag = 0; 2438 } 2439 /* 2440 * Sanity check: avoid coming within 16 descriptors 2441 * of the end of the ring. 2442 */ 2443 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2444 return(ENOBUFS); 2445 cur = frag; 2446 TI_INC(frag, TI_TX_RING_CNT); 2447 cnt++; 2448 } 2449 2450 if (i < dmamap->dm_nsegs) 2451 return(ENOBUFS); 2452 2453 if (frag == sc->ti_tx_saved_considx) 2454 return(ENOBUFS); 2455 2456 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2457 2458 /* Sync the packet's DMA map. */ 2459 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2460 BUS_DMASYNC_PREWRITE); 2461 2462 /* Sync the descriptors we are using. */ 2463 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2464 2465 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2466 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2467 sc->txdma[cur] = dma; 2468 sc->ti_txcnt += cnt; 2469 2470 *txidx = frag; 2471 2472 return(0); 2473 } 2474 2475 /* 2476 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2477 * to the mbuf data regions directly in the transmit descriptors. 2478 */ 2479 static void ti_start(ifp) 2480 struct ifnet *ifp; 2481 { 2482 struct ti_softc *sc; 2483 struct mbuf *m_head = NULL; 2484 u_int32_t prodidx = 0; 2485 2486 sc = ifp->if_softc; 2487 2488 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2489 2490 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2491 IFQ_POLL(&ifp->if_snd, m_head); 2492 if (m_head == NULL) 2493 break; 2494 2495 /* 2496 * Pack the data into the transmit ring. If we 2497 * don't have room, set the OACTIVE flag and wait 2498 * for the NIC to drain the ring. 2499 */ 2500 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2501 ifp->if_flags |= IFF_OACTIVE; 2502 break; 2503 } 2504 2505 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2506 2507 /* 2508 * If there's a BPF listener, bounce a copy of this frame 2509 * to him. 2510 */ 2511 #if NBPFILTER > 0 2512 if (ifp->if_bpf) 2513 bpf_mtap(ifp->if_bpf, m_head); 2514 #endif 2515 } 2516 2517 /* Transmit */ 2518 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2519 2520 /* 2521 * Set a timeout in case the chip goes out to lunch. 2522 */ 2523 ifp->if_timer = 5; 2524 2525 return; 2526 } 2527 2528 static void ti_init(xsc) 2529 void *xsc; 2530 { 2531 struct ti_softc *sc = xsc; 2532 int s; 2533 2534 s = splnet(); 2535 2536 /* Cancel pending I/O and flush buffers. */ 2537 ti_stop(sc); 2538 2539 /* Init the gen info block, ring control blocks and firmware. */ 2540 if (ti_gibinit(sc)) { 2541 printf("%s: initialization failure\n", sc->sc_dev.dv_xname); 2542 splx(s); 2543 return; 2544 } 2545 2546 splx(s); 2547 2548 return; 2549 } 2550 2551 static void ti_init2(sc) 2552 struct ti_softc *sc; 2553 { 2554 struct ti_cmd_desc cmd; 2555 struct ifnet *ifp; 2556 u_int8_t *m; 2557 struct ifmedia *ifm; 2558 int tmp; 2559 2560 ifp = &sc->ethercom.ec_if; 2561 2562 /* Specify MTU and interface index. */ 2563 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->sc_dev.dv_unit); /* ??? */ 2564 2565 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2566 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2567 tmp += ETHER_VLAN_ENCAP_LEN; 2568 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2569 2570 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2571 2572 /* Load our MAC address. */ 2573 m = (u_int8_t *)LLADDR(ifp->if_sadl); 2574 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2575 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2576 | (m[4] << 8) | m[5]); 2577 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2578 2579 /* Enable or disable promiscuous mode as needed. */ 2580 if (ifp->if_flags & IFF_PROMISC) { 2581 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2582 } else { 2583 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2584 } 2585 2586 /* Program multicast filter. */ 2587 ti_setmulti(sc); 2588 2589 /* 2590 * If this is a Tigon 1, we should tell the 2591 * firmware to use software packet filtering. 2592 */ 2593 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2594 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2595 } 2596 2597 /* Init RX ring. */ 2598 ti_init_rx_ring_std(sc); 2599 2600 /* Init jumbo RX ring. */ 2601 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2602 ti_init_rx_ring_jumbo(sc); 2603 2604 /* 2605 * If this is a Tigon 2, we can also configure the 2606 * mini ring. 2607 */ 2608 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2609 ti_init_rx_ring_mini(sc); 2610 2611 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2612 sc->ti_rx_saved_considx = 0; 2613 2614 /* Init TX ring. */ 2615 ti_init_tx_ring(sc); 2616 2617 /* Tell firmware we're alive. */ 2618 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2619 2620 /* Enable host interrupts. */ 2621 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2622 2623 ifp->if_flags |= IFF_RUNNING; 2624 ifp->if_flags &= ~IFF_OACTIVE; 2625 2626 /* 2627 * Make sure to set media properly. We have to do this 2628 * here since we have to issue commands in order to set 2629 * the link negotiation and we can't issue commands until 2630 * the firmware is running. 2631 */ 2632 ifm = &sc->ifmedia; 2633 tmp = ifm->ifm_media; 2634 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2635 ti_ifmedia_upd(ifp); 2636 ifm->ifm_media = tmp; 2637 2638 return; 2639 } 2640 2641 /* 2642 * Set media options. 2643 */ 2644 static int ti_ifmedia_upd(ifp) 2645 struct ifnet *ifp; 2646 { 2647 struct ti_softc *sc; 2648 struct ifmedia *ifm; 2649 struct ti_cmd_desc cmd; 2650 2651 sc = ifp->if_softc; 2652 ifm = &sc->ifmedia; 2653 2654 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2655 return(EINVAL); 2656 2657 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2658 case IFM_AUTO: 2659 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2660 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2661 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2662 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2663 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2664 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2665 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2666 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2667 break; 2668 case IFM_1000_SX: 2669 case IFM_1000_T: 2670 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2671 CSR_WRITE_4(sc, TI_GCR_GLINK, 2672 TI_GLNK_PREF|TI_GLNK_1000MB|TI_GLNK_FULL_DUPLEX| 2673 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2674 } else { 2675 CSR_WRITE_4(sc, TI_GCR_GLINK, 2676 TI_GLNK_PREF|TI_GLNK_1000MB| 2677 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2678 } 2679 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2680 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2681 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2682 break; 2683 case IFM_100_FX: 2684 case IFM_10_FL: 2685 case IFM_100_TX: 2686 case IFM_10_T: 2687 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2688 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2689 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2690 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2691 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2692 } else { 2693 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2694 } 2695 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2696 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2697 } else { 2698 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2699 } 2700 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2701 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2702 break; 2703 } 2704 2705 sc->ethercom.ec_if.if_baudrate = 2706 ifmedia_baudrate(ifm->ifm_media); 2707 2708 return(0); 2709 } 2710 2711 /* 2712 * Report current media status. 2713 */ 2714 static void ti_ifmedia_sts(ifp, ifmr) 2715 struct ifnet *ifp; 2716 struct ifmediareq *ifmr; 2717 { 2718 struct ti_softc *sc; 2719 u_int32_t media = 0; 2720 2721 sc = ifp->if_softc; 2722 2723 ifmr->ifm_status = IFM_AVALID; 2724 ifmr->ifm_active = IFM_ETHER; 2725 2726 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2727 return; 2728 2729 ifmr->ifm_status |= IFM_ACTIVE; 2730 2731 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2732 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2733 if (sc->ti_copper) 2734 ifmr->ifm_active |= IFM_1000_T; 2735 else 2736 ifmr->ifm_active |= IFM_1000_SX; 2737 if (media & TI_GLNK_FULL_DUPLEX) 2738 ifmr->ifm_active |= IFM_FDX; 2739 else 2740 ifmr->ifm_active |= IFM_HDX; 2741 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2742 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2743 if (sc->ti_copper) { 2744 if (media & TI_LNK_100MB) 2745 ifmr->ifm_active |= IFM_100_TX; 2746 if (media & TI_LNK_10MB) 2747 ifmr->ifm_active |= IFM_10_T; 2748 } else { 2749 if (media & TI_LNK_100MB) 2750 ifmr->ifm_active |= IFM_100_FX; 2751 if (media & TI_LNK_10MB) 2752 ifmr->ifm_active |= IFM_10_FL; 2753 } 2754 if (media & TI_LNK_FULL_DUPLEX) 2755 ifmr->ifm_active |= IFM_FDX; 2756 if (media & TI_LNK_HALF_DUPLEX) 2757 ifmr->ifm_active |= IFM_HDX; 2758 } 2759 2760 sc->ethercom.ec_if.if_baudrate = 2761 ifmedia_baudrate(sc->ifmedia.ifm_media); 2762 2763 return; 2764 } 2765 2766 static int 2767 ti_ether_ioctl(ifp, cmd, data) 2768 struct ifnet *ifp; 2769 u_long cmd; 2770 caddr_t data; 2771 { 2772 struct ifaddr *ifa = (struct ifaddr *) data; 2773 struct ti_softc *sc = ifp->if_softc; 2774 2775 if ((ifp->if_flags & IFF_UP) == 0) { 2776 ifp->if_flags |= IFF_UP; 2777 ti_init(sc); 2778 } 2779 2780 switch (cmd) { 2781 case SIOCSIFADDR: 2782 2783 switch (ifa->ifa_addr->sa_family) { 2784 #ifdef INET 2785 case AF_INET: 2786 arp_ifinit(ifp, ifa); 2787 break; 2788 #endif 2789 #ifdef NS 2790 case AF_NS: 2791 { 2792 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 2793 2794 if (ns_nullhost(*ina)) 2795 ina->x_host = *(union ns_host *) 2796 LLADDR(ifp->if_sadl); 2797 else 2798 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 2799 ifp->if_addrlen); 2800 break; 2801 } 2802 #endif 2803 default: 2804 break; 2805 } 2806 break; 2807 2808 default: 2809 return (EINVAL); 2810 } 2811 2812 return (0); 2813 } 2814 2815 static int ti_ioctl(ifp, command, data) 2816 struct ifnet *ifp; 2817 u_long command; 2818 caddr_t data; 2819 { 2820 struct ti_softc *sc = ifp->if_softc; 2821 struct ifreq *ifr = (struct ifreq *) data; 2822 int s, error = 0; 2823 struct ti_cmd_desc cmd; 2824 2825 s = splnet(); 2826 2827 switch(command) { 2828 case SIOCSIFADDR: 2829 case SIOCGIFADDR: 2830 error = ti_ether_ioctl(ifp, command, data); 2831 break; 2832 case SIOCSIFMTU: 2833 if (ifr->ifr_mtu > ETHERMTU_JUMBO) 2834 error = EINVAL; 2835 else { 2836 ifp->if_mtu = ifr->ifr_mtu; 2837 ti_init(sc); 2838 } 2839 break; 2840 case SIOCSIFFLAGS: 2841 if (ifp->if_flags & IFF_UP) { 2842 /* 2843 * If only the state of the PROMISC flag changed, 2844 * then just use the 'set promisc mode' command 2845 * instead of reinitializing the entire NIC. Doing 2846 * a full re-init means reloading the firmware and 2847 * waiting for it to start up, which may take a 2848 * second or two. 2849 */ 2850 if (ifp->if_flags & IFF_RUNNING && 2851 ifp->if_flags & IFF_PROMISC && 2852 !(sc->ti_if_flags & IFF_PROMISC)) { 2853 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2854 TI_CMD_CODE_PROMISC_ENB, 0); 2855 } else if (ifp->if_flags & IFF_RUNNING && 2856 !(ifp->if_flags & IFF_PROMISC) && 2857 sc->ti_if_flags & IFF_PROMISC) { 2858 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2859 TI_CMD_CODE_PROMISC_DIS, 0); 2860 } else 2861 ti_init(sc); 2862 } else { 2863 if (ifp->if_flags & IFF_RUNNING) { 2864 ti_stop(sc); 2865 } 2866 } 2867 sc->ti_if_flags = ifp->if_flags; 2868 error = 0; 2869 break; 2870 case SIOCADDMULTI: 2871 case SIOCDELMULTI: 2872 error = (command == SIOCADDMULTI) ? 2873 ether_addmulti(ifr, &sc->ethercom) : 2874 ether_delmulti(ifr, &sc->ethercom); 2875 if (error == ENETRESET) { 2876 if (ifp->if_flags & IFF_RUNNING) 2877 ti_setmulti(sc); 2878 error = 0; 2879 } 2880 break; 2881 case SIOCSIFMEDIA: 2882 case SIOCGIFMEDIA: 2883 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2884 break; 2885 default: 2886 error = EINVAL; 2887 break; 2888 } 2889 2890 (void)splx(s); 2891 2892 return(error); 2893 } 2894 2895 static void ti_watchdog(ifp) 2896 struct ifnet *ifp; 2897 { 2898 struct ti_softc *sc; 2899 2900 sc = ifp->if_softc; 2901 2902 printf("%s: watchdog timeout -- resetting\n", sc->sc_dev.dv_xname); 2903 ti_stop(sc); 2904 ti_init(sc); 2905 2906 ifp->if_oerrors++; 2907 2908 return; 2909 } 2910 2911 /* 2912 * Stop the adapter and free any mbufs allocated to the 2913 * RX and TX lists. 2914 */ 2915 static void ti_stop(sc) 2916 struct ti_softc *sc; 2917 { 2918 struct ifnet *ifp; 2919 struct ti_cmd_desc cmd; 2920 2921 ifp = &sc->ethercom.ec_if; 2922 2923 /* Disable host interrupts. */ 2924 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2925 /* 2926 * Tell firmware we're shutting down. 2927 */ 2928 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2929 2930 /* Halt and reinitialize. */ 2931 ti_chipinit(sc); 2932 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2933 ti_chipinit(sc); 2934 2935 /* Free the RX lists. */ 2936 ti_free_rx_ring_std(sc); 2937 2938 /* Free jumbo RX list. */ 2939 ti_free_rx_ring_jumbo(sc); 2940 2941 /* Free mini RX list. */ 2942 ti_free_rx_ring_mini(sc); 2943 2944 /* Free TX buffers. */ 2945 ti_free_tx_ring(sc); 2946 2947 sc->ti_ev_prodidx.ti_idx = 0; 2948 sc->ti_return_prodidx.ti_idx = 0; 2949 sc->ti_tx_considx.ti_idx = 0; 2950 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2951 2952 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2953 2954 return; 2955 } 2956 2957 /* 2958 * Stop all chip I/O so that the kernel's probe routines don't 2959 * get confused by errant DMAs when rebooting. 2960 */ 2961 static void ti_shutdown(v) 2962 void *v; 2963 { 2964 struct ti_softc *sc = v; 2965 2966 ti_chipinit(sc); 2967 2968 return; 2969 } 2970
Indexes created Fri Sep 26 20:09:58 GMT 2025