if_ti.c revision 1.53
1 /* $NetBSD: if_ti.c,v 1.53 2003/01/17 08:11:51 itojun Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.53 2003/01/17 08:11:51 itojun Exp $"); 85 86 #include "bpfilter.h" 87 #include "opt_inet.h" 88 #include "opt_ns.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/queue.h> 98 #include <sys/device.h> 99 #include <sys/reboot.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #ifdef INET 114 #include <netinet/in.h> 115 #include <netinet/if_inarp.h> 116 #include <netinet/in_systm.h> 117 #include <netinet/ip.h> 118 #endif 119 120 #ifdef NS 121 #include <netns/ns.h> 122 #include <netns/ns_if.h> 123 #endif 124 125 #include <machine/bus.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/pcidevs.h> 130 131 #include <dev/pci/if_tireg.h> 132 133 #include <dev/microcode/tigon/ti_fw.h> 134 #include <dev/microcode/tigon/ti_fw2.h> 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 140 static const struct ti_type ti_devs[] = { 141 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 142 "Alteon AceNIC 1000BASE-SX Ethernet" }, 143 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 144 "Alteon AceNIC 1000BASE-T Ethernet" }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 146 "3Com 3c985-SX Gigabit Ethernet" }, 147 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 148 "Netgear GA620 1000BASE-SX Ethernet" }, 149 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 150 "Netgear GA620 1000BASE-T Ethernet" }, 151 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 152 "Silicon Graphics Gigabit Ethernet" }, 153 { 0, 0, NULL } 154 }; 155 156 static const struct ti_type *ti_type_match __P((struct pci_attach_args *)); 157 static int ti_probe __P((struct device *, struct cfdata *, void *)); 158 static void ti_attach __P((struct device *, struct device *, void *)); 159 static void ti_shutdown __P((void *)); 160 static void ti_txeof_tigon1 __P((struct ti_softc *)); 161 static void ti_txeof_tigon2 __P((struct ti_softc *)); 162 static void ti_rxeof __P((struct ti_softc *)); 163 164 static void ti_stats_update __P((struct ti_softc *)); 165 static int ti_encap_tigon1 __P((struct ti_softc *, struct mbuf *, 166 u_int32_t *)); 167 static int ti_encap_tigon2 __P((struct ti_softc *, struct mbuf *, 168 u_int32_t *)); 169 170 static int ti_intr __P((void *)); 171 static void ti_start __P((struct ifnet *)); 172 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 173 static void ti_init __P((void *)); 174 static void ti_init2 __P((struct ti_softc *)); 175 static void ti_stop __P((struct ti_softc *)); 176 static void ti_watchdog __P((struct ifnet *)); 177 static int ti_ifmedia_upd __P((struct ifnet *)); 178 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 179 180 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 181 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 182 int, u_int8_t *)); 183 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 184 185 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 186 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 187 static void ti_setmulti __P((struct ti_softc *)); 188 189 static void ti_mem __P((struct ti_softc *, u_int32_t, 190 u_int32_t, caddr_t)); 191 static void ti_loadfw __P((struct ti_softc *)); 192 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 193 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 194 caddr_t, int)); 195 static void ti_handle_events __P((struct ti_softc *)); 196 static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 197 static void *ti_jalloc __P((struct ti_softc *)); 198 static void ti_jfree __P((struct mbuf *, caddr_t, u_int, void *)); 199 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 200 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 201 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 202 static int ti_init_rx_ring_std __P((struct ti_softc *)); 203 static void ti_free_rx_ring_std __P((struct ti_softc *)); 204 static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 205 static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 206 static int ti_init_rx_ring_mini __P((struct ti_softc *)); 207 static void ti_free_rx_ring_mini __P((struct ti_softc *)); 208 static void ti_free_tx_ring __P((struct ti_softc *)); 209 static int ti_init_tx_ring __P((struct ti_softc *)); 210 211 static int ti_64bitslot_war __P((struct ti_softc *)); 212 static int ti_chipinit __P((struct ti_softc *)); 213 static int ti_gibinit __P((struct ti_softc *)); 214 215 static int ti_ether_ioctl __P((struct ifnet *, u_long, caddr_t)); 216 217 CFATTACH_DECL(ti, sizeof(struct ti_softc), 218 ti_probe, ti_attach, NULL, NULL); 219 220 /* 221 * Send an instruction or address to the EEPROM, check for ACK. 222 */ 223 static u_int32_t ti_eeprom_putbyte(sc, byte) 224 struct ti_softc *sc; 225 int byte; 226 { 227 int i, ack = 0; 228 229 /* 230 * Make sure we're in TX mode. 231 */ 232 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 233 234 /* 235 * Feed in each bit and stobe the clock. 236 */ 237 for (i = 0x80; i; i >>= 1) { 238 if (byte & i) { 239 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 240 } else { 241 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 242 } 243 DELAY(1); 244 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 245 DELAY(1); 246 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 247 } 248 249 /* 250 * Turn off TX mode. 251 */ 252 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 253 254 /* 255 * Check for ack. 256 */ 257 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 258 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 259 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 260 261 return(ack); 262 } 263 264 /* 265 * Read a byte of data stored in the EEPROM at address 'addr.' 266 * We have to send two address bytes since the EEPROM can hold 267 * more than 256 bytes of data. 268 */ 269 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 270 struct ti_softc *sc; 271 int addr; 272 u_int8_t *dest; 273 { 274 int i; 275 u_int8_t byte = 0; 276 277 EEPROM_START; 278 279 /* 280 * Send write control code to EEPROM. 281 */ 282 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 283 printf("%s: failed to send write command, status: %x\n", 284 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 285 return(1); 286 } 287 288 /* 289 * Send first byte of address of byte we want to read. 290 */ 291 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 292 printf("%s: failed to send address, status: %x\n", 293 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 294 return(1); 295 } 296 /* 297 * Send second byte address of byte we want to read. 298 */ 299 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 300 printf("%s: failed to send address, status: %x\n", 301 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 302 return(1); 303 } 304 305 EEPROM_STOP; 306 EEPROM_START; 307 /* 308 * Send read control code to EEPROM. 309 */ 310 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 311 printf("%s: failed to send read command, status: %x\n", 312 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 313 return(1); 314 } 315 316 /* 317 * Start reading bits from EEPROM. 318 */ 319 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 320 for (i = 0x80; i; i >>= 1) { 321 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 322 DELAY(1); 323 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 324 byte |= i; 325 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 326 DELAY(1); 327 } 328 329 EEPROM_STOP; 330 331 /* 332 * No ACK generated for read, so just return byte. 333 */ 334 335 *dest = byte; 336 337 return(0); 338 } 339 340 /* 341 * Read a sequence of bytes from the EEPROM. 342 */ 343 static int ti_read_eeprom(sc, dest, off, cnt) 344 struct ti_softc *sc; 345 caddr_t dest; 346 int off; 347 int cnt; 348 { 349 int err = 0, i; 350 u_int8_t byte = 0; 351 352 for (i = 0; i < cnt; i++) { 353 err = ti_eeprom_getbyte(sc, off + i, &byte); 354 if (err) 355 break; 356 *(dest + i) = byte; 357 } 358 359 return(err ? 1 : 0); 360 } 361 362 /* 363 * NIC memory access function. Can be used to either clear a section 364 * of NIC local memory or (if buf is non-NULL) copy data into it. 365 */ 366 static void ti_mem(sc, addr, len, buf) 367 struct ti_softc *sc; 368 u_int32_t addr, len; 369 caddr_t buf; 370 { 371 int segptr, segsize, cnt; 372 caddr_t ptr; 373 374 segptr = addr; 375 cnt = len; 376 ptr = buf; 377 378 while(cnt) { 379 if (cnt < TI_WINLEN) 380 segsize = cnt; 381 else 382 segsize = TI_WINLEN - (segptr % TI_WINLEN); 383 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 384 if (buf == NULL) { 385 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 386 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 387 segsize / 4); 388 } else { 389 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 390 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 391 (u_int32_t *)ptr, segsize / 4); 392 ptr += segsize; 393 } 394 segptr += segsize; 395 cnt -= segsize; 396 } 397 398 return; 399 } 400 401 /* 402 * Load firmware image into the NIC. Check that the firmware revision 403 * is acceptable and see if we want the firmware for the Tigon 1 or 404 * Tigon 2. 405 */ 406 static void ti_loadfw(sc) 407 struct ti_softc *sc; 408 { 409 switch(sc->ti_hwrev) { 410 case TI_HWREV_TIGON: 411 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 412 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 413 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 414 printf("%s: firmware revision mismatch; want " 415 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 416 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 417 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 418 tigonFwReleaseMinor, tigonFwReleaseFix); 419 return; 420 } 421 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 422 (caddr_t)tigonFwText); 423 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 424 (caddr_t)tigonFwData); 425 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 426 (caddr_t)tigonFwRodata); 427 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 428 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 429 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 430 break; 431 case TI_HWREV_TIGON_II: 432 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 433 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 434 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 435 printf("%s: firmware revision mismatch; want " 436 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 437 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 438 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 439 tigon2FwReleaseMinor, tigon2FwReleaseFix); 440 return; 441 } 442 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 443 (caddr_t)tigon2FwText); 444 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 445 (caddr_t)tigon2FwData); 446 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 447 (caddr_t)tigon2FwRodata); 448 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 449 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 450 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 451 break; 452 default: 453 printf("%s: can't load firmware: unknown hardware rev\n", 454 sc->sc_dev.dv_xname); 455 break; 456 } 457 458 return; 459 } 460 461 /* 462 * Send the NIC a command via the command ring. 463 */ 464 static void ti_cmd(sc, cmd) 465 struct ti_softc *sc; 466 struct ti_cmd_desc *cmd; 467 { 468 u_int32_t index; 469 470 index = sc->ti_cmd_saved_prodidx; 471 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 472 TI_INC(index, TI_CMD_RING_CNT); 473 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 474 sc->ti_cmd_saved_prodidx = index; 475 476 return; 477 } 478 479 /* 480 * Send the NIC an extended command. The 'len' parameter specifies the 481 * number of command slots to include after the initial command. 482 */ 483 static void ti_cmd_ext(sc, cmd, arg, len) 484 struct ti_softc *sc; 485 struct ti_cmd_desc *cmd; 486 caddr_t arg; 487 int len; 488 { 489 u_int32_t index; 490 int i; 491 492 index = sc->ti_cmd_saved_prodidx; 493 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 494 TI_INC(index, TI_CMD_RING_CNT); 495 for (i = 0; i < len; i++) { 496 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 497 *(u_int32_t *)(&arg[i * 4])); 498 TI_INC(index, TI_CMD_RING_CNT); 499 } 500 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 501 sc->ti_cmd_saved_prodidx = index; 502 503 return; 504 } 505 506 /* 507 * Handle events that have triggered interrupts. 508 */ 509 static void ti_handle_events(sc) 510 struct ti_softc *sc; 511 { 512 struct ti_event_desc *e; 513 514 if (sc->ti_rdata->ti_event_ring == NULL) 515 return; 516 517 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 518 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 519 switch(e->ti_event) { 520 case TI_EV_LINKSTAT_CHANGED: 521 sc->ti_linkstat = e->ti_code; 522 if (e->ti_code == TI_EV_CODE_LINK_UP) 523 printf("%s: 10/100 link up\n", 524 sc->sc_dev.dv_xname); 525 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 526 printf("%s: gigabit link up\n", 527 sc->sc_dev.dv_xname); 528 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 529 printf("%s: link down\n", 530 sc->sc_dev.dv_xname); 531 break; 532 case TI_EV_ERROR: 533 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 534 printf("%s: invalid command\n", 535 sc->sc_dev.dv_xname); 536 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 537 printf("%s: unknown command\n", 538 sc->sc_dev.dv_xname); 539 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 540 printf("%s: bad config data\n", 541 sc->sc_dev.dv_xname); 542 break; 543 case TI_EV_FIRMWARE_UP: 544 ti_init2(sc); 545 break; 546 case TI_EV_STATS_UPDATED: 547 ti_stats_update(sc); 548 break; 549 case TI_EV_RESET_JUMBO_RING: 550 case TI_EV_MCAST_UPDATED: 551 /* Who cares. */ 552 break; 553 default: 554 printf("%s: unknown event: %d\n", 555 sc->sc_dev.dv_xname, e->ti_event); 556 break; 557 } 558 /* Advance the consumer index. */ 559 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 560 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 561 } 562 563 return; 564 } 565 566 /* 567 * Memory management for the jumbo receive ring is a pain in the 568 * butt. We need to allocate at least 9018 bytes of space per frame, 569 * _and_ it has to be contiguous (unless you use the extended 570 * jumbo descriptor format). Using malloc() all the time won't 571 * work: malloc() allocates memory in powers of two, which means we 572 * would end up wasting a considerable amount of space by allocating 573 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 574 * to do our own memory management. 575 * 576 * The driver needs to allocate a contiguous chunk of memory at boot 577 * time. We then chop this up ourselves into 9K pieces and use them 578 * as external mbuf storage. 579 * 580 * One issue here is how much memory to allocate. The jumbo ring has 581 * 256 slots in it, but at 9K per slot than can consume over 2MB of 582 * RAM. This is a bit much, especially considering we also need 583 * RAM for the standard ring and mini ring (on the Tigon 2). To 584 * save space, we only actually allocate enough memory for 64 slots 585 * by default, which works out to between 500 and 600K. This can 586 * be tuned by changing a #define in if_tireg.h. 587 */ 588 589 static int ti_alloc_jumbo_mem(sc) 590 struct ti_softc *sc; 591 { 592 caddr_t ptr; 593 int i; 594 struct ti_jpool_entry *entry; 595 bus_dma_segment_t dmaseg; 596 int error, dmanseg; 597 598 /* Grab a big chunk o' storage. */ 599 if ((error = bus_dmamem_alloc(sc->sc_dmat, 600 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 601 BUS_DMA_NOWAIT)) != 0) { 602 printf("%s: can't allocate jumbo buffer, error = %d\n", 603 sc->sc_dev.dv_xname, error); 604 return (error); 605 } 606 607 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 608 TI_JMEM, (caddr_t *)&sc->ti_cdata.ti_jumbo_buf, 609 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 610 printf("%s: can't map jumbo buffer, error = %d\n", 611 sc->sc_dev.dv_xname, error); 612 return (error); 613 } 614 615 if ((error = bus_dmamap_create(sc->sc_dmat, 616 TI_JMEM, 1, 617 TI_JMEM, 0, BUS_DMA_NOWAIT, 618 &sc->jumbo_dmamap)) != 0) { 619 printf("%s: can't create jumbo buffer DMA map, error = %d\n", 620 sc->sc_dev.dv_xname, error); 621 return (error); 622 } 623 624 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 625 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 626 BUS_DMA_NOWAIT)) != 0) { 627 printf("%s: can't load jumbo buffer DMA map, error = %d\n", 628 sc->sc_dev.dv_xname, error); 629 return (error); 630 } 631 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 632 633 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 634 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 635 636 /* 637 * Now divide it up into 9K pieces and save the addresses 638 * in an array. 639 */ 640 ptr = sc->ti_cdata.ti_jumbo_buf; 641 for (i = 0; i < TI_JSLOTS; i++) { 642 sc->ti_cdata.ti_jslots[i] = ptr; 643 ptr += TI_JLEN; 644 entry = malloc(sizeof(struct ti_jpool_entry), 645 M_DEVBUF, M_NOWAIT); 646 if (entry == NULL) { 647 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 648 sc->ti_cdata.ti_jumbo_buf = NULL; 649 printf("%s: no memory for jumbo " 650 "buffer queue!\n", sc->sc_dev.dv_xname); 651 return(ENOBUFS); 652 } 653 entry->slot = i; 654 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 655 jpool_entries); 656 } 657 658 return(0); 659 } 660 661 /* 662 * Allocate a jumbo buffer. 663 */ 664 static void *ti_jalloc(sc) 665 struct ti_softc *sc; 666 { 667 struct ti_jpool_entry *entry; 668 669 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 670 671 if (entry == NULL) { 672 printf("%s: no free jumbo buffers\n", sc->sc_dev.dv_xname); 673 return(NULL); 674 } 675 676 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 677 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 678 return(sc->ti_cdata.ti_jslots[entry->slot]); 679 } 680 681 /* 682 * Release a jumbo buffer. 683 */ 684 static void ti_jfree(m, buf, size, arg) 685 struct mbuf *m; 686 caddr_t buf; 687 u_int size; 688 void *arg; 689 { 690 struct ti_softc *sc; 691 int i, s; 692 struct ti_jpool_entry *entry; 693 694 /* Extract the softc struct pointer. */ 695 sc = (struct ti_softc *)arg; 696 697 if (sc == NULL) 698 panic("ti_jfree: didn't get softc pointer!"); 699 700 /* calculate the slot this buffer belongs to */ 701 702 i = ((caddr_t)buf 703 - (caddr_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 704 705 if ((i < 0) || (i >= TI_JSLOTS)) 706 panic("ti_jfree: asked to free buffer that we don't manage!"); 707 708 s = splvm(); 709 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 710 if (entry == NULL) 711 panic("ti_jfree: buffer not in use!"); 712 entry->slot = i; 713 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 714 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 715 716 if (__predict_true(m != NULL)) 717 pool_cache_put(&mbpool_cache, m); 718 splx(s); 719 } 720 721 722 /* 723 * Intialize a standard receive ring descriptor. 724 */ 725 static int ti_newbuf_std(sc, i, m, dmamap) 726 struct ti_softc *sc; 727 int i; 728 struct mbuf *m; 729 bus_dmamap_t dmamap; /* required if (m != NULL) */ 730 { 731 struct mbuf *m_new = NULL; 732 struct ti_rx_desc *r; 733 int error; 734 735 if (dmamap == NULL) { 736 /* if (m) panic() */ 737 738 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 739 MCLBYTES, 0, BUS_DMA_NOWAIT, 740 &dmamap)) != 0) { 741 printf("%s: can't create recv map, error = %d\n", 742 sc->sc_dev.dv_xname, error); 743 return(ENOMEM); 744 } 745 } 746 sc->std_dmamap[i] = dmamap; 747 748 if (m == NULL) { 749 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 750 if (m_new == NULL) { 751 printf("%s: mbuf allocation failed " 752 "-- packet dropped!\n", sc->sc_dev.dv_xname); 753 return(ENOBUFS); 754 } 755 756 MCLGET(m_new, M_DONTWAIT); 757 if (!(m_new->m_flags & M_EXT)) { 758 printf("%s: cluster allocation failed " 759 "-- packet dropped!\n", sc->sc_dev.dv_xname); 760 m_freem(m_new); 761 return(ENOBUFS); 762 } 763 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 764 m_adj(m_new, ETHER_ALIGN); 765 766 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 767 mtod(m_new, caddr_t), m_new->m_len, NULL, 768 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 769 printf("%s: can't load recv map, error = %d\n", 770 sc->sc_dev.dv_xname, error); 771 return (ENOMEM); 772 } 773 } else { 774 m_new = m; 775 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 776 m_new->m_data = m_new->m_ext.ext_buf; 777 m_adj(m_new, ETHER_ALIGN); 778 779 /* reuse the dmamap */ 780 } 781 782 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 783 r = &sc->ti_rdata->ti_rx_std_ring[i]; 784 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 785 r->ti_type = TI_BDTYPE_RECV_BD; 786 r->ti_flags = 0; 787 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 788 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 789 if (sc->ethercom.ec_if.if_capenable & 790 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 791 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 792 r->ti_len = m_new->m_len; /* == ds_len */ 793 r->ti_idx = i; 794 795 return(0); 796 } 797 798 /* 799 * Intialize a mini receive ring descriptor. This only applies to 800 * the Tigon 2. 801 */ 802 static int ti_newbuf_mini(sc, i, m, dmamap) 803 struct ti_softc *sc; 804 int i; 805 struct mbuf *m; 806 bus_dmamap_t dmamap; /* required if (m != NULL) */ 807 { 808 struct mbuf *m_new = NULL; 809 struct ti_rx_desc *r; 810 int error; 811 812 if (dmamap == NULL) { 813 /* if (m) panic() */ 814 815 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 816 MHLEN, 0, BUS_DMA_NOWAIT, 817 &dmamap)) != 0) { 818 printf("%s: can't create recv map, error = %d\n", 819 sc->sc_dev.dv_xname, error); 820 return(ENOMEM); 821 } 822 } 823 sc->mini_dmamap[i] = dmamap; 824 825 if (m == NULL) { 826 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 827 if (m_new == NULL) { 828 printf("%s: mbuf allocation failed " 829 "-- packet dropped!\n", sc->sc_dev.dv_xname); 830 return(ENOBUFS); 831 } 832 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 833 m_adj(m_new, ETHER_ALIGN); 834 835 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 836 mtod(m_new, caddr_t), m_new->m_len, NULL, 837 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 838 printf("%s: can't load recv map, error = %d\n", 839 sc->sc_dev.dv_xname, error); 840 return (ENOMEM); 841 } 842 } else { 843 m_new = m; 844 m_new->m_data = m_new->m_pktdat; 845 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 846 m_adj(m_new, ETHER_ALIGN); 847 848 /* reuse the dmamap */ 849 } 850 851 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 852 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 853 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 854 r->ti_type = TI_BDTYPE_RECV_BD; 855 r->ti_flags = TI_BDFLAG_MINI_RING; 856 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 857 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 858 if (sc->ethercom.ec_if.if_capenable & 859 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 860 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 861 r->ti_len = m_new->m_len; /* == ds_len */ 862 r->ti_idx = i; 863 864 return(0); 865 } 866 867 /* 868 * Initialize a jumbo receive ring descriptor. This allocates 869 * a jumbo buffer from the pool managed internally by the driver. 870 */ 871 static int ti_newbuf_jumbo(sc, i, m) 872 struct ti_softc *sc; 873 int i; 874 struct mbuf *m; 875 { 876 struct mbuf *m_new = NULL; 877 struct ti_rx_desc *r; 878 879 if (m == NULL) { 880 caddr_t *buf = NULL; 881 882 /* Allocate the mbuf. */ 883 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 884 if (m_new == NULL) { 885 printf("%s: mbuf allocation failed " 886 "-- packet dropped!\n", sc->sc_dev.dv_xname); 887 return(ENOBUFS); 888 } 889 890 /* Allocate the jumbo buffer */ 891 buf = ti_jalloc(sc); 892 if (buf == NULL) { 893 m_freem(m_new); 894 printf("%s: jumbo allocation failed " 895 "-- packet dropped!\n", sc->sc_dev.dv_xname); 896 return(ENOBUFS); 897 } 898 899 /* Attach the buffer to the mbuf. */ 900 MEXTADD(m_new, (void *)buf, ETHER_MAX_LEN_JUMBO, 901 M_DEVBUF, ti_jfree, sc); 902 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 903 } else { 904 m_new = m; 905 m_new->m_data = m_new->m_ext.ext_buf; 906 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 907 } 908 909 m_adj(m_new, ETHER_ALIGN); 910 /* Set up the descriptor. */ 911 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 912 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 913 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 914 ((caddr_t)mtod(m_new, caddr_t) 915 - (caddr_t)sc->ti_cdata.ti_jumbo_buf); 916 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 917 r->ti_flags = TI_BDFLAG_JUMBO_RING; 918 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 919 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 920 if (sc->ethercom.ec_if.if_capenable & 921 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 922 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 923 r->ti_len = m_new->m_len; 924 r->ti_idx = i; 925 926 return(0); 927 } 928 929 /* 930 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 931 * that's 1MB or memory, which is a lot. For now, we fill only the first 932 * 256 ring entries and hope that our CPU is fast enough to keep up with 933 * the NIC. 934 */ 935 static int ti_init_rx_ring_std(sc) 936 struct ti_softc *sc; 937 { 938 int i; 939 struct ti_cmd_desc cmd; 940 941 for (i = 0; i < TI_SSLOTS; i++) { 942 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 943 return(ENOBUFS); 944 }; 945 946 TI_UPDATE_STDPROD(sc, i - 1); 947 sc->ti_std = i - 1; 948 949 return(0); 950 } 951 952 static void ti_free_rx_ring_std(sc) 953 struct ti_softc *sc; 954 { 955 int i; 956 957 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 958 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 959 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 960 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 961 962 /* if (sc->std_dmamap[i] == 0) panic() */ 963 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 964 sc->std_dmamap[i] = 0; 965 } 966 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 967 sizeof(struct ti_rx_desc)); 968 } 969 970 return; 971 } 972 973 static int ti_init_rx_ring_jumbo(sc) 974 struct ti_softc *sc; 975 { 976 int i; 977 struct ti_cmd_desc cmd; 978 979 for (i = 0; i < (TI_JSLOTS - 20); i++) { 980 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 981 return(ENOBUFS); 982 }; 983 984 TI_UPDATE_JUMBOPROD(sc, i - 1); 985 sc->ti_jumbo = i - 1; 986 987 return(0); 988 } 989 990 static void ti_free_rx_ring_jumbo(sc) 991 struct ti_softc *sc; 992 { 993 int i; 994 995 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 996 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 997 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 998 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 999 } 1000 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 1001 sizeof(struct ti_rx_desc)); 1002 } 1003 1004 return; 1005 } 1006 1007 static int ti_init_rx_ring_mini(sc) 1008 struct ti_softc *sc; 1009 { 1010 int i; 1011 1012 for (i = 0; i < TI_MSLOTS; i++) { 1013 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 1014 return(ENOBUFS); 1015 }; 1016 1017 TI_UPDATE_MINIPROD(sc, i - 1); 1018 sc->ti_mini = i - 1; 1019 1020 return(0); 1021 } 1022 1023 static void ti_free_rx_ring_mini(sc) 1024 struct ti_softc *sc; 1025 { 1026 int i; 1027 1028 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1029 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1030 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1031 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1032 1033 /* if (sc->mini_dmamap[i] == 0) panic() */ 1034 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1035 sc->mini_dmamap[i] = 0; 1036 } 1037 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1038 sizeof(struct ti_rx_desc)); 1039 } 1040 1041 return; 1042 } 1043 1044 static void ti_free_tx_ring(sc) 1045 struct ti_softc *sc; 1046 { 1047 int i; 1048 struct txdmamap_pool_entry *dma; 1049 1050 if (sc->ti_rdata->ti_tx_ring == NULL) 1051 return; 1052 1053 for (i = 0; i < TI_TX_RING_CNT; i++) { 1054 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1055 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1056 sc->ti_cdata.ti_tx_chain[i] = NULL; 1057 1058 /* if (sc->txdma[i] == 0) panic() */ 1059 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1060 link); 1061 sc->txdma[i] = 0; 1062 } 1063 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1064 sizeof(struct ti_tx_desc)); 1065 } 1066 1067 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1068 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1069 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1070 free(dma, M_DEVBUF); 1071 } 1072 1073 return; 1074 } 1075 1076 static int ti_init_tx_ring(sc) 1077 struct ti_softc *sc; 1078 { 1079 int i, error; 1080 bus_dmamap_t dmamap; 1081 struct txdmamap_pool_entry *dma; 1082 1083 sc->ti_txcnt = 0; 1084 sc->ti_tx_saved_considx = 0; 1085 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1086 1087 SIMPLEQ_INIT(&sc->txdma_list); 1088 for (i = 0; i < TI_RSLOTS; i++) { 1089 /* I've seen mbufs with 30 fragments. */ 1090 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 1091 40, ETHER_MAX_LEN_JUMBO, 0, 1092 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1093 printf("%s: can't create tx map, error = %d\n", 1094 sc->sc_dev.dv_xname, error); 1095 return(ENOMEM); 1096 } 1097 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1098 if (!dma) { 1099 printf("%s: can't alloc txdmamap_pool_entry\n", 1100 sc->sc_dev.dv_xname); 1101 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1102 return (ENOMEM); 1103 } 1104 dma->dmamap = dmamap; 1105 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1106 } 1107 1108 return(0); 1109 } 1110 1111 /* 1112 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1113 * but we have to support the old way too so that Tigon 1 cards will 1114 * work. 1115 */ 1116 void ti_add_mcast(sc, addr) 1117 struct ti_softc *sc; 1118 struct ether_addr *addr; 1119 { 1120 struct ti_cmd_desc cmd; 1121 u_int16_t *m; 1122 u_int32_t ext[2] = {0, 0}; 1123 1124 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1125 1126 switch(sc->ti_hwrev) { 1127 case TI_HWREV_TIGON: 1128 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1129 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1130 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1131 break; 1132 case TI_HWREV_TIGON_II: 1133 ext[0] = htons(m[0]); 1134 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1135 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1136 break; 1137 default: 1138 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1139 break; 1140 } 1141 1142 return; 1143 } 1144 1145 void ti_del_mcast(sc, addr) 1146 struct ti_softc *sc; 1147 struct ether_addr *addr; 1148 { 1149 struct ti_cmd_desc cmd; 1150 u_int16_t *m; 1151 u_int32_t ext[2] = {0, 0}; 1152 1153 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1154 1155 switch(sc->ti_hwrev) { 1156 case TI_HWREV_TIGON: 1157 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1158 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1159 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1160 break; 1161 case TI_HWREV_TIGON_II: 1162 ext[0] = htons(m[0]); 1163 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1164 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1165 break; 1166 default: 1167 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1168 break; 1169 } 1170 1171 return; 1172 } 1173 1174 /* 1175 * Configure the Tigon's multicast address filter. 1176 * 1177 * The actual multicast table management is a bit of a pain, thanks to 1178 * slight brain damage on the part of both Alteon and us. With our 1179 * multicast code, we are only alerted when the multicast address table 1180 * changes and at that point we only have the current list of addresses: 1181 * we only know the current state, not the previous state, so we don't 1182 * actually know what addresses were removed or added. The firmware has 1183 * state, but we can't get our grubby mits on it, and there is no 'delete 1184 * all multicast addresses' command. Hence, we have to maintain our own 1185 * state so we know what addresses have been programmed into the NIC at 1186 * any given time. 1187 */ 1188 static void ti_setmulti(sc) 1189 struct ti_softc *sc; 1190 { 1191 struct ifnet *ifp; 1192 struct ti_cmd_desc cmd; 1193 struct ti_mc_entry *mc; 1194 u_int32_t intrs; 1195 struct ether_multi *enm; 1196 struct ether_multistep step; 1197 1198 ifp = &sc->ethercom.ec_if; 1199 1200 /* Disable interrupts. */ 1201 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1202 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1203 1204 /* First, zot all the existing filters. */ 1205 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1206 ti_del_mcast(sc, &mc->mc_addr); 1207 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1208 free(mc, M_DEVBUF); 1209 } 1210 1211 /* 1212 * Remember all multicast addresses so that we can delete them 1213 * later. Punt if there is a range of addresses or memory shortage. 1214 */ 1215 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1216 while (enm != NULL) { 1217 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1218 ETHER_ADDR_LEN) != 0) 1219 goto allmulti; 1220 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1221 M_NOWAIT)) == NULL) 1222 goto allmulti; 1223 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1224 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1225 ETHER_NEXT_MULTI(step, enm); 1226 } 1227 1228 /* Accept only programmed multicast addresses */ 1229 ifp->if_flags &= ~IFF_ALLMULTI; 1230 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1231 1232 /* Now program new ones. */ 1233 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1234 ti_add_mcast(sc, &mc->mc_addr); 1235 1236 /* Re-enable interrupts. */ 1237 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1238 1239 return; 1240 1241 allmulti: 1242 /* No need to keep individual multicast addresses */ 1243 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1244 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1245 free(mc, M_DEVBUF); 1246 } 1247 1248 /* Accept all multicast addresses */ 1249 ifp->if_flags |= IFF_ALLMULTI; 1250 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1251 1252 /* Re-enable interrupts. */ 1253 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1254 } 1255 1256 /* 1257 * Check to see if the BIOS has configured us for a 64 bit slot when 1258 * we aren't actually in one. If we detect this condition, we can work 1259 * around it on the Tigon 2 by setting a bit in the PCI state register, 1260 * but for the Tigon 1 we must give up and abort the interface attach. 1261 */ 1262 static int ti_64bitslot_war(sc) 1263 struct ti_softc *sc; 1264 { 1265 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1266 CSR_WRITE_4(sc, 0x600, 0); 1267 CSR_WRITE_4(sc, 0x604, 0); 1268 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1269 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1270 if (sc->ti_hwrev == TI_HWREV_TIGON) 1271 return(EINVAL); 1272 else { 1273 TI_SETBIT(sc, TI_PCI_STATE, 1274 TI_PCISTATE_32BIT_BUS); 1275 return(0); 1276 } 1277 } 1278 } 1279 1280 return(0); 1281 } 1282 1283 /* 1284 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1285 * self-test results. 1286 */ 1287 static int ti_chipinit(sc) 1288 struct ti_softc *sc; 1289 { 1290 u_int32_t cacheline; 1291 u_int32_t pci_writemax = 0; 1292 1293 /* Initialize link to down state. */ 1294 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1295 1296 /* Set endianness before we access any non-PCI registers. */ 1297 #if BYTE_ORDER == BIG_ENDIAN 1298 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1299 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1300 #else 1301 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1302 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1303 #endif 1304 1305 /* Check the ROM failed bit to see if self-tests passed. */ 1306 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1307 printf("%s: board self-diagnostics failed!\n", 1308 sc->sc_dev.dv_xname); 1309 return(ENODEV); 1310 } 1311 1312 /* Halt the CPU. */ 1313 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1314 1315 /* Figure out the hardware revision. */ 1316 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1317 case TI_REV_TIGON_I: 1318 sc->ti_hwrev = TI_HWREV_TIGON; 1319 break; 1320 case TI_REV_TIGON_II: 1321 sc->ti_hwrev = TI_HWREV_TIGON_II; 1322 break; 1323 default: 1324 printf("%s: unsupported chip revision\n", sc->sc_dev.dv_xname); 1325 return(ENODEV); 1326 } 1327 1328 /* Do special setup for Tigon 2. */ 1329 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1330 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1331 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1332 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1333 } 1334 1335 /* Set up the PCI state register. */ 1336 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1337 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1338 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1339 } 1340 1341 /* Clear the read/write max DMA parameters. */ 1342 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1343 TI_PCISTATE_READ_MAXDMA)); 1344 1345 /* Get cache line size. */ 1346 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1347 1348 /* 1349 * If the system has set enabled the PCI memory write 1350 * and invalidate command in the command register, set 1351 * the write max parameter accordingly. This is necessary 1352 * to use MWI with the Tigon 2. 1353 */ 1354 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1355 & PCI_COMMAND_INVALIDATE_ENABLE) { 1356 switch(cacheline) { 1357 case 1: 1358 case 4: 1359 case 8: 1360 case 16: 1361 case 32: 1362 case 64: 1363 break; 1364 default: 1365 /* Disable PCI memory write and invalidate. */ 1366 if (bootverbose) 1367 printf("%s: cache line size %d not " 1368 "supported; disabling PCI MWI\n", 1369 sc->sc_dev.dv_xname, cacheline); 1370 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1371 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1372 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1373 break; 1374 } 1375 } 1376 1377 #ifdef __brokenalpha__ 1378 /* 1379 * From the Alteon sample driver: 1380 * Must insure that we do not cross an 8K (bytes) boundary 1381 * for DMA reads. Our highest limit is 1K bytes. This is a 1382 * restriction on some ALPHA platforms with early revision 1383 * 21174 PCI chipsets, such as the AlphaPC 164lx 1384 */ 1385 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1386 #else 1387 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1388 #endif 1389 1390 /* This sets the min dma param all the way up (0xff). */ 1391 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1392 1393 /* Configure DMA variables. */ 1394 #if BYTE_ORDER == BIG_ENDIAN 1395 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1396 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1397 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1398 TI_OPMODE_DONT_FRAG_JUMBO); 1399 #else 1400 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1401 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1402 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1403 #endif 1404 1405 /* 1406 * Only allow 1 DMA channel to be active at a time. 1407 * I don't think this is a good idea, but without it 1408 * the firmware racks up lots of nicDmaReadRingFull 1409 * errors. 1410 * Incompatible with hardware assisted checksums. 1411 */ 1412 if ((sc->ethercom.ec_if.if_capenable & 1413 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4|IFCAP_CSUM_IPv4)) == 0) 1414 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1415 1416 /* Recommended settings from Tigon manual. */ 1417 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1418 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1419 1420 if (ti_64bitslot_war(sc)) { 1421 printf("%s: bios thinks we're in a 64 bit slot, " 1422 "but we aren't", sc->sc_dev.dv_xname); 1423 return(EINVAL); 1424 } 1425 1426 return(0); 1427 } 1428 1429 /* 1430 * Initialize the general information block and firmware, and 1431 * start the CPU(s) running. 1432 */ 1433 static int ti_gibinit(sc) 1434 struct ti_softc *sc; 1435 { 1436 struct ti_rcb *rcb; 1437 int i; 1438 struct ifnet *ifp; 1439 1440 ifp = &sc->ethercom.ec_if; 1441 1442 /* Disable interrupts for now. */ 1443 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1444 1445 /* Tell the chip where to find the general information block. */ 1446 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1447 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1448 1449 /* Load the firmware into SRAM. */ 1450 ti_loadfw(sc); 1451 1452 /* Set up the contents of the general info and ring control blocks. */ 1453 1454 /* Set up the event ring and producer pointer. */ 1455 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1456 1457 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1458 rcb->ti_flags = 0; 1459 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1460 TI_CDEVPRODADDR(sc); 1461 1462 sc->ti_ev_prodidx.ti_idx = 0; 1463 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1464 sc->ti_ev_saved_considx = 0; 1465 1466 /* Set up the command ring and producer mailbox. */ 1467 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1468 1469 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1470 rcb->ti_flags = 0; 1471 rcb->ti_max_len = 0; 1472 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1473 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1474 } 1475 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1476 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1477 sc->ti_cmd_saved_prodidx = 0; 1478 1479 /* 1480 * Assign the address of the stats refresh buffer. 1481 * We re-use the current stats buffer for this to 1482 * conserve memory. 1483 */ 1484 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1485 TI_CDSTATSADDR(sc); 1486 1487 /* Set up the standard receive ring. */ 1488 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1489 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1490 rcb->ti_max_len = ETHER_MAX_LEN; 1491 rcb->ti_flags = 0; 1492 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1493 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1494 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1495 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1496 if (sc->ethercom.ec_nvlans != 0) 1497 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1498 1499 /* Set up the jumbo receive ring. */ 1500 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1501 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1502 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1503 rcb->ti_flags = 0; 1504 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1505 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1506 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1507 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1508 if (sc->ethercom.ec_nvlans != 0) 1509 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1510 1511 /* 1512 * Set up the mini ring. Only activated on the 1513 * Tigon 2 but the slot in the config block is 1514 * still there on the Tigon 1. 1515 */ 1516 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1517 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1518 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1519 if (sc->ti_hwrev == TI_HWREV_TIGON) 1520 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1521 else 1522 rcb->ti_flags = 0; 1523 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1524 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1525 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1526 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1527 if (sc->ethercom.ec_nvlans != 0) 1528 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1529 1530 /* 1531 * Set up the receive return ring. 1532 */ 1533 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1534 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1535 rcb->ti_flags = 0; 1536 rcb->ti_max_len = TI_RETURN_RING_CNT; 1537 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1538 TI_CDRTNPRODADDR(sc); 1539 1540 /* 1541 * Set up the tx ring. Note: for the Tigon 2, we have the option 1542 * of putting the transmit ring in the host's address space and 1543 * letting the chip DMA it instead of leaving the ring in the NIC's 1544 * memory and accessing it through the shared memory region. We 1545 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1546 * so we have to revert to the shared memory scheme if we detect 1547 * a Tigon 1 chip. 1548 */ 1549 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1550 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1551 sc->ti_tx_ring_nic = 1552 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1553 } 1554 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1555 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1556 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1557 if (sc->ti_hwrev == TI_HWREV_TIGON) 1558 rcb->ti_flags = 0; 1559 else 1560 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1561 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1562 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1563 /* 1564 * When we get the packet, there is a pseudo-header seed already 1565 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1566 * compute the pseudo-header checksum again! 1567 */ 1568 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1569 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM| 1570 TI_RCB_FLAG_NO_PHDR_CKSUM; 1571 if (sc->ethercom.ec_nvlans != 0) 1572 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1573 rcb->ti_max_len = TI_TX_RING_CNT; 1574 if (sc->ti_hwrev == TI_HWREV_TIGON) 1575 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1576 else 1577 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1578 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1579 TI_CDTXCONSADDR(sc); 1580 1581 /* 1582 * We're done frobbing the General Information Block. Sync 1583 * it. Note we take care of the first stats sync here, as 1584 * well. 1585 */ 1586 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1587 1588 /* Set up tuneables */ 1589 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1590 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1591 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1592 (sc->ti_rx_coal_ticks / 10)); 1593 else 1594 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1595 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1596 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1597 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1598 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1599 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1600 1601 /* Turn interrupts on. */ 1602 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1603 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1604 1605 /* Start CPU. */ 1606 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1607 1608 return(0); 1609 } 1610 1611 /* 1612 * look for id in the device list, returning the first match 1613 */ 1614 static const struct ti_type * 1615 ti_type_match(pa) 1616 struct pci_attach_args *pa; 1617 { 1618 const struct ti_type *t; 1619 1620 t = ti_devs; 1621 while(t->ti_name != NULL) { 1622 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1623 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1624 return (t); 1625 } 1626 t++; 1627 } 1628 1629 return(NULL); 1630 } 1631 1632 /* 1633 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1634 * against our list and return its name if we find a match. 1635 */ 1636 static int ti_probe(parent, match, aux) 1637 struct device *parent; 1638 struct cfdata *match; 1639 void *aux; 1640 { 1641 struct pci_attach_args *pa = aux; 1642 const struct ti_type *t; 1643 1644 t = ti_type_match(pa); 1645 1646 return((t == NULL) ? 0 : 1); 1647 } 1648 1649 static void ti_attach(parent, self, aux) 1650 struct device *parent, *self; 1651 void *aux; 1652 { 1653 u_int32_t command; 1654 struct ifnet *ifp; 1655 struct ti_softc *sc; 1656 u_char eaddr[ETHER_ADDR_LEN]; 1657 struct pci_attach_args *pa = aux; 1658 pci_chipset_tag_t pc = pa->pa_pc; 1659 pci_intr_handle_t ih; 1660 const char *intrstr = NULL; 1661 bus_dma_segment_t dmaseg; 1662 int error, dmanseg, nolinear; 1663 const struct ti_type *t; 1664 1665 t = ti_type_match(pa); 1666 if (t == NULL) { 1667 printf("ti_attach: were did the card go ?\n"); 1668 return; 1669 } 1670 1671 printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class)); 1672 1673 sc = (struct ti_softc *)self; 1674 1675 /* 1676 * Map control/status registers. 1677 */ 1678 nolinear = 0; 1679 if (pci_mapreg_map(pa, 0x10, 1680 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1681 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1682 NULL, NULL)) { 1683 nolinear = 1; 1684 if (pci_mapreg_map(pa, 0x10, 1685 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1686 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1687 printf(": can't map memory space\n"); 1688 return; 1689 } 1690 } 1691 if (nolinear == 0) 1692 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1693 else 1694 sc->ti_vhandle = NULL; 1695 1696 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1697 command |= PCI_COMMAND_MASTER_ENABLE; 1698 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1699 1700 /* Allocate interrupt */ 1701 if (pci_intr_map(pa, &ih)) { 1702 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 1703 return;; 1704 } 1705 intrstr = pci_intr_string(pc, ih); 1706 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1707 if (sc->sc_ih == NULL) { 1708 printf("%s: couldn't establish interrupt", 1709 sc->sc_dev.dv_xname); 1710 if (intrstr != NULL) 1711 printf(" at %s", intrstr); 1712 printf("\n"); 1713 return;; 1714 } 1715 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1716 /* 1717 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1718 * doing do could allow DMA to corrupt kernel memory during the 1719 * reboot before the driver initializes. 1720 */ 1721 (void) shutdownhook_establish(ti_shutdown, sc); 1722 1723 if (ti_chipinit(sc)) { 1724 printf("%s: chip initialization failed\n", self->dv_xname); 1725 goto fail2; 1726 } 1727 1728 /* 1729 * Deal with some chip diffrences. 1730 */ 1731 switch (sc->ti_hwrev) { 1732 case TI_HWREV_TIGON: 1733 sc->sc_tx_encap = ti_encap_tigon1; 1734 sc->sc_tx_eof = ti_txeof_tigon1; 1735 if (nolinear == 1) 1736 printf("%s: memory space not mapped linear\n", 1737 self->dv_xname); 1738 break; 1739 1740 case TI_HWREV_TIGON_II: 1741 sc->sc_tx_encap = ti_encap_tigon2; 1742 sc->sc_tx_eof = ti_txeof_tigon2; 1743 break; 1744 1745 default: 1746 printf("%s: Unknown chip version: %d\n", self->dv_xname, 1747 sc->ti_hwrev); 1748 goto fail2; 1749 } 1750 1751 /* Zero out the NIC's on-board SRAM. */ 1752 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1753 1754 /* Init again -- zeroing memory may have clobbered some registers. */ 1755 if (ti_chipinit(sc)) { 1756 printf("%s: chip initialization failed\n", self->dv_xname); 1757 goto fail2; 1758 } 1759 1760 /* 1761 * Get station address from the EEPROM. Note: the manual states 1762 * that the MAC address is at offset 0x8c, however the data is 1763 * stored as two longwords (since that's how it's loaded into 1764 * the NIC). This means the MAC address is actually preceded 1765 * by two zero bytes. We need to skip over those. 1766 */ 1767 if (ti_read_eeprom(sc, (caddr_t)&eaddr, 1768 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1769 printf("%s: failed to read station address\n", self->dv_xname); 1770 goto fail2; 1771 } 1772 1773 /* 1774 * A Tigon chip was detected. Inform the world. 1775 */ 1776 printf("%s: Ethernet address: %s\n", self->dv_xname, 1777 ether_sprintf(eaddr)); 1778 1779 sc->sc_dmat = pa->pa_dmat; 1780 1781 /* Allocate the general information block and ring buffers. */ 1782 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1783 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1784 BUS_DMA_NOWAIT)) != 0) { 1785 printf("%s: can't allocate ring buffer, error = %d\n", 1786 sc->sc_dev.dv_xname, error); 1787 goto fail2; 1788 } 1789 1790 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1791 sizeof(struct ti_ring_data), (caddr_t *)&sc->ti_rdata, 1792 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1793 printf("%s: can't map ring buffer, error = %d\n", 1794 sc->sc_dev.dv_xname, error); 1795 goto fail2; 1796 } 1797 1798 if ((error = bus_dmamap_create(sc->sc_dmat, 1799 sizeof(struct ti_ring_data), 1, 1800 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1801 &sc->info_dmamap)) != 0) { 1802 printf("%s: can't create ring buffer DMA map, error = %d\n", 1803 sc->sc_dev.dv_xname, error); 1804 goto fail2; 1805 } 1806 1807 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1808 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1809 BUS_DMA_NOWAIT)) != 0) { 1810 printf("%s: can't load ring buffer DMA map, error = %d\n", 1811 sc->sc_dev.dv_xname, error); 1812 goto fail2; 1813 } 1814 1815 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1816 1817 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1818 1819 /* Try to allocate memory for jumbo buffers. */ 1820 if (ti_alloc_jumbo_mem(sc)) { 1821 printf("%s: jumbo buffer allocation failed\n", self->dv_xname); 1822 goto fail2; 1823 } 1824 1825 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1826 1827 /* 1828 * We really need a better way to tell a 1000baseT card 1829 * from a 1000baseSX one, since in theory there could be 1830 * OEMed 1000baseT cards from lame vendors who aren't 1831 * clever enough to change the PCI ID. For the moment 1832 * though, the AceNIC is the only copper card available. 1833 */ 1834 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1835 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1836 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1837 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1838 sc->ti_copper = 1; 1839 else 1840 sc->ti_copper = 0; 1841 1842 /* Set default tuneable values. */ 1843 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1844 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1845 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1846 sc->ti_rx_max_coal_bds = 64; 1847 sc->ti_tx_max_coal_bds = 128; 1848 sc->ti_tx_buf_ratio = 21; 1849 1850 /* Set up ifnet structure */ 1851 ifp = &sc->ethercom.ec_if; 1852 ifp->if_softc = sc; 1853 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1854 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1855 ifp->if_ioctl = ti_ioctl; 1856 ifp->if_start = ti_start; 1857 ifp->if_watchdog = ti_watchdog; 1858 IFQ_SET_READY(&ifp->if_snd); 1859 1860 #if 0 1861 /* 1862 * XXX This is not really correct -- we don't necessarily 1863 * XXX want to queue up as many as we can transmit at the 1864 * XXX upper layer like that. Someone with a board should 1865 * XXX check to see how this affects performance. 1866 */ 1867 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1868 #endif 1869 1870 /* 1871 * We can support 802.1Q VLAN-sized frames. 1872 */ 1873 sc->ethercom.ec_capabilities |= 1874 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1875 1876 /* 1877 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1878 */ 1879 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1880 IFCAP_CSUM_UDPv4; 1881 1882 /* Set up ifmedia support. */ 1883 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1884 if (sc->ti_copper) { 1885 /* 1886 * Copper cards allow manual 10/100 mode selection, 1887 * but not manual 1000baseT mode selection. Why? 1888 * Becuase currently there's no way to specify the 1889 * master/slave setting through the firmware interface, 1890 * so Alteon decided to just bag it and handle it 1891 * via autonegotiation. 1892 */ 1893 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1894 ifmedia_add(&sc->ifmedia, 1895 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1896 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1897 ifmedia_add(&sc->ifmedia, 1898 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1899 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 1900 ifmedia_add(&sc->ifmedia, 1901 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 1902 } else { 1903 /* Fiber cards don't support 10/100 modes. */ 1904 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1905 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1906 } 1907 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1908 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1909 1910 /* 1911 * Call MI attach routines. 1912 */ 1913 if_attach(ifp); 1914 ether_ifattach(ifp, eaddr); 1915 1916 return; 1917 fail2: 1918 pci_intr_disestablish(pc, sc->sc_ih); 1919 return; 1920 } 1921 1922 /* 1923 * Frame reception handling. This is called if there's a frame 1924 * on the receive return list. 1925 * 1926 * Note: we have to be able to handle three possibilities here: 1927 * 1) the frame is from the mini receive ring (can only happen) 1928 * on Tigon 2 boards) 1929 * 2) the frame is from the jumbo receive ring 1930 * 3) the frame is from the standard receive ring 1931 */ 1932 1933 static void ti_rxeof(sc) 1934 struct ti_softc *sc; 1935 { 1936 struct ifnet *ifp; 1937 struct ti_cmd_desc cmd; 1938 1939 ifp = &sc->ethercom.ec_if; 1940 1941 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1942 struct ti_rx_desc *cur_rx; 1943 u_int32_t rxidx; 1944 struct mbuf *m = NULL; 1945 u_int16_t vlan_tag = 0; 1946 int have_tag = 0; 1947 struct ether_header *eh; 1948 bus_dmamap_t dmamap; 1949 1950 cur_rx = 1951 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1952 rxidx = cur_rx->ti_idx; 1953 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1954 1955 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1956 have_tag = 1; 1957 vlan_tag = cur_rx->ti_vlan_tag; 1958 } 1959 1960 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1961 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1962 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1963 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1964 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1965 ifp->if_ierrors++; 1966 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1967 continue; 1968 } 1969 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1970 == ENOBUFS) { 1971 ifp->if_ierrors++; 1972 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1973 continue; 1974 } 1975 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1976 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1977 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1978 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1979 dmamap = sc->mini_dmamap[rxidx]; 1980 sc->mini_dmamap[rxidx] = 0; 1981 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1982 ifp->if_ierrors++; 1983 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1984 continue; 1985 } 1986 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1987 == ENOBUFS) { 1988 ifp->if_ierrors++; 1989 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1990 continue; 1991 } 1992 } else { 1993 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1994 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1995 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1996 dmamap = sc->std_dmamap[rxidx]; 1997 sc->std_dmamap[rxidx] = 0; 1998 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1999 ifp->if_ierrors++; 2000 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2001 continue; 2002 } 2003 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 2004 == ENOBUFS) { 2005 ifp->if_ierrors++; 2006 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2007 continue; 2008 } 2009 } 2010 2011 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 2012 ifp->if_ipackets++; 2013 m->m_pkthdr.rcvif = ifp; 2014 2015 #if NBPFILTER > 0 2016 /* 2017 * Handle BPF listeners. Let the BPF user see the packet, but 2018 * don't pass it up to the ether_input() layer unless it's 2019 * a broadcast packet, multicast packet, matches our ethernet 2020 * address or the interface is in promiscuous mode. 2021 */ 2022 if (ifp->if_bpf) 2023 bpf_mtap(ifp->if_bpf, m); 2024 #endif 2025 2026 eh = mtod(m, struct ether_header *); 2027 switch (ntohs(eh->ether_type)) { 2028 #ifdef INET 2029 case ETHERTYPE_IP: 2030 { 2031 struct ip *ip = (struct ip *) (eh + 1); 2032 2033 /* 2034 * Note the Tigon firmware does not invert 2035 * the checksum for us, hence the XOR. 2036 */ 2037 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2038 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 2039 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2040 /* 2041 * ntohs() the constant so the compiler can 2042 * optimize... 2043 * 2044 * XXX Figure out a sane way to deal with 2045 * fragmented packets. 2046 */ 2047 if ((ip->ip_off & htons(IP_MF|IP_OFFMASK)) == 0) { 2048 switch (ip->ip_p) { 2049 case IPPROTO_TCP: 2050 m->m_pkthdr.csum_data = 2051 cur_rx->ti_tcp_udp_cksum; 2052 m->m_pkthdr.csum_flags |= 2053 M_CSUM_TCPv4|M_CSUM_DATA; 2054 break; 2055 case IPPROTO_UDP: 2056 m->m_pkthdr.csum_data = 2057 cur_rx->ti_tcp_udp_cksum; 2058 m->m_pkthdr.csum_flags |= 2059 M_CSUM_UDPv4|M_CSUM_DATA; 2060 break; 2061 default: 2062 /* Nothing */; 2063 } 2064 } 2065 break; 2066 } 2067 #endif 2068 default: 2069 /* Nothing. */ 2070 break; 2071 } 2072 2073 if (have_tag) { 2074 struct m_tag *mtag; 2075 2076 mtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2077 M_NOWAIT); 2078 if (mtag) 2079 *(u_int *)mtag = vlan_tag; 2080 else { 2081 printf("%s: no mbuf for tag\n", ifp->if_xname); 2082 m_freem(m); 2083 continue; 2084 } 2085 have_tag = vlan_tag = 0; 2086 } 2087 (*ifp->if_input)(ifp, m); 2088 } 2089 2090 /* Only necessary on the Tigon 1. */ 2091 if (sc->ti_hwrev == TI_HWREV_TIGON) 2092 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2093 sc->ti_rx_saved_considx); 2094 2095 TI_UPDATE_STDPROD(sc, sc->ti_std); 2096 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2097 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2098 2099 return; 2100 } 2101 2102 static void ti_txeof_tigon1(sc) 2103 struct ti_softc *sc; 2104 { 2105 struct ti_tx_desc *cur_tx = NULL; 2106 struct ifnet *ifp; 2107 struct txdmamap_pool_entry *dma; 2108 2109 ifp = &sc->ethercom.ec_if; 2110 2111 /* 2112 * Go through our tx ring and free mbufs for those 2113 * frames that have been sent. 2114 */ 2115 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2116 u_int32_t idx = 0; 2117 2118 idx = sc->ti_tx_saved_considx; 2119 if (idx > 383) 2120 CSR_WRITE_4(sc, TI_WINBASE, 2121 TI_TX_RING_BASE + 6144); 2122 else if (idx > 255) 2123 CSR_WRITE_4(sc, TI_WINBASE, 2124 TI_TX_RING_BASE + 4096); 2125 else if (idx > 127) 2126 CSR_WRITE_4(sc, TI_WINBASE, 2127 TI_TX_RING_BASE + 2048); 2128 else 2129 CSR_WRITE_4(sc, TI_WINBASE, 2130 TI_TX_RING_BASE); 2131 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2132 if (cur_tx->ti_flags & TI_BDFLAG_END) 2133 ifp->if_opackets++; 2134 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2135 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2136 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2137 2138 dma = sc->txdma[idx]; 2139 KDASSERT(dma != NULL); 2140 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2141 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2142 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2143 2144 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2145 sc->txdma[idx] = NULL; 2146 } 2147 sc->ti_txcnt--; 2148 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2149 ifp->if_timer = 0; 2150 } 2151 2152 if (cur_tx != NULL) 2153 ifp->if_flags &= ~IFF_OACTIVE; 2154 2155 return; 2156 } 2157 2158 static void ti_txeof_tigon2(sc) 2159 struct ti_softc *sc; 2160 { 2161 struct ti_tx_desc *cur_tx = NULL; 2162 struct ifnet *ifp; 2163 struct txdmamap_pool_entry *dma; 2164 int firstidx, cnt; 2165 2166 ifp = &sc->ethercom.ec_if; 2167 2168 /* 2169 * Go through our tx ring and free mbufs for those 2170 * frames that have been sent. 2171 */ 2172 firstidx = sc->ti_tx_saved_considx; 2173 cnt = 0; 2174 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2175 u_int32_t idx = 0; 2176 2177 idx = sc->ti_tx_saved_considx; 2178 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2179 if (cur_tx->ti_flags & TI_BDFLAG_END) 2180 ifp->if_opackets++; 2181 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2182 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2183 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2184 2185 dma = sc->txdma[idx]; 2186 KDASSERT(dma != NULL); 2187 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2188 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2189 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2190 2191 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2192 sc->txdma[idx] = NULL; 2193 } 2194 cnt++; 2195 sc->ti_txcnt--; 2196 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2197 ifp->if_timer = 0; 2198 } 2199 2200 if (cnt != 0) 2201 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2202 2203 if (cur_tx != NULL) 2204 ifp->if_flags &= ~IFF_OACTIVE; 2205 2206 return; 2207 } 2208 2209 static int ti_intr(xsc) 2210 void *xsc; 2211 { 2212 struct ti_softc *sc; 2213 struct ifnet *ifp; 2214 2215 sc = xsc; 2216 ifp = &sc->ethercom.ec_if; 2217 2218 #ifdef notdef 2219 /* Avoid this for now -- checking this register is expensive. */ 2220 /* Make sure this is really our interrupt. */ 2221 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2222 return (0); 2223 #endif 2224 2225 /* Ack interrupt and stop others from occuring. */ 2226 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2227 2228 if (ifp->if_flags & IFF_RUNNING) { 2229 /* Check RX return ring producer/consumer */ 2230 ti_rxeof(sc); 2231 2232 /* Check TX ring producer/consumer */ 2233 (*sc->sc_tx_eof)(sc); 2234 } 2235 2236 ti_handle_events(sc); 2237 2238 /* Re-enable interrupts. */ 2239 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2240 2241 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2242 IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2243 ti_start(ifp); 2244 2245 return (1); 2246 } 2247 2248 static void ti_stats_update(sc) 2249 struct ti_softc *sc; 2250 { 2251 struct ifnet *ifp; 2252 2253 ifp = &sc->ethercom.ec_if; 2254 2255 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2256 2257 ifp->if_collisions += 2258 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2259 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2260 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2261 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2262 ifp->if_collisions; 2263 2264 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2265 } 2266 2267 /* 2268 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2269 * pointers to descriptors. 2270 */ 2271 static int ti_encap_tigon1(sc, m_head, txidx) 2272 struct ti_softc *sc; 2273 struct mbuf *m_head; 2274 u_int32_t *txidx; 2275 { 2276 struct ti_tx_desc *f = NULL; 2277 u_int32_t frag, cur, cnt = 0; 2278 struct txdmamap_pool_entry *dma; 2279 bus_dmamap_t dmamap; 2280 int error, i; 2281 struct m_tag *mtag; 2282 u_int16_t csum_flags = 0; 2283 2284 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2285 if (dma == NULL) { 2286 return ENOMEM; 2287 } 2288 dmamap = dma->dmamap; 2289 2290 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2291 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2292 if (error) { 2293 struct mbuf *m; 2294 int i = 0; 2295 for (m = m_head; m; m = m->m_next) 2296 i++; 2297 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2298 "error %d\n", m_head->m_pkthdr.len, i, error); 2299 return (ENOMEM); 2300 } 2301 2302 cur = frag = *txidx; 2303 2304 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2305 /* IP header checksum field must be 0! */ 2306 csum_flags |= TI_BDFLAG_IP_CKSUM; 2307 } 2308 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2309 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2310 2311 /* XXX fragmented packet checksum capability? */ 2312 2313 /* 2314 * Start packing the mbufs in this chain into 2315 * the fragment pointers. Stop when we run out 2316 * of fragments or hit the end of the mbuf chain. 2317 */ 2318 for (i = 0; i < dmamap->dm_nsegs; i++) { 2319 if (frag > 383) 2320 CSR_WRITE_4(sc, TI_WINBASE, 2321 TI_TX_RING_BASE + 6144); 2322 else if (frag > 255) 2323 CSR_WRITE_4(sc, TI_WINBASE, 2324 TI_TX_RING_BASE + 4096); 2325 else if (frag > 127) 2326 CSR_WRITE_4(sc, TI_WINBASE, 2327 TI_TX_RING_BASE + 2048); 2328 else 2329 CSR_WRITE_4(sc, TI_WINBASE, 2330 TI_TX_RING_BASE); 2331 f = &sc->ti_tx_ring_nic[frag % 128]; 2332 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2333 break; 2334 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2335 f->ti_len = dmamap->dm_segs[i].ds_len; 2336 f->ti_flags = csum_flags; 2337 mtag = m_tag_find(m_head, PACKET_TAG_VLAN, NULL); 2338 if (mtag) { 2339 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2340 f->ti_vlan_tag = *(u_int *)(mtag + 1); 2341 } else { 2342 f->ti_vlan_tag = 0; 2343 } 2344 /* 2345 * Sanity check: avoid coming within 16 descriptors 2346 * of the end of the ring. 2347 */ 2348 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2349 return(ENOBUFS); 2350 cur = frag; 2351 TI_INC(frag, TI_TX_RING_CNT); 2352 cnt++; 2353 } 2354 2355 if (i < dmamap->dm_nsegs) 2356 return(ENOBUFS); 2357 2358 if (frag == sc->ti_tx_saved_considx) 2359 return(ENOBUFS); 2360 2361 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2362 TI_BDFLAG_END; 2363 2364 /* Sync the packet's DMA map. */ 2365 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2366 BUS_DMASYNC_PREWRITE); 2367 2368 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2369 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2370 sc->txdma[cur] = dma; 2371 sc->ti_txcnt += cnt; 2372 2373 *txidx = frag; 2374 2375 return(0); 2376 } 2377 2378 static int ti_encap_tigon2(sc, m_head, txidx) 2379 struct ti_softc *sc; 2380 struct mbuf *m_head; 2381 u_int32_t *txidx; 2382 { 2383 struct ti_tx_desc *f = NULL; 2384 u_int32_t frag, firstfrag, cur, cnt = 0; 2385 struct txdmamap_pool_entry *dma; 2386 bus_dmamap_t dmamap; 2387 int error, i; 2388 struct m_tag *mtag; 2389 u_int16_t csum_flags = 0; 2390 2391 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2392 if (dma == NULL) { 2393 return ENOMEM; 2394 } 2395 dmamap = dma->dmamap; 2396 2397 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2398 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2399 if (error) { 2400 struct mbuf *m; 2401 int i = 0; 2402 for (m = m_head; m; m = m->m_next) 2403 i++; 2404 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2405 "error %d\n", m_head->m_pkthdr.len, i, error); 2406 return (ENOMEM); 2407 } 2408 2409 cur = firstfrag = frag = *txidx; 2410 2411 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2412 /* IP header checksum field must be 0! */ 2413 csum_flags |= TI_BDFLAG_IP_CKSUM; 2414 } 2415 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2416 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2417 2418 /* XXX fragmented packet checksum capability? */ 2419 2420 /* 2421 * Start packing the mbufs in this chain into 2422 * the fragment pointers. Stop when we run out 2423 * of fragments or hit the end of the mbuf chain. 2424 */ 2425 for (i = 0; i < dmamap->dm_nsegs; i++) { 2426 f = &sc->ti_rdata->ti_tx_ring[frag]; 2427 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2428 break; 2429 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2430 f->ti_len = dmamap->dm_segs[i].ds_len; 2431 f->ti_flags = csum_flags; 2432 mtag = m_tag_find(m_head, PACKET_TAG_VLAN, NULL); 2433 if (mtag) { 2434 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2435 f->ti_vlan_tag = *(u_int *)(mtag + 1); 2436 } else { 2437 f->ti_vlan_tag = 0; 2438 } 2439 /* 2440 * Sanity check: avoid coming within 16 descriptors 2441 * of the end of the ring. 2442 */ 2443 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2444 return(ENOBUFS); 2445 cur = frag; 2446 TI_INC(frag, TI_TX_RING_CNT); 2447 cnt++; 2448 } 2449 2450 if (i < dmamap->dm_nsegs) 2451 return(ENOBUFS); 2452 2453 if (frag == sc->ti_tx_saved_considx) 2454 return(ENOBUFS); 2455 2456 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2457 2458 /* Sync the packet's DMA map. */ 2459 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2460 BUS_DMASYNC_PREWRITE); 2461 2462 /* Sync the descriptors we are using. */ 2463 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2464 2465 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2466 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2467 sc->txdma[cur] = dma; 2468 sc->ti_txcnt += cnt; 2469 2470 *txidx = frag; 2471 2472 return(0); 2473 } 2474 2475 /* 2476 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2477 * to the mbuf data regions directly in the transmit descriptors. 2478 */ 2479 static void ti_start(ifp) 2480 struct ifnet *ifp; 2481 { 2482 struct ti_softc *sc; 2483 struct mbuf *m_head = NULL; 2484 u_int32_t prodidx = 0; 2485 2486 sc = ifp->if_softc; 2487 2488 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2489 2490 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2491 IFQ_POLL(&ifp->if_snd, m_head); 2492 if (m_head == NULL) 2493 break; 2494 2495 /* 2496 * Pack the data into the transmit ring. If we 2497 * don't have room, set the OACTIVE flag and wait 2498 * for the NIC to drain the ring. 2499 */ 2500 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2501 ifp->if_flags |= IFF_OACTIVE; 2502 break; 2503 } 2504 2505 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2506 2507 /* 2508 * If there's a BPF listener, bounce a copy of this frame 2509 * to him. 2510 */ 2511 #if NBPFILTER > 0 2512 if (ifp->if_bpf) 2513 bpf_mtap(ifp->if_bpf, m_head); 2514 #endif 2515 } 2516 2517 /* Transmit */ 2518 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2519 2520 /* 2521 * Set a timeout in case the chip goes out to lunch. 2522 */ 2523 ifp->if_timer = 5; 2524 2525 return; 2526 } 2527 2528 static void ti_init(xsc) 2529 void *xsc; 2530 { 2531 struct ti_softc *sc = xsc; 2532 int s; 2533 2534 s = splnet(); 2535 2536 /* Cancel pending I/O and flush buffers. */ 2537 ti_stop(sc); 2538 2539 /* Init the gen info block, ring control blocks and firmware. */ 2540 if (ti_gibinit(sc)) { 2541 printf("%s: initialization failure\n", sc->sc_dev.dv_xname); 2542 splx(s); 2543 return; 2544 } 2545 2546 splx(s); 2547 2548 return; 2549 } 2550 2551 static void ti_init2(sc) 2552 struct ti_softc *sc; 2553 { 2554 struct ti_cmd_desc cmd; 2555 struct ifnet *ifp; 2556 u_int8_t *m; 2557 struct ifmedia *ifm; 2558 int tmp; 2559 2560 ifp = &sc->ethercom.ec_if; 2561 2562 /* Specify MTU and interface index. */ 2563 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->sc_dev.dv_unit); /* ??? */ 2564 2565 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2566 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2567 tmp += ETHER_VLAN_ENCAP_LEN; 2568 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2569 2570 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2571 2572 /* Load our MAC address. */ 2573 m = (u_int8_t *)LLADDR(ifp->if_sadl); 2574 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2575 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2576 | (m[4] << 8) | m[5]); 2577 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2578 2579 /* Enable or disable promiscuous mode as needed. */ 2580 if (ifp->if_flags & IFF_PROMISC) { 2581 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2582 } else { 2583 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2584 } 2585 2586 /* Program multicast filter. */ 2587 ti_setmulti(sc); 2588 2589 /* 2590 * If this is a Tigon 1, we should tell the 2591 * firmware to use software packet filtering. 2592 */ 2593 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2594 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2595 } 2596 2597 /* Init RX ring. */ 2598 ti_init_rx_ring_std(sc); 2599 2600 /* Init jumbo RX ring. */ 2601 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2602 ti_init_rx_ring_jumbo(sc); 2603 2604 /* 2605 * If this is a Tigon 2, we can also configure the 2606 * mini ring. 2607 */ 2608 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2609 ti_init_rx_ring_mini(sc); 2610 2611 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2612 sc->ti_rx_saved_considx = 0; 2613 2614 /* Init TX ring. */ 2615 ti_init_tx_ring(sc); 2616 2617 /* Tell firmware we're alive. */ 2618 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2619 2620 /* Enable host interrupts. */ 2621 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2622 2623 ifp->if_flags |= IFF_RUNNING; 2624 ifp->if_flags &= ~IFF_OACTIVE; 2625 2626 /* 2627 * Make sure to set media properly. We have to do this 2628 * here since we have to issue commands in order to set 2629 * the link negotiation and we can't issue commands until 2630 * the firmware is running. 2631 */ 2632 ifm = &sc->ifmedia; 2633 tmp = ifm->ifm_media; 2634 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2635 ti_ifmedia_upd(ifp); 2636 ifm->ifm_media = tmp; 2637 2638 return; 2639 } 2640 2641 /* 2642 * Set media options. 2643 */ 2644 static int ti_ifmedia_upd(ifp) 2645 struct ifnet *ifp; 2646 { 2647 struct ti_softc *sc; 2648 struct ifmedia *ifm; 2649 struct ti_cmd_desc cmd; 2650 2651 sc = ifp->if_softc; 2652 ifm = &sc->ifmedia; 2653 2654 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2655 return(EINVAL); 2656 2657 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2658 case IFM_AUTO: 2659 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2660 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2661 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2662 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2663 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2664 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2665 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2666 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2667 break; 2668 case IFM_1000_SX: 2669 case IFM_1000_T: 2670 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2671 CSR_WRITE_4(sc, TI_GCR_GLINK, 2672 TI_GLNK_PREF|TI_GLNK_1000MB|TI_GLNK_FULL_DUPLEX| 2673 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2674 } else { 2675 CSR_WRITE_4(sc, TI_GCR_GLINK, 2676 TI_GLNK_PREF|TI_GLNK_1000MB| 2677 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2678 } 2679 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2680 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2681 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2682 break; 2683 case IFM_100_FX: 2684 case IFM_10_FL: 2685 case IFM_100_TX: 2686 case IFM_10_T: 2687 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2688 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2689 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2690 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2691 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2692 } else { 2693 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2694 } 2695 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2696 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2697 } else { 2698 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2699 } 2700 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2701 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2702 break; 2703 } 2704 2705 sc->ethercom.ec_if.if_baudrate = 2706 ifmedia_baudrate(ifm->ifm_media); 2707 2708 return(0); 2709 } 2710 2711 /* 2712 * Report current media status. 2713 */ 2714 static void ti_ifmedia_sts(ifp, ifmr) 2715 struct ifnet *ifp; 2716 struct ifmediareq *ifmr; 2717 { 2718 struct ti_softc *sc; 2719 u_int32_t media = 0; 2720 2721 sc = ifp->if_softc; 2722 2723 ifmr->ifm_status = IFM_AVALID; 2724 ifmr->ifm_active = IFM_ETHER; 2725 2726 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2727 return; 2728 2729 ifmr->ifm_status |= IFM_ACTIVE; 2730 2731 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2732 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2733 if (sc->ti_copper) 2734 ifmr->ifm_active |= IFM_1000_T; 2735 else 2736 ifmr->ifm_active |= IFM_1000_SX; 2737 if (media & TI_GLNK_FULL_DUPLEX) 2738 ifmr->ifm_active |= IFM_FDX; 2739 else 2740 ifmr->ifm_active |= IFM_HDX; 2741 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2742 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2743 if (sc->ti_copper) { 2744 if (media & TI_LNK_100MB) 2745 ifmr->ifm_active |= IFM_100_TX; 2746 if (media & TI_LNK_10MB) 2747 ifmr->ifm_active |= IFM_10_T; 2748 } else { 2749 if (media & TI_LNK_100MB) 2750 ifmr->ifm_active |= IFM_100_FX; 2751 if (media & TI_LNK_10MB) 2752 ifmr->ifm_active |= IFM_10_FL; 2753 } 2754 if (media & TI_LNK_FULL_DUPLEX) 2755 ifmr->ifm_active |= IFM_FDX; 2756 if (media & TI_LNK_HALF_DUPLEX) 2757 ifmr->ifm_active |= IFM_HDX; 2758 } 2759 2760 sc->ethercom.ec_if.if_baudrate = 2761 ifmedia_baudrate(sc->ifmedia.ifm_media); 2762 2763 return; 2764 } 2765 2766 static int 2767 ti_ether_ioctl(ifp, cmd, data) 2768 struct ifnet *ifp; 2769 u_long cmd; 2770 caddr_t data; 2771 { 2772 struct ifaddr *ifa = (struct ifaddr *) data; 2773 struct ti_softc *sc = ifp->if_softc; 2774 2775 if ((ifp->if_flags & IFF_UP) == 0) { 2776 ifp->if_flags |= IFF_UP; 2777 ti_init(sc); 2778 } 2779 2780 switch (cmd) { 2781 case SIOCSIFADDR: 2782 2783 switch (ifa->ifa_addr->sa_family) { 2784 #ifdef INET 2785 case AF_INET: 2786 arp_ifinit(ifp, ifa); 2787 break; 2788 #endif 2789 #ifdef NS 2790 case AF_NS: 2791 { 2792 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 2793 2794 if (ns_nullhost(*ina)) 2795 ina->x_host = *(union ns_host *) 2796 LLADDR(ifp->if_sadl); 2797 else 2798 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 2799 ifp->if_addrlen); 2800 break; 2801 } 2802 #endif 2803 default: 2804 break; 2805 } 2806 break; 2807 2808 default: 2809 return (EINVAL); 2810 } 2811 2812 return (0); 2813 } 2814 2815 static int ti_ioctl(ifp, command, data) 2816 struct ifnet *ifp; 2817 u_long command; 2818 caddr_t data; 2819 { 2820 struct ti_softc *sc = ifp->if_softc; 2821 struct ifreq *ifr = (struct ifreq *) data; 2822 int s, error = 0; 2823 struct ti_cmd_desc cmd; 2824 2825 s = splnet(); 2826 2827 switch(command) { 2828 case SIOCSIFADDR: 2829 case SIOCGIFADDR: 2830 error = ti_ether_ioctl(ifp, command, data); 2831 break; 2832 case SIOCSIFMTU: 2833 if (ifr->ifr_mtu > ETHERMTU_JUMBO) 2834 error = EINVAL; 2835 else { 2836 ifp->if_mtu = ifr->ifr_mtu; 2837 ti_init(sc); 2838 } 2839 break; 2840 case SIOCSIFFLAGS: 2841 if (ifp->if_flags & IFF_UP) { 2842 /* 2843 * If only the state of the PROMISC flag changed, 2844 * then just use the 'set promisc mode' command 2845 * instead of reinitializing the entire NIC. Doing 2846 * a full re-init means reloading the firmware and 2847 * waiting for it to start up, which may take a 2848 * second or two. 2849 */ 2850 if (ifp->if_flags & IFF_RUNNING && 2851 ifp->if_flags & IFF_PROMISC && 2852 !(sc->ti_if_flags & IFF_PROMISC)) { 2853 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2854 TI_CMD_CODE_PROMISC_ENB, 0); 2855 } else if (ifp->if_flags & IFF_RUNNING && 2856 !(ifp->if_flags & IFF_PROMISC) && 2857 sc->ti_if_flags & IFF_PROMISC) { 2858 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2859 TI_CMD_CODE_PROMISC_DIS, 0); 2860 } else 2861 ti_init(sc); 2862 } else { 2863 if (ifp->if_flags & IFF_RUNNING) { 2864 ti_stop(sc); 2865 } 2866 } 2867 sc->ti_if_flags = ifp->if_flags; 2868 error = 0; 2869 break; 2870 case SIOCADDMULTI: 2871 case SIOCDELMULTI: 2872 error = (command == SIOCADDMULTI) ? 2873 ether_addmulti(ifr, &sc->ethercom) : 2874 ether_delmulti(ifr, &sc->ethercom); 2875 if (error == ENETRESET) { 2876 if (ifp->if_flags & IFF_RUNNING) 2877 ti_setmulti(sc); 2878 error = 0; 2879 } 2880 break; 2881 case SIOCSIFMEDIA: 2882 case SIOCGIFMEDIA: 2883 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2884 break; 2885 default: 2886 error = EINVAL; 2887 break; 2888 } 2889 2890 (void)splx(s); 2891 2892 return(error); 2893 } 2894 2895 static void ti_watchdog(ifp) 2896 struct ifnet *ifp; 2897 { 2898 struct ti_softc *sc; 2899 2900 sc = ifp->if_softc; 2901 2902 printf("%s: watchdog timeout -- resetting\n", sc->sc_dev.dv_xname); 2903 ti_stop(sc); 2904 ti_init(sc); 2905 2906 ifp->if_oerrors++; 2907 2908 return; 2909 } 2910 2911 /* 2912 * Stop the adapter and free any mbufs allocated to the 2913 * RX and TX lists. 2914 */ 2915 static void ti_stop(sc) 2916 struct ti_softc *sc; 2917 { 2918 struct ifnet *ifp; 2919 struct ti_cmd_desc cmd; 2920 2921 ifp = &sc->ethercom.ec_if; 2922 2923 /* Disable host interrupts. */ 2924 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2925 /* 2926 * Tell firmware we're shutting down. 2927 */ 2928 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2929 2930 /* Halt and reinitialize. */ 2931 ti_chipinit(sc); 2932 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2933 ti_chipinit(sc); 2934 2935 /* Free the RX lists. */ 2936 ti_free_rx_ring_std(sc); 2937 2938 /* Free jumbo RX list. */ 2939 ti_free_rx_ring_jumbo(sc); 2940 2941 /* Free mini RX list. */ 2942 ti_free_rx_ring_mini(sc); 2943 2944 /* Free TX buffers. */ 2945 ti_free_tx_ring(sc); 2946 2947 sc->ti_ev_prodidx.ti_idx = 0; 2948 sc->ti_return_prodidx.ti_idx = 0; 2949 sc->ti_tx_considx.ti_idx = 0; 2950 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2951 2952 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2953 2954 return; 2955 } 2956 2957 /* 2958 * Stop all chip I/O so that the kernel's probe routines don't 2959 * get confused by errant DMAs when rebooting. 2960 */ 2961 static void ti_shutdown(v) 2962 void *v; 2963 { 2964 struct ti_softc *sc = v; 2965 2966 ti_chipinit(sc); 2967 2968 return; 2969 } 2970
Indexes created Fri Sep 26 20:09:58 GMT 2025