if_ti.c revision 1.59
1 /* $NetBSD: if_ti.c,v 1.59 2004/03/18 22:45:35 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.59 2004/03/18 22:45:35 bouyer Exp $"); 85 86 #include "bpfilter.h" 87 #include "opt_inet.h" 88 #include "opt_ns.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/queue.h> 98 #include <sys/device.h> 99 #include <sys/reboot.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #ifdef INET 114 #include <netinet/in.h> 115 #include <netinet/if_inarp.h> 116 #include <netinet/in_systm.h> 117 #include <netinet/ip.h> 118 #endif 119 120 #ifdef NS 121 #include <netns/ns.h> 122 #include <netns/ns_if.h> 123 #endif 124 125 #include <machine/bus.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/pcidevs.h> 130 131 #include <dev/pci/if_tireg.h> 132 133 #include <dev/microcode/tigon/ti_fw.h> 134 #include <dev/microcode/tigon/ti_fw2.h> 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 140 static const struct ti_type ti_devs[] = { 141 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 142 "Alteon AceNIC 1000BASE-SX Ethernet" }, 143 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 144 "Alteon AceNIC 1000BASE-T Ethernet" }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 146 "3Com 3c985-SX Gigabit Ethernet" }, 147 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 148 "Netgear GA620 1000BASE-SX Ethernet" }, 149 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 150 "Netgear GA620 1000BASE-T Ethernet" }, 151 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 152 "Silicon Graphics Gigabit Ethernet" }, 153 { 0, 0, NULL } 154 }; 155 156 static const struct ti_type *ti_type_match __P((struct pci_attach_args *)); 157 static int ti_probe __P((struct device *, struct cfdata *, void *)); 158 static void ti_attach __P((struct device *, struct device *, void *)); 159 static void ti_shutdown __P((void *)); 160 static void ti_txeof_tigon1 __P((struct ti_softc *)); 161 static void ti_txeof_tigon2 __P((struct ti_softc *)); 162 static void ti_rxeof __P((struct ti_softc *)); 163 164 static void ti_stats_update __P((struct ti_softc *)); 165 static int ti_encap_tigon1 __P((struct ti_softc *, struct mbuf *, 166 u_int32_t *)); 167 static int ti_encap_tigon2 __P((struct ti_softc *, struct mbuf *, 168 u_int32_t *)); 169 170 static int ti_intr __P((void *)); 171 static void ti_start __P((struct ifnet *)); 172 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 173 static void ti_init __P((void *)); 174 static void ti_init2 __P((struct ti_softc *)); 175 static void ti_stop __P((struct ti_softc *)); 176 static void ti_watchdog __P((struct ifnet *)); 177 static int ti_ifmedia_upd __P((struct ifnet *)); 178 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 179 180 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 181 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 182 int, u_int8_t *)); 183 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 184 185 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 186 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 187 static void ti_setmulti __P((struct ti_softc *)); 188 189 static void ti_mem __P((struct ti_softc *, u_int32_t, 190 u_int32_t, caddr_t)); 191 static void ti_loadfw __P((struct ti_softc *)); 192 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 193 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 194 caddr_t, int)); 195 static void ti_handle_events __P((struct ti_softc *)); 196 static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 197 static void *ti_jalloc __P((struct ti_softc *)); 198 static void ti_jfree __P((struct mbuf *, caddr_t, size_t, void *)); 199 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 200 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 201 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 202 static int ti_init_rx_ring_std __P((struct ti_softc *)); 203 static void ti_free_rx_ring_std __P((struct ti_softc *)); 204 static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 205 static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 206 static int ti_init_rx_ring_mini __P((struct ti_softc *)); 207 static void ti_free_rx_ring_mini __P((struct ti_softc *)); 208 static void ti_free_tx_ring __P((struct ti_softc *)); 209 static int ti_init_tx_ring __P((struct ti_softc *)); 210 211 static int ti_64bitslot_war __P((struct ti_softc *)); 212 static int ti_chipinit __P((struct ti_softc *)); 213 static int ti_gibinit __P((struct ti_softc *)); 214 215 static int ti_ether_ioctl __P((struct ifnet *, u_long, caddr_t)); 216 217 CFATTACH_DECL(ti, sizeof(struct ti_softc), 218 ti_probe, ti_attach, NULL, NULL); 219 220 /* 221 * Send an instruction or address to the EEPROM, check for ACK. 222 */ 223 static u_int32_t ti_eeprom_putbyte(sc, byte) 224 struct ti_softc *sc; 225 int byte; 226 { 227 int i, ack = 0; 228 229 /* 230 * Make sure we're in TX mode. 231 */ 232 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 233 234 /* 235 * Feed in each bit and stobe the clock. 236 */ 237 for (i = 0x80; i; i >>= 1) { 238 if (byte & i) { 239 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 240 } else { 241 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 242 } 243 DELAY(1); 244 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 245 DELAY(1); 246 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 247 } 248 249 /* 250 * Turn off TX mode. 251 */ 252 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 253 254 /* 255 * Check for ack. 256 */ 257 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 258 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 259 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 260 261 return(ack); 262 } 263 264 /* 265 * Read a byte of data stored in the EEPROM at address 'addr.' 266 * We have to send two address bytes since the EEPROM can hold 267 * more than 256 bytes of data. 268 */ 269 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 270 struct ti_softc *sc; 271 int addr; 272 u_int8_t *dest; 273 { 274 int i; 275 u_int8_t byte = 0; 276 277 EEPROM_START; 278 279 /* 280 * Send write control code to EEPROM. 281 */ 282 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 283 printf("%s: failed to send write command, status: %x\n", 284 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 285 return(1); 286 } 287 288 /* 289 * Send first byte of address of byte we want to read. 290 */ 291 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 292 printf("%s: failed to send address, status: %x\n", 293 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 294 return(1); 295 } 296 /* 297 * Send second byte address of byte we want to read. 298 */ 299 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 300 printf("%s: failed to send address, status: %x\n", 301 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 302 return(1); 303 } 304 305 EEPROM_STOP; 306 EEPROM_START; 307 /* 308 * Send read control code to EEPROM. 309 */ 310 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 311 printf("%s: failed to send read command, status: %x\n", 312 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 313 return(1); 314 } 315 316 /* 317 * Start reading bits from EEPROM. 318 */ 319 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 320 for (i = 0x80; i; i >>= 1) { 321 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 322 DELAY(1); 323 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 324 byte |= i; 325 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 326 DELAY(1); 327 } 328 329 EEPROM_STOP; 330 331 /* 332 * No ACK generated for read, so just return byte. 333 */ 334 335 *dest = byte; 336 337 return(0); 338 } 339 340 /* 341 * Read a sequence of bytes from the EEPROM. 342 */ 343 static int ti_read_eeprom(sc, dest, off, cnt) 344 struct ti_softc *sc; 345 caddr_t dest; 346 int off; 347 int cnt; 348 { 349 int err = 0, i; 350 u_int8_t byte = 0; 351 352 for (i = 0; i < cnt; i++) { 353 err = ti_eeprom_getbyte(sc, off + i, &byte); 354 if (err) 355 break; 356 *(dest + i) = byte; 357 } 358 359 return(err ? 1 : 0); 360 } 361 362 /* 363 * NIC memory access function. Can be used to either clear a section 364 * of NIC local memory or (if buf is non-NULL) copy data into it. 365 */ 366 static void ti_mem(sc, addr, len, buf) 367 struct ti_softc *sc; 368 u_int32_t addr, len; 369 caddr_t buf; 370 { 371 int segptr, segsize, cnt; 372 caddr_t ptr; 373 374 segptr = addr; 375 cnt = len; 376 ptr = buf; 377 378 while(cnt) { 379 if (cnt < TI_WINLEN) 380 segsize = cnt; 381 else 382 segsize = TI_WINLEN - (segptr % TI_WINLEN); 383 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 384 if (buf == NULL) { 385 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 386 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 387 segsize / 4); 388 } else { 389 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 390 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 391 (u_int32_t *)ptr, segsize / 4); 392 ptr += segsize; 393 } 394 segptr += segsize; 395 cnt -= segsize; 396 } 397 398 return; 399 } 400 401 /* 402 * Load firmware image into the NIC. Check that the firmware revision 403 * is acceptable and see if we want the firmware for the Tigon 1 or 404 * Tigon 2. 405 */ 406 static void ti_loadfw(sc) 407 struct ti_softc *sc; 408 { 409 switch(sc->ti_hwrev) { 410 case TI_HWREV_TIGON: 411 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 412 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 413 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 414 printf("%s: firmware revision mismatch; want " 415 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 416 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 417 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 418 tigonFwReleaseMinor, tigonFwReleaseFix); 419 return; 420 } 421 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 422 (caddr_t)tigonFwText); 423 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 424 (caddr_t)tigonFwData); 425 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 426 (caddr_t)tigonFwRodata); 427 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 428 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 429 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 430 break; 431 case TI_HWREV_TIGON_II: 432 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 433 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 434 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 435 printf("%s: firmware revision mismatch; want " 436 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 437 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 438 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 439 tigon2FwReleaseMinor, tigon2FwReleaseFix); 440 return; 441 } 442 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 443 (caddr_t)tigon2FwText); 444 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 445 (caddr_t)tigon2FwData); 446 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 447 (caddr_t)tigon2FwRodata); 448 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 449 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 450 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 451 break; 452 default: 453 printf("%s: can't load firmware: unknown hardware rev\n", 454 sc->sc_dev.dv_xname); 455 break; 456 } 457 458 return; 459 } 460 461 /* 462 * Send the NIC a command via the command ring. 463 */ 464 static void ti_cmd(sc, cmd) 465 struct ti_softc *sc; 466 struct ti_cmd_desc *cmd; 467 { 468 u_int32_t index; 469 470 index = sc->ti_cmd_saved_prodidx; 471 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 472 TI_INC(index, TI_CMD_RING_CNT); 473 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 474 sc->ti_cmd_saved_prodidx = index; 475 476 return; 477 } 478 479 /* 480 * Send the NIC an extended command. The 'len' parameter specifies the 481 * number of command slots to include after the initial command. 482 */ 483 static void ti_cmd_ext(sc, cmd, arg, len) 484 struct ti_softc *sc; 485 struct ti_cmd_desc *cmd; 486 caddr_t arg; 487 int len; 488 { 489 u_int32_t index; 490 int i; 491 492 index = sc->ti_cmd_saved_prodidx; 493 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 494 TI_INC(index, TI_CMD_RING_CNT); 495 for (i = 0; i < len; i++) { 496 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 497 *(u_int32_t *)(&arg[i * 4])); 498 TI_INC(index, TI_CMD_RING_CNT); 499 } 500 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 501 sc->ti_cmd_saved_prodidx = index; 502 503 return; 504 } 505 506 /* 507 * Handle events that have triggered interrupts. 508 */ 509 static void ti_handle_events(sc) 510 struct ti_softc *sc; 511 { 512 struct ti_event_desc *e; 513 514 if (sc->ti_rdata->ti_event_ring == NULL) 515 return; 516 517 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 518 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 519 switch(e->ti_event) { 520 case TI_EV_LINKSTAT_CHANGED: 521 sc->ti_linkstat = e->ti_code; 522 if (e->ti_code == TI_EV_CODE_LINK_UP) 523 printf("%s: 10/100 link up\n", 524 sc->sc_dev.dv_xname); 525 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 526 printf("%s: gigabit link up\n", 527 sc->sc_dev.dv_xname); 528 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 529 printf("%s: link down\n", 530 sc->sc_dev.dv_xname); 531 break; 532 case TI_EV_ERROR: 533 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 534 printf("%s: invalid command\n", 535 sc->sc_dev.dv_xname); 536 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 537 printf("%s: unknown command\n", 538 sc->sc_dev.dv_xname); 539 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 540 printf("%s: bad config data\n", 541 sc->sc_dev.dv_xname); 542 break; 543 case TI_EV_FIRMWARE_UP: 544 ti_init2(sc); 545 break; 546 case TI_EV_STATS_UPDATED: 547 ti_stats_update(sc); 548 break; 549 case TI_EV_RESET_JUMBO_RING: 550 case TI_EV_MCAST_UPDATED: 551 /* Who cares. */ 552 break; 553 default: 554 printf("%s: unknown event: %d\n", 555 sc->sc_dev.dv_xname, e->ti_event); 556 break; 557 } 558 /* Advance the consumer index. */ 559 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 560 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 561 } 562 563 return; 564 } 565 566 /* 567 * Memory management for the jumbo receive ring is a pain in the 568 * butt. We need to allocate at least 9018 bytes of space per frame, 569 * _and_ it has to be contiguous (unless you use the extended 570 * jumbo descriptor format). Using malloc() all the time won't 571 * work: malloc() allocates memory in powers of two, which means we 572 * would end up wasting a considerable amount of space by allocating 573 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 574 * to do our own memory management. 575 * 576 * The driver needs to allocate a contiguous chunk of memory at boot 577 * time. We then chop this up ourselves into 9K pieces and use them 578 * as external mbuf storage. 579 * 580 * One issue here is how much memory to allocate. The jumbo ring has 581 * 256 slots in it, but at 9K per slot than can consume over 2MB of 582 * RAM. This is a bit much, especially considering we also need 583 * RAM for the standard ring and mini ring (on the Tigon 2). To 584 * save space, we only actually allocate enough memory for 64 slots 585 * by default, which works out to between 500 and 600K. This can 586 * be tuned by changing a #define in if_tireg.h. 587 */ 588 589 static int ti_alloc_jumbo_mem(sc) 590 struct ti_softc *sc; 591 { 592 caddr_t ptr; 593 int i; 594 struct ti_jpool_entry *entry; 595 bus_dma_segment_t dmaseg; 596 int error, dmanseg; 597 598 /* Grab a big chunk o' storage. */ 599 if ((error = bus_dmamem_alloc(sc->sc_dmat, 600 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 601 BUS_DMA_NOWAIT)) != 0) { 602 printf("%s: can't allocate jumbo buffer, error = %d\n", 603 sc->sc_dev.dv_xname, error); 604 return (error); 605 } 606 607 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 608 TI_JMEM, (caddr_t *)&sc->ti_cdata.ti_jumbo_buf, 609 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 610 printf("%s: can't map jumbo buffer, error = %d\n", 611 sc->sc_dev.dv_xname, error); 612 return (error); 613 } 614 615 if ((error = bus_dmamap_create(sc->sc_dmat, 616 TI_JMEM, 1, 617 TI_JMEM, 0, BUS_DMA_NOWAIT, 618 &sc->jumbo_dmamap)) != 0) { 619 printf("%s: can't create jumbo buffer DMA map, error = %d\n", 620 sc->sc_dev.dv_xname, error); 621 return (error); 622 } 623 624 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 625 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 626 BUS_DMA_NOWAIT)) != 0) { 627 printf("%s: can't load jumbo buffer DMA map, error = %d\n", 628 sc->sc_dev.dv_xname, error); 629 return (error); 630 } 631 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 632 633 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 634 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 635 636 /* 637 * Now divide it up into 9K pieces and save the addresses 638 * in an array. 639 */ 640 ptr = sc->ti_cdata.ti_jumbo_buf; 641 for (i = 0; i < TI_JSLOTS; i++) { 642 sc->ti_cdata.ti_jslots[i] = ptr; 643 ptr += TI_JLEN; 644 entry = malloc(sizeof(struct ti_jpool_entry), 645 M_DEVBUF, M_NOWAIT); 646 if (entry == NULL) { 647 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 648 sc->ti_cdata.ti_jumbo_buf = NULL; 649 printf("%s: no memory for jumbo " 650 "buffer queue!\n", sc->sc_dev.dv_xname); 651 return(ENOBUFS); 652 } 653 entry->slot = i; 654 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 655 jpool_entries); 656 } 657 658 return(0); 659 } 660 661 /* 662 * Allocate a jumbo buffer. 663 */ 664 static void *ti_jalloc(sc) 665 struct ti_softc *sc; 666 { 667 struct ti_jpool_entry *entry; 668 669 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 670 671 if (entry == NULL) { 672 printf("%s: no free jumbo buffers\n", sc->sc_dev.dv_xname); 673 return(NULL); 674 } 675 676 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 677 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 678 return(sc->ti_cdata.ti_jslots[entry->slot]); 679 } 680 681 /* 682 * Release a jumbo buffer. 683 */ 684 static void ti_jfree(m, buf, size, arg) 685 struct mbuf *m; 686 caddr_t buf; 687 size_t size; 688 void *arg; 689 { 690 struct ti_softc *sc; 691 int i, s; 692 struct ti_jpool_entry *entry; 693 694 /* Extract the softc struct pointer. */ 695 sc = (struct ti_softc *)arg; 696 697 if (sc == NULL) 698 panic("ti_jfree: didn't get softc pointer!"); 699 700 /* calculate the slot this buffer belongs to */ 701 702 i = ((caddr_t)buf 703 - (caddr_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 704 705 if ((i < 0) || (i >= TI_JSLOTS)) 706 panic("ti_jfree: asked to free buffer that we don't manage!"); 707 708 s = splvm(); 709 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 710 if (entry == NULL) 711 panic("ti_jfree: buffer not in use!"); 712 entry->slot = i; 713 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 714 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 715 716 if (__predict_true(m != NULL)) 717 pool_cache_put(&mbpool_cache, m); 718 splx(s); 719 } 720 721 722 /* 723 * Intialize a standard receive ring descriptor. 724 */ 725 static int ti_newbuf_std(sc, i, m, dmamap) 726 struct ti_softc *sc; 727 int i; 728 struct mbuf *m; 729 bus_dmamap_t dmamap; /* required if (m != NULL) */ 730 { 731 struct mbuf *m_new = NULL; 732 struct ti_rx_desc *r; 733 int error; 734 735 if (dmamap == NULL) { 736 /* if (m) panic() */ 737 738 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 739 MCLBYTES, 0, BUS_DMA_NOWAIT, 740 &dmamap)) != 0) { 741 printf("%s: can't create recv map, error = %d\n", 742 sc->sc_dev.dv_xname, error); 743 return(ENOMEM); 744 } 745 } 746 sc->std_dmamap[i] = dmamap; 747 748 if (m == NULL) { 749 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 750 if (m_new == NULL) { 751 printf("%s: mbuf allocation failed " 752 "-- packet dropped!\n", sc->sc_dev.dv_xname); 753 return(ENOBUFS); 754 } 755 756 MCLGET(m_new, M_DONTWAIT); 757 if (!(m_new->m_flags & M_EXT)) { 758 printf("%s: cluster allocation failed " 759 "-- packet dropped!\n", sc->sc_dev.dv_xname); 760 m_freem(m_new); 761 return(ENOBUFS); 762 } 763 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 764 m_adj(m_new, ETHER_ALIGN); 765 766 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 767 mtod(m_new, caddr_t), m_new->m_len, NULL, 768 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 769 printf("%s: can't load recv map, error = %d\n", 770 sc->sc_dev.dv_xname, error); 771 return (ENOMEM); 772 } 773 } else { 774 m_new = m; 775 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 776 m_new->m_data = m_new->m_ext.ext_buf; 777 m_adj(m_new, ETHER_ALIGN); 778 779 /* reuse the dmamap */ 780 } 781 782 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 783 r = &sc->ti_rdata->ti_rx_std_ring[i]; 784 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 785 r->ti_type = TI_BDTYPE_RECV_BD; 786 r->ti_flags = 0; 787 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 788 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 789 if (sc->ethercom.ec_if.if_capenable & 790 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 791 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 792 r->ti_len = m_new->m_len; /* == ds_len */ 793 r->ti_idx = i; 794 795 return(0); 796 } 797 798 /* 799 * Intialize a mini receive ring descriptor. This only applies to 800 * the Tigon 2. 801 */ 802 static int ti_newbuf_mini(sc, i, m, dmamap) 803 struct ti_softc *sc; 804 int i; 805 struct mbuf *m; 806 bus_dmamap_t dmamap; /* required if (m != NULL) */ 807 { 808 struct mbuf *m_new = NULL; 809 struct ti_rx_desc *r; 810 int error; 811 812 if (dmamap == NULL) { 813 /* if (m) panic() */ 814 815 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 816 MHLEN, 0, BUS_DMA_NOWAIT, 817 &dmamap)) != 0) { 818 printf("%s: can't create recv map, error = %d\n", 819 sc->sc_dev.dv_xname, error); 820 return(ENOMEM); 821 } 822 } 823 sc->mini_dmamap[i] = dmamap; 824 825 if (m == NULL) { 826 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 827 if (m_new == NULL) { 828 printf("%s: mbuf allocation failed " 829 "-- packet dropped!\n", sc->sc_dev.dv_xname); 830 return(ENOBUFS); 831 } 832 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 833 m_adj(m_new, ETHER_ALIGN); 834 835 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 836 mtod(m_new, caddr_t), m_new->m_len, NULL, 837 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 838 printf("%s: can't load recv map, error = %d\n", 839 sc->sc_dev.dv_xname, error); 840 return (ENOMEM); 841 } 842 } else { 843 m_new = m; 844 m_new->m_data = m_new->m_pktdat; 845 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 846 m_adj(m_new, ETHER_ALIGN); 847 848 /* reuse the dmamap */ 849 } 850 851 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 852 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 853 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 854 r->ti_type = TI_BDTYPE_RECV_BD; 855 r->ti_flags = TI_BDFLAG_MINI_RING; 856 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 857 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 858 if (sc->ethercom.ec_if.if_capenable & 859 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 860 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 861 r->ti_len = m_new->m_len; /* == ds_len */ 862 r->ti_idx = i; 863 864 return(0); 865 } 866 867 /* 868 * Initialize a jumbo receive ring descriptor. This allocates 869 * a jumbo buffer from the pool managed internally by the driver. 870 */ 871 static int ti_newbuf_jumbo(sc, i, m) 872 struct ti_softc *sc; 873 int i; 874 struct mbuf *m; 875 { 876 struct mbuf *m_new = NULL; 877 struct ti_rx_desc *r; 878 879 if (m == NULL) { 880 caddr_t *buf = NULL; 881 882 /* Allocate the mbuf. */ 883 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 884 if (m_new == NULL) { 885 printf("%s: mbuf allocation failed " 886 "-- packet dropped!\n", sc->sc_dev.dv_xname); 887 return(ENOBUFS); 888 } 889 890 /* Allocate the jumbo buffer */ 891 buf = ti_jalloc(sc); 892 if (buf == NULL) { 893 m_freem(m_new); 894 printf("%s: jumbo allocation failed " 895 "-- packet dropped!\n", sc->sc_dev.dv_xname); 896 return(ENOBUFS); 897 } 898 899 /* Attach the buffer to the mbuf. */ 900 MEXTADD(m_new, (void *)buf, ETHER_MAX_LEN_JUMBO, 901 M_DEVBUF, ti_jfree, sc); 902 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 903 } else { 904 m_new = m; 905 m_new->m_data = m_new->m_ext.ext_buf; 906 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 907 } 908 909 m_adj(m_new, ETHER_ALIGN); 910 /* Set up the descriptor. */ 911 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 912 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 913 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 914 ((caddr_t)mtod(m_new, caddr_t) 915 - (caddr_t)sc->ti_cdata.ti_jumbo_buf); 916 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 917 r->ti_flags = TI_BDFLAG_JUMBO_RING; 918 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 919 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 920 if (sc->ethercom.ec_if.if_capenable & 921 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 922 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 923 r->ti_len = m_new->m_len; 924 r->ti_idx = i; 925 926 return(0); 927 } 928 929 /* 930 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 931 * that's 1MB or memory, which is a lot. For now, we fill only the first 932 * 256 ring entries and hope that our CPU is fast enough to keep up with 933 * the NIC. 934 */ 935 static int ti_init_rx_ring_std(sc) 936 struct ti_softc *sc; 937 { 938 int i; 939 struct ti_cmd_desc cmd; 940 941 for (i = 0; i < TI_SSLOTS; i++) { 942 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 943 return(ENOBUFS); 944 }; 945 946 TI_UPDATE_STDPROD(sc, i - 1); 947 sc->ti_std = i - 1; 948 949 return(0); 950 } 951 952 static void ti_free_rx_ring_std(sc) 953 struct ti_softc *sc; 954 { 955 int i; 956 957 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 958 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 959 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 960 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 961 962 /* if (sc->std_dmamap[i] == 0) panic() */ 963 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 964 sc->std_dmamap[i] = 0; 965 } 966 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 967 sizeof(struct ti_rx_desc)); 968 } 969 970 return; 971 } 972 973 static int ti_init_rx_ring_jumbo(sc) 974 struct ti_softc *sc; 975 { 976 int i; 977 struct ti_cmd_desc cmd; 978 979 for (i = 0; i < (TI_JSLOTS - 20); i++) { 980 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 981 return(ENOBUFS); 982 }; 983 984 TI_UPDATE_JUMBOPROD(sc, i - 1); 985 sc->ti_jumbo = i - 1; 986 987 return(0); 988 } 989 990 static void ti_free_rx_ring_jumbo(sc) 991 struct ti_softc *sc; 992 { 993 int i; 994 995 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 996 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 997 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 998 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 999 } 1000 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 1001 sizeof(struct ti_rx_desc)); 1002 } 1003 1004 return; 1005 } 1006 1007 static int ti_init_rx_ring_mini(sc) 1008 struct ti_softc *sc; 1009 { 1010 int i; 1011 1012 for (i = 0; i < TI_MSLOTS; i++) { 1013 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 1014 return(ENOBUFS); 1015 }; 1016 1017 TI_UPDATE_MINIPROD(sc, i - 1); 1018 sc->ti_mini = i - 1; 1019 1020 return(0); 1021 } 1022 1023 static void ti_free_rx_ring_mini(sc) 1024 struct ti_softc *sc; 1025 { 1026 int i; 1027 1028 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1029 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1030 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1031 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1032 1033 /* if (sc->mini_dmamap[i] == 0) panic() */ 1034 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1035 sc->mini_dmamap[i] = 0; 1036 } 1037 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1038 sizeof(struct ti_rx_desc)); 1039 } 1040 1041 return; 1042 } 1043 1044 static void ti_free_tx_ring(sc) 1045 struct ti_softc *sc; 1046 { 1047 int i; 1048 struct txdmamap_pool_entry *dma; 1049 1050 if (sc->ti_rdata->ti_tx_ring == NULL) 1051 return; 1052 1053 for (i = 0; i < TI_TX_RING_CNT; i++) { 1054 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1055 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1056 sc->ti_cdata.ti_tx_chain[i] = NULL; 1057 1058 /* if (sc->txdma[i] == 0) panic() */ 1059 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1060 link); 1061 sc->txdma[i] = 0; 1062 } 1063 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1064 sizeof(struct ti_tx_desc)); 1065 } 1066 1067 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1068 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1069 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1070 free(dma, M_DEVBUF); 1071 } 1072 1073 return; 1074 } 1075 1076 static int ti_init_tx_ring(sc) 1077 struct ti_softc *sc; 1078 { 1079 int i, error; 1080 bus_dmamap_t dmamap; 1081 struct txdmamap_pool_entry *dma; 1082 1083 sc->ti_txcnt = 0; 1084 sc->ti_tx_saved_considx = 0; 1085 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1086 1087 SIMPLEQ_INIT(&sc->txdma_list); 1088 for (i = 0; i < TI_RSLOTS; i++) { 1089 /* I've seen mbufs with 30 fragments. */ 1090 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 1091 40, ETHER_MAX_LEN_JUMBO, 0, 1092 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1093 printf("%s: can't create tx map, error = %d\n", 1094 sc->sc_dev.dv_xname, error); 1095 return(ENOMEM); 1096 } 1097 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1098 if (!dma) { 1099 printf("%s: can't alloc txdmamap_pool_entry\n", 1100 sc->sc_dev.dv_xname); 1101 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1102 return (ENOMEM); 1103 } 1104 dma->dmamap = dmamap; 1105 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1106 } 1107 1108 return(0); 1109 } 1110 1111 /* 1112 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1113 * but we have to support the old way too so that Tigon 1 cards will 1114 * work. 1115 */ 1116 void ti_add_mcast(sc, addr) 1117 struct ti_softc *sc; 1118 struct ether_addr *addr; 1119 { 1120 struct ti_cmd_desc cmd; 1121 u_int16_t *m; 1122 u_int32_t ext[2] = {0, 0}; 1123 1124 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1125 1126 switch(sc->ti_hwrev) { 1127 case TI_HWREV_TIGON: 1128 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1129 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1130 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1131 break; 1132 case TI_HWREV_TIGON_II: 1133 ext[0] = htons(m[0]); 1134 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1135 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1136 break; 1137 default: 1138 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1139 break; 1140 } 1141 1142 return; 1143 } 1144 1145 void ti_del_mcast(sc, addr) 1146 struct ti_softc *sc; 1147 struct ether_addr *addr; 1148 { 1149 struct ti_cmd_desc cmd; 1150 u_int16_t *m; 1151 u_int32_t ext[2] = {0, 0}; 1152 1153 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1154 1155 switch(sc->ti_hwrev) { 1156 case TI_HWREV_TIGON: 1157 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1158 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1159 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1160 break; 1161 case TI_HWREV_TIGON_II: 1162 ext[0] = htons(m[0]); 1163 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1164 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1165 break; 1166 default: 1167 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1168 break; 1169 } 1170 1171 return; 1172 } 1173 1174 /* 1175 * Configure the Tigon's multicast address filter. 1176 * 1177 * The actual multicast table management is a bit of a pain, thanks to 1178 * slight brain damage on the part of both Alteon and us. With our 1179 * multicast code, we are only alerted when the multicast address table 1180 * changes and at that point we only have the current list of addresses: 1181 * we only know the current state, not the previous state, so we don't 1182 * actually know what addresses were removed or added. The firmware has 1183 * state, but we can't get our grubby mits on it, and there is no 'delete 1184 * all multicast addresses' command. Hence, we have to maintain our own 1185 * state so we know what addresses have been programmed into the NIC at 1186 * any given time. 1187 */ 1188 static void ti_setmulti(sc) 1189 struct ti_softc *sc; 1190 { 1191 struct ifnet *ifp; 1192 struct ti_cmd_desc cmd; 1193 struct ti_mc_entry *mc; 1194 u_int32_t intrs; 1195 struct ether_multi *enm; 1196 struct ether_multistep step; 1197 1198 ifp = &sc->ethercom.ec_if; 1199 1200 /* Disable interrupts. */ 1201 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1202 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1203 1204 /* First, zot all the existing filters. */ 1205 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1206 ti_del_mcast(sc, &mc->mc_addr); 1207 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1208 free(mc, M_DEVBUF); 1209 } 1210 1211 /* 1212 * Remember all multicast addresses so that we can delete them 1213 * later. Punt if there is a range of addresses or memory shortage. 1214 */ 1215 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1216 while (enm != NULL) { 1217 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1218 ETHER_ADDR_LEN) != 0) 1219 goto allmulti; 1220 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1221 M_NOWAIT)) == NULL) 1222 goto allmulti; 1223 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1224 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1225 ETHER_NEXT_MULTI(step, enm); 1226 } 1227 1228 /* Accept only programmed multicast addresses */ 1229 ifp->if_flags &= ~IFF_ALLMULTI; 1230 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1231 1232 /* Now program new ones. */ 1233 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1234 ti_add_mcast(sc, &mc->mc_addr); 1235 1236 /* Re-enable interrupts. */ 1237 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1238 1239 return; 1240 1241 allmulti: 1242 /* No need to keep individual multicast addresses */ 1243 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1244 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1245 free(mc, M_DEVBUF); 1246 } 1247 1248 /* Accept all multicast addresses */ 1249 ifp->if_flags |= IFF_ALLMULTI; 1250 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1251 1252 /* Re-enable interrupts. */ 1253 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1254 } 1255 1256 /* 1257 * Check to see if the BIOS has configured us for a 64 bit slot when 1258 * we aren't actually in one. If we detect this condition, we can work 1259 * around it on the Tigon 2 by setting a bit in the PCI state register, 1260 * but for the Tigon 1 we must give up and abort the interface attach. 1261 */ 1262 static int ti_64bitslot_war(sc) 1263 struct ti_softc *sc; 1264 { 1265 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1266 CSR_WRITE_4(sc, 0x600, 0); 1267 CSR_WRITE_4(sc, 0x604, 0); 1268 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1269 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1270 if (sc->ti_hwrev == TI_HWREV_TIGON) 1271 return(EINVAL); 1272 else { 1273 TI_SETBIT(sc, TI_PCI_STATE, 1274 TI_PCISTATE_32BIT_BUS); 1275 return(0); 1276 } 1277 } 1278 } 1279 1280 return(0); 1281 } 1282 1283 /* 1284 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1285 * self-test results. 1286 */ 1287 static int ti_chipinit(sc) 1288 struct ti_softc *sc; 1289 { 1290 u_int32_t cacheline; 1291 u_int32_t pci_writemax = 0; 1292 u_int32_t rev; 1293 1294 /* Initialize link to down state. */ 1295 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1296 1297 /* Set endianness before we access any non-PCI registers. */ 1298 #if BYTE_ORDER == BIG_ENDIAN 1299 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1300 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1301 #else 1302 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1303 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1304 #endif 1305 1306 /* Check the ROM failed bit to see if self-tests passed. */ 1307 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1308 printf("%s: board self-diagnostics failed!\n", 1309 sc->sc_dev.dv_xname); 1310 return(ENODEV); 1311 } 1312 1313 /* Halt the CPU. */ 1314 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1315 1316 /* Figure out the hardware revision. */ 1317 rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK; 1318 switch(rev) { 1319 case TI_REV_TIGON_I: 1320 sc->ti_hwrev = TI_HWREV_TIGON; 1321 break; 1322 case TI_REV_TIGON_II: 1323 sc->ti_hwrev = TI_HWREV_TIGON_II; 1324 break; 1325 default: 1326 printf("%s: unsupported chip revision 0x%x\n", 1327 sc->sc_dev.dv_xname, rev); 1328 return(ENODEV); 1329 } 1330 1331 /* Do special setup for Tigon 2. */ 1332 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1333 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1334 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1335 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1336 } 1337 1338 /* Set up the PCI state register. */ 1339 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1340 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1341 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1342 } 1343 1344 /* Clear the read/write max DMA parameters. */ 1345 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1346 TI_PCISTATE_READ_MAXDMA)); 1347 1348 /* Get cache line size. */ 1349 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1350 1351 /* 1352 * If the system has set enabled the PCI memory write 1353 * and invalidate command in the command register, set 1354 * the write max parameter accordingly. This is necessary 1355 * to use MWI with the Tigon 2. 1356 */ 1357 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1358 & PCI_COMMAND_INVALIDATE_ENABLE) { 1359 switch(cacheline) { 1360 case 1: 1361 case 4: 1362 case 8: 1363 case 16: 1364 case 32: 1365 case 64: 1366 break; 1367 default: 1368 /* Disable PCI memory write and invalidate. */ 1369 if (bootverbose) 1370 printf("%s: cache line size %d not " 1371 "supported; disabling PCI MWI\n", 1372 sc->sc_dev.dv_xname, cacheline); 1373 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1374 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1375 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1376 break; 1377 } 1378 } 1379 1380 #ifdef __brokenalpha__ 1381 /* 1382 * From the Alteon sample driver: 1383 * Must insure that we do not cross an 8K (bytes) boundary 1384 * for DMA reads. Our highest limit is 1K bytes. This is a 1385 * restriction on some ALPHA platforms with early revision 1386 * 21174 PCI chipsets, such as the AlphaPC 164lx 1387 */ 1388 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1389 #else 1390 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1391 #endif 1392 1393 /* This sets the min dma param all the way up (0xff). */ 1394 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1395 1396 /* Configure DMA variables. */ 1397 #if BYTE_ORDER == BIG_ENDIAN 1398 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1399 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1400 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1401 TI_OPMODE_DONT_FRAG_JUMBO); 1402 #else 1403 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1404 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1405 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1406 #endif 1407 1408 /* 1409 * Only allow 1 DMA channel to be active at a time. 1410 * I don't think this is a good idea, but without it 1411 * the firmware racks up lots of nicDmaReadRingFull 1412 * errors. 1413 * Incompatible with hardware assisted checksums. 1414 */ 1415 if ((sc->ethercom.ec_if.if_capenable & 1416 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4|IFCAP_CSUM_IPv4)) == 0) 1417 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1418 1419 /* Recommended settings from Tigon manual. */ 1420 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1421 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1422 1423 if (ti_64bitslot_war(sc)) { 1424 printf("%s: bios thinks we're in a 64 bit slot, " 1425 "but we aren't", sc->sc_dev.dv_xname); 1426 return(EINVAL); 1427 } 1428 1429 return(0); 1430 } 1431 1432 /* 1433 * Initialize the general information block and firmware, and 1434 * start the CPU(s) running. 1435 */ 1436 static int ti_gibinit(sc) 1437 struct ti_softc *sc; 1438 { 1439 struct ti_rcb *rcb; 1440 int i; 1441 struct ifnet *ifp; 1442 1443 ifp = &sc->ethercom.ec_if; 1444 1445 /* Disable interrupts for now. */ 1446 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1447 1448 /* Tell the chip where to find the general information block. */ 1449 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1450 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1451 1452 /* Load the firmware into SRAM. */ 1453 ti_loadfw(sc); 1454 1455 /* Set up the contents of the general info and ring control blocks. */ 1456 1457 /* Set up the event ring and producer pointer. */ 1458 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1459 1460 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1461 rcb->ti_flags = 0; 1462 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1463 TI_CDEVPRODADDR(sc); 1464 1465 sc->ti_ev_prodidx.ti_idx = 0; 1466 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1467 sc->ti_ev_saved_considx = 0; 1468 1469 /* Set up the command ring and producer mailbox. */ 1470 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1471 1472 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1473 rcb->ti_flags = 0; 1474 rcb->ti_max_len = 0; 1475 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1476 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1477 } 1478 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1479 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1480 sc->ti_cmd_saved_prodidx = 0; 1481 1482 /* 1483 * Assign the address of the stats refresh buffer. 1484 * We re-use the current stats buffer for this to 1485 * conserve memory. 1486 */ 1487 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1488 TI_CDSTATSADDR(sc); 1489 1490 /* Set up the standard receive ring. */ 1491 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1492 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1493 rcb->ti_max_len = ETHER_MAX_LEN; 1494 rcb->ti_flags = 0; 1495 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1496 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1497 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1498 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1499 if (sc->ethercom.ec_nvlans != 0) 1500 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1501 1502 /* Set up the jumbo receive ring. */ 1503 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1504 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1505 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1506 rcb->ti_flags = 0; 1507 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1508 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1509 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1510 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1511 if (sc->ethercom.ec_nvlans != 0) 1512 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1513 1514 /* 1515 * Set up the mini ring. Only activated on the 1516 * Tigon 2 but the slot in the config block is 1517 * still there on the Tigon 1. 1518 */ 1519 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1520 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1521 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1522 if (sc->ti_hwrev == TI_HWREV_TIGON) 1523 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1524 else 1525 rcb->ti_flags = 0; 1526 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1527 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1528 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1529 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1530 if (sc->ethercom.ec_nvlans != 0) 1531 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1532 1533 /* 1534 * Set up the receive return ring. 1535 */ 1536 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1537 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1538 rcb->ti_flags = 0; 1539 rcb->ti_max_len = TI_RETURN_RING_CNT; 1540 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1541 TI_CDRTNPRODADDR(sc); 1542 1543 /* 1544 * Set up the tx ring. Note: for the Tigon 2, we have the option 1545 * of putting the transmit ring in the host's address space and 1546 * letting the chip DMA it instead of leaving the ring in the NIC's 1547 * memory and accessing it through the shared memory region. We 1548 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1549 * so we have to revert to the shared memory scheme if we detect 1550 * a Tigon 1 chip. 1551 */ 1552 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1553 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1554 sc->ti_tx_ring_nic = 1555 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1556 } 1557 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1558 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1559 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1560 if (sc->ti_hwrev == TI_HWREV_TIGON) 1561 rcb->ti_flags = 0; 1562 else 1563 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1564 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1565 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1566 /* 1567 * When we get the packet, there is a pseudo-header seed already 1568 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1569 * compute the pseudo-header checksum again! 1570 */ 1571 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1572 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM| 1573 TI_RCB_FLAG_NO_PHDR_CKSUM; 1574 if (sc->ethercom.ec_nvlans != 0) 1575 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1576 rcb->ti_max_len = TI_TX_RING_CNT; 1577 if (sc->ti_hwrev == TI_HWREV_TIGON) 1578 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1579 else 1580 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1581 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1582 TI_CDTXCONSADDR(sc); 1583 1584 /* 1585 * We're done frobbing the General Information Block. Sync 1586 * it. Note we take care of the first stats sync here, as 1587 * well. 1588 */ 1589 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1590 1591 /* Set up tuneables */ 1592 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1593 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1594 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1595 (sc->ti_rx_coal_ticks / 10)); 1596 else 1597 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1598 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1599 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1600 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1601 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1602 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1603 1604 /* Turn interrupts on. */ 1605 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1606 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1607 1608 /* Start CPU. */ 1609 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1610 1611 return(0); 1612 } 1613 1614 /* 1615 * look for id in the device list, returning the first match 1616 */ 1617 static const struct ti_type * 1618 ti_type_match(pa) 1619 struct pci_attach_args *pa; 1620 { 1621 const struct ti_type *t; 1622 1623 t = ti_devs; 1624 while(t->ti_name != NULL) { 1625 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1626 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1627 return (t); 1628 } 1629 t++; 1630 } 1631 1632 return(NULL); 1633 } 1634 1635 /* 1636 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1637 * against our list and return its name if we find a match. 1638 */ 1639 static int ti_probe(parent, match, aux) 1640 struct device *parent; 1641 struct cfdata *match; 1642 void *aux; 1643 { 1644 struct pci_attach_args *pa = aux; 1645 const struct ti_type *t; 1646 1647 t = ti_type_match(pa); 1648 1649 return((t == NULL) ? 0 : 1); 1650 } 1651 1652 static void ti_attach(parent, self, aux) 1653 struct device *parent, *self; 1654 void *aux; 1655 { 1656 u_int32_t command; 1657 struct ifnet *ifp; 1658 struct ti_softc *sc; 1659 u_char eaddr[ETHER_ADDR_LEN]; 1660 struct pci_attach_args *pa = aux; 1661 pci_chipset_tag_t pc = pa->pa_pc; 1662 pci_intr_handle_t ih; 1663 const char *intrstr = NULL; 1664 bus_dma_segment_t dmaseg; 1665 int error, dmanseg, nolinear; 1666 const struct ti_type *t; 1667 1668 t = ti_type_match(pa); 1669 if (t == NULL) { 1670 printf("ti_attach: were did the card go ?\n"); 1671 return; 1672 } 1673 1674 printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class)); 1675 1676 sc = (struct ti_softc *)self; 1677 1678 /* 1679 * Map control/status registers. 1680 */ 1681 nolinear = 0; 1682 if (pci_mapreg_map(pa, 0x10, 1683 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1684 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1685 NULL, NULL)) { 1686 nolinear = 1; 1687 if (pci_mapreg_map(pa, 0x10, 1688 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1689 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1690 printf(": can't map memory space\n"); 1691 return; 1692 } 1693 } 1694 if (nolinear == 0) 1695 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1696 else 1697 sc->ti_vhandle = NULL; 1698 1699 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1700 command |= PCI_COMMAND_MASTER_ENABLE; 1701 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1702 1703 /* Allocate interrupt */ 1704 if (pci_intr_map(pa, &ih)) { 1705 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 1706 return; 1707 } 1708 intrstr = pci_intr_string(pc, ih); 1709 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1710 if (sc->sc_ih == NULL) { 1711 printf("%s: couldn't establish interrupt", 1712 sc->sc_dev.dv_xname); 1713 if (intrstr != NULL) 1714 printf(" at %s", intrstr); 1715 printf("\n"); 1716 return; 1717 } 1718 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1719 /* 1720 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1721 * doing do could allow DMA to corrupt kernel memory during the 1722 * reboot before the driver initializes. 1723 */ 1724 (void) shutdownhook_establish(ti_shutdown, sc); 1725 1726 if (ti_chipinit(sc)) { 1727 printf("%s: chip initialization failed\n", self->dv_xname); 1728 goto fail2; 1729 } 1730 1731 /* 1732 * Deal with some chip diffrences. 1733 */ 1734 switch (sc->ti_hwrev) { 1735 case TI_HWREV_TIGON: 1736 sc->sc_tx_encap = ti_encap_tigon1; 1737 sc->sc_tx_eof = ti_txeof_tigon1; 1738 if (nolinear == 1) 1739 printf("%s: memory space not mapped linear\n", 1740 self->dv_xname); 1741 break; 1742 1743 case TI_HWREV_TIGON_II: 1744 sc->sc_tx_encap = ti_encap_tigon2; 1745 sc->sc_tx_eof = ti_txeof_tigon2; 1746 break; 1747 1748 default: 1749 printf("%s: Unknown chip version: %d\n", self->dv_xname, 1750 sc->ti_hwrev); 1751 goto fail2; 1752 } 1753 1754 /* Zero out the NIC's on-board SRAM. */ 1755 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1756 1757 /* Init again -- zeroing memory may have clobbered some registers. */ 1758 if (ti_chipinit(sc)) { 1759 printf("%s: chip initialization failed\n", self->dv_xname); 1760 goto fail2; 1761 } 1762 1763 /* 1764 * Get station address from the EEPROM. Note: the manual states 1765 * that the MAC address is at offset 0x8c, however the data is 1766 * stored as two longwords (since that's how it's loaded into 1767 * the NIC). This means the MAC address is actually preceded 1768 * by two zero bytes. We need to skip over those. 1769 */ 1770 if (ti_read_eeprom(sc, (caddr_t)&eaddr, 1771 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1772 printf("%s: failed to read station address\n", self->dv_xname); 1773 goto fail2; 1774 } 1775 1776 /* 1777 * A Tigon chip was detected. Inform the world. 1778 */ 1779 printf("%s: Ethernet address: %s\n", self->dv_xname, 1780 ether_sprintf(eaddr)); 1781 1782 sc->sc_dmat = pa->pa_dmat; 1783 1784 /* Allocate the general information block and ring buffers. */ 1785 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1786 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1787 BUS_DMA_NOWAIT)) != 0) { 1788 printf("%s: can't allocate ring buffer, error = %d\n", 1789 sc->sc_dev.dv_xname, error); 1790 goto fail2; 1791 } 1792 1793 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1794 sizeof(struct ti_ring_data), (caddr_t *)&sc->ti_rdata, 1795 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1796 printf("%s: can't map ring buffer, error = %d\n", 1797 sc->sc_dev.dv_xname, error); 1798 goto fail2; 1799 } 1800 1801 if ((error = bus_dmamap_create(sc->sc_dmat, 1802 sizeof(struct ti_ring_data), 1, 1803 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1804 &sc->info_dmamap)) != 0) { 1805 printf("%s: can't create ring buffer DMA map, error = %d\n", 1806 sc->sc_dev.dv_xname, error); 1807 goto fail2; 1808 } 1809 1810 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1811 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1812 BUS_DMA_NOWAIT)) != 0) { 1813 printf("%s: can't load ring buffer DMA map, error = %d\n", 1814 sc->sc_dev.dv_xname, error); 1815 goto fail2; 1816 } 1817 1818 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1819 1820 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1821 1822 /* Try to allocate memory for jumbo buffers. */ 1823 if (ti_alloc_jumbo_mem(sc)) { 1824 printf("%s: jumbo buffer allocation failed\n", self->dv_xname); 1825 goto fail2; 1826 } 1827 1828 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1829 1830 /* 1831 * We really need a better way to tell a 1000baseT card 1832 * from a 1000baseSX one, since in theory there could be 1833 * OEMed 1000baseT cards from lame vendors who aren't 1834 * clever enough to change the PCI ID. For the moment 1835 * though, the AceNIC is the only copper card available. 1836 */ 1837 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1838 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1839 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1840 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1841 sc->ti_copper = 1; 1842 else 1843 sc->ti_copper = 0; 1844 1845 /* Set default tuneable values. */ 1846 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1847 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1848 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1849 sc->ti_rx_max_coal_bds = 64; 1850 sc->ti_tx_max_coal_bds = 128; 1851 sc->ti_tx_buf_ratio = 21; 1852 1853 /* Set up ifnet structure */ 1854 ifp = &sc->ethercom.ec_if; 1855 ifp->if_softc = sc; 1856 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1857 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1858 ifp->if_ioctl = ti_ioctl; 1859 ifp->if_start = ti_start; 1860 ifp->if_watchdog = ti_watchdog; 1861 IFQ_SET_READY(&ifp->if_snd); 1862 1863 #if 0 1864 /* 1865 * XXX This is not really correct -- we don't necessarily 1866 * XXX want to queue up as many as we can transmit at the 1867 * XXX upper layer like that. Someone with a board should 1868 * XXX check to see how this affects performance. 1869 */ 1870 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1871 #endif 1872 1873 /* 1874 * We can support 802.1Q VLAN-sized frames. 1875 */ 1876 sc->ethercom.ec_capabilities |= 1877 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1878 1879 /* 1880 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1881 */ 1882 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1883 IFCAP_CSUM_UDPv4; 1884 1885 /* Set up ifmedia support. */ 1886 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1887 if (sc->ti_copper) { 1888 /* 1889 * Copper cards allow manual 10/100 mode selection, 1890 * but not manual 1000baseT mode selection. Why? 1891 * Because currently there's no way to specify the 1892 * master/slave setting through the firmware interface, 1893 * so Alteon decided to just bag it and handle it 1894 * via autonegotiation. 1895 */ 1896 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1897 ifmedia_add(&sc->ifmedia, 1898 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1899 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1900 ifmedia_add(&sc->ifmedia, 1901 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1902 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 1903 ifmedia_add(&sc->ifmedia, 1904 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 1905 } else { 1906 /* Fiber cards don't support 10/100 modes. */ 1907 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1908 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1909 } 1910 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1911 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1912 1913 /* 1914 * Call MI attach routines. 1915 */ 1916 if_attach(ifp); 1917 ether_ifattach(ifp, eaddr); 1918 1919 return; 1920 fail2: 1921 pci_intr_disestablish(pc, sc->sc_ih); 1922 return; 1923 } 1924 1925 /* 1926 * Frame reception handling. This is called if there's a frame 1927 * on the receive return list. 1928 * 1929 * Note: we have to be able to handle three possibilities here: 1930 * 1) the frame is from the mini receive ring (can only happen) 1931 * on Tigon 2 boards) 1932 * 2) the frame is from the jumbo receive ring 1933 * 3) the frame is from the standard receive ring 1934 */ 1935 1936 static void ti_rxeof(sc) 1937 struct ti_softc *sc; 1938 { 1939 struct ifnet *ifp; 1940 struct ti_cmd_desc cmd; 1941 1942 ifp = &sc->ethercom.ec_if; 1943 1944 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1945 struct ti_rx_desc *cur_rx; 1946 u_int32_t rxidx; 1947 struct mbuf *m = NULL; 1948 u_int16_t vlan_tag = 0; 1949 int have_tag = 0; 1950 struct ether_header *eh; 1951 bus_dmamap_t dmamap; 1952 1953 cur_rx = 1954 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1955 rxidx = cur_rx->ti_idx; 1956 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1957 1958 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1959 have_tag = 1; 1960 /* ti_vlan_tag also has the priority, trim it */ 1961 vlan_tag = cur_rx->ti_vlan_tag & 4095; 1962 } 1963 1964 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1965 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1966 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1967 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1968 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1969 ifp->if_ierrors++; 1970 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1971 continue; 1972 } 1973 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1974 == ENOBUFS) { 1975 ifp->if_ierrors++; 1976 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1977 continue; 1978 } 1979 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1980 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1981 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1982 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1983 dmamap = sc->mini_dmamap[rxidx]; 1984 sc->mini_dmamap[rxidx] = 0; 1985 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1986 ifp->if_ierrors++; 1987 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1988 continue; 1989 } 1990 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1991 == ENOBUFS) { 1992 ifp->if_ierrors++; 1993 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1994 continue; 1995 } 1996 } else { 1997 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1998 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1999 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2000 dmamap = sc->std_dmamap[rxidx]; 2001 sc->std_dmamap[rxidx] = 0; 2002 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2003 ifp->if_ierrors++; 2004 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2005 continue; 2006 } 2007 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 2008 == ENOBUFS) { 2009 ifp->if_ierrors++; 2010 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2011 continue; 2012 } 2013 } 2014 2015 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 2016 ifp->if_ipackets++; 2017 m->m_pkthdr.rcvif = ifp; 2018 2019 #if NBPFILTER > 0 2020 /* 2021 * Handle BPF listeners. Let the BPF user see the packet, but 2022 * don't pass it up to the ether_input() layer unless it's 2023 * a broadcast packet, multicast packet, matches our ethernet 2024 * address or the interface is in promiscuous mode. 2025 */ 2026 if (ifp->if_bpf) 2027 bpf_mtap(ifp->if_bpf, m); 2028 #endif 2029 2030 eh = mtod(m, struct ether_header *); 2031 switch (ntohs(eh->ether_type)) { 2032 #ifdef INET 2033 case ETHERTYPE_IP: 2034 { 2035 struct ip *ip = (struct ip *) (eh + 1); 2036 2037 /* 2038 * Note the Tigon firmware does not invert 2039 * the checksum for us, hence the XOR. 2040 */ 2041 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2042 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 2043 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2044 /* 2045 * ntohs() the constant so the compiler can 2046 * optimize... 2047 * 2048 * XXX Figure out a sane way to deal with 2049 * fragmented packets. 2050 */ 2051 if ((ip->ip_off & htons(IP_MF|IP_OFFMASK)) == 0) { 2052 switch (ip->ip_p) { 2053 case IPPROTO_TCP: 2054 m->m_pkthdr.csum_data = 2055 cur_rx->ti_tcp_udp_cksum; 2056 m->m_pkthdr.csum_flags |= 2057 M_CSUM_TCPv4|M_CSUM_DATA; 2058 break; 2059 case IPPROTO_UDP: 2060 m->m_pkthdr.csum_data = 2061 cur_rx->ti_tcp_udp_cksum; 2062 m->m_pkthdr.csum_flags |= 2063 M_CSUM_UDPv4|M_CSUM_DATA; 2064 break; 2065 default: 2066 /* Nothing */; 2067 } 2068 } 2069 break; 2070 } 2071 #endif 2072 default: 2073 /* Nothing. */ 2074 break; 2075 } 2076 2077 if (have_tag) { 2078 struct m_tag *mtag; 2079 2080 mtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2081 M_NOWAIT); 2082 if (mtag) { 2083 *(u_int *)(mtag + 1) = vlan_tag; 2084 m_tag_prepend(m, mtag); 2085 have_tag = vlan_tag = 0; 2086 } else { 2087 printf("%s: no mbuf for tag\n", ifp->if_xname); 2088 m_freem(m); 2089 have_tag = vlan_tag = 0; 2090 continue; 2091 } 2092 } 2093 (*ifp->if_input)(ifp, m); 2094 } 2095 2096 /* Only necessary on the Tigon 1. */ 2097 if (sc->ti_hwrev == TI_HWREV_TIGON) 2098 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2099 sc->ti_rx_saved_considx); 2100 2101 TI_UPDATE_STDPROD(sc, sc->ti_std); 2102 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2103 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2104 2105 return; 2106 } 2107 2108 static void ti_txeof_tigon1(sc) 2109 struct ti_softc *sc; 2110 { 2111 struct ti_tx_desc *cur_tx = NULL; 2112 struct ifnet *ifp; 2113 struct txdmamap_pool_entry *dma; 2114 2115 ifp = &sc->ethercom.ec_if; 2116 2117 /* 2118 * Go through our tx ring and free mbufs for those 2119 * frames that have been sent. 2120 */ 2121 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2122 u_int32_t idx = 0; 2123 2124 idx = sc->ti_tx_saved_considx; 2125 if (idx > 383) 2126 CSR_WRITE_4(sc, TI_WINBASE, 2127 TI_TX_RING_BASE + 6144); 2128 else if (idx > 255) 2129 CSR_WRITE_4(sc, TI_WINBASE, 2130 TI_TX_RING_BASE + 4096); 2131 else if (idx > 127) 2132 CSR_WRITE_4(sc, TI_WINBASE, 2133 TI_TX_RING_BASE + 2048); 2134 else 2135 CSR_WRITE_4(sc, TI_WINBASE, 2136 TI_TX_RING_BASE); 2137 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2138 if (cur_tx->ti_flags & TI_BDFLAG_END) 2139 ifp->if_opackets++; 2140 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2141 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2142 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2143 2144 dma = sc->txdma[idx]; 2145 KDASSERT(dma != NULL); 2146 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2147 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2148 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2149 2150 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2151 sc->txdma[idx] = NULL; 2152 } 2153 sc->ti_txcnt--; 2154 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2155 ifp->if_timer = 0; 2156 } 2157 2158 if (cur_tx != NULL) 2159 ifp->if_flags &= ~IFF_OACTIVE; 2160 2161 return; 2162 } 2163 2164 static void ti_txeof_tigon2(sc) 2165 struct ti_softc *sc; 2166 { 2167 struct ti_tx_desc *cur_tx = NULL; 2168 struct ifnet *ifp; 2169 struct txdmamap_pool_entry *dma; 2170 int firstidx, cnt; 2171 2172 ifp = &sc->ethercom.ec_if; 2173 2174 /* 2175 * Go through our tx ring and free mbufs for those 2176 * frames that have been sent. 2177 */ 2178 firstidx = sc->ti_tx_saved_considx; 2179 cnt = 0; 2180 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2181 u_int32_t idx = 0; 2182 2183 idx = sc->ti_tx_saved_considx; 2184 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2185 if (cur_tx->ti_flags & TI_BDFLAG_END) 2186 ifp->if_opackets++; 2187 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2188 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2189 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2190 2191 dma = sc->txdma[idx]; 2192 KDASSERT(dma != NULL); 2193 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2194 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2195 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2196 2197 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2198 sc->txdma[idx] = NULL; 2199 } 2200 cnt++; 2201 sc->ti_txcnt--; 2202 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2203 ifp->if_timer = 0; 2204 } 2205 2206 if (cnt != 0) 2207 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2208 2209 if (cur_tx != NULL) 2210 ifp->if_flags &= ~IFF_OACTIVE; 2211 2212 return; 2213 } 2214 2215 static int ti_intr(xsc) 2216 void *xsc; 2217 { 2218 struct ti_softc *sc; 2219 struct ifnet *ifp; 2220 2221 sc = xsc; 2222 ifp = &sc->ethercom.ec_if; 2223 2224 #ifdef notdef 2225 /* Avoid this for now -- checking this register is expensive. */ 2226 /* Make sure this is really our interrupt. */ 2227 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2228 return (0); 2229 #endif 2230 2231 /* Ack interrupt and stop others from occuring. */ 2232 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2233 2234 if (ifp->if_flags & IFF_RUNNING) { 2235 /* Check RX return ring producer/consumer */ 2236 ti_rxeof(sc); 2237 2238 /* Check TX ring producer/consumer */ 2239 (*sc->sc_tx_eof)(sc); 2240 } 2241 2242 ti_handle_events(sc); 2243 2244 /* Re-enable interrupts. */ 2245 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2246 2247 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2248 IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2249 ti_start(ifp); 2250 2251 return (1); 2252 } 2253 2254 static void ti_stats_update(sc) 2255 struct ti_softc *sc; 2256 { 2257 struct ifnet *ifp; 2258 2259 ifp = &sc->ethercom.ec_if; 2260 2261 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2262 2263 ifp->if_collisions += 2264 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2265 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2266 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2267 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2268 ifp->if_collisions; 2269 2270 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2271 } 2272 2273 /* 2274 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2275 * pointers to descriptors. 2276 */ 2277 static int ti_encap_tigon1(sc, m_head, txidx) 2278 struct ti_softc *sc; 2279 struct mbuf *m_head; 2280 u_int32_t *txidx; 2281 { 2282 struct ti_tx_desc *f = NULL; 2283 u_int32_t frag, cur, cnt = 0; 2284 struct txdmamap_pool_entry *dma; 2285 bus_dmamap_t dmamap; 2286 int error, i; 2287 struct m_tag *mtag; 2288 u_int16_t csum_flags = 0; 2289 2290 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2291 if (dma == NULL) { 2292 return ENOMEM; 2293 } 2294 dmamap = dma->dmamap; 2295 2296 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2297 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2298 if (error) { 2299 struct mbuf *m; 2300 int i = 0; 2301 for (m = m_head; m; m = m->m_next) 2302 i++; 2303 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2304 "error %d\n", m_head->m_pkthdr.len, i, error); 2305 return (ENOMEM); 2306 } 2307 2308 cur = frag = *txidx; 2309 2310 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2311 /* IP header checksum field must be 0! */ 2312 csum_flags |= TI_BDFLAG_IP_CKSUM; 2313 } 2314 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2315 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2316 2317 /* XXX fragmented packet checksum capability? */ 2318 2319 /* 2320 * Start packing the mbufs in this chain into 2321 * the fragment pointers. Stop when we run out 2322 * of fragments or hit the end of the mbuf chain. 2323 */ 2324 for (i = 0; i < dmamap->dm_nsegs; i++) { 2325 if (frag > 383) 2326 CSR_WRITE_4(sc, TI_WINBASE, 2327 TI_TX_RING_BASE + 6144); 2328 else if (frag > 255) 2329 CSR_WRITE_4(sc, TI_WINBASE, 2330 TI_TX_RING_BASE + 4096); 2331 else if (frag > 127) 2332 CSR_WRITE_4(sc, TI_WINBASE, 2333 TI_TX_RING_BASE + 2048); 2334 else 2335 CSR_WRITE_4(sc, TI_WINBASE, 2336 TI_TX_RING_BASE); 2337 f = &sc->ti_tx_ring_nic[frag % 128]; 2338 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2339 break; 2340 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2341 f->ti_len = dmamap->dm_segs[i].ds_len; 2342 f->ti_flags = csum_flags; 2343 mtag = m_tag_find(m_head, PACKET_TAG_VLAN, NULL); 2344 if (mtag) { 2345 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2346 f->ti_vlan_tag = *(u_int *)(mtag + 1); 2347 } else { 2348 f->ti_vlan_tag = 0; 2349 } 2350 /* 2351 * Sanity check: avoid coming within 16 descriptors 2352 * of the end of the ring. 2353 */ 2354 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2355 return(ENOBUFS); 2356 cur = frag; 2357 TI_INC(frag, TI_TX_RING_CNT); 2358 cnt++; 2359 } 2360 2361 if (i < dmamap->dm_nsegs) 2362 return(ENOBUFS); 2363 2364 if (frag == sc->ti_tx_saved_considx) 2365 return(ENOBUFS); 2366 2367 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2368 TI_BDFLAG_END; 2369 2370 /* Sync the packet's DMA map. */ 2371 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2372 BUS_DMASYNC_PREWRITE); 2373 2374 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2375 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2376 sc->txdma[cur] = dma; 2377 sc->ti_txcnt += cnt; 2378 2379 *txidx = frag; 2380 2381 return(0); 2382 } 2383 2384 static int ti_encap_tigon2(sc, m_head, txidx) 2385 struct ti_softc *sc; 2386 struct mbuf *m_head; 2387 u_int32_t *txidx; 2388 { 2389 struct ti_tx_desc *f = NULL; 2390 u_int32_t frag, firstfrag, cur, cnt = 0; 2391 struct txdmamap_pool_entry *dma; 2392 bus_dmamap_t dmamap; 2393 int error, i; 2394 struct m_tag *mtag; 2395 u_int16_t csum_flags = 0; 2396 2397 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2398 if (dma == NULL) { 2399 return ENOMEM; 2400 } 2401 dmamap = dma->dmamap; 2402 2403 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2404 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2405 if (error) { 2406 struct mbuf *m; 2407 int i = 0; 2408 for (m = m_head; m; m = m->m_next) 2409 i++; 2410 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2411 "error %d\n", m_head->m_pkthdr.len, i, error); 2412 return (ENOMEM); 2413 } 2414 2415 cur = firstfrag = frag = *txidx; 2416 2417 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2418 /* IP header checksum field must be 0! */ 2419 csum_flags |= TI_BDFLAG_IP_CKSUM; 2420 } 2421 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2422 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2423 2424 /* XXX fragmented packet checksum capability? */ 2425 2426 /* 2427 * Start packing the mbufs in this chain into 2428 * the fragment pointers. Stop when we run out 2429 * of fragments or hit the end of the mbuf chain. 2430 */ 2431 for (i = 0; i < dmamap->dm_nsegs; i++) { 2432 f = &sc->ti_rdata->ti_tx_ring[frag]; 2433 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2434 break; 2435 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2436 f->ti_len = dmamap->dm_segs[i].ds_len; 2437 f->ti_flags = csum_flags; 2438 mtag = m_tag_find(m_head, PACKET_TAG_VLAN, NULL); 2439 if (mtag) { 2440 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2441 f->ti_vlan_tag = *(u_int *)(mtag + 1); 2442 } else { 2443 f->ti_vlan_tag = 0; 2444 } 2445 /* 2446 * Sanity check: avoid coming within 16 descriptors 2447 * of the end of the ring. 2448 */ 2449 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2450 return(ENOBUFS); 2451 cur = frag; 2452 TI_INC(frag, TI_TX_RING_CNT); 2453 cnt++; 2454 } 2455 2456 if (i < dmamap->dm_nsegs) 2457 return(ENOBUFS); 2458 2459 if (frag == sc->ti_tx_saved_considx) 2460 return(ENOBUFS); 2461 2462 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2463 2464 /* Sync the packet's DMA map. */ 2465 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2466 BUS_DMASYNC_PREWRITE); 2467 2468 /* Sync the descriptors we are using. */ 2469 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2470 2471 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2472 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2473 sc->txdma[cur] = dma; 2474 sc->ti_txcnt += cnt; 2475 2476 *txidx = frag; 2477 2478 return(0); 2479 } 2480 2481 /* 2482 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2483 * to the mbuf data regions directly in the transmit descriptors. 2484 */ 2485 static void ti_start(ifp) 2486 struct ifnet *ifp; 2487 { 2488 struct ti_softc *sc; 2489 struct mbuf *m_head = NULL; 2490 u_int32_t prodidx = 0; 2491 2492 sc = ifp->if_softc; 2493 2494 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2495 2496 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2497 IFQ_POLL(&ifp->if_snd, m_head); 2498 if (m_head == NULL) 2499 break; 2500 2501 /* 2502 * Pack the data into the transmit ring. If we 2503 * don't have room, set the OACTIVE flag and wait 2504 * for the NIC to drain the ring. 2505 */ 2506 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2507 ifp->if_flags |= IFF_OACTIVE; 2508 break; 2509 } 2510 2511 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2512 2513 /* 2514 * If there's a BPF listener, bounce a copy of this frame 2515 * to him. 2516 */ 2517 #if NBPFILTER > 0 2518 if (ifp->if_bpf) 2519 bpf_mtap(ifp->if_bpf, m_head); 2520 #endif 2521 } 2522 2523 /* Transmit */ 2524 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2525 2526 /* 2527 * Set a timeout in case the chip goes out to lunch. 2528 */ 2529 ifp->if_timer = 5; 2530 2531 return; 2532 } 2533 2534 static void ti_init(xsc) 2535 void *xsc; 2536 { 2537 struct ti_softc *sc = xsc; 2538 int s; 2539 2540 s = splnet(); 2541 2542 /* Cancel pending I/O and flush buffers. */ 2543 ti_stop(sc); 2544 2545 /* Init the gen info block, ring control blocks and firmware. */ 2546 if (ti_gibinit(sc)) { 2547 printf("%s: initialization failure\n", sc->sc_dev.dv_xname); 2548 splx(s); 2549 return; 2550 } 2551 2552 splx(s); 2553 2554 return; 2555 } 2556 2557 static void ti_init2(sc) 2558 struct ti_softc *sc; 2559 { 2560 struct ti_cmd_desc cmd; 2561 struct ifnet *ifp; 2562 u_int8_t *m; 2563 struct ifmedia *ifm; 2564 int tmp; 2565 2566 ifp = &sc->ethercom.ec_if; 2567 2568 /* Specify MTU and interface index. */ 2569 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->sc_dev.dv_unit); /* ??? */ 2570 2571 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2572 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2573 tmp += ETHER_VLAN_ENCAP_LEN; 2574 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2575 2576 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2577 2578 /* Load our MAC address. */ 2579 m = (u_int8_t *)LLADDR(ifp->if_sadl); 2580 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2581 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2582 | (m[4] << 8) | m[5]); 2583 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2584 2585 /* Enable or disable promiscuous mode as needed. */ 2586 if (ifp->if_flags & IFF_PROMISC) { 2587 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2588 } else { 2589 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2590 } 2591 2592 /* Program multicast filter. */ 2593 ti_setmulti(sc); 2594 2595 /* 2596 * If this is a Tigon 1, we should tell the 2597 * firmware to use software packet filtering. 2598 */ 2599 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2600 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2601 } 2602 2603 /* Init RX ring. */ 2604 ti_init_rx_ring_std(sc); 2605 2606 /* Init jumbo RX ring. */ 2607 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2608 ti_init_rx_ring_jumbo(sc); 2609 2610 /* 2611 * If this is a Tigon 2, we can also configure the 2612 * mini ring. 2613 */ 2614 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2615 ti_init_rx_ring_mini(sc); 2616 2617 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2618 sc->ti_rx_saved_considx = 0; 2619 2620 /* Init TX ring. */ 2621 ti_init_tx_ring(sc); 2622 2623 /* Tell firmware we're alive. */ 2624 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2625 2626 /* Enable host interrupts. */ 2627 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2628 2629 ifp->if_flags |= IFF_RUNNING; 2630 ifp->if_flags &= ~IFF_OACTIVE; 2631 2632 /* 2633 * Make sure to set media properly. We have to do this 2634 * here since we have to issue commands in order to set 2635 * the link negotiation and we can't issue commands until 2636 * the firmware is running. 2637 */ 2638 ifm = &sc->ifmedia; 2639 tmp = ifm->ifm_media; 2640 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2641 ti_ifmedia_upd(ifp); 2642 ifm->ifm_media = tmp; 2643 2644 return; 2645 } 2646 2647 /* 2648 * Set media options. 2649 */ 2650 static int ti_ifmedia_upd(ifp) 2651 struct ifnet *ifp; 2652 { 2653 struct ti_softc *sc; 2654 struct ifmedia *ifm; 2655 struct ti_cmd_desc cmd; 2656 2657 sc = ifp->if_softc; 2658 ifm = &sc->ifmedia; 2659 2660 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2661 return(EINVAL); 2662 2663 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2664 case IFM_AUTO: 2665 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2666 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2667 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2668 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2669 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2670 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2671 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2672 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2673 break; 2674 case IFM_1000_SX: 2675 case IFM_1000_T: 2676 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2677 CSR_WRITE_4(sc, TI_GCR_GLINK, 2678 TI_GLNK_PREF|TI_GLNK_1000MB|TI_GLNK_FULL_DUPLEX| 2679 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2680 } else { 2681 CSR_WRITE_4(sc, TI_GCR_GLINK, 2682 TI_GLNK_PREF|TI_GLNK_1000MB| 2683 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2684 } 2685 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2686 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2687 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2688 break; 2689 case IFM_100_FX: 2690 case IFM_10_FL: 2691 case IFM_100_TX: 2692 case IFM_10_T: 2693 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2694 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2695 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2696 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2697 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2698 } else { 2699 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2700 } 2701 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2702 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2703 } else { 2704 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2705 } 2706 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2707 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2708 break; 2709 } 2710 2711 sc->ethercom.ec_if.if_baudrate = 2712 ifmedia_baudrate(ifm->ifm_media); 2713 2714 return(0); 2715 } 2716 2717 /* 2718 * Report current media status. 2719 */ 2720 static void ti_ifmedia_sts(ifp, ifmr) 2721 struct ifnet *ifp; 2722 struct ifmediareq *ifmr; 2723 { 2724 struct ti_softc *sc; 2725 u_int32_t media = 0; 2726 2727 sc = ifp->if_softc; 2728 2729 ifmr->ifm_status = IFM_AVALID; 2730 ifmr->ifm_active = IFM_ETHER; 2731 2732 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2733 return; 2734 2735 ifmr->ifm_status |= IFM_ACTIVE; 2736 2737 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2738 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2739 if (sc->ti_copper) 2740 ifmr->ifm_active |= IFM_1000_T; 2741 else 2742 ifmr->ifm_active |= IFM_1000_SX; 2743 if (media & TI_GLNK_FULL_DUPLEX) 2744 ifmr->ifm_active |= IFM_FDX; 2745 else 2746 ifmr->ifm_active |= IFM_HDX; 2747 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2748 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2749 if (sc->ti_copper) { 2750 if (media & TI_LNK_100MB) 2751 ifmr->ifm_active |= IFM_100_TX; 2752 if (media & TI_LNK_10MB) 2753 ifmr->ifm_active |= IFM_10_T; 2754 } else { 2755 if (media & TI_LNK_100MB) 2756 ifmr->ifm_active |= IFM_100_FX; 2757 if (media & TI_LNK_10MB) 2758 ifmr->ifm_active |= IFM_10_FL; 2759 } 2760 if (media & TI_LNK_FULL_DUPLEX) 2761 ifmr->ifm_active |= IFM_FDX; 2762 if (media & TI_LNK_HALF_DUPLEX) 2763 ifmr->ifm_active |= IFM_HDX; 2764 } 2765 2766 sc->ethercom.ec_if.if_baudrate = 2767 ifmedia_baudrate(sc->ifmedia.ifm_media); 2768 2769 return; 2770 } 2771 2772 static int 2773 ti_ether_ioctl(ifp, cmd, data) 2774 struct ifnet *ifp; 2775 u_long cmd; 2776 caddr_t data; 2777 { 2778 struct ifaddr *ifa = (struct ifaddr *) data; 2779 struct ti_softc *sc = ifp->if_softc; 2780 2781 if ((ifp->if_flags & IFF_UP) == 0) { 2782 ifp->if_flags |= IFF_UP; 2783 ti_init(sc); 2784 } 2785 2786 switch (cmd) { 2787 case SIOCSIFADDR: 2788 2789 switch (ifa->ifa_addr->sa_family) { 2790 #ifdef INET 2791 case AF_INET: 2792 arp_ifinit(ifp, ifa); 2793 break; 2794 #endif 2795 #ifdef NS 2796 case AF_NS: 2797 { 2798 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 2799 2800 if (ns_nullhost(*ina)) 2801 ina->x_host = *(union ns_host *) 2802 LLADDR(ifp->if_sadl); 2803 else 2804 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 2805 ifp->if_addrlen); 2806 break; 2807 } 2808 #endif 2809 default: 2810 break; 2811 } 2812 break; 2813 2814 default: 2815 return (EINVAL); 2816 } 2817 2818 return (0); 2819 } 2820 2821 static int ti_ioctl(ifp, command, data) 2822 struct ifnet *ifp; 2823 u_long command; 2824 caddr_t data; 2825 { 2826 struct ti_softc *sc = ifp->if_softc; 2827 struct ifreq *ifr = (struct ifreq *) data; 2828 int s, error = 0; 2829 struct ti_cmd_desc cmd; 2830 2831 s = splnet(); 2832 2833 switch(command) { 2834 case SIOCSIFADDR: 2835 case SIOCGIFADDR: 2836 error = ti_ether_ioctl(ifp, command, data); 2837 break; 2838 case SIOCSIFMTU: 2839 if (ifr->ifr_mtu > ETHERMTU_JUMBO) 2840 error = EINVAL; 2841 else { 2842 ifp->if_mtu = ifr->ifr_mtu; 2843 ti_init(sc); 2844 } 2845 break; 2846 case SIOCSIFFLAGS: 2847 if (ifp->if_flags & IFF_UP) { 2848 /* 2849 * If only the state of the PROMISC flag changed, 2850 * then just use the 'set promisc mode' command 2851 * instead of reinitializing the entire NIC. Doing 2852 * a full re-init means reloading the firmware and 2853 * waiting for it to start up, which may take a 2854 * second or two. 2855 */ 2856 if (ifp->if_flags & IFF_RUNNING && 2857 ifp->if_flags & IFF_PROMISC && 2858 !(sc->ti_if_flags & IFF_PROMISC)) { 2859 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2860 TI_CMD_CODE_PROMISC_ENB, 0); 2861 } else if (ifp->if_flags & IFF_RUNNING && 2862 !(ifp->if_flags & IFF_PROMISC) && 2863 sc->ti_if_flags & IFF_PROMISC) { 2864 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2865 TI_CMD_CODE_PROMISC_DIS, 0); 2866 } else 2867 ti_init(sc); 2868 } else { 2869 if (ifp->if_flags & IFF_RUNNING) { 2870 ti_stop(sc); 2871 } 2872 } 2873 sc->ti_if_flags = ifp->if_flags; 2874 error = 0; 2875 break; 2876 case SIOCADDMULTI: 2877 case SIOCDELMULTI: 2878 error = (command == SIOCADDMULTI) ? 2879 ether_addmulti(ifr, &sc->ethercom) : 2880 ether_delmulti(ifr, &sc->ethercom); 2881 if (error == ENETRESET) { 2882 if (ifp->if_flags & IFF_RUNNING) 2883 ti_setmulti(sc); 2884 error = 0; 2885 } 2886 break; 2887 case SIOCSIFMEDIA: 2888 case SIOCGIFMEDIA: 2889 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2890 break; 2891 default: 2892 error = EINVAL; 2893 break; 2894 } 2895 2896 (void)splx(s); 2897 2898 return(error); 2899 } 2900 2901 static void ti_watchdog(ifp) 2902 struct ifnet *ifp; 2903 { 2904 struct ti_softc *sc; 2905 2906 sc = ifp->if_softc; 2907 2908 printf("%s: watchdog timeout -- resetting\n", sc->sc_dev.dv_xname); 2909 ti_stop(sc); 2910 ti_init(sc); 2911 2912 ifp->if_oerrors++; 2913 2914 return; 2915 } 2916 2917 /* 2918 * Stop the adapter and free any mbufs allocated to the 2919 * RX and TX lists. 2920 */ 2921 static void ti_stop(sc) 2922 struct ti_softc *sc; 2923 { 2924 struct ifnet *ifp; 2925 struct ti_cmd_desc cmd; 2926 2927 ifp = &sc->ethercom.ec_if; 2928 2929 /* Disable host interrupts. */ 2930 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2931 /* 2932 * Tell firmware we're shutting down. 2933 */ 2934 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2935 2936 /* Halt and reinitialize. */ 2937 ti_chipinit(sc); 2938 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2939 ti_chipinit(sc); 2940 2941 /* Free the RX lists. */ 2942 ti_free_rx_ring_std(sc); 2943 2944 /* Free jumbo RX list. */ 2945 ti_free_rx_ring_jumbo(sc); 2946 2947 /* Free mini RX list. */ 2948 ti_free_rx_ring_mini(sc); 2949 2950 /* Free TX buffers. */ 2951 ti_free_tx_ring(sc); 2952 2953 sc->ti_ev_prodidx.ti_idx = 0; 2954 sc->ti_return_prodidx.ti_idx = 0; 2955 sc->ti_tx_considx.ti_idx = 0; 2956 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2957 2958 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2959 2960 return; 2961 } 2962 2963 /* 2964 * Stop all chip I/O so that the kernel's probe routines don't 2965 * get confused by errant DMAs when rebooting. 2966 */ 2967 static void ti_shutdown(v) 2968 void *v; 2969 { 2970 struct ti_softc *sc = v; 2971 2972 ti_chipinit(sc); 2973 2974 return; 2975 } 2976
Indexes created Fri Sep 26 20:09:58 GMT 2025