if_ti.c revision 1.61
1 /* $NetBSD: if_ti.c,v 1.61 2004/07/27 07:59:51 he Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.61 2004/07/27 07:59:51 he Exp $"); 85 86 #include "bpfilter.h" 87 #include "opt_inet.h" 88 #include "opt_ns.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/queue.h> 98 #include <sys/device.h> 99 #include <sys/reboot.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #ifdef INET 114 #include <netinet/in.h> 115 #include <netinet/if_inarp.h> 116 #include <netinet/in_systm.h> 117 #include <netinet/ip.h> 118 #endif 119 120 #ifdef NS 121 #include <netns/ns.h> 122 #include <netns/ns_if.h> 123 #endif 124 125 #include <machine/bus.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/pcidevs.h> 130 131 #include <dev/pci/if_tireg.h> 132 133 #include <dev/microcode/tigon/ti_fw.h> 134 #include <dev/microcode/tigon/ti_fw2.h> 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 140 static const struct ti_type ti_devs[] = { 141 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 142 "Alteon AceNIC 1000BASE-SX Ethernet" }, 143 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 144 "Alteon AceNIC 1000BASE-T Ethernet" }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 146 "3Com 3c985-SX Gigabit Ethernet" }, 147 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 148 "Netgear GA620 1000BASE-SX Ethernet" }, 149 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 150 "Netgear GA620 1000BASE-T Ethernet" }, 151 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 152 "Silicon Graphics Gigabit Ethernet" }, 153 { 0, 0, NULL } 154 }; 155 156 static const struct ti_type *ti_type_match __P((struct pci_attach_args *)); 157 static int ti_probe __P((struct device *, struct cfdata *, void *)); 158 static void ti_attach __P((struct device *, struct device *, void *)); 159 static void ti_shutdown __P((void *)); 160 static void ti_txeof_tigon1 __P((struct ti_softc *)); 161 static void ti_txeof_tigon2 __P((struct ti_softc *)); 162 static void ti_rxeof __P((struct ti_softc *)); 163 164 static void ti_stats_update __P((struct ti_softc *)); 165 static int ti_encap_tigon1 __P((struct ti_softc *, struct mbuf *, 166 u_int32_t *)); 167 static int ti_encap_tigon2 __P((struct ti_softc *, struct mbuf *, 168 u_int32_t *)); 169 170 static int ti_intr __P((void *)); 171 static void ti_start __P((struct ifnet *)); 172 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 173 static void ti_init __P((void *)); 174 static void ti_init2 __P((struct ti_softc *)); 175 static void ti_stop __P((struct ti_softc *)); 176 static void ti_watchdog __P((struct ifnet *)); 177 static int ti_ifmedia_upd __P((struct ifnet *)); 178 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 179 180 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 181 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 182 int, u_int8_t *)); 183 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 184 185 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 186 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 187 static void ti_setmulti __P((struct ti_softc *)); 188 189 static void ti_mem __P((struct ti_softc *, u_int32_t, 190 u_int32_t, caddr_t)); 191 static void ti_loadfw __P((struct ti_softc *)); 192 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 193 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 194 caddr_t, int)); 195 static void ti_handle_events __P((struct ti_softc *)); 196 static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 197 static void *ti_jalloc __P((struct ti_softc *)); 198 static void ti_jfree __P((struct mbuf *, caddr_t, size_t, void *)); 199 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 200 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 201 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 202 static int ti_init_rx_ring_std __P((struct ti_softc *)); 203 static void ti_free_rx_ring_std __P((struct ti_softc *)); 204 static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 205 static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 206 static int ti_init_rx_ring_mini __P((struct ti_softc *)); 207 static void ti_free_rx_ring_mini __P((struct ti_softc *)); 208 static void ti_free_tx_ring __P((struct ti_softc *)); 209 static int ti_init_tx_ring __P((struct ti_softc *)); 210 211 static int ti_64bitslot_war __P((struct ti_softc *)); 212 static int ti_chipinit __P((struct ti_softc *)); 213 static int ti_gibinit __P((struct ti_softc *)); 214 215 static int ti_ether_ioctl __P((struct ifnet *, u_long, caddr_t)); 216 217 CFATTACH_DECL(ti, sizeof(struct ti_softc), 218 ti_probe, ti_attach, NULL, NULL); 219 220 /* 221 * Send an instruction or address to the EEPROM, check for ACK. 222 */ 223 static u_int32_t ti_eeprom_putbyte(sc, byte) 224 struct ti_softc *sc; 225 int byte; 226 { 227 int i, ack = 0; 228 229 /* 230 * Make sure we're in TX mode. 231 */ 232 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 233 234 /* 235 * Feed in each bit and stobe the clock. 236 */ 237 for (i = 0x80; i; i >>= 1) { 238 if (byte & i) { 239 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 240 } else { 241 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 242 } 243 DELAY(1); 244 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 245 DELAY(1); 246 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 247 } 248 249 /* 250 * Turn off TX mode. 251 */ 252 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 253 254 /* 255 * Check for ack. 256 */ 257 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 258 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 259 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 260 261 return(ack); 262 } 263 264 /* 265 * Read a byte of data stored in the EEPROM at address 'addr.' 266 * We have to send two address bytes since the EEPROM can hold 267 * more than 256 bytes of data. 268 */ 269 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 270 struct ti_softc *sc; 271 int addr; 272 u_int8_t *dest; 273 { 274 int i; 275 u_int8_t byte = 0; 276 277 EEPROM_START; 278 279 /* 280 * Send write control code to EEPROM. 281 */ 282 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 283 printf("%s: failed to send write command, status: %x\n", 284 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 285 return(1); 286 } 287 288 /* 289 * Send first byte of address of byte we want to read. 290 */ 291 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 292 printf("%s: failed to send address, status: %x\n", 293 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 294 return(1); 295 } 296 /* 297 * Send second byte address of byte we want to read. 298 */ 299 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 300 printf("%s: failed to send address, status: %x\n", 301 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 302 return(1); 303 } 304 305 EEPROM_STOP; 306 EEPROM_START; 307 /* 308 * Send read control code to EEPROM. 309 */ 310 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 311 printf("%s: failed to send read command, status: %x\n", 312 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 313 return(1); 314 } 315 316 /* 317 * Start reading bits from EEPROM. 318 */ 319 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 320 for (i = 0x80; i; i >>= 1) { 321 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 322 DELAY(1); 323 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 324 byte |= i; 325 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 326 DELAY(1); 327 } 328 329 EEPROM_STOP; 330 331 /* 332 * No ACK generated for read, so just return byte. 333 */ 334 335 *dest = byte; 336 337 return(0); 338 } 339 340 /* 341 * Read a sequence of bytes from the EEPROM. 342 */ 343 static int ti_read_eeprom(sc, dest, off, cnt) 344 struct ti_softc *sc; 345 caddr_t dest; 346 int off; 347 int cnt; 348 { 349 int err = 0, i; 350 u_int8_t byte = 0; 351 352 for (i = 0; i < cnt; i++) { 353 err = ti_eeprom_getbyte(sc, off + i, &byte); 354 if (err) 355 break; 356 *(dest + i) = byte; 357 } 358 359 return(err ? 1 : 0); 360 } 361 362 /* 363 * NIC memory access function. Can be used to either clear a section 364 * of NIC local memory or (if buf is non-NULL) copy data into it. 365 */ 366 static void ti_mem(sc, addr, len, buf) 367 struct ti_softc *sc; 368 u_int32_t addr, len; 369 caddr_t buf; 370 { 371 int segptr, segsize, cnt; 372 caddr_t ptr; 373 374 segptr = addr; 375 cnt = len; 376 ptr = buf; 377 378 while(cnt) { 379 if (cnt < TI_WINLEN) 380 segsize = cnt; 381 else 382 segsize = TI_WINLEN - (segptr % TI_WINLEN); 383 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 384 if (buf == NULL) { 385 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 386 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 387 segsize / 4); 388 } else { 389 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 390 bus_space_write_region_stream_4(sc->ti_btag, 391 sc->ti_bhandle, 392 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 393 (u_int32_t *)ptr, segsize / 4); 394 #else 395 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 396 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 397 (u_int32_t *)ptr, segsize / 4); 398 #endif 399 ptr += segsize; 400 } 401 segptr += segsize; 402 cnt -= segsize; 403 } 404 405 return; 406 } 407 408 /* 409 * Load firmware image into the NIC. Check that the firmware revision 410 * is acceptable and see if we want the firmware for the Tigon 1 or 411 * Tigon 2. 412 */ 413 static void ti_loadfw(sc) 414 struct ti_softc *sc; 415 { 416 switch(sc->ti_hwrev) { 417 case TI_HWREV_TIGON: 418 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 419 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 420 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 421 printf("%s: firmware revision mismatch; want " 422 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 423 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 424 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 425 tigonFwReleaseMinor, tigonFwReleaseFix); 426 return; 427 } 428 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 429 (caddr_t)tigonFwText); 430 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 431 (caddr_t)tigonFwData); 432 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 433 (caddr_t)tigonFwRodata); 434 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 435 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 436 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 437 break; 438 case TI_HWREV_TIGON_II: 439 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 440 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 441 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 442 printf("%s: firmware revision mismatch; want " 443 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 444 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 445 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 446 tigon2FwReleaseMinor, tigon2FwReleaseFix); 447 return; 448 } 449 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 450 (caddr_t)tigon2FwText); 451 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 452 (caddr_t)tigon2FwData); 453 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 454 (caddr_t)tigon2FwRodata); 455 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 456 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 457 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 458 break; 459 default: 460 printf("%s: can't load firmware: unknown hardware rev\n", 461 sc->sc_dev.dv_xname); 462 break; 463 } 464 465 return; 466 } 467 468 /* 469 * Send the NIC a command via the command ring. 470 */ 471 static void ti_cmd(sc, cmd) 472 struct ti_softc *sc; 473 struct ti_cmd_desc *cmd; 474 { 475 u_int32_t index; 476 477 index = sc->ti_cmd_saved_prodidx; 478 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 479 TI_INC(index, TI_CMD_RING_CNT); 480 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 481 sc->ti_cmd_saved_prodidx = index; 482 483 return; 484 } 485 486 /* 487 * Send the NIC an extended command. The 'len' parameter specifies the 488 * number of command slots to include after the initial command. 489 */ 490 static void ti_cmd_ext(sc, cmd, arg, len) 491 struct ti_softc *sc; 492 struct ti_cmd_desc *cmd; 493 caddr_t arg; 494 int len; 495 { 496 u_int32_t index; 497 int i; 498 499 index = sc->ti_cmd_saved_prodidx; 500 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 501 TI_INC(index, TI_CMD_RING_CNT); 502 for (i = 0; i < len; i++) { 503 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 504 *(u_int32_t *)(&arg[i * 4])); 505 TI_INC(index, TI_CMD_RING_CNT); 506 } 507 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 508 sc->ti_cmd_saved_prodidx = index; 509 510 return; 511 } 512 513 /* 514 * Handle events that have triggered interrupts. 515 */ 516 static void ti_handle_events(sc) 517 struct ti_softc *sc; 518 { 519 struct ti_event_desc *e; 520 521 if (sc->ti_rdata->ti_event_ring == NULL) 522 return; 523 524 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 525 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 526 switch(e->ti_event) { 527 case TI_EV_LINKSTAT_CHANGED: 528 sc->ti_linkstat = e->ti_code; 529 if (e->ti_code == TI_EV_CODE_LINK_UP) 530 printf("%s: 10/100 link up\n", 531 sc->sc_dev.dv_xname); 532 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 533 printf("%s: gigabit link up\n", 534 sc->sc_dev.dv_xname); 535 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 536 printf("%s: link down\n", 537 sc->sc_dev.dv_xname); 538 break; 539 case TI_EV_ERROR: 540 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 541 printf("%s: invalid command\n", 542 sc->sc_dev.dv_xname); 543 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 544 printf("%s: unknown command\n", 545 sc->sc_dev.dv_xname); 546 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 547 printf("%s: bad config data\n", 548 sc->sc_dev.dv_xname); 549 break; 550 case TI_EV_FIRMWARE_UP: 551 ti_init2(sc); 552 break; 553 case TI_EV_STATS_UPDATED: 554 ti_stats_update(sc); 555 break; 556 case TI_EV_RESET_JUMBO_RING: 557 case TI_EV_MCAST_UPDATED: 558 /* Who cares. */ 559 break; 560 default: 561 printf("%s: unknown event: %d\n", 562 sc->sc_dev.dv_xname, e->ti_event); 563 break; 564 } 565 /* Advance the consumer index. */ 566 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 567 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 568 } 569 570 return; 571 } 572 573 /* 574 * Memory management for the jumbo receive ring is a pain in the 575 * butt. We need to allocate at least 9018 bytes of space per frame, 576 * _and_ it has to be contiguous (unless you use the extended 577 * jumbo descriptor format). Using malloc() all the time won't 578 * work: malloc() allocates memory in powers of two, which means we 579 * would end up wasting a considerable amount of space by allocating 580 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 581 * to do our own memory management. 582 * 583 * The driver needs to allocate a contiguous chunk of memory at boot 584 * time. We then chop this up ourselves into 9K pieces and use them 585 * as external mbuf storage. 586 * 587 * One issue here is how much memory to allocate. The jumbo ring has 588 * 256 slots in it, but at 9K per slot than can consume over 2MB of 589 * RAM. This is a bit much, especially considering we also need 590 * RAM for the standard ring and mini ring (on the Tigon 2). To 591 * save space, we only actually allocate enough memory for 64 slots 592 * by default, which works out to between 500 and 600K. This can 593 * be tuned by changing a #define in if_tireg.h. 594 */ 595 596 static int ti_alloc_jumbo_mem(sc) 597 struct ti_softc *sc; 598 { 599 caddr_t ptr; 600 int i; 601 struct ti_jpool_entry *entry; 602 bus_dma_segment_t dmaseg; 603 int error, dmanseg; 604 605 /* Grab a big chunk o' storage. */ 606 if ((error = bus_dmamem_alloc(sc->sc_dmat, 607 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 608 BUS_DMA_NOWAIT)) != 0) { 609 printf("%s: can't allocate jumbo buffer, error = %d\n", 610 sc->sc_dev.dv_xname, error); 611 return (error); 612 } 613 614 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 615 TI_JMEM, (caddr_t *)&sc->ti_cdata.ti_jumbo_buf, 616 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 617 printf("%s: can't map jumbo buffer, error = %d\n", 618 sc->sc_dev.dv_xname, error); 619 return (error); 620 } 621 622 if ((error = bus_dmamap_create(sc->sc_dmat, 623 TI_JMEM, 1, 624 TI_JMEM, 0, BUS_DMA_NOWAIT, 625 &sc->jumbo_dmamap)) != 0) { 626 printf("%s: can't create jumbo buffer DMA map, error = %d\n", 627 sc->sc_dev.dv_xname, error); 628 return (error); 629 } 630 631 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 632 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 633 BUS_DMA_NOWAIT)) != 0) { 634 printf("%s: can't load jumbo buffer DMA map, error = %d\n", 635 sc->sc_dev.dv_xname, error); 636 return (error); 637 } 638 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 639 640 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 641 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 642 643 /* 644 * Now divide it up into 9K pieces and save the addresses 645 * in an array. 646 */ 647 ptr = sc->ti_cdata.ti_jumbo_buf; 648 for (i = 0; i < TI_JSLOTS; i++) { 649 sc->ti_cdata.ti_jslots[i] = ptr; 650 ptr += TI_JLEN; 651 entry = malloc(sizeof(struct ti_jpool_entry), 652 M_DEVBUF, M_NOWAIT); 653 if (entry == NULL) { 654 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 655 sc->ti_cdata.ti_jumbo_buf = NULL; 656 printf("%s: no memory for jumbo " 657 "buffer queue!\n", sc->sc_dev.dv_xname); 658 return(ENOBUFS); 659 } 660 entry->slot = i; 661 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 662 jpool_entries); 663 } 664 665 return(0); 666 } 667 668 /* 669 * Allocate a jumbo buffer. 670 */ 671 static void *ti_jalloc(sc) 672 struct ti_softc *sc; 673 { 674 struct ti_jpool_entry *entry; 675 676 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 677 678 if (entry == NULL) { 679 printf("%s: no free jumbo buffers\n", sc->sc_dev.dv_xname); 680 return(NULL); 681 } 682 683 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 684 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 685 return(sc->ti_cdata.ti_jslots[entry->slot]); 686 } 687 688 /* 689 * Release a jumbo buffer. 690 */ 691 static void ti_jfree(m, buf, size, arg) 692 struct mbuf *m; 693 caddr_t buf; 694 size_t size; 695 void *arg; 696 { 697 struct ti_softc *sc; 698 int i, s; 699 struct ti_jpool_entry *entry; 700 701 /* Extract the softc struct pointer. */ 702 sc = (struct ti_softc *)arg; 703 704 if (sc == NULL) 705 panic("ti_jfree: didn't get softc pointer!"); 706 707 /* calculate the slot this buffer belongs to */ 708 709 i = ((caddr_t)buf 710 - (caddr_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 711 712 if ((i < 0) || (i >= TI_JSLOTS)) 713 panic("ti_jfree: asked to free buffer that we don't manage!"); 714 715 s = splvm(); 716 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 717 if (entry == NULL) 718 panic("ti_jfree: buffer not in use!"); 719 entry->slot = i; 720 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 721 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 722 723 if (__predict_true(m != NULL)) 724 pool_cache_put(&mbpool_cache, m); 725 splx(s); 726 } 727 728 729 /* 730 * Intialize a standard receive ring descriptor. 731 */ 732 static int ti_newbuf_std(sc, i, m, dmamap) 733 struct ti_softc *sc; 734 int i; 735 struct mbuf *m; 736 bus_dmamap_t dmamap; /* required if (m != NULL) */ 737 { 738 struct mbuf *m_new = NULL; 739 struct ti_rx_desc *r; 740 int error; 741 742 if (dmamap == NULL) { 743 /* if (m) panic() */ 744 745 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 746 MCLBYTES, 0, BUS_DMA_NOWAIT, 747 &dmamap)) != 0) { 748 printf("%s: can't create recv map, error = %d\n", 749 sc->sc_dev.dv_xname, error); 750 return(ENOMEM); 751 } 752 } 753 sc->std_dmamap[i] = dmamap; 754 755 if (m == NULL) { 756 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 757 if (m_new == NULL) { 758 printf("%s: mbuf allocation failed " 759 "-- packet dropped!\n", sc->sc_dev.dv_xname); 760 return(ENOBUFS); 761 } 762 763 MCLGET(m_new, M_DONTWAIT); 764 if (!(m_new->m_flags & M_EXT)) { 765 printf("%s: cluster allocation failed " 766 "-- packet dropped!\n", sc->sc_dev.dv_xname); 767 m_freem(m_new); 768 return(ENOBUFS); 769 } 770 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 771 m_adj(m_new, ETHER_ALIGN); 772 773 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 774 mtod(m_new, caddr_t), m_new->m_len, NULL, 775 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 776 printf("%s: can't load recv map, error = %d\n", 777 sc->sc_dev.dv_xname, error); 778 return (ENOMEM); 779 } 780 } else { 781 m_new = m; 782 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 783 m_new->m_data = m_new->m_ext.ext_buf; 784 m_adj(m_new, ETHER_ALIGN); 785 786 /* reuse the dmamap */ 787 } 788 789 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 790 r = &sc->ti_rdata->ti_rx_std_ring[i]; 791 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 792 r->ti_type = TI_BDTYPE_RECV_BD; 793 r->ti_flags = 0; 794 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 795 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 796 if (sc->ethercom.ec_if.if_capenable & 797 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 798 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 799 r->ti_len = m_new->m_len; /* == ds_len */ 800 r->ti_idx = i; 801 802 return(0); 803 } 804 805 /* 806 * Intialize a mini receive ring descriptor. This only applies to 807 * the Tigon 2. 808 */ 809 static int ti_newbuf_mini(sc, i, m, dmamap) 810 struct ti_softc *sc; 811 int i; 812 struct mbuf *m; 813 bus_dmamap_t dmamap; /* required if (m != NULL) */ 814 { 815 struct mbuf *m_new = NULL; 816 struct ti_rx_desc *r; 817 int error; 818 819 if (dmamap == NULL) { 820 /* if (m) panic() */ 821 822 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 823 MHLEN, 0, BUS_DMA_NOWAIT, 824 &dmamap)) != 0) { 825 printf("%s: can't create recv map, error = %d\n", 826 sc->sc_dev.dv_xname, error); 827 return(ENOMEM); 828 } 829 } 830 sc->mini_dmamap[i] = dmamap; 831 832 if (m == NULL) { 833 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 834 if (m_new == NULL) { 835 printf("%s: mbuf allocation failed " 836 "-- packet dropped!\n", sc->sc_dev.dv_xname); 837 return(ENOBUFS); 838 } 839 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 840 m_adj(m_new, ETHER_ALIGN); 841 842 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 843 mtod(m_new, caddr_t), m_new->m_len, NULL, 844 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 845 printf("%s: can't load recv map, error = %d\n", 846 sc->sc_dev.dv_xname, error); 847 return (ENOMEM); 848 } 849 } else { 850 m_new = m; 851 m_new->m_data = m_new->m_pktdat; 852 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 853 m_adj(m_new, ETHER_ALIGN); 854 855 /* reuse the dmamap */ 856 } 857 858 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 859 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 860 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 861 r->ti_type = TI_BDTYPE_RECV_BD; 862 r->ti_flags = TI_BDFLAG_MINI_RING; 863 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 864 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 865 if (sc->ethercom.ec_if.if_capenable & 866 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 867 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 868 r->ti_len = m_new->m_len; /* == ds_len */ 869 r->ti_idx = i; 870 871 return(0); 872 } 873 874 /* 875 * Initialize a jumbo receive ring descriptor. This allocates 876 * a jumbo buffer from the pool managed internally by the driver. 877 */ 878 static int ti_newbuf_jumbo(sc, i, m) 879 struct ti_softc *sc; 880 int i; 881 struct mbuf *m; 882 { 883 struct mbuf *m_new = NULL; 884 struct ti_rx_desc *r; 885 886 if (m == NULL) { 887 caddr_t *buf = NULL; 888 889 /* Allocate the mbuf. */ 890 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 891 if (m_new == NULL) { 892 printf("%s: mbuf allocation failed " 893 "-- packet dropped!\n", sc->sc_dev.dv_xname); 894 return(ENOBUFS); 895 } 896 897 /* Allocate the jumbo buffer */ 898 buf = ti_jalloc(sc); 899 if (buf == NULL) { 900 m_freem(m_new); 901 printf("%s: jumbo allocation failed " 902 "-- packet dropped!\n", sc->sc_dev.dv_xname); 903 return(ENOBUFS); 904 } 905 906 /* Attach the buffer to the mbuf. */ 907 MEXTADD(m_new, (void *)buf, ETHER_MAX_LEN_JUMBO, 908 M_DEVBUF, ti_jfree, sc); 909 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 910 } else { 911 m_new = m; 912 m_new->m_data = m_new->m_ext.ext_buf; 913 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 914 } 915 916 m_adj(m_new, ETHER_ALIGN); 917 /* Set up the descriptor. */ 918 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 919 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 920 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 921 ((caddr_t)mtod(m_new, caddr_t) 922 - (caddr_t)sc->ti_cdata.ti_jumbo_buf); 923 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 924 r->ti_flags = TI_BDFLAG_JUMBO_RING; 925 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 926 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 927 if (sc->ethercom.ec_if.if_capenable & 928 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 929 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 930 r->ti_len = m_new->m_len; 931 r->ti_idx = i; 932 933 return(0); 934 } 935 936 /* 937 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 938 * that's 1MB or memory, which is a lot. For now, we fill only the first 939 * 256 ring entries and hope that our CPU is fast enough to keep up with 940 * the NIC. 941 */ 942 static int ti_init_rx_ring_std(sc) 943 struct ti_softc *sc; 944 { 945 int i; 946 struct ti_cmd_desc cmd; 947 948 for (i = 0; i < TI_SSLOTS; i++) { 949 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 950 return(ENOBUFS); 951 }; 952 953 TI_UPDATE_STDPROD(sc, i - 1); 954 sc->ti_std = i - 1; 955 956 return(0); 957 } 958 959 static void ti_free_rx_ring_std(sc) 960 struct ti_softc *sc; 961 { 962 int i; 963 964 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 965 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 966 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 967 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 968 969 /* if (sc->std_dmamap[i] == 0) panic() */ 970 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 971 sc->std_dmamap[i] = 0; 972 } 973 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 974 sizeof(struct ti_rx_desc)); 975 } 976 977 return; 978 } 979 980 static int ti_init_rx_ring_jumbo(sc) 981 struct ti_softc *sc; 982 { 983 int i; 984 struct ti_cmd_desc cmd; 985 986 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 987 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 988 return(ENOBUFS); 989 }; 990 991 TI_UPDATE_JUMBOPROD(sc, i - 1); 992 sc->ti_jumbo = i - 1; 993 994 return(0); 995 } 996 997 static void ti_free_rx_ring_jumbo(sc) 998 struct ti_softc *sc; 999 { 1000 int i; 1001 1002 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1003 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1004 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1005 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1006 } 1007 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 1008 sizeof(struct ti_rx_desc)); 1009 } 1010 1011 return; 1012 } 1013 1014 static int ti_init_rx_ring_mini(sc) 1015 struct ti_softc *sc; 1016 { 1017 int i; 1018 1019 for (i = 0; i < TI_MSLOTS; i++) { 1020 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 1021 return(ENOBUFS); 1022 }; 1023 1024 TI_UPDATE_MINIPROD(sc, i - 1); 1025 sc->ti_mini = i - 1; 1026 1027 return(0); 1028 } 1029 1030 static void ti_free_rx_ring_mini(sc) 1031 struct ti_softc *sc; 1032 { 1033 int i; 1034 1035 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1036 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1037 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1038 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1039 1040 /* if (sc->mini_dmamap[i] == 0) panic() */ 1041 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1042 sc->mini_dmamap[i] = 0; 1043 } 1044 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1045 sizeof(struct ti_rx_desc)); 1046 } 1047 1048 return; 1049 } 1050 1051 static void ti_free_tx_ring(sc) 1052 struct ti_softc *sc; 1053 { 1054 int i; 1055 struct txdmamap_pool_entry *dma; 1056 1057 if (sc->ti_rdata->ti_tx_ring == NULL) 1058 return; 1059 1060 for (i = 0; i < TI_TX_RING_CNT; i++) { 1061 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1062 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1063 sc->ti_cdata.ti_tx_chain[i] = NULL; 1064 1065 /* if (sc->txdma[i] == 0) panic() */ 1066 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1067 link); 1068 sc->txdma[i] = 0; 1069 } 1070 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1071 sizeof(struct ti_tx_desc)); 1072 } 1073 1074 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1075 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1076 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1077 free(dma, M_DEVBUF); 1078 } 1079 1080 return; 1081 } 1082 1083 static int ti_init_tx_ring(sc) 1084 struct ti_softc *sc; 1085 { 1086 int i, error; 1087 bus_dmamap_t dmamap; 1088 struct txdmamap_pool_entry *dma; 1089 1090 sc->ti_txcnt = 0; 1091 sc->ti_tx_saved_considx = 0; 1092 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1093 1094 SIMPLEQ_INIT(&sc->txdma_list); 1095 for (i = 0; i < TI_RSLOTS; i++) { 1096 /* I've seen mbufs with 30 fragments. */ 1097 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 1098 40, ETHER_MAX_LEN_JUMBO, 0, 1099 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1100 printf("%s: can't create tx map, error = %d\n", 1101 sc->sc_dev.dv_xname, error); 1102 return(ENOMEM); 1103 } 1104 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1105 if (!dma) { 1106 printf("%s: can't alloc txdmamap_pool_entry\n", 1107 sc->sc_dev.dv_xname); 1108 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1109 return (ENOMEM); 1110 } 1111 dma->dmamap = dmamap; 1112 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1113 } 1114 1115 return(0); 1116 } 1117 1118 /* 1119 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1120 * but we have to support the old way too so that Tigon 1 cards will 1121 * work. 1122 */ 1123 void ti_add_mcast(sc, addr) 1124 struct ti_softc *sc; 1125 struct ether_addr *addr; 1126 { 1127 struct ti_cmd_desc cmd; 1128 u_int16_t *m; 1129 u_int32_t ext[2] = {0, 0}; 1130 1131 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1132 1133 switch(sc->ti_hwrev) { 1134 case TI_HWREV_TIGON: 1135 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1136 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1137 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1138 break; 1139 case TI_HWREV_TIGON_II: 1140 ext[0] = htons(m[0]); 1141 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1142 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1143 break; 1144 default: 1145 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1146 break; 1147 } 1148 1149 return; 1150 } 1151 1152 void ti_del_mcast(sc, addr) 1153 struct ti_softc *sc; 1154 struct ether_addr *addr; 1155 { 1156 struct ti_cmd_desc cmd; 1157 u_int16_t *m; 1158 u_int32_t ext[2] = {0, 0}; 1159 1160 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1161 1162 switch(sc->ti_hwrev) { 1163 case TI_HWREV_TIGON: 1164 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1165 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1166 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1167 break; 1168 case TI_HWREV_TIGON_II: 1169 ext[0] = htons(m[0]); 1170 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1171 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1172 break; 1173 default: 1174 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1175 break; 1176 } 1177 1178 return; 1179 } 1180 1181 /* 1182 * Configure the Tigon's multicast address filter. 1183 * 1184 * The actual multicast table management is a bit of a pain, thanks to 1185 * slight brain damage on the part of both Alteon and us. With our 1186 * multicast code, we are only alerted when the multicast address table 1187 * changes and at that point we only have the current list of addresses: 1188 * we only know the current state, not the previous state, so we don't 1189 * actually know what addresses were removed or added. The firmware has 1190 * state, but we can't get our grubby mits on it, and there is no 'delete 1191 * all multicast addresses' command. Hence, we have to maintain our own 1192 * state so we know what addresses have been programmed into the NIC at 1193 * any given time. 1194 */ 1195 static void ti_setmulti(sc) 1196 struct ti_softc *sc; 1197 { 1198 struct ifnet *ifp; 1199 struct ti_cmd_desc cmd; 1200 struct ti_mc_entry *mc; 1201 u_int32_t intrs; 1202 struct ether_multi *enm; 1203 struct ether_multistep step; 1204 1205 ifp = &sc->ethercom.ec_if; 1206 1207 /* Disable interrupts. */ 1208 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1209 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1210 1211 /* First, zot all the existing filters. */ 1212 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1213 ti_del_mcast(sc, &mc->mc_addr); 1214 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1215 free(mc, M_DEVBUF); 1216 } 1217 1218 /* 1219 * Remember all multicast addresses so that we can delete them 1220 * later. Punt if there is a range of addresses or memory shortage. 1221 */ 1222 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1223 while (enm != NULL) { 1224 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1225 ETHER_ADDR_LEN) != 0) 1226 goto allmulti; 1227 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1228 M_NOWAIT)) == NULL) 1229 goto allmulti; 1230 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1231 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1232 ETHER_NEXT_MULTI(step, enm); 1233 } 1234 1235 /* Accept only programmed multicast addresses */ 1236 ifp->if_flags &= ~IFF_ALLMULTI; 1237 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1238 1239 /* Now program new ones. */ 1240 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1241 ti_add_mcast(sc, &mc->mc_addr); 1242 1243 /* Re-enable interrupts. */ 1244 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1245 1246 return; 1247 1248 allmulti: 1249 /* No need to keep individual multicast addresses */ 1250 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1251 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1252 free(mc, M_DEVBUF); 1253 } 1254 1255 /* Accept all multicast addresses */ 1256 ifp->if_flags |= IFF_ALLMULTI; 1257 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1258 1259 /* Re-enable interrupts. */ 1260 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1261 } 1262 1263 /* 1264 * Check to see if the BIOS has configured us for a 64 bit slot when 1265 * we aren't actually in one. If we detect this condition, we can work 1266 * around it on the Tigon 2 by setting a bit in the PCI state register, 1267 * but for the Tigon 1 we must give up and abort the interface attach. 1268 */ 1269 static int ti_64bitslot_war(sc) 1270 struct ti_softc *sc; 1271 { 1272 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1273 CSR_WRITE_4(sc, 0x600, 0); 1274 CSR_WRITE_4(sc, 0x604, 0); 1275 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1276 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1277 if (sc->ti_hwrev == TI_HWREV_TIGON) 1278 return(EINVAL); 1279 else { 1280 TI_SETBIT(sc, TI_PCI_STATE, 1281 TI_PCISTATE_32BIT_BUS); 1282 return(0); 1283 } 1284 } 1285 } 1286 1287 return(0); 1288 } 1289 1290 /* 1291 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1292 * self-test results. 1293 */ 1294 static int ti_chipinit(sc) 1295 struct ti_softc *sc; 1296 { 1297 u_int32_t cacheline; 1298 u_int32_t pci_writemax = 0; 1299 u_int32_t rev; 1300 1301 /* Initialize link to down state. */ 1302 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1303 1304 /* Set endianness before we access any non-PCI registers. */ 1305 #if BYTE_ORDER == BIG_ENDIAN 1306 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1307 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1308 #else 1309 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1310 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1311 #endif 1312 1313 /* Check the ROM failed bit to see if self-tests passed. */ 1314 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1315 printf("%s: board self-diagnostics failed!\n", 1316 sc->sc_dev.dv_xname); 1317 return(ENODEV); 1318 } 1319 1320 /* Halt the CPU. */ 1321 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1322 1323 /* Figure out the hardware revision. */ 1324 rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK; 1325 switch(rev) { 1326 case TI_REV_TIGON_I: 1327 sc->ti_hwrev = TI_HWREV_TIGON; 1328 break; 1329 case TI_REV_TIGON_II: 1330 sc->ti_hwrev = TI_HWREV_TIGON_II; 1331 break; 1332 default: 1333 printf("%s: unsupported chip revision 0x%x\n", 1334 sc->sc_dev.dv_xname, rev); 1335 return(ENODEV); 1336 } 1337 1338 /* Do special setup for Tigon 2. */ 1339 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1340 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1341 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1342 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1343 } 1344 1345 /* Set up the PCI state register. */ 1346 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1347 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1348 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1349 } 1350 1351 /* Clear the read/write max DMA parameters. */ 1352 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1353 TI_PCISTATE_READ_MAXDMA)); 1354 1355 /* Get cache line size. */ 1356 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1357 1358 /* 1359 * If the system has set enabled the PCI memory write 1360 * and invalidate command in the command register, set 1361 * the write max parameter accordingly. This is necessary 1362 * to use MWI with the Tigon 2. 1363 */ 1364 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1365 & PCI_COMMAND_INVALIDATE_ENABLE) { 1366 switch(cacheline) { 1367 case 1: 1368 case 4: 1369 case 8: 1370 case 16: 1371 case 32: 1372 case 64: 1373 break; 1374 default: 1375 /* Disable PCI memory write and invalidate. */ 1376 if (bootverbose) 1377 printf("%s: cache line size %d not " 1378 "supported; disabling PCI MWI\n", 1379 sc->sc_dev.dv_xname, cacheline); 1380 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1381 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1382 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1383 break; 1384 } 1385 } 1386 1387 #ifdef __brokenalpha__ 1388 /* 1389 * From the Alteon sample driver: 1390 * Must insure that we do not cross an 8K (bytes) boundary 1391 * for DMA reads. Our highest limit is 1K bytes. This is a 1392 * restriction on some ALPHA platforms with early revision 1393 * 21174 PCI chipsets, such as the AlphaPC 164lx 1394 */ 1395 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1396 #else 1397 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1398 #endif 1399 1400 /* This sets the min dma param all the way up (0xff). */ 1401 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1402 1403 /* Configure DMA variables. */ 1404 #if BYTE_ORDER == BIG_ENDIAN 1405 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1406 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1407 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1408 TI_OPMODE_DONT_FRAG_JUMBO); 1409 #else 1410 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1411 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1412 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1413 #endif 1414 1415 /* 1416 * Only allow 1 DMA channel to be active at a time. 1417 * I don't think this is a good idea, but without it 1418 * the firmware racks up lots of nicDmaReadRingFull 1419 * errors. 1420 * Incompatible with hardware assisted checksums. 1421 */ 1422 if ((sc->ethercom.ec_if.if_capenable & 1423 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4|IFCAP_CSUM_IPv4)) == 0) 1424 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1425 1426 /* Recommended settings from Tigon manual. */ 1427 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1428 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1429 1430 if (ti_64bitslot_war(sc)) { 1431 printf("%s: bios thinks we're in a 64 bit slot, " 1432 "but we aren't", sc->sc_dev.dv_xname); 1433 return(EINVAL); 1434 } 1435 1436 return(0); 1437 } 1438 1439 /* 1440 * Initialize the general information block and firmware, and 1441 * start the CPU(s) running. 1442 */ 1443 static int ti_gibinit(sc) 1444 struct ti_softc *sc; 1445 { 1446 struct ti_rcb *rcb; 1447 int i; 1448 struct ifnet *ifp; 1449 1450 ifp = &sc->ethercom.ec_if; 1451 1452 /* Disable interrupts for now. */ 1453 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1454 1455 /* Tell the chip where to find the general information block. */ 1456 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1457 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1458 1459 /* Load the firmware into SRAM. */ 1460 ti_loadfw(sc); 1461 1462 /* Set up the contents of the general info and ring control blocks. */ 1463 1464 /* Set up the event ring and producer pointer. */ 1465 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1466 1467 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1468 rcb->ti_flags = 0; 1469 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1470 TI_CDEVPRODADDR(sc); 1471 1472 sc->ti_ev_prodidx.ti_idx = 0; 1473 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1474 sc->ti_ev_saved_considx = 0; 1475 1476 /* Set up the command ring and producer mailbox. */ 1477 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1478 1479 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1480 rcb->ti_flags = 0; 1481 rcb->ti_max_len = 0; 1482 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1483 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1484 } 1485 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1486 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1487 sc->ti_cmd_saved_prodidx = 0; 1488 1489 /* 1490 * Assign the address of the stats refresh buffer. 1491 * We re-use the current stats buffer for this to 1492 * conserve memory. 1493 */ 1494 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1495 TI_CDSTATSADDR(sc); 1496 1497 /* Set up the standard receive ring. */ 1498 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1499 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1500 rcb->ti_max_len = ETHER_MAX_LEN; 1501 rcb->ti_flags = 0; 1502 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1503 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1504 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1505 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1506 if (sc->ethercom.ec_nvlans != 0) 1507 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1508 1509 /* Set up the jumbo receive ring. */ 1510 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1511 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1512 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1513 rcb->ti_flags = 0; 1514 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1515 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1516 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1517 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1518 if (sc->ethercom.ec_nvlans != 0) 1519 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1520 1521 /* 1522 * Set up the mini ring. Only activated on the 1523 * Tigon 2 but the slot in the config block is 1524 * still there on the Tigon 1. 1525 */ 1526 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1527 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1528 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1529 if (sc->ti_hwrev == TI_HWREV_TIGON) 1530 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1531 else 1532 rcb->ti_flags = 0; 1533 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1534 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1535 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1536 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1537 if (sc->ethercom.ec_nvlans != 0) 1538 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1539 1540 /* 1541 * Set up the receive return ring. 1542 */ 1543 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1544 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1545 rcb->ti_flags = 0; 1546 rcb->ti_max_len = TI_RETURN_RING_CNT; 1547 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1548 TI_CDRTNPRODADDR(sc); 1549 1550 /* 1551 * Set up the tx ring. Note: for the Tigon 2, we have the option 1552 * of putting the transmit ring in the host's address space and 1553 * letting the chip DMA it instead of leaving the ring in the NIC's 1554 * memory and accessing it through the shared memory region. We 1555 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1556 * so we have to revert to the shared memory scheme if we detect 1557 * a Tigon 1 chip. 1558 */ 1559 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1560 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1561 sc->ti_tx_ring_nic = 1562 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1563 } 1564 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1565 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1566 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1567 if (sc->ti_hwrev == TI_HWREV_TIGON) 1568 rcb->ti_flags = 0; 1569 else 1570 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1571 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1572 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1573 /* 1574 * When we get the packet, there is a pseudo-header seed already 1575 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1576 * compute the pseudo-header checksum again! 1577 */ 1578 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1579 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM| 1580 TI_RCB_FLAG_NO_PHDR_CKSUM; 1581 if (sc->ethercom.ec_nvlans != 0) 1582 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1583 rcb->ti_max_len = TI_TX_RING_CNT; 1584 if (sc->ti_hwrev == TI_HWREV_TIGON) 1585 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1586 else 1587 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1588 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1589 TI_CDTXCONSADDR(sc); 1590 1591 /* 1592 * We're done frobbing the General Information Block. Sync 1593 * it. Note we take care of the first stats sync here, as 1594 * well. 1595 */ 1596 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1597 1598 /* Set up tuneables */ 1599 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1600 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1601 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1602 (sc->ti_rx_coal_ticks / 10)); 1603 else 1604 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1605 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1606 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1607 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1608 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1609 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1610 1611 /* Turn interrupts on. */ 1612 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1613 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1614 1615 /* Start CPU. */ 1616 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1617 1618 return(0); 1619 } 1620 1621 /* 1622 * look for id in the device list, returning the first match 1623 */ 1624 static const struct ti_type * 1625 ti_type_match(pa) 1626 struct pci_attach_args *pa; 1627 { 1628 const struct ti_type *t; 1629 1630 t = ti_devs; 1631 while(t->ti_name != NULL) { 1632 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1633 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1634 return (t); 1635 } 1636 t++; 1637 } 1638 1639 return(NULL); 1640 } 1641 1642 /* 1643 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1644 * against our list and return its name if we find a match. 1645 */ 1646 static int ti_probe(parent, match, aux) 1647 struct device *parent; 1648 struct cfdata *match; 1649 void *aux; 1650 { 1651 struct pci_attach_args *pa = aux; 1652 const struct ti_type *t; 1653 1654 t = ti_type_match(pa); 1655 1656 return((t == NULL) ? 0 : 1); 1657 } 1658 1659 static void ti_attach(parent, self, aux) 1660 struct device *parent, *self; 1661 void *aux; 1662 { 1663 u_int32_t command; 1664 struct ifnet *ifp; 1665 struct ti_softc *sc; 1666 u_char eaddr[ETHER_ADDR_LEN]; 1667 struct pci_attach_args *pa = aux; 1668 pci_chipset_tag_t pc = pa->pa_pc; 1669 pci_intr_handle_t ih; 1670 const char *intrstr = NULL; 1671 bus_dma_segment_t dmaseg; 1672 int error, dmanseg, nolinear; 1673 const struct ti_type *t; 1674 1675 t = ti_type_match(pa); 1676 if (t == NULL) { 1677 printf("ti_attach: were did the card go ?\n"); 1678 return; 1679 } 1680 1681 printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class)); 1682 1683 sc = (struct ti_softc *)self; 1684 1685 /* 1686 * Map control/status registers. 1687 */ 1688 nolinear = 0; 1689 if (pci_mapreg_map(pa, 0x10, 1690 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1691 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1692 NULL, NULL)) { 1693 nolinear = 1; 1694 if (pci_mapreg_map(pa, 0x10, 1695 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1696 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1697 printf(": can't map memory space\n"); 1698 return; 1699 } 1700 } 1701 if (nolinear == 0) 1702 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1703 else 1704 sc->ti_vhandle = NULL; 1705 1706 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1707 command |= PCI_COMMAND_MASTER_ENABLE; 1708 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1709 1710 /* Allocate interrupt */ 1711 if (pci_intr_map(pa, &ih)) { 1712 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 1713 return; 1714 } 1715 intrstr = pci_intr_string(pc, ih); 1716 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1717 if (sc->sc_ih == NULL) { 1718 printf("%s: couldn't establish interrupt", 1719 sc->sc_dev.dv_xname); 1720 if (intrstr != NULL) 1721 printf(" at %s", intrstr); 1722 printf("\n"); 1723 return; 1724 } 1725 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1726 /* 1727 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1728 * doing do could allow DMA to corrupt kernel memory during the 1729 * reboot before the driver initializes. 1730 */ 1731 (void) shutdownhook_establish(ti_shutdown, sc); 1732 1733 if (ti_chipinit(sc)) { 1734 printf("%s: chip initialization failed\n", self->dv_xname); 1735 goto fail2; 1736 } 1737 1738 /* 1739 * Deal with some chip diffrences. 1740 */ 1741 switch (sc->ti_hwrev) { 1742 case TI_HWREV_TIGON: 1743 sc->sc_tx_encap = ti_encap_tigon1; 1744 sc->sc_tx_eof = ti_txeof_tigon1; 1745 if (nolinear == 1) 1746 printf("%s: memory space not mapped linear\n", 1747 self->dv_xname); 1748 break; 1749 1750 case TI_HWREV_TIGON_II: 1751 sc->sc_tx_encap = ti_encap_tigon2; 1752 sc->sc_tx_eof = ti_txeof_tigon2; 1753 break; 1754 1755 default: 1756 printf("%s: Unknown chip version: %d\n", self->dv_xname, 1757 sc->ti_hwrev); 1758 goto fail2; 1759 } 1760 1761 /* Zero out the NIC's on-board SRAM. */ 1762 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1763 1764 /* Init again -- zeroing memory may have clobbered some registers. */ 1765 if (ti_chipinit(sc)) { 1766 printf("%s: chip initialization failed\n", self->dv_xname); 1767 goto fail2; 1768 } 1769 1770 /* 1771 * Get station address from the EEPROM. Note: the manual states 1772 * that the MAC address is at offset 0x8c, however the data is 1773 * stored as two longwords (since that's how it's loaded into 1774 * the NIC). This means the MAC address is actually preceded 1775 * by two zero bytes. We need to skip over those. 1776 */ 1777 if (ti_read_eeprom(sc, (caddr_t)&eaddr, 1778 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1779 printf("%s: failed to read station address\n", self->dv_xname); 1780 goto fail2; 1781 } 1782 1783 /* 1784 * A Tigon chip was detected. Inform the world. 1785 */ 1786 printf("%s: Ethernet address: %s\n", self->dv_xname, 1787 ether_sprintf(eaddr)); 1788 1789 sc->sc_dmat = pa->pa_dmat; 1790 1791 /* Allocate the general information block and ring buffers. */ 1792 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1793 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1794 BUS_DMA_NOWAIT)) != 0) { 1795 printf("%s: can't allocate ring buffer, error = %d\n", 1796 sc->sc_dev.dv_xname, error); 1797 goto fail2; 1798 } 1799 1800 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1801 sizeof(struct ti_ring_data), (caddr_t *)&sc->ti_rdata, 1802 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1803 printf("%s: can't map ring buffer, error = %d\n", 1804 sc->sc_dev.dv_xname, error); 1805 goto fail2; 1806 } 1807 1808 if ((error = bus_dmamap_create(sc->sc_dmat, 1809 sizeof(struct ti_ring_data), 1, 1810 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1811 &sc->info_dmamap)) != 0) { 1812 printf("%s: can't create ring buffer DMA map, error = %d\n", 1813 sc->sc_dev.dv_xname, error); 1814 goto fail2; 1815 } 1816 1817 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1818 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1819 BUS_DMA_NOWAIT)) != 0) { 1820 printf("%s: can't load ring buffer DMA map, error = %d\n", 1821 sc->sc_dev.dv_xname, error); 1822 goto fail2; 1823 } 1824 1825 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1826 1827 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1828 1829 /* Try to allocate memory for jumbo buffers. */ 1830 if (ti_alloc_jumbo_mem(sc)) { 1831 printf("%s: jumbo buffer allocation failed\n", self->dv_xname); 1832 goto fail2; 1833 } 1834 1835 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1836 1837 /* 1838 * We really need a better way to tell a 1000baseT card 1839 * from a 1000baseSX one, since in theory there could be 1840 * OEMed 1000baseT cards from lame vendors who aren't 1841 * clever enough to change the PCI ID. For the moment 1842 * though, the AceNIC is the only copper card available. 1843 */ 1844 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1845 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1846 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1847 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1848 sc->ti_copper = 1; 1849 else 1850 sc->ti_copper = 0; 1851 1852 /* Set default tuneable values. */ 1853 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1854 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1855 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1856 sc->ti_rx_max_coal_bds = 64; 1857 sc->ti_tx_max_coal_bds = 128; 1858 sc->ti_tx_buf_ratio = 21; 1859 1860 /* Set up ifnet structure */ 1861 ifp = &sc->ethercom.ec_if; 1862 ifp->if_softc = sc; 1863 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1864 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1865 ifp->if_ioctl = ti_ioctl; 1866 ifp->if_start = ti_start; 1867 ifp->if_watchdog = ti_watchdog; 1868 IFQ_SET_READY(&ifp->if_snd); 1869 1870 #if 0 1871 /* 1872 * XXX This is not really correct -- we don't necessarily 1873 * XXX want to queue up as many as we can transmit at the 1874 * XXX upper layer like that. Someone with a board should 1875 * XXX check to see how this affects performance. 1876 */ 1877 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1878 #endif 1879 1880 /* 1881 * We can support 802.1Q VLAN-sized frames. 1882 */ 1883 sc->ethercom.ec_capabilities |= 1884 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1885 1886 /* 1887 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1888 */ 1889 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1890 IFCAP_CSUM_UDPv4; 1891 1892 /* Set up ifmedia support. */ 1893 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1894 if (sc->ti_copper) { 1895 /* 1896 * Copper cards allow manual 10/100 mode selection, 1897 * but not manual 1000baseT mode selection. Why? 1898 * Because currently there's no way to specify the 1899 * master/slave setting through the firmware interface, 1900 * so Alteon decided to just bag it and handle it 1901 * via autonegotiation. 1902 */ 1903 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1904 ifmedia_add(&sc->ifmedia, 1905 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1906 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1907 ifmedia_add(&sc->ifmedia, 1908 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1909 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 1910 ifmedia_add(&sc->ifmedia, 1911 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 1912 } else { 1913 /* Fiber cards don't support 10/100 modes. */ 1914 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1915 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1916 } 1917 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1918 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1919 1920 /* 1921 * Call MI attach routines. 1922 */ 1923 if_attach(ifp); 1924 ether_ifattach(ifp, eaddr); 1925 1926 return; 1927 fail2: 1928 pci_intr_disestablish(pc, sc->sc_ih); 1929 return; 1930 } 1931 1932 /* 1933 * Frame reception handling. This is called if there's a frame 1934 * on the receive return list. 1935 * 1936 * Note: we have to be able to handle three possibilities here: 1937 * 1) the frame is from the mini receive ring (can only happen) 1938 * on Tigon 2 boards) 1939 * 2) the frame is from the jumbo receive ring 1940 * 3) the frame is from the standard receive ring 1941 */ 1942 1943 static void ti_rxeof(sc) 1944 struct ti_softc *sc; 1945 { 1946 struct ifnet *ifp; 1947 struct ti_cmd_desc cmd; 1948 1949 ifp = &sc->ethercom.ec_if; 1950 1951 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1952 struct ti_rx_desc *cur_rx; 1953 u_int32_t rxidx; 1954 struct mbuf *m = NULL; 1955 u_int16_t vlan_tag = 0; 1956 int have_tag = 0; 1957 struct ether_header *eh; 1958 bus_dmamap_t dmamap; 1959 1960 cur_rx = 1961 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1962 rxidx = cur_rx->ti_idx; 1963 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1964 1965 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1966 have_tag = 1; 1967 /* ti_vlan_tag also has the priority, trim it */ 1968 vlan_tag = cur_rx->ti_vlan_tag & 4095; 1969 } 1970 1971 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1972 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1973 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1974 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1975 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1976 ifp->if_ierrors++; 1977 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1978 continue; 1979 } 1980 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1981 == ENOBUFS) { 1982 ifp->if_ierrors++; 1983 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1984 continue; 1985 } 1986 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1987 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1988 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1989 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1990 dmamap = sc->mini_dmamap[rxidx]; 1991 sc->mini_dmamap[rxidx] = 0; 1992 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1993 ifp->if_ierrors++; 1994 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1995 continue; 1996 } 1997 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1998 == ENOBUFS) { 1999 ifp->if_ierrors++; 2000 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 2001 continue; 2002 } 2003 } else { 2004 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2005 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2006 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2007 dmamap = sc->std_dmamap[rxidx]; 2008 sc->std_dmamap[rxidx] = 0; 2009 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2010 ifp->if_ierrors++; 2011 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2012 continue; 2013 } 2014 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 2015 == ENOBUFS) { 2016 ifp->if_ierrors++; 2017 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2018 continue; 2019 } 2020 } 2021 2022 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 2023 ifp->if_ipackets++; 2024 m->m_pkthdr.rcvif = ifp; 2025 2026 #if NBPFILTER > 0 2027 /* 2028 * Handle BPF listeners. Let the BPF user see the packet, but 2029 * don't pass it up to the ether_input() layer unless it's 2030 * a broadcast packet, multicast packet, matches our ethernet 2031 * address or the interface is in promiscuous mode. 2032 */ 2033 if (ifp->if_bpf) 2034 bpf_mtap(ifp->if_bpf, m); 2035 #endif 2036 2037 eh = mtod(m, struct ether_header *); 2038 switch (ntohs(eh->ether_type)) { 2039 #ifdef INET 2040 case ETHERTYPE_IP: 2041 { 2042 struct ip *ip = (struct ip *) (eh + 1); 2043 2044 /* 2045 * Note the Tigon firmware does not invert 2046 * the checksum for us, hence the XOR. 2047 */ 2048 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2049 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 2050 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2051 /* 2052 * ntohs() the constant so the compiler can 2053 * optimize... 2054 * 2055 * XXX Figure out a sane way to deal with 2056 * fragmented packets. 2057 */ 2058 if ((ip->ip_off & htons(IP_MF|IP_OFFMASK)) == 0) { 2059 switch (ip->ip_p) { 2060 case IPPROTO_TCP: 2061 m->m_pkthdr.csum_data = 2062 cur_rx->ti_tcp_udp_cksum; 2063 m->m_pkthdr.csum_flags |= 2064 M_CSUM_TCPv4|M_CSUM_DATA; 2065 break; 2066 case IPPROTO_UDP: 2067 m->m_pkthdr.csum_data = 2068 cur_rx->ti_tcp_udp_cksum; 2069 m->m_pkthdr.csum_flags |= 2070 M_CSUM_UDPv4|M_CSUM_DATA; 2071 break; 2072 default: 2073 /* Nothing */; 2074 } 2075 } 2076 break; 2077 } 2078 #endif 2079 default: 2080 /* Nothing. */ 2081 break; 2082 } 2083 2084 if (have_tag) { 2085 struct m_tag *mtag; 2086 2087 mtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2088 M_NOWAIT); 2089 if (mtag) { 2090 *(u_int *)(mtag + 1) = vlan_tag; 2091 m_tag_prepend(m, mtag); 2092 have_tag = vlan_tag = 0; 2093 } else { 2094 printf("%s: no mbuf for tag\n", ifp->if_xname); 2095 m_freem(m); 2096 have_tag = vlan_tag = 0; 2097 continue; 2098 } 2099 } 2100 (*ifp->if_input)(ifp, m); 2101 } 2102 2103 /* Only necessary on the Tigon 1. */ 2104 if (sc->ti_hwrev == TI_HWREV_TIGON) 2105 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2106 sc->ti_rx_saved_considx); 2107 2108 TI_UPDATE_STDPROD(sc, sc->ti_std); 2109 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2110 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2111 2112 return; 2113 } 2114 2115 static void ti_txeof_tigon1(sc) 2116 struct ti_softc *sc; 2117 { 2118 struct ti_tx_desc *cur_tx = NULL; 2119 struct ifnet *ifp; 2120 struct txdmamap_pool_entry *dma; 2121 2122 ifp = &sc->ethercom.ec_if; 2123 2124 /* 2125 * Go through our tx ring and free mbufs for those 2126 * frames that have been sent. 2127 */ 2128 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2129 u_int32_t idx = 0; 2130 2131 idx = sc->ti_tx_saved_considx; 2132 if (idx > 383) 2133 CSR_WRITE_4(sc, TI_WINBASE, 2134 TI_TX_RING_BASE + 6144); 2135 else if (idx > 255) 2136 CSR_WRITE_4(sc, TI_WINBASE, 2137 TI_TX_RING_BASE + 4096); 2138 else if (idx > 127) 2139 CSR_WRITE_4(sc, TI_WINBASE, 2140 TI_TX_RING_BASE + 2048); 2141 else 2142 CSR_WRITE_4(sc, TI_WINBASE, 2143 TI_TX_RING_BASE); 2144 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2145 if (cur_tx->ti_flags & TI_BDFLAG_END) 2146 ifp->if_opackets++; 2147 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2148 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2149 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2150 2151 dma = sc->txdma[idx]; 2152 KDASSERT(dma != NULL); 2153 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2154 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2155 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2156 2157 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2158 sc->txdma[idx] = NULL; 2159 } 2160 sc->ti_txcnt--; 2161 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2162 ifp->if_timer = 0; 2163 } 2164 2165 if (cur_tx != NULL) 2166 ifp->if_flags &= ~IFF_OACTIVE; 2167 2168 return; 2169 } 2170 2171 static void ti_txeof_tigon2(sc) 2172 struct ti_softc *sc; 2173 { 2174 struct ti_tx_desc *cur_tx = NULL; 2175 struct ifnet *ifp; 2176 struct txdmamap_pool_entry *dma; 2177 int firstidx, cnt; 2178 2179 ifp = &sc->ethercom.ec_if; 2180 2181 /* 2182 * Go through our tx ring and free mbufs for those 2183 * frames that have been sent. 2184 */ 2185 firstidx = sc->ti_tx_saved_considx; 2186 cnt = 0; 2187 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2188 u_int32_t idx = 0; 2189 2190 idx = sc->ti_tx_saved_considx; 2191 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2192 if (cur_tx->ti_flags & TI_BDFLAG_END) 2193 ifp->if_opackets++; 2194 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2195 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2196 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2197 2198 dma = sc->txdma[idx]; 2199 KDASSERT(dma != NULL); 2200 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2201 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2202 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2203 2204 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2205 sc->txdma[idx] = NULL; 2206 } 2207 cnt++; 2208 sc->ti_txcnt--; 2209 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2210 ifp->if_timer = 0; 2211 } 2212 2213 if (cnt != 0) 2214 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2215 2216 if (cur_tx != NULL) 2217 ifp->if_flags &= ~IFF_OACTIVE; 2218 2219 return; 2220 } 2221 2222 static int ti_intr(xsc) 2223 void *xsc; 2224 { 2225 struct ti_softc *sc; 2226 struct ifnet *ifp; 2227 2228 sc = xsc; 2229 ifp = &sc->ethercom.ec_if; 2230 2231 #ifdef notdef 2232 /* Avoid this for now -- checking this register is expensive. */ 2233 /* Make sure this is really our interrupt. */ 2234 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2235 return (0); 2236 #endif 2237 2238 /* Ack interrupt and stop others from occuring. */ 2239 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2240 2241 if (ifp->if_flags & IFF_RUNNING) { 2242 /* Check RX return ring producer/consumer */ 2243 ti_rxeof(sc); 2244 2245 /* Check TX ring producer/consumer */ 2246 (*sc->sc_tx_eof)(sc); 2247 } 2248 2249 ti_handle_events(sc); 2250 2251 /* Re-enable interrupts. */ 2252 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2253 2254 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2255 IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2256 ti_start(ifp); 2257 2258 return (1); 2259 } 2260 2261 static void ti_stats_update(sc) 2262 struct ti_softc *sc; 2263 { 2264 struct ifnet *ifp; 2265 2266 ifp = &sc->ethercom.ec_if; 2267 2268 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2269 2270 ifp->if_collisions += 2271 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2272 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2273 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2274 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2275 ifp->if_collisions; 2276 2277 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2278 } 2279 2280 /* 2281 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2282 * pointers to descriptors. 2283 */ 2284 static int ti_encap_tigon1(sc, m_head, txidx) 2285 struct ti_softc *sc; 2286 struct mbuf *m_head; 2287 u_int32_t *txidx; 2288 { 2289 struct ti_tx_desc *f = NULL; 2290 u_int32_t frag, cur, cnt = 0; 2291 struct txdmamap_pool_entry *dma; 2292 bus_dmamap_t dmamap; 2293 int error, i; 2294 struct m_tag *mtag; 2295 u_int16_t csum_flags = 0; 2296 2297 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2298 if (dma == NULL) { 2299 return ENOMEM; 2300 } 2301 dmamap = dma->dmamap; 2302 2303 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2304 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2305 if (error) { 2306 struct mbuf *m; 2307 int i = 0; 2308 for (m = m_head; m; m = m->m_next) 2309 i++; 2310 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2311 "error %d\n", m_head->m_pkthdr.len, i, error); 2312 return (ENOMEM); 2313 } 2314 2315 cur = frag = *txidx; 2316 2317 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2318 /* IP header checksum field must be 0! */ 2319 csum_flags |= TI_BDFLAG_IP_CKSUM; 2320 } 2321 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2322 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2323 2324 /* XXX fragmented packet checksum capability? */ 2325 2326 /* 2327 * Start packing the mbufs in this chain into 2328 * the fragment pointers. Stop when we run out 2329 * of fragments or hit the end of the mbuf chain. 2330 */ 2331 for (i = 0; i < dmamap->dm_nsegs; i++) { 2332 if (frag > 383) 2333 CSR_WRITE_4(sc, TI_WINBASE, 2334 TI_TX_RING_BASE + 6144); 2335 else if (frag > 255) 2336 CSR_WRITE_4(sc, TI_WINBASE, 2337 TI_TX_RING_BASE + 4096); 2338 else if (frag > 127) 2339 CSR_WRITE_4(sc, TI_WINBASE, 2340 TI_TX_RING_BASE + 2048); 2341 else 2342 CSR_WRITE_4(sc, TI_WINBASE, 2343 TI_TX_RING_BASE); 2344 f = &sc->ti_tx_ring_nic[frag % 128]; 2345 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2346 break; 2347 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2348 f->ti_len = dmamap->dm_segs[i].ds_len; 2349 f->ti_flags = csum_flags; 2350 mtag = m_tag_find(m_head, PACKET_TAG_VLAN, NULL); 2351 if (mtag) { 2352 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2353 f->ti_vlan_tag = *(u_int *)(mtag + 1); 2354 } else { 2355 f->ti_vlan_tag = 0; 2356 } 2357 /* 2358 * Sanity check: avoid coming within 16 descriptors 2359 * of the end of the ring. 2360 */ 2361 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2362 return(ENOBUFS); 2363 cur = frag; 2364 TI_INC(frag, TI_TX_RING_CNT); 2365 cnt++; 2366 } 2367 2368 if (i < dmamap->dm_nsegs) 2369 return(ENOBUFS); 2370 2371 if (frag == sc->ti_tx_saved_considx) 2372 return(ENOBUFS); 2373 2374 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2375 TI_BDFLAG_END; 2376 2377 /* Sync the packet's DMA map. */ 2378 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2379 BUS_DMASYNC_PREWRITE); 2380 2381 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2382 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2383 sc->txdma[cur] = dma; 2384 sc->ti_txcnt += cnt; 2385 2386 *txidx = frag; 2387 2388 return(0); 2389 } 2390 2391 static int ti_encap_tigon2(sc, m_head, txidx) 2392 struct ti_softc *sc; 2393 struct mbuf *m_head; 2394 u_int32_t *txidx; 2395 { 2396 struct ti_tx_desc *f = NULL; 2397 u_int32_t frag, firstfrag, cur, cnt = 0; 2398 struct txdmamap_pool_entry *dma; 2399 bus_dmamap_t dmamap; 2400 int error, i; 2401 struct m_tag *mtag; 2402 u_int16_t csum_flags = 0; 2403 2404 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2405 if (dma == NULL) { 2406 return ENOMEM; 2407 } 2408 dmamap = dma->dmamap; 2409 2410 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2411 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2412 if (error) { 2413 struct mbuf *m; 2414 int i = 0; 2415 for (m = m_head; m; m = m->m_next) 2416 i++; 2417 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2418 "error %d\n", m_head->m_pkthdr.len, i, error); 2419 return (ENOMEM); 2420 } 2421 2422 cur = firstfrag = frag = *txidx; 2423 2424 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2425 /* IP header checksum field must be 0! */ 2426 csum_flags |= TI_BDFLAG_IP_CKSUM; 2427 } 2428 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2429 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2430 2431 /* XXX fragmented packet checksum capability? */ 2432 2433 /* 2434 * Start packing the mbufs in this chain into 2435 * the fragment pointers. Stop when we run out 2436 * of fragments or hit the end of the mbuf chain. 2437 */ 2438 for (i = 0; i < dmamap->dm_nsegs; i++) { 2439 f = &sc->ti_rdata->ti_tx_ring[frag]; 2440 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2441 break; 2442 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2443 f->ti_len = dmamap->dm_segs[i].ds_len; 2444 f->ti_flags = csum_flags; 2445 mtag = m_tag_find(m_head, PACKET_TAG_VLAN, NULL); 2446 if (mtag) { 2447 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2448 f->ti_vlan_tag = *(u_int *)(mtag + 1); 2449 } else { 2450 f->ti_vlan_tag = 0; 2451 } 2452 /* 2453 * Sanity check: avoid coming within 16 descriptors 2454 * of the end of the ring. 2455 */ 2456 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2457 return(ENOBUFS); 2458 cur = frag; 2459 TI_INC(frag, TI_TX_RING_CNT); 2460 cnt++; 2461 } 2462 2463 if (i < dmamap->dm_nsegs) 2464 return(ENOBUFS); 2465 2466 if (frag == sc->ti_tx_saved_considx) 2467 return(ENOBUFS); 2468 2469 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2470 2471 /* Sync the packet's DMA map. */ 2472 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2473 BUS_DMASYNC_PREWRITE); 2474 2475 /* Sync the descriptors we are using. */ 2476 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2477 2478 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2479 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2480 sc->txdma[cur] = dma; 2481 sc->ti_txcnt += cnt; 2482 2483 *txidx = frag; 2484 2485 return(0); 2486 } 2487 2488 /* 2489 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2490 * to the mbuf data regions directly in the transmit descriptors. 2491 */ 2492 static void ti_start(ifp) 2493 struct ifnet *ifp; 2494 { 2495 struct ti_softc *sc; 2496 struct mbuf *m_head = NULL; 2497 u_int32_t prodidx = 0; 2498 2499 sc = ifp->if_softc; 2500 2501 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2502 2503 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2504 IFQ_POLL(&ifp->if_snd, m_head); 2505 if (m_head == NULL) 2506 break; 2507 2508 /* 2509 * Pack the data into the transmit ring. If we 2510 * don't have room, set the OACTIVE flag and wait 2511 * for the NIC to drain the ring. 2512 */ 2513 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2514 ifp->if_flags |= IFF_OACTIVE; 2515 break; 2516 } 2517 2518 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2519 2520 /* 2521 * If there's a BPF listener, bounce a copy of this frame 2522 * to him. 2523 */ 2524 #if NBPFILTER > 0 2525 if (ifp->if_bpf) 2526 bpf_mtap(ifp->if_bpf, m_head); 2527 #endif 2528 } 2529 2530 /* Transmit */ 2531 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2532 2533 /* 2534 * Set a timeout in case the chip goes out to lunch. 2535 */ 2536 ifp->if_timer = 5; 2537 2538 return; 2539 } 2540 2541 static void ti_init(xsc) 2542 void *xsc; 2543 { 2544 struct ti_softc *sc = xsc; 2545 int s; 2546 2547 s = splnet(); 2548 2549 /* Cancel pending I/O and flush buffers. */ 2550 ti_stop(sc); 2551 2552 /* Init the gen info block, ring control blocks and firmware. */ 2553 if (ti_gibinit(sc)) { 2554 printf("%s: initialization failure\n", sc->sc_dev.dv_xname); 2555 splx(s); 2556 return; 2557 } 2558 2559 splx(s); 2560 2561 return; 2562 } 2563 2564 static void ti_init2(sc) 2565 struct ti_softc *sc; 2566 { 2567 struct ti_cmd_desc cmd; 2568 struct ifnet *ifp; 2569 u_int8_t *m; 2570 struct ifmedia *ifm; 2571 int tmp; 2572 2573 ifp = &sc->ethercom.ec_if; 2574 2575 /* Specify MTU and interface index. */ 2576 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->sc_dev.dv_unit); /* ??? */ 2577 2578 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2579 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2580 tmp += ETHER_VLAN_ENCAP_LEN; 2581 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2582 2583 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2584 2585 /* Load our MAC address. */ 2586 m = (u_int8_t *)LLADDR(ifp->if_sadl); 2587 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2588 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2589 | (m[4] << 8) | m[5]); 2590 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2591 2592 /* Enable or disable promiscuous mode as needed. */ 2593 if (ifp->if_flags & IFF_PROMISC) { 2594 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2595 } else { 2596 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2597 } 2598 2599 /* Program multicast filter. */ 2600 ti_setmulti(sc); 2601 2602 /* 2603 * If this is a Tigon 1, we should tell the 2604 * firmware to use software packet filtering. 2605 */ 2606 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2607 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2608 } 2609 2610 /* Init RX ring. */ 2611 ti_init_rx_ring_std(sc); 2612 2613 /* Init jumbo RX ring. */ 2614 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2615 ti_init_rx_ring_jumbo(sc); 2616 2617 /* 2618 * If this is a Tigon 2, we can also configure the 2619 * mini ring. 2620 */ 2621 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2622 ti_init_rx_ring_mini(sc); 2623 2624 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2625 sc->ti_rx_saved_considx = 0; 2626 2627 /* Init TX ring. */ 2628 ti_init_tx_ring(sc); 2629 2630 /* Tell firmware we're alive. */ 2631 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2632 2633 /* Enable host interrupts. */ 2634 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2635 2636 ifp->if_flags |= IFF_RUNNING; 2637 ifp->if_flags &= ~IFF_OACTIVE; 2638 2639 /* 2640 * Make sure to set media properly. We have to do this 2641 * here since we have to issue commands in order to set 2642 * the link negotiation and we can't issue commands until 2643 * the firmware is running. 2644 */ 2645 ifm = &sc->ifmedia; 2646 tmp = ifm->ifm_media; 2647 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2648 ti_ifmedia_upd(ifp); 2649 ifm->ifm_media = tmp; 2650 2651 return; 2652 } 2653 2654 /* 2655 * Set media options. 2656 */ 2657 static int ti_ifmedia_upd(ifp) 2658 struct ifnet *ifp; 2659 { 2660 struct ti_softc *sc; 2661 struct ifmedia *ifm; 2662 struct ti_cmd_desc cmd; 2663 2664 sc = ifp->if_softc; 2665 ifm = &sc->ifmedia; 2666 2667 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2668 return(EINVAL); 2669 2670 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2671 case IFM_AUTO: 2672 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2673 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2674 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2675 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2676 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2677 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2678 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2679 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2680 break; 2681 case IFM_1000_SX: 2682 case IFM_1000_T: 2683 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2684 CSR_WRITE_4(sc, TI_GCR_GLINK, 2685 TI_GLNK_PREF|TI_GLNK_1000MB|TI_GLNK_FULL_DUPLEX| 2686 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2687 } else { 2688 CSR_WRITE_4(sc, TI_GCR_GLINK, 2689 TI_GLNK_PREF|TI_GLNK_1000MB| 2690 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2691 } 2692 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2693 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2694 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2695 break; 2696 case IFM_100_FX: 2697 case IFM_10_FL: 2698 case IFM_100_TX: 2699 case IFM_10_T: 2700 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2701 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2702 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2703 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2704 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2705 } else { 2706 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2707 } 2708 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2709 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2710 } else { 2711 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2712 } 2713 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2714 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2715 break; 2716 } 2717 2718 sc->ethercom.ec_if.if_baudrate = 2719 ifmedia_baudrate(ifm->ifm_media); 2720 2721 return(0); 2722 } 2723 2724 /* 2725 * Report current media status. 2726 */ 2727 static void ti_ifmedia_sts(ifp, ifmr) 2728 struct ifnet *ifp; 2729 struct ifmediareq *ifmr; 2730 { 2731 struct ti_softc *sc; 2732 u_int32_t media = 0; 2733 2734 sc = ifp->if_softc; 2735 2736 ifmr->ifm_status = IFM_AVALID; 2737 ifmr->ifm_active = IFM_ETHER; 2738 2739 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2740 return; 2741 2742 ifmr->ifm_status |= IFM_ACTIVE; 2743 2744 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2745 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2746 if (sc->ti_copper) 2747 ifmr->ifm_active |= IFM_1000_T; 2748 else 2749 ifmr->ifm_active |= IFM_1000_SX; 2750 if (media & TI_GLNK_FULL_DUPLEX) 2751 ifmr->ifm_active |= IFM_FDX; 2752 else 2753 ifmr->ifm_active |= IFM_HDX; 2754 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2755 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2756 if (sc->ti_copper) { 2757 if (media & TI_LNK_100MB) 2758 ifmr->ifm_active |= IFM_100_TX; 2759 if (media & TI_LNK_10MB) 2760 ifmr->ifm_active |= IFM_10_T; 2761 } else { 2762 if (media & TI_LNK_100MB) 2763 ifmr->ifm_active |= IFM_100_FX; 2764 if (media & TI_LNK_10MB) 2765 ifmr->ifm_active |= IFM_10_FL; 2766 } 2767 if (media & TI_LNK_FULL_DUPLEX) 2768 ifmr->ifm_active |= IFM_FDX; 2769 if (media & TI_LNK_HALF_DUPLEX) 2770 ifmr->ifm_active |= IFM_HDX; 2771 } 2772 2773 sc->ethercom.ec_if.if_baudrate = 2774 ifmedia_baudrate(sc->ifmedia.ifm_media); 2775 2776 return; 2777 } 2778 2779 static int 2780 ti_ether_ioctl(ifp, cmd, data) 2781 struct ifnet *ifp; 2782 u_long cmd; 2783 caddr_t data; 2784 { 2785 struct ifaddr *ifa = (struct ifaddr *) data; 2786 struct ti_softc *sc = ifp->if_softc; 2787 2788 if ((ifp->if_flags & IFF_UP) == 0) { 2789 ifp->if_flags |= IFF_UP; 2790 ti_init(sc); 2791 } 2792 2793 switch (cmd) { 2794 case SIOCSIFADDR: 2795 2796 switch (ifa->ifa_addr->sa_family) { 2797 #ifdef INET 2798 case AF_INET: 2799 arp_ifinit(ifp, ifa); 2800 break; 2801 #endif 2802 #ifdef NS 2803 case AF_NS: 2804 { 2805 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 2806 2807 if (ns_nullhost(*ina)) 2808 ina->x_host = *(union ns_host *) 2809 LLADDR(ifp->if_sadl); 2810 else 2811 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 2812 ifp->if_addrlen); 2813 break; 2814 } 2815 #endif 2816 default: 2817 break; 2818 } 2819 break; 2820 2821 default: 2822 return (EINVAL); 2823 } 2824 2825 return (0); 2826 } 2827 2828 static int ti_ioctl(ifp, command, data) 2829 struct ifnet *ifp; 2830 u_long command; 2831 caddr_t data; 2832 { 2833 struct ti_softc *sc = ifp->if_softc; 2834 struct ifreq *ifr = (struct ifreq *) data; 2835 int s, error = 0; 2836 struct ti_cmd_desc cmd; 2837 2838 s = splnet(); 2839 2840 switch(command) { 2841 case SIOCSIFADDR: 2842 case SIOCGIFADDR: 2843 error = ti_ether_ioctl(ifp, command, data); 2844 break; 2845 case SIOCSIFMTU: 2846 if (ifr->ifr_mtu > ETHERMTU_JUMBO) 2847 error = EINVAL; 2848 else { 2849 ifp->if_mtu = ifr->ifr_mtu; 2850 ti_init(sc); 2851 } 2852 break; 2853 case SIOCSIFFLAGS: 2854 if (ifp->if_flags & IFF_UP) { 2855 /* 2856 * If only the state of the PROMISC flag changed, 2857 * then just use the 'set promisc mode' command 2858 * instead of reinitializing the entire NIC. Doing 2859 * a full re-init means reloading the firmware and 2860 * waiting for it to start up, which may take a 2861 * second or two. 2862 */ 2863 if (ifp->if_flags & IFF_RUNNING && 2864 ifp->if_flags & IFF_PROMISC && 2865 !(sc->ti_if_flags & IFF_PROMISC)) { 2866 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2867 TI_CMD_CODE_PROMISC_ENB, 0); 2868 } else if (ifp->if_flags & IFF_RUNNING && 2869 !(ifp->if_flags & IFF_PROMISC) && 2870 sc->ti_if_flags & IFF_PROMISC) { 2871 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2872 TI_CMD_CODE_PROMISC_DIS, 0); 2873 } else 2874 ti_init(sc); 2875 } else { 2876 if (ifp->if_flags & IFF_RUNNING) { 2877 ti_stop(sc); 2878 } 2879 } 2880 sc->ti_if_flags = ifp->if_flags; 2881 error = 0; 2882 break; 2883 case SIOCADDMULTI: 2884 case SIOCDELMULTI: 2885 error = (command == SIOCADDMULTI) ? 2886 ether_addmulti(ifr, &sc->ethercom) : 2887 ether_delmulti(ifr, &sc->ethercom); 2888 if (error == ENETRESET) { 2889 if (ifp->if_flags & IFF_RUNNING) 2890 ti_setmulti(sc); 2891 error = 0; 2892 } 2893 break; 2894 case SIOCSIFMEDIA: 2895 case SIOCGIFMEDIA: 2896 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2897 break; 2898 default: 2899 error = EINVAL; 2900 break; 2901 } 2902 2903 (void)splx(s); 2904 2905 return(error); 2906 } 2907 2908 static void ti_watchdog(ifp) 2909 struct ifnet *ifp; 2910 { 2911 struct ti_softc *sc; 2912 2913 sc = ifp->if_softc; 2914 2915 printf("%s: watchdog timeout -- resetting\n", sc->sc_dev.dv_xname); 2916 ti_stop(sc); 2917 ti_init(sc); 2918 2919 ifp->if_oerrors++; 2920 2921 return; 2922 } 2923 2924 /* 2925 * Stop the adapter and free any mbufs allocated to the 2926 * RX and TX lists. 2927 */ 2928 static void ti_stop(sc) 2929 struct ti_softc *sc; 2930 { 2931 struct ifnet *ifp; 2932 struct ti_cmd_desc cmd; 2933 2934 ifp = &sc->ethercom.ec_if; 2935 2936 /* Disable host interrupts. */ 2937 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2938 /* 2939 * Tell firmware we're shutting down. 2940 */ 2941 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2942 2943 /* Halt and reinitialize. */ 2944 ti_chipinit(sc); 2945 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2946 ti_chipinit(sc); 2947 2948 /* Free the RX lists. */ 2949 ti_free_rx_ring_std(sc); 2950 2951 /* Free jumbo RX list. */ 2952 ti_free_rx_ring_jumbo(sc); 2953 2954 /* Free mini RX list. */ 2955 ti_free_rx_ring_mini(sc); 2956 2957 /* Free TX buffers. */ 2958 ti_free_tx_ring(sc); 2959 2960 sc->ti_ev_prodidx.ti_idx = 0; 2961 sc->ti_return_prodidx.ti_idx = 0; 2962 sc->ti_tx_considx.ti_idx = 0; 2963 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2964 2965 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2966 2967 return; 2968 } 2969 2970 /* 2971 * Stop all chip I/O so that the kernel's probe routines don't 2972 * get confused by errant DMAs when rebooting. 2973 */ 2974 static void ti_shutdown(v) 2975 void *v; 2976 { 2977 struct ti_softc *sc = v; 2978 2979 ti_chipinit(sc); 2980 2981 return; 2982 } 2983
Indexes created Fri Sep 26 20:09:58 GMT 2025